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r23970 Thursday 27th June, 2013 at 07:00:22 UTC by Barry Rodewald
whitestar: Hooked up Deco Type 2 DMD.
[src/mame/drivers]whitestar.c

trunk/src/mame/drivers/whitestar.c
r23969r23970
66#include "emu.h"
77#include "video/mc6845.h"
88#include "audio/decobsmt.h"
9#include "video/decodmd2.h"
910#include "rendlay.h"
1011
1112class whitestar_state : public driver_device
r23969r23970
1415   whitestar_state(const machine_config &mconfig, device_type type, const char *tag)
1516      : driver_device(mconfig, type, tag),
1617      m_maincpu(*this, "maincpu"),
17      m_dmdcpu(*this, "dmdcpu"),
18      m_mc6845(*this, "mc6845"),
1918      m_decobsmt(*this, "decobsmt"),
20      m_vram(*this, "vram"){ }
19      m_decodmd(*this, "decodmd")
20   { }
2121
2222   required_device<cpu_device> m_maincpu;
23   required_device<cpu_device> m_dmdcpu;
24   required_device<mc6845_device> m_mc6845;
23   //required_device<cpu_device> m_dmdcpu;
24   //required_device<mc6845_device> m_mc6845;
2525   required_device<decobsmt_device> m_decobsmt;
26   required_device<decodmd_type2_device> m_decodmd;
2627
2728   UINT8 m_dmd_latch;
2829   UINT8 m_dmd_ctrl;
2930   UINT8 m_dmd_status;
3031   UINT8 m_dmd_busy;
3132
32   required_shared_ptr<UINT8> m_vram;
33
3433   DECLARE_WRITE8_MEMBER(dmd_latch_w);
3534   DECLARE_READ8_MEMBER(dmd_latch_r);
3635   DECLARE_WRITE8_MEMBER(dmd_ctrl_w);
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4039
4140   DECLARE_WRITE8_MEMBER(bank_w);
4241   DECLARE_WRITE8_MEMBER(dmd_bank_w);
42   DECLARE_WRITE8_MEMBER(dmddata_w);
4343
4444   DECLARE_READ8_MEMBER(dips_r);
4545   DECLARE_READ8_MEMBER(switch_r);
r23969r23970
4747   DECLARE_READ8_MEMBER(dedicated_switch_r);
4848   DECLARE_DRIVER_INIT(whitestar);
4949   virtual void machine_reset();
50   virtual void palette_init();
5150   INTERRUPT_GEN_MEMBER(whitestar_firq_interrupt);
5251};
5352
r23969r23970
8281   AM_RANGE(0x3200, 0x3200) AM_WRITE(bank_w)
8382   AM_RANGE(0x3300, 0x3300) AM_WRITE(switch_w)
8483   AM_RANGE(0x3400, 0x3400) AM_READ(switch_r)
85   AM_RANGE(0x3600, 0x3600) AM_WRITE(dmd_latch_w)
86   AM_RANGE(0x3601, 0x3601) AM_READWRITE(dmd_ctrl_r, dmd_ctrl_w)
87   AM_RANGE(0x3700, 0x3700) AM_READ(dmd_status_r)
84   AM_RANGE(0x3600, 0x3600) AM_WRITE(dmddata_w)
85   AM_RANGE(0x3601, 0x3601) AM_DEVREADWRITE("decodmd",decodmd_type2_device,ctrl_r, ctrl_w)
86   AM_RANGE(0x3700, 0x3700) AM_DEVREAD("decodmd",decodmd_type2_device,busy_r)
8887   AM_RANGE(0x3800, 0x3800) AM_DEVWRITE(DECOBSMT_TAG, decobsmt_device, bsmt_comms_w)
8988   AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank1")
9089   AM_RANGE(0x8000, 0xffff) AM_ROM AM_REGION("user1", 0x18000)
r23969r23970
104103   membank("bank1")->set_base(memregion("user1")->base() + (data & 0x1f) * 0x4000);
105104}
106105
107WRITE8_MEMBER(whitestar_state::dmd_bank_w)
106// Whitestar automatically pulses the DMD IRQ line?  DE hardware doesn't do that...
107WRITE8_MEMBER(whitestar_state::dmddata_w)
108108{
109   membank("dmd_bank1")->set_base(memregion("dmdcpu")->base() + (data & 0x1f) * 0x4000);
109   m_decodmd->data_w(space,offset,data);
110   m_decodmd->ctrl_w(space,0,1);
111   m_decodmd->ctrl_w(space,0,0);
110112}
111
112READ8_MEMBER(whitestar_state::dmd_latch_r)
113{
114   m_dmd_busy = 0;
115   m_dmdcpu->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
116   return m_dmd_latch;
117}
118
119WRITE8_MEMBER(whitestar_state::dmd_latch_w)
120{
121   m_dmd_latch = data;
122   m_dmd_busy = 1;
123   m_dmdcpu->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
124   m_dmdcpu->set_input_line(M6809_IRQ_LINE, ASSERT_LINE);
125}
126
127READ8_MEMBER(whitestar_state::dmd_ctrl_r)
128{
129   return m_dmd_ctrl;
130}
131
132WRITE8_MEMBER(whitestar_state::dmd_ctrl_w)
133{
134   m_dmd_ctrl = data;
135   m_dmdcpu->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
136   if (data!=0) {
137      bank_w(space,0,0);
138      m_dmdcpu->reset();
139   }
140}
141
142/*U202 - HC245
143  D0 = BUSY   -> SOUND BUSY?
144  D1 = SSTO   -> SOUND RELATED
145  D2 = MPIN   -> ??
146  D3 = CN8-22 -> DMD STAT0
147  D4 = CN8-23 -> DMD STAT1
148  D5 = CN8-24 -> DMD STAT2
149  D6 = CN8-25 -> DMD STAT3
150  D7 = CN8-26 -> DMD BUSY
151*/
152READ8_MEMBER(whitestar_state::dmd_status_r)
153{
154   return (m_dmd_busy ? 0x80 : 0x00) | (m_dmd_status << 3);
155}
156
157WRITE8_MEMBER(whitestar_state::dmd_status_w)
158{
159   m_dmd_status = data & 0x0f;
160}
161
162static ADDRESS_MAP_START( whitestar_dmd_map, AS_PROGRAM, 8, whitestar_state )
163   AM_RANGE(0x0000, 0x1fff) AM_RAM
164   AM_RANGE(0x2000, 0x2fff) AM_RAM AM_SHARE("vram") // video out
165   AM_RANGE(0x3000, 0x3000) AM_DEVREADWRITE("mc6845", mc6845_device, register_r, address_w)
166   AM_RANGE(0x3001, 0x3001) AM_DEVWRITE("mc6845", mc6845_device, register_w)
167   AM_RANGE(0x3002, 0x3002) AM_WRITE(dmd_bank_w)
168   AM_RANGE(0x3003, 0x3003) AM_READ(dmd_latch_r)
169   AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("dmd_bank1")
170   AM_RANGE(0x4000, 0x4000) AM_WRITE(dmd_status_w)
171   AM_RANGE(0x8000, 0xffff) AM_ROM AM_REGION("dmdcpu", 0x78000)
172ADDRESS_MAP_END
173
174113void whitestar_state::machine_reset()
175114{
176115   membank("bank1")->set_base(memregion("user1")->base());
177   membank("dmd_bank1")->set_base(memregion("dmdcpu")->base());
178116}
179117
180118DRIVER_INIT_MEMBER(whitestar_state,whitestar)
r23969r23970
187125   device.execute().set_input_line(M6809_FIRQ_LINE, HOLD_LINE);
188126}
189127
190#define DMD_CHUNK_SIZE 10
191#define MCFG_DMD_ADD(_tag, _width, _height) \
192   MCFG_DEVICE_ADD(_tag, SCREEN, 0) \
193   MCFG_SCREEN_TYPE(LCD) \
194   MCFG_SCREEN_REFRESH_RATE(60) \
195   MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) \
196   MCFG_SCREEN_UPDATE_DEVICE("mc6845", mc6845_device, screen_update) \
197   MCFG_SCREEN_SIZE( _width * DMD_CHUNK_SIZE, _height *DMD_CHUNK_SIZE) \
198   MCFG_SCREEN_VISIBLE_AREA( 0, _width * DMD_CHUNK_SIZE-1, 0, _height*DMD_CHUNK_SIZE-1 ) \
199   MCFG_DEFAULT_LAYOUT( layout_lcd )
200
201
202void dmd_put_pixel(bitmap_rgb32 &bitmap, int x, int y, rgb_t color)
128static const decodmd_intf decodmd_interface =
203129{
204   int midx = x * DMD_CHUNK_SIZE + DMD_CHUNK_SIZE/2;
205   int midy = y * DMD_CHUNK_SIZE + DMD_CHUNK_SIZE/2;
206   int width = DMD_CHUNK_SIZE-2;
207   // compute parameters
208   width /= 2;
209   float ooradius2 = 1.0f / (float)(width * width);
210
211   // iterate over y
212   for (UINT32 y = 0; y <= width; y++)
213   {
214      UINT32 *d0 = &bitmap.pix32(midy - y);
215      UINT32 *d1 = &bitmap.pix32(midy + y);
216      float xval = width * sqrt(1.0f - (float)(y * y) * ooradius2);
217      INT32 left, right;
218
219      // compute left/right coordinates
220      left = midx - (INT32)(xval + 0.5f);
221      right = midx + (INT32)(xval + 0.5f);
222
223      // draw this scanline
224      for (UINT32 x = left; x < right; x++)
225         d0[x] = d1[x] = color;
226   }
227}
228
229MC6845_UPDATE_ROW( whitestar_update_row )
230{
231   whitestar_state *state = device->machine().driver_data<whitestar_state>();
232   const rgb_t *palette = palette_entry_list_raw(bitmap.palette());
233   UINT8 *vram  = state->m_vram + ((ma & 0x100)<<2) + (ra << 4);
234   int xi;
235
236   for (int x = 0; x < 128/8; x++)
237   {
238      UINT16 val = (vram[x]<<8) + vram[x+0x200];
239      val = BITSWAP16(val,15,7,14,6,13,5,12,4,11,3,10,2,9,1,8,0);
240
241      for(xi=0;xi<8;xi++)
242         dmd_put_pixel(bitmap, (x*8 + xi), ra, palette[((val>>(14-xi*2)) & 0x03) + 1]);
243   }
244}
245
246static MC6845_INTERFACE( whitestar_crtc6845_interface )
247{
248   NULL,
249   false,      /* show border area */
250   1,
251   NULL,
252   whitestar_update_row,
253   NULL,
254   DEVCB_NULL,
255   DEVCB_NULL,
256   DEVCB_NULL,
257   DEVCB_NULL,
258   NULL
130   ":dmdcpu"  // region containing DMD ROM data
259131};
260132
261void whitestar_state::palette_init()
262{
263   palette_set_color(machine(), 0, MAKE_RGB(0, 0, 0));
264
265   palette_set_color(machine(), 1, MAKE_RGB(20, 20, 20));
266   palette_set_color(machine(), 2, MAKE_RGB(84, 73, 10));
267   palette_set_color(machine(), 3, MAKE_RGB(168, 147, 21));
268   palette_set_color(machine(), 4, MAKE_RGB(255, 224, 32));
269}
270
271133static MACHINE_CONFIG_START( whitestar, whitestar_state )
272134   /* basic machine hardware */
273135   MCFG_CPU_ADD("maincpu", M6809, 2000000)
274136   MCFG_CPU_PROGRAM_MAP(whitestar_map)
275137   MCFG_CPU_PERIODIC_INT_DRIVER(whitestar_state, whitestar_firq_interrupt,  976) // value taken from PinMAME
276138
277   MCFG_CPU_ADD("dmdcpu", M6809, (8000000/4))
278   MCFG_CPU_PROGRAM_MAP(whitestar_dmd_map)
279   MCFG_CPU_PERIODIC_INT_DRIVER(whitestar_state, whitestar_firq_interrupt,  80) // value taken from PinMAME
280
281
282139   /* sound hardware */
283140   MCFG_DECOBSMT_ADD(DECOBSMT_TAG)
284141
285   MCFG_MC6845_ADD("mc6845", MC6845, 2000000, whitestar_crtc6845_interface)
286
287   /* video hardware */
288   MCFG_DMD_ADD("screen", 128, 32)
289
290   MCFG_PALETTE_LENGTH(5)
142   MCFG_DECODMD_TYPE2_ADD("decodmd",decodmd_interface)
291143MACHINE_CONFIG_END
292144
293145// 8Mbit ROMs are mapped oddly: the first 4Mbit of each of the ROMs goes in order u17, u21, u36, u37

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