MAME SVN History

199869 Revisions

r23921 Tuesday 25th June, 2013 at 04:03:40 UTC by David Haywood
legacy_cpu-- this is a first pass at converting to a modern device, I'd be surprised if there are no issue but it's already a weeks worth of updating + testing.

[src/emu/cpu/m68000]	68307bus.c 68307bus.h 68307ser.c 68307ser.h 68307sim.c 68307sim.h 68307tmu.c 68307tmu.h 68340dma.c 68340dma.h 68340ser.c 68340ser.h 68340sim.c 68340sim.h 68340tmu.c 68340tmu.h m68000.h m68k_in.c m68kcpu.c m68kcpu.h m68kfpu.c m68kmake.c m68kmmu.h
[src/mame/drivers]	astrafr.c bfm_sc4h.c bfm_swp.c cd32.c mpu4vid.c mpu5hw.c pluto5.c segahang.c segaorun.c segas16a.c segaxbd.c
[src/mame/includes]	amiga.h atarig1.h atarig42.h bfm_sc45.h cps1.h cyberbal.h megadriv.h stv.h tatsumi.h toaplan2.h
[src/mame/machine]	cps2crpt.c deco102.c fd1089.c fd1094.c megadriv.c
[src/mess/drivers]	apollo.c dectalk.c
[src/mess/includes]	abc1600.h apollo.h mac.h
[src/mess/machine]	apollo.c apollo_dbg.c mac.c

trunk/src/mame/drivers/pluto5.c
r23920	r23921
195	195	protected:
196	196
197	197	// devices
198		required_device<~~cpu~~_device> m_maincpu;
	198	required_device<m68000_base_device> m_maincpu;
199	199	public:
200	200	DECLARE_DRIVER_INIT(hb);
201	201	virtual void machine_start();

trunk/src/mame/drivers/segaxbd.c
r23920	r23921
601	601
602	602	READ16_MEMBER( segaxbd_state::rascot_excs_r )
603	603	{
604		logerror("%06X:rascot_excs_r(%04X)\n", m_maincpu->pc(), offset*2);
	604	//logerror("%06X:rascot_excs_r(%04X)\n", m_maincpu->pc(), offset*2);
605	605
606	606	// probably receives commands from the server here
607	607	//return space.machine().rand() & 0xff;
r23920	r23921
616	616
617	617	WRITE16_MEMBER( segaxbd_state::rascot_excs_w )
618	618	{
619		logerror("%06X:rascot_excs_w(%04X) = %04X & %04X\n", m_maincpu->pc(), offset*2, data, mem_mask);
	619	//logerror("%06X:rascot_excs_w(%04X) = %04X & %04X\n", m_maincpu->pc(), offset*2, data, mem_mask);
620	620	}
621	621
622	622
r23920	r23921
627	627
628	628	READ16_MEMBER( segaxbd_state::smgp_excs_r )
629	629	{
630		logerror("%06X:smgp_excs_r(%04X)\n", m_maincpu->pc(), offset*2);
	630	//logerror("%06X:smgp_excs_r(%04X)\n", m_maincpu->pc(), offset*2);
631	631	return 0xffff;
632	632	}
633	633
r23920	r23921
639	639
640	640	WRITE16_MEMBER( segaxbd_state::smgp_excs_w )
641	641	{
642		logerror("%06X:smgp_excs_w(%04X) = %04X & %04X\n", m_maincpu->pc(), offset*2, data, mem_mask);
	642	//logerror("%06X:smgp_excs_w(%04X) = %04X & %04X\n", m_maincpu->pc(), offset*2, data, mem_mask);
643	643	}
644	644
645	645

trunk/src/mame/drivers/bfm_sc4h.c
r23920	r23921
551	551	// if (dedicated == false)
552	552	{
553	553	int pc = space.device().safe_pc();
554		//m68ki_cpu_core *m68k = m68k_get_safe_token(&space.device());
	554	//_m68ki_cpu_core *m68k = m68k_get_safe_token(&space.device());
555	555	// serial output to the VFD at least..
556	556	logerror("%08x bfm_sc4_68307_portb_w %04x %04x\n", pc, data, line_mask);
557	557
r23920	r23921
603	603	{
604	604	m_nvram->set_base(m_mainram, sizeof(m_mainram));
605	605
	606
606	607	m68307_set_port_callbacks(m_maincpu,
607	608	bfm_sc4_68307_porta_r,
608	609	bfm_sc4_68307_porta_w,
r23920	r23921
610	611	bfm_sc4_68307_portb_w );
611	612	m68307_set_duart68681(m_maincpu,machine().device("m68307_68681"));
612	613
	614
	615
613	616	int reels = 6;
614	617	m_reels=reels;
615	618

trunk/src/mame/drivers/segas16a.c
r23920	r23921
300	300	case 0x2000/2:
301	301	return ioport((offset & 1) ? "DSW2" : "DSW1")->read();
302	302	}
303		logerror("%06X:standard_io_r - unknown read access to address %04X\n", m_maincpu->pc(), offset * 2);
	303	//logerror("%06X:standard_io_r - unknown read access to address %04X\n", m_maincpu->pc(), offset * 2);
304	304	return 0xffff;
305	305	}
306	306
r23920	r23921
321	321	synchronize(TID_PPI_WRITE, ((offset & 3) << 8) \| (data & 0xff));
322	322	return;
323	323	}
324		logerror("%06X:standard_io_w - unknown write access to address %04X = %04X & %04X\n", m_maincpu->pc(), offset * 2, data, mem_mask);
	324	//logerror("%06X:standard_io_w - unknown write access to address %04X = %04X & %04X\n", m_maincpu->pc(), offset * 2, data, mem_mask);
325	325	}
326	326
327	327

trunk/src/mame/drivers/segahang.c
r23920	r23921
243	243	}
244	244	}
245	245
246		logerror("%06X:hangon_io_r - unknown read access to address %04X\n", m_maincpu->pc(), offset * 2);
	246	//logerror("%06X:hangon_io_r - unknown read access to address %04X\n", m_maincpu->pc(), offset * 2);
247	247	return open_bus_r(space, 0, mem_mask);
248	248	}
249	249
r23920	r23921
271	271	return;
272	272	}
273	273
274		logerror("%06X:hangon_io_w - unknown write access to address %04X = %04X & %04X\n", m_maincpu->pc(), offset * 2, data, mem_mask);
	274	//logerror("%06X:hangon_io_w - unknown write access to address %04X = %04X & %04X\n", m_maincpu->pc(), offset * 2, data, mem_mask);
275	275	}
276	276
277	277
r23920	r23921
304	304	}
305	305	}
306	306
307		logerror("%06X:sharrier_io_r - unknown read access to address %04X\n", m_maincpu->pc(), offset * 2);
	307	//logerror("%06X:sharrier_io_r - unknown read access to address %04X\n", m_maincpu->pc(), offset * 2);
308	308	return open_bus_r(space, 0, mem_mask);
309	309	}
310	310
r23920	r23921
333	333	return;
334	334	}
335	335
336		logerror("%06X:sharrier_io_w - unknown write access to address %04X = %04X & %04X\n", m_maincpu->pc(), offset * 2, data, mem_mask);
	336	//logerror("%06X:sharrier_io_w - unknown write access to address %04X = %04X & %04X\n", m_maincpu->pc(), offset * 2, data, mem_mask);
337	337	}
338	338
339	339

trunk/src/mame/drivers/mpu4vid.c
r23920	r23921
195	195	#include "crmaze2p.lh"
196	196	#include "crmaze4p.lh"
197	197	#include "includes/mpu4.h"
	198	#include "cpu/m68000/m68000.h"
198	199
199	200
200	201	struct ef9369_t
r23920	r23921
230	231	{
231	232	}
232	233
233		required_device<~~cpu~~_device> m_videocpu;
	234	required_device<m68000_base_device> m_videocpu;
234	235	optional_device<scn2674_device> m_scn2674;
235	236	optional_shared_ptr<UINT16> m_vid_vidram;
236	237	optional_shared_ptr<UINT16> m_vid_mainram;

trunk/src/mame/drivers/cd32.c
r23920	r23921
1245	1245	static void cndypuzl_input_hack(running_machine &machine)
1246	1246	{
1247	1247	cd32_state *state = machine.driver_data<cd32_state>();
	1248	cpu_device* thiscpu = (cpu_device*)state->m_maincpu;
1248	1249
1249		if (st~~ate->m_ma~~incpu->pc() < state->m_chip_ram.bytes())
	1250	if (thiscpu->pc() < state->m_chip_ram.bytes())
1250	1251	{
1251	1252	//(*state->m_chip_ram_w)(0x051c02, 0x0000);
1252	1253
r23920	r23921
1264	1265	static void haremchl_input_hack(running_machine &machine)
1265	1266	{
1266	1267	cd32_state *state = machine.driver_data<cd32_state>();
	1268	cpu_device* thiscpu = (cpu_device*)state->m_maincpu;
1267	1269
1268		if (st~~ate->m_ma~~incpu->pc() < state->m_chip_ram.bytes())
	1270	if (thiscpu->pc() < state->m_chip_ram.bytes())
1269	1271	{
1270	1272	//amiga_chip_ram_w8(state, 0x002907, 0x00);
1271	1273
r23920	r23921
1284	1286	static void lsrquiz_input_hack(running_machine &machine)
1285	1287	{
1286	1288	cd32_state *state = machine.driver_data<cd32_state>();
	1289	cpu_device* thiscpu = (cpu_device*)state->m_maincpu;
1287	1290
1288		if (st~~ate->m_ma~~incpu->pc() < state->m_chip_ram.bytes())
	1291	if (thiscpu->pc() < state->m_chip_ram.bytes())
1289	1292	{
1290	1293	//amiga_chip_ram_w8(state, 0x001e1b, 0x00);
1291	1294
r23920	r23921
1305	1308	static void lsrquiz2_input_hack(running_machine &machine)
1306	1309	{
1307	1310	cd32_state *state = machine.driver_data<cd32_state>();
	1311	cpu_device* thiscpu = (cpu_device*)state->m_maincpu;
1308	1312
1309		if (st~~ate->m_ma~~incpu->pc() < state->m_chip_ram.bytes())
	1313	if (thiscpu->pc() < state->m_chip_ram.bytes())
1310	1314	{
1311	1315	//amiga_chip_ram_w8(state, 0x046107, 0x00);
1312	1316
r23920	r23921
1325	1329	static void lasstixx_input_hack(running_machine &machine)
1326	1330	{
1327	1331	cd32_state *state = machine.driver_data<cd32_state>();
	1332	cpu_device* thiscpu = (cpu_device*)state->m_maincpu;
1328	1333
1329		if (st~~ate->m_ma~~incpu->pc() < state->m_chip_ram.bytes())
	1334	if (thiscpu->pc() < state->m_chip_ram.bytes())
1330	1335	{
1331	1336	//amiga_chip_ram_w8(state, 0x00281c, 0x00);
1332	1337
r23920	r23921
1345	1350	static void mgnumber_input_hack(running_machine &machine)
1346	1351	{
1347	1352	cd32_state *state = machine.driver_data<cd32_state>();
	1353	cpu_device* thiscpu = (cpu_device*)state->m_maincpu;
1348	1354
1349		if (st~~ate->m_ma~~incpu->pc() < state->m_chip_ram.bytes())
	1355	if (thiscpu->pc() < state->m_chip_ram.bytes())
1350	1356	{
1351	1357	//(*state->m_chip_ram_w)(0x04bfa0, 0x0000);
1352	1358
r23920	r23921
1364	1370	static void mgprem11_input_hack(running_machine &machine)
1365	1371	{
1366	1372	cd32_state *state = machine.driver_data<cd32_state>();
	1373	cpu_device* thiscpu = (cpu_device*)state->m_maincpu;
1367	1374
1368		if (st~~ate->m_ma~~incpu->pc() < state->m_chip_ram.bytes())
	1375	if (thiscpu->pc() < state->m_chip_ram.bytes())
1369	1376	{
1370	1377	//amiga_chip_ram_w8(state, 0x044f7e, 0x00);
1371	1378

trunk/src/mame/drivers/bfm_swp.c
r23920	r23921
127	127	protected:
128	128
129	129	// devices
130		required_device<~~cpu~~_device> m_maincpu;
	130	required_device<m68000_base_device> m_maincpu;
131	131
132	132	virtual void machine_start();
133	133	};

trunk/src/mame/drivers/astrafr.c
r23920	r23921
113	113	}
114	114
115	115	// devices
116		required_device<cpu_device> m_maincpu;
117		optional_device<cpu_device> m_slavecpu;
	116	required_device<m68000_base_device> m_maincpu;
	117	optional_device<m68000_base_device> m_slavecpu;
118	118
119	119	DECLARE_DRIVER_INIT(astradec_sml);
120	120	DECLARE_DRIVER_INIT(astradec);

trunk/src/mame/drivers/segaorun.c
r23920	r23921
348	348
349	349	READ8_MEMBER( segaorun_state::unknown_porta_r )
350	350	{
351		logerror("%06X:read from 8255 port A\n", m_maincpu->pc());
	351	//logerror("%06X:read from 8255 port A\n", m_maincpu->pc());
352	352	return 0;
353	353	}
354	354
355	355	READ8_MEMBER( segaorun_state::unknown_portb_r )
356	356	{
357		logerror("%06X:read from 8255 port B\n", m_maincpu->pc());
	357	//logerror("%06X:read from 8255 port B\n", m_maincpu->pc());
358	358	return 0;
359	359	}
360	360
361	361	READ8_MEMBER( segaorun_state::unknown_portc_r )
362	362	{
363		logerror("%06X:read from 8255 port C\n", m_maincpu->pc());
	363	//logerror("%06X:read from 8255 port C\n", m_maincpu->pc());
364	364	return 0;
365	365	}
366	366
r23920	r23921
372	372
373	373	WRITE8_MEMBER( segaorun_state::unknown_porta_w )
374	374	{
375		logerror("%06X:write %02X to 8255 port A\n", m_maincpu->pc(), data);
	375	//logerror("%06X:write %02X to 8255 port A\n", m_maincpu->pc(), data);
376	376	}
377	377
378	378	WRITE8_MEMBER( segaorun_state::unknown_portb_w )
379	379	{
380		logerror("%06X:write %02X to 8255 port B\n", m_maincpu->pc(), data);
	380	//logerror("%06X:write %02X to 8255 port B\n", m_maincpu->pc(), data);
381	381	}
382	382
383	383

trunk/src/mame/drivers/mpu5hw.c
r23920	r23921
58	58	protected:
59	59
60	60	// devices
61		required_device<~~cpu~~_device> m_maincpu;
	61	required_device<m68000_base_device> m_maincpu;
62	62	virtual void machine_start();
63	63	};
64	64

trunk/src/mame/machine/fd1094.c
r23920	r23921
605	605	// fd1094_device - constructor
606	606	//-------------------------------------------------
607	607
	608
608	609	fd1094_device::fd1094_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
609		: m68000_device(mconfig, ~~M68000,~~ tag, owner, clock),
	610	: m68000_device(mconfig, tag, owner, clock),
610	611	m_state(0x00),
611	612	m_irqmode(false),
612	613	m_cache(*this),

trunk/src/mame/machine/deco102.c
r23920	r23921
59	59	memcpy(buf, rom, size);
60	60
61	61	space.set_decrypted_region(0, size - 1, opcodes);
62		m68k_set_encrypted_opcode_range(machine.device(cputag), 0, size);
	62	m68k_set_encrypted_opcode_range((m68000_base_device*)machine.device(cputag), 0, size);
63	63
64	64	for (i = 0; i < size / 2; i++)
65	65	{

trunk/src/mame/machine/megadriv.c
r23920	r23921
1144	1144	}
1145	1145
1146	1146	m68k_set_tas_callback(m_maincpu, megadriv_tas_callback);
1147
	1147
1148	1148	m_megadrive_io_read_data_port_ptr = read8_delegate(FUNC(md_base_state::megadrive_io_read_data_port_3button),this);
1149	1149	m_megadrive_io_write_data_port_ptr = write16_delegate(FUNC(md_base_state::megadrive_io_write_data_port_3button),this);
1150	1150

trunk/src/mame/machine/fd1089.c
r23920	r23921
215	215	//-------------------------------------------------
216	216
217	217	fd1089_base_device::fd1089_base_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock)
218		: m68000_device(mconfig, ~~M68000,~~ tag, owner, clock)
	218	: m68000_device(mconfig, tag, owner, clock)
219	219	{
220	220	// override the name after the m68000 initializes
221	221	m_name.cpy(name);

trunk/src/mame/machine/cps2crpt.c
r23920	r23921
721	721	}
722	722
723	723	space.set_decrypted_region(0x000000, length - 1, dec);
724		m68k_set_encrypted_opcode_range(machine.device("maincpu"), 0, length);
	724	m68k_set_encrypted_opcode_range((m68000_base_device*)machine.device("maincpu"), 0, length);
725	725	}
726	726
727	727

trunk/src/mame/includes/megadriv.h
r23920	r23921
18	18	#include "machine/mega32x.h"
19	19	#include "machine/megacd.h"
20	20	#include "video/315_5124.h"
	21	#include "cpu/m68000/m68000.h"
21	22
22	23	#define MASTER_CLOCK_NTSC 53693175
23	24	#define MASTER_CLOCK_PAL 53203424
r23920	r23921
68	69	m_segacd(*this,"segacd"),
69	70	m_megadrive_ram(*this,"megadrive_ram")
70	71	{ }
71		required_device<~~cpu~~_device> m_maincpu;
	72	required_device<m68000_base_device> m_maincpu;
72	73	optional_device<cpu_device> m_z80snd;
73	74	optional_device<ym2612_device> m_ymsnd;
74	75	required_device<sega_genesis_vdp_device> m_vdp;

trunk/src/mame/includes/cps1.h
r23920	r23921
5	5	#include "sound/qsound.h"
6	6	#include "sound/okim6295.h"
7	7	#include "machine/timekpr.h"
	8	#include "cpu/m68000/m68000.h"
8	9
9	10	struct gfx_range
10	11	{
r23920	r23921
166	167	UINT16 *m_bootleg_work_ram;
167	168
168	169	/* devices */
169		required_device<~~cpu~~_device> m_maincpu;
	170	required_device<m68000_base_device> m_maincpu;
170	171	optional_device<cpu_device> m_audiocpu;
171	172	optional_device<okim6295_device> m_oki;
172	173	optional_device<m48t35_device> m_m48t35;

trunk/src/mame/includes/tatsumi.h
r23920	r23921
1	1	#include "sound/okim6295.h"
	2	#include "cpu/m68000/m68000.h"
2	3
3	4	class tatsumi_state : public driver_device
4	5	{
r23920	r23921
136	137	DECLARE_READ8_MEMBER(tatsumi_hack_oki_r);
137	138	required_device<cpu_device> m_maincpu;
138	139	required_device<cpu_device> m_audiocpu;
139		required_device<~~cpu~~_device> m_subcpu;
	140	required_device<m68000_base_device> m_subcpu;
140	141	optional_device<cpu_device> m_subcpu2;
141	142	required_device<okim6295_device> m_oki;
142	143	};

trunk/src/mame/includes/atarig1.h
r23920	r23921
15	15	m_maincpu(*this, "maincpu"),
16	16	m_mo_command(*this, "mo_command") { }
17	17
18		required_device<~~m68000~~_device> m_maincpu;
	18	required_device<cpu_device> m_maincpu;
19	19
20	20	bool m_is_pitfight;
21	21

trunk/src/mame/includes/toaplan2.h
r23920	r23921
11	11	// VDP related
12	12	#include "video/gp9001.h"
13	13	#include "sound/okim6295.h"
	14	#include "cpu/m68000/m68000.h"
14	15	// Cache the CPUs and VDPs for faster access
15	16	class toaplan2_state : public driver_device
16	17	{
r23920	r23921
148	149	void toaplan2_vblank_irq(int irq_line);
149	150	DECLARE_WRITE_LINE_MEMBER(irqhandler);
150	151	DECLARE_WRITE_LINE_MEMBER(bbakraid_irqhandler);
151		required_device<~~cpu~~_device> m_maincpu;
	152	required_device<m68000_base_device> m_maincpu;
152	153	optional_device<cpu_device> m_audiocpu;
153	154	optional_device<nmk112_device> m_nmk112;
154	155	optional_device<okim6295_device> m_oki;

trunk/src/mame/includes/atarig42.h
r23920	r23921
15	15	m_maincpu(*this, "maincpu"),
16	16	m_mo_command(*this, "mo_command") { }
17	17
18		required_device<~~m68000~~_device> m_maincpu;
	18	required_device<cpu_device> m_maincpu;
19	19
20	20	UINT16 m_playfield_base;
21	21

trunk/src/mame/includes/bfm_sc45.h
r23920	r23921
9	9	#include "sound/ymz280b.h"
10	10	#include "machine/68681.h"
11	11	#include "machine/nvram.h"
	12	#include "cpu/m68000/m68000.h"
12	13
13	14	// common base class for things shared between sc4 and sc5
14	15	class bfm_sc45_state : public driver_device
r23920	r23921
24	25	}
25	26
26	27	public:
27		required_device<~~legacy~~_~~cpu~~_device> m_maincpu;
	28	required_device<m68000_base_device> m_maincpu;
28	29	required_device<duart68681_device> m_duart;
29	30	optional_device<bfm_bda_t> m_vfd0;
30	31	required_device<ymz280b_device> m_ymz;
r23920	r23921
547	548	DECLARE_MACHINE_START(adder4);
548	549
549	550	// devices
550		required_device<~~cpu~~_device> m_adder4cpu;
	551	required_device<m68000_base_device> m_adder4cpu;
551	552	};
552	553
553	554

trunk/src/mame/includes/amiga.h
r23920	r23921
14	14
15	15	#include "machine/6526cia.h"
16	16	#include "machine/amigafdc.h"
	17	#include "cpu/m68000/m68000.h"
17	18
	19
18	20	/*************************************
19	21	*
20	22	* Debugging
r23920	r23921
400	402
401	403	{ }
402	404
403		required_device<~~cpu~~_device> m_maincpu;
	405	required_device<m68000_base_device> m_maincpu;
404	406	required_device<legacy_mos6526_device> m_cia_0;
405	407	required_device<legacy_mos6526_device> m_cia_1;
406	408	optional_device<amiga_fdc> m_fdc;

trunk/src/mame/includes/cyberbal.h
r23920	r23921
23	23	m_paletteram_0(*this, "paletteram_0"),
24	24	m_paletteram_1(*this, "paletteram_1") { }
25	25
26		required_device<~~m68000~~_device> m_maincpu;
	26	required_device<cpu_device> m_maincpu;
27	27	optional_device<m6502_device> m_audiocpu;
28		optional_device<m68000_device> m_extracpu;
29		optional_device<m68000_device> m_daccpu;
	28	optional_device<cpu_device> m_extracpu;
	29	optional_device<cpu_device> m_daccpu;
30	30	optional_device<dac_device> m_dac1;
31	31	optional_device<dac_device> m_dac2;
32	32	optional_shared_ptr<UINT16> m_paletteram_0;

trunk/src/mame/includes/stv.h
r23920	r23921
1	1	/----------- defined in drivers/stv.c -----------/
2	2	#include "cdrom.h"
3	3	#include "machine/eeprom.h"
	4	#include "cpu/m68000/m68000.h"
4	5
5	6	#define MAX_FILTERS (24)
6	7	#define MAX_BLOCKS (200)
r23920	r23921
141	142
142	143	required_device<cpu_device> m_maincpu;
143	144	required_device<cpu_device> m_slave;
144		required_device<~~cpu~~_device> m_audiocpu;
	145	required_device<m68000_base_device> m_audiocpu;
145	146	optional_device<eeprom_device> m_eeprom;
146	147
147	148	bitmap_rgb32 m_tmpbitmap;

trunk/src/emu/cpu/m68000/68340sim.c
r23920	r23921
4	4	#include "m68kcpu.h"
5	5
6	6
7		READ16_~~HANDL~~ER( m68340_internal_sim_r )
	7	READ16_MEMBER( m68000_base_device::m68340_internal_sim_r )
8	8	{
9		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	9	m68000_base_device *m68k = this;
10	10	m68340_sim* sim = m68k->m68340SIM;
11	11	assert(sim != NULL);
12	12
r23920	r23921
54	54	return 0x0000;
55	55	}
56	56
57		READ8_~~HANDL~~ER( m68340_internal_sim_ports_r )
	57	READ8_MEMBER( m68000_base_device::m68340_internal_sim_ports_r )
58	58	{
59	59	offset += 0x10;
60		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	60	m68000_base_device *m68k = this;
61	61	m68340_sim* sim = m68k->m68340SIM;
62	62	assert(sim != NULL);
63	63
r23920	r23921
109	109	return 0x00;
110	110	}
111	111
112		READ32_~~HANDL~~ER( m68340_internal_sim_cs_r )
	112	READ32_MEMBER( m68000_base_device::m68340_internal_sim_cs_r )
113	113	{
114	114	offset += m68340SIM_AM_CS0>>2;
115	115
116		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	116	m68000_base_device *m68k = this;
117	117	m68340_sim* sim = m68k->m68340SIM;
118	118	assert(sim != NULL);
119	119
r23920	r23921
141	141	return 0x00000000;
142	142	}
143	143
144		WRITE16_~~HANDL~~ER( m68340_internal_sim_w )
	144	WRITE16_MEMBER( m68000_base_device::m68340_internal_sim_w )
145	145	{
146		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	146	m68000_base_device *m68k = this;
147	147	m68340_sim* sim = m68k->m68340SIM;
148	148	assert(sim != NULL);
149	149
r23920	r23921
190	190	}
191	191	}
192	192
193		WRITE8_~~HANDL~~ER( m68340_internal_sim_ports_w )
	193	WRITE8_MEMBER( m68000_base_device::m68340_internal_sim_ports_w )
194	194	{
195	195	offset += 0x10;
196		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	196	m68000_base_device *m68k = this;
197	197	m68340_sim* sim = m68k->m68340SIM;
198	198	assert(sim != NULL);
199	199
r23920	r23921
243	243	}
244	244	}
245	245
246		WRITE32_~~HANDL~~ER( m68340_internal_sim_cs_w )
	246	WRITE32_MEMBER( m68000_base_device::m68340_internal_sim_cs_w )
247	247	{
248	248	offset += m68340SIM_AM_CS0>>2;
249		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	249	m68000_base_device *m68k = this;
250	250	m68340_sim* sim = m68k->m68340SIM;
251	251	assert(sim != NULL);
252	252

trunk/src/emu/cpu/m68000/m68kcpu.c
r23920	r23921
37	37	#include <setjmp.h>
38	38	#include "m68kcpu.h"
39	39	#include "m68kops.h"
	40
40	41	#include "m68kfpu.c"
41
42	42	#include "m68kmmu.h"
43	43
44		extern void m68040_fpu_op0(m68ki_cpu_core *m68k);
45		extern void m68040_fpu_op1(m68ki_cpu_core *m68k);
46		extern void m68881_mmu_ops(m68ki_cpu_core *m68k);
	44	extern void m68040_fpu_op0(m68000_base_device *m68k);
	45	extern void m68040_fpu_op1(m68000_base_device *m68k);
	46	extern void m68881_mmu_ops(m68000_base_device *m68k);
47	47
48	48	/* ======================================================================== */
49	49	/* ================================= DATA ================================= */
r23920	r23921
644	644	/* ================================= API ================================== */
645	645	/* ======================================================================== */
646	646
647		static void set_irq_line(m68ki_~~cpu~~_core *m68k, int irqline, int state)
	647	static void set_irq_line(m68000_base_device *m68k, int irqline, int state)
648	648	{
649	649	UINT32 old_level = m68k->int_level;
650	650	UINT32 vstate = m68k->virq_state;
r23920	r23921
668	668	m68k->nmi_pending = TRUE;
669	669	}
670	670
671		static void m68k_presave(m68ki_~~cpu~~_core *m68k)
	671	static void m68k_presave(m68000_base_device *m68k)
672	672	{
673	673	m68k->save_sr = m68ki_get_sr(m68k);
674	674	m68k->save_stopped = (m68k->stopped & STOP_LEVEL_STOP) != 0;
675	675	m68k->save_halted = (m68k->stopped & STOP_LEVEL_HALT) != 0;
676	676	}
677	677
678		static void m68k_postload(m68ki_~~cpu~~_core *m68k)
	678	static void m68k_postload(m68000_base_device *m68k)
679	679	{
680	680	m68ki_set_sr_noint_nosp(m68k, m68k->save_sr);
681	681	m68k->stopped = m68k->save_stopped ? STOP_LEVEL_STOP : 0
r23920	r23921
683	683	m68ki_jump(m68k, REG_PC(m68k));
684	684	}
685	685
686		static void m68k_cause_bus_error(m68ki_~~cpu~~_core *m68k)
	686	static void m68k_cause_bus_error(m68000_base_device *m68k)
687	687	{
688	688	UINT32 sr;
689	689
r23920	r23921
708	708	m68ki_jump_vector(m68k, EXCEPTION_BUS_ERROR);
709	709	}
710	710
711		/* translate logical to physical addresses */
712		static CPU_TRANSLATE( m68k )
	711	bool m68000_base_device::memory_translate(address_spacenum space, int intention, offs_t &address)
713	712	{
714		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
715
716	713	/* only applies to the program address space and only does something if the MMU's enabled */
717		if (~~m68k~~)
	714	if (this)
718	715	{
719	716	/* 68040 needs to call the MMU even when disabled so transparent translation works */
720		if ((space == AS_PROGRAM) && ((~~m68k->~~pmmu_enabled) \|\| (CPU_TYPE_IS_040_PLUS(~~m68k->~~cpu_type))))
	717	if ((space == AS_PROGRAM) && ((pmmu_enabled) \|\| (CPU_TYPE_IS_040_PLUS(cpu_type))))
721	718	{
722	719	// FIXME: mmu_tmp_sr will be overwritten in pmmu_translate_addr_with_fc
723		UINT16 mmu_tmp_sr = m68k->mmu_tmp_sr;
724		int mode = m68k->s_flag ? FUNCTION_CODE_SUPERVISOR_PROGRAM : FUNCTION_CODE_USER_PROGRAM;
725		// UINT32 va=*address;
	720	UINT16 temp_mmu_tmp_sr = mmu_tmp_sr;
	721	int mode = s_flag ? FUNCTION_CODE_SUPERVISOR_PROGRAM : FUNCTION_CODE_USER_PROGRAM;
	722	// UINT32 va=address;
726	723
727		if (CPU_TYPE_IS_040_PLUS(~~m68k->~~cpu_type))
	724	if (CPU_TYPE_IS_040_PLUS(cpu_type))
728	725	{
729		address = pmmu_translate_addr_with_fc_040(~~m68k~~, address, mode, 1);
	726	address = pmmu_translate_addr_with_fc_040(this, address, mode, 1);
730	727	}
731	728	else
732	729	{
733		address = pmmu_translate_addr_with_fc(~~m68k~~, address, mode, 1);
	730	address = pmmu_translate_addr_with_fc(this, address, mode, 1);
734	731	}
735	732
736		if ((m68k->mmu_tmp_sr & M68K_MMU_SR_INVALID) != 0) {
737		// logerror("cpu_translate_m68k failed with mmu_sr=%04x va=%08x pa=%08x\n",m68k->mmu_tmp_sr,va ,*address);
738		*address = 0;
	733	if ((mmu_tmp_sr & M68K_MMU_SR_INVALID) != 0) {
	734	// logerror("cpu_translate_m68k failed with mmu_sr=%04x va=%08x pa=%08x\n",mmu_tmp_sr,va ,address);
	735	address = 0;
739	736	}
740	737
741		m~~68k->~~mmu_tmp_sr = mmu_tmp_sr;
	738	mmu_tmp_sr = temp_mmu_tmp_sr;
742	739	}
743	740	}
744	741	return TRUE;
745	742	}
746	743
747		/* translate logical to physical addresses for Apple HMMU */
748		static CPU_TRANSLATE( m68khmmu )
749		{
750		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
751	744
752		/* only applies to the program address space and only does something if the MMU's enabled */
753		if (m68k)
754		{
755		if ((space == AS_PROGRAM) && (m68k->hmmu_enabled))
756		{
757		address = hmmu_translate_addr(m68k, address);
758		}
759		}
760		return TRUE;
761		}
762	745
763		/* Execute some instructions until we use up cycles clock cycles */
764		static CPU_EXECUTE( m68k )
	746
	747
	748
	749
	750
	751
	752	inline void m68000_base_device::cpu_execute(void)
765	753	{
766		~~m68k~~i_c~~pu_~~core *m68k = ~~m68k_g~~e~~t_s~~a~~fe_toke~~n~~(dev~~ice);
	754	initial_cycles = remaining_cycles;
767	755
768		m68k->initial_cycles = m68k->remaining_cycles;
769
770	756	/* eat up any reset cycles */
771		if (m68k->reset_cycles) {
772		int rc = m68k->reset_cycles;
773		m68k->reset_cycles = 0;
774		m68k->remaining_cycles -= rc;
	757	if (reset_cycles) {
	758	int rc = reset_cycles;
	759	reset_cycles = 0;
	760	remaining_cycles -= rc;
775	761
776		if (~~m68k->~~remaining_cycles <= 0) return;
	762	if (remaining_cycles <= 0) return;
777	763	}
778	764
779	765	/* See if interrupts came in */
780		m68ki_check_interrupts(~~m68k~~);
	766	m68ki_check_interrupts(this);
781	767
782	768	/* Make sure we're not stopped */
783		if(!~~m68k->~~stopped)
	769	if(!stopped)
784	770	{
785	771	/* Return point if we had an address error */
786		m68ki_set_address_error_trap(~~m68k~~); /* auto-disable (see m68kcpu.h) */
	772	m68ki_set_address_error_trap(this); /* auto-disable (see m68kcpu.h) */
787	773
788	774	/* Main loop. Keep going until we run out of clock cycles */
789		while (~~m68k->~~remaining_cycles > 0)
	775	while (remaining_cycles > 0)
790	776	{
791	777	/* Set tracing accodring to T1. (T0 is done inside instruction) */
792		m68ki_trace_t1(~~m68k~~); /* auto-disable (see m68kcpu.h) */
	778	m68ki_trace_t1(this); /* auto-disable (see m68kcpu.h) */
793	779
794	780	/* Call external hook to peek at CPU */
795		debugger_instruction_hook(~~dev~~ice, REG_PC(~~m68k~~));
	781	debugger_instruction_hook(this, REG_PC(this));
796	782
797	783	/* call external instruction hook (independent of debug mode) */
798		if (m68k->instruction_hook != NULL)
799		m68k->instruction_hook(device, REG_PC(m68k));
	784	if (instruction_hook != NULL)
	785	instruction_hook(this, REG_PC(this));
800	786
801	787	/* Record previous program counter */
802		REG_PPC(~~m68k~~) = REG_PC(~~m68k~~);
	788	REG_PPC(this) = REG_PC(this);
803	789
804		if (!~~m68k->~~pmmu_enabled)
	790	if (!pmmu_enabled)
805	791	{
806		~~m68k->~~run_mode = RUN_MODE_NORMAL;
	792	run_mode = RUN_MODE_NORMAL;
807	793	/* Read an instruction and call its handler */
808		m68k->ir = m68ki_read_imm_16(m68k);
809		m68k->jump_table[m68k->ir](m68k);
810		m68k->remaining_cycles -= m68k->cyc_instruction[m68k->ir];
	794	ir = m68ki_read_imm_16(this);
	795	jump_table[ir](this);
	796	remaining_cycles -= cyc_instruction[ir];
811	797	}
812	798	else
813	799	{
814		~~m68k->~~run_mode = RUN_MODE_NORMAL;
	800	run_mode = RUN_MODE_NORMAL;
815	801	// save CPU address registers values at start of instruction
816	802	int i;
817	803	UINT32 tmp_dar[16];
818	804
819	805	for (i = 15; i >= 0; i--)
820	806	{
821		tmp_dar[i] = REG_DA(~~m68k~~)[i];
	807	tmp_dar[i] = REG_DA(this)[i];
822	808	}
823	809
824		m~~68k->m~~mu_tmp_buserror_occurred = 0;
	810	mmu_tmp_buserror_occurred = 0;
825	811
826	812	/* Read an instruction and call its handler */
827		~~m68k->~~ir = m68ki_read_imm_16(~~m68k~~);
	813	ir = m68ki_read_imm_16(this);
828	814
829		if (!m~~68k->m~~mu_tmp_buserror_occurred)
	815	if (!mmu_tmp_buserror_occurred)
830	816	{
831		m68k->jump_table[m68k->ir](m68k);
832		m68k->remaining_cycles -= m68k->cyc_instruction[m68k->ir];
	817	jump_table[ir](this);
	818	remaining_cycles -= cyc_instruction[ir];
833	819	}
834	820
835		if (m~~68k->m~~mu_tmp_buserror_occurred)
	821	if (mmu_tmp_buserror_occurred)
836	822	{
837	823	UINT32 sr;
838	824
839		m~~68k->m~~mu_tmp_buserror_occurred = 0;
	825	mmu_tmp_buserror_occurred = 0;
840	826
841	827	// restore cpu address registers to value at start of instruction
842	828	for (i = 15; i >= 0; i--)
843	829	{
844		if (REG_DA(~~m68k~~)[i] != tmp_dar[i])
	830	if (REG_DA(this)[i] != tmp_dar[i])
845	831	{
846	832	// logerror("PMMU: pc=%08x sp=%08x bus error: fixed %s[%d]: %08x -> %08x\n",
847		// REG_PPC(m68k), REG_A(m68k)[7], i < 8 ? "D" : "A", i & 7, REG_DA(m68k)[i], tmp_dar[i]);
848		REG_DA(m68k)[i] = tmp_dar[i];
	833	// REG_PPC(this), REG_A(this)[7], i < 8 ? "D" : "A", i & 7, REG_DA(this)[i], tmp_dar[i]);
	834	REG_DA(this)[i] = tmp_dar[i];
849	835	}
850	836	}
851	837
852		sr = m68ki_init_exception(~~m68k~~);
	838	sr = m68ki_init_exception(this);
853	839
854		~~m68k->~~run_mode = RUN_MODE_BERR_AERR_RESET;
	840	run_mode = RUN_MODE_BERR_AERR_RESET;
855	841
856		if (!CPU_TYPE_IS_020_PLUS(~~m68k->~~cpu_type))
	842	if (!CPU_TYPE_IS_020_PLUS(cpu_type))
857	843	{
858	844	/* Note: This is implemented for 68000 only! */
859		m68ki_stack_frame_buserr(~~m68k~~, sr);
	845	m68ki_stack_frame_buserr(this, sr);
860	846	}
861		else if(!CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) {
862		if (m68k->mmu_tmp_buserror_address == REG_PPC(m68k))
	847	else if(!CPU_TYPE_IS_040_PLUS(cpu_type)) {
	848	if (mmu_tmp_buserror_address == REG_PPC(this))
863	849	{
864		m68ki_stack_frame_1010(~~m68k~~, sr, EXCEPTION_BUS_ERROR, REG_PPC(~~m68k~~), ~~m68k->~~mmu_tmp_buserror_address);
	850	m68ki_stack_frame_1010(this, sr, EXCEPTION_BUS_ERROR, REG_PPC(this), mmu_tmp_buserror_address);
865	851	}
866	852	else
867	853	{
868		m68ki_stack_frame_1011(~~m68k~~, sr, EXCEPTION_BUS_ERROR, REG_PPC(~~m68k~~), ~~m68k->~~mmu_tmp_buserror_address);
	854	m68ki_stack_frame_1011(this, sr, EXCEPTION_BUS_ERROR, REG_PPC(this), mmu_tmp_buserror_address);
869	855	}
870	856	}
871	857	else
872	858	{
873		m68ki_stack_frame_0111(~~m68k~~, sr, EXCEPTION_BUS_ERROR, REG_PPC(~~m68k~~), ~~m68k->~~mmu_tmp_buserror_address, true);
	859	m68ki_stack_frame_0111(this, sr, EXCEPTION_BUS_ERROR, REG_PPC(this), mmu_tmp_buserror_address, true);
874	860	}
875	861
876		m68ki_jump_vector(~~m68k~~, EXCEPTION_BUS_ERROR);
	862	m68ki_jump_vector(this, EXCEPTION_BUS_ERROR);
877	863
878	864	// TODO:
879	865	/* Use up some clock cycles and undo the instruction's cycles */
880		// ~~m68k->~~remaining_cycles -= ~~m68k->~~cyc_exception[EXCEPTION_BUS_ERROR] - ~~m68k->~~cyc_instruction[~~m68k->~~ir];
	866	// remaining_cycles -= cyc_exception[EXCEPTION_BUS_ERROR] - cyc_instruction[ir];
881	867	}
882	868	}
883	869
884	870	/* Trace m68k_exception, if necessary */
885		m68ki_exception_if_trace(~~m68k~~); /* auto-disable (see m68kcpu.h) */
	871	m68ki_exception_if_trace(this); /* auto-disable (see m68kcpu.h) */
886	872	}
887	873
888	874	/* set previous PC to current PC for the next entry into the loop */
889		REG_PPC(~~m68k~~) = REG_PC(~~m68k~~);
	875	REG_PPC(this) = REG_PC(this);
890	876	}
891		else if (m68k->remaining_cycles > 0)
892		m68k->remaining_cycles = 0;
	877	else if (remaining_cycles > 0)
	878	remaining_cycles = 0;
893	879	}
894	880
895		static CPU_INIT( m68k )
	881
	882
	883	void m68000_base_device::init_cpu_common(void)
896	884	{
897	885	static UINT32 emulation_initialized = 0;
898		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
899	886
900		m68k->device = device;
901		m68k->program = &device->space(AS_PROGRAM);
902		m68k->int_ack_callback = irqcallback;
	887	//this = device;//deviceparam;
	888	program = &space(AS_PROGRAM);
	889	int_ack_callback = static_standard_irq_callback;
903	890
904	891	/* disable all MMUs */
905		m68k->has_pmmu = 0;
906		m68k->has_hmmu = 0;
907		m68k->pmmu_enabled = 0;
908		m68k->hmmu_enabled = 0;
	892	has_pmmu = 0;
	893	has_hmmu = 0;
	894	pmmu_enabled = 0;
	895	hmmu_enabled = 0;
909	896
910	897	/* The first call to this function initializes the opcode handler jump table */
911	898	if(!emulation_initialized)
r23920	r23921
915	902	}
916	903
917	904	/* Note, D covers A because the dar array is common, REG_A(m68k)=REG_D(m68k)+8 */
918		device->save_item(NAME(REG_D(m68k)));
919		device->save_item(NAME(REG_PPC(m68k)));
920		device->save_item(NAME(REG_PC(m68k)));
921		device->save_item(NAME(REG_USP(m68k)));
922		device->save_item(NAME(REG_ISP(m68k)));
923		device->save_item(NAME(REG_MSP(m68k)));
924		device->save_item(NAME(m68k->vbr));
925		device->save_item(NAME(m68k->sfc));
926		device->save_item(NAME(m68k->dfc));
927		device->save_item(NAME(m68k->cacr));
928		device->save_item(NAME(m68k->caar));
929		device->save_item(NAME(m68k->save_sr));
930		device->save_item(NAME(m68k->int_level));
931		device->save_item(NAME(m68k->save_stopped));
932		device->save_item(NAME(m68k->save_halted));
933		device->save_item(NAME(m68k->pref_addr));
934		device->save_item(NAME(m68k->pref_data));
935		device->machine().save().register_presave(save_prepost_delegate(FUNC(m68k_presave), m68k));
936		device->machine().save().register_postload(save_prepost_delegate(FUNC(m68k_postload), m68k));
	905	save_item(NAME(REG_D(this)));
	906	save_item(NAME(REG_PPC(this)));
	907	save_item(NAME(REG_PC(this)));
	908	save_item(NAME(REG_USP(this)));
	909	save_item(NAME(REG_ISP(this)));
	910	save_item(NAME(REG_MSP(this)));
	911	save_item(NAME(vbr));
	912	save_item(NAME(sfc));
	913	save_item(NAME(dfc));
	914	save_item(NAME(cacr));
	915	save_item(NAME(caar));
	916	save_item(NAME(save_sr));
	917	save_item(NAME(int_level));
	918	save_item(NAME(save_stopped));
	919	save_item(NAME(save_halted));
	920	save_item(NAME(pref_addr));
	921	save_item(NAME(pref_data));
	922	machine().save().register_presave(save_prepost_delegate(FUNC(m68k_presave), this));
	923	machine().save().register_postload(save_prepost_delegate(FUNC(m68k_postload), this));
	924
	925	m_icountptr = &remaining_cycles;
	926	remaining_cycles = 0;
	927
937	928	}
938	929
939		/* Pulse the RESET line on the CPU */
940		static CPU_RESET( m68k )
	930	void m68000_base_device::reset_cpu(void)
941	931	{
942		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
943
944	932	/* Disable the PMMU/HMMU on reset, if any */
945		m68k->pmmu_enabled = 0;
946		m68k->hmmu_enabled = 0;
	933	pmmu_enabled = 0;
	934	hmmu_enabled = 0;
947	935
948		m68k->mmu_tc = 0;
949		m68k->mmu_tt0 = 0;
950		m68k->mmu_tt1 = 0;
	936	mmu_tc = 0;
	937	mmu_tt0 = 0;
	938	mmu_tt1 = 0;
951	939
952	940	/* Clear all stop levels and eat up all remaining cycles */
953		m68k->stopped = 0;
954		if (m68k->remaining_cycles > 0)
955		m68k->remaining_cycles = 0;
	941	stopped = 0;
	942	if (remaining_cycles > 0)
	943	remaining_cycles = 0;
956	944
957		~~m68k->~~run_mode = RUN_MODE_BERR_AERR_RESET;
	945	run_mode = RUN_MODE_BERR_AERR_RESET;
958	946
959	947	/* Turn off tracing */
960		m68k->t1_flag = m68k->t0_flag = 0;
961		m68ki_clear_trace(m68k);
	948	t1_flag = t0_flag = 0;
	949	m68ki_clear_trace(this);
962	950	/* Interrupt mask to level 7 */
963		m68k->int_mask = 0x0700;
964		m68k->int_level = 0;
965		m68k->virq_state = 0;
	951	int_mask = 0x0700;
	952	int_level = 0;
	953	virq_state = 0;
966	954	/* Reset VBR */
967		~~m68k->~~vbr = 0;
	955	vbr = 0;
968	956	/* Go to supervisor mode */
969		m68ki_set_sm_flag(~~m68k~~, SFLAG_SET \| MFLAG_CLEAR);
	957	m68ki_set_sm_flag(this, SFLAG_SET \| MFLAG_CLEAR);
970	958
971	959	/* Invalidate the prefetch queue */
972	960	/* Set to arbitrary number since our first fetch is from 0 */
973		~~m68k->~~pref_addr = 0x1000;
	961	pref_addr = 0x1000;
974	962
975	963	/* Read the initial stack pointer and program counter */
976		m68ki_jump(m68k, 0);
977		REG_SP(m68k) = m68ki_read_imm_32(m68k);
978		REG_PC(m68k) = m68ki_read_imm_32(m68k);
979		m68ki_jump(m68k, REG_PC(m68k));
	964	m68ki_jump(this, 0);
	965	REG_SP(this) = m68ki_read_imm_32(this);
	966	REG_PC(this) = m68ki_read_imm_32(this);
	967	m68ki_jump(this, REG_PC(this));
980	968
981		~~m68k->~~run_mode = RUN_MODE_NORMAL;
	969	run_mode = RUN_MODE_NORMAL;
982	970
983		~~m68k->~~reset_cycles = ~~m68k->~~cyc_exception[EXCEPTION_RESET];
	971	reset_cycles = cyc_exception[EXCEPTION_RESET];
984	972
985	973	/* flush the MMU's cache */
986		pmmu_atc_flush(~~m68k~~);
	974	pmmu_atc_flush(this);
987	975
988		if(CPU_TYPE_IS_EC020_PLUS(~~m68k->~~cpu_type))
	976	if(CPU_TYPE_IS_EC020_PLUS(cpu_type))
989	977	{
990	978	// clear instruction cache
991		m68ki_ic_clear(~~m68k~~);
	979	m68ki_ic_clear(this);
992	980	}
993	981
994	982	// disable instruction hook
995		~~m68k->~~instruction_hook = NULL;
	983	instruction_hook = NULL;
996	984
997		if (m68k->m68307SIM) m68k->m68307SIM->reset();
998		if (m68k->m68307MBUS) m68k->m68307MBUS->reset();
999		if (m68k->m68307SERIAL) m68k->m68307SERIAL->reset();
1000		if (m68k->m68307TIMER) m68k->m68307TIMER->reset();
	985	if (m68307SIM) m68307SIM->reset();
	986	if (m68307MBUS) m68307MBUS->reset();
	987	if (m68307SERIAL) m68307SERIAL->reset();
	988	if (m68307TIMER) m68307TIMER->reset();
1001	989
1002		m68k->m68307_base = 0xbfff;
1003		m68k->m68307_scrhigh = 0x0007;
1004		m68k->m68307_scrlow = 0xf010;
1005
1006
	990	m68307_base = 0xbfff;
	991	m68307_scrhigh = 0x0007;
	992	m68307_scrlow = 0xf010;
1007	993	}
1008	994
1009		static CPU_DISASSEMBLE( m68k )
1010		{
1011		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
1012		return m68k_disassemble_raw(buffer, pc, oprom, opram, m68k->dasm_type);
1013		}
1014	995
1015	996
1016
1017	997	/**************************************************************************
1018	998	* STATE IMPORT/EXPORT
1019	999	**************************************************************************/
1020	1000
1021		static ~~CPU~~_~~IMPORT~~_~~STATE(~~ ~~m68k~~ )
	1001	void m68000_base_device::state_import(const device_state_entry &entry)
1022	1002	{
1023		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
1024
1025	1003	switch (entry.index())
1026	1004	{
1027	1005	case M68K_SR:
1028	1006	case STATE_GENFLAGS:
1029		m68ki_set_sr(~~m68k~~, ~~m68k->~~iotemp);
	1007	m68ki_set_sr(this, iotemp);
1030	1008	break;
1031	1009
1032	1010	case M68K_ISP:
1033		if (m68k->s_flag && !m68k->m_flag)
1034		REG_SP(m68k) = m68k->iotemp;
	1011	if (s_flag && !m_flag)
	1012	REG_SP(this) = iotemp;
1035	1013	else
1036		REG_ISP(~~m68k~~) = ~~m68k->~~iotemp;
	1014	REG_ISP(this) = iotemp;
1037	1015	break;
1038	1016
1039	1017	case M68K_USP:
1040		if (!m68k->s_flag)
1041		REG_SP(m68k) = m68k->iotemp;
	1018	if (!s_flag)
	1019	REG_SP(this) = iotemp;
1042	1020	else
1043		REG_USP(~~m68k~~) = ~~m68k->~~iotemp;
	1021	REG_USP(this) = iotemp;
1044	1022	break;
1045	1023
1046	1024	case M68K_MSP:
1047		if (m68k->s_flag && m68k->m_flag)
1048		REG_SP(m68k) = m68k->iotemp;
	1025	if (s_flag && m_flag)
	1026	REG_SP(this) = iotemp;
1049	1027	else
1050		REG_MSP(~~m68k~~) = ~~m68k->~~iotemp;
	1028	REG_MSP(this) = iotemp;
1051	1029	break;
1052	1030
1053	1031	default:
1054		fatalerror("CPU_IMPORT_STATE(~~m68k~~) called for unexpected value\n");
	1032	fatalerror("CPU_IMPORT_STATE(this) called for unexpected value\n");
1055	1033	break;
1056	1034	}
	1035
1057	1036	}
1058	1037
1059	1038
1060		static CPU_EXPORT_STATE( m68k )
	1039
	1040	void m68000_base_device::state_export(const device_state_entry &entry)
1061	1041	{
1062		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
1063
1064	1042	switch (entry.index())
1065	1043	{
1066	1044	case M68K_SR:
1067	1045	case STATE_GENFLAGS:
1068		~~m68k->~~iotemp = m68ki_get_sr(~~m68k~~);
	1046	iotemp = m68ki_get_sr(this);
1069	1047	break;
1070	1048
1071	1049	case M68K_ISP:
1072		~~m68k->~~iotemp = (~~m68k->~~s_flag && !m~~68k->m~~_flag) ? REG_SP(~~m68k~~) : REG_ISP(~~m68k~~);
	1050	iotemp = (s_flag && !m_flag) ? REG_SP(this) : REG_ISP(this);
1073	1051	break;
1074	1052
1075	1053	case M68K_USP:
1076		~~m68k->~~iotemp = (!~~m68k->~~s_flag) ? REG_SP(~~m68k~~) : REG_USP(~~m68k~~);
	1054	iotemp = (!s_flag) ? REG_SP(this) : REG_USP(this);
1077	1055	break;
1078	1056
1079	1057	case M68K_MSP:
1080		~~m68k->~~iotemp = (~~m68k->~~s_flag && m~~68k->m~~_flag) ? REG_SP(~~m68k~~) : REG_MSP(~~m68k~~);
	1058	iotemp = (s_flag && m_flag) ? REG_SP(this) : REG_MSP(this);
1081	1059	break;
1082	1060
1083	1061	case M68K_FP0:
r23920	r23921
1091	1069	break;
1092	1070
1093	1071	default:
1094		fatalerror("CPU_EXPORT_STATE(~~m68k~~) called for unexpected value\n");
	1072	fatalerror("CPU_EXPORT_STATE(this) called for unexpected value\n");
1095	1073	break;
1096	1074	}
1097	1075	}
1098	1076
1099		static ~~CPU~~_~~SET~~_~~INFO(~~ ~~m68k~~ )
	1077	void m68000_base_device::state_string_export(const device_state_entry &entry, astring &string)
1100	1078	{
1101		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
1102		switch (state)
1103		{
1104		/* --- the following bits of info are set as 64-bit signed integers --- */
1105		case CPUINFO_INT_INPUT_STATE + 0:
1106		case CPUINFO_INT_INPUT_STATE + 1:
1107		case CPUINFO_INT_INPUT_STATE + 2:
1108		case CPUINFO_INT_INPUT_STATE + 3:
1109		case CPUINFO_INT_INPUT_STATE + 4:
1110		case CPUINFO_INT_INPUT_STATE + 5:
1111		case CPUINFO_INT_INPUT_STATE + 6:
1112		case CPUINFO_INT_INPUT_STATE + 7:
1113		case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI:
1114		set_irq_line(m68k, state - CPUINFO_INT_INPUT_STATE, info->i);
1115		break;
1116
1117		case CPUINFO_INT_INPUT_STATE + M68K_LINE_BUSERROR:
1118		if (info->i == ASSERT_LINE)
1119		{
1120		m68k_cause_bus_error(m68k);
1121		}
1122		break;
1123		}
1124		}
1125
1126		static CPU_EXPORT_STRING( m68k )
1127		{
1128		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
1129	1079	UINT16 sr;
1130	1080
1131	1081	switch (entry.index())
1132	1082	{
1133	1083	case M68K_FP0:
1134		string.printf("%f", fx80_to_double(REG_FP(~~m68k~~)[0]));
	1084	string.printf("%f", fx80_to_double(REG_FP(this)[0]));
1135	1085	break;
1136	1086
1137	1087	case M68K_FP1:
1138		string.printf("%f", fx80_to_double(REG_FP(~~m68k~~)[1]));
	1088	string.printf("%f", fx80_to_double(REG_FP(this)[1]));
1139	1089	break;
1140	1090
1141	1091	case M68K_FP2:
1142		string.printf("%f", fx80_to_double(REG_FP(~~m68k~~)[2]));
	1092	string.printf("%f", fx80_to_double(REG_FP(this)[2]));
1143	1093	break;
1144	1094
1145	1095	case M68K_FP3:
1146		string.printf("%f", fx80_to_double(REG_FP(~~m68k~~)[3]));
	1096	string.printf("%f", fx80_to_double(REG_FP(this)[3]));
1147	1097	break;
1148	1098
1149	1099	case M68K_FP4:
1150		string.printf("%f", fx80_to_double(REG_FP(~~m68k~~)[4]));
	1100	string.printf("%f", fx80_to_double(REG_FP(this)[4]));
1151	1101	break;
1152	1102
1153	1103	case M68K_FP5:
1154		string.printf("%f", fx80_to_double(REG_FP(~~m68k~~)[5]));
	1104	string.printf("%f", fx80_to_double(REG_FP(this)[5]));
1155	1105	break;
1156	1106
1157	1107	case M68K_FP6:
1158		string.printf("%f", fx80_to_double(REG_FP(~~m68k~~)[6]));
	1108	string.printf("%f", fx80_to_double(REG_FP(this)[6]));
1159	1109	break;
1160	1110
1161	1111	case M68K_FP7:
1162		string.printf("%f", fx80_to_double(REG_FP(~~m68k~~)[7]));
	1112	string.printf("%f", fx80_to_double(REG_FP(this)[7]));
1163	1113	break;
1164	1114
1165	1115	case STATE_GENFLAGS:
1166		sr = m68ki_get_sr(~~m68k~~);
	1116	sr = m68ki_get_sr(this);
1167	1117	string.printf("%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
1168	1118	sr & 0x8000 ? 'T':'.',
1169	1119	sr & 0x4000 ? 't':'.',
r23920	r23921
1183	1133	sr & 0x0001 ? 'C':'.');
1184	1134	break;
1185	1135	}
1186		}
1187	1136
1188		static CPU_GET_INFO( m68k )
1189		{
1190		m68ki_cpu_core *m68k = (device != NULL && device->token() != NULL) ? m68k_get_safe_token(device) : NULL;
1191
1192		switch (state)
1193		{
1194		/* --- the following bits of info are returned as 64-bit signed integers --- */
1195		case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(m68ki_cpu_core); break;
1196		case CPUINFO_INT_INPUT_LINES: info->i = 8; break;
1197		case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = -1; break;
1198		case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
1199		case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
1200		case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
1201		case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break;
1202		case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 10; break;
1203		case CPUINFO_INT_MIN_CYCLES: info->i = 4; break;
1204		case CPUINFO_INT_MAX_CYCLES: info->i = 158; break;
1205
1206		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 16; break;
1207		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break;
1208		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
1209
1210		case CPUINFO_INT_INPUT_STATE + 0: info->i = 0; /* there is no level 0 */ break;
1211		case CPUINFO_INT_INPUT_STATE + 1: info->i = (m68k->virq_state >> 1) & 1; break;
1212		case CPUINFO_INT_INPUT_STATE + 2: info->i = (m68k->virq_state >> 2) & 1; break;
1213		case CPUINFO_INT_INPUT_STATE + 3: info->i = (m68k->virq_state >> 3) & 1; break;
1214		case CPUINFO_INT_INPUT_STATE + 4: info->i = (m68k->virq_state >> 4) & 1; break;
1215		case CPUINFO_INT_INPUT_STATE + 5: info->i = (m68k->virq_state >> 5) & 1; break;
1216		case CPUINFO_INT_INPUT_STATE + 6: info->i = (m68k->virq_state >> 6) & 1; break;
1217		case CPUINFO_INT_INPUT_STATE + 7: info->i = (m68k->virq_state >> 7) & 1; break;
1218
1219		/* --- the following bits of info are returned as pointers to functions --- */
1220		case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(m68k); break;
1221		case CPUINFO_FCT_INIT: /* set per-core */ break;
1222		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(m68k); break;
1223		case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(m68k); break;
1224		case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(m68k); break;
1225		case CPUINFO_FCT_IMPORT_STATE: info->import_state = CPU_IMPORT_STATE_NAME(m68k); break;
1226		case CPUINFO_FCT_EXPORT_STATE: info->export_state = CPU_EXPORT_STATE_NAME(m68k); break;
1227		case CPUINFO_FCT_EXPORT_STRING: info->export_string = CPU_EXPORT_STRING_NAME(m68k); break;
1228		case CPUINFO_FCT_TRANSLATE: info->translate = CPU_TRANSLATE_NAME(m68k); break;
1229
1230		/* --- the following bits of info are returned as pointers --- */
1231		case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &m68k->remaining_cycles; break;
1232
1233		/* --- the following bits of info are returned as NULL-terminated strings --- */
1234		case CPUINFO_STR_NAME: /* set per-core */ break;
1235		case CPUINFO_STR_FAMILY: strcpy(info->s, "Motorola 68K"); break;
1236		case CPUINFO_STR_VERSION: strcpy(info->s, "4.95"); break;
1237		case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
1238		case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Karl Stenerud. All rights reserved. (2.1 fixes HJB, FPU+MMU by RB+HO+OG)"); break;
1239		}
1240	1137	}
1241	1138
1242	1139
1243	1140	/* global access */
1244	1141
1245		void m68k_set_encrypted_opcode_range(device_t *device, offs_t start, offs_t end)
	1142	void m68k_set_encrypted_opcode_range(m68000_base_device *device, offs_t start, offs_t end)
1246	1143	{
1247		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
1248		m68k->encrypted_start = start;
1249		m68k->encrypted_end = end;
	1144	device->encrypted_start = start;
	1145	device->encrypted_end = end;
1250	1146	}
1251	1147
1252		void m68k_set_hmmu_enable(device_t *device, int enable)
	1148	void m68k_set_hmmu_enable(m68000_base_device *device, int enable)
1253	1149	{
1254		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
1255
1256		m68k->hmmu_enabled = enable;
	1150	device->hmmu_enabled = enable;
1257	1151	}
1258	1152
1259		void m68k_set_instruction_hook(device_t *device, instruction_hook_t ihook)
	1153	void m68k_set_instruction_hook(m68000_base_device *device, instruction_hook_t ihook)
1260	1154	{
1261		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
1262
1263		m68k->instruction_hook = ihook;
	1155	device->instruction_hook = ihook;
1264	1156	}
1265	1157
1266	1158	/****************************************************************************
1267	1159	* 8-bit data memory interface
1268	1160	****************************************************************************/
1269	1161
1270		UINT16 m68k_me~~mory~~_~~int~~e~~rfa~~ce::m68008_read_immediate_16(offs_t address)
	1162	UINT16 m68000_base_device::m68008_read_immediate_16(offs_t address)
1271	1163	{
1272	1164	return (m_direct->read_decrypted_byte(address) << 8) \| (m_direct->read_decrypted_byte(address + 1));
1273	1165	}
1274	1166
1275		void m68k_me~~mory~~_~~int~~e~~rfa~~ce::init8(address_space &space)
	1167	void m68000_base_device::init8(address_space &space)
1276	1168	{
1277	1169	m_space = &space;
1278	1170	m_direct = &space.direct();
1279		m_cpustate = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	1171	// m_cpustate = this;
1280	1172	opcode_xor = 0;
1281	1173
1282		readimm16 = m68k_readimm16_delegate(FUNC(m68k_me~~mory~~_~~int~~e~~rfa~~ce::m68008_read_immediate_16), this);
	1174	readimm16 = m68k_readimm16_delegate(FUNC(m68000_base_device::m68008_read_immediate_16), this);
1283	1175	read8 = m68k_read8_delegate(FUNC(address_space::read_byte), &space);
1284	1176	read16 = m68k_read16_delegate(FUNC(address_space::read_word), &space);
1285	1177	read32 = m68k_read32_delegate(FUNC(address_space::read_dword), &space);
r23920	r23921
1292	1184	* 16-bit data memory interface
1293	1185	****************************************************************************/
1294	1186
1295		UINT16 m68k_me~~mory~~_~~int~~e~~rfa~~ce::read_immediate_16(offs_t address)
	1187	UINT16 m68000_base_device::read_immediate_16(offs_t address)
1296	1188	{
1297	1189	return m_direct->read_decrypted_word((address), opcode_xor);
1298	1190	}
1299	1191
1300		UINT16 m68k_me~~mory~~_~~int~~e~~rfa~~ce::simple_read_immediate_16(offs_t address)
	1192	UINT16 m68000_base_device::simple_read_immediate_16(offs_t address)
1301	1193	{
1302	1194	return m_direct->read_decrypted_word(address);
1303	1195	}
1304	1196
1305		void m68k_me~~mory~~_~~int~~e~~rfa~~ce::init16(address_space &space)
	1197	void m68000_base_device::init16(address_space &space)
1306	1198	{
1307	1199	m_space = &space;
1308	1200	m_direct = &space.direct();
1309		m_cpustate = m68k_get_safe_token(&space.device());
1310	1201	opcode_xor = 0;
1311	1202
1312		readimm16 = m68k_readimm16_delegate(FUNC(m68k_me~~mory~~_~~int~~e~~rfa~~ce::simple_read_immediate_16), this);
	1203	readimm16 = m68k_readimm16_delegate(FUNC(m68000_base_device::simple_read_immediate_16), this);
1313	1204	read8 = m68k_read8_delegate(FUNC(address_space::read_byte), &space);
1314	1205	read16 = m68k_read16_delegate(FUNC(address_space::read_word), &space);
1315	1206	read32 = m68k_read32_delegate(FUNC(address_space::read_dword), &space);
r23920	r23921
1322	1213	and install handlers? Going through this logic for every memory access is
1323	1214	very slow */
1324	1215
1325		int m68307_calc_cs(m68ki_~~cpu~~_core *m68k, offs_t address)
	1216	int m68307_calc_cs(m68000_base_device *m68k, offs_t address)
1326	1217	{
1327	1218	m68307_sim* sim = m68k->m68307SIM;
1328	1219
r23920	r23921
1339	1230
1340	1231	/* see note above */
1341	1232
1342		int m68340_calc_cs(m68ki_~~cpu~~_core *m68k, offs_t address)
	1233	int m68340_calc_cs(m68000_base_device *m68k, offs_t address)
1343	1234	{
1344	1235	m68340_sim* sim = m68k->m68340SIM;
1345	1236
r23920	r23921
1365	1256
1366	1257
1367	1258
1368		UINT16 m68k_me~~mory~~_~~int~~e~~rfa~~ce::simple_read_immediate_16_m68307(offs_t address)
	1259	UINT16 m68000_base_device::simple_read_immediate_16_m68307(offs_t address)
1369	1260	{
1370		// m~~_cpustate->m~~68307_currentcs = m68307_calc_cs(~~m_cpus~~t~~ate~~, address);
	1261	// m68307_currentcs = m68307_calc_cs(this, address);
1371	1262	return m_direct->read_decrypted_word(address);
1372	1263	}
1373	1264
1374		UINT8 m68k_me~~mory~~_~~int~~e~~rfa~~ce::read_byte_m68307(offs_t address)
	1265	UINT8 m68000_base_device::read_byte_m68307(offs_t address)
1375	1266	{
1376		// m~~_cpustate->m~~68307_currentcs = m68307_calc_cs(~~m_cpus~~t~~ate~~, address);
	1267	// m68307_currentcs = m68307_calc_cs(this, address);
1377	1268	return m_space->read_byte(address);
1378	1269	}
1379	1270
1380		UINT16 m68k_me~~mory~~_~~int~~e~~rfa~~ce::read_word_m68307(offs_t address)
	1271	UINT16 m68000_base_device::read_word_m68307(offs_t address)
1381	1272	{
1382		// m~~_cpustate->m~~68307_currentcs = m68307_calc_cs(~~m_cpus~~t~~ate~~, address);
	1273	// m68307_currentcs = m68307_calc_cs(this, address);
1383	1274	return m_space->read_word(address);
1384	1275	}
1385	1276
1386		UINT32 m68k_me~~mory~~_~~int~~e~~rfa~~ce::read_dword_m68307(offs_t address)
	1277	UINT32 m68000_base_device::read_dword_m68307(offs_t address)
1387	1278	{
1388		// m~~_cpustate->m~~68307_currentcs = m68307_calc_cs(~~m_cpus~~t~~ate~~, address);
	1279	// m68307_currentcs = m68307_calc_cs(this, address);
1389	1280	return m_space->read_dword(address);
1390	1281	}
1391	1282
1392		void m68k_me~~mory~~_~~int~~e~~rfa~~ce::write_byte_m68307(offs_t address, UINT8 data)
	1283	void m68000_base_device::write_byte_m68307(offs_t address, UINT8 data)
1393	1284	{
1394		// m~~_cpustate->m~~68307_currentcs = m68307_calc_cs(~~m_cpus~~t~~ate~~, address);
	1285	// m68307_currentcs = m68307_calc_cs(this, address);
1395	1286	m_space->write_byte(address, data);
1396	1287	}
1397	1288
1398		void m68k_me~~mory~~_~~int~~e~~rfa~~ce::write_word_m68307(offs_t address, UINT16 data)
	1289	void m68000_base_device::write_word_m68307(offs_t address, UINT16 data)
1399	1290	{
1400		// m~~_cpustate->m~~68307_currentcs = m68307_calc_cs(~~m_cpus~~t~~ate~~, address);
	1291	// m68307_currentcs = m68307_calc_cs(this, address);
1401	1292	m_space->write_word(address, data);
1402	1293	}
1403	1294
1404		void m68k_me~~mory~~_~~int~~e~~rfa~~ce::write_dword_m68307(offs_t address, UINT32 data)
	1295	void m68000_base_device::write_dword_m68307(offs_t address, UINT32 data)
1405	1296	{
1406		// m~~_cpustate->m~~68307_currentcs = m68307_calc_cs(~~m_cpus~~t~~ate~~, address);
	1297	// m68307_currentcs = m68307_calc_cs(this, address);
1407	1298	m_space->write_dword(address, data);
1408	1299	}
1409	1300
1410	1301
1411	1302
1412	1303
1413		void m68k_me~~mory~~_~~int~~e~~rfa~~ce::init16_m68307(address_space &space)
	1304	void m68000_base_device::init16_m68307(address_space &space)
1414	1305	{
1415	1306	m_space = &space;
1416	1307	m_direct = &space.direct();
1417		m_cpustate = m68k_get_safe_token(&space.device());
1418	1308	opcode_xor = 0;
1419	1309
1420		readimm16 = m68k_readimm16_delegate(FUNC(m68k_memory_interface::simple_read_immediate_16_m68307), this);
1421		read8 = m68k_read8_delegate(FUNC(m68k_memory_interface::read_byte_m68307), this);
1422		read16 = m68k_read16_delegate(FUNC(m68k_memory_interface::read_word_m68307), this);
1423		read32 = m68k_read32_delegate(FUNC(m68k_memory_interface::read_dword_m68307), this);
1424		write8 = m68k_write8_delegate(FUNC(m68k_memory_interface::write_byte_m68307), this);
1425		write16 = m68k_write16_delegate(FUNC(m68k_memory_interface::write_word_m68307), this);
1426		write32 = m68k_write32_delegate(FUNC(m68k_memory_interface::write_dword_m68307), this);
	1310	readimm16 = m68k_readimm16_delegate(FUNC(m68000_base_device::simple_read_immediate_16_m68307), this);
	1311	read8 = m68k_read8_delegate(FUNC(m68000_base_device::read_byte_m68307), this);
	1312	read16 = m68k_read16_delegate(FUNC(m68000_base_device::read_word_m68307), this);
	1313	read32 = m68k_read32_delegate(FUNC(m68000_base_device::read_dword_m68307), this);
	1314	write8 = m68k_write8_delegate(FUNC(m68000_base_device::write_byte_m68307), this);
	1315	write16 = m68k_write16_delegate(FUNC(m68000_base_device::write_word_m68307), this);
	1316	write32 = m68k_write32_delegate(FUNC(m68000_base_device::write_dword_m68307), this);
1427	1317	}
1428	1318
1429	1319	/****************************************************************************
r23920	r23921
1431	1321	****************************************************************************/
1432	1322
1433	1323	/* interface for 32-bit data bus (68EC020, 68020) */
1434		void m68k_me~~mory~~_~~int~~e~~rfa~~ce::init32(address_space &space)
	1324	void m68000_base_device::init32(address_space &space)
1435	1325	{
1436	1326	m_space = &space;
1437	1327	m_direct = &space.direct();
1438		m_cpustate = m68k_get_safe_token(&space.device());
1439	1328	opcode_xor = WORD_XOR_BE(0);
1440	1329
1441		readimm16 = m68k_readimm16_delegate(FUNC(m68k_me~~mory~~_~~int~~e~~rfa~~ce::read_immediate_16), this);
	1330	readimm16 = m68k_readimm16_delegate(FUNC(m68000_base_device::read_immediate_16), this);
1442	1331	read8 = m68k_read8_delegate(FUNC(address_space::read_byte), &space);
1443	1332	read16 = m68k_read16_delegate(FUNC(address_space::read_word_unaligned), &space);
1444	1333	read32 = m68k_read32_delegate(FUNC(address_space::read_dword_unaligned), &space);
r23920	r23921
1448	1337	}
1449	1338
1450	1339	/* interface for 32-bit data bus with PMMU (68EC020, 68020) */
1451		UINT8 m68k_me~~mory~~_~~int~~e~~rfa~~ce::read_byte_32_mmu(offs_t address)
	1340	UINT8 m68000_base_device::read_byte_32_mmu(offs_t address)
1452	1341	{
1453		if (~~m_cpustate->~~pmmu_enabled)
	1342	if (pmmu_enabled)
1454	1343	{
1455		address = pmmu_translate_addr(m_cpustate, address);
1456		if (m_cpustate->mmu_tmp_buserror_occurred) {
	1344	address = pmmu_translate_addr(this, address);
	1345	if (mmu_tmp_buserror_occurred) {
1457	1346	return ~0;
1458	1347	}
1459	1348	}
r23920	r23921
1461	1350	return m_space->read_byte(address);
1462	1351	}
1463	1352
1464		void m68k_me~~mory~~_~~int~~e~~rfa~~ce::write_byte_32_mmu(offs_t address, UINT8 data)
	1353	void m68000_base_device::write_byte_32_mmu(offs_t address, UINT8 data)
1465	1354	{
1466		if (~~m_cpustate->~~pmmu_enabled)
	1355	if (pmmu_enabled)
1467	1356	{
1468		address = pmmu_translate_addr(m_cpustate, address);
1469		if (m_cpustate->mmu_tmp_buserror_occurred) {
	1357	address = pmmu_translate_addr(this, address);
	1358	if (mmu_tmp_buserror_occurred) {
1470	1359	return;
1471	1360	}
1472	1361	}
r23920	r23921
1474	1363	m_space->write_byte(address, data);
1475	1364	}
1476	1365
1477		UINT16 m68k_me~~mory~~_~~int~~e~~rfa~~ce::read_immediate_16_mmu(offs_t address)
	1366	UINT16 m68000_base_device::read_immediate_16_mmu(offs_t address)
1478	1367	{
1479		if (~~m_cpustate->~~pmmu_enabled)
	1368	if (pmmu_enabled)
1480	1369	{
1481		address = pmmu_translate_addr(m_cpustate, address);
1482		if (m_cpustate->mmu_tmp_buserror_occurred) {
	1370	address = pmmu_translate_addr(this, address);
	1371	if (mmu_tmp_buserror_occurred) {
1483	1372	return ~0;
1484	1373	}
1485	1374	}
1486	1375
1487		return m_direct->read_decrypted_word((address), ~~m_cpustate->memory.~~opcode_xor);
	1376	return m_direct->read_decrypted_word((address), opcode_xor);
1488	1377	}
1489	1378
1490	1379	/* potentially misaligned 16-bit reads with a 32-bit data bus (and 24-bit address bus) */
1491		UINT16 m68k_me~~mory~~_~~int~~e~~rfa~~ce::readword_d32_mmu(offs_t address)
	1380	UINT16 m68000_base_device::readword_d32_mmu(offs_t address)
1492	1381	{
1493	1382	UINT16 result;
1494	1383
1495		if (~~m_cpustate->~~pmmu_enabled)
	1384	if (pmmu_enabled)
1496	1385	{
1497		UINT32 address0 = pmmu_translate_addr(m_cpustate, address);
1498		if (m_cpustate->mmu_tmp_buserror_occurred) {
	1386	UINT32 address0 = pmmu_translate_addr(this, address);
	1387	if (mmu_tmp_buserror_occurred) {
1499	1388	return ~0;
1500	1389	} else if (!(address & 1)) {
1501	1390	return m_space->read_word(address0);
1502	1391	} else {
1503		UINT32 address1 = pmmu_translate_addr(m_cpustate, address + 1);
1504		if (m_cpustate->mmu_tmp_buserror_occurred) {
	1392	UINT32 address1 = pmmu_translate_addr(this, address + 1);
	1393	if (mmu_tmp_buserror_occurred) {
1505	1394	return ~0;
1506	1395	} else {
1507	1396	result = m_space->read_byte(address0) << 8;
r23920	r23921
1517	1406	}
1518	1407
1519	1408	/* potentially misaligned 16-bit writes with a 32-bit data bus (and 24-bit address bus) */
1520		void m68k_me~~mory~~_~~int~~e~~rfa~~ce::writeword_d32_mmu(offs_t address, UINT16 data)
	1409	void m68000_base_device::writeword_d32_mmu(offs_t address, UINT16 data)
1521	1410	{
1522		if (~~m_cpustate->~~pmmu_enabled)
	1411	if (pmmu_enabled)
1523	1412	{
1524		UINT32 address0 = pmmu_translate_addr(m_cpustate, address);
1525		if (m_cpustate->mmu_tmp_buserror_occurred) {
	1413	UINT32 address0 = pmmu_translate_addr(this, address);
	1414	if (mmu_tmp_buserror_occurred) {
1526	1415	return;
1527	1416	} else if (!(address & 1)) {
1528	1417	m_space->write_word(address0, data);
1529	1418	return;
1530	1419	} else {
1531		UINT32 address1 = pmmu_translate_addr(m_cpustate, address + 1);
1532		if (m_cpustate->mmu_tmp_buserror_occurred) {
	1420	UINT32 address1 = pmmu_translate_addr(this, address + 1);
	1421	if (mmu_tmp_buserror_occurred) {
1533	1422	return;
1534	1423	} else {
1535	1424	m_space->write_byte(address0, data >> 8);
r23920	r23921
1549	1438	}
1550	1439
1551	1440	/* potentially misaligned 32-bit reads with a 32-bit data bus (and 24-bit address bus) */
1552		UINT32 m68k_me~~mory~~_~~int~~e~~rfa~~ce::readlong_d32_mmu(offs_t address)
	1441	UINT32 m68000_base_device::readlong_d32_mmu(offs_t address)
1553	1442	{
1554	1443	UINT32 result;
1555	1444
1556		if (~~m_cpustate->~~pmmu_enabled)
	1445	if (pmmu_enabled)
1557	1446	{
1558		UINT32 address0 = pmmu_translate_addr(m_cpustate, address);
1559		if (m_cpustate->mmu_tmp_buserror_occurred) {
	1447	UINT32 address0 = pmmu_translate_addr(this, address);
	1448	if (mmu_tmp_buserror_occurred) {
1560	1449	return ~0;
1561	1450	} else if ((address +3) & 0xfc) {
1562	1451	// not at page boundary; use default code
r23920	r23921
1564	1453	} else if (!(address & 3)) { // 0
1565	1454	return m_space->read_dword(address0);
1566	1455	} else {
1567		UINT32 address2 = pmmu_translate_addr(m_cpustate, address+2);
1568		if (m_cpustate->mmu_tmp_buserror_occurred) {
	1456	UINT32 address2 = pmmu_translate_addr(this, address+2);
	1457	if (mmu_tmp_buserror_occurred) {
1569	1458	return ~0;
1570	1459	} else if (!(address & 1)) { // 2
1571	1460	result = m_space->read_word(address0) << 16;
1572	1461	return result \| m_space->read_word(address2);
1573	1462	} else {
1574		UINT32 address1 = pmmu_translate_addr(m_cpustate, address+1);
1575		UINT32 address3 = pmmu_translate_addr(m_cpustate, address+3);
1576		if (m_cpustate->mmu_tmp_buserror_occurred) {
	1463	UINT32 address1 = pmmu_translate_addr(this, address+1);
	1464	UINT32 address3 = pmmu_translate_addr(this, address+3);
	1465	if (mmu_tmp_buserror_occurred) {
1577	1466	return ~0;
1578	1467	} else {
1579	1468	result = m_space->read_byte(address0) << 24;
r23920	r23921
1597	1486	}
1598	1487
1599	1488	/* potentially misaligned 32-bit writes with a 32-bit data bus (and 24-bit address bus) */
1600		void m68k_me~~mory~~_~~int~~e~~rfa~~ce::writelong_d32_mmu(offs_t address, UINT32 data)
	1489	void m68000_base_device::writelong_d32_mmu(offs_t address, UINT32 data)
1601	1490	{
1602		if (~~m_cpustate->~~pmmu_enabled)
	1491	if (pmmu_enabled)
1603	1492	{
1604		UINT32 address0 = pmmu_translate_addr(m_cpustate, address);
1605		if (m_cpustate->mmu_tmp_buserror_occurred) {
	1493	UINT32 address0 = pmmu_translate_addr(this, address);
	1494	if (mmu_tmp_buserror_occurred) {
1606	1495	return;
1607	1496	} else if ((address +3) & 0xfc) {
1608	1497	// not at page boundary; use default code
r23920	r23921
1611	1500	m_space->write_dword(address0, data);
1612	1501	return;
1613	1502	} else {
1614		UINT32 address2 = pmmu_translate_addr(m_cpustate, address+2);
1615		if (m_cpustate->mmu_tmp_buserror_occurred) {
	1503	UINT32 address2 = pmmu_translate_addr(this, address+2);
	1504	if (mmu_tmp_buserror_occurred) {
1616	1505	return;
1617	1506	} else if (!(address & 1)) { // 2
1618	1507	m_space->write_word(address0, data >> 16);
1619	1508	m_space->write_word(address2, data);
1620	1509	return;
1621	1510	} else {
1622		UINT32 address1 = pmmu_translate_addr(m_cpustate, address+1);
1623		UINT32 address3 = pmmu_translate_addr(m_cpustate, address+3);
1624		if (m_cpustate->mmu_tmp_buserror_occurred) {
	1511	UINT32 address1 = pmmu_translate_addr(this, address+1);
	1512	UINT32 address3 = pmmu_translate_addr(this, address+3);
	1513	if (mmu_tmp_buserror_occurred) {
1625	1514	return;
1626	1515	} else {
1627	1516	m_space->write_byte(address0, data >> 24);
r23920	r23921
1649	1538	m_space->write_byte(address + 3, data);
1650	1539	}
1651	1540
1652		void m68k_me~~mory~~_~~int~~e~~rfa~~ce::init32mmu(address_space &space)
	1541	void m68000_base_device::init32mmu(address_space &space)
1653	1542	{
1654	1543	m_space = &space;
1655	1544	m_direct = &space.direct();
1656		m_cpustate = m68k_get_safe_token(&space.device());
1657	1545	opcode_xor = WORD_XOR_BE(0);
1658	1546
1659		readimm16 = m68k_readimm16_delegate(FUNC(m68k_memory_interface::read_immediate_16_mmu), this);
1660		read8 = m68k_read8_delegate(FUNC(m68k_memory_interface::read_byte_32_mmu), this);
1661		read16 = m68k_read16_delegate(FUNC(m68k_memory_interface::readword_d32_mmu), this);
1662		read32 = m68k_read32_delegate(FUNC(m68k_memory_interface::readlong_d32_mmu), this);
1663		write8 = m68k_write8_delegate(FUNC(m68k_memory_interface::write_byte_32_mmu), this);
1664		write16 = m68k_write16_delegate(FUNC(m68k_memory_interface::writeword_d32_mmu), this);
1665		write32 = m68k_write32_delegate(FUNC(m68k_memory_interface::writelong_d32_mmu), this);
	1547	readimm16 = m68k_readimm16_delegate(FUNC(m68000_base_device::read_immediate_16_mmu), this);
	1548	read8 = m68k_read8_delegate(FUNC(m68000_base_device::read_byte_32_mmu), this);
	1549	read16 = m68k_read16_delegate(FUNC(m68000_base_device::readword_d32_mmu), this);
	1550	read32 = m68k_read32_delegate(FUNC(m68000_base_device::readlong_d32_mmu), this);
	1551	write8 = m68k_write8_delegate(FUNC(m68000_base_device::write_byte_32_mmu), this);
	1552	write16 = m68k_write16_delegate(FUNC(m68000_base_device::writeword_d32_mmu), this);
	1553	write32 = m68k_write32_delegate(FUNC(m68000_base_device::writelong_d32_mmu), this);
1666	1554	}
1667	1555
1668	1556
1669	1557	/* interface for 32-bit data bus with PMMU (68EC020, 68020) */
1670		UINT8 m68k_me~~mory~~_~~int~~e~~rfa~~ce::read_byte_32_hmmu(offs_t address)
	1558	UINT8 m68000_base_device::read_byte_32_hmmu(offs_t address)
1671	1559	{
1672		if (~~m_cpustate->~~hmmu_enabled)
	1560	if (hmmu_enabled)
1673	1561	{
1674		address = hmmu_translate_addr(~~m_cpus~~t~~ate~~, address);
	1562	address = hmmu_translate_addr(this, address);
1675	1563	}
1676	1564
1677	1565	return m_space->read_byte(address);
1678	1566	}
1679	1567
1680		void m68k_me~~mory~~_~~int~~e~~rfa~~ce::write_byte_32_hmmu(offs_t address, UINT8 data)
	1568	void m68000_base_device::write_byte_32_hmmu(offs_t address, UINT8 data)
1681	1569	{
1682		if (~~m_cpustate->~~hmmu_enabled)
	1570	if (hmmu_enabled)
1683	1571	{
1684		address = hmmu_translate_addr(~~m_cpus~~t~~ate~~, address);
	1572	address = hmmu_translate_addr(this, address);
1685	1573	}
1686	1574
1687	1575	m_space->write_byte(address, data);
1688	1576	}
1689	1577
1690		UINT16 m68k_me~~mory~~_~~int~~e~~rfa~~ce::read_immediate_16_hmmu(offs_t address)
	1578	UINT16 m68000_base_device::read_immediate_16_hmmu(offs_t address)
1691	1579	{
1692		if (~~m_cpustate->~~hmmu_enabled)
	1580	if (hmmu_enabled)
1693	1581	{
1694		address = hmmu_translate_addr(~~m_cpus~~t~~ate~~, address);
	1582	address = hmmu_translate_addr(this, address);
1695	1583	}
1696	1584
1697		return m_direct->read_decrypted_word((address), ~~m_cpustate->memory.~~opcode_xor);
	1585	return m_direct->read_decrypted_word((address), opcode_xor);
1698	1586	}
1699	1587
1700	1588	/* potentially misaligned 16-bit reads with a 32-bit data bus (and 24-bit address bus) */
1701		UINT16 m68k_me~~mory~~_~~int~~e~~rfa~~ce::readword_d32_hmmu(offs_t address)
	1589	UINT16 m68000_base_device::readword_d32_hmmu(offs_t address)
1702	1590	{
1703	1591	UINT16 result;
1704	1592
1705		if (~~m_cpustate->~~hmmu_enabled)
	1593	if (hmmu_enabled)
1706	1594	{
1707		address = hmmu_translate_addr(~~m_cpus~~t~~ate~~, address);
	1595	address = hmmu_translate_addr(this, address);
1708	1596	}
1709	1597
1710	1598	if (!(address & 1))
r23920	r23921
1714	1602	}
1715	1603
1716	1604	/* potentially misaligned 16-bit writes with a 32-bit data bus (and 24-bit address bus) */
1717		void m68k_me~~mory~~_~~int~~e~~rfa~~ce::writeword_d32_hmmu(offs_t address, UINT16 data)
	1605	void m68000_base_device::writeword_d32_hmmu(offs_t address, UINT16 data)
1718	1606	{
1719		if (~~m_cpustate->~~hmmu_enabled)
	1607	if (hmmu_enabled)
1720	1608	{
1721		address = hmmu_translate_addr(~~m_cpus~~t~~ate~~, address);
	1609	address = hmmu_translate_addr(this, address);
1722	1610	}
1723	1611
1724	1612	if (!(address & 1))
r23920	r23921
1731	1619	}
1732	1620
1733	1621	/* potentially misaligned 32-bit reads with a 32-bit data bus (and 24-bit address bus) */
1734		UINT32 m68k_me~~mory~~_~~int~~e~~rfa~~ce::readlong_d32_hmmu(offs_t address)
	1622	UINT32 m68000_base_device::readlong_d32_hmmu(offs_t address)
1735	1623	{
1736	1624	UINT32 result;
1737	1625
1738		if (~~m_cpustate->~~hmmu_enabled)
	1626	if (hmmu_enabled)
1739	1627	{
1740		address = hmmu_translate_addr(~~m_cpus~~t~~ate~~, address);
	1628	address = hmmu_translate_addr(this, address);
1741	1629	}
1742	1630
1743	1631	if (!(address & 3))
r23920	r23921
1753	1641	}
1754	1642
1755	1643	/* potentially misaligned 32-bit writes with a 32-bit data bus (and 24-bit address bus) */
1756		void m68k_me~~mory~~_~~int~~e~~rfa~~ce::writelong_d32_hmmu(offs_t address, UINT32 data)
	1644	void m68000_base_device::writelong_d32_hmmu(offs_t address, UINT32 data)
1757	1645	{
1758		if (~~m_cpustate->~~hmmu_enabled)
	1646	if (hmmu_enabled)
1759	1647	{
1760		address = hmmu_translate_addr(~~m_cpus~~t~~ate~~, address);
	1648	address = hmmu_translate_addr(this, address);
1761	1649	}
1762	1650
1763	1651	if (!(address & 3))
r23920	r23921
1776	1664	m_space->write_byte(address + 3, data);
1777	1665	}
1778	1666
1779		void m68k_me~~mory~~_~~int~~e~~rfa~~ce::init32hmmu(address_space &space)
	1667	void m68000_base_device::init32hmmu(address_space &space)
1780	1668	{
1781	1669	m_space = &space;
1782	1670	m_direct = &space.direct();
1783		m_cpustate = m68k_get_safe_token(&space.device());
1784	1671	opcode_xor = WORD_XOR_BE(0);
1785	1672
1786		readimm16 = m68k_readimm16_delegate(FUNC(m68k_memory_interface::read_immediate_16_hmmu), this);
1787		read8 = m68k_read8_delegate(FUNC(m68k_memory_interface::read_byte_32_hmmu), this);
1788		read16 = m68k_read16_delegate(FUNC(m68k_memory_interface::readword_d32_hmmu), this);
1789		read32 = m68k_read32_delegate(FUNC(m68k_memory_interface::readlong_d32_hmmu), this);
1790		write8 = m68k_write8_delegate(FUNC(m68k_memory_interface::write_byte_32_hmmu), this);
1791		write16 = m68k_write16_delegate(FUNC(m68k_memory_interface::writeword_d32_hmmu), this);
1792		write32 = m68k_write32_delegate(FUNC(m68k_memory_interface::writelong_d32_hmmu), this);
	1673	readimm16 = m68k_readimm16_delegate(FUNC(m68000_base_device::read_immediate_16_hmmu), this);
	1674	read8 = m68k_read8_delegate(FUNC(m68000_base_device::read_byte_32_hmmu), this);
	1675	read16 = m68k_read16_delegate(FUNC(m68000_base_device::readword_d32_hmmu), this);
	1676	read32 = m68k_read32_delegate(FUNC(m68000_base_device::readlong_d32_hmmu), this);
	1677	write8 = m68k_write8_delegate(FUNC(m68000_base_device::write_byte_32_hmmu), this);
	1678	write16 = m68k_write16_delegate(FUNC(m68000_base_device::writeword_d32_hmmu), this);
	1679	write32 = m68k_write32_delegate(FUNC(m68000_base_device::writelong_d32_hmmu), this);
1793	1680	}
1794	1681
1795		void m68k_set_reset_callback(device_t *device, m68k_reset_func callback)
	1682	void m68k_set_reset_callback(m68000_base_device *device, m68k_reset_func callback)
1796	1683	{
1797		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
1798		m68k->reset_instr_callback = callback;
	1684	device->reset_instr_callback = callback;
1799	1685	}
1800	1686
1801		void m68k_set_cmpild_callback(device_t *device, m68k_cmpild_func callback)
	1687	void m68k_set_cmpild_callback(m68000_base_device *device, m68k_cmpild_func callback)
1802	1688	{
1803		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
1804		m68k->cmpild_instr_callback = callback;
	1689	device->cmpild_instr_callback = callback;
1805	1690	}
1806	1691
1807		void m68k_set_rte_callback(device_t *device, m68k_rte_func callback)
	1692	void m68k_set_rte_callback(m68000_base_device *device, m68k_rte_func callback)
1808	1693	{
1809		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
1810		m68k->rte_instr_callback = callback;
	1694	device->rte_instr_callback = callback;
1811	1695	}
1812	1696
1813		void m68k_set_tas_callback(device_t *device, m68k_tas_func callback)
	1697	void m68k_set_tas_callback(m68000_base_device *device, m68k_tas_func callback)
1814	1698	{
1815		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
1816		m68k->tas_instr_callback = callback;
	1699	device->tas_instr_callback = callback;
1817	1700	}
1818	1701
1819		UINT16 m68k_get_fc(device_t *device)
	1702	UINT16 m68k_get_fc(m68000_base_device *device)
1820	1703	{
1821		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
1822		return m68k->mmu_tmp_fc;
	1704	return device->mmu_tmp_fc;
1823	1705	}
1824	1706
1825		void m68307_set_port_callbacks(device_t *device, m68307_porta_read_callback porta_r, m68307_porta_write_callback porta_w, m68307_portb_read_callback portb_r, m68307_portb_write_callback portb_w)
	1707	void m68307_set_port_callbacks(m68000_base_device *device, m68307_porta_read_callback porta_r, m68307_porta_write_callback porta_w, m68307_portb_read_callback portb_r, m68307_portb_write_callback portb_w)
1826	1708	{
1827		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
1828		m68k->m_m68307_porta_r = porta_r;
1829		m68k->m_m68307_porta_w = porta_w;
1830		m68k->m_m68307_portb_r = portb_r;
1831		m68k->m_m68307_portb_w = portb_w;
	1709	device->m_m68307_porta_r = porta_r;
	1710	device->m_m68307_porta_w = porta_w;
	1711	device->m_m68307_portb_r = portb_r;
	1712	device->m_m68307_portb_w = portb_w;
1832	1713	}
1833	1714
1834		void m68307_set_duart68681(device_t* cpudev, device_t* duart68681)
	1715	void m68307_set_duart68681(m68000_base_device* cpudev, device_t* duart68681)
1835	1716	{
1836		m68ki_cpu_core *m68k = m68k_get_safe_token(cpudev);
1837		if (m68k->m68307SERIAL)
1838		m68k->m68307SERIAL->m68307ser_set_duart68681(duart68681);
	1717	if (cpudev->m68307SERIAL)
	1718	cpudev->m68307SERIAL->m68307ser_set_duart68681(duart68681);
1839	1719	}
1840	1720
1841	1721
1842	1722
1843	1723
1844		UINT16 m68307_get_cs(device_t *device, offs_t address)
	1724	UINT16 m68307_get_cs(m68000_base_device *device, offs_t address)
1845	1725	{
1846		m68ki_cpu~~_co~~re *m68k = m68k_~~get_s~~afe_~~token~~(device);
	1726	device->m68307_currentcs = m68307_calc_cs(device, address);
1847	1727
1848		m68k->m68307_currentcs = m68307_calc_cs(m68k, address);
1849
1850		return m68k->m68307_currentcs;
	1728	return device->m68307_currentcs;
1851	1729	}
1852	1730
1853		UINT16 m68340_get_cs(device_t *device, offs_t address)
	1731	UINT16 m68340_get_cs(m68000_base_device *device, offs_t address)
1854	1732	{
1855		m68ki_cpu~~_co~~re *m68k = m68k_~~get_s~~afe_~~token~~(device);
	1733	device->m68307_currentcs = m68340_calc_cs(device, address);
1856	1734
1857		m68k->m68307_currentcs = m68340_calc_cs(m68k, address);
1858
1859		return m68k->m68307_currentcs;
	1735	return device->m68307_currentcs;
1860	1736	}
1861	1737
1862	1738	/****************************************************************************
1863	1739	* State definition
1864	1740	****************************************************************************/
1865	1741
1866		~~static~~ void define_state(device_t *d~~evice~~)
	1742	void m68000_base_device::define_state(void)
1867	1743	{
1868		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
1869		UINT32 addrmask = (m68k->cpu_type & MASK_24BIT_SPACE) ? 0xffffff : 0xffffffff;
	1744	UINT32 addrmask = (cpu_type & MASK_24BIT_SPACE) ? 0xffffff : 0xffffffff;
1870	1745
1871		device_state_interface *state;
1872		device->interface(state);
1873		state->state_add(M68K_PC, "PC", m68k->pc).mask(addrmask);
1874		state->state_add(STATE_GENPC, "GENPC", m68k->pc).mask(addrmask).noshow();
1875		state->state_add(STATE_GENPCBASE, "GENPCBASE", m68k->ppc).mask(addrmask).noshow();
1876		state->state_add(M68K_SP, "SP", m68k->dar[15]);
1877		state->state_add(STATE_GENSP, "GENSP", m68k->dar[15]).noshow();
1878		state->state_add(STATE_GENFLAGS, "GENFLAGS", m68k->iotemp).noshow().callimport().callexport().formatstr("%16s");
1879		state->state_add(M68K_ISP, "ISP", m68k->iotemp).callimport().callexport();
1880		state->state_add(M68K_USP, "USP", m68k->iotemp).callimport().callexport();
1881		if (m68k->cpu_type & MASK_020_OR_LATER)
1882		state->state_add(M68K_MSP, "MSP", m68k->iotemp).callimport().callexport();
1883		state->state_add(M68K_ISP, "ISP", m68k->iotemp).callimport().callexport();
	1746	state_add(M68K_PC, "PC", pc).mask(addrmask);
	1747	state_add(STATE_GENPC, "GENPC", pc).mask(addrmask).noshow();
	1748	state_add(STATE_GENPCBASE, "GENPCBASE", ppc).mask(addrmask).noshow();
	1749	state_add(M68K_SP, "SP", dar[15]);
	1750	state_add(STATE_GENSP, "GENSP", dar[15]).noshow();
	1751	state_add(STATE_GENFLAGS, "GENFLAGS", iotemp).noshow().callimport().callexport().formatstr("%16s");
	1752	state_add(M68K_ISP, "ISP", iotemp).callimport().callexport();
	1753	state_add(M68K_USP, "USP", iotemp).callimport().callexport();
	1754	if (cpu_type & MASK_020_OR_LATER)
	1755	state_add(M68K_MSP, "MSP", iotemp).callimport().callexport();
	1756	state_add(M68K_ISP, "ISP", iotemp).callimport().callexport();
1884	1757
1885	1758	astring tempstr;
1886	1759	for (int regnum = 0; regnum < 8; regnum++)
1887		state~~->state~~_add(M68K_D0 + regnum, tempstr.format("D%d", regnum), ~~m68k->~~dar[regnum]);
	1760	state_add(M68K_D0 + regnum, tempstr.format("D%d", regnum), dar[regnum]);
1888	1761	for (int regnum = 0; regnum < 8; regnum++)
1889		state~~->state~~_add(M68K_A0 + regnum, tempstr.format("A%d", regnum), ~~m68k->~~dar[8 + regnum]);
	1762	state_add(M68K_A0 + regnum, tempstr.format("A%d", regnum), dar[8 + regnum]);
1890	1763
1891		state->state_add(M68K_PREF_ADDR, "PREF_ADDR", m68k->pref_addr).mask(addrmask);
1892		state->state_add(M68K_PREF_DATA, "PREF_DATA", m68k->pref_data);
	1764	state_add(M68K_PREF_ADDR, "PREF_ADDR", pref_addr).mask(addrmask);
	1765	state_add(M68K_PREF_DATA, "PREF_DATA", pref_data);
1893	1766
1894		if (~~m68k->~~cpu_type & MASK_010_OR_LATER)
	1767	if (cpu_type & MASK_010_OR_LATER)
1895	1768	{
1896		state->state_add(M68K_SFC, "SFC", m68k->sfc).mask(0x7);
1897		state->state_add(M68K_DFC, "DFC", m68k->dfc).mask(0x7);
1898		state->state_add(M68K_VBR, "VBR", m68k->vbr);
	1769	state_add(M68K_SFC, "SFC", sfc).mask(0x7);
	1770	state_add(M68K_DFC, "DFC", dfc).mask(0x7);
	1771	state_add(M68K_VBR, "VBR", vbr);
1899	1772	}
1900	1773
1901		if (~~m68k->~~cpu_type & MASK_020_OR_LATER)
	1774	if (cpu_type & MASK_020_OR_LATER)
1902	1775	{
1903		state->state_add(M68K_CACR, "CACR", m68k->cacr);
1904		state->state_add(M68K_CAAR, "CAAR", m68k->caar);
	1776	state_add(M68K_CACR, "CACR", cacr);
	1777	state_add(M68K_CAAR, "CAAR", caar);
1905	1778	}
1906	1779
1907		if (~~m68k->~~cpu_type & MASK_030_OR_LATER)
	1780	if (cpu_type & MASK_030_OR_LATER)
1908	1781	{
1909	1782	for (int regnum = 0; regnum < 8; regnum++)
1910		state->state_add(M68K_FP0 + regnum, tempstr.format("FP%d", regnum), m68k->iotemp).callimport().callexport().formatstr("%10s");
1911		state->state_add(M68K_FPSR, "FPSR", m68k->fpsr);
1912		state->state_add(M68K_FPCR, "FPCR", m68k->fpcr);
	1783	state_add(M68K_FP0 + regnum, tempstr.format("FP%d", regnum), iotemp).callimport().callexport().formatstr("%10s");
	1784	state_add(M68K_FPSR, "FPSR", fpsr);
	1785	state_add(M68K_FPCR, "FPCR", fpcr);
1913	1786	}
1914	1787	}
1915	1788
1916	1789
1917		/****************************************************************************
1918		* 68000 section
1919		****************************************************************************/
	1790	/* 68307 specifics - MOVE */
1920	1791
1921		static CPU_INIT( m68000 )
1922		{
1923		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
1924
1925		CPU_INIT_CALL(m68k);
1926
1927		m68k->cpu_type = CPU_TYPE_000;
1928		m68k->dasm_type = M68K_CPU_TYPE_68000;
1929		// hack alert: we use placement new to ensure we are properly initialized
1930		// because we live in the device state which is allocated as bytes
1931		// remove me when we have a real C++ device
1932		new(&m68k->memory) m68k_memory_interface;
1933		m68k->memory.init16(*m68k->program);
1934		m68k->sr_mask = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */
1935		m68k->jump_table = m68ki_instruction_jump_table[0];
1936		m68k->cyc_instruction = m68ki_cycles[0];
1937		m68k->cyc_exception = m68ki_exception_cycle_table[0];
1938		m68k->cyc_bcc_notake_b = -2;
1939		m68k->cyc_bcc_notake_w = 2;
1940		m68k->cyc_dbcc_f_noexp = -2;
1941		m68k->cyc_dbcc_f_exp = 2;
1942		m68k->cyc_scc_r_true = 2;
1943		m68k->cyc_movem_w = 2;
1944		m68k->cyc_movem_l = 3;
1945		m68k->cyc_shift = 1;
1946		m68k->cyc_reset = 132;
1947		m68k->has_pmmu = 0;
1948		m68k->has_hmmu = 0;
1949		m68k->has_fpu = 0;
1950
1951		define_state(device);
1952		}
1953
1954		CPU_GET_INFO( m68000 )
1955		{
1956		switch (state)
1957		{
1958		/* --- the following bits of info are returned as pointers to data or functions --- */
1959		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68000); break;
1960
1961		/* --- the following bits of info are returned as NULL-terminated strings --- */
1962		case CPUINFO_STR_NAME: strcpy(info->s, "68000"); break;
1963
1964		default: CPU_GET_INFO_CALL(m68k); break;
1965		}
1966		}
1967
1968		static CPU_INIT( m68301 )
1969		{
1970		// m68ki_cpu_core *m68k = m68k_get_safe_token(device);
1971
1972		CPU_INIT_CALL(m68000);
1973
1974		/* there is a basic implementation of this in emu/machine/tmp68301.c but it should be moved here */
1975
1976		}
1977
1978		CPU_GET_INFO( m68301 )
1979		{
1980		switch (state)
1981		{
1982		/* --- the following bits of info are returned as pointers to data or functions --- */
1983		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68301); break;
1984
1985		/* --- the following bits of info are returned as NULL-terminated strings --- */
1986		case CPUINFO_STR_NAME: strcpy(info->s, "68301"); break;
1987
1988		default: CPU_GET_INFO_CALL(m68k); break;
1989		}
1990		}
1991
1992
1993
1994
1995	1792	void m68307_set_interrupt(device_t *device, int level, int vector)
1996	1793	{
1997	1794	device->execute().set_input_line_and_vector(level, HOLD_LINE, vector);
1998	1795	}
1999	1796
2000		void m68307_timer0_interrupt(~~legacy~~_~~cpu~~_device *cpudev)
	1797	void m68307_timer0_interrupt(m68000_base_device *cpudev)
2001	1798	{
2002		m68ki_cpu_core* m68k = m68k_get_safe_token(cpudev);
2003		int prioritylevel = (m68k->m68307SIM->m_picr & 0x7000)>>12;
2004		int vector = (m68k->m68307SIM->m_pivr & 0x00f0) \| 0xa;
	1799	int prioritylevel = (cpudev->m68307SIM->m_picr & 0x7000)>>12;
	1800	int vector = (cpudev->m68307SIM->m_pivr & 0x00f0) \| 0xa;
2005	1801	m68307_set_interrupt(cpudev, prioritylevel, vector);
2006	1802	}
2007	1803
2008		void m68307_timer1_interrupt(~~legacy~~_~~cpu~~_device *cpudev)
	1804	void m68307_timer1_interrupt(m68000_base_device *cpudev)
2009	1805	{
2010		m68ki_cpu_core* m68k = m68k_get_safe_token(cpudev);
2011		int prioritylevel = (m68k->m68307SIM->m_picr & 0x0700)>>8;
2012		int vector = (m68k->m68307SIM->m_pivr & 0x00f0) \| 0xb;
	1806	int prioritylevel = (cpudev->m68307SIM->m_picr & 0x0700)>>8;
	1807	int vector = (cpudev->m68307SIM->m_pivr & 0x00f0) \| 0xb;
2013	1808	m68307_set_interrupt(cpudev, prioritylevel, vector);
2014	1809	}
2015	1810
2016		void m68307_serial_interrupt(~~legacy~~_~~cpu~~_device *cpudev, int vector)
	1811	void m68307_serial_interrupt(m68000_base_device *cpudev, int vector)
2017	1812	{
2018		m68ki_cpu_core* m68k = m68k_get_safe_token(cpudev);
2019		int prioritylevel = (m68k->m68307SIM->m_picr & 0x0070)>>4;
	1813	int prioritylevel = (cpudev->m68307SIM->m_picr & 0x0070)>>4;
2020	1814	m68307_set_interrupt(cpudev, prioritylevel, vector);
2021	1815	}
2022	1816
2023		void m68307_mbus_interrupt(~~legacy~~_~~cpu~~_device *cpudev)
	1817	void m68307_mbus_interrupt(m68000_base_device *cpudev)
2024	1818	{
2025		m68ki_cpu_core* m68k = m68k_get_safe_token(cpudev);
2026		int prioritylevel = (m68k->m68307SIM->m_picr & 0x0007)>>0;
2027		int vector = (m68k->m68307SIM->m_pivr & 0x00f0) \| 0xd;
	1819	int prioritylevel = (cpudev->m68307SIM->m_picr & 0x0007)>>0;
	1820	int vector = (cpudev->m68307SIM->m_pivr & 0x00f0) \| 0xd;
2028	1821	m68307_set_interrupt(cpudev, prioritylevel, vector);
2029	1822	}
2030	1823
2031		void m68307_licr2_interrupt(~~legacy~~_~~cpu~~_device *cpudev)
	1824	void m68307_licr2_interrupt(m68000_base_device *cpudev)
2032	1825	{
2033		m68ki_cpu_core* m68k = m68k_get_safe_token(cpudev);
2034		int prioritylevel = (m68k->m68307SIM->m_licr2 & 0x0007)>>0;
2035		int vector = (m68k->m68307SIM->m_pivr & 0x00f0) \| 0x9;
2036		m68k->m68307SIM->m_licr2 \|= 0x8;
	1826	int prioritylevel = (cpudev->m68307SIM->m_licr2 & 0x0007)>>0;
	1827	int vector = (cpudev->m68307SIM->m_pivr & 0x00f0) \| 0x9;
	1828	cpudev->m68307SIM->m_licr2 \|= 0x8;
2037	1829
2038	1830
2039	1831	m68307_set_interrupt(cpudev, prioritylevel, vector);
2040	1832	}
2041	1833
2042
2043
2044		static CPU_INIT( m68307 )
	1834	void m68000_base_device::init_cpu_m68307(void)
2045	1835	{
2046		~~m68k~~i_cpu_core *m68~~k = m68k_get_safe_token~~(~~device~~);
	1836	init_cpu_m68000();
2047	1837
2048		CPU_INIT_CALL(m68000);
2049
2050	1838	/* basic CS logic, timers, mbus, serial logic
2051	1839	set via remappable register
2052	1840	*/
2053		new(&m68k->memory) m68k_memory_interface;
2054		m68k->memory.init16_m68307(*m68k->program);
	1841
	1842	init16_m68307(*program);
2055	1843
2056		m68k->m68307SIM = new m68307_sim();
2057		m68k->m68307MBUS = new m68307_mbus();
2058		m68k->m68307SERIAL = new m68307_serial();
2059		m68k->m68307TIMER = new m68307_timer();
	1844	m68307SIM = new m68307_sim();
	1845	m68307MBUS = new m68307_mbus();
	1846	m68307SERIAL = new m68307_serial();
	1847	m68307TIMER = new m68307_timer();
2060	1848
2061		m68~~k->m68~~307TIMER->init(~~dev~~ice);
	1849	m68307TIMER->init(this);
2062	1850
2063		m68k->m68307SIM->reset();
2064		m68k->m68307MBUS->reset();
2065		m68k->m68307SERIAL->reset();
2066		m68k->m68307TIMER->reset();
	1851	m68307SIM->reset();
	1852	m68307MBUS->reset();
	1853	m68307SERIAL->reset();
	1854	m68307TIMER->reset();
2067	1855
2068		m68k->internal = &device->space(AS_PROGRAM);
2069		m68k->m68307_base = 0xbfff;
2070		m68k->m68307_scrhigh = 0x0007;
2071		m68k->m68307_scrlow = 0xf010;
	1856	internal = &this->space(AS_PROGRAM);
	1857	m68307_base = 0xbfff;
	1858	m68307_scrhigh = 0x0007;
	1859	m68307_scrlow = 0xf010;
2072	1860
2073		m68307_set_port_callbacks(~~dev~~ice, 0,0,0,0);
	1861	m68307_set_port_callbacks(this, 0,0,0,0);
2074	1862	}
2075	1863
2076		static READ16_HANDLER( m68307_internal_base_r )
	1864
	1865
	1866	READ16_MEMBER( m68000_base_device::m68307_internal_base_r )
2077	1867	{
2078		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	1868	m68000_base_device *m68k = this;
2079	1869
2080	1870	int pc = space.device().safe_pc();
2081	1871	logerror("%08x m68307_internal_base_r %08x, (%04x)\n", pc, offset*2,mem_mask);
r23920	r23921
2092	1882	return 0x0000;
2093	1883	}
2094	1884
2095		~~static~~ WRITE16_~~HANDL~~ER( m68307_internal_base_w )
	1885	WRITE16_MEMBER( m68000_base_device::m68307_internal_base_w )
2096	1886	{
2097		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	1887	m68000_base_device *m68k = this;
2098	1888
2099	1889	int pc = space.device().safe_pc();
2100	1890	logerror("%08x m68307_internal_base_w %08x, %04x (%04x)\n", pc, offset*2,data,mem_mask);
r23920	r23921
2120	1910	base = (m68k->m68307_base & 0x0fff) << 12;
2121	1911	//mask = (m68k->m68307_base & 0xe000) >> 13;
2122	1912	//if ( m68k->m68307_base & 0x1000 ) mask \|= 7;
2123		m68k->internal->install_legacy_readwrite_handler(base + 0x000, base + 0x04f, FUNC(m68307_internal_sim_r), FUNC(m68307_internal_sim_w));
2124		m68k->internal->install_legacy_readwrite_handler(base + 0x100, base + 0x11f, FUNC(m68307_internal_serial_r), FUNC(m68307_internal_serial_w), 0xffff);
2125		m68k->internal->install_legacy_readwrite_handler(base + 0x120, base + 0x13f, FUNC(m68307_internal_timer_r), FUNC(m68307_internal_timer_w));
2126		m68k->internal->install_legacy_readwrite_handler(base + 0x140, base + 0x149, FUNC(m68307_internal_mbus_r), FUNC(m68307_internal_mbus_w), 0xffff);
	1913	m68k->internal->install_readwrite_handler(base + 0x000, base + 0x04f, read16_delegate(FUNC(m68000_base_device::m68307_internal_sim_r),this), write16_delegate(FUNC(m68000_base_device::m68307_internal_sim_w),this));
	1914	m68k->internal->install_readwrite_handler(base + 0x100, base + 0x11f, read8_delegate(FUNC(m68000_base_device::m68307_internal_serial_r),this), write8_delegate(FUNC(m68000_base_device::m68307_internal_serial_w),this), 0xffff);
	1915	m68k->internal->install_readwrite_handler(base + 0x120, base + 0x13f, read16_delegate(FUNC(m68000_base_device::m68307_internal_timer_r),this), write16_delegate(FUNC(m68000_base_device::m68307_internal_timer_w),this));
	1916	m68k->internal->install_readwrite_handler(base + 0x140, base + 0x149, read8_delegate(FUNC(m68000_base_device::m68307_internal_mbus_r),this), write8_delegate(FUNC(m68000_base_device::m68307_internal_mbus_w),this), 0xffff);
2127	1917
	1918
2128	1919	break;
2129	1920
2130	1921	case 0x4:
r23920	r23921
2141	1932	}
2142	1933	}
2143	1934
2144		static ADDRESS_MAP_START( m68307_internal_map, AS_PROGRAM, 16, legacy_cpu_device )
2145		AM_RANGE(0x000000f0, 0x000000ff) AM_READWRITE_LEGACY(m68307_internal_base_r, m68307_internal_base_w)
	1935	static ADDRESS_MAP_START( m68307_internal_map, AS_PROGRAM, 16, m68000_base_device )
	1936	AM_RANGE(0x000000f0, 0x000000ff) AM_READWRITE(m68307_internal_base_r, m68307_internal_base_w)
2146	1937	ADDRESS_MAP_END
2147	1938
2148		CPU_GET_INFO( m68307 )
	1939	/* 68340 specifics - MOVE */
	1940
	1941	READ32_MEMBER( m68000_base_device::m68340_internal_base_r )
2149	1942	{
2150		switch (state)
	1943	m68000_base_device *m68k = this;
	1944	int pc = space.device().safe_pc();
	1945	logerror("%08x m68340_internal_base_r %08x, (%08x)\n", pc, offset*4,mem_mask);
	1946	return m68k->m68340_base;
	1947	}
	1948
	1949	WRITE32_MEMBER( m68000_base_device::m68340_internal_base_w )
	1950	{
	1951	m68000_base_device *m68k = this;
	1952
	1953	int pc = space.device().safe_pc();
	1954	logerror("%08x m68340_internal_base_w %08x, %08x (%08x)\n", pc, offset*4,data,mem_mask);
	1955
	1956	// other conditions?
	1957	if (m68k->dfc==0x7)
2151	1958	{
2152		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break;
	1959	// unmap old modules
	1960	if (m68k->m68340_base&1)
	1961	{
	1962	int base = m68k->m68340_base & 0xfffff000;
2153	1963
2154		/* --- the following bits of info are returned as pointers to data or functions --- */
2155		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68307); break;
	1964	m68k->internal->unmap_readwrite(base + 0x000, base + 0x05f);
	1965	m68k->internal->unmap_readwrite(base + 0x600, base + 0x67f);
	1966	m68k->internal->unmap_readwrite(base + 0x700, base + 0x723);
	1967	m68k->internal->unmap_readwrite(base + 0x780, base + 0x7bf);
2156	1968
2157		/* --- the following bits of info are returned as NULL-terminated strings --- */
2158		case CPUINFO_STR_NAME: strcpy(info->s, "68307"); break;
	1969	}
2159	1970
2160		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(m68307_internal_map); break;
	1971	COMBINE_DATA(&m68k->m68340_base);
	1972	logerror("%08x m68340_internal_base_w %08x, %08x (%08x) (m68340_base write)\n", pc, offset*4,data,mem_mask);
2161	1973
	1974	// map new modules
	1975	if (m68k->m68340_base&1)
	1976	{
	1977	int base = m68k->m68340_base & 0xfffff000;
2162	1978
2163		default: CPU_GET_INFO_CALL(m68k); break;
	1979	m68k->internal->install_readwrite_handler(base + 0x000, base + 0x03f, read16_delegate(FUNC(m68000_base_device::m68340_internal_sim_r),this), write16_delegate(FUNC(m68000_base_device::m68340_internal_sim_w),this),0xffffffff);
	1980	m68k->internal->install_readwrite_handler(base + 0x010, base + 0x01f, read8_delegate(FUNC(m68000_base_device::m68340_internal_sim_ports_r),this),write8_delegate(FUNC(m68000_base_device::m68340_internal_sim_ports_w),this),0xffffffff);
	1981	m68k->internal->install_readwrite_handler(base + 0x040, base + 0x05f, read32_delegate(FUNC(m68000_base_device::m68340_internal_sim_cs_r),this), write32_delegate(FUNC(m68000_base_device::m68340_internal_sim_cs_w),this));
	1982	m68k->internal->install_readwrite_handler(base + 0x600, base + 0x67f, read32_delegate(FUNC(m68000_base_device::m68340_internal_timer_r),this), write32_delegate(FUNC(m68000_base_device::m68340_internal_timer_w),this));
	1983	m68k->internal->install_readwrite_handler(base + 0x700, base + 0x723, read32_delegate(FUNC(m68000_base_device::m68340_internal_serial_r),this), write32_delegate(FUNC(m68000_base_device::m68340_internal_serial_w),this));
	1984	m68k->internal->install_readwrite_handler(base + 0x780, base + 0x7bf, read32_delegate(FUNC(m68000_base_device::m68340_internal_dma_r),this), write32_delegate(FUNC(m68000_base_device::m68340_internal_dma_w),this));
	1985
	1986	}
	1987
2164	1988	}
	1989	else
	1990	{
	1991	logerror("%08x m68340_internal_base_w %08x, %04x (%04x) (should fall through?)\n", pc, offset*4,data,mem_mask);
	1992	}
	1993
	1994
	1995
2165	1996	}
2166	1997
2167	1998
2168		/****************************************************************************
2169		* M68008 section
2170		****************************************************************************/
	1999	static ADDRESS_MAP_START( m68340_internal_map, AS_PROGRAM, 32, m68000_base_device )
	2000	AM_RANGE(0x0003ff00, 0x0003ff03) AM_READWRITE( m68340_internal_base_r, m68340_internal_base_w)
	2001	ADDRESS_MAP_END
2171	2002
2172		static CPU_INIT( m68008 )
	2003
	2004	/****************
	2005	CPU Inits
	2006	****************/
	2007
	2008
	2009	void m68000_base_device::init_cpu_m68000(void)
2173	2010	{
2174		~~m68k~~i_cpu_core *m~~68k =~~ m~~68k_get_safe_t~~oken(~~device~~);
	2011	init_cpu_common();
2175	2012
2176		CPU_INIT_CALL(m68k);
	2013	cpu_type = CPU_TYPE_000;
	2014	// dasm_type = M68K_CPU_TYPE_68000;
	2015
	2016	init16(*program);
	2017	sr_mask = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */
	2018	jump_table = m68ki_instruction_jump_table[0];
	2019	cyc_instruction = m68ki_cycles[0];
	2020	cyc_exception = m68ki_exception_cycle_table[0];
	2021	cyc_bcc_notake_b = -2;
	2022	cyc_bcc_notake_w = 2;
	2023	cyc_dbcc_f_noexp = -2;
	2024	cyc_dbcc_f_exp = 2;
	2025	cyc_scc_r_true = 2;
	2026	cyc_movem_w = 2;
	2027	cyc_movem_l = 3;
	2028	cyc_shift = 1;
	2029	cyc_reset = 132;
	2030	has_pmmu = 0;
	2031	has_hmmu = 0;
	2032	has_fpu = 0;
2177	2033
2178		m68k->cpu_type = CPU_TYPE_008;
2179		m68k->dasm_type = M68K_CPU_TYPE_68008;
2180		// hack alert: we use placement new to ensure we are properly initialized
2181		// because we live in the device state which is allocated as bytes
2182		// remove me when we have a real C++ device
2183		new(&m68k->memory) m68k_memory_interface;
2184		m68k->memory.init8(*m68k->program);
2185		m68k->sr_mask = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */
2186		m68k->jump_table = m68ki_instruction_jump_table[0];
2187		m68k->cyc_instruction = m68ki_cycles[0];
2188		m68k->cyc_exception = m68ki_exception_cycle_table[0];
2189		m68k->cyc_bcc_notake_b = -2;
2190		m68k->cyc_bcc_notake_w = 2;
2191		m68k->cyc_dbcc_f_noexp = -2;
2192		m68k->cyc_dbcc_f_exp = 2;
2193		m68k->cyc_scc_r_true = 2;
2194		m68k->cyc_movem_w = 2;
2195		m68k->cyc_movem_l = 3;
2196		m68k->cyc_shift = 1;
2197		m68k->cyc_reset = 132;
2198		m68k->has_pmmu = 0;
2199		m68k->has_fpu = 0;
	2034	define_state();
2200	2035
2201		define_state(device);
2202	2036	}
2203	2037
2204		CPU_GET_INFO( m68008 )
	2038
	2039	void m68000_base_device::init_cpu_m68008(void)
2205	2040	{
2206		switch (state)
2207		{
2208		/* --- the following bits of info are returned as 64-bit signed integers --- */
2209		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break;
2210		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 20; break;
2211	2041
2212		/* --- the following bits of info are returned as pointers to data or functions --- */
2213		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68008); break;
	2042	init_cpu_common();
2214	2043
2215		/* --- the following bits of info are returned as NULL-terminated strings --- */
2216		case CPUINFO_STR_NAME: strcpy(info->s, "68008"); break;
	2044	cpu_type = CPU_TYPE_008;
	2045	// dasm_type = M68K_CPU_TYPE_68008;
	2046
	2047	init8(*program);
	2048	sr_mask = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */
	2049	jump_table = m68ki_instruction_jump_table[0];
	2050	cyc_instruction = m68ki_cycles[0];
	2051	cyc_exception = m68ki_exception_cycle_table[0];
	2052	cyc_bcc_notake_b = -2;
	2053	cyc_bcc_notake_w = 2;
	2054	cyc_dbcc_f_noexp = -2;
	2055	cyc_dbcc_f_exp = 2;
	2056	cyc_scc_r_true = 2;
	2057	cyc_movem_w = 2;
	2058	cyc_movem_l = 3;
	2059	cyc_shift = 1;
	2060	cyc_reset = 132;
	2061	has_pmmu = 0;
	2062	has_fpu = 0;
2217	2063
2218		default: CPU_GET_INFO_CALL(m68k); break;
2219		}
	2064	define_state();
	2065
2220	2066	}
2221	2067
2222		CPU_GET_INFO( m68008plcc )
	2068
	2069	void m68000_base_device::init_cpu_m68010(void)
2223	2070	{
2224		switch (state)
2225		{
2226		/* --- the following bits of info are returned as 64-bit signed integers --- */
2227		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break;
2228		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 22; break;
2229	2071
2230		/* --- the following bits of info are returned as pointers to data or functions --- */
2231		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68008); break;
	2072	init_cpu_common();
	2073	cpu_type = CPU_TYPE_010;
	2074	// dasm_type = M68K_CPU_TYPE_68010;
	2075
	2076	init16(*program);
	2077	sr_mask = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */
	2078	jump_table = m68ki_instruction_jump_table[1];
	2079	cyc_instruction = m68ki_cycles[1];
	2080	cyc_exception = m68ki_exception_cycle_table[1];
	2081	cyc_bcc_notake_b = -4;
	2082	cyc_bcc_notake_w = 0;
	2083	cyc_dbcc_f_noexp = 0;
	2084	cyc_dbcc_f_exp = 6;
	2085	cyc_scc_r_true = 0;
	2086	cyc_movem_w = 2;
	2087	cyc_movem_l = 3;
	2088	cyc_shift = 1;
	2089	cyc_reset = 130;
	2090	has_pmmu = 0;
	2091	has_fpu = 0;
2232	2092
2233		/* --- the following bits of info are returned as NULL-terminated strings --- */
2234		case CPUINFO_STR_NAME: strcpy(info->s, "68008"); break;
	2093	define_state();
	2094	}
2235	2095
2236		default: CPU_GET_INFO_CALL(m68k); break;
2237		}
	2096
	2097	void m68000_base_device::init_cpu_m68020(void)
	2098	{
	2099	init_cpu_common();
	2100	cpu_type = CPU_TYPE_020;
	2101	// dasm_type = M68K_CPU_TYPE_68020;
	2102
	2103	init32(*program);
	2104	sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
	2105	jump_table = m68ki_instruction_jump_table[2];
	2106	cyc_instruction = m68ki_cycles[2];
	2107	cyc_exception = m68ki_exception_cycle_table[2];
	2108	cyc_bcc_notake_b = -2;
	2109	cyc_bcc_notake_w = 0;
	2110	cyc_dbcc_f_noexp = 0;
	2111	cyc_dbcc_f_exp = 4;
	2112	cyc_scc_r_true = 0;
	2113	cyc_movem_w = 2;
	2114	cyc_movem_l = 2;
	2115	cyc_shift = 0;
	2116	cyc_reset = 518;
	2117
	2118	define_state();
2238	2119	}
2239	2120
2240	2121
2241		/****************************************************************************
2242		* M68010 section
2243		****************************************************************************/
	2122	void m68000_base_device::init_cpu_m68020pmmu(void)
	2123	{
	2124	init_cpu_m68020();
2244	2125
2245		static CPU_INIT( m68010 )
	2126	has_pmmu = 1;
	2127	has_fpu = 1;
	2128
	2129
	2130	init32mmu(*program);
	2131	}
	2132
	2133
	2134
	2135	void m68000_base_device::init_cpu_m68020hmmu(void)
2246	2136	{
2247		~~m68k~~i_cpu_core *m68~~k = m68k_get_safe_token~~(~~device~~);
	2137	init_cpu_m68020();
2248	2138
2249		CPU_INIT_CALL(m68k);
	2139	has_hmmu = 1;
	2140	has_fpu = 1;
2250	2141
2251		m68k->cpu_type = CPU_TYPE_010;
2252		m68k->dasm_type = M68K_CPU_TYPE_68010;
2253		// hack alert: we use placement new to ensure we are properly initialized
2254		// because we live in the device state which is allocated as bytes
2255		// remove me when we have a real C++ device
2256		new(&m68k->memory) m68k_memory_interface;
2257		m68k->memory.init16(*m68k->program);
2258		m68k->sr_mask = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */
2259		m68k->jump_table = m68ki_instruction_jump_table[1];
2260		m68k->cyc_instruction = m68ki_cycles[1];
2261		m68k->cyc_exception = m68ki_exception_cycle_table[1];
2262		m68k->cyc_bcc_notake_b = -4;
2263		m68k->cyc_bcc_notake_w = 0;
2264		m68k->cyc_dbcc_f_noexp = 0;
2265		m68k->cyc_dbcc_f_exp = 6;
2266		m68k->cyc_scc_r_true = 0;
2267		m68k->cyc_movem_w = 2;
2268		m68k->cyc_movem_l = 3;
2269		m68k->cyc_shift = 1;
2270		m68k->cyc_reset = 130;
2271		m68k->has_pmmu = 0;
2272		m68k->has_fpu = 0;
2273
2274		define_state(device);
	2142
	2143	init32hmmu(*program);
2275	2144	}
2276	2145
2277		~~CPU~~_~~GET~~_~~INFO(~~ m68010 )
	2146	void m68000_base_device::init_cpu_m68ec020(void)
2278	2147	{
2279		switch (state)
2280		{
2281		/* --- the following bits of info are returned as pointers to data or functions --- */
2282		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68010); break;
	2148	init_cpu_common();
2283	2149
2284		/* --- the following bits of info are returned as NULL-terminated strings --- */
2285		case CPUINFO_STR_NAME: strcpy(info->s, "68010"); break;
	2150	cpu_type = CPU_TYPE_EC020;
	2151	// dasm_type = M68K_CPU_TYPE_68EC020;
2286	2152
2287		default: CPU_GET_INFO_CALL(m68k); break;
2288		}
	2153
	2154	init32(*program);
	2155	sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
	2156	jump_table = m68ki_instruction_jump_table[2];
	2157	cyc_instruction = m68ki_cycles[2];
	2158	cyc_exception = m68ki_exception_cycle_table[2];
	2159	cyc_bcc_notake_b = -2;
	2160	cyc_bcc_notake_w = 0;
	2161	cyc_dbcc_f_noexp = 0;
	2162	cyc_dbcc_f_exp = 4;
	2163	cyc_scc_r_true = 0;
	2164	cyc_movem_w = 2;
	2165	cyc_movem_l = 2;
	2166	cyc_shift = 0;
	2167	cyc_reset = 518;
	2168	has_pmmu = 0;
	2169	has_fpu = 0;
	2170
	2171	define_state();
2289	2172	}
2290	2173
2291	2174
2292		/****************************************************************************
2293		* M68020 section
2294		****************************************************************************/
2295
2296		static CPU_INIT( m68020 )
	2175	void m68000_base_device::init_cpu_m68030(void)
2297	2176	{
2298		~~m68k~~i_cpu_core *m~~68k =~~ m~~68k_get_safe_t~~oken(~~device~~);
	2177	init_cpu_common();
2299	2178
2300		CPU_INIT_CALL(m68k);
	2179	cpu_type = CPU_TYPE_030;
	2180	// dasm_type = M68K_CPU_TYPE_68030;
2301	2181
2302		m68k->cpu_type = CPU_TYPE_020;
2303		m68k->dasm_type = M68K_CPU_TYPE_68020;
2304		// hack alert: we use placement new to ensure we are properly initialized
2305		// because we live in the device state which is allocated as bytes
2306		// remove me when we have a real C++ device
2307		new(&m68k->memory) m68k_memory_interface;
2308		m68k->memory.init32(*m68k->program);
2309		m68k->sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
2310		m68k->jump_table = m68ki_instruction_jump_table[2];
2311		m68k->cyc_instruction = m68ki_cycles[2];
2312		m68k->cyc_exception = m68ki_exception_cycle_table[2];
2313		m68k->cyc_bcc_notake_b = -2;
2314		m68k->cyc_bcc_notake_w = 0;
2315		m68k->cyc_dbcc_f_noexp = 0;
2316		m68k->cyc_dbcc_f_exp = 4;
2317		m68k->cyc_scc_r_true = 0;
2318		m68k->cyc_movem_w = 2;
2319		m68k->cyc_movem_l = 2;
2320		m68k->cyc_shift = 0;
2321		m68k->cyc_reset = 518;
	2182
	2183	init32mmu(*program);
	2184	sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
	2185	jump_table = m68ki_instruction_jump_table[3];
	2186	cyc_instruction = m68ki_cycles[3];
	2187	cyc_exception = m68ki_exception_cycle_table[3];
	2188	cyc_bcc_notake_b = -2;
	2189	cyc_bcc_notake_w = 0;
	2190	cyc_dbcc_f_noexp = 0;
	2191	cyc_dbcc_f_exp = 4;
	2192	cyc_scc_r_true = 0;
	2193	cyc_movem_w = 2;
	2194	cyc_movem_l = 2;
	2195	cyc_shift = 0;
	2196	cyc_reset = 518;
	2197	has_pmmu = 1;
	2198	has_fpu = 1;
2322	2199
2323		define_state(~~device~~);
	2200	define_state();
2324	2201	}
2325	2202
2326		CPU_GET_INFO( m68020 )
2327		{
2328		switch (state)
2329		{
2330		/* --- the following bits of info are returned as 64-bit signed integers --- */
2331		case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 20; break;
2332		case CPUINFO_INT_MIN_CYCLES: info->i = 2; break;
2333		case CPUINFO_INT_MAX_CYCLES: info->i = 158; break;
2334	2203
2335		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 32; break;
2336		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break;
2337	2204
2338		/* --- the following bits of info are returned as pointers to data or functions --- */
2339		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68020); break;
	2205	void m68000_base_device::init_cpu_m68ec030(void)
	2206	{
	2207	init_cpu_common();
	2208
	2209	cpu_type = CPU_TYPE_EC030;
	2210	// dasm_type = M68K_CPU_TYPE_68EC030;
2340	2211
2341		/* --- the following bits of info are returned as NULL-terminated strings --- */
2342		case CPUINFO_STR_NAME: strcpy(info->s, "68020"); break;
	2212
	2213	init32(*program);
	2214	sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
	2215	jump_table = m68ki_instruction_jump_table[3];
	2216	cyc_instruction = m68ki_cycles[3];
	2217	cyc_exception = m68ki_exception_cycle_table[3];
	2218	cyc_bcc_notake_b = -2;
	2219	cyc_bcc_notake_w = 0;
	2220	cyc_dbcc_f_noexp = 0;
	2221	cyc_dbcc_f_exp = 4;
	2222	cyc_scc_r_true = 0;
	2223	cyc_movem_w = 2;
	2224	cyc_movem_l = 2;
	2225	cyc_shift = 0;
	2226	cyc_reset = 518;
	2227	has_pmmu = 0; /* EC030 lacks the PMMU and is effectively a die-shrink 68020 */
	2228	has_fpu = 1;
2343	2229
2344		default: CPU_GET_INFO_CALL(m68k); break;
2345		}
	2230	define_state();
2346	2231	}
2347	2232
2348		// 68020 with 68851 PMMU
2349		static CPU_INIT( m68020pmmu )
	2233
	2234
	2235	void m68000_base_device::init_cpu_m68040(void)
2350	2236	{
2351		~~m68k~~i_cpu_core *m~~68k =~~ m~~68k_get_safe_t~~oken(~~device~~);
	2237	init_cpu_common();
2352	2238
2353		CPU_INIT_CALL(m68020);
	2239	cpu_type = CPU_TYPE_040;
	2240	// dasm_type = M68K_CPU_TYPE_68040;
2354	2241
2355		m68k->has_pmmu = 1;
2356		m68k->has_fpu = 1;
	2242
	2243	init32mmu(*program);
	2244	sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
	2245	jump_table = m68ki_instruction_jump_table[4];
	2246	cyc_instruction = m68ki_cycles[4];
	2247	cyc_exception = m68ki_exception_cycle_table[4];
	2248	cyc_bcc_notake_b = -2;
	2249	cyc_bcc_notake_w = 0;
	2250	cyc_dbcc_f_noexp = 0;
	2251	cyc_dbcc_f_exp = 4;
	2252	cyc_scc_r_true = 0;
	2253	cyc_movem_w = 2;
	2254	cyc_movem_l = 2;
	2255	cyc_shift = 0;
	2256	cyc_reset = 518;
	2257	has_pmmu = 1;
	2258	has_fpu = 1;
2357	2259
2358		// hack alert: we use placement new to ensure we are properly initialized
2359		// because we live in the device state which is allocated as bytes
2360		// remove me when we have a real C++ device
2361		new(&m68k->memory) m68k_memory_interface;
2362		m68k->memory.init32mmu(*m68k->program);
	2260	define_state();
2363	2261	}
2364	2262
2365		CPU_GET_INFO( m68020pmmu )
	2263
	2264	void m68000_base_device::init_cpu_m68ec040(void)
2366	2265	{
2367		switch (state)
2368		{
2369		/* --- the following bits of info are returned as pointers to data or functions --- */
2370		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68020pmmu); break;
	2266	init_cpu_common();
2371	2267
2372		/* --- the following bits of info are returned as NULL-terminated strings --- */
2373		case CPUINFO_STR_NAME: strcpy(info->s, "68020, 68851"); break;
	2268	cpu_type = CPU_TYPE_EC040;
	2269	// dasm_type = M68K_CPU_TYPE_68EC040;
2374	2270
2375		default: CPU_GET_INFO_CALL(m68020); break;
2376		}
	2271
	2272	init32(*program);
	2273	sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
	2274	jump_table = m68ki_instruction_jump_table[4];
	2275	cyc_instruction = m68ki_cycles[4];
	2276	cyc_exception = m68ki_exception_cycle_table[4];
	2277	cyc_bcc_notake_b = -2;
	2278	cyc_bcc_notake_w = 0;
	2279	cyc_dbcc_f_noexp = 0;
	2280	cyc_dbcc_f_exp = 4;
	2281	cyc_scc_r_true = 0;
	2282	cyc_movem_w = 2;
	2283	cyc_movem_l = 2;
	2284	cyc_shift = 0;
	2285	cyc_reset = 518;
	2286	has_pmmu = 0;
	2287	has_fpu = 0;
	2288
	2289	define_state();
2377	2290	}
2378	2291
2379		// 68020 with Apple HMMU & 68881 FPU
2380		static CPU_INIT( m68020hmmu )
	2292
	2293	void m68000_base_device::init_cpu_m68lc040(void)
2381	2294	{
2382		~~m68k~~i_cpu_core *m~~68k =~~ m~~68k_get_safe_t~~oken(~~device~~);
	2295	init_cpu_common();
2383	2296
2384		CPU_INIT_CALL(m68020);
	2297	cpu_type = CPU_TYPE_LC040;
	2298	// dasm_type = M68K_CPU_TYPE_68LC040;
2385	2299
2386		m68k->has_hmmu = 1;
2387		m68k->has_fpu = 1;
2388		// hack alert: we use placement new to ensure we are properly initialized
2389		// because we live in the device state which is allocated as bytes
2390		// remove me when we have a real C++ device
2391		new(&m68k->memory) m68k_memory_interface;
2392		m68k->memory.init32hmmu(*m68k->program);
	2300
	2301	init32mmu(*program);
	2302	sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
	2303	jump_table = m68ki_instruction_jump_table[4];
	2304	cyc_instruction = m68ki_cycles[4];
	2305	cyc_exception = m68ki_exception_cycle_table[4];
	2306	cyc_bcc_notake_b = -2;
	2307	cyc_bcc_notake_w = 0;
	2308	cyc_dbcc_f_noexp = 0;
	2309	cyc_dbcc_f_exp = 4;
	2310	cyc_scc_r_true = 0;
	2311	cyc_movem_w = 2;
	2312	cyc_movem_l = 2;
	2313	cyc_shift = 0;
	2314	cyc_reset = 518;
	2315	has_pmmu = 1;
	2316	has_fpu = 0;
	2317
	2318	define_state();
2393	2319	}
2394	2320
2395		CPU_GET_INFO( m68020hmmu )
	2321
	2322	void m68000_base_device::init_cpu_scc68070(void)
2396	2323	{
2397		switch (state)
2398		{
2399		/* --- the following bits of info are returned as pointers to data or functions --- */
2400		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68020hmmu); break;
2401		case CPUINFO_FCT_TRANSLATE: info->translate = CPU_TRANSLATE_NAME(m68khmmu); break;
	2324	init_cpu_m68010();
	2325	cpu_type = CPU_TYPE_SCC070;
	2326	}
2402	2327
2403		/* --- the following bits of info are returned as NULL-terminated strings --- */
2404		case CPUINFO_STR_NAME: strcpy(info->s, "68020, Apple HMMU"); break;
2405	2328
2406		default: CPU_GET_INFO_CALL(m68020); break;
2407		}
	2329	void m68000_base_device::init_cpu_m68340(void)
	2330	{
	2331	init_cpu_common();
	2332
	2333	cpu_type = CPU_TYPE_68340;
	2334	// dasm_type = M68K_CPU_TYPE_68340;
	2335
	2336
	2337	init32(*program);
	2338	sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
	2339	jump_table = m68ki_instruction_jump_table[5];
	2340	cyc_instruction = m68ki_cycles[5];
	2341	cyc_exception = m68ki_exception_cycle_table[5];
	2342	cyc_bcc_notake_b = -2;
	2343	cyc_bcc_notake_w = 0;
	2344	cyc_dbcc_f_noexp = 0;
	2345	cyc_dbcc_f_exp = 4;
	2346	cyc_scc_r_true = 0;
	2347	cyc_movem_w = 2;
	2348	cyc_movem_l = 2;
	2349	cyc_shift = 0;
	2350	cyc_reset = 518;
	2351
	2352	m68340SIM = new m68340_sim();
	2353	m68340DMA = new m68340_dma();
	2354	m68340SERIAL = new m68340_serial();
	2355	m68340TIMER = new m68340_timer();
	2356
	2357	m68340SIM->reset();
	2358	m68340DMA->reset();
	2359	m68340SERIAL->reset();
	2360	m68340TIMER->reset();
	2361
	2362	m68340_base = 0x00000000;
	2363
	2364	internal = &this->space(AS_PROGRAM);
	2365
	2366	define_state();
2408	2367	}
2409	2368
2410		/****************************************************************************
2411		* M680EC20 section
2412		****************************************************************************/
2413	2369
2414		static CPU_INIT( m68ec020 )
	2370
	2371	void m68000_base_device::init_cpu_coldfire(void)
2415	2372	{
2416		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
	2373	init_cpu_common();
	2374
	2375	cpu_type = CPU_TYPE_COLDFIRE;
	2376	// dasm_type = M68K_CPU_TYPE_COLDFIRE;
2417	2377
2418		CPU_INIT_CALL(m68k);
	2378
	2379	init32(*program);
	2380	sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
	2381	jump_table = m68ki_instruction_jump_table[6];
	2382	cyc_instruction = m68ki_cycles[6];
	2383	cyc_exception = m68ki_exception_cycle_table[6];
	2384	cyc_bcc_notake_b = -2;
	2385	cyc_bcc_notake_w = 0;
	2386	cyc_dbcc_f_noexp = 0;
	2387	cyc_dbcc_f_exp = 4;
	2388	cyc_scc_r_true = 0;
	2389	cyc_movem_w = 2;
	2390	cyc_movem_l = 2;
	2391	cyc_shift = 0;
	2392	cyc_reset = 518;
2419	2393
2420		m68k->cpu_type = CPU_TYPE_EC020;
2421		m68k->dasm_type = M68K_CPU_TYPE_68EC020;
2422		// hack alert: we use placement new to ensure we are properly initialized
2423		// because we live in the device state which is allocated as bytes
2424		// remove me when we have a real C++ device
2425		new(&m68k->memory) m68k_memory_interface;
2426		m68k->memory.init32(*m68k->program);
2427		m68k->sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
2428		m68k->jump_table = m68ki_instruction_jump_table[2];
2429		m68k->cyc_instruction = m68ki_cycles[2];
2430		m68k->cyc_exception = m68ki_exception_cycle_table[2];
2431		m68k->cyc_bcc_notake_b = -2;
2432		m68k->cyc_bcc_notake_w = 0;
2433		m68k->cyc_dbcc_f_noexp = 0;
2434		m68k->cyc_dbcc_f_exp = 4;
2435		m68k->cyc_scc_r_true = 0;
2436		m68k->cyc_movem_w = 2;
2437		m68k->cyc_movem_l = 2;
2438		m68k->cyc_shift = 0;
2439		m68k->cyc_reset = 518;
2440		m68k->has_pmmu = 0;
2441		m68k->has_fpu = 0;
	2394	define_state();
	2395	}
2442	2396
2443		define_state(device);
	2397
	2398
	2399
	2400
	2401
	2402	/*
	2403	case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
	2404	case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
	2405
	2406	case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break;
	2407	case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
	2408
	2409	case CPUINFO_INT_INPUT_STATE + 0: info->i = 0; // there is no level 0
	2410	case CPUINFO_INT_INPUT_STATE + 1: info->i = (m68k->virq_state >> 1) & 1; break;
	2411	case CPUINFO_INT_INPUT_STATE + 2: info->i = (m68k->virq_state >> 2) & 1; break;
	2412	case CPUINFO_INT_INPUT_STATE + 3: info->i = (m68k->virq_state >> 3) & 1; break;
	2413	case CPUINFO_INT_INPUT_STATE + 4: info->i = (m68k->virq_state >> 4) & 1; break;
	2414	case CPUINFO_INT_INPUT_STATE + 5: info->i = (m68k->virq_state >> 5) & 1; break;
	2415	case CPUINFO_INT_INPUT_STATE + 6: info->i = (m68k->virq_state >> 6) & 1; break;
	2416	case CPUINFO_INT_INPUT_STATE + 7: info->i = (m68k->virq_state >> 7) & 1; break;
	2417
	2418	case CPUINFO_STR_FAMILY: strcpy(info->s, "Motorola 68K"); break;
	2419	case CPUINFO_STR_VERSION: strcpy(info->s, "4.95"); break;
	2420	case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
	2421	case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Karl Stenerud. All rights reserved. (2.1 fixes HJB, FPU+MMU by RB+HO+OG)"); break;
	2422
	2423
	2424	*/
	2425
	2426
	2427
	2428
	2429
	2430	CPU_DISASSEMBLE( dasm_m68000 )
	2431	{
	2432	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68000);
2444	2433	}
2445	2434
2446		CPU_~~GET_~~I~~NFO~~( m68ec020 )
	2435	CPU_DISASSEMBLE( dasm_m68008 )
2447	2436	{
2448		switch (state)
2449		{
2450		/* --- the following bits of info are returned as 64-bit signed integers --- */
2451		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break;
	2437	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68008);
	2438	}
2452	2439
2453		/* --- the following bits of info are returned as pointers to data or functions --- */
2454		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68ec020); break;
	2440	CPU_DISASSEMBLE( dasm_m68010 )
	2441	{
	2442	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68010);
	2443	}
2455	2444
2456		/* --- the following bits of info are returned as NULL-terminated strings --- */
2457		case CPUINFO_STR_NAME: strcpy(info->s, "68EC020"); break;
	2445	CPU_DISASSEMBLE( dasm_m68020 )
	2446	{
	2447	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68020);
	2448	}
2458	2449
2459		default: CPU_GET_INFO_CALL(m68020); break;
2460		}
	2450	CPU_DISASSEMBLE( dasm_m68030 )
	2451	{
	2452	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68030);
2461	2453	}
2462	2454
2463		/****************************************************************************
2464		* M68030 section
2465		****************************************************************************/
	2455	CPU_DISASSEMBLE( dasm_m68ec030 )
	2456	{
	2457	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68EC030);
	2458	}
2466	2459
2467		~~static~~ CPU_I~~NIT~~( m68030 )
	2460	CPU_DISASSEMBLE( dasm_m68040 )
2468	2461	{
2469		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
	2462	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68040);
	2463	}
2470	2464
2471		CPU_INIT_CALL(m68k);
	2465	CPU_DISASSEMBLE( dasm_m68ec040 )
	2466	{
	2467	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68EC040);
	2468	}
2472	2469
2473		m68k->cpu_type = CPU_TYPE_030;
2474		m68k->dasm_type = M68K_CPU_TYPE_68030;
2475		// hack alert: we use placement new to ensure we are properly initialized
2476		// because we live in the device state which is allocated as bytes
2477		// remove me when we have a real C++ device
2478		new(&m68k->memory) m68k_memory_interface;
2479		m68k->memory.init32mmu(*m68k->program);
2480		m68k->sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
2481		m68k->jump_table = m68ki_instruction_jump_table[3];
2482		m68k->cyc_instruction = m68ki_cycles[3];
2483		m68k->cyc_exception = m68ki_exception_cycle_table[3];
2484		m68k->cyc_bcc_notake_b = -2;
2485		m68k->cyc_bcc_notake_w = 0;
2486		m68k->cyc_dbcc_f_noexp = 0;
2487		m68k->cyc_dbcc_f_exp = 4;
2488		m68k->cyc_scc_r_true = 0;
2489		m68k->cyc_movem_w = 2;
2490		m68k->cyc_movem_l = 2;
2491		m68k->cyc_shift = 0;
2492		m68k->cyc_reset = 518;
2493		m68k->has_pmmu = 1;
2494		m68k->has_fpu = 1;
	2470	CPU_DISASSEMBLE( dasm_m68lc040 )
	2471	{
	2472	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68LC040);
	2473	}
2495	2474
2496		define_state(device);
	2475	CPU_DISASSEMBLE( dasm_m68340 )
	2476	{
	2477	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68340);
2497	2478	}
2498	2479
2499		CPU_~~GET_~~I~~NFO~~( m~~68030~~ )
	2480	CPU_DISASSEMBLE( dasm_coldfire )
2500	2481	{
2501		switch (state)
	2482	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_COLDFIRE);
	2483	}
	2484
	2485	offs_t m68000_base_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68000)(this, buffer, pc, oprom, opram, options); };
	2486	offs_t m68000_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68000)(this, buffer, pc, oprom, opram, options); };
	2487	offs_t m68301_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68000)(this, buffer, pc, oprom, opram, options); };
	2488	offs_t m68307_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68000)(this, buffer, pc, oprom, opram, options); };
	2489	offs_t m68008_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68008)(this, buffer, pc, oprom, opram, options); };
	2490	offs_t m68008plcc_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68008)(this, buffer, pc, oprom, opram, options); };
	2491	offs_t m68010_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68010)(this, buffer, pc, oprom, opram, options); };
	2492	offs_t m68ec020_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68020)(this, buffer, pc, oprom, opram, options); };
	2493	offs_t m68020_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68020)(this, buffer, pc, oprom, opram, options); };
	2494	offs_t m68020pmmu_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68020)(this, buffer, pc, oprom, opram, options); };
	2495	offs_t m68020hmmu_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68020)(this, buffer, pc, oprom, opram, options); };
	2496	offs_t m68ec030_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68ec030)(this, buffer, pc, oprom, opram, options); };
	2497	offs_t m68030_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68030)(this, buffer, pc, oprom, opram, options); };
	2498	offs_t m68ec040_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68ec040)(this, buffer, pc, oprom, opram, options); };
	2499	offs_t m68lc040_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68lc040)(this, buffer, pc, oprom, opram, options); };
	2500	offs_t m68040_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68040)(this, buffer, pc, oprom, opram, options); };
	2501	offs_t scc68070_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68000)(this, buffer, pc, oprom, opram, options); };
	2502	offs_t m68340_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_m68340)(this, buffer, pc, oprom, opram, options); };
	2503	offs_t mcf5206e_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options) { return CPU_DISASSEMBLE_NAME(dasm_coldfire)(this, buffer, pc, oprom, opram, options); };
	2504
	2505
	2506	/* Service an interrupt request and start exception processing */
	2507	void m68000_base_device::m68ki_exception_interrupt(m68000_base_device *m68k, UINT32 int_level)
	2508	{
	2509	UINT32 vector;
	2510	UINT32 sr;
	2511	UINT32 new_pc;
	2512
	2513	if(CPU_TYPE_IS_000(cpu_type))
2502	2514	{
2503		/* --- the following bits of info are returned as 64-bit signed integers --- */
2504		case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 20; break;
2505		case CPUINFO_INT_MIN_CYCLES: info->i = 2; break;
2506		case CPUINFO_INT_MAX_CYCLES: info->i = 158; break;
	2515	instr_mode = INSTRUCTION_NO;
	2516	}
2507	2517
2508		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 32; break;
2509		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break;
	2518	/* Turn off the stopped state */
	2519	stopped &= ~STOP_LEVEL_STOP;
2510	2520
2511		/* --- the following bits of info are returned as pointers to data or functions --- */
2512		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68030); break;
	2521	/* If we are halted, don't do anything */
	2522	if(stopped)
	2523	return;
2513	2524
2514		/* --- the following bits of info are returned as NULL-terminated strings --- */
2515		case CPUINFO_STR_NAME: strcpy(info->s, "68030"); break;
	2525	/* Acknowledge the interrupt */
	2526	vector = (*int_ack_callback)(this, int_level);
	2527
	2528	/* Get the interrupt vector */
	2529	if(vector == M68K_INT_ACK_AUTOVECTOR)
	2530	/* Use the autovectors. This is the most commonly used implementation */
	2531	vector = EXCEPTION_INTERRUPT_AUTOVECTOR+int_level;
	2532	else if(vector == M68K_INT_ACK_SPURIOUS)
	2533	/* Called if no devices respond to the interrupt acknowledge */
	2534	vector = EXCEPTION_SPURIOUS_INTERRUPT;
	2535	else if(vector > 255)
	2536	return;
2516	2537
2517		default: CPU_GET_INFO_CALL(m68k); break;
	2538	/* Start exception processing */
	2539	sr = m68ki_init_exception(m68k);
	2540
	2541	/* Set the interrupt mask to the level of the one being serviced */
	2542	int_mask = int_level<<8;
	2543
	2544	/* Get the new PC */
	2545	new_pc = m68ki_read_data_32(this, (vector<<2) + vbr);
	2546
	2547	/* If vector is uninitialized, call the uninitialized interrupt vector */
	2548	if(new_pc == 0)
	2549	new_pc = m68ki_read_data_32(this, (EXCEPTION_UNINITIALIZED_INTERRUPT<<2) + vbr);
	2550
	2551	/* Generate a stack frame */
	2552	m68ki_stack_frame_0000(this, REG_PC(m68k), sr, vector);
	2553	if(m_flag && CPU_TYPE_IS_EC020_PLUS(cpu_type))
	2554	{
	2555	/* Create throwaway frame */
	2556	m68ki_set_sm_flag(this, s_flag); /* clear M */
	2557	sr \|= 0x2000; /* Same as SR in master stack frame except S is forced high */
	2558	m68ki_stack_frame_0001(this, REG_PC(m68k), sr, vector);
2518	2559	}
	2560
	2561	m68ki_jump(this, new_pc);
	2562
	2563	/* Defer cycle counting until later */
	2564	remaining_cycles -= cyc_exception[vector];
2519	2565	}
2520	2566
2521	2567
2522		/****************************************************************************
2523		* M680EC30 section
2524		****************************************************************************/
	2568	const device_type M68K = &device_creator<m68000_base_device>;
2525	2569
2526		static CPU_INIT( m68ec030 )
	2570	//-------------------------------------------------
	2571	// h6280_device - constructor
	2572	//-------------------------------------------------
	2573
	2574	m68000_base_device::m68000_base_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	2575	: cpu_device(mconfig, M68K, "M68K", tag, owner, clock, "m68k", __FILE__),
	2576	m_program_config("program", ENDIANNESS_BIG, 16, 24)
2527	2577	{
2528		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
	2578	clear_all();
	2579	}
2529	2580
2530		CPU_INIT_CALL(m68k);
2531	2581
2532		m68k->cpu_type = CPU_TYPE_EC030;
2533		m68k->dasm_type = M68K_CPU_TYPE_68EC030;
2534		// hack alert: we use placement new to ensure we are properly initialized
2535		// because we live in the device state which is allocated as bytes
2536		// remove me when we have a real C++ device
2537		new(&m68k->memory) m68k_memory_interface;
2538		m68k->memory.init32(*m68k->program);
2539		m68k->sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
2540		m68k->jump_table = m68ki_instruction_jump_table[3];
2541		m68k->cyc_instruction = m68ki_cycles[3];
2542		m68k->cyc_exception = m68ki_exception_cycle_table[3];
2543		m68k->cyc_bcc_notake_b = -2;
2544		m68k->cyc_bcc_notake_w = 0;
2545		m68k->cyc_dbcc_f_noexp = 0;
2546		m68k->cyc_dbcc_f_exp = 4;
2547		m68k->cyc_scc_r_true = 0;
2548		m68k->cyc_movem_w = 2;
2549		m68k->cyc_movem_l = 2;
2550		m68k->cyc_shift = 0;
2551		m68k->cyc_reset = 518;
2552		m68k->has_pmmu = 0; /* EC030 lacks the PMMU and is effectively a die-shrink 68020 */
2553		m68k->has_fpu = 1;
2554	2582
2555		define_state(device);
	2583
	2584	m68000_base_device::m68000_base_device(const machine_config &mconfig, const char name, const char tag, device_t *owner, UINT32 clock,
	2585	const device_type type, UINT32 prg_data_width, UINT32 prg_address_bits, address_map_constructor internal_map, const char shortname, const char source)
	2586	: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source),
	2587	m_program_config("program", ENDIANNESS_BIG, prg_data_width, prg_address_bits, 0, internal_map)
	2588	{
	2589	clear_all();
2556	2590	}
2557	2591
2558		CPU_GET_INFO( m68ec030 )
	2592
	2593	m68000_base_device::m68000_base_device(const machine_config &mconfig, const char name, const char tag, device_t *owner, UINT32 clock,
	2594	const device_type type, UINT32 prg_data_width, UINT32 prg_address_bits, const char shortname, const char source)
	2595	: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source),
	2596	m_program_config("program", ENDIANNESS_BIG, prg_data_width, prg_address_bits)
2559	2597	{
2560		switch (state)
2561		{
2562		/* --- the following bits of info are returned as pointers to data or functions --- */
2563		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68ec030); break;
	2598	clear_all();
	2599	}
2564	2600
2565		/* --- the following bits of info are returned as NULL-terminated strings --- */
2566		case CPUINFO_STR_NAME: strcpy(info->s, "68EC030"); break;
	2601	void m68000_base_device::clear_all()
	2602	{
2567	2603
2568		default: CPU_GET_INFO_CALL(m68030); break;
2569		}
	2604	cpu_type= 0;
	2605	// dasm_type= 0;
	2606	for (int i=0;i<16;i++)
	2607	dar[i]= 0;
	2608	ppc= 0;
	2609	pc= 0;
	2610	for (int i=0;i<7;i++)
	2611	sp[i]= 0;
	2612	vbr= 0;
	2613	sfc= 0;
	2614	dfc= 0;
	2615	cacr= 0;
	2616	caar= 0;
	2617	ir= 0;
	2618	// for (int i=0;i<8;i++)
	2619	// fpr[i]= 0;
	2620	fpiar= 0;
	2621	fpsr= 0;
	2622	fpcr= 0;
	2623	t1_flag= 0;
	2624	t0_flag= 0;
	2625	s_flag= 0;
	2626	m_flag= 0;
	2627	x_flag= 0;
	2628	n_flag= 0;
	2629	not_z_flag= 0;
	2630	v_flag= 0;
	2631	c_flag= 0;
	2632	int_mask= 0;
	2633	int_level= 0;
	2634	stopped= 0;
	2635	pref_addr= 0;
	2636	pref_data= 0;
	2637	sr_mask= 0;
	2638	instr_mode= 0;
	2639	run_mode= 0;
	2640	has_pmmu= 0;
	2641	has_hmmu= 0;
	2642	pmmu_enabled= 0;
	2643	hmmu_enabled= 0;
	2644	has_fpu= 0;
	2645	fpu_just_reset= 0;
	2646
	2647	cyc_bcc_notake_b = 0;
	2648	cyc_bcc_notake_w = 0;
	2649	cyc_dbcc_f_noexp = 0;
	2650	cyc_dbcc_f_exp = 0;
	2651	cyc_scc_r_true = 0;
	2652	cyc_movem_w = 0;
	2653	cyc_movem_l = 0;
	2654	cyc_shift = 0;
	2655	cyc_reset = 0;
	2656
	2657	initial_cycles = 0;
	2658	remaining_cycles = 0;
	2659	reset_cycles = 0;
	2660	tracing = 0;
	2661
	2662	// aerr_trap = 0;
	2663
	2664	aerr_address = 0;
	2665	aerr_write_mode = 0;
	2666	aerr_fc = 0;
	2667
	2668	virq_state = 0;
	2669	nmi_pending = 0;
	2670
	2671	cyc_instruction = 0;
	2672	cyc_exception = 0;
	2673
	2674	int_ack_callback = 0;
	2675	bkpt_ack_callback = 0;
	2676	reset_instr_callback = 0;
	2677	cmpild_instr_callback = 0;
	2678	rte_instr_callback = 0;
	2679	tas_instr_callback = 0;
	2680
	2681	program = 0;
	2682
	2683	opcode_xor = 0;
	2684	// readimm16 = 0;
	2685	// read8 = 0;
	2686	// read16 = 0;
	2687	// read32 = 0;
	2688	// write8 = 0;
	2689	// write16 = 0;
	2690	// write32 = 0;
	2691
	2692	m_space = 0;
	2693	m_direct = 0;
	2694
	2695
	2696	encrypted_start = 0;
	2697	encrypted_end = 0;
	2698
	2699	iotemp = 0;
	2700
	2701	save_sr = 0;
	2702	save_stopped = 0;
	2703	save_halted = 0;
	2704
	2705
	2706	mmu_crp_aptr = mmu_crp_limit = 0;
	2707	mmu_srp_aptr = mmu_srp_limit = 0;
	2708	mmu_urp_aptr = 0;
	2709	mmu_tc = 0;
	2710	mmu_sr = 0;
	2711	mmu_sr_040 = 0;
	2712
	2713	for (int i=0; i<MMU_ATC_ENTRIES;i++)
	2714	mmu_atc_tag[i] = mmu_atc_data[i] = 0;
	2715
	2716	mmu_atc_rr = 0;
	2717	mmu_tt0 = mmu_tt1 = 0;
	2718	mmu_itt0 = mmu_itt1 = mmu_dtt0 = mmu_dtt1 = 0;
	2719	mmu_acr0= mmu_acr1 = mmu_acr2 = mmu_acr3 = 0;
	2720	mmu_tmp_sr = 0;
	2721	mmu_tmp_fc = 0;
	2722	mmu_tmp_rw = 0;
	2723	mmu_tmp_buserror_address = 0;
	2724	mmu_tmp_buserror_occurred = 0;
	2725	mmu_tmp_buserror_fc = 0;
	2726	mmu_tmp_buserror_rw = 0;
	2727
	2728	for (int i=0;i<M68K_IC_SIZE;i++)
	2729	ic_address[i] = 0;
	2730
	2731	for (int i=0;i<M68K_IC_SIZE;i++)
	2732	ic_data[i] = 0;
	2733
	2734	m68307SIM = 0;
	2735	m68307MBUS = 0;
	2736	m68307SERIAL = 0;
	2737	m68307TIMER = 0;
	2738	m68307_base = 0;
	2739	m68307_scrhigh = 0;
	2740	m68307_scrlow = 0;
	2741	m68307_currentcs = 0;
	2742	m68340SIM = 0;
	2743	m68340DMA = 0;
	2744	m68340SERIAL = 0;
	2745	m68340TIMER = 0;
	2746	m68340_base = 0;
	2747	internal = 0;
	2748	m_m68307_porta_r = 0;
	2749	m_m68307_porta_w = 0;
	2750	m_m68307_portb_r = 0;
	2751	m_m68307_portb_w = 0;
	2752	instruction_hook = 0;
2570	2753	}
2571	2754
2572		/****************************************************************************
2573		* M68040 section
2574		****************************************************************************/
2575	2755
2576		~~stat~~ic ~~CPU_INIT(~~ m68040 )
	2756	void m68000_base_device::execute_run()
2577	2757	{
2578		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
	2758	cpu_execute();
	2759	}
2579	2760
2580		CPU_INIT_CALL(m68k);
	2761	void m68000_base_device::device_start()
	2762	{
2581	2763
2582		m68k->cpu_type = CPU_TYPE_040;
2583		m68k->dasm_type = M68K_CPU_TYPE_68040;
2584		// hack alert: we use placement new to ensure we are properly initialized
2585		// because we live in the device state which is allocated as bytes
2586		// remove me when we have a real C++ device
2587		new(&m68k->memory) m68k_memory_interface;
2588		m68k->memory.init32mmu(*m68k->program);
2589		m68k->sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
2590		m68k->jump_table = m68ki_instruction_jump_table[4];
2591		m68k->cyc_instruction = m68ki_cycles[4];
2592		m68k->cyc_exception = m68ki_exception_cycle_table[4];
2593		m68k->cyc_bcc_notake_b = -2;
2594		m68k->cyc_bcc_notake_w = 0;
2595		m68k->cyc_dbcc_f_noexp = 0;
2596		m68k->cyc_dbcc_f_exp = 4;
2597		m68k->cyc_scc_r_true = 0;
2598		m68k->cyc_movem_w = 2;
2599		m68k->cyc_movem_l = 2;
2600		m68k->cyc_shift = 0;
2601		m68k->cyc_reset = 518;
2602		m68k->has_pmmu = 1;
2603		m68k->has_fpu = 1;
	2764	}
2604	2765
2605		define_state(device);
	2766	void m68000_base_device::device_reset()
	2767	{
	2768	reset_cpu();
2606	2769	}
2607	2770
2608		~~CPU_GET_INFO(~~ m68040 )
	2771	void m68000_base_device::device_stop()
2609	2772	{
2610		switch (state)
2611		{
2612		/* --- the following bits of info are returned as 64-bit signed integers --- */
2613		case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 20; break;
2614		case CPUINFO_INT_MIN_CYCLES: info->i = 2; break;
2615		case CPUINFO_INT_MAX_CYCLES: info->i = 158; break;
2616	2773
2617		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 32; break;
2618		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break;
	2774	}
2619	2775
2620		/* --- the following bits of info are returned as pointers to data or functions --- */
2621		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68040); break;
2622	2776
2623		/* --- the following bits of info are returned as NULL-terminated strings --- */
2624		case CPUINFO_STR_NAME: strcpy(info->s, "68040"); break;
2625	2777
2626		default: CPU_GET_INFO_CALL(m68k); break;
	2778
	2779	void m68000_base_device::execute_set_input(int inputnum, int state)
	2780	{
	2781	switch (inputnum)
	2782	{
	2783	/* --- the following bits of info are set as 64-bit signed integers --- */
	2784	case M68K_IRQ_NONE:
	2785	case M68K_IRQ_1:
	2786	case M68K_IRQ_2:
	2787	case M68K_IRQ_3:
	2788	case M68K_IRQ_4:
	2789	case M68K_IRQ_5:
	2790	case M68K_IRQ_6:
	2791	case M68K_IRQ_7:
	2792	case INPUT_LINE_NMI:
	2793	set_irq_line(this, inputnum, state);
	2794	break;
	2795
	2796	case M68K_LINE_BUSERROR:
	2797	if (state == ASSERT_LINE)
	2798	{
	2799	m68k_cause_bus_error(this);
	2800	}
	2801	break;
2627	2802	}
2628	2803	}
2629	2804
2630		/****************************************************************************
2631		* M68EC040 section
2632		****************************************************************************/
2633	2805
2634		static ~~CPU~~_~~INIT(~~ m68ec040 )
	2806	const address_space_config *m68000_base_device::memory_space_config(address_spacenum spacenum) const
2635	2807	{
2636		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
	2808	if (spacenum == AS_PROGRAM)
	2809	{
	2810	return &m_program_config;
	2811	}
2637	2812
2638		CPU_INIT_CALL(m68k);
	2813	return NULL;
	2814	}
2639	2815
2640		m68k->cpu_type = CPU_TYPE_EC040;
2641		m68k->dasm_type = M68K_CPU_TYPE_68EC040;
2642		// hack alert: we use placement new to ensure we are properly initialized
2643		// because we live in the device state which is allocated as bytes
2644		// remove me when we have a real C++ device
2645		new(&m68k->memory) m68k_memory_interface;
2646		m68k->memory.init32(*m68k->program);
2647		m68k->sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
2648		m68k->jump_table = m68ki_instruction_jump_table[4];
2649		m68k->cyc_instruction = m68ki_cycles[4];
2650		m68k->cyc_exception = m68ki_exception_cycle_table[4];
2651		m68k->cyc_bcc_notake_b = -2;
2652		m68k->cyc_bcc_notake_w = 0;
2653		m68k->cyc_dbcc_f_noexp = 0;
2654		m68k->cyc_dbcc_f_exp = 4;
2655		m68k->cyc_scc_r_true = 0;
2656		m68k->cyc_movem_w = 2;
2657		m68k->cyc_movem_l = 2;
2658		m68k->cyc_shift = 0;
2659		m68k->cyc_reset = 518;
2660		m68k->has_pmmu = 0;
2661		m68k->has_fpu = 0;
2662	2816
2663		define_state(device);
	2817
	2818	const device_type M68000 = &device_creator<m68000_device>;
	2819	const device_type M68301 = &device_creator<m68301_device>;
	2820	const device_type M68307 = &device_creator<m68307_device>;
	2821	const device_type M68008 = &device_creator<m68008_device>;
	2822	const device_type M68008PLCC = &device_creator<m68008plcc_device>;
	2823	const device_type M68010 = &device_creator<m68010_device>;
	2824	const device_type M68EC020 = &device_creator<m68ec020_device>;
	2825	const device_type M68020 = &device_creator<m68020_device>;
	2826	const device_type M68020PMMU = &device_creator<m68020pmmu_device>;
	2827	const device_type M68020HMMU = &device_creator<m68020hmmu_device>;
	2828	const device_type M68EC030 = &device_creator<m68ec030_device>;
	2829	const device_type M68030 = &device_creator<m68030_device>;
	2830	const device_type M68EC040 = &device_creator<m68ec040_device>;
	2831	const device_type M68LC040 = &device_creator<m68lc040_device>;
	2832	const device_type M68040 = &device_creator<m68040_device>;
	2833	const device_type SCC68070 = &device_creator<scc68070_device>;
	2834	const device_type M68340 = &device_creator<m68340_device>;
	2835	const device_type MCF5206E = &device_creator<mcf5206e_device>;
	2836
	2837	m68000_device::m68000_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	2838	: m68000_base_device(mconfig, "M68000", tag, owner, clock, M68000, 16,24, "m68000", __FILE__)
	2839	{
	2840
2664	2841	}
2665	2842
2666		~~CPU_GET_INFO(~~ m68ec040 )
	2843	void m68000_device::device_start()
2667	2844	{
2668		switch (state)
2669		{
2670		/* --- the following bits of info are returned as pointers to data or functions --- */
2671		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68ec040); break;
	2845	init_cpu_m68000();
	2846	}
2672	2847
2673		/* --- the following bits of info are returned as NULL-terminated strings --- */
2674		case CPUINFO_STR_NAME: strcpy(info->s, "68EC040"); break;
2675	2848
2676		default: CPU_GET_INFO_CALL(m68040); break;
2677		}
	2849
	2850
	2851	m68301_device::m68301_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	2852	: m68000_base_device(mconfig, "M68301", tag, owner, clock, M68301, 16,24, "m68301", __FILE__)
	2853	{
	2854
2678	2855	}
2679	2856
2680		/****************************************************************************
2681		* M68LC040 section
2682		****************************************************************************/
2683	2857
2684		~~stat~~ic ~~CPU_INIT(~~ m68lc040 )
	2858	void m68301_device::device_start()
2685	2859	{
2686		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
	2860	init_cpu_m68000();
	2861	}
2687	2862
2688		CPU_INIT_CALL(m68k);
2689	2863
2690		m68k->cpu_type = CPU_TYPE_LC040;
2691		m68k->dasm_type = M68K_CPU_TYPE_68LC040;
2692		// hack alert: we use placement new to ensure we are properly initialized
2693		// because we live in the device state which is allocated as bytes
2694		// remove me when we have a real C++ device
2695		new(&m68k->memory) m68k_memory_interface;
2696		m68k->memory.init32mmu(*m68k->program);
2697		m68k->sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
2698		m68k->jump_table = m68ki_instruction_jump_table[4];
2699		m68k->cyc_instruction = m68ki_cycles[4];
2700		m68k->cyc_exception = m68ki_exception_cycle_table[4];
2701		m68k->cyc_bcc_notake_b = -2;
2702		m68k->cyc_bcc_notake_w = 0;
2703		m68k->cyc_dbcc_f_noexp = 0;
2704		m68k->cyc_dbcc_f_exp = 4;
2705		m68k->cyc_scc_r_true = 0;
2706		m68k->cyc_movem_w = 2;
2707		m68k->cyc_movem_l = 2;
2708		m68k->cyc_shift = 0;
2709		m68k->cyc_reset = 518;
2710		m68k->has_pmmu = 1;
2711		m68k->has_fpu = 0;
2712	2864
2713		define_state(device);
	2865
	2866	m68307_device::m68307_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	2867	: m68000_base_device(mconfig, "M68307", tag, owner, clock, M68307, 16,24, ADDRESS_MAP_NAME(m68307_internal_map), "m68307", __FILE__)
	2868	{
	2869
2714	2870	}
2715	2871
2716		~~CPU_GET_INFO(~~ m68lc040 )
	2872	void m68307_device::device_start()
2717	2873	{
2718		switch (state)
2719		{
2720		/* --- the following bits of info are returned as pointers to data or functions --- */
2721		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68lc040); break;
	2874	init_cpu_m68307();
	2875	}
2722	2876
2723		/* --- the following bits of info are returned as NULL-terminated strings --- */
2724		case CPUINFO_STR_NAME: strcpy(info->s, "68LC040"); break;
	2877	/* m68008_device */
2725	2878
2726		default: CPU_GET_INFO_CALL(m68040); break;
2727		}
	2879	m68008_device::m68008_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	2880	: m68000_base_device(mconfig, "M68008", tag, owner, clock, M68008, 8,20, "m68008", __FILE__)
	2881	{
	2882
2728	2883	}
2729	2884
2730		/****************************************************************************
2731		* SCC-68070 section
2732		****************************************************************************/
	2885	void m68008_device::device_start()
	2886	{
	2887	init_cpu_m68008();
	2888	}
2733	2889
2734		static CPU_INIT( scc68070 )
	2890
	2891	m68008plcc_device::m68008plcc_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	2892	: m68000_base_device(mconfig, "M68008PLCC", tag, owner, clock, M68008, 8,22, "m68008plcc", __FILE__)
2735	2893	{
2736		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
2737	2894
2738		~~CPU_INIT_CALL(m68010);~~
	2895	}
2739	2896
2740		m68k->cpu_type = CPU_TYPE_SCC070;
	2897	void m68008plcc_device::device_start()
	2898	{
	2899	init_cpu_m68008();
2741	2900	}
2742	2901
2743		CPU_GET_INFO( scc68070 )
	2902
	2903
	2904	m68010_device::m68010_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	2905	: m68000_base_device(mconfig, "M68010", tag, owner, clock, M68010, 16,24, "m68010", __FILE__)
2744	2906	{
2745		switch (state)
2746		{
2747		/* --- the following bits of info are returned as 64-bit signed integers --- */
2748		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break;
2749	2907
2750		/* --- the following bits of info are returned as pointers to data or functions --- */
2751		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(scc68070); break;
	2908	}
2752	2909
2753		/* --- the following bits of info are returned as NULL-terminated strings --- */
2754		case CPUINFO_STR_NAME: strcpy(info->s, "SCC68070"); break;
	2910	void m68010_device::device_start()
	2911	{
	2912	init_cpu_m68010();
	2913	}
2755	2914
2756		default: CPU_GET_INFO_CALL(m68k); break;
2757		}
	2915
	2916
	2917	m68020_device::m68020_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	2918	: m68000_base_device(mconfig, "M68020", tag, owner, clock, M68020, 32,32, "m68020", __FILE__)
	2919	{
	2920
2758	2921	}
2759	2922
2760		/****************************************************************************
2761		* Freescale M68340 section
2762		****************************************************************************/
	2923	void m68020_device::device_start()
	2924	{
	2925	init_cpu_m68020();
	2926	}
2763	2927
2764		static READ32_HANDLER( m68340_internal_base_r )
	2928	// 68020 with 68851 PMMU
	2929	m68020pmmu_device::m68020pmmu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	2930	: m68000_base_device(mconfig, "M68020PMMU", tag, owner, clock, M68020PMMU, 32,32, "m68020pmmu", __FILE__)
2765	2931	{
2766		m68ki_cpu_core *m68k = m68k_get_safe_token(&space.device());
2767		int pc = space.device().safe_pc();
2768		logerror("%08x m68340_internal_base_r %08x, (%08x)\n", pc, offset*4,mem_mask);
2769		return m68k->m68340_base;
	2932
2770	2933	}
2771	2934
2772		~~stat~~ic ~~WRITE32_HANDLER(~~ m68340_inte~~rnal_bas~~e_w )
	2935	void m68020pmmu_device::device_start()
2773	2936	{
2774		m68ki_cpu_core *m68k = m68k_get_safe_token(&space.device());
	2937	init_cpu_m68020pmmu();
	2938	}
2775	2939
2776		int pc = space.device().safe_pc();
2777		logerror("%08x m68340_internal_base_w %08x, %08x (%08x)\n", pc, offset*4,data,mem_mask);
2778
2779		// other conditions?
2780		if (m68k->dfc==0x7)
	2940	bool m68020hmmu_device::memory_translate(address_spacenum space, int intention, offs_t &address)
	2941	{
	2942	/* only applies to the program address space and only does something if the MMU's enabled */
	2943	if (this)
2781	2944	{
2782		// unmap old modules
2783		if (m68k->m68340_base&1)
	2945	if ((space == AS_PROGRAM) && (hmmu_enabled))
2784	2946	{
2785		int base = m68k->m68340_base & 0xfffff000;
	2947	address = hmmu_translate_addr(this, address);
	2948	}
	2949	}
	2950	return TRUE;
	2951	}
2786	2952
2787		m68k->internal->unmap_readwrite(base + 0x000, base + 0x05f);
2788		m68k->internal->unmap_readwrite(base + 0x600, base + 0x67f);
2789		m68k->internal->unmap_readwrite(base + 0x700, base + 0x723);
2790		m68k->internal->unmap_readwrite(base + 0x780, base + 0x7bf);
2791	2953
2792		}
	2954	// 68020 with Apple HMMU & 68881 FPU
	2955	// case CPUINFO_FCT_TRANSLATE: info->translate = CPU_TRANSLATE_NAME(m68khmmu); break;
	2956	m68020hmmu_device::m68020hmmu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	2957	: m68000_base_device(mconfig, "M68020HMMU", tag, owner, clock, M68020HMMU, 32,32, "m68020hmmu", __FILE__)
	2958	{
2793	2959
2794		COMBINE_DATA(&m68k->m68340_base);
2795		logerror("%08x m68340_internal_base_w %08x, %08x (%08x) (m68340_base write)\n", pc, offset*4,data,mem_mask);
	2960	}
2796	2961
2797		// map new modules
2798		if (m68k->m68340_base&1)
2799		{
2800		int base = m68k->m68340_base & 0xfffff000;
	2962	void m68020hmmu_device::device_start()
	2963	{
	2964	init_cpu_m68020hmmu();
	2965	}
2801	2966
2802		m68k->internal->install_legacy_readwrite_handler(base + 0x000, base + 0x03f, FUNC(m68340_internal_sim_r), FUNC(m68340_internal_sim_w),0xffffffff);
2803		m68k->internal->install_legacy_readwrite_handler(base + 0x010, base + 0x01f, FUNC(m68340_internal_sim_ports_r), FUNC(m68340_internal_sim_ports_w),0xffffffff);
2804		m68k->internal->install_legacy_readwrite_handler(base + 0x040, base + 0x05f, FUNC(m68340_internal_sim_cs_r), FUNC(m68340_internal_sim_cs_w));
2805		m68k->internal->install_legacy_readwrite_handler(base + 0x600, base + 0x67f, FUNC(m68340_internal_timer_r), FUNC(m68340_internal_timer_w));
2806		m68k->internal->install_legacy_readwrite_handler(base + 0x700, base + 0x723, FUNC(m68340_internal_serial_r), FUNC(m68340_internal_serial_w));
2807		m68k->internal->install_legacy_readwrite_handler(base + 0x780, base + 0x7bf, FUNC(m68340_internal_dma_r), FUNC(m68340_internal_dma_w));
2808	2967
2809		}
	2968	m68ec020_device::m68ec020_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	2969	: m68000_base_device(mconfig, "M68EC020", tag, owner, clock, M68EC020, 32,24, "m68ec020", __FILE__)
	2970	{
2810	2971
2811		}
2812		else
2813		{
2814		logerror("%08x m68340_internal_base_w %08x, %04x (%04x) (should fall through?)\n", pc, offset*4,data,mem_mask);
2815		}
	2972	}
2816	2973
	2974	void m68ec020_device::device_start()
	2975	{
	2976	init_cpu_m68ec020();
	2977	}
2817	2978
	2979	m68030_device::m68030_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	2980	: m68000_base_device(mconfig, "M68030", tag, owner, clock, M68030, 32,32, "m68030", __FILE__)
	2981	{
2818	2982
2819	2983	}
2820	2984
	2985	void m68030_device::device_start()
	2986	{
	2987	init_cpu_m68030();
	2988	}
2821	2989
2822		static ADDRESS_MAP_START( m68340_internal_map, AS_PROGRAM, 32, legacy_cpu_device )
2823		AM_RANGE(0x0003ff00, 0x0003ff03) AM_READWRITE_LEGACY( m68340_internal_base_r, m68340_internal_base_w)
2824		ADDRESS_MAP_END
	2990	m68ec030_device::m68ec030_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	2991	: m68000_base_device(mconfig, "M68EC030", tag, owner, clock, M68EC030, 32,32, "m68ec030", __FILE__)
	2992	{
2825	2993
2826		static CPU_INIT( m68340 )
	2994	}
	2995
	2996	void m68ec030_device::device_start()
2827	2997	{
2828		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
	2998	init_cpu_m68ec030();
	2999	}
2829	3000
2830		CPU_INIT_CALL(m68k);
	3001	m68040_device::m68040_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	3002	: m68000_base_device(mconfig, "M68040", tag, owner, clock, M68040, 32,32, "m68040", __FILE__)
	3003	{
2831	3004
2832		m68k->cpu_type = CPU_TYPE_68340;
2833		m68k->dasm_type = M68K_CPU_TYPE_68340;
2834		// hack alert: we use placement new to ensure we are properly initialized
2835		// because we live in the device state which is allocated as bytes
2836		// remove me when we have a real C++ device
2837		new(&m68k->memory) m68k_memory_interface;
2838		m68k->memory.init32(*m68k->program);
2839		m68k->sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
2840		m68k->jump_table = m68ki_instruction_jump_table[5];
2841		m68k->cyc_instruction = m68ki_cycles[5];
2842		m68k->cyc_exception = m68ki_exception_cycle_table[5];
2843		m68k->cyc_bcc_notake_b = -2;
2844		m68k->cyc_bcc_notake_w = 0;
2845		m68k->cyc_dbcc_f_noexp = 0;
2846		m68k->cyc_dbcc_f_exp = 4;
2847		m68k->cyc_scc_r_true = 0;
2848		m68k->cyc_movem_w = 2;
2849		m68k->cyc_movem_l = 2;
2850		m68k->cyc_shift = 0;
2851		m68k->cyc_reset = 518;
	3005	}
2852	3006
2853		m68k->m68340SIM = new m68340_sim();
2854		m68k->m68340DMA = new m68340_dma();
2855		m68k->m68340SERIAL = new m68340_serial();
2856		m68k->m68340TIMER = new m68340_timer();
2857	3007
2858		m68k->m68340SIM->reset();
2859		m68k->m68340DMA->reset();
2860		m68k->m68340SERIAL->reset();
2861		m68k->m68340TIMER->reset();
	3008	void m68040_device::device_start()
	3009	{
	3010	init_cpu_m68040();
	3011	}
2862	3012
2863		m68k->m68340_base = 0x00000000;
2864	3013
2865		m68k->internal = &device->space(AS_PROGRAM);
2866	3014
2867		define_state(device);
	3015	m68ec040_device::m68ec040_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	3016	: m68000_base_device(mconfig, "M68EC040", tag, owner, clock, M68EC040, 32,32, "m68ec040", __FILE__)
	3017	{
	3018
2868	3019	}
2869	3020
2870		~~CPU_GET_INFO(~~ m68340 )
	3021	void m68ec040_device::device_start()
2871	3022	{
2872		switch (state)
2873		{
2874		/* --- the following bits of info are returned as 64-bit signed integers --- */
2875		case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 20; break;
2876		case CPUINFO_INT_MIN_CYCLES: info->i = 2; break;
2877		case CPUINFO_INT_MAX_CYCLES: info->i = 158; break;
	3023	init_cpu_m68ec040();
	3024	}
2878	3025
2879		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 32; break;
2880		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break;
2881	3026
2882		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map32 = ADDRESS_MAP_NAME(m68340_internal_map); break;
2883	3027
2884		/* --- the following bits of info are returned as pointers to data or functions --- */
2885		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(m68340); break;
	3028	m68lc040_device::m68lc040_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	3029	: m68000_base_device(mconfig, "M68LC040", tag, owner, clock, M68LC040, 32,32, "m68lc040", __FILE__)
	3030	{
2886	3031
2887		/* --- the following bits of info are returned as NULL-terminated strings --- */
2888		case CPUINFO_STR_NAME: strcpy(info->s, "Freescale 68340"); break;
	3032	}
2889	3033
2890		default: CPU_GET_INFO_CALL(m68k); break;
2891		}
	3034	void m68lc040_device::device_start()
	3035	{
	3036	init_cpu_m68lc040();
2892	3037	}
2893	3038
2894		/*
2895		ColdFire
2896	3039
2897		*/
	3040	scc68070_device::scc68070_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	3041	: m68000_base_device(mconfig, "SCC68070", tag, owner, clock, SCC68070, 16,32, "scc68070", __FILE__)
	3042	{
2898	3043
2899		static CPU_INIT( coldfire )
	3044	}
	3045
	3046	void scc68070_device::device_start()
2900	3047	{
2901		m68ki_cpu_core *m68k = m68k_get_safe_token(device);
	3048	init_cpu_scc68070();
	3049	}
2902	3050
2903		CPU_INIT_CALL(m68k);
2904	3051
2905		m68k->cpu_type = CPU_TYPE_COLDFIRE;
2906		m68k->dasm_type = M68K_CPU_TYPE_COLDFIRE;
2907		// hack alert: we use placement new to ensure we are properly initialized
2908		// because we live in the device state which is allocated as bytes
2909		// remove me when we have a real C++ device
2910		new(&m68k->memory) m68k_memory_interface;
2911		m68k->memory.init32(*m68k->program);
2912		m68k->sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
2913		m68k->jump_table = m68ki_instruction_jump_table[6];
2914		m68k->cyc_instruction = m68ki_cycles[6];
2915		m68k->cyc_exception = m68ki_exception_cycle_table[6];
2916		m68k->cyc_bcc_notake_b = -2;
2917		m68k->cyc_bcc_notake_w = 0;
2918		m68k->cyc_dbcc_f_noexp = 0;
2919		m68k->cyc_dbcc_f_exp = 4;
2920		m68k->cyc_scc_r_true = 0;
2921		m68k->cyc_movem_w = 2;
2922		m68k->cyc_movem_l = 2;
2923		m68k->cyc_shift = 0;
2924		m68k->cyc_reset = 518;
	3052	m68340_device::m68340_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	3053	: m68000_base_device(mconfig, "M68340", tag, owner, clock, M68340, 32,32, ADDRESS_MAP_NAME(m68340_internal_map), "m68340", __FILE__)
	3054	{
2925	3055
2926		define_state(device);
2927	3056	}
2928	3057
2929		~~CPU_GET_INFO(~~ m~~cf520~~6e )
	3058	void m68340_device::device_start()
2930	3059	{
2931		switch (state)
2932		{
2933		/* --- the following bits of info are returned as 64-bit signed integers --- */
2934		case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 20; break;
2935		case CPUINFO_INT_MIN_CYCLES: info->i = 2; break;
2936		case CPUINFO_INT_MAX_CYCLES: info->i = 158; break;
	3060	init_cpu_m68340();
	3061	}
2937	3062
2938		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 32; break;
2939		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break;
2940	3063
2941		/* --- the following bits of info are returned as pointers to data or functions --- */
2942		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(coldfire); break;
2943	3064
2944		/* --- the following bits of info are returned as NULL-terminated strings --- */
2945		case CPUINFO_STR_NAME: strcpy(info->s, "MCF5206E"); break;
	3065	mcf5206e_device::mcf5206e_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	3066	: m68000_base_device(mconfig, "MCF5206E", tag, owner, clock, MCF5206E, 32,32, "mcf5206e", __FILE__)
	3067	{
2946	3068
2947		default: CPU_GET_INFO_CALL(m68k); break;
2948		}
2949	3069	}
2950	3070
2951		DEFINE_LEGACY_CPU_DEVICE(M68000, m68000);
2952		DEFINE_LEGACY_CPU_DEVICE(M68301, m68301);
2953		DEFINE_LEGACY_CPU_DEVICE(M68307, m68307);
2954		DEFINE_LEGACY_CPU_DEVICE(M68008, m68008);
2955		DEFINE_LEGACY_CPU_DEVICE(M68008PLCC, m68008plcc);
2956		DEFINE_LEGACY_CPU_DEVICE(M68010, m68010);
2957		DEFINE_LEGACY_CPU_DEVICE(M68EC020, m68ec020);
2958		DEFINE_LEGACY_CPU_DEVICE(M68020, m68020);
2959		DEFINE_LEGACY_CPU_DEVICE(M68020PMMU, m68020pmmu);
2960		DEFINE_LEGACY_CPU_DEVICE(M68020HMMU, m68020hmmu);
2961		DEFINE_LEGACY_CPU_DEVICE(M68EC030, m68ec030);
2962		DEFINE_LEGACY_CPU_DEVICE(M68030, m68030);
2963		DEFINE_LEGACY_CPU_DEVICE(M68EC040, m68ec040);
2964		DEFINE_LEGACY_CPU_DEVICE(M68LC040, m68lc040);
2965		DEFINE_LEGACY_CPU_DEVICE(M68040, m68040);
2966		DEFINE_LEGACY_CPU_DEVICE(SCC68070, scc68070);
2967		DEFINE_LEGACY_CPU_DEVICE(M68340, m68340);
2968		DEFINE_LEGACY_CPU_DEVICE(MCF5206E, mcf5206e);
	3071	void mcf5206e_device::device_start()
	3072	{
	3073	init_cpu_coldfire();
	3074	}
		No newline at end of file

trunk/src/emu/cpu/m68000/68340ser.c
r23920	r23921
4	4	#include "m68kcpu.h"
5	5
6	6
7		READ32_HANDLER( m68340_internal_serial_r )
	7	READ32_HANDLER( m68000_base_device::m68340_internal_serial_r )
8	8	{
9		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	9	m68000_base_device *m68k = this;
10	10	m68340_serial* serial = m68k->m68340SERIAL;
11	11	assert(serial != NULL);
12	12
r23920	r23921
19	19	return 0x00000000;
20	20	}
21	21
22		WRITE32_~~HANDL~~ER( m68340_internal_serial_w )
	22	WRITE32_MEMBER( m68000_base_device::m68340_internal_serial_w )
23	23	{
24		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	24	m68000_base_device *m68k = this;
25	25	m68340_serial* serial = m68k->m68340SERIAL;
26	26	assert(serial != NULL);
27	27

trunk/src/emu/cpu/m68000/m68000.h
r23920	r23921
14	14	#include "68340ser.h"
15	15	#include "68340tmu.h"
16	16
	17	#include "../../../lib/softfloat/milieu.h"
	18	#include "../../../lib/softfloat/softfloat.h"
	19	#include <setjmp.h>
	20
	21
	22	/* MMU constants */
	23	#define MMU_ATC_ENTRIES (22) // 68851 has 64, 030 has 22
	24
	25	/* instruction cache constants */
	26	#define M68K_IC_SIZE 128
	27
	28
	29
	30
	31	/* Address error */
	32	/* sigjmp() on Mac OS X and BSD in general saves signal contexts and is super-slow, use sigsetjmp() to tell it not to /
	33	#ifdef _BSD_SETJMP_H
	34	#define m68ki_set_address_error_trap(m68k) \
	35	if(sigsetjmp(m68k->aerr_trap, 0) != 0) \
	36	{ \
	37	m68ki_exception_address_error(m68k); \
	38	if(m68k->stopped) \
	39	{ \
	40	if (m68k->remaining_cycles > 0) \
	41	m68k->remaining_cycles = 0; \
	42	return; \
	43	} \
	44	}
	45
	46	#define m68ki_check_address_error(m68k, ADDR, WRITE_MODE, FC) \
	47	if((ADDR)&1) \
	48	{ \
	49	m68k->aerr_address = ADDR; \
	50	m68k->aerr_write_mode = WRITE_MODE; \
	51	m68k->aerr_fc = FC; \
	52	siglongjmp(m68k->aerr_trap, 1); \
	53	}
	54	#else
	55	#define m68ki_set_address_error_trap(m68k) \
	56	SETJMP_GNUC_PROTECT(); \
	57	if(setjmp(m68k->aerr_trap) != 0) \
	58	{ \
	59	m68ki_exception_address_error(m68k); \
	60	if(m68k->stopped) \
	61	{ \
	62	if (m68k->remaining_cycles > 0) \
	63	m68k->remaining_cycles = 0; \
	64	return; \
	65	} \
	66	}
	67
	68	#define m68ki_check_address_error(m68k, ADDR, WRITE_MODE, FC) \
	69	if((ADDR)&1) \
	70	{ \
	71	m68k->aerr_address = ADDR; \
	72	m68k->aerr_write_mode = WRITE_MODE; \
	73	m68k->aerr_fc = FC; \
	74	longjmp(m68k->aerr_trap, 1); \
	75	}
	76	#endif
	77
	78
	79
17	80	/* There are 7 levels of interrupt to the 68K.
18	81	* A transition from < 7 to 7 will cause a non-maskable interrupt (NMI).
19	82	*/
r23920	r23921
108	171
109	172
110	173
111		DECLARE_LEGACY_CPU_DEVICE(M68000, m68000);
112		DECLARE_LEGACY_CPU_DEVICE(M68301, m68301);
113		DECLARE_LEGACY_CPU_DEVICE(M68307, m68307);
114		DECLARE_LEGACY_CPU_DEVICE(M68008, m68008);
115		DECLARE_LEGACY_CPU_DEVICE(M68008PLCC, m68008plcc);
116		DECLARE_LEGACY_CPU_DEVICE(M68010, m68010);
117		DECLARE_LEGACY_CPU_DEVICE(M68EC020, m68ec020);
118		DECLARE_LEGACY_CPU_DEVICE(M68020, m68020);
119		DECLARE_LEGACY_CPU_DEVICE(M68020PMMU, m68020pmmu);
120		DECLARE_LEGACY_CPU_DEVICE(M68020HMMU, m68020hmmu);
121		DECLARE_LEGACY_CPU_DEVICE(M68EC030, m68ec030);
122		DECLARE_LEGACY_CPU_DEVICE(M68030, m68030);
123		DECLARE_LEGACY_CPU_DEVICE(M68EC040, m68ec040);
124		DECLARE_LEGACY_CPU_DEVICE(M68LC040, m68lc040);
125		DECLARE_LEGACY_CPU_DEVICE(M68040, m68040);
126		DECLARE_LEGACY_CPU_DEVICE(SCC68070, scc68070);
127		DECLARE_LEGACY_CPU_DEVICE(M68340, m68340);
128		DECLARE_LEGACY_CPU_DEVICE(MCF5206E, mcf5206e);
129	174
	175	unsigned int m68k_disassemble_raw(char* str_buff, unsigned int pc, const unsigned char* opdata, const unsigned char* argdata, unsigned int cpu_type);
130	176
131		void m68k_set_encrypted_opcode_range(device_t *device, offs_t start, offs_t end);
132	177
133		void m68k_set_hmmu_enable(device_t *device, int enable);
134	178
135		~~unsign~~ed int ~~m68k_disassemble_raw~~(~~char~~* str_bu~~ff, unsigned int p~~c~~, cons~~t ~~uns~~ign~~ed c~~har* o~~pda~~ta~~, con~~s~~t unsign~~ed char* ~~arg~~d~~ata, uns~~igned int cpu~~_ty~~pe);
	179	typedef int (instruction_hook_t)(m68000_base_device device, offs_t curpc);
136	180
137		void m68k_set_reset_callback(device_t *device, m68k_reset_func callback);
138		void m68k_set_cmpild_callback(device_t *device, m68k_cmpild_func callback);
139		void m68k_set_rte_callback(device_t *device, m68k_rte_func callback);
140		void m68k_set_tas_callback(device_t *device, m68k_tas_func callback);
141		UINT16 m68k_get_fc(device_t *device);
142	181
143		void m68307_set_port_callbacks(device_t *device, m68307_porta_read_callback porta_r, m68307_porta_write_callback m_m68307_porta_w, m68307_portb_read_callback portb_r, m68307_portb_write_callback m_m68307_portb_w);
144		UINT16 m68307_get_cs(device_t *device, offs_t address);
145		UINT16 m68340_get_cs(device_t *device, offs_t address);
146		void m68307_set_interrupt(device_t *device, int level, int vector);
147		void m68307_timer0_interrupt(legacy_cpu_device *cpudev);
148		void m68307_timer1_interrupt(legacy_cpu_device *cpudev);
149		void m68307_serial_interrupt(legacy_cpu_device *cpudev, int vector);
150		void m68307_mbus_interrupt(legacy_cpu_device *cpudev);
151		void m68307_licr2_interrupt(legacy_cpu_device *cpudev);
152	182
153		~~void m68307_s~~et~~_dua~~rt~~68681(~~device_t* cpudev, ~~device_t* duart~~68~~681)~~;
	183	extern const device_type M68K;
154	184
155		typedef int (instruction_hook_t)(device_t device, offs_t curpc);
156		void m68k_set_instruction_hook(device_t *device, instruction_hook_t ihook);
	185	class m68000_base_device : public cpu_device
	186	{
	187	public:
157	188
	189	// construction/destruction
	190	m68000_base_device(const machine_config &mconfig, const char name, const char tag, device_t *owner, UINT32 clock,
	191	const device_type type, UINT32 prg_data_width, UINT32 prg_address_bits, const char shortname, const char source);
158	192
	193	m68000_base_device(const machine_config &mconfig, const char name, const char tag, device_t *owner, UINT32 clock,
	194	const device_type type, UINT32 prg_data_width, UINT32 prg_address_bits, address_map_constructor internal_map, const char shortname, const char source);
	195
	196	m68000_base_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	197
	198	void clear_all(void);
	199
	200	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	201	virtual UINT32 disasm_max_opcode_bytes() const { return 10; };
	202	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	203
	204
	205
	206
	207	// device_execute_interface overrides
	208	virtual UINT32 execute_min_cycles() const { return 4; };
	209	virtual UINT32 execute_max_cycles() const { return 158; };
	210	virtual UINT32 execute_input_lines() const { return 8; }; // number of input lines
	211	virtual void execute_run();
	212	virtual void execute_set_input(int inputnum, int state);
	213
	214	// device-level overrides
	215	virtual void device_start();
	216	virtual void device_reset();
	217	virtual void device_stop();
	218
	219	// device_memory_interface overrides
	220	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
	221
	222	// address spaces
	223	const address_space_config m_program_config;
	224
	225	void define_state(void);
	226
	227
	228
	229
	230	public:
	231
	232
	233	UINT32 cpu_type; /* CPU Type: 68000, 68008, 68010, 68EC020, 68020, 68EC030, 68030, 68EC040, or 68040 */
	234	// UINT32 dasm_type; /* disassembly type */
	235	UINT32 dar[16]; /* Data and Address Registers */
	236	UINT32 ppc; /* Previous program counter */
	237	UINT32 pc; /* Program Counter */
	238	UINT32 sp[7]; /* User, Interrupt, and Master Stack Pointers */
	239	UINT32 vbr; /* Vector Base Register (m68010+) */
	240	UINT32 sfc; /* Source Function Code Register (m68010+) */
	241	UINT32 dfc; /* Destination Function Code Register (m68010+) */
	242	UINT32 cacr; /* Cache Control Register (m68020, unemulated) */
	243	UINT32 caar; /* Cache Address Register (m68020, unemulated) */
	244	UINT32 ir; /* Instruction Register */
	245	floatx80 fpr[8]; /* FPU Data Register (m68030/040) */
	246	UINT32 fpiar; /* FPU Instruction Address Register (m68040) */
	247	UINT32 fpsr; /* FPU Status Register (m68040) */
	248	UINT32 fpcr; /* FPU Control Register (m68040) */
	249	UINT32 t1_flag; /* Trace 1 */
	250	UINT32 t0_flag; /* Trace 0 */
	251	UINT32 s_flag; /* Supervisor */
	252	UINT32 m_flag; /* Master/Interrupt state */
	253	UINT32 x_flag; /* Extend */
	254	UINT32 n_flag; /* Negative */
	255	UINT32 not_z_flag; /* Zero, inverted for speedups */
	256	UINT32 v_flag; /* Overflow */
	257	UINT32 c_flag; /* Carry */
	258	UINT32 int_mask; /* I0-I2 */
	259	UINT32 int_level; /* State of interrupt pins IPL0-IPL2 -- ASG: changed from ints_pending */
	260	UINT32 stopped; /* Stopped state */
	261	UINT32 pref_addr; /* Last prefetch address */
	262	UINT32 pref_data; /* Data in the prefetch queue */
	263	UINT32 sr_mask; /* Implemented status register bits */
	264	UINT32 instr_mode; /* Stores whether we are in instruction mode or group 0/1 exception mode */
	265	UINT32 run_mode; /* Stores whether we are processing a reset, bus error, address error, or something else */
	266	int has_pmmu; /* Indicates if a PMMU available (yes on 030, 040, no on EC030) */
	267	int has_hmmu; /* Indicates if an Apple HMMU is available in place of the 68851 (020 only) */
	268	int pmmu_enabled; /* Indicates if the PMMU is enabled */
	269	int hmmu_enabled; /* Indicates if the HMMU is enabled */
	270	int has_fpu; /* Indicates if a FPU is available (yes on 030, 040, may be on 020) */
	271	int fpu_just_reset; /* Indicates the FPU was just reset */
	272
	273	/* Clocks required for instructions / exceptions */
	274	UINT32 cyc_bcc_notake_b;
	275	UINT32 cyc_bcc_notake_w;
	276	UINT32 cyc_dbcc_f_noexp;
	277	UINT32 cyc_dbcc_f_exp;
	278	UINT32 cyc_scc_r_true;
	279	UINT32 cyc_movem_w;
	280	UINT32 cyc_movem_l;
	281	UINT32 cyc_shift;
	282	UINT32 cyc_reset;
	283
	284	int initial_cycles;
	285	int remaining_cycles; /* Number of clocks remaining */
	286	int reset_cycles;
	287	UINT32 tracing;
	288
	289	#ifdef _BSD_SETJMP_H
	290	sigjmp_buf aerr_trap;
	291	#else
	292	jmp_buf aerr_trap;
	293	#endif
	294	UINT32 aerr_address;
	295	UINT32 aerr_write_mode;
	296	UINT32 aerr_fc;
	297
	298	/* Virtual IRQ lines state */
	299	UINT32 virq_state;
	300	UINT32 nmi_pending;
	301
	302	void (*jump_table)(m68000_base_device m68k);
	303	const UINT8* cyc_instruction;
	304	const UINT8* cyc_exception;
	305
	306	/* Callbacks to host */
	307	device_irq_acknowledge_callback int_ack_callback; /* Interrupt Acknowledge */
	308	m68k_bkpt_ack_func bkpt_ack_callback; /* Breakpoint Acknowledge */
	309	m68k_reset_func reset_instr_callback; /* Called when a RESET instruction is encountered */
	310	m68k_cmpild_func cmpild_instr_callback; /* Called when a CMPI.L #v, Dn instruction is encountered */
	311	m68k_rte_func rte_instr_callback; /* Called when a RTE instruction is encountered */
	312	m68k_tas_func tas_instr_callback; /* Called when a TAS instruction is encountered, allows / disallows writeback */
	313
	314	address_space *program;
	315
	316
	317
	318	/* Redirect memory calls */
	319
	320	typedef delegate<UINT8 (offs_t)> m68k_read8_delegate;
	321	typedef delegate<UINT16 (offs_t)> m68k_readimm16_delegate;
	322	typedef delegate<UINT16 (offs_t)> m68k_read16_delegate;
	323	typedef delegate<UINT32 (offs_t)> m68k_read32_delegate;
	324	typedef delegate<void (offs_t, UINT8)> m68k_write8_delegate;
	325	typedef delegate<void (offs_t, UINT16)> m68k_write16_delegate;
	326	typedef delegate<void (offs_t, UINT32)> m68k_write32_delegate;
	327
	328	// class m68k_memory_interface
	329	// {
	330	public:
	331	void init8(address_space &space);
	332	void init16(address_space &space);
	333	void init16_m68307(address_space &space);
	334	void init32(address_space &space);
	335	void init32mmu(address_space &space);
	336	void init32hmmu(address_space &space);
	337
	338	offs_t opcode_xor; // Address Calculation
	339	m68k_readimm16_delegate readimm16; // Immediate read 16 bit
	340	m68k_read8_delegate read8;
	341	m68k_read16_delegate read16;
	342	m68k_read32_delegate read32;
	343	m68k_write8_delegate write8;
	344	m68k_write16_delegate write16;
	345	m68k_write32_delegate write32;
	346
	347	private:
	348	UINT16 m68008_read_immediate_16(offs_t address);
	349	UINT16 read_immediate_16(offs_t address);
	350	UINT16 simple_read_immediate_16(offs_t address);
	351
	352	UINT16 simple_read_immediate_16_m68307(offs_t address);
	353	UINT8 read_byte_m68307(offs_t address);
	354	UINT16 read_word_m68307(offs_t address);
	355	UINT32 read_dword_m68307(offs_t address);
	356	void write_byte_m68307(offs_t address, UINT8 data);
	357	void write_word_m68307(offs_t address, UINT16 data);
	358	void write_dword_m68307(offs_t address, UINT32 data);
	359
	360	UINT8 read_byte_32_mmu(offs_t address);
	361	void write_byte_32_mmu(offs_t address, UINT8 data);
	362	UINT16 read_immediate_16_mmu(offs_t address);
	363	UINT16 readword_d32_mmu(offs_t address);
	364	void writeword_d32_mmu(offs_t address, UINT16 data);
	365	UINT32 readlong_d32_mmu(offs_t address);
	366	void writelong_d32_mmu(offs_t address, UINT32 data);
	367
	368	UINT8 read_byte_32_hmmu(offs_t address);
	369	void write_byte_32_hmmu(offs_t address, UINT8 data);
	370	UINT16 read_immediate_16_hmmu(offs_t address);
	371	UINT16 readword_d32_hmmu(offs_t address);
	372	void writeword_d32_hmmu(offs_t address, UINT16 data);
	373	UINT32 readlong_d32_hmmu(offs_t address);
	374	void writelong_d32_hmmu(offs_t address, UINT32 data);
	375
	376	address_space *m_space;
	377	direct_read_data *m_direct;
	378	// m68000_base_device *m_cpustate;
	379	// };
	380
	381	public:
	382	// m68k_memory_interface memory;
	383	offs_t encrypted_start;
	384	offs_t encrypted_end;
	385
	386	UINT32 iotemp;
	387
	388	/* save state data */
	389	UINT16 save_sr;
	390	UINT8 save_stopped;
	391	UINT8 save_halted;
	392
	393	/* PMMU registers */
	394	UINT32 mmu_crp_aptr, mmu_crp_limit;
	395	UINT32 mmu_srp_aptr, mmu_srp_limit;
	396	UINT32 mmu_urp_aptr; /* 040 only */
	397	UINT32 mmu_tc;
	398	UINT16 mmu_sr;
	399	UINT32 mmu_sr_040;
	400	UINT32 mmu_atc_tag[MMU_ATC_ENTRIES], mmu_atc_data[MMU_ATC_ENTRIES];
	401	UINT32 mmu_atc_rr;
	402	UINT32 mmu_tt0, mmu_tt1;
	403	UINT32 mmu_itt0, mmu_itt1, mmu_dtt0, mmu_dtt1;
	404	UINT32 mmu_acr0, mmu_acr1, mmu_acr2, mmu_acr3;
	405
	406	UINT16 mmu_tmp_sr; /* temporary hack: status code for ptest and to handle write protection */
	407	UINT16 mmu_tmp_fc; /* temporary hack: function code for the mmu (moves) */
	408	UINT16 mmu_tmp_rw; /* temporary hack: read/write (1/0) for the mmu */
	409	UINT32 mmu_tmp_buserror_address; /* temporary hack: (first) bus error address */
	410	UINT16 mmu_tmp_buserror_occurred; /* temporary hack: flag that bus error has occurred from mmu */
	411	UINT16 mmu_tmp_buserror_fc; /* temporary hack: (first) bus error fc */
	412	UINT16 mmu_tmp_buserror_rw; /* temporary hack: (first) bus error rw */
	413
	414	UINT32 ic_address[M68K_IC_SIZE]; /* instruction cache address data */
	415	UINT16 ic_data[M68K_IC_SIZE]; /* instruction cache content data */
	416
	417	/* 68307 peripheral modules */
	418	m68307_sim* m68307SIM;
	419	m68307_mbus* m68307MBUS;
	420	m68307_serial* m68307SERIAL;
	421	m68307_timer* m68307TIMER;
	422
	423	UINT16 m68307_base;
	424	UINT16 m68307_scrhigh;
	425	UINT16 m68307_scrlow;
	426
	427	int m68307_currentcs;
	428
	429	/* 68340 peripheral modules */
	430	m68340_sim* m68340SIM;
	431	m68340_dma* m68340DMA;
	432	m68340_serial* m68340SERIAL;
	433	m68340_timer* m68340TIMER;
	434
	435	UINT32 m68340_base;
	436
	437
	438	DECLARE_READ16_MEMBER( m68307_internal_base_r );
	439	DECLARE_WRITE16_MEMBER( m68307_internal_base_w );
	440	DECLARE_READ16_MEMBER( m68307_internal_timer_r );
	441	DECLARE_WRITE16_MEMBER( m68307_internal_timer_w );
	442	DECLARE_READ16_MEMBER( m68307_internal_sim_r );
	443	DECLARE_WRITE16_MEMBER( m68307_internal_sim_w );
	444	DECLARE_READ8_MEMBER( m68307_internal_serial_r );
	445	DECLARE_WRITE8_MEMBER( m68307_internal_serial_w );
	446	DECLARE_READ8_MEMBER( m68307_internal_mbus_r );
	447	DECLARE_WRITE8_MEMBER( m68307_internal_mbus_w );
	448
	449	READ32_MEMBER( m68340_internal_base_r );
	450	WRITE32_MEMBER( m68340_internal_base_w );
	451	READ32_MEMBER( m68340_internal_dma_r );
	452	WRITE32_MEMBER( m68340_internal_dma_w );
	453	READ32_HANDLER( m68340_internal_serial_r );
	454	WRITE32_MEMBER( m68340_internal_serial_w );
	455	READ16_MEMBER( m68340_internal_sim_r );
	456	READ8_MEMBER( m68340_internal_sim_ports_r );
	457	READ32_MEMBER( m68340_internal_sim_cs_r );
	458	WRITE16_MEMBER( m68340_internal_sim_w );
	459	WRITE8_MEMBER( m68340_internal_sim_ports_w );
	460	WRITE32_MEMBER( m68340_internal_sim_cs_w );
	461	READ32_MEMBER( m68340_internal_timer_r );
	462	WRITE32_MEMBER( m68340_internal_timer_w );
	463
	464
	465	/* 68308 / 68340 internal address map */
	466	address_space *internal;
	467
	468	/* callbacks for internal ports */
	469	m68307_porta_read_callback m_m68307_porta_r;
	470	m68307_porta_write_callback m_m68307_porta_w;
	471	m68307_portb_read_callback m_m68307_portb_r;
	472	m68307_portb_write_callback m_m68307_portb_w;
	473
	474
	475
	476	/* external instruction hook (does not depend on debug mode) */
	477	instruction_hook_t instruction_hook;
	478
	479
	480
	481	void init_cpu_common(void);
	482	void init_cpu_m68000(void);
	483	void init_cpu_m68307(void);
	484	void init_cpu_m68008(void);
	485	void init_cpu_m68010(void);
	486	void init_cpu_m68020(void);
	487	void init_cpu_m68020pmmu(void);
	488	void init_cpu_m68020hmmu(void);
	489	void init_cpu_m68ec020(void);
	490	void init_cpu_m68030(void);
	491	void init_cpu_m68ec030(void);
	492	void init_cpu_m68040(void);
	493	void init_cpu_m68ec040(void);
	494	void init_cpu_m68lc040(void);
	495	void init_cpu_m68340(void);
	496	void init_cpu_scc68070(void);
	497	void init_cpu_coldfire(void);
	498
	499
	500	void m68ki_exception_interrupt(m68000_base_device *m68k, UINT32 int_level);
	501
	502	void reset_cpu(void);
	503	inline void cpu_execute(void);
	504
	505	// device_state_interface overrides
	506	virtual void state_import(const device_state_entry &entry);
	507	virtual void state_export(const device_state_entry &entry);
	508	virtual void state_string_export(const device_state_entry &entry, astring &string);
	509
	510	// device_memory_interface overrides
	511	virtual bool memory_translate(address_spacenum space, int intention, offs_t &address);
	512	};
	513
	514
	515
	516	class m68000_device : public m68000_base_device
	517	{
	518	public:
	519	// construction/destruction
	520	m68000_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	521
	522	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	523	virtual UINT32 disasm_max_opcode_bytes() const { return 10; };
	524	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	525
	526	virtual UINT32 execute_min_cycles() const { return 4; };
	527	virtual UINT32 execute_max_cycles() const { return 158; };
	528
	529	virtual UINT32 execute_default_irq_vector() const { return -1; };
	530
	531	// device-level overrides
	532	virtual void device_start();
	533	protected:
	534	};
	535
	536	class m68301_device : public m68000_base_device
	537	{
	538	public:
	539	// construction/destruction
	540	m68301_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	541
	542	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	543	virtual UINT32 disasm_max_opcode_bytes() const { return 10; };
	544	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	545
	546	virtual UINT32 execute_min_cycles() const { return 4; };
	547	virtual UINT32 execute_max_cycles() const { return 158; };
	548
	549	virtual UINT32 execute_default_irq_vector() const { return -1; };
	550
	551	// device-level overrides
	552	virtual void device_start();
	553	protected:
	554	};
	555
	556
	557	class m68307_device : public m68000_base_device
	558	{
	559	public:
	560	// construction/destruction
	561	m68307_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	562
	563	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	564	virtual UINT32 disasm_max_opcode_bytes() const { return 10; };
	565	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	566
	567	virtual UINT32 execute_min_cycles() const { return 4; };
	568	virtual UINT32 execute_max_cycles() const { return 158; };
	569
	570	virtual UINT32 execute_default_irq_vector() const { return -1; };
	571
	572	// device-level overrides
	573	virtual void device_start();
	574	protected:
	575	};
	576
	577	class m68008_device : public m68000_base_device
	578	{
	579	public:
	580	// construction/destruction
	581	m68008_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	582
	583	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	584	virtual UINT32 disasm_max_opcode_bytes() const { return 10; };
	585	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	586
	587	virtual UINT32 execute_min_cycles() const { return 4; };
	588	virtual UINT32 execute_max_cycles() const { return 158; };
	589
	590	virtual UINT32 execute_default_irq_vector() const { return -1; };
	591
	592	// device-level overrides
	593	virtual void device_start();
	594	protected:
	595	};
	596
	597	class m68008plcc_device : public m68000_base_device
	598	{
	599	public:
	600	// construction/destruction
	601	m68008plcc_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	602
	603	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	604	virtual UINT32 disasm_max_opcode_bytes() const { return 10; };
	605	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	606
	607	virtual UINT32 execute_min_cycles() const { return 4; };
	608	virtual UINT32 execute_max_cycles() const { return 158; };
	609
	610	virtual UINT32 execute_default_irq_vector() const { return -1; };
	611
	612	// device-level overrides
	613	virtual void device_start();
	614	protected:
	615	};
	616
	617	class m68010_device : public m68000_base_device
	618	{
	619	public:
	620	// construction/destruction
	621	m68010_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	622
	623	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	624	virtual UINT32 disasm_max_opcode_bytes() const { return 10; };
	625	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	626
	627	virtual UINT32 execute_min_cycles() const { return 4; };
	628	virtual UINT32 execute_max_cycles() const { return 158; };
	629
	630	virtual UINT32 execute_default_irq_vector() const { return -1; };
	631
	632	// device-level overrides
	633	virtual void device_start();
	634	protected:
	635	};
	636
	637	class m68ec020_device : public m68000_base_device
	638	{
	639	public:
	640	// construction/destruction
	641	m68ec020_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	642
	643	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	644	virtual UINT32 disasm_max_opcode_bytes() const { return 20; };
	645	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	646
	647	virtual UINT32 execute_min_cycles() const { return 2; };
	648	virtual UINT32 execute_max_cycles() const { return 158; };
	649
	650	virtual UINT32 execute_default_irq_vector() const { return -1; };
	651
	652	// device-level overrides
	653	virtual void device_start();
	654	protected:
	655	};
	656
	657	class m68020_device : public m68000_base_device
	658	{
	659	public:
	660	// construction/destruction
	661	m68020_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	662
	663	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	664	virtual UINT32 disasm_max_opcode_bytes() const { return 20; };
	665	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	666
	667	virtual UINT32 execute_min_cycles() const { return 2; };
	668	virtual UINT32 execute_max_cycles() const { return 158; };
	669
	670	virtual UINT32 execute_default_irq_vector() const { return -1; };
	671
	672	// device-level overrides
	673	virtual void device_start();
	674	protected:
	675	};
	676
	677	class m68020pmmu_device : public m68000_base_device
	678	{
	679	public:
	680	// construction/destruction
	681	m68020pmmu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	682
	683	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	684	virtual UINT32 disasm_max_opcode_bytes() const { return 20; };
	685	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	686
	687	virtual UINT32 execute_min_cycles() const { return 2; };
	688	virtual UINT32 execute_max_cycles() const { return 158; };
	689
	690	virtual UINT32 execute_default_irq_vector() const { return -1; };
	691
	692	// device-level overrides
	693	virtual void device_start();
	694	protected:
	695	};
	696
	697	class m68020hmmu_device : public m68000_base_device
	698	{
	699	public:
	700	// construction/destruction
	701	m68020hmmu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	702
	703	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	704	virtual UINT32 disasm_max_opcode_bytes() const { return 20; };
	705	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	706
	707	virtual UINT32 execute_min_cycles() const { return 2; };
	708	virtual UINT32 execute_max_cycles() const { return 158; };
	709
	710	virtual UINT32 execute_default_irq_vector() const { return -1; };
	711
	712	virtual bool memory_translate(address_spacenum space, int intention, offs_t &address);
	713
	714	// device-level overrides
	715	virtual void device_start();
	716	protected:
	717	};
	718
	719	class m68ec030_device : public m68000_base_device
	720	{
	721	public:
	722	// construction/destruction
	723	m68ec030_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	724
	725	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	726	virtual UINT32 disasm_max_opcode_bytes() const { return 20; };
	727	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	728
	729	virtual UINT32 execute_min_cycles() const { return 2; };
	730	virtual UINT32 execute_max_cycles() const { return 158; };
	731
	732	virtual UINT32 execute_default_irq_vector() const { return -1; };
	733
	734	// device-level overrides
	735	virtual void device_start();
	736	protected:
	737	};
	738
	739	class m68030_device : public m68000_base_device
	740	{
	741	public:
	742	// construction/destruction
	743	m68030_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	744
	745	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	746	virtual UINT32 disasm_max_opcode_bytes() const { return 20; };
	747	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	748
	749	virtual UINT32 execute_min_cycles() const { return 2; };
	750	virtual UINT32 execute_max_cycles() const { return 158; };
	751
	752	virtual UINT32 execute_default_irq_vector() const { return -1; };
	753
	754	// device-level overrides
	755	virtual void device_start();
	756	protected:
	757	};
	758
	759	class m68ec040_device : public m68000_base_device
	760	{
	761	public:
	762	// construction/destruction
	763	m68ec040_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	764
	765	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	766	virtual UINT32 disasm_max_opcode_bytes() const { return 20; };
	767	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	768
	769	virtual UINT32 execute_min_cycles() const { return 2; };
	770	virtual UINT32 execute_max_cycles() const { return 158; };
	771
	772	virtual UINT32 execute_default_irq_vector() const { return -1; };
	773
	774	// device-level overrides
	775	virtual void device_start();
	776	protected:
	777	};
	778
	779	class m68lc040_device : public m68000_base_device
	780	{
	781	public:
	782	// construction/destruction
	783	m68lc040_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	784
	785	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	786	virtual UINT32 disasm_max_opcode_bytes() const { return 20; };
	787	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	788
	789	virtual UINT32 execute_min_cycles() const { return 2; };
	790	virtual UINT32 execute_max_cycles() const { return 158; };
	791
	792	virtual UINT32 execute_default_irq_vector() const { return -1; };
	793
	794	// device-level overrides
	795	virtual void device_start();
	796	protected:
	797	};
	798
	799	class m68040_device : public m68000_base_device
	800	{
	801	public:
	802	// construction/destruction
	803	m68040_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	804
	805	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	806	virtual UINT32 disasm_max_opcode_bytes() const { return 20; };
	807	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	808
	809	virtual UINT32 execute_min_cycles() const { return 2; };
	810	virtual UINT32 execute_max_cycles() const { return 158; };
	811
	812	virtual UINT32 execute_default_irq_vector() const { return -1; };
	813
	814	// device-level overrides
	815	virtual void device_start();
	816	protected:
	817	};
	818
	819	class scc68070_device : public m68000_base_device
	820	{
	821	public:
	822	// construction/destruction
	823	scc68070_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	824
	825	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	826	virtual UINT32 disasm_max_opcode_bytes() const { return 10; };
	827	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	828
	829	virtual UINT32 execute_min_cycles() const { return 4; };
	830	virtual UINT32 execute_max_cycles() const { return 158; };
	831
	832	virtual UINT32 execute_default_irq_vector() const { return -1; };
	833
	834	// device-level overrides
	835	virtual void device_start();
	836	protected:
	837	};
	838
	839
	840
	841
	842	class m68340_device : public m68000_base_device
	843	{
	844	public:
	845	// construction/destruction
	846	m68340_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	847
	848	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	849	virtual UINT32 disasm_max_opcode_bytes() const { return 20; };
	850	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	851
	852	virtual UINT32 execute_min_cycles() const { return 2; };
	853	virtual UINT32 execute_max_cycles() const { return 158; };
	854
	855	virtual UINT32 execute_default_irq_vector() const { return -1; };
	856
	857	// device-level overrides
	858	virtual void device_start();
	859	protected:
	860	};
	861
	862
	863
	864	class mcf5206e_device : public m68000_base_device
	865	{
	866	public:
	867	// construction/destruction
	868	mcf5206e_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	869
	870	virtual UINT32 disasm_min_opcode_bytes() const { return 2; };
	871	virtual UINT32 disasm_max_opcode_bytes() const { return 20; };
	872	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	873
	874	virtual UINT32 execute_min_cycles() const { return 2; };
	875	virtual UINT32 execute_max_cycles() const { return 158; };
	876
	877	virtual UINT32 execute_default_irq_vector() const { return -1; };
	878
	879
	880	// device-level overrides
	881	virtual void device_start();
	882	protected:
	883	};
	884
	885
	886	extern const device_type M68000;
	887	extern const device_type M68301;
	888	extern const device_type M68307;
	889	extern const device_type M68008;
	890	extern const device_type M68008PLCC;
	891	extern const device_type M68010;
	892	extern const device_type M68EC020;
	893	extern const device_type M68020;
	894	extern const device_type M68020PMMU;
	895	extern const device_type M68020HMMU;
	896	extern const device_type M68EC030;
	897	extern const device_type M68030;
	898	extern const device_type M68EC040;
	899	extern const device_type M68LC040;
	900	extern const device_type M68040;
	901	extern const device_type SCC68070;
	902	extern const device_type M68340;
	903	extern const device_type MCF5206E;
	904
	905	extern void m68k_set_reset_callback(m68000_base_device *device, m68k_reset_func callback);
	906	extern void m68k_set_cmpild_callback(m68000_base_device *device, m68k_cmpild_func callback);
	907	extern void m68k_set_rte_callback(m68000_base_device *device, m68k_rte_func callback);
	908	extern void m68k_set_tas_callback(m68000_base_device *device, m68k_tas_func callback);
	909	extern UINT16 m68k_get_fc(m68000_base_device *device);
	910	extern void m68307_set_port_callbacks(m68000_base_device *device, m68307_porta_read_callback porta_r, m68307_porta_write_callback porta_w, m68307_portb_read_callback portb_r, m68307_portb_write_callback portb_w);
	911	extern void m68307_set_duart68681(m68000_base_device* cpudev, device_t* duart68681);
	912	extern UINT16 m68307_get_cs(m68000_base_device *device, offs_t address);
	913	extern UINT16 m68340_get_cs(m68000_base_device *device, offs_t address);
	914	extern void m68307_timer0_interrupt(m68000_base_device *cpudev);
	915	extern void m68307_timer1_interrupt(m68000_base_device *cpudev);
	916	extern void m68307_serial_interrupt(m68000_base_device *cpudev, int vector);
	917	extern void m68307_mbus_interrupt(m68000_base_device *cpudev);
	918	extern void m68307_licr2_interrupt(m68000_base_device *cpudev);
	919	extern void m68k_set_encrypted_opcode_range(m68000_base_device *device, offs_t start, offs_t end);
	920	extern void m68k_set_hmmu_enable(m68000_base_device *device, int enable);
	921	extern void m68k_set_instruction_hook(m68000_base_device *device, instruction_hook_t ihook);
	922
159	923	#endif /* __M68000_H__ */

trunk/src/emu/cpu/m68000/68307sim.c
r23920	r23921
4	4	#include "m68kcpu.h"
5	5
6	6
7		READ16_~~HANDL~~ER( m68307_internal_sim_r )
	7	READ16_MEMBER( m68000_base_device::m68307_internal_sim_r )
8	8	{
9		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	9	m68000_base_device *m68k = this;
10	10	m68307_sim* sim = m68k->m68307SIM;
11	11	assert(sim != NULL);
12	12
r23920	r23921
16	16	{
17	17	switch (offset<<1)
18	18	{
19		case m68307SIM_PADAT: return sim->read_padat(space, mem_mask);
20		case m68307SIM_PBDAT: return sim->read_pbdat(space, mem_mask);
	19	case m68307SIM_PADAT: return sim->read_padat(this, space, mem_mask);
	20	case m68307SIM_PBDAT: return sim->read_pbdat(this, space, mem_mask);
21	21
22	22	case m68307SIM_LICR2: return (sim->m_licr2);
23	23
r23920	r23921
41	41	}
42	42
43	43
44		WRITE16_~~HANDL~~ER( m68307_internal_sim_w )
	44	WRITE16_MEMBER( m68000_base_device::m68307_internal_sim_w )
45	45	{
46		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	46	m68000_base_device *m68k = this;
47	47	m68307_sim* sim = m68k->m68307SIM;
48	48	assert(sim != NULL);
49	49
r23920	r23921
64	64	break;
65	65
66	66	case m68307SIM_PADAT:
67		sim->write_padat(space, data,mem_mask);
	67	sim->write_padat(this, space, data,mem_mask);
68	68	break;
69	69
70	70	case m68307SIM_PBCNT:
r23920	r23921
78	78	break;
79	79
80	80	case m68307SIM_PBDAT:
81		sim->write_pbdat(space, data, mem_mask);
	81	sim->write_pbdat(this, space, data, mem_mask);
82	82	break;
83	83
84	84
r23920	r23921
149	149	}
150	150
151	151
152		UINT16 m68307_sim::read_padat(address_space &space, UINT16 mem_mask)
	152	UINT16 m68307_sim::read_padat(m68000_base_device* m68k, address_space &space, UINT16 mem_mask)
153	153	{
154	154	int pc = space.device().safe_pc();
155		m68ki_cpu_core *m68k = m68k_get_safe_token(&space.device());
156	155
157	156	if (m68k->m_m68307_porta_r)
158	157	{
r23920	r23921
176	175	}
177	176
178	177
179		void m68307_sim::write_padat(address_space &space, UINT16 data, UINT16 mem_mask)
	178	void m68307_sim::write_padat(m68000_base_device* m68k, address_space &space, UINT16 data, UINT16 mem_mask)
180	179	{
181	180	int pc = space.device().safe_pc();
182		m68ki_cpu_core *m68k = m68k_get_safe_token(&space.device());
183	181	COMBINE_DATA(&m_padat);
184	182
185	183	if (m68k->m_m68307_porta_w)
r23920	r23921
202	200	COMBINE_DATA(&m_pbddr);
203	201	}
204	202
205		UINT16 m68307_sim::read_pbdat(address_space &space, UINT16 mem_mask)
	203	UINT16 m68307_sim::read_pbdat(m68000_base_device* m68k, address_space &space, UINT16 mem_mask)
206	204	{
207	205	int pc = space.device().safe_pc();
208		m68ki_cpu_core *m68k = m68k_get_safe_token(&space.device());
209	206
210	207	if (m68k->m_m68307_portb_r)
211	208	{
r23920	r23921
229	226	}
230	227
231	228
232		void m68307_sim::write_pbdat(address_space &space, UINT16 data, UINT16 mem_mask)
	229	void m68307_sim::write_pbdat(m68000_base_device* m68k, address_space &space, UINT16 data, UINT16 mem_mask)
233	230	{
234	231	int pc = space.device().safe_pc();
235		m68ki_cpu_core *m68k = m68k_get_safe_token(&space.device());
236	232	COMBINE_DATA(&m_pbdat);
237	233
238	234	if (m68k->m_m68307_portb_w)

trunk/src/emu/cpu/m68000/m68kfpu.c
r23920	r23921
51	51	return float64_to_floatx80(*d);
52	52	}
53	53
54		INLINE floatx80 load_extended_float80(m68ki_~~cpu~~_core *m68k, UINT32 ea)
	54	INLINE floatx80 load_extended_float80(m68000_base_device *m68k, UINT32 ea)
55	55	{
56	56	UINT32 d1,d2;
57	57	UINT16 d3;
r23920	r23921
67	67	return fp;
68	68	}
69	69
70		INLINE void store_extended_float80(m68ki_~~cpu~~_core *m68k, UINT32 ea, floatx80 fpr)
	70	INLINE void store_extended_float80(m68000_base_device *m68k, UINT32 ea, floatx80 fpr)
71	71	{
72	72	m68ki_write_16(m68k, ea+0, fpr.high);
73	73	m68ki_write_16(m68k, ea+2, 0);
r23920	r23921
75	75	m68ki_write_32(m68k, ea+8, fpr.low&0xffffffff);
76	76	}
77	77
78		INLINE floatx80 load_pack_float80(m68ki_~~cpu~~_core *m68k, UINT32 ea)
	78	INLINE floatx80 load_pack_float80(m68000_base_device *m68k, UINT32 ea)
79	79	{
80	80	UINT32 dw1, dw2, dw3;
81	81	floatx80 result;
r23920	r23921
126	126	return result;
127	127	}
128	128
129		INLINE void store_pack_float80(m68ki_~~cpu~~_core *m68k, UINT32 ea, int k, floatx80 fpr)
	129	INLINE void store_pack_float80(m68000_base_device *m68k, UINT32 ea, int k, floatx80 fpr)
130	130	{
131	131	UINT32 dw1, dw2, dw3;
132	132	char str[128], *ch;
r23920	r23921
258	258	m68ki_write_32(m68k, ea+8, dw3);
259	259	}
260	260
261		INLINE void SET_CONDITION_CODES(m68ki_~~cpu~~_core *m68k, floatx80 reg)
	261	INLINE void SET_CONDITION_CODES(m68000_base_device *m68k, floatx80 reg)
262	262	{
263	263	// UINT64 *regi;
264	264
r23920	r23921
291	291	}
292	292	}
293	293
294		INLINE int TEST_CONDITION(m68ki_~~cpu~~_core *m68k, int condition)
	294	INLINE int TEST_CONDITION(m68000_base_device *m68k, int condition)
295	295	{
296	296	int n = (REG_FPSR(m68k) & FPCC_N) != 0;
297	297	int z = (REG_FPSR(m68k) & FPCC_Z) != 0;
r23920	r23921
353	353	return r;
354	354	}
355	355
356		static UINT8 READ_EA_8(m68ki_~~cpu~~_core *m68k, int ea)
	356	static UINT8 READ_EA_8(m68000_base_device *m68k, int ea)
357	357	{
358	358	int mode = (ea >> 3) & 0x7;
359	359	int reg = (ea & 0x7);
r23920	r23921
429	429	return 0;
430	430	}
431	431
432		static UINT16 READ_EA_16(m68ki_~~cpu~~_core *m68k, int ea)
	432	static UINT16 READ_EA_16(m68000_base_device *m68k, int ea)
433	433	{
434	434	int mode = (ea >> 3) & 0x7;
435	435	int reg = (ea & 0x7);
r23920	r23921
506	506	return 0;
507	507	}
508	508
509		static UINT32 READ_EA_32(m68ki_~~cpu~~_core *m68k, int ea)
	509	static UINT32 READ_EA_32(m68000_base_device *m68k, int ea)
510	510	{
511	511	int mode = (ea >> 3) & 0x7;
512	512	int reg = (ea & 0x7);
r23920	r23921
581	581	return 0;
582	582	}
583	583
584		static UINT64 READ_EA_64(m68ki_~~cpu~~_core *m68k, int ea)
	584	static UINT64 READ_EA_64(m68000_base_device *m68k, int ea)
585	585	{
586	586	int mode = (ea >> 3) & 0x7;
587	587	int reg = (ea & 0x7);
r23920	r23921
668	668	}
669	669
670	670
671		static floatx80 READ_EA_FPE(m68ki_~~cpu~~_core *m68k, int ea)
	671	static floatx80 READ_EA_FPE(m68000_base_device *m68k, int ea)
672	672	{
673	673	floatx80 fpr;
674	674	int mode = (ea >> 3) & 0x7;
r23920	r23921
743	743	return fpr;
744	744	}
745	745
746		static floatx80 READ_EA_PACK(m68ki_~~cpu~~_core *m68k, int ea)
	746	static floatx80 READ_EA_PACK(m68000_base_device *m68k, int ea)
747	747	{
748	748	floatx80 fpr;
749	749	int mode = (ea >> 3) & 0x7;
r23920	r23921
790	790	return fpr;
791	791	}
792	792
793		static void WRITE_EA_8(m68ki_~~cpu~~_core *m68k, int ea, UINT8 data)
	793	static void WRITE_EA_8(m68000_base_device *m68k, int ea, UINT8 data)
794	794	{
795	795	int mode = (ea >> 3) & 0x7;
796	796	int reg = (ea & 0x7);
r23920	r23921
858	858	}
859	859	}
860	860
861		static void WRITE_EA_16(m68ki_~~cpu~~_core *m68k, int ea, UINT16 data)
	861	static void WRITE_EA_16(m68000_base_device *m68k, int ea, UINT16 data)
862	862	{
863	863	int mode = (ea >> 3) & 0x7;
864	864	int reg = (ea & 0x7);
r23920	r23921
926	926	}
927	927	}
928	928
929		static void WRITE_EA_32(m68ki_~~cpu~~_core *m68k, int ea, UINT32 data)
	929	static void WRITE_EA_32(m68000_base_device *m68k, int ea, UINT32 data)
930	930	{
931	931	int mode = (ea >> 3) & 0x7;
932	932	int reg = (ea & 0x7);
r23920	r23921
999	999	}
1000	1000	}
1001	1001
1002		static void WRITE_EA_64(m68ki_~~cpu~~_core *m68k, int ea, UINT64 data)
	1002	static void WRITE_EA_64(m68000_base_device *m68k, int ea, UINT64 data)
1003	1003	{
1004	1004	int mode = (ea >> 3) & 0x7;
1005	1005	int reg = (ea & 0x7);
r23920	r23921
1072	1072	}
1073	1073	}
1074	1074
1075		static void WRITE_EA_FPE(m68ki_~~cpu~~_core *m68k, int ea, floatx80 fpr)
	1075	static void WRITE_EA_FPE(m68000_base_device *m68k, int ea, floatx80 fpr)
1076	1076	{
1077	1077	int mode = (ea >> 3) & 0x7;
1078	1078	int reg = (ea & 0x7);
r23920	r23921
1116	1116	}
1117	1117	}
1118	1118
1119		static void WRITE_EA_PACK(m68ki_~~cpu~~_core *m68k, int ea, int k, floatx80 fpr)
	1119	static void WRITE_EA_PACK(m68000_base_device *m68k, int ea, int k, floatx80 fpr)
1120	1120	{
1121	1121	int mode = (ea >> 3) & 0x7;
1122	1122	int reg = (ea & 0x7);
r23920	r23921
1160	1160	}
1161	1161	}
1162	1162
1163		static void fpgen_rm_reg(m68ki_~~cpu~~_core *m68k, UINT16 w2)
	1163	static void fpgen_rm_reg(m68000_base_device *m68k, UINT16 w2)
1164	1164	{
1165	1165	int ea = m68k->ir & 0x3f;
1166	1166	int rm = (w2 >> 14) & 0x1;
r23920	r23921
1525	1525	}
1526	1526	}
1527	1527
1528		static void fmove_reg_mem(m68ki_~~cpu~~_core *m68k, UINT16 w2)
	1528	static void fmove_reg_mem(m68000_base_device *m68k, UINT16 w2)
1529	1529	{
1530	1530	int ea = m68k->ir & 0x3f;
1531	1531	int src = (w2 >> 7) & 0x7;
r23920	r23921
1597	1597	m68k->remaining_cycles -= 12;
1598	1598	}
1599	1599
1600		static void fmove_fpcr(m68ki_~~cpu~~_core *m68k, UINT16 w2)
	1600	static void fmove_fpcr(m68000_base_device *m68k, UINT16 w2)
1601	1601	{
1602	1602	int ea = m68k->ir & 0x3f;
1603	1603	int dir = (w2 >> 13) & 0x1;
r23920	r23921
1699	1699	m68k->remaining_cycles -= 10;
1700	1700	}
1701	1701
1702		static void fmovem(m68ki_~~cpu~~_core *m68k, UINT16 w2)
	1702	static void fmovem(m68000_base_device *m68k, UINT16 w2)
1703	1703	{
1704	1704	int i;
1705	1705	int ea = m68k->ir & 0x3f;
r23920	r23921
1813	1813	}
1814	1814	}
1815	1815
1816		static void fscc(m68ki_~~cpu~~_core *m68k)
	1816	static void fscc(m68000_base_device *m68k)
1817	1817	{
1818	1818	int ea = m68k->ir & 0x3f;
1819	1819	int condition = (INT16)(OPER_I_16(m68k));
r23920	r23921
1822	1822	m68k->remaining_cycles -= 7; // ???
1823	1823	}
1824	1824
1825		static void fbcc16(m68ki_~~cpu~~_core *m68k)
	1825	static void fbcc16(m68000_base_device *m68k)
1826	1826	{
1827	1827	INT32 offset;
1828	1828	int condition = m68k->ir & 0x3f;
r23920	r23921
1839	1839	m68k->remaining_cycles -= 7;
1840	1840	}
1841	1841
1842		static void fbcc32(m68ki_~~cpu~~_core *m68k)
	1842	static void fbcc32(m68000_base_device *m68k)
1843	1843	{
1844	1844	INT32 offset;
1845	1845	int condition = m68k->ir & 0x3f;
r23920	r23921
1857	1857	}
1858	1858
1859	1859
1860		void m68040_fpu_op0(m68ki_~~cpu~~_core *m68k)
	1860	void m68040_fpu_op0(m68000_base_device *m68k)
1861	1861	{
1862	1862	m68k->fpu_just_reset = 0;
1863	1863
r23920	r23921
1928	1928	}
1929	1929	}
1930	1930
1931		static int perform_fsave(m68ki_~~cpu~~_core *m68k, UINT32 addr, int inc)
	1931	static int perform_fsave(m68000_base_device *m68k, UINT32 addr, int inc)
1932	1932	{
1933	1933	if(m68k->cpu_type & CPU_TYPE_040)
1934	1934	{
r23920	r23921
1970	1970	}
1971	1971
1972	1972	// FRESTORE on a NULL frame reboots the FPU - all registers to NaN, the 3 status regs to 0
1973		static void do_frestore_null(m68ki_~~cpu~~_core *m68k)
	1973	static void do_frestore_null(m68000_base_device *m68k)
1974	1974	{
1975	1975	int i;
1976	1976
r23920	r23921
1988	1988	m68k->fpu_just_reset = 1;
1989	1989	}
1990	1990
1991		static void m68040_do_fsave(m68ki_~~cpu~~_core *m68k, UINT32 addr, int reg, int inc)
	1991	static void m68040_do_fsave(m68000_base_device *m68k, UINT32 addr, int reg, int inc)
1992	1992	{
1993	1993	if (m68k->fpu_just_reset)
1994	1994	{
r23920	r23921
2003	2003	}
2004	2004	}
2005	2005
2006		static void m68040_do_frestore(m68ki_~~cpu~~_core *m68k, UINT32 addr, int reg)
	2006	static void m68040_do_frestore(m68000_base_device *m68k, UINT32 addr, int reg)
2007	2007	{
2008	2008	bool m40 = m68k->cpu_type & CPU_TYPE_040;
2009	2009	UINT32 temp = m68ki_read_32(m68k, addr);
r23920	r23921
2041	2041	}
2042	2042	}
2043	2043
2044		void m68040_fpu_op1(m68ki_~~cpu~~_core *m68k)
	2044	void m68040_fpu_op1(m68000_base_device *m68k)
2045	2045	{
2046	2046	int ea = m68k->ir & 0x3f;
2047	2047	int mode = (ea >> 3) & 0x7;

trunk/src/emu/cpu/m68000/68307bus.c
r23920	r23921
5	5	#include "m68kcpu.h"
6	6
7	7
8		READ8_~~HANDL~~ER( m68307_internal_mbus_r )
	8	READ8_MEMBER( m68000_base_device::m68307_internal_mbus_r )
9	9	{
10		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	10	m68000_base_device *m68k = this;
11	11	m68307_mbus* mbus = m68k->m68307MBUS;
12	12	assert(mbus != NULL);
13	13	UINT8 retval;
r23920	r23921
53	53	return 0xff;
54	54	}
55	55
56		WRITE8_~~HANDL~~ER( m68307_internal_mbus_w )
	56	WRITE8_MEMBER( m68000_base_device::m68307_internal_mbus_w )
57	57	{
58		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	58	m68000_base_device *m68k = this;
59	59	m68307_mbus* mbus = m68k->m68307MBUS;
60	60	assert(mbus != NULL);
61	61

trunk/src/emu/cpu/m68000/68307ser.c
r23920	r23921
13	13	#include "m68kcpu.h"
14	14
15	15
16		READ8_~~HANDL~~ER( m68307_internal_serial_r )
	16	READ8_MEMBER( m68000_base_device::m68307_internal_serial_r )
17	17	{
18		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	18	m68000_base_device *m68k = this;
19	19	m68307_serial* serial = m68k->m68307SERIAL;
20	20	assert(serial != NULL);
21	21
r23920	r23921
90	90	return 0x0000;
91	91	}
92	92
93		WRITE8_~~HANDL~~ER( m68307_internal_serial_w )
	93	WRITE8_MEMBER( m68000_base_device::m68307_internal_serial_w )
94	94	{
95		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	95	m68000_base_device *m68k = this;
96	96	m68307_serial* serial = m68k->m68307SERIAL;
97	97	assert(serial != NULL);
98	98

trunk/src/emu/cpu/m68000/m68kcpu.h
r23920	r23921
25	25	#ifndef __M68KCPU_H__
26	26	#define __M68KCPU_H__
27	27
28		~~typedef~~ class _m68ki_~~cpu~~_~~cor~~e ~~m68k~~i_c~~pu_cor~~e;
	28	class m68000_base_device;
29	29
30	30	#include "m68000.h"
31		#include "../../../lib/softfloat/milieu.h"
32		#include "../../../lib/softfloat/softfloat.h"
33	31
	32
34	33	#include <limits.h>
35	34	#include <setjmp.h>
36	35
r23920	r23921
101	100	#define RUN_MODE_NORMAL 0
102	101	#define RUN_MODE_BERR_AERR_RESET 1
103	102
104		/* MMU constants */
105		#define MMU_ATC_ENTRIES (22) // 68851 has 64, 030 has 22
106	103
107		/* instruction cache constants */
108		#define M68K_IC_SIZE 128
109	104
110	105	#define M68K_CACR_IBE 0x10 // Instruction Burst Enable
111	106	#define M68K_CACR_CI 0x08 // Clear Instruction Cache
r23920	r23921
266	261	/* Cause a trace exception if we are tracing */
267	262	#define m68ki_exception_if_trace(m68k) if(m68k->tracing) m68ki_exception_trace(m68k)
268	263
269
270		/* Address error */
271		/* sigjmp() on Mac OS X and BSD in general saves signal contexts and is super-slow, use sigsetjmp() to tell it not to /
272		#ifdef _BSD_SETJMP_H
273		#define m68ki_set_address_error_trap(m68k) \
274		if(sigsetjmp(m68k->aerr_trap, 0) != 0) \
275		{ \
276		m68ki_exception_address_error(m68k); \
277		if(m68k->stopped) \
278		{ \
279		if (m68k->remaining_cycles > 0) \
280		m68k->remaining_cycles = 0; \
281		return; \
282		} \
283		}
284
285		#define m68ki_check_address_error(m68k, ADDR, WRITE_MODE, FC) \
286		if((ADDR)&1) \
287		{ \
288		m68k->aerr_address = ADDR; \
289		m68k->aerr_write_mode = WRITE_MODE; \
290		m68k->aerr_fc = FC; \
291		siglongjmp(m68k->aerr_trap, 1); \
292		}
293		#else
294		#define m68ki_set_address_error_trap(m68k) \
295		SETJMP_GNUC_PROTECT(); \
296		if(setjmp(m68k->aerr_trap) != 0) \
297		{ \
298		m68ki_exception_address_error(m68k); \
299		if(m68k->stopped) \
300		{ \
301		if (m68k->remaining_cycles > 0) \
302		m68k->remaining_cycles = 0; \
303		return; \
304		} \
305		}
306
307		#define m68ki_check_address_error(m68k, ADDR, WRITE_MODE, FC) \
308		if((ADDR)&1) \
309		{ \
310		m68k->aerr_address = ADDR; \
311		m68k->aerr_write_mode = WRITE_MODE; \
312		m68k->aerr_fc = FC; \
313		longjmp(m68k->aerr_trap, 1); \
314		}
315		#endif
316
317
318	264	/* -------------------------- EA / Operand Access ------------------------- */
319	265
320	266	/*
r23920	r23921
535	481	double f;
536	482	};
537	483
538		/* Redirect memory calls */
539
540		typedef delegate<UINT8 (offs_t)> m68k_read8_delegate;
541		typedef delegate<UINT16 (offs_t)> m68k_readimm16_delegate;
542		typedef delegate<UINT16 (offs_t)> m68k_read16_delegate;
543		typedef delegate<UINT32 (offs_t)> m68k_read32_delegate;
544		typedef delegate<void (offs_t, UINT8)> m68k_write8_delegate;
545		typedef delegate<void (offs_t, UINT16)> m68k_write16_delegate;
546		typedef delegate<void (offs_t, UINT32)> m68k_write32_delegate;
547
548		class m68k_memory_interface
	484	class m68000_base_device_ops
549	485	{
550	486	public:
551		void init8(address_space &space);
552		void init16(address_space &space);
553		void init16_m68307(address_space &space);
554		void init32(address_space &space);
555		void init32mmu(address_space &space);
556		void init32hmmu(address_space &space);
557
558		offs_t opcode_xor; // Address Calculation
559		m68k_readimm16_delegate readimm16; // Immediate read 16 bit
560		m68k_read8_delegate read8;
561		m68k_read16_delegate read16;
562		m68k_read32_delegate read32;
563		m68k_write8_delegate write8;
564		m68k_write16_delegate write16;
565		m68k_write32_delegate write32;
566
567		private:
568		UINT16 m68008_read_immediate_16(offs_t address);
569		UINT16 read_immediate_16(offs_t address);
570		UINT16 simple_read_immediate_16(offs_t address);
571
572		UINT16 simple_read_immediate_16_m68307(offs_t address);
573		UINT8 read_byte_m68307(offs_t address);
574		UINT16 read_word_m68307(offs_t address);
575		UINT32 read_dword_m68307(offs_t address);
576		void write_byte_m68307(offs_t address, UINT8 data);
577		void write_word_m68307(offs_t address, UINT16 data);
578		void write_dword_m68307(offs_t address, UINT32 data);
579
580		UINT8 read_byte_32_mmu(offs_t address);
581		void write_byte_32_mmu(offs_t address, UINT8 data);
582		UINT16 read_immediate_16_mmu(offs_t address);
583		UINT16 readword_d32_mmu(offs_t address);
584		void writeword_d32_mmu(offs_t address, UINT16 data);
585		UINT32 readlong_d32_mmu(offs_t address);
586		void writelong_d32_mmu(offs_t address, UINT32 data);
587
588		UINT8 read_byte_32_hmmu(offs_t address);
589		void write_byte_32_hmmu(offs_t address, UINT8 data);
590		UINT16 read_immediate_16_hmmu(offs_t address);
591		UINT16 readword_d32_hmmu(offs_t address);
592		void writeword_d32_hmmu(offs_t address, UINT16 data);
593		UINT32 readlong_d32_hmmu(offs_t address);
594		void writelong_d32_hmmu(offs_t address, UINT32 data);
595
596		address_space *m_space;
597		direct_read_data *m_direct;
598		m68ki_cpu_core *m_cpustate;
599		};
600
601		class _m68ki_cpu_core
602		{
603		public:
604
605		UINT32 cpu_type; /* CPU Type: 68000, 68008, 68010, 68EC020, 68020, 68EC030, 68030, 68EC040, or 68040 */
606		UINT32 dasm_type; /* disassembly type */
607		UINT32 dar[16]; /* Data and Address Registers */
608		UINT32 ppc; /* Previous program counter */
609		UINT32 pc; /* Program Counter */
610		UINT32 sp[7]; /* User, Interrupt, and Master Stack Pointers */
611		UINT32 vbr; /* Vector Base Register (m68010+) */
612		UINT32 sfc; /* Source Function Code Register (m68010+) */
613		UINT32 dfc; /* Destination Function Code Register (m68010+) */
614		UINT32 cacr; /* Cache Control Register (m68020, unemulated) */
615		UINT32 caar; /* Cache Address Register (m68020, unemulated) */
616		UINT32 ir; /* Instruction Register */
617		floatx80 fpr[8]; /* FPU Data Register (m68030/040) */
618		UINT32 fpiar; /* FPU Instruction Address Register (m68040) */
619		UINT32 fpsr; /* FPU Status Register (m68040) */
620		UINT32 fpcr; /* FPU Control Register (m68040) */
621		UINT32 t1_flag; /* Trace 1 */
622		UINT32 t0_flag; /* Trace 0 */
623		UINT32 s_flag; /* Supervisor */
624		UINT32 m_flag; /* Master/Interrupt state */
625		UINT32 x_flag; /* Extend */
626		UINT32 n_flag; /* Negative */
627		UINT32 not_z_flag; /* Zero, inverted for speedups */
628		UINT32 v_flag; /* Overflow */
629		UINT32 c_flag; /* Carry */
630		UINT32 int_mask; /* I0-I2 */
631		UINT32 int_level; /* State of interrupt pins IPL0-IPL2 -- ASG: changed from ints_pending */
632		UINT32 stopped; /* Stopped state */
633		UINT32 pref_addr; /* Last prefetch address */
634		UINT32 pref_data; /* Data in the prefetch queue */
635		UINT32 sr_mask; /* Implemented status register bits */
636		UINT32 instr_mode; /* Stores whether we are in instruction mode or group 0/1 exception mode */
637		UINT32 run_mode; /* Stores whether we are processing a reset, bus error, address error, or something else */
638		int has_pmmu; /* Indicates if a PMMU available (yes on 030, 040, no on EC030) */
639		int has_hmmu; /* Indicates if an Apple HMMU is available in place of the 68851 (020 only) */
640		int pmmu_enabled; /* Indicates if the PMMU is enabled */
641		int hmmu_enabled; /* Indicates if the HMMU is enabled */
642		int has_fpu; /* Indicates if a FPU is available (yes on 030, 040, may be on 020) */
643		int fpu_just_reset; /* Indicates the FPU was just reset */
644
645		/* Clocks required for instructions / exceptions */
646		UINT32 cyc_bcc_notake_b;
647		UINT32 cyc_bcc_notake_w;
648		UINT32 cyc_dbcc_f_noexp;
649		UINT32 cyc_dbcc_f_exp;
650		UINT32 cyc_scc_r_true;
651		UINT32 cyc_movem_w;
652		UINT32 cyc_movem_l;
653		UINT32 cyc_shift;
654		UINT32 cyc_reset;
655
656		int initial_cycles;
657		int remaining_cycles; /* Number of clocks remaining */
658		int reset_cycles;
659		UINT32 tracing;
660
661		#ifdef _BSD_SETJMP_H
662		sigjmp_buf aerr_trap;
663		#else
664		jmp_buf aerr_trap;
665		#endif
666		UINT32 aerr_address;
667		UINT32 aerr_write_mode;
668		UINT32 aerr_fc;
669
670		/* Virtual IRQ lines state */
671		UINT32 virq_state;
672		UINT32 nmi_pending;
673
674		void (*jump_table)(m68ki_cpu_core m68k);
675		const UINT8* cyc_instruction;
676		const UINT8* cyc_exception;
677
678		/* Callbacks to host */
679		device_irq_acknowledge_callback int_ack_callback; /* Interrupt Acknowledge */
680		m68k_bkpt_ack_func bkpt_ack_callback; /* Breakpoint Acknowledge */
681		m68k_reset_func reset_instr_callback; /* Called when a RESET instruction is encountered */
682		m68k_cmpild_func cmpild_instr_callback; /* Called when a CMPI.L #v, Dn instruction is encountered */
683		m68k_rte_func rte_instr_callback; /* Called when a RTE instruction is encountered */
684		m68k_tas_func tas_instr_callback; /* Called when a TAS instruction is encountered, allows / disallows writeback */
685
686		legacy_cpu_device *device;
687		address_space *program;
688		m68k_memory_interface memory;
689		offs_t encrypted_start;
690		offs_t encrypted_end;
691
692		UINT32 iotemp;
693
694		/* save state data */
695		UINT16 save_sr;
696		UINT8 save_stopped;
697		UINT8 save_halted;
698
699		/* PMMU registers */
700		UINT32 mmu_crp_aptr, mmu_crp_limit;
701		UINT32 mmu_srp_aptr, mmu_srp_limit;
702		UINT32 mmu_urp_aptr; /* 040 only */
703		UINT32 mmu_tc;
704		UINT16 mmu_sr;
705		UINT32 mmu_sr_040;
706		UINT32 mmu_atc_tag[MMU_ATC_ENTRIES], mmu_atc_data[MMU_ATC_ENTRIES];
707		UINT32 mmu_atc_rr;
708		UINT32 mmu_tt0, mmu_tt1;
709		UINT32 mmu_itt0, mmu_itt1, mmu_dtt0, mmu_dtt1;
710		UINT32 mmu_acr0, mmu_acr1, mmu_acr2, mmu_acr3;
711
712		UINT16 mmu_tmp_sr; /* temporary hack: status code for ptest and to handle write protection */
713		UINT16 mmu_tmp_fc; /* temporary hack: function code for the mmu (moves) */
714		UINT16 mmu_tmp_rw; /* temporary hack: read/write (1/0) for the mmu */
715		UINT32 mmu_tmp_buserror_address; /* temporary hack: (first) bus error address */
716		UINT16 mmu_tmp_buserror_occurred; /* temporary hack: flag that bus error has occurred from mmu */
717		UINT16 mmu_tmp_buserror_fc; /* temporary hack: (first) bus error fc */
718		UINT16 mmu_tmp_buserror_rw; /* temporary hack: (first) bus error rw */
719
720		UINT32 ic_address[M68K_IC_SIZE]; /* instruction cache address data */
721		UINT16 ic_data[M68K_IC_SIZE]; /* instruction cache content data */
722
723		/* 68307 peripheral modules */
724		m68307_sim* m68307SIM;
725		m68307_mbus* m68307MBUS;
726		m68307_serial* m68307SERIAL;
727		m68307_timer* m68307TIMER;
728
729		UINT16 m68307_base;
730		UINT16 m68307_scrhigh;
731		UINT16 m68307_scrlow;
732
733		int m68307_currentcs;
734
735		/* 68340 peripheral modules */
736		m68340_sim* m68340SIM;
737		m68340_dma* m68340DMA;
738		m68340_serial* m68340SERIAL;
739		m68340_timer* m68340TIMER;
740
741		UINT32 m68340_base;
742
743
744		/* 68308 / 68340 internal address map */
745		address_space *internal;
746
747		/* callbacks for internal ports */
748		m68307_porta_read_callback m_m68307_porta_r;
749		m68307_porta_write_callback m_m68307_porta_w;
750		m68307_portb_read_callback m_m68307_portb_r;
751		m68307_portb_write_callback m_m68307_portb_w;
752
753
754
755		/* external instruction hook (does not depend on debug mode) */
756		typedef int (instruction_hook_t)(device_t device, offs_t curpc);
757		instruction_hook_t instruction_hook;
758
759	487	#define OPCODE_PROTOTYPES
760	488	#include "m68kops.h"
761	489	#undef OPCODE_PROTOTYPES
762	490	};
763	491
764	492
765		INLINE m68ki_cpu_core m68k_get_safe_token(device_t device)
766		{
767		assert(device != NULL);
768		assert(device->type() == M68000 \|\|
769		device->type() == M68301 \|\|
770		device->type() == M68307 \|\|
771		device->type() == M68008 \|\|
772		device->type() == M68008PLCC \|\|
773		device->type() == M68010 \|\|
774		device->type() == M68EC020 \|\|
775		device->type() == M68020 \|\|
776		device->type() == M68020HMMU \|\|
777		device->type() == M68020PMMU \|\|
778		device->type() == M68EC030 \|\|
779		device->type() == M68030 \|\|
780		device->type() == M68EC040 \|\|
781		device->type() == M68040 \|\|
782		device->type() == SCC68070 \|\|
783		device->type() == MCF5206E \|\|
784		device->type() == M68340);
785		return (m68ki_cpu_core )downcast<legacy_cpu_device >(device)->token();
786		}
787	493
788	494	extern const UINT8 m68ki_shift_8_table[];
789	495	extern const UINT16 m68ki_shift_16_table[];
r23920	r23921
792	498	extern const UINT8 m68ki_ea_idx_cycle_table[];
793	499
794	500	/* Read data immediately after the program counter */
795		INLINE UINT32 m68ki_read_imm_16(m68ki_cpu_core *m68k);
796		INLINE UINT32 m68ki_read_imm_32(m68ki_cpu_core *m68k);
	501	INLINE UINT32 m68ki_read_imm_16(m68000_base_device *m68k);
	502	INLINE UINT32 m68ki_read_imm_32(m68000_base_device *m68k);
797	503
798	504	/* Read data with specific function code */
799		INLINE UINT32 m68ki_read_8_fc (m68ki_cpu_core *m68k, UINT32 address, UINT32 fc);
800		INLINE UINT32 m68ki_read_16_fc (m68ki_cpu_core *m68k, UINT32 address, UINT32 fc);
801		INLINE UINT32 m68ki_read_32_fc (m68ki_cpu_core *m68k, UINT32 address, UINT32 fc);
	505	INLINE UINT32 m68ki_read_8_fc (m68000_base_device *m68k, UINT32 address, UINT32 fc);
	506	INLINE UINT32 m68ki_read_16_fc (m68000_base_device *m68k, UINT32 address, UINT32 fc);
	507	INLINE UINT32 m68ki_read_32_fc (m68000_base_device *m68k, UINT32 address, UINT32 fc);
802	508
803	509	/* Write data with specific function code */
804		INLINE void m68ki_write_8_fc (m68ki_cpu_core *m68k, UINT32 address, UINT32 fc, UINT32 value);
805		INLINE void m68ki_write_16_fc(m68ki_cpu_core *m68k, UINT32 address, UINT32 fc, UINT32 value);
806		INLINE void m68ki_write_32_fc(m68ki_cpu_core *m68k, UINT32 address, UINT32 fc, UINT32 value);
807		INLINE void m68ki_write_32_pd_fc(m68ki_cpu_core *m68k, UINT32 address, UINT32 fc, UINT32 value);
	510	INLINE void m68ki_write_8_fc (m68000_base_device *m68k, UINT32 address, UINT32 fc, UINT32 value);
	511	INLINE void m68ki_write_16_fc(m68000_base_device *m68k, UINT32 address, UINT32 fc, UINT32 value);
	512	INLINE void m68ki_write_32_fc(m68000_base_device *m68k, UINT32 address, UINT32 fc, UINT32 value);
	513	INLINE void m68ki_write_32_pd_fc(m68000_base_device *m68k, UINT32 address, UINT32 fc, UINT32 value);
808	514
809	515	/* Indexed and PC-relative ea fetching */
810		INLINE UINT32 m68ki_get_ea_pcdi(m68ki_cpu_core *m68k);
811		INLINE UINT32 m68ki_get_ea_pcix(m68ki_cpu_core *m68k);
812		INLINE UINT32 m68ki_get_ea_ix(m68ki_cpu_core *m68k, UINT32 An);
	516	INLINE UINT32 m68ki_get_ea_pcdi(m68000_base_device *m68k);
	517	INLINE UINT32 m68ki_get_ea_pcix(m68000_base_device *m68k);
	518	INLINE UINT32 m68ki_get_ea_ix(m68000_base_device *m68k, UINT32 An);
813	519
814	520	/* Operand fetching */
815		INLINE UINT32 OPER_AY_AI_8(m68ki_cpu_core *m68k);
816		INLINE UINT32 OPER_AY_AI_16(m68ki_cpu_core *m68k);
817		INLINE UINT32 OPER_AY_AI_32(m68ki_cpu_core *m68k);
818		INLINE UINT32 OPER_AY_PI_8(m68ki_cpu_core *m68k);
819		INLINE UINT32 OPER_AY_PI_16(m68ki_cpu_core *m68k);
820		INLINE UINT32 OPER_AY_PI_32(m68ki_cpu_core *m68k);
821		INLINE UINT32 OPER_AY_PD_8(m68ki_cpu_core *m68k);
822		INLINE UINT32 OPER_AY_PD_16(m68ki_cpu_core *m68k);
823		INLINE UINT32 OPER_AY_PD_32(m68ki_cpu_core *m68k);
824		INLINE UINT32 OPER_AY_DI_8(m68ki_cpu_core *m68k);
825		INLINE UINT32 OPER_AY_DI_16(m68ki_cpu_core *m68k);
826		INLINE UINT32 OPER_AY_DI_32(m68ki_cpu_core *m68k);
827		INLINE UINT32 OPER_AY_IX_8(m68ki_cpu_core *m68k);
828		INLINE UINT32 OPER_AY_IX_16(m68ki_cpu_core *m68k);
829		INLINE UINT32 OPER_AY_IX_32(m68ki_cpu_core *m68k);
	521	INLINE UINT32 OPER_AY_AI_8(m68000_base_device *m68k);
	522	INLINE UINT32 OPER_AY_AI_16(m68000_base_device *m68k);
	523	INLINE UINT32 OPER_AY_AI_32(m68000_base_device *m68k);
	524	INLINE UINT32 OPER_AY_PI_8(m68000_base_device *m68k);
	525	INLINE UINT32 OPER_AY_PI_16(m68000_base_device *m68k);
	526	INLINE UINT32 OPER_AY_PI_32(m68000_base_device *m68k);
	527	INLINE UINT32 OPER_AY_PD_8(m68000_base_device *m68k);
	528	INLINE UINT32 OPER_AY_PD_16(m68000_base_device *m68k);
	529	INLINE UINT32 OPER_AY_PD_32(m68000_base_device *m68k);
	530	INLINE UINT32 OPER_AY_DI_8(m68000_base_device *m68k);
	531	INLINE UINT32 OPER_AY_DI_16(m68000_base_device *m68k);
	532	INLINE UINT32 OPER_AY_DI_32(m68000_base_device *m68k);
	533	INLINE UINT32 OPER_AY_IX_8(m68000_base_device *m68k);
	534	INLINE UINT32 OPER_AY_IX_16(m68000_base_device *m68k);
	535	INLINE UINT32 OPER_AY_IX_32(m68000_base_device *m68k);
830	536
831		INLINE UINT32 OPER_AX_AI_8(m68ki_cpu_core *m68k);
832		INLINE UINT32 OPER_AX_AI_16(m68ki_cpu_core *m68k);
833		INLINE UINT32 OPER_AX_AI_32(m68ki_cpu_core *m68k);
834		INLINE UINT32 OPER_AX_PI_8(m68ki_cpu_core *m68k);
835		INLINE UINT32 OPER_AX_PI_16(m68ki_cpu_core *m68k);
836		INLINE UINT32 OPER_AX_PI_32(m68ki_cpu_core *m68k);
837		INLINE UINT32 OPER_AX_PD_8(m68ki_cpu_core *m68k);
838		INLINE UINT32 OPER_AX_PD_16(m68ki_cpu_core *m68k);
839		INLINE UINT32 OPER_AX_PD_32(m68ki_cpu_core *m68k);
840		INLINE UINT32 OPER_AX_DI_8(m68ki_cpu_core *m68k);
841		INLINE UINT32 OPER_AX_DI_16(m68ki_cpu_core *m68k);
842		INLINE UINT32 OPER_AX_DI_32(m68ki_cpu_core *m68k);
843		INLINE UINT32 OPER_AX_IX_8(m68ki_cpu_core *m68k);
844		INLINE UINT32 OPER_AX_IX_16(m68ki_cpu_core *m68k);
845		INLINE UINT32 OPER_AX_IX_32(m68ki_cpu_core *m68k);
	537	INLINE UINT32 OPER_AX_AI_8(m68000_base_device *m68k);
	538	INLINE UINT32 OPER_AX_AI_16(m68000_base_device *m68k);
	539	INLINE UINT32 OPER_AX_AI_32(m68000_base_device *m68k);
	540	INLINE UINT32 OPER_AX_PI_8(m68000_base_device *m68k);
	541	INLINE UINT32 OPER_AX_PI_16(m68000_base_device *m68k);
	542	INLINE UINT32 OPER_AX_PI_32(m68000_base_device *m68k);
	543	INLINE UINT32 OPER_AX_PD_8(m68000_base_device *m68k);
	544	INLINE UINT32 OPER_AX_PD_16(m68000_base_device *m68k);
	545	INLINE UINT32 OPER_AX_PD_32(m68000_base_device *m68k);
	546	INLINE UINT32 OPER_AX_DI_8(m68000_base_device *m68k);
	547	INLINE UINT32 OPER_AX_DI_16(m68000_base_device *m68k);
	548	INLINE UINT32 OPER_AX_DI_32(m68000_base_device *m68k);
	549	INLINE UINT32 OPER_AX_IX_8(m68000_base_device *m68k);
	550	INLINE UINT32 OPER_AX_IX_16(m68000_base_device *m68k);
	551	INLINE UINT32 OPER_AX_IX_32(m68000_base_device *m68k);
846	552
847		INLINE UINT32 OPER_A7_PI_8(m68ki_cpu_core *m68k);
848		INLINE UINT32 OPER_A7_PD_8(m68ki_cpu_core *m68k);
	553	INLINE UINT32 OPER_A7_PI_8(m68000_base_device *m68k);
	554	INLINE UINT32 OPER_A7_PD_8(m68000_base_device *m68k);
849	555
850		INLINE UINT32 OPER_AW_8(m68ki_cpu_core *m68k);
851		INLINE UINT32 OPER_AW_16(m68ki_cpu_core *m68k);
852		INLINE UINT32 OPER_AW_32(m68ki_cpu_core *m68k);
853		INLINE UINT32 OPER_AL_8(m68ki_cpu_core *m68k);
854		INLINE UINT32 OPER_AL_16(m68ki_cpu_core *m68k);
855		INLINE UINT32 OPER_AL_32(m68ki_cpu_core *m68k);
856		INLINE UINT32 OPER_PCDI_8(m68ki_cpu_core *m68k);
857		INLINE UINT32 OPER_PCDI_16(m68ki_cpu_core *m68k);
858		INLINE UINT32 OPER_PCDI_32(m68ki_cpu_core *m68k);
859		INLINE UINT32 OPER_PCIX_8(m68ki_cpu_core *m68k);
860		INLINE UINT32 OPER_PCIX_16(m68ki_cpu_core *m68k);
861		INLINE UINT32 OPER_PCIX_32(m68ki_cpu_core *m68k);
	556	INLINE UINT32 OPER_AW_8(m68000_base_device *m68k);
	557	INLINE UINT32 OPER_AW_16(m68000_base_device *m68k);
	558	INLINE UINT32 OPER_AW_32(m68000_base_device *m68k);
	559	INLINE UINT32 OPER_AL_8(m68000_base_device *m68k);
	560	INLINE UINT32 OPER_AL_16(m68000_base_device *m68k);
	561	INLINE UINT32 OPER_AL_32(m68000_base_device *m68k);
	562	INLINE UINT32 OPER_PCDI_8(m68000_base_device *m68k);
	563	INLINE UINT32 OPER_PCDI_16(m68000_base_device *m68k);
	564	INLINE UINT32 OPER_PCDI_32(m68000_base_device *m68k);
	565	INLINE UINT32 OPER_PCIX_8(m68000_base_device *m68k);
	566	INLINE UINT32 OPER_PCIX_16(m68000_base_device *m68k);
	567	INLINE UINT32 OPER_PCIX_32(m68000_base_device *m68k);
862	568
863	569	/* Stack operations */
864		INLINE void m68ki_push_16(m68ki_cpu_core *m68k, UINT32 value);
865		INLINE void m68ki_push_32(m68ki_cpu_core *m68k, UINT32 value);
866		INLINE UINT32 m68ki_pull_16(m68ki_cpu_core *m68k);
867		INLINE UINT32 m68ki_pull_32(m68ki_cpu_core *m68k);
	570	INLINE void m68ki_push_16(m68000_base_device *m68k, UINT32 value);
	571	INLINE void m68ki_push_32(m68000_base_device *m68k, UINT32 value);
	572	INLINE UINT32 m68ki_pull_16(m68000_base_device *m68k);
	573	INLINE UINT32 m68ki_pull_32(m68000_base_device *m68k);
868	574
869	575	/* Program flow operations */
870		INLINE void m68ki_jump(m68ki_cpu_core *m68k, UINT32 new_pc);
871		INLINE void m68ki_jump_vector(m68ki_cpu_core *m68k, UINT32 vector);
872		INLINE void m68ki_branch_8(m68ki_cpu_core *m68k, UINT32 offset);
873		INLINE void m68ki_branch_16(m68ki_cpu_core *m68k, UINT32 offset);
874		INLINE void m68ki_branch_32(m68ki_cpu_core *m68k, UINT32 offset);
	576	INLINE void m68ki_jump(m68000_base_device *m68k, UINT32 new_pc);
	577	INLINE void m68ki_jump_vector(m68000_base_device *m68k, UINT32 vector);
	578	INLINE void m68ki_branch_8(m68000_base_device *m68k, UINT32 offset);
	579	INLINE void m68ki_branch_16(m68000_base_device *m68k, UINT32 offset);
	580	INLINE void m68ki_branch_32(m68000_base_device *m68k, UINT32 offset);
875	581
876	582	/* Status register operations. */
877		INLINE void m68ki_set_s_flag(m68ki_cpu_core m68k, UINT32 value); / Only bit 2 of value should be set (i.e. 4 or 0) */
878		INLINE void m68ki_set_sm_flag(m68ki_cpu_core m68k, UINT32 value); / only bits 1 and 2 of value should be set */
879		INLINE void m68ki_set_ccr(m68ki_cpu_core m68k, UINT32 value); / set the condition code register */
880		INLINE void m68ki_set_sr(m68ki_cpu_core m68k, UINT32 value); / set the status register */
881		INLINE void m68ki_set_sr_noint(m68ki_cpu_core m68k, UINT32 value); / set the status register */
	583	INLINE void m68ki_set_s_flag(m68000_base_device m68k, UINT32 value); / Only bit 2 of value should be set (i.e. 4 or 0) */
	584	INLINE void m68ki_set_sm_flag(m68000_base_device m68k, UINT32 value); / only bits 1 and 2 of value should be set */
	585	INLINE void m68ki_set_ccr(m68000_base_device m68k, UINT32 value); / set the condition code register */
	586	INLINE void m68ki_set_sr(m68000_base_device m68k, UINT32 value); / set the status register */
	587	INLINE void m68ki_set_sr_noint(m68000_base_device m68k, UINT32 value); / set the status register */
882	588
883	589	/* Exception processing */
884		INLINE UINT32 m68ki_init_exception(m68ki_~~cpu~~_core m68k); / Initial exception processing */
	590	INLINE UINT32 m68ki_init_exception(m68000_base_device m68k); / Initial exception processing */
885	591
886		INLINE void m68ki_stack_frame_3word(m68ki_cpu_core m68k, UINT32 pc, UINT32 sr); / Stack various frame types */
887		INLINE void m68ki_stack_frame_buserr(m68ki_cpu_core *m68k, UINT32 sr);
	592	INLINE void m68ki_stack_frame_3word(m68000_base_device m68k, UINT32 pc, UINT32 sr); / Stack various frame types */
	593	INLINE void m68ki_stack_frame_buserr(m68000_base_device *m68k, UINT32 sr);
888	594
889		INLINE void m68ki_stack_frame_0000(m68ki_cpu_core *m68k, UINT32 pc, UINT32 sr, UINT32 vector);
890		INLINE void m68ki_stack_frame_0001(m68ki_cpu_core *m68k, UINT32 pc, UINT32 sr, UINT32 vector);
891		INLINE void m68ki_stack_frame_0010(m68ki_cpu_core *m68k, UINT32 sr, UINT32 vector);
892		INLINE void m68ki_stack_frame_1000(m68ki_cpu_core *m68k, UINT32 pc, UINT32 sr, UINT32 vector);
893		INLINE void m68ki_stack_frame_1010(m68ki_cpu_core *m68k, UINT32 sr, UINT32 vector, UINT32 pc, UINT32 fault_address);
894		INLINE void m68ki_stack_frame_1011(m68ki_cpu_core *m68k, UINT32 sr, UINT32 vector, UINT32 pc, UINT32 fault_address);
895		INLINE void m68ki_stack_frame_0111(m68ki_cpu_core *m68k, UINT32 sr, UINT32 vector, UINT32 pc, UINT32 fault_address, bool in_mmu);
	595	INLINE void m68ki_stack_frame_0000(m68000_base_device *m68k, UINT32 pc, UINT32 sr, UINT32 vector);
	596	INLINE void m68ki_stack_frame_0001(m68000_base_device *m68k, UINT32 pc, UINT32 sr, UINT32 vector);
	597	INLINE void m68ki_stack_frame_0010(m68000_base_device *m68k, UINT32 sr, UINT32 vector);
	598	INLINE void m68ki_stack_frame_1000(m68000_base_device *m68k, UINT32 pc, UINT32 sr, UINT32 vector);
	599	INLINE void m68ki_stack_frame_1010(m68000_base_device *m68k, UINT32 sr, UINT32 vector, UINT32 pc, UINT32 fault_address);
	600	INLINE void m68ki_stack_frame_1011(m68000_base_device *m68k, UINT32 sr, UINT32 vector, UINT32 pc, UINT32 fault_address);
	601	INLINE void m68ki_stack_frame_0111(m68000_base_device *m68k, UINT32 sr, UINT32 vector, UINT32 pc, UINT32 fault_address, bool in_mmu);
896	602
897		INLINE void m68ki_exception_trap(m68ki_cpu_core *m68k, UINT32 vector);
898		INLINE void m68ki_exception_trapN(m68ki_cpu_core *m68k, UINT32 vector);
899		INLINE void m68ki_exception_trace(m68ki_cpu_core *m68k);
900		INLINE void m68ki_exception_privilege_violation(m68ki_cpu_core *m68k);
901		INLINE void m68ki_exception_1010(m68ki_cpu_core *m68k);
902		INLINE void m68ki_exception_1111(m68ki_cpu_core *m68k);
903		INLINE void m68ki_exception_illegal(m68ki_cpu_core *m68k);
904		INLINE void m68ki_exception_format_error(m68ki_cpu_core *m68k);
905		INLINE void m68ki_exception_address_error(m68ki_cpu_core *m68k);
906		INLINE void m68ki_exception_interrupt(m68ki_cpu_core *m68k, UINT32 int_level);
907		INLINE void m68ki_check_interrupts(m68ki_cpu_core m68k); / ASG: check for interrupts */
	603	INLINE void m68ki_exception_trap(m68000_base_device *m68k, UINT32 vector);
	604	INLINE void m68ki_exception_trapN(m68000_base_device *m68k, UINT32 vector);
	605	INLINE void m68ki_exception_trace(m68000_base_device *m68k);
	606	INLINE void m68ki_exception_privilege_violation(m68000_base_device *m68k);
	607	INLINE void m68ki_exception_1010(m68000_base_device *m68k);
	608	INLINE void m68ki_exception_1111(m68000_base_device *m68k);
	609	INLINE void m68ki_exception_illegal(m68000_base_device *m68k);
	610	INLINE void m68ki_exception_format_error(m68000_base_device *m68k);
	611	INLINE void m68ki_exception_address_error(m68000_base_device *m68k);
908	612
	613	INLINE void m68ki_check_interrupts(m68000_base_device m68k); / ASG: check for interrupts */
	614
909	615	/* quick disassembly (used for logging) */
910	616	char* m68ki_disassemble_quick(unsigned int pc, unsigned int cpu_type);
911	617
r23920	r23921
915	621	/* ======================================================================== */
916	622
917	623
918		INLINE unsigned int m68k_read_immediate_32(m68ki_~~cpu~~_core *m68k, unsigned int address)
	624	INLINE unsigned int m68k_read_immediate_32(m68000_base_device *m68k, unsigned int address)
919	625	{
920		return (m68k->memory.readimm16(address) << 16) \| m68k->memory.readimm16(address + 2);
	626	return (m68k->/memory./readimm16(address) << 16) \| m68k->/memory./readimm16(address + 2);
921	627	}
922	628
923		INLINE unsigned int m68k_read_pcrelative_8(m68ki_~~cpu~~_core *m68k, unsigned int address)
	629	INLINE unsigned int m68k_read_pcrelative_8(m68000_base_device *m68k, unsigned int address)
924	630	{
925	631	if (address >= m68k->encrypted_start && address < m68k->encrypted_end)
926		return ((m68k->memory.readimm16(address&~1)>>(8*(1-(address & 1))))&0xff);
	632	return ((m68k->/memory./readimm16(address&~1)>>(8*(1-(address & 1))))&0xff);
927	633
928		return m68k->memory.read8(address);
	634	return m68k->/memory./read8(address);
929	635	}
930	636
931		INLINE unsigned int m68k_read_pcrelative_16(m68ki_~~cpu~~_core *m68k, unsigned int address)
	637	INLINE unsigned int m68k_read_pcrelative_16(m68000_base_device *m68k, unsigned int address)
932	638	{
933	639	if (address >= m68k->encrypted_start && address < m68k->encrypted_end)
934		return m68k->memory.readimm16(address);
	640	return m68k->/memory./readimm16(address);
935	641
936		return m68k->memory.read16(address);
	642	return m68k->/memory./read16(address);
937	643	}
938	644
939		INLINE unsigned int m68k_read_pcrelative_32(m68ki_~~cpu~~_core *m68k, unsigned int address)
	645	INLINE unsigned int m68k_read_pcrelative_32(m68000_base_device *m68k, unsigned int address)
940	646	{
941	647	if (address >= m68k->encrypted_start && address < m68k->encrypted_end)
942	648	return m68k_read_immediate_32(m68k, address);
943	649
944		return m68k->memory.read32(address);
	650	return m68k->/memory./read32(address);
945	651	}
946	652
947	653
r23920	r23921
950	656	* A real 68k first writes the high word to [address+2], and then writes the
951	657	* low word to [address].
952	658	*/
953		INLINE void m68kx_write_memory_32_pd(m68ki_~~cpu~~_core *m68k, unsigned int address, unsigned int value)
	659	INLINE void m68kx_write_memory_32_pd(m68000_base_device *m68k, unsigned int address, unsigned int value)
954	660	{
955		m68k->memory.write16(address+2, value>>16);
956		m68k->memory.write16(address, value&0xffff);
	661	m68k->/memory./write16(address+2, value>>16);
	662	m68k->/memory./write16(address, value&0xffff);
957	663	}
958	664
959	665
960	666	/* ---------------------------- Read Immediate ---------------------------- */
961	667
962	668	// clear the instruction cache
963		INLINE void m68ki_ic_clear(m68ki_~~cpu~~_core *m68k)
	669	INLINE void m68ki_ic_clear(m68000_base_device *m68k)
964	670	{
965	671	int i;
966	672	for (i=0; i< M68K_IC_SIZE; i++) {
r23920	r23921
970	676
971	677	// read immediate word using the instruction cache
972	678
973		INLINE UINT32 m68ki_ic_readimm16(m68ki_~~cpu~~_core *m68k, UINT32 address)
	679	INLINE UINT32 m68ki_ic_readimm16(m68000_base_device *m68k, UINT32 address)
974	680	{
975	681	/* if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type) && (m68k->cacr & M68K_CACR_EI))
976	682	{
r23920	r23921
992	698	}
993	699	else*/
994	700	{
995		return m68k->memory.readimm16(address);
	701	return m68k->/memory./readimm16(address);
996	702	}
997	703
998	704	// this can't happen, but Apple GCC insists
r23920	r23921
1002	708	/* Handles all immediate reads, does address error check, function code setting,
1003	709	* and prefetching if they are enabled in m68kconf.h
1004	710	*/
1005		INLINE UINT32 m68ki_read_imm_16(m68ki_~~cpu~~_core *m68k)
	711	INLINE UINT32 m68ki_read_imm_16(m68000_base_device *m68k)
1006	712	{
1007	713	UINT32 result;
1008	714
r23920	r23921
1029	735	return result;
1030	736	}
1031	737
1032		INLINE UINT32 m68ki_read_imm_32(m68ki_~~cpu~~_core *m68k)
	738	INLINE UINT32 m68ki_read_imm_32(m68000_base_device *m68k)
1033	739	{
1034	740	UINT32 temp_val;
1035	741
r23920	r23921
1066	772	* These functions will also check for address error and set the function
1067	773	* code if they are enabled in m68kconf.h.
1068	774	*/
1069		INLINE UINT32 m68ki_read_8_fc(m68ki_~~cpu~~_core *m68k, UINT32 address, UINT32 fc)
	775	INLINE UINT32 m68ki_read_8_fc(m68000_base_device *m68k, UINT32 address, UINT32 fc)
1070	776	{
1071	777	m68k->mmu_tmp_fc = fc;
1072	778	m68k->mmu_tmp_rw = 1;
1073		return m68k->memory.read8(address);
	779	return m68k->/memory./read8(address);
1074	780	}
1075		INLINE UINT32 m68ki_read_16_fc(m68ki_~~cpu~~_core *m68k, UINT32 address, UINT32 fc)
	781	INLINE UINT32 m68ki_read_16_fc(m68000_base_device *m68k, UINT32 address, UINT32 fc)
1076	782	{
1077	783	if (CPU_TYPE_IS_010_LESS(m68k->cpu_type))
1078	784	{
r23920	r23921
1080	786	}
1081	787	m68k->mmu_tmp_fc = fc;
1082	788	m68k->mmu_tmp_rw = 1;
1083		return m68k->memory.read16(address);
	789	return m68k->/memory./read16(address);
1084	790	}
1085		INLINE UINT32 m68ki_read_32_fc(m68ki_~~cpu~~_core *m68k, UINT32 address, UINT32 fc)
	791	INLINE UINT32 m68ki_read_32_fc(m68000_base_device *m68k, UINT32 address, UINT32 fc)
1086	792	{
1087	793	if (CPU_TYPE_IS_010_LESS(m68k->cpu_type))
1088	794	{
r23920	r23921
1090	796	}
1091	797	m68k->mmu_tmp_fc = fc;
1092	798	m68k->mmu_tmp_rw = 1;
1093		return m68k->memory.read32(address);
	799	return m68k->/memory./read32(address);
1094	800	}
1095	801
1096		INLINE void m68ki_write_8_fc(m68ki_~~cpu~~_core *m68k, UINT32 address, UINT32 fc, UINT32 value)
	802	INLINE void m68ki_write_8_fc(m68000_base_device *m68k, UINT32 address, UINT32 fc, UINT32 value)
1097	803	{
1098	804	m68k->mmu_tmp_fc = fc;
1099	805	m68k->mmu_tmp_rw = 0;
1100		m68k->memory.write8(address, value);
	806	m68k->/memory./write8(address, value);
1101	807	}
1102		INLINE void m68ki_write_16_fc(m68ki_~~cpu~~_core *m68k, UINT32 address, UINT32 fc, UINT32 value)
	808	INLINE void m68ki_write_16_fc(m68000_base_device *m68k, UINT32 address, UINT32 fc, UINT32 value)
1103	809	{
1104	810	if (CPU_TYPE_IS_010_LESS(m68k->cpu_type))
1105	811	{
r23920	r23921
1107	813	}
1108	814	m68k->mmu_tmp_fc = fc;
1109	815	m68k->mmu_tmp_rw = 0;
1110		m68k->memory.write16(address, value);
	816	m68k->/memory./write16(address, value);
1111	817	}
1112		INLINE void m68ki_write_32_fc(m68ki_~~cpu~~_core *m68k, UINT32 address, UINT32 fc, UINT32 value)
	818	INLINE void m68ki_write_32_fc(m68000_base_device *m68k, UINT32 address, UINT32 fc, UINT32 value)
1113	819	{
1114	820	if (CPU_TYPE_IS_010_LESS(m68k->cpu_type))
1115	821	{
r23920	r23921
1117	823	}
1118	824	m68k->mmu_tmp_fc = fc;
1119	825	m68k->mmu_tmp_rw = 0;
1120		m68k->memory.write32(address, value);
	826	m68k->/memory./write32(address, value);
1121	827	}
1122	828
1123	829	/* Special call to simulate undocumented 68k behavior when move.l with a
r23920	r23921
1125	831	* A real 68k first writes the high word to [address+2], and then writes the
1126	832	* low word to [address].
1127	833	*/
1128		INLINE void m68ki_write_32_pd_fc(m68ki_~~cpu~~_core *m68k, UINT32 address, UINT32 fc, UINT32 value)
	834	INLINE void m68ki_write_32_pd_fc(m68000_base_device *m68k, UINT32 address, UINT32 fc, UINT32 value)
1129	835	{
1130	836	if (CPU_TYPE_IS_010_LESS(m68k->cpu_type))
1131	837	{
r23920	r23921
1133	839	}
1134	840	m68k->mmu_tmp_fc = fc;
1135	841	m68k->mmu_tmp_rw = 0;
1136		m68k->memory.write16(address+2, value>>16);
1137		m68k->memory.write16(address, value&0xffff);
	842	m68k->/memory./write16(address+2, value>>16);
	843	m68k->/memory./write16(address, value&0xffff);
1138	844	}
1139	845
1140	846
r23920	r23921
1143	849	/* The program counter relative addressing modes cause operands to be
1144	850	* retrieved from program space, not data space.
1145	851	*/
1146		INLINE UINT32 m68ki_get_ea_pcdi(m68ki_~~cpu~~_core *m68k)
	852	INLINE UINT32 m68ki_get_ea_pcdi(m68000_base_device *m68k)
1147	853	{
1148	854	UINT32 old_pc = REG_PC(m68k);
1149	855	return old_pc + MAKE_INT_16(m68ki_read_imm_16(m68k));
1150	856	}
1151	857
1152	858
1153		INLINE UINT32 m68ki_get_ea_pcix(m68ki_~~cpu~~_core *m68k)
	859	INLINE UINT32 m68ki_get_ea_pcix(m68000_base_device *m68k)
1154	860	{
1155	861	return m68ki_get_ea_ix(m68k, REG_PC(m68k));
1156	862	}
r23920	r23921
1197	903	* 1 011 mem indir with long outer
1198	904	* 1 100-111 reserved
1199	905	*/
1200		INLINE UINT32 m68ki_get_ea_ix(m68ki_~~cpu~~_core *m68k, UINT32 An)
	906	INLINE UINT32 m68ki_get_ea_ix(m68000_base_device *m68k, UINT32 An)
1201	907	{
1202	908	/* An = base register */
1203	909	UINT32 extension = m68ki_read_imm_16(m68k);
r23920	r23921
1270	976
1271	977
1272	978	/* Fetch operands */
1273		INLINE UINT32 OPER_AY_AI_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_AI_8(m68k); return m68ki_read_8(m68k, ea); }
1274		INLINE UINT32 OPER_AY_AI_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_AI_16(m68k); return m68ki_read_16(m68k, ea);}
1275		INLINE UINT32 OPER_AY_AI_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_AI_32(m68k); return m68ki_read_32(m68k, ea);}
1276		INLINE UINT32 OPER_AY_PI_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_PI_8(m68k); return m68ki_read_8(m68k, ea); }
1277		INLINE UINT32 OPER_AY_PI_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_PI_16(m68k); return m68ki_read_16(m68k, ea);}
1278		INLINE UINT32 OPER_AY_PI_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_PI_32(m68k); return m68ki_read_32(m68k, ea);}
1279		INLINE UINT32 OPER_AY_PD_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_PD_8(m68k); return m68ki_read_8(m68k, ea); }
1280		INLINE UINT32 OPER_AY_PD_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_PD_16(m68k); return m68ki_read_16(m68k, ea);}
1281		INLINE UINT32 OPER_AY_PD_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_PD_32(m68k); return m68ki_read_32(m68k, ea);}
1282		INLINE UINT32 OPER_AY_DI_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_DI_8(m68k); return m68ki_read_8(m68k, ea); }
1283		INLINE UINT32 OPER_AY_DI_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_DI_16(m68k); return m68ki_read_16(m68k, ea);}
1284		INLINE UINT32 OPER_AY_DI_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_DI_32(m68k); return m68ki_read_32(m68k, ea);}
1285		INLINE UINT32 OPER_AY_IX_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_IX_8(m68k); return m68ki_read_8(m68k, ea); }
1286		INLINE UINT32 OPER_AY_IX_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_IX_16(m68k); return m68ki_read_16(m68k, ea);}
1287		INLINE UINT32 OPER_AY_IX_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_IX_32(m68k); return m68ki_read_32(m68k, ea);}
	979	INLINE UINT32 OPER_AY_AI_8(m68000_base_device *m68k) {UINT32 ea = EA_AY_AI_8(m68k); return m68ki_read_8(m68k, ea); }
	980	INLINE UINT32 OPER_AY_AI_16(m68000_base_device *m68k) {UINT32 ea = EA_AY_AI_16(m68k); return m68ki_read_16(m68k, ea);}
	981	INLINE UINT32 OPER_AY_AI_32(m68000_base_device *m68k) {UINT32 ea = EA_AY_AI_32(m68k); return m68ki_read_32(m68k, ea);}
	982	INLINE UINT32 OPER_AY_PI_8(m68000_base_device *m68k) {UINT32 ea = EA_AY_PI_8(m68k); return m68ki_read_8(m68k, ea); }
	983	INLINE UINT32 OPER_AY_PI_16(m68000_base_device *m68k) {UINT32 ea = EA_AY_PI_16(m68k); return m68ki_read_16(m68k, ea);}
	984	INLINE UINT32 OPER_AY_PI_32(m68000_base_device *m68k) {UINT32 ea = EA_AY_PI_32(m68k); return m68ki_read_32(m68k, ea);}
	985	INLINE UINT32 OPER_AY_PD_8(m68000_base_device *m68k) {UINT32 ea = EA_AY_PD_8(m68k); return m68ki_read_8(m68k, ea); }
	986	INLINE UINT32 OPER_AY_PD_16(m68000_base_device *m68k) {UINT32 ea = EA_AY_PD_16(m68k); return m68ki_read_16(m68k, ea);}
	987	INLINE UINT32 OPER_AY_PD_32(m68000_base_device *m68k) {UINT32 ea = EA_AY_PD_32(m68k); return m68ki_read_32(m68k, ea);}
	988	INLINE UINT32 OPER_AY_DI_8(m68000_base_device *m68k) {UINT32 ea = EA_AY_DI_8(m68k); return m68ki_read_8(m68k, ea); }
	989	INLINE UINT32 OPER_AY_DI_16(m68000_base_device *m68k) {UINT32 ea = EA_AY_DI_16(m68k); return m68ki_read_16(m68k, ea);}
	990	INLINE UINT32 OPER_AY_DI_32(m68000_base_device *m68k) {UINT32 ea = EA_AY_DI_32(m68k); return m68ki_read_32(m68k, ea);}
	991	INLINE UINT32 OPER_AY_IX_8(m68000_base_device *m68k) {UINT32 ea = EA_AY_IX_8(m68k); return m68ki_read_8(m68k, ea); }
	992	INLINE UINT32 OPER_AY_IX_16(m68000_base_device *m68k) {UINT32 ea = EA_AY_IX_16(m68k); return m68ki_read_16(m68k, ea);}
	993	INLINE UINT32 OPER_AY_IX_32(m68000_base_device *m68k) {UINT32 ea = EA_AY_IX_32(m68k); return m68ki_read_32(m68k, ea);}
1288	994
1289		INLINE UINT32 OPER_AX_AI_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_AI_8(m68k); return m68ki_read_8(m68k, ea); }
1290		INLINE UINT32 OPER_AX_AI_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_AI_16(m68k); return m68ki_read_16(m68k, ea);}
1291		INLINE UINT32 OPER_AX_AI_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_AI_32(m68k); return m68ki_read_32(m68k, ea);}
1292		INLINE UINT32 OPER_AX_PI_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_PI_8(m68k); return m68ki_read_8(m68k, ea); }
1293		INLINE UINT32 OPER_AX_PI_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_PI_16(m68k); return m68ki_read_16(m68k, ea);}
1294		INLINE UINT32 OPER_AX_PI_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_PI_32(m68k); return m68ki_read_32(m68k, ea);}
1295		INLINE UINT32 OPER_AX_PD_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_PD_8(m68k); return m68ki_read_8(m68k, ea); }
1296		INLINE UINT32 OPER_AX_PD_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_PD_16(m68k); return m68ki_read_16(m68k, ea);}
1297		INLINE UINT32 OPER_AX_PD_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_PD_32(m68k); return m68ki_read_32(m68k, ea);}
1298		INLINE UINT32 OPER_AX_DI_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_DI_8(m68k); return m68ki_read_8(m68k, ea); }
1299		INLINE UINT32 OPER_AX_DI_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_DI_16(m68k); return m68ki_read_16(m68k, ea);}
1300		INLINE UINT32 OPER_AX_DI_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_DI_32(m68k); return m68ki_read_32(m68k, ea);}
1301		INLINE UINT32 OPER_AX_IX_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_IX_8(m68k); return m68ki_read_8(m68k, ea); }
1302		INLINE UINT32 OPER_AX_IX_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_IX_16(m68k); return m68ki_read_16(m68k, ea);}
1303		INLINE UINT32 OPER_AX_IX_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_IX_32(m68k); return m68ki_read_32(m68k, ea);}
	995	INLINE UINT32 OPER_AX_AI_8(m68000_base_device *m68k) {UINT32 ea = EA_AX_AI_8(m68k); return m68ki_read_8(m68k, ea); }
	996	INLINE UINT32 OPER_AX_AI_16(m68000_base_device *m68k) {UINT32 ea = EA_AX_AI_16(m68k); return m68ki_read_16(m68k, ea);}
	997	INLINE UINT32 OPER_AX_AI_32(m68000_base_device *m68k) {UINT32 ea = EA_AX_AI_32(m68k); return m68ki_read_32(m68k, ea);}
	998	INLINE UINT32 OPER_AX_PI_8(m68000_base_device *m68k) {UINT32 ea = EA_AX_PI_8(m68k); return m68ki_read_8(m68k, ea); }
	999	INLINE UINT32 OPER_AX_PI_16(m68000_base_device *m68k) {UINT32 ea = EA_AX_PI_16(m68k); return m68ki_read_16(m68k, ea);}
	1000	INLINE UINT32 OPER_AX_PI_32(m68000_base_device *m68k) {UINT32 ea = EA_AX_PI_32(m68k); return m68ki_read_32(m68k, ea);}
	1001	INLINE UINT32 OPER_AX_PD_8(m68000_base_device *m68k) {UINT32 ea = EA_AX_PD_8(m68k); return m68ki_read_8(m68k, ea); }
	1002	INLINE UINT32 OPER_AX_PD_16(m68000_base_device *m68k) {UINT32 ea = EA_AX_PD_16(m68k); return m68ki_read_16(m68k, ea);}
	1003	INLINE UINT32 OPER_AX_PD_32(m68000_base_device *m68k) {UINT32 ea = EA_AX_PD_32(m68k); return m68ki_read_32(m68k, ea);}
	1004	INLINE UINT32 OPER_AX_DI_8(m68000_base_device *m68k) {UINT32 ea = EA_AX_DI_8(m68k); return m68ki_read_8(m68k, ea); }
	1005	INLINE UINT32 OPER_AX_DI_16(m68000_base_device *m68k) {UINT32 ea = EA_AX_DI_16(m68k); return m68ki_read_16(m68k, ea);}
	1006	INLINE UINT32 OPER_AX_DI_32(m68000_base_device *m68k) {UINT32 ea = EA_AX_DI_32(m68k); return m68ki_read_32(m68k, ea);}
	1007	INLINE UINT32 OPER_AX_IX_8(m68000_base_device *m68k) {UINT32 ea = EA_AX_IX_8(m68k); return m68ki_read_8(m68k, ea); }
	1008	INLINE UINT32 OPER_AX_IX_16(m68000_base_device *m68k) {UINT32 ea = EA_AX_IX_16(m68k); return m68ki_read_16(m68k, ea);}
	1009	INLINE UINT32 OPER_AX_IX_32(m68000_base_device *m68k) {UINT32 ea = EA_AX_IX_32(m68k); return m68ki_read_32(m68k, ea);}
1304	1010
1305		INLINE UINT32 OPER_A7_PI_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_A7_PI_8(m68k); return m68ki_read_8(m68k, ea); }
1306		INLINE UINT32 OPER_A7_PD_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_A7_PD_8(m68k); return m68ki_read_8(m68k, ea); }
	1011	INLINE UINT32 OPER_A7_PI_8(m68000_base_device *m68k) {UINT32 ea = EA_A7_PI_8(m68k); return m68ki_read_8(m68k, ea); }
	1012	INLINE UINT32 OPER_A7_PD_8(m68000_base_device *m68k) {UINT32 ea = EA_A7_PD_8(m68k); return m68ki_read_8(m68k, ea); }
1307	1013
1308		INLINE UINT32 OPER_AW_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AW_8(m68k); return m68ki_read_8(m68k, ea); }
1309		INLINE UINT32 OPER_AW_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AW_16(m68k); return m68ki_read_16(m68k, ea);}
1310		INLINE UINT32 OPER_AW_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AW_32(m68k); return m68ki_read_32(m68k, ea);}
1311		INLINE UINT32 OPER_AL_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AL_8(m68k); return m68ki_read_8(m68k, ea); }
1312		INLINE UINT32 OPER_AL_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AL_16(m68k); return m68ki_read_16(m68k, ea);}
1313		INLINE UINT32 OPER_AL_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AL_32(m68k); return m68ki_read_32(m68k, ea);}
1314		INLINE UINT32 OPER_PCDI_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_PCDI_8(m68k); return m68ki_read_pcrel_8(m68k, ea); }
1315		INLINE UINT32 OPER_PCDI_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_PCDI_16(m68k); return m68ki_read_pcrel_16(m68k, ea);}
1316		INLINE UINT32 OPER_PCDI_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_PCDI_32(m68k); return m68ki_read_pcrel_32(m68k, ea);}
1317		INLINE UINT32 OPER_PCIX_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_PCIX_8(m68k); return m68ki_read_pcrel_8(m68k, ea); }
1318		INLINE UINT32 OPER_PCIX_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_PCIX_16(m68k); return m68ki_read_pcrel_16(m68k, ea);}
1319		INLINE UINT32 OPER_PCIX_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_PCIX_32(m68k); return m68ki_read_pcrel_32(m68k, ea);}
	1014	INLINE UINT32 OPER_AW_8(m68000_base_device *m68k) {UINT32 ea = EA_AW_8(m68k); return m68ki_read_8(m68k, ea); }
	1015	INLINE UINT32 OPER_AW_16(m68000_base_device *m68k) {UINT32 ea = EA_AW_16(m68k); return m68ki_read_16(m68k, ea);}
	1016	INLINE UINT32 OPER_AW_32(m68000_base_device *m68k) {UINT32 ea = EA_AW_32(m68k); return m68ki_read_32(m68k, ea);}
	1017	INLINE UINT32 OPER_AL_8(m68000_base_device *m68k) {UINT32 ea = EA_AL_8(m68k); return m68ki_read_8(m68k, ea); }
	1018	INLINE UINT32 OPER_AL_16(m68000_base_device *m68k) {UINT32 ea = EA_AL_16(m68k); return m68ki_read_16(m68k, ea);}
	1019	INLINE UINT32 OPER_AL_32(m68000_base_device *m68k) {UINT32 ea = EA_AL_32(m68k); return m68ki_read_32(m68k, ea);}
	1020	INLINE UINT32 OPER_PCDI_8(m68000_base_device *m68k) {UINT32 ea = EA_PCDI_8(m68k); return m68ki_read_pcrel_8(m68k, ea); }
	1021	INLINE UINT32 OPER_PCDI_16(m68000_base_device *m68k) {UINT32 ea = EA_PCDI_16(m68k); return m68ki_read_pcrel_16(m68k, ea);}
	1022	INLINE UINT32 OPER_PCDI_32(m68000_base_device *m68k) {UINT32 ea = EA_PCDI_32(m68k); return m68ki_read_pcrel_32(m68k, ea);}
	1023	INLINE UINT32 OPER_PCIX_8(m68000_base_device *m68k) {UINT32 ea = EA_PCIX_8(m68k); return m68ki_read_pcrel_8(m68k, ea); }
	1024	INLINE UINT32 OPER_PCIX_16(m68000_base_device *m68k) {UINT32 ea = EA_PCIX_16(m68k); return m68ki_read_pcrel_16(m68k, ea);}
	1025	INLINE UINT32 OPER_PCIX_32(m68000_base_device *m68k) {UINT32 ea = EA_PCIX_32(m68k); return m68ki_read_pcrel_32(m68k, ea);}
1320	1026
1321	1027
1322	1028
1323	1029	/* ---------------------------- Stack Functions --------------------------- */
1324	1030
1325	1031	/* Push/pull data from the stack */
1326		INLINE void m68ki_push_16(m68ki_~~cpu~~_core *m68k, UINT32 value)
	1032	INLINE void m68ki_push_16(m68000_base_device *m68k, UINT32 value)
1327	1033	{
1328	1034	REG_SP(m68k) = MASK_OUT_ABOVE_32(REG_SP(m68k) - 2);
1329	1035	m68ki_write_16(m68k, REG_SP(m68k), value);
1330	1036	}
1331	1037
1332		INLINE void m68ki_push_32(m68ki_~~cpu~~_core *m68k, UINT32 value)
	1038	INLINE void m68ki_push_32(m68000_base_device *m68k, UINT32 value)
1333	1039	{
1334	1040	REG_SP(m68k) = MASK_OUT_ABOVE_32(REG_SP(m68k) - 4);
1335	1041	m68ki_write_32(m68k, REG_SP(m68k), value);
1336	1042	}
1337	1043
1338		INLINE UINT32 m68ki_pull_16(m68ki_~~cpu~~_core *m68k)
	1044	INLINE UINT32 m68ki_pull_16(m68000_base_device *m68k)
1339	1045	{
1340	1046	REG_SP(m68k) = MASK_OUT_ABOVE_32(REG_SP(m68k) + 2);
1341	1047	return m68ki_read_16(m68k, REG_SP(m68k)-2);
1342	1048	}
1343	1049
1344		INLINE UINT32 m68ki_pull_32(m68ki_~~cpu~~_core *m68k)
	1050	INLINE UINT32 m68ki_pull_32(m68000_base_device *m68k)
1345	1051	{
1346	1052	REG_SP(m68k) = MASK_OUT_ABOVE_32(REG_SP(m68k) + 4);
1347	1053	return m68ki_read_32(m68k, REG_SP(m68k)-4);
r23920	r23921
1351	1057	/* Increment/decrement the stack as if doing a push/pull but
1352	1058	* don't do any memory access.
1353	1059	*/
1354		INLINE void m68ki_fake_push_16(m68ki_~~cpu~~_core *m68k)
	1060	INLINE void m68ki_fake_push_16(m68000_base_device *m68k)
1355	1061	{
1356	1062	REG_SP(m68k) = MASK_OUT_ABOVE_32(REG_SP(m68k) - 2);
1357	1063	}
1358	1064
1359		INLINE void m68ki_fake_push_32(m68ki_~~cpu~~_core *m68k)
	1065	INLINE void m68ki_fake_push_32(m68000_base_device *m68k)
1360	1066	{
1361	1067	REG_SP(m68k) = MASK_OUT_ABOVE_32(REG_SP(m68k) - 4);
1362	1068	}
1363	1069
1364		INLINE void m68ki_fake_pull_16(m68ki_~~cpu~~_core *m68k)
	1070	INLINE void m68ki_fake_pull_16(m68000_base_device *m68k)
1365	1071	{
1366	1072	REG_SP(m68k) = MASK_OUT_ABOVE_32(REG_SP(m68k) + 2);
1367	1073	}
1368	1074
1369		INLINE void m68ki_fake_pull_32(m68ki_~~cpu~~_core *m68k)
	1075	INLINE void m68ki_fake_pull_32(m68000_base_device *m68k)
1370	1076	{
1371	1077	REG_SP(m68k) = MASK_OUT_ABOVE_32(REG_SP(m68k) + 4);
1372	1078	}
r23920	r23921
1378	1084	* These functions will also call the pc_changed callback if it was enabled
1379	1085	* in m68kconf.h.
1380	1086	*/
1381		INLINE void m68ki_jump(m68ki_~~cpu~~_core *m68k, UINT32 new_pc)
	1087	INLINE void m68ki_jump(m68000_base_device *m68k, UINT32 new_pc)
1382	1088	{
1383	1089	REG_PC(m68k) = new_pc;
1384	1090	}
1385	1091
1386		INLINE void m68ki_jump_vector(m68ki_~~cpu~~_core *m68k, UINT32 vector)
	1092	INLINE void m68ki_jump_vector(m68000_base_device *m68k, UINT32 vector)
1387	1093	{
1388	1094	REG_PC(m68k) = (vector<<2) + m68k->vbr;
1389	1095	REG_PC(m68k) = m68ki_read_data_32(m68k, REG_PC(m68k));
r23920	r23921
1395	1101	* So far I've found no problems with not calling pc_changed for 8 or 16
1396	1102	* bit branches.
1397	1103	*/
1398		INLINE void m68ki_branch_8(m68ki_~~cpu~~_core *m68k, UINT32 offset)
	1104	INLINE void m68ki_branch_8(m68000_base_device *m68k, UINT32 offset)
1399	1105	{
1400	1106	REG_PC(m68k) += MAKE_INT_8(offset);
1401	1107	}
1402	1108
1403		INLINE void m68ki_branch_16(m68ki_~~cpu~~_core *m68k, UINT32 offset)
	1109	INLINE void m68ki_branch_16(m68000_base_device *m68k, UINT32 offset)
1404	1110	{
1405	1111	REG_PC(m68k) += MAKE_INT_16(offset);
1406	1112	}
1407	1113
1408		INLINE void m68ki_branch_32(m68ki_~~cpu~~_core *m68k, UINT32 offset)
	1114	INLINE void m68ki_branch_32(m68000_base_device *m68k, UINT32 offset)
1409	1115	{
1410	1116	REG_PC(m68k) += offset;
1411	1117	}
r23920	r23921
1417	1123	/* Set the S flag and change the active stack pointer.
1418	1124	* Note that value MUST be 4 or 0.
1419	1125	*/
1420		INLINE void m68ki_set_s_flag(m68ki_~~cpu~~_core *m68k, UINT32 value)
	1126	INLINE void m68ki_set_s_flag(m68000_base_device *m68k, UINT32 value)
1421	1127	{
1422	1128	/* Backup the old stack pointer */
1423	1129	REG_SP_BASE(m68k)[m68k->s_flag \| ((m68k->s_flag>>1) & m68k->m_flag)] = REG_SP(m68k);
r23920	r23921
1430	1136	/* Set the S and M flags and change the active stack pointer.
1431	1137	* Note that value MUST be 0, 2, 4, or 6 (bit2 = S, bit1 = M).
1432	1138	*/
1433		INLINE void m68ki_set_sm_flag(m68ki_~~cpu~~_core *m68k, UINT32 value)
	1139	INLINE void m68ki_set_sm_flag(m68000_base_device *m68k, UINT32 value)
1434	1140	{
1435	1141	/* Backup the old stack pointer */
1436	1142	REG_SP_BASE(m68k)[m68k->s_flag \| ((m68k->s_flag>>1) & m68k->m_flag)] = REG_SP(m68k);
r23920	r23921
1442	1148	}
1443	1149
1444	1150	/* Set the S and M flags. Don't touch the stack pointer. */
1445		INLINE void m68ki_set_sm_flag_nosp(m68ki_~~cpu~~_core *m68k, UINT32 value)
	1151	INLINE void m68ki_set_sm_flag_nosp(m68000_base_device *m68k, UINT32 value)
1446	1152	{
1447	1153	/* Set the S and M flags */
1448	1154	m68k->s_flag = value & SFLAG_SET;
r23920	r23921
1451	1157
1452	1158
1453	1159	/* Set the condition code register */
1454		INLINE void m68ki_set_ccr(m68ki_~~cpu~~_core *m68k, UINT32 value)
	1160	INLINE void m68ki_set_ccr(m68000_base_device *m68k, UINT32 value)
1455	1161	{
1456	1162	m68k->x_flag = BIT_4(value) << 4;
1457	1163	m68k->n_flag = BIT_3(value) << 4;
r23920	r23921
1461	1167	}
1462	1168
1463	1169	/* Set the status register but don't check for interrupts */
1464		INLINE void m68ki_set_sr_noint(m68ki_~~cpu~~_core *m68k, UINT32 value)
	1170	INLINE void m68ki_set_sr_noint(m68000_base_device *m68k, UINT32 value)
1465	1171	{
1466	1172	/* Mask out the "unimplemented" bits */
1467	1173	value &= m68k->sr_mask;
r23920	r23921
1477	1183	/* Set the status register but don't check for interrupts nor
1478	1184	* change the stack pointer
1479	1185	*/
1480		INLINE void m68ki_set_sr_noint_nosp(m68ki_~~cpu~~_core *m68k, UINT32 value)
	1186	INLINE void m68ki_set_sr_noint_nosp(m68000_base_device *m68k, UINT32 value)
1481	1187	{
1482	1188	/* Mask out the "unimplemented" bits */
1483	1189	value &= m68k->sr_mask;
r23920	r23921
1491	1197	}
1492	1198
1493	1199	/* Set the status register and check for interrupts */
1494		INLINE void m68ki_set_sr(m68ki_~~cpu~~_core *m68k, UINT32 value)
	1200	INLINE void m68ki_set_sr(m68000_base_device *m68k, UINT32 value)
1495	1201	{
1496	1202	m68ki_set_sr_noint(m68k, value);
1497	1203	m68ki_check_interrupts(m68k);
r23920	r23921
1501	1207	/* ------------------------- Exception Processing ------------------------- */
1502	1208
1503	1209	/* Initiate exception processing */
1504		INLINE UINT32 m68ki_init_exception(m68ki_~~cpu~~_core *m68k)
	1210	INLINE UINT32 m68ki_init_exception(m68000_base_device *m68k)
1505	1211	{
1506	1212	/* Save the old status register */
1507	1213	UINT32 sr = m68ki_get_sr(m68k);
r23920	r23921
1516	1222	}
1517	1223
1518	1224	/* 3 word stack frame (68000 only) */
1519		INLINE void m68ki_stack_frame_3word(m68ki_~~cpu~~_core *m68k, UINT32 pc, UINT32 sr)
	1225	INLINE void m68ki_stack_frame_3word(m68000_base_device *m68k, UINT32 pc, UINT32 sr)
1520	1226	{
1521	1227	m68ki_push_32(m68k, pc);
1522	1228	m68ki_push_16(m68k, sr);
r23920	r23921
1525	1231	/* Format 0 stack frame.
1526	1232	* This is the standard stack frame for 68010+.
1527	1233	*/
1528		INLINE void m68ki_stack_frame_0000(m68ki_~~cpu~~_core *m68k, UINT32 pc, UINT32 sr, UINT32 vector)
	1234	INLINE void m68ki_stack_frame_0000(m68000_base_device *m68k, UINT32 pc, UINT32 sr, UINT32 vector)
1529	1235	{
1530	1236	/* Stack a 3-word frame if we are 68000 */
1531	1237	if(m68k->cpu_type == CPU_TYPE_000 \|\| m68k->cpu_type == CPU_TYPE_008)
r23920	r23921
1541	1247	/* Format 1 stack frame (68020).
1542	1248	* For 68020, this is the 4 word throwaway frame.
1543	1249	*/
1544		INLINE void m68ki_stack_frame_0001(m68ki_~~cpu~~_core *m68k, UINT32 pc, UINT32 sr, UINT32 vector)
	1250	INLINE void m68ki_stack_frame_0001(m68000_base_device *m68k, UINT32 pc, UINT32 sr, UINT32 vector)
1545	1251	{
1546	1252	m68ki_push_16(m68k, 0x1000 \| (vector<<2));
1547	1253	m68ki_push_32(m68k, pc);
r23920	r23921
1551	1257	/* Format 2 stack frame.
1552	1258	* This is used only by 68020 for trap exceptions.
1553	1259	*/
1554		INLINE void m68ki_stack_frame_0010(m68ki_~~cpu~~_core *m68k, UINT32 sr, UINT32 vector)
	1260	INLINE void m68ki_stack_frame_0010(m68000_base_device *m68k, UINT32 sr, UINT32 vector)
1555	1261	{
1556	1262	m68ki_push_32(m68k, REG_PPC(m68k));
1557	1263	m68ki_push_16(m68k, 0x2000 \| (vector<<2));
r23920	r23921
1562	1268
1563	1269	/* Bus error stack frame (68000 only).
1564	1270	*/
1565		INLINE void m68ki_stack_frame_buserr(m68ki_~~cpu~~_core *m68k, UINT32 sr)
	1271	INLINE void m68ki_stack_frame_buserr(m68000_base_device *m68k, UINT32 sr)
1566	1272	{
1567	1273	m68ki_push_32(m68k, REG_PC(m68k));
1568	1274	m68ki_push_16(m68k, sr);
r23920	r23921
1579	1285	/* Format 8 stack frame (68010).
1580	1286	* 68010 only. This is the 29 word bus/address error frame.
1581	1287	*/
1582		INLINE void m68ki_stack_frame_1000(m68ki_~~cpu~~_core *m68k, UINT32 pc, UINT32 sr, UINT32 vector)
	1288	INLINE void m68ki_stack_frame_1000(m68000_base_device *m68k, UINT32 pc, UINT32 sr, UINT32 vector)
1583	1289	{
1584	1290	/* VERSION
1585	1291	* NUMBER
r23920	r23921
1633	1339	* if the error happens at an instruction boundary.
1634	1340	* PC stacked is address of next instruction.
1635	1341	*/
1636		INLINE void m68ki_stack_frame_1010(m68ki_~~cpu~~_core *m68k, UINT32 sr, UINT32 vector, UINT32 pc, UINT32 fault_address)
	1342	INLINE void m68ki_stack_frame_1010(m68000_base_device *m68k, UINT32 sr, UINT32 vector, UINT32 pc, UINT32 fault_address)
1637	1343	{
1638	1344	int orig_rw = m68k->mmu_tmp_buserror_rw; // this gets splatted by the following pushes, so save it now
1639	1345	int orig_fc = m68k->mmu_tmp_buserror_fc;
r23920	r23921
1685	1391	* if the error happens during instruction execution.
1686	1392	* PC stacked is address of instruction in progress.
1687	1393	*/
1688		INLINE void m68ki_stack_frame_1011(m68ki_~~cpu~~_core *m68k, UINT32 sr, UINT32 vector, UINT32 pc, UINT32 fault_address)
	1394	INLINE void m68ki_stack_frame_1011(m68000_base_device *m68k, UINT32 sr, UINT32 vector, UINT32 pc, UINT32 fault_address)
1689	1395	{
1690	1396	int orig_rw = m68k->mmu_tmp_buserror_rw; // this gets splatted by the following pushes, so save it now
1691	1397	int orig_fc = m68k->mmu_tmp_buserror_fc;
r23920	r23921
1759	1465	* This is used by the 68040 for bus fault and mmu trap
1760	1466	* 30 words
1761	1467	*/
1762		INLINE void m68ki_stack_frame_0111(m68ki_~~cpu~~_core *m68k, UINT32 sr, UINT32 vector, UINT32 pc, UINT32 fault_address, bool in_mmu)
	1468	INLINE void m68ki_stack_frame_0111(m68000_base_device *m68k, UINT32 sr, UINT32 vector, UINT32 pc, UINT32 fault_address, bool in_mmu)
1763	1469	{
1764	1470	int orig_rw = m68k->mmu_tmp_buserror_rw; // this gets splatted by the following pushes, so save it now
1765	1471	int orig_fc = m68k->mmu_tmp_buserror_fc;
r23920	r23921
1802	1508	/* Used for Group 2 exceptions.
1803	1509	* These stack a type 2 frame on the 020.
1804	1510	*/
1805		INLINE void m68ki_exception_trap(m68ki_~~cpu~~_core *m68k, UINT32 vector)
	1511	INLINE void m68ki_exception_trap(m68000_base_device *m68k, UINT32 vector)
1806	1512	{
1807	1513	UINT32 sr = m68ki_init_exception(m68k);
1808	1514
r23920	r23921
1818	1524	}
1819	1525
1820	1526	/* Trap#n stacks a 0 frame but behaves like group2 otherwise */
1821		INLINE void m68ki_exception_trapN(m68ki_~~cpu~~_core *m68k, UINT32 vector)
	1527	INLINE void m68ki_exception_trapN(m68000_base_device *m68k, UINT32 vector)
1822	1528	{
1823	1529	UINT32 sr = m68ki_init_exception(m68k);
1824	1530	m68ki_stack_frame_0000(m68k, REG_PC(m68k), sr, vector);
r23920	r23921
1829	1535	}
1830	1536
1831	1537	/* Exception for trace mode */
1832		INLINE void m68ki_exception_trace(m68ki_~~cpu~~_core *m68k)
	1538	INLINE void m68ki_exception_trace(m68000_base_device *m68k)
1833	1539	{
1834	1540	UINT32 sr = m68ki_init_exception(m68k);
1835	1541
r23920	r23921
1854	1560	}
1855	1561
1856	1562	/* Exception for privilege violation */
1857		INLINE void m68ki_exception_privilege_violation(m68ki_~~cpu~~_core *m68k)
	1563	INLINE void m68ki_exception_privilege_violation(m68000_base_device *m68k)
1858	1564	{
1859	1565	UINT32 sr = m68ki_init_exception(m68k);
1860	1566
r23920	r23921
1871	1577	}
1872	1578
1873	1579	/* Exception for A-Line instructions */
1874		INLINE void m68ki_exception_1010(m68ki_~~cpu~~_core *m68k)
	1580	INLINE void m68ki_exception_1010(m68000_base_device *m68k)
1875	1581	{
1876	1582	UINT32 sr;
1877	1583
r23920	r23921
1884	1590	}
1885	1591
1886	1592	/* Exception for F-Line instructions */
1887		INLINE void m68ki_exception_1111(m68ki_~~cpu~~_core *m68k)
	1593	INLINE void m68ki_exception_1111(m68000_base_device *m68k)
1888	1594	{
1889	1595	UINT32 sr;
1890	1596
r23920	r23921
1897	1603	}
1898	1604
1899	1605	/* Exception for illegal instructions */
1900		INLINE void m68ki_exception_illegal(m68ki_~~cpu~~_core *m68k)
	1606	INLINE void m68ki_exception_illegal(m68000_base_device *m68k)
1901	1607	{
1902	1608	UINT32 sr;
1903	1609
r23920	r23921
1916	1622	}
1917	1623
1918	1624	/* Exception for format errror in RTE */
1919		INLINE void m68ki_exception_format_error(m68ki_~~cpu~~_core *m68k)
	1625	INLINE void m68ki_exception_format_error(m68000_base_device *m68k)
1920	1626	{
1921	1627	UINT32 sr = m68ki_init_exception(m68k);
1922	1628	m68ki_stack_frame_0000(m68k, REG_PC(m68k), sr, EXCEPTION_FORMAT_ERROR);
r23920	r23921
1927	1633	}
1928	1634
1929	1635	/* Exception for address error */
1930		INLINE void m68ki_exception_address_error(m68ki_~~cpu~~_core *m68k)
	1636	INLINE void m68ki_exception_address_error(m68000_base_device *m68k)
1931	1637	{
1932	1638	UINT32 sr = m68ki_init_exception(m68k);
1933	1639
r23920	r23921
1937	1643	*/
1938	1644	if(m68k->run_mode == RUN_MODE_BERR_AERR_RESET)
1939	1645	{
1940		m68k->memory.read8(0x00ffff01);
	1646	m68k->/memory./read8(0x00ffff01);
1941	1647	m68k->stopped = STOP_LEVEL_HALT;
1942	1648	return;
1943	1649	}
r23920	r23921
1953	1659	}
1954	1660
1955	1661
1956		/* Service an interrupt request and start exception processing */
1957		INLINE void m68ki_exception_interrupt(m68ki_cpu_core *m68k, UINT32 int_level)
1958		{
1959		UINT32 vector;
1960		UINT32 sr;
1961		UINT32 new_pc;
1962	1662
1963		if(CPU_TYPE_IS_000(m68k->cpu_type))
1964		{
1965		m68k->instr_mode = INSTRUCTION_NO;
1966		}
1967
1968		/* Turn off the stopped state */
1969		m68k->stopped &= ~STOP_LEVEL_STOP;
1970
1971		/* If we are halted, don't do anything */
1972		if(m68k->stopped)
1973		return;
1974
1975		/* Acknowledge the interrupt */
1976		vector = (*m68k->int_ack_callback)(m68k->device, int_level);
1977
1978		/* Get the interrupt vector */
1979		if(vector == M68K_INT_ACK_AUTOVECTOR)
1980		/* Use the autovectors. This is the most commonly used implementation */
1981		vector = EXCEPTION_INTERRUPT_AUTOVECTOR+int_level;
1982		else if(vector == M68K_INT_ACK_SPURIOUS)
1983		/* Called if no devices respond to the interrupt acknowledge */
1984		vector = EXCEPTION_SPURIOUS_INTERRUPT;
1985		else if(vector > 255)
1986		return;
1987
1988		/* Start exception processing */
1989		sr = m68ki_init_exception(m68k);
1990
1991		/* Set the interrupt mask to the level of the one being serviced */
1992		m68k->int_mask = int_level<<8;
1993
1994		/* Get the new PC */
1995		new_pc = m68ki_read_data_32(m68k, (vector<<2) + m68k->vbr);
1996
1997		/* If vector is uninitialized, call the uninitialized interrupt vector */
1998		if(new_pc == 0)
1999		new_pc = m68ki_read_data_32(m68k, (EXCEPTION_UNINITIALIZED_INTERRUPT<<2) + m68k->vbr);
2000
2001		/* Generate a stack frame */
2002		m68ki_stack_frame_0000(m68k, REG_PC(m68k), sr, vector);
2003		if(m68k->m_flag && CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type))
2004		{
2005		/* Create throwaway frame */
2006		m68ki_set_sm_flag(m68k, m68k->s_flag); /* clear M */
2007		sr \|= 0x2000; /* Same as SR in master stack frame except S is forced high */
2008		m68ki_stack_frame_0001(m68k, REG_PC(m68k), sr, vector);
2009		}
2010
2011		m68ki_jump(m68k, new_pc);
2012
2013		/* Defer cycle counting until later */
2014		m68k->remaining_cycles -= m68k->cyc_exception[vector];
2015		}
2016
2017
2018	1663	/* ASG: Check for interrupts */
2019		INLINE void m68ki_check_interrupts(m68ki_~~cpu~~_core *m68k)
	1664	INLINE void m68ki_check_interrupts(m68000_base_device *m68k)
2020	1665	{
2021	1666	if(m68k->nmi_pending)
2022	1667	{
2023	1668	m68k->nmi_pending = FALSE;
2024		m68ki_exception_interrupt(m68k, 7);
	1669	m68k->m68ki_exception_interrupt(m68k, 7);
2025	1670	}
2026	1671	else if(m68k->int_level > m68k->int_mask)
2027		m68ki_exception_interrupt(m68k, m68k->int_level>>8);
	1672	m68k->m68ki_exception_interrupt(m68k, m68k->int_level>>8);
2028	1673	}
2029	1674
2030	1675

trunk/src/emu/cpu/m68000/68340sim.h
r23920	r23921
41	41
42	42
43	43
44		DECLARE_READ16_HANDLER( m68340_internal_sim_r );
45		DECLARE_WRITE16_HANDLER( m68340_internal_sim_w );
46		DECLARE_READ32_HANDLER( m68340_internal_sim_cs_r );
47		DECLARE_WRITE32_HANDLER( m68340_internal_sim_cs_w );
48		DECLARE_READ8_HANDLER( m68340_internal_sim_ports_r );
49		DECLARE_WRITE8_HANDLER( m68340_internal_sim_ports_w );
50	44
51	45
52	46
53
54	47	class m68340_sim
55	48	{
56	49	public:

trunk/src/emu/cpu/m68000/68340ser.h
r23920	r23921
1	1
2		DECLARE_READ32_HANDLER( m68340_internal_serial_r );
3		DECLARE_WRITE32_HANDLER( m68340_internal_serial_w );
4
5	2	class m68340_serial
6	3	{
7	4	public:

trunk/src/emu/cpu/m68000/68307sim.h
r23920	r23921
1	1	/* 68307 SIM module */
2	2
3		DECLARE_READ16_HANDLER( m68307_internal_sim_r );
4		DECLARE_WRITE16_HANDLER( m68307_internal_sim_w );
	3	#include "m68000.h"
5	4
	5	class m68000_base_device;
	6
	7
6	8	/* ports */
7	9	#define m68307SIM_PACNT (0x10)
8	10	#define m68307SIM_PADDR (0x12)
r23920	r23921
51	53
52	54	void write_pacnt(UINT16 data, UINT16 mem_mask);
53	55	void write_paddr(UINT16 data, UINT16 mem_mask);
54		UINT16 read_padat(address_space &space, UINT16 mem_mask);
55		void write_padat(address_space &space, UINT16 data, UINT16 mem_mask);
	56	UINT16 read_padat(m68000_base_device* m68k, address_space &space, UINT16 mem_mask);
	57	void write_padat(m68000_base_device* m68k, address_space &space, UINT16 data, UINT16 mem_mask);
56	58
57	59	void write_pbcnt(UINT16 data, UINT16 mem_mask);
58	60	void write_pbddr(UINT16 data, UINT16 mem_mask);
59		UINT16 read_pbdat(address_space &space, UINT16 mem_mask);
60		void write_pbdat(address_space &space, UINT16 data, UINT16 mem_mask);
	61	UINT16 read_pbdat(m68000_base_device* m68k, address_space &space, UINT16 mem_mask);
	62	void write_pbdat(m68000_base_device* m68k, address_space &space, UINT16 data, UINT16 mem_mask);
61	63
62	64
63	65

trunk/src/emu/cpu/m68000/68307ser.h
r23920	r23921
	1	#include "m68000.h"
1	2	#include "machine/68681.h"
2	3
3	4	#define m68307SER_UMR1_UMR2 (0x01)
r23920	r23921
17	18	#define m68307SER_UOP1 (0x1d)
18	19	#define m68307SER_UOP0 (0x1f)
19	20
20
21		DECLARE_READ8_HANDLER( m68307_internal_serial_r );
22		DECLARE_WRITE8_HANDLER( m68307_internal_serial_w );
23
24	21	class m68307_serial
25	22	{
26	23	public:

trunk/src/emu/cpu/m68000/68307bus.h
r23920	r23921
	1	#include "m68000.h"
	2
1	3	#define m68307BUS_MADR (0x01)
2	4	#define m68307BUS_MFDR (0x03)
3	5	#define m68307BUS_MBCR (0x05)
r23920	r23921
4	6	#define m68307BUS_MBSR (0x07)
5	7	#define m68307BUS_MBDR (0x09)
6	8
7		DECLARE_READ8_HANDLER( m68307_internal_mbus_r );
8		DECLARE_WRITE8_HANDLER( m68307_internal_mbus_w );
9	9
10	10	class m68307_mbus
11	11	{

trunk/src/emu/cpu/m68000/68340dma.c
r23920	r23921
4	4	#include "m68kcpu.h"
5	5
6	6
7		READ32_~~HANDL~~ER( m68340_internal_dma_r )
	7	READ32_MEMBER( m68000_base_device::m68340_internal_dma_r )
8	8	{
9		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	9	m68000_base_device *m68k = this;
10	10	m68340_dma* dma = m68k->m68340DMA;
11	11	assert(dma != NULL);
12	12
r23920	r23921
19	19	return 0x00000000;
20	20	}
21	21
22		WRITE32_~~HANDL~~ER( m68340_internal_dma_w )
	22	WRITE32_MEMBER( m68000_base_device::m68340_internal_dma_w )
23	23	{
24		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	24	m68000_base_device *m68k = this;
25	25	m68340_dma* dma = m68k->m68340DMA;
26	26	assert(dma != NULL);
27	27

trunk/src/emu/cpu/m68000/m68kmmu.h
r23920	r23921
47	47	#define M68K_MMU_TC_SRE 0x02000000
48	48
49	49	/* decodes the effective address */
50		static UINT32 DECODE_EA_32(m68ki_~~cpu~~_core *m68k, int ea)
	50	static UINT32 DECODE_EA_32(m68000_base_device *m68k, int ea)
51	51	{
52	52	int mode = (ea >> 3) & 0x7;
53	53	int reg = (ea & 0x7);
r23920	r23921
106	106	/*
107	107	pmmu_atc_add: adds this address to the ATC
108	108	*/
109		void pmmu_atc_add(m68ki_~~cpu~~_core *m68k, UINT32 logical, UINT32 physical, int fc)
	109	void pmmu_atc_add(m68000_base_device *m68k, UINT32 logical, UINT32 physical, int fc)
110	110	{
111	111	int i, found;
112	112
r23920	r23921
163	163
164	164	7fff0003 001ffd10 80f05750 is what should load
165	165	*/
166		void pmmu_atc_flush(m68ki_~~cpu~~_core *m68k)
	166	void pmmu_atc_flush(m68000_base_device *m68k)
167	167	{
168	168	int i;
169	169	// printf("ATC flush: pc=%08x\n", REG_PPC(m68k));
r23920	r23921
177	177	}
178	178
179	179
180		INLINE UINT32 get_dt2_table_entry(m68ki_~~cpu~~_core *m68k, UINT32 tptr, UINT8 ptest)
	180	INLINE UINT32 get_dt2_table_entry(m68000_base_device *m68k, UINT32 tptr, UINT8 ptest)
181	181	{
182	182	UINT32 tbl_entry = m68k->program->read_dword(tptr);
183	183	UINT32 dt = tbl_entry & M68K_MMU_DF_DT;
r23920	r23921
199	199	return tbl_entry;
200	200	}
201	201
202		INLINE UINT32 get_dt3_table_entry(m68ki_~~cpu~~_core *m68k, UINT32 tptr, UINT8 fc, UINT8 ptest)
	202	INLINE UINT32 get_dt3_table_entry(m68000_base_device *m68k, UINT32 tptr, UINT8 fc, UINT8 ptest)
203	203	{
204	204	UINT32 tbl_entry2 = m68k->program->read_dword(tptr);
205	205	UINT32 tbl_entry = m68k->program->read_dword(tptr + 4);
r23920	r23921
227	227	/*
228	228	pmmu_translate_addr_with_fc: perform 68851/68030-style PMMU address translation
229	229	*/
230		/INLINE/ static UINT32 pmmu_translate_addr_with_fc(m68ki_~~cpu~~_core *m68k, UINT32 addr_in, UINT8 fc, UINT8 ptest)
	230	/INLINE/ static UINT32 pmmu_translate_addr_with_fc(m68000_base_device *m68k, UINT32 addr_in, UINT8 fc, UINT8 ptest)
231	231	{
232	232	UINT32 addr_out, tbl_entry = 0, tamode = 0, tbmode = 0, tcmode = 0;
233	233	UINT32 root_aptr, root_limit, tofs, ps, is, abits, bbits, cbits;
r23920	r23921
526	526
527	527	// FC bits: 2 = supervisor, 1 = program, 0 = data
528	528	// the 68040 is a subset of the 68851 and 68030 PMMUs - the page table sizes are fixed, there is no early termination, etc, etc.
529		/INLINE/ static UINT32 pmmu_translate_addr_with_fc_040(m68ki_~~cpu~~_core *m68k, UINT32 addr_in, UINT8 fc, UINT8 ptest)
	529	/INLINE/ static UINT32 pmmu_translate_addr_with_fc_040(m68000_base_device *m68k, UINT32 addr_in, UINT8 fc, UINT8 ptest)
530	530	{
531	531	UINT32 addr_out, tt0, tt1;
532	532
r23920	r23921
761	761	/*
762	762	pmmu_translate_addr: perform 68851/68030-style PMMU address translation
763	763	*/
764		/INLINE/ static UINT32 pmmu_translate_addr(m68ki_~~cpu~~_core *m68k, UINT32 addr_in)
	764	/INLINE/ static UINT32 pmmu_translate_addr(m68000_base_device *m68k, UINT32 addr_in)
765	765	{
766	766	UINT32 addr_out;
767	767
r23920	r23921
787	787	m68851_mmu_ops: COP 0 MMU opcode handling
788	788	*/
789	789
790		void m68881_mmu_ops(m68ki_~~cpu~~_core *m68k)
	790	void m68881_mmu_ops(m68000_base_device *m68k)
791	791	{
792	792	UINT16 modes;
793	793	UINT32 ea = m68k->ir & 0x3f;
r23920	r23921
1063	1063
1064	1064
1065	1065	/* Apple HMMU translation is much simpler */
1066		INLINE UINT32 hmmu_translate_addr(m68ki_~~cpu~~_core *m68k, UINT32 addr_in)
	1066	INLINE UINT32 hmmu_translate_addr(m68000_base_device *m68k, UINT32 addr_in)
1067	1067	{
1068	1068	UINT32 addr_out;
1069	1069

trunk/src/emu/cpu/m68000/68340tmu.c
r23920	r23921
5	5
6	6
7	7
8		READ32_~~HANDL~~ER( m68340_internal_timer_r )
	8	READ32_MEMBER( m68000_base_device::m68340_internal_timer_r )
9	9	{
10		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	10	m68000_base_device *m68k = this;
11	11	m68340_timer* timer = m68k->m68340TIMER;
12	12	assert(timer != NULL);
13	13
r23920	r23921
20	20	return 0x00000000;
21	21	}
22	22
23		WRITE32_~~HANDL~~ER( m68340_internal_timer_w )
	23	WRITE32_MEMBER( m68000_base_device::m68340_internal_timer_w )
24	24	{
25		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	25	m68000_base_device *m68k = this;
26	26	m68340_timer* timer = m68k->m68340TIMER;
27	27	assert(timer != NULL);
28	28

trunk/src/emu/cpu/m68000/68340dma.h
r23920	r23921
1	1
2		DECLARE_READ32_HANDLER( m68340_internal_dma_r );
3		DECLARE_WRITE32_HANDLER( m68340_internal_dma_w );
4
5	2	class m68340_dma
6	3	{
7	4	public:

trunk/src/emu/cpu/m68000/m68k_in.c
r23920	r23921
102	102	/* Build the opcode handler table */
103	103	void m68ki_build_opcode_table(void);
104	104
105		extern void (m68ki_instruction_jump_table[][0x10000])(m68ki_~~cpu~~_core m68k); /* opcode handler jump table */
	105	extern void (m68ki_instruction_jump_table[][0x10000])(m68000_base_device m68k); /* opcode handler jump table */
106	106	extern unsigned char m68ki_cycles[][0x10000];
107	107
108	108
r23920	r23921
124	124
125	125	#define NUM_CPU_TYPES 7
126	126
127		void (m68ki_instruction_jump_table[NUM_CPU_TYPES][0x10000])(m68ki_~~cpu~~_core m68k); /* opcode handler jump table */
	127	void (m68ki_instruction_jump_table[NUM_CPU_TYPES][0x10000])(m68000_base_device m68k); /* opcode handler jump table */
128	128	unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
129	129
130	130	/* This is used to generate the opcode handler jump table */
131	131	struct opcode_handler_struct
132	132	{
133		void (opcode_handler)(m68ki_~~cpu~~_core m68k); /* handler function */
	133	void (opcode_handler)(m68000_base_device m68k); /* handler function */
134	134	unsigned int mask; /* mask on opcode */
135	135	unsigned int match; /* what to match after masking */
136	136	unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
r23920	r23921
174	174	/* default to illegal */
175	175	for(k=0;k<NUM_CPU_TYPES;k++)
176	176	{
177		m68ki_instruction_jump_table[k][i] = _m68ki_~~cpu~~_core::m68k_op_illegal;
	177	m68ki_instruction_jump_table[k][i] = m68000_base_device_ops::m68k_op_illegal;
178	178	m68ki_cycles[k][i] = 0;
179	179	}
180	180	}
r23920	r23921
269	269
270	270	#include "emu.h"
271	271	#include "m68kcpu.h"
272		extern void m68040_fpu_op0(m68ki_cpu_core *m68k);
273		extern void m68040_fpu_op1(m68ki_cpu_core *m68k);
274		extern void m68881_mmu_ops(m68ki_cpu_core *m68k);
	272	extern void m68040_fpu_op0(m68000_base_device *m68k);
	273	extern void m68040_fpu_op1(m68000_base_device *m68k);
	274	extern void m68881_mmu_ops(m68000_base_device *m68k);
275	275
276	276	/* ======================================================================== */
277	277	/* ========================= INSTRUCTION HANDLERS ========================= */
r23920	r23921
3159	3159	if(CPU_TYPE_IS_010_PLUS((mc68kcpu)->cpu_type))
3160	3160	{
3161	3161	if ((mc68kcpu)->bkpt_ack_callback != NULL)
3162		(*(mc68kcpu)->bkpt_ack_callback)((mc68kcpu)~~->device~~, CPU_TYPE_IS_EC020_PLUS((mc68kcpu)->cpu_type) ? (mc68kcpu)->ir & 7 : 0);
	3162	(*(mc68kcpu)->bkpt_ack_callback)((mc68kcpu), CPU_TYPE_IS_EC020_PLUS((mc68kcpu)->cpu_type) ? (mc68kcpu)->ir & 7 : 0);
3163	3163	}
3164	3164	m68ki_exception_illegal(mc68kcpu);
3165	3165	}
r23920	r23921
3324	3324	REG_PC(mc68kcpu) += 2;
3325	3325	(void)ea; /* just to avoid an 'unused variable' warning */
3326	3326	logerror("%s at %08x: called unimplemented instruction %04x (callm)\n",
3327		(mc68kcpu)->~~device->~~tag(), REG_PC(mc68kcpu) - 2, (mc68kcpu)->ir);
	3327	(mc68kcpu)->tag(), REG_PC(mc68kcpu) - 2, (mc68kcpu)->ir);
3328	3328	return;
3329	3329	}
3330	3330	m68ki_exception_illegal(mc68kcpu);
r23920	r23921
4261	4261	UINT32 res = dst - src;
4262	4262
4263	4263	if ((mc68kcpu)->cmpild_instr_callback != NULL)
4264		(*(mc68kcpu)->cmpild_instr_callback)((mc68kcpu)~~->device~~, src, (mc68kcpu)->ir & 7);
	4264	(*(mc68kcpu)->cmpild_instr_callback)((mc68kcpu), src, (mc68kcpu)->ir & 7);
4265	4265
4266	4266	(mc68kcpu)->n_flag = NFLAG_32(res);
4267	4267	(mc68kcpu)->not_z_flag = MASK_OUT_ABOVE_32(res);
r23920	r23921
4402	4402	if(CPU_TYPE_IS_EC020_PLUS((mc68kcpu)->cpu_type))
4403	4403	{
4404	4404	logerror("%s at %08x: called unimplemented instruction %04x (cpbcc)\n",
4405		(mc68kcpu)->~~device->~~tag(), REG_PC(mc68kcpu) - 2, (mc68kcpu)->ir);
	4405	(mc68kcpu)->tag(), REG_PC(mc68kcpu) - 2, (mc68kcpu)->ir);
4406	4406	return;
4407	4407	}
4408	4408	m68ki_exception_1111(mc68kcpu);
r23920	r23921
4414	4414	if(CPU_TYPE_IS_EC020_PLUS((mc68kcpu)->cpu_type))
4415	4415	{
4416	4416	logerror("%s at %08x: called unimplemented instruction %04x (cpdbcc)\n",
4417		(mc68kcpu)->~~device->~~tag(), REG_PC(mc68kcpu) - 2, (mc68kcpu)->ir);
	4417	(mc68kcpu)->tag(), REG_PC(mc68kcpu) - 2, (mc68kcpu)->ir);
4418	4418	return;
4419	4419	}
4420	4420	m68ki_exception_1111(mc68kcpu);
r23920	r23921
4426	4426	if(CPU_TYPE_IS_EC020_PLUS((mc68kcpu)->cpu_type) && (mc68kcpu->has_fpu \|\| mc68kcpu->has_pmmu))
4427	4427	{
4428	4428	logerror("%s at %08x: called unimplemented instruction %04x (cpgen)\n",
4429		(mc68kcpu)->~~device->~~tag(), REG_PC(mc68kcpu) - 2, (mc68kcpu)->ir);
	4429	(mc68kcpu)->tag(), REG_PC(mc68kcpu) - 2, (mc68kcpu)->ir);
4430	4430	return;
4431	4431	}
4432	4432	m68ki_exception_1111(mc68kcpu);
r23920	r23921
4438	4438	if(CPU_TYPE_IS_EC020_PLUS((mc68kcpu)->cpu_type))
4439	4439	{
4440	4440	logerror("%s at %08x: called unimplemented instruction %04x (cpscc)\n",
4441		(mc68kcpu)->~~device->~~tag(), REG_PC(mc68kcpu) - 2, (mc68kcpu)->ir);
	4441	(mc68kcpu)->tag(), REG_PC(mc68kcpu) - 2, (mc68kcpu)->ir);
4442	4442	return;
4443	4443	}
4444	4444	m68ki_exception_1111(mc68kcpu);
r23920	r23921
4450	4450	if(CPU_TYPE_IS_EC020_PLUS((mc68kcpu)->cpu_type))
4451	4451	{
4452	4452	logerror("%s at %08x: called unimplemented instruction %04x (cptrapcc)\n",
4453		(mc68kcpu)->~~device->~~tag(), REG_PC(mc68kcpu) - 2, (mc68kcpu)->ir);
	4453	(mc68kcpu)->tag(), REG_PC(mc68kcpu) - 2, (mc68kcpu)->ir);
4454	4454	return;
4455	4455	}
4456	4456	m68ki_exception_1111(mc68kcpu);
r23920	r23921
8262	8262	if((mc68kcpu)->s_flag)
8263	8263	{
8264	8264	if ((mc68kcpu)->reset_instr_callback != NULL)
8265		(*(mc68kcpu)->reset_instr_callback)((mc68kcpu)~~->device~~);
	8265	(*(mc68kcpu)->reset_instr_callback)((mc68kcpu));
8266	8266	(mc68kcpu)->remaining_cycles -= (mc68kcpu)->cyc_reset;
8267	8267	return;
8268	8268	}
r23920	r23921
8968	8968	UINT32 format_word;
8969	8969
8970	8970	if ((mc68kcpu)->rte_instr_callback != NULL)
8971		(*(mc68kcpu)->rte_instr_callback)((mc68kcpu)~~->device~~);
	8971	(*(mc68kcpu)->rte_instr_callback)((mc68kcpu));
8972	8972	m68ki_trace_t0(mc68kcpu); /* auto-disable (see m68kcpu.h) */
8973	8973
8974	8974	if(CPU_TYPE_IS_000((mc68kcpu)->cpu_type))
r23920	r23921
9129	9129	{
9130	9130	m68ki_trace_t0(mc68kcpu); /* auto-disable (see m68kcpu.h) */
9131	9131	logerror("%s at %08x: called unimplemented instruction %04x (rtm)\n",
9132		(mc68kcpu)->~~device->~~tag(), REG_PC(mc68kcpu) - 2, (mc68kcpu)->ir);
	9132	(mc68kcpu)->tag(), REG_PC(mc68kcpu) - 2, (mc68kcpu)->ir);
9133	9133	return;
9134	9134	}
9135	9135	m68ki_exception_illegal(mc68kcpu);
r23920	r23921
10003	10003
10004	10004	/* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
10005	10005	disabled in order to function properly. Some Amiga software may also rely
10006		on ~~(mc68kcpu)~~, but only when accessing specific addresses so additional functionality
	10006	on this, but only when accessing specific addresses so additional functionality
10007	10007	will be needed. */
10008	10008	if ((mc68kcpu)->tas_instr_callback != NULL)
10009		allow_writeback = (*(mc68kcpu)->tas_instr_callback)((mc68kcpu)~~->device~~);
	10009	allow_writeback = (*(mc68kcpu)->tas_instr_callback)((mc68kcpu));
10010	10010
10011	10011	if (allow_writeback)
10012	10012	m68ki_write_8((mc68kcpu), ea, dst \| 0x80);
r23920	r23921
10511	10511	if(CPU_TYPE_IS_040_PLUS((mc68kcpu)->cpu_type))
10512	10512	{
10513	10513	logerror("%s at %08x: called unimplemented instruction %04x (cpush)\n",
10514		(mc68kcpu)->~~device->~~tag(), REG_PC(mc68kcpu) - 2, (mc68kcpu)->ir);
	10514	(mc68kcpu)->tag(), REG_PC(mc68kcpu) - 2, (mc68kcpu)->ir);
10515	10515	return;
10516	10516	}
10517	10517	m68ki_exception_1111(mc68kcpu);

trunk/src/emu/cpu/m68000/68307tmu.c
r23920	r23921
4	4	#include "emu.h"
5	5	#include "m68kcpu.h"
6	6
7		READ16_~~HANDL~~ER( m68307_internal_timer_r )
	7	READ16_MEMBER( m68000_base_device::m68307_internal_timer_r )
8	8	{
9		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	9	m68000_base_device *m68k = this;
10	10	m68307_timer* timer = m68k->m68307TIMER;
11	11	assert(timer != NULL);
12	12
r23920	r23921
32	32	return 0x0000;
33	33	}
34	34
35		WRITE16_~~HANDL~~ER( m68307_internal_timer_w )
	35	WRITE16_MEMBER( m68000_base_device::m68307_internal_timer_w )
36	36	{
37		m68ki_~~cpu~~_core *m68k = ~~m68k_ge~~t~~_safe_token(&space.dev~~i~~ce())~~;
	37	m68000_base_device *m68k = this;
38	38	m68307_timer* timer = m68k->m68307TIMER;
39	39	assert(timer != NULL);
40	40
r23920	r23921
101	101
102	102	static TIMER_CALLBACK( m68307_timer0_callback )
103	103	{
104		legacy_cpu_device dev = (legacy_cpu_device )ptr;
105		m68ki_cpu_core* m68k = m68k_get_safe_token(dev);
	104	m68000_base_device* m68k = (m68000_base_device *)ptr;
106	105	m68307_single_timer* tptr = &m68k->m68307TIMER->singletimer[0];
107	106	tptr->regs[m68307TIMER_TMR] \|= 0x2;
108	107
109		m68307_timer0_interrupt(~~dev~~);
	108	m68307_timer0_interrupt(m68k);
110	109
111		tptr->mametimer->adjust(m68k->~~device->~~cycles_to_attotime(20000));
	110	tptr->mametimer->adjust(m68k->cycles_to_attotime(20000));
112	111	}
113	112
114	113	static TIMER_CALLBACK( m68307_timer1_callback )
115	114	{
116		legacy_cpu_device dev = (legacy_cpu_device )ptr;
117		m68ki_cpu_core* m68k = m68k_get_safe_token(dev);
	115	m68000_base_device* m68k = (m68000_base_device *)ptr;
118	116	m68307_single_timer* tptr = &m68k->m68307TIMER->singletimer[1];
119	117	tptr->regs[m68307TIMER_TMR] \|= 0x2;
120	118
121		m68307_timer1_interrupt(~~dev~~);
	119	m68307_timer1_interrupt(m68k);
122	120
123		tptr->mametimer->adjust(m68k->~~device->~~cycles_to_attotime(20000));
	121	tptr->mametimer->adjust(m68k->cycles_to_attotime(20000));
124	122
125	123	}
126	124
r23920	r23921
129	127	printf("wd timer\n");
130	128	}
131	129
132		void m68307_timer::init(~~legacy~~_~~cpu~~_device *device)
	130	void m68307_timer::init(m68000_base_device *device)
133	131	{
	132	parent = device;
	133
134	134	m68307_single_timer* tptr;
135	135
136	136	tptr = &singletimer[0];
137		tptr->mametimer = device->machine().scheduler().timer_alloc(FUNC(m68307_timer0_callback), de~~vice~~);
	137	tptr->mametimer = device->machine().scheduler().timer_alloc(FUNC(m68307_timer0_callback), parent);
138	138
139	139	tptr = &singletimer[1];
140		tptr->mametimer = device->machine().scheduler().timer_alloc(FUNC(m68307_timer1_callback), de~~vice~~);
	140	tptr->mametimer = device->machine().scheduler().timer_alloc(FUNC(m68307_timer1_callback), parent);
141	141
142		parent = device;
143	142
144		wd_mametimer = device->machine().scheduler().timer_alloc(FUNC(m68307_wd_timer_callback), de~~vice~~);
	143	wd_mametimer = device->machine().scheduler().timer_alloc(FUNC(m68307_wd_timer_callback), parent);
145	144
146	145
147	146	}
r23920	r23921
162	161
163	162	void m68307_timer::write_tmr(UINT16 data, UINT16 mem_mask, int which)
164	163	{
165		m68ki_~~cpu~~_core* m68k = ~~m68k_get_safe_token(~~parent);
	164	m68000_base_device* m68k = parent;
166	165	m68307_single_timer* tptr = &singletimer[which];
167	166
168	167	COMBINE_DATA(&tptr->regs[m68307TIMER_TMR]);
r23920	r23921
204	203	if (rst==0x0) logerror("(timer is reset)\n");
205	204	if (rst==0x1) logerror("(timer is running)\n");
206	205
207		tptr->mametimer->adjust(m68k->~~device->~~cycles_to_attotime(100000));
	206	tptr->mametimer->adjust(m68k->cycles_to_attotime(100000));
208	207
209	208	logerror("\n");
210	209

trunk/src/emu/cpu/m68000/68340tmu.h
r23920	r23921
1	1
2		DECLARE_READ32_HANDLER( m68340_internal_timer_r );
3		DECLARE_WRITE32_HANDLER( m68340_internal_timer_w );
4	2
5	3	class m68340_timer
6	4	{

trunk/src/emu/cpu/m68000/68307tmu.h
r23920	r23921
1	1
2		DECLARE_READ16_HANDLER( m68307_internal_timer_r );
3		DECLARE_WRITE16_HANDLER( m68307_internal_timer_w );
	2	#include "m68000.h"
4	3
	4	class m68000_base_device;
	5
	6
5	7	#define m68307TIMER_TMR (0x0)
6	8	#define m68307TIMER_TRR (0x1)
7	9	#define m68307TIMER_TCR (0x2)
r23920	r23921
25	27	m68307_single_timer singletimer[2];
26	28
27	29	emu_timer *wd_mametimer;
28		~~legacy~~_~~cpu~~_device *parent;
	30	m68000_base_device *parent;
29	31
30	32	void write_tmr(UINT16 data, UINT16 mem_mask, int which);
31	33	void write_trr(UINT16 data, UINT16 mem_mask, int which);
32	34	void write_ter(UINT16 data, UINT16 mem_mask, int which);
33	35	UINT16 read_tcn(UINT16 mem_mask, int which);
34	36
35		void init(~~legacy~~_~~cpu~~_device *device);
	37	void init(m68000_base_device *device);
36	38	void reset(void);
37	39	};

trunk/src/emu/cpu/m68000/m68kmake.c
r23920	r23921
790	790	/* Write the name of an opcode handler function */
791	791	static void write_function_name(FILE* filep, char* base_name)
792	792	{
793		fprintf(filep, "void _m68ki_cpu_core::%s(_m68ki_cpu_core* mc68kcpu)\n", base_name);
794		fprintf(g_prototype_file, "static void %s(_m68ki_cpu_core* mc68kcpu);\n", base_name);
	793	fprintf(filep, "void m68000_base_device_ops::%s(m68000_base_device* mc68kcpu)\n", base_name);
	794	fprintf(g_prototype_file, "static void %s(m68000_base_device* mc68kcpu);\n", base_name);
795	795	}
796	796
797	797	static void add_opcode_output_table_entry(opcode_struct* op, char* name)
r23920	r23921
804	804
805	805	ptr = op;
806	806
807		sprintf( ptr->name, "_m68ki_~~cpu~~_core::%s", name);
	807	sprintf( ptr->name, "m68000_base_device_ops::%s", name);
808	808	ptr->bits = num_bits(ptr->op_mask);
809	809	}
810	810

trunk/src/mess/drivers/apollo.c
r23920	r23921
141	141	apollo_set_cpu_has_fpu - enable/disable the FPU
142	142	-------------------------------------------------*/
143	143
144		void apollo_set_cpu_has_fpu(device_t *device, int onoff)
	144	void apollo_set_cpu_has_fpu(m68000_base_device *device, int onoff)
145	145	{
146	146	if (device == NULL \|\| (device->type() != M68020PMMU && device->type() != M68030))
147	147	{
r23920	r23921
149	149	}
150	150	else
151	151	{
152		m68ki_cpu_core cpu = (m68ki_cpu_core ) downcast<legacy_cpu_device *> (device)->token();
153		cpu->has_fpu = onoff;
	152
	153	device->has_fpu = onoff;
154	154	DLOG1(("apollo_set_cpu_has_fpu: FPU has been %s", onoff ? "enabled" : "disabled"));
155	155	}
156	156	}
r23920	r23921
216	216	apollo_instruction_hook
217	217	must be called by the CPU core before executing each instruction
218	218	***************************************************************************/
219		int apollo_instruction_hook(device_t *device, offs_t curpc)
	219	int apollo_instruction_hook(m68000_base_device *device, offs_t curpc)
220	220	{
221		m68ki_cpu_core m68k = (m68ki_cpu_core ) downcast<legacy_cpu_device *> (device)->token();
	221	m68000_base_device *m68k = device;
	222	//m68000_base_device m68k = (m68000_base_device ) downcast<legacy_cpu_device *> (device)->token();
222	223
223	224	static UINT16 idle_counter = 0;
224	225
r23920	r23921
512	513	{
513	514	offs_t address = offset * 4;
514	515
515		m68ki_~~cpu~~_core m68k = (m68ki_~~cpu~~_core ) downcast<legacy_cpu_device *>(&space.device())->token();
	516	m68000_base_device m68k = (m68000_base_device ) downcast<legacy_cpu_device *>(&space.device())->token();
516	517
517	518	if ((address & 0xfff00000) == 0xfa800000 && VERBOSE < 2) {
518	519	// ?

trunk/src/mess/drivers/dectalk.c
r23920	r23921
291	291	void dectalk_x2212_recall( );
292	292	void dectalk_semaphore_w ( UINT16 data );
293	293	UINT16 dectalk_outfifo_r ( );
294		required_device<~~cpu~~_device> m_maincpu;
	294	required_device<m68000_base_device> m_maincpu;
295	295	required_device<cpu_device> m_dsp;
296	296	required_device<dac_device> m_dac;
297	297

trunk/src/mess/machine/mac.c
r23920	r23921
1131	1131	result = fdc->read(offset >> 8);
1132	1132
1133	1133	if (LOG_MAC_IWM)
1134		printf("mac_iwm_r: offset=0x%08x mem_mask %04x = %02x (PC %x)\n", offset, mem_mask, result, ~~m_m~~ainc~~pu->~~pc());
	1134	printf("mac_iwm_r: offset=0x%08x mem_mask %04x = %02x (PC %x)\n", offset, mem_mask, result, space.device().safe_pc());
1135	1135
1136	1136	return (result << 8) \| result;
1137	1137	}
r23920	r23921
1141	1141	applefdc_base_device *fdc = space.machine().device<applefdc_base_device>("fdc");
1142	1142
1143	1143	if (LOG_MAC_IWM)
1144		printf("mac_iwm_w: offset=0x%08x data=0x%04x mask %04x (PC=%x)\n", offset, data, mem_mask, ~~m_m~~ainc~~pu->~~pc());
	1144	printf("mac_iwm_w: offset=0x%08x data=0x%04x mask %04x (PC=%x)\n", offset, data, mem_mask, space.device().safe_pc());
1145	1145
1146	1146	if (ACCESSING_BITS_0_7)
1147	1147	fdc->write((offset >> 8), data & 0xff);
r23920	r23921
1500	1500	else if (ADB_IS_EGRET)
1501	1501	{
1502	1502	#if LOG_ADB
1503		printf("68K: New Egret state: SS %d VF %d (PC %x)\n", (data>>5)&1, (data>>4)&1, ~~m_m~~ainc~~pu->~~pc());
	1503	printf("68K: New Egret state: SS %d VF %d (PC %x)\n", (data>>5)&1, (data>>4)&1, space.device().safe_pc());
1504	1504	#endif
1505	1505	m_egret->set_via_full((data&0x10) ? 1 : 0);
1506	1506	m_egret->set_sys_session((data&0x20) ? 1 : 0);
r23920	r23921
1508	1508	else if (ADB_IS_CUDA)
1509	1509	{
1510	1510	#if LOG_ADB
1511		printf("68K: New Cuda state: TIP %d BYTEACK %d (PC %x)\n", (data>>5)&1, (data>>4)&1, ~~m_m~~ainc~~pu->~~pc());
	1511	printf("68K: New Cuda state: TIP %d BYTEACK %d (PC %x)\n", (data>>5)&1, (data>>4)&1, space.device().safe_pc());
1512	1512	#endif
1513	1513	m_cuda->set_byteack((data&0x10) ? 1 : 0);
1514	1514	m_cuda->set_tip((data&0x20) ? 1 : 0);
r23920	r23921
1578	1578	data = m_via2->read(space, offset);
1579	1579
1580	1580	if (LOG_VIA)
1581		logerror("mac_via2_r: offset=0x%02x = %02x (PC=%x)\n", offset*2, data, ~~m_m~~ainc~~pu->~~pc());
	1581	logerror("mac_via2_r: offset=0x%02x = %02x (PC=%x)\n", offset*2, data, space.device().safe_pc());
1582	1582
1583	1583	return (data & 0xff) \| (data << 8);
1584	1584	}
r23920	r23921
1589	1589	offset &= 0x0f;
1590	1590
1591	1591	if (LOG_VIA)
1592		logerror("mac_via2_w: offset=%x data=0x%08x mask=%x (PC=%x)\n", offset, data, mem_mask, ~~m_m~~ainc~~pu->~~pc());
	1592	logerror("mac_via2_w: offset=%x data=0x%08x mask=%x (PC=%x)\n", offset, data, mem_mask, space.device().safe_pc());
1593	1593
1594	1594	if (ACCESSING_BITS_0_7)
1595	1595	m_via2->write(space, offset, data & 0xff);

trunk/src/mess/machine/apollo_dbg.c
r23920	r23921
864	864
865	865	// get parameter string for parameter type and value at addr
866	866
867		static const char get_param(m68ki_~~cpu~~_core m68k, UINT32 addr, char type)
	867	static const char get_param(m68000_base_device m68k, UINT32 addr, char type)
868	868	{
869	869	UINT32 value = ~0;
870	870
r23920	r23921
880	880
881	881	if (!m68k->mmu_tmp_buserror_occurred)
882	882	{
883		value = m68k->~~memory.~~read32(addr);
	883	value = m68k->read32(addr);
884	884	if (!m68k->mmu_tmp_buserror_occurred && (value != ~0))
885	885	{
886	886	switch (type)
887	887	{
888	888	case 'S': // string w/o terminating 0
889		value1 = m68k->~~memory.~~read32(addr + 4);
	889	value1 = m68k->read32(addr + 4);
890	890	if (!m68k->mmu_tmp_buserror_occurred && (value1 != ~0))
891	891	{
892		maxlen = m68k->~~memory.~~read16(value1);
	892	maxlen = m68k->read16(value1);
893	893	if (maxlen > sizeof(sb) - 2)
894	894	{
895	895	maxlen = sizeof(sb) - 2;
r23920	r23921
898	898	case 's': // string
899	899	i = 0;
900	900	sb[i++] = '"';
901		while (i <= maxlen && (ch = m68k->~~memory.~~read8(value++)) != 0
	901	while (i <= maxlen && (ch = m68k->read8(value++)) != 0
902	902	&& !m68k->mmu_tmp_buserror_occurred)
903	903	{
904	904	sb[i++] = ch < 32 ? '.' : ch;
r23920	r23921
907	907	sb[i] = 0;
908	908	break;
909	909	case 'b': // byte (1 byte)
910		sprintf(sb, "0x%x", m68k->~~memory.~~read8(value));
	910	sprintf(sb, "0x%x", m68k->read8(value));
911	911	break;
912	912	case 'p': // pointer
913	913	sprintf(sb, "0x%x", value);
914	914	break;
915	915	case 'w': // word (2 byte)
916		sprintf(sb, "0x%x", m68k->~~memory.~~read16(value));
	916	sprintf(sb, "0x%x", m68k->read16(value));
917	917	break;
918	918	case 'x': // default (hex 32 bit)
919		sprintf(sb, "0x%x", m68k->~~memory.~~read32(value));
	919	sprintf(sb, "0x%x", m68k->read32(value));
920	920	break;
921	921	case 'u': // uid
922		sprintf(sb, "%08x.%08x", m68k->memory.read32(value),
923		m68k->memory.read32(value + 4));
	922	sprintf(sb, "%08x.%08x", m68k->read32(value),
	923	m68k->read32(value + 4));
924	924	break;
925	925	default:
926	926	sprintf(sb, "%c", type);
r23920	r23921
934	934
935	935	// get the svc call string
936	936
937		static const char* get_svc_call(m68ki_~~cpu~~_core *m68k, int trap_no,
	937	static const char* get_svc_call(m68000_base_device *m68k, int trap_no,
938	938	int trap_code, char *sb)
939	939	{
940	940	UINT32 sp = REG_A(m68k)[7];
r23920	r23921
1034	1034	return sb;
1035	1035	}
1036	1036
1037		static const char * disassemble(m68ki_~~cpu~~_core m68k, offs_t pc, char sb)
	1037	static const char * disassemble(m68000_base_device m68k, offs_t pc, char sb)
1038	1038	{
1039	1039	UINT8 oprom[10];
1040	1040	UINT8 opram[10];
r23920	r23921
1050	1050	int i;
1051	1051	for (i = 0; i < sizeof(oprom); i++)
1052	1052	{
1053		oprom[i] = opram[i] = m68k->~~memory.~~read8(pc + i);
	1053	oprom[i] = opram[i] = m68k->read8(pc + i);
1054	1054	if (m68k->mmu_tmp_buserror_occurred)
1055	1055	{
1056	1056	sprintf(sb, "- (apollo_disassemble failed at %08x)", pc + i);
r23920	r23921
1062	1062	return sb;
1063	1063	}
1064	1064	}
1065		m68k->d~~evice->d~~isassemble(sb, pc, oprom, opram, options);
	1065	m68k->disassemble(sb, pc, oprom, opram, options);
1066	1066
1067	1067	// restore previous bus error state
1068	1068	m68k->mmu_tmp_buserror_occurred = tmp_buserror_occurred;
r23920	r23921
1071	1071	return sb;
1072	1072	}
1073	1073
1074		static const UINT16 get_data(m68ki_~~cpu~~_core m68k, offs_t addr)
	1074	static const UINT16 get_data(m68000_base_device m68k, offs_t addr)
1075	1075	{
1076	1076	static UINT16 data[4];
1077	1077
r23920	r23921
1085	1085	int i;
1086	1086	for (i = 0; i < sizeof(data); i += 2)
1087	1087	{
1088		data[i/2] = m68k->~~memory.~~read16(addr + i);
	1088	data[i/2] = m68k->read16(addr + i);
1089	1089	}
1090	1090
1091	1091	// restore previous bus error state
r23920	r23921
1114	1114	{
1115	1115	UINT32 ppc_save;
1116	1116	UINT16 ir;
1117		m68ki_~~cpu~~_core m68k = (m68ki_~~cpu~~_core ) downcast<legacy_cpu_device *> (device)->token();
	1117	m68000_base_device m68k = (m68000_base_device ) downcast<legacy_cpu_device *> (device)->token();
1118	1118	m68k->mmu_tmp_buserror_occurred = 0;
1119	1119
1120	1120	/* Read next instruction */
1121		ir = (m68k->pref_addr == REG_PC(m68k)) ? m68k->pref_data : m68k->~~memory.~~readimm16(REG_PC(m68k));
	1121	ir = (m68k->pref_addr == REG_PC(m68k)) ? m68k->pref_data : m68k->readimm16(REG_PC(m68k));
1122	1122
1123	1123	// apollo_cpu_context expects the PC of current opcode in REG_PPC (not the previous PC)
1124	1124	ppc_save = REG_PPC(m68k);

trunk/src/mess/machine/apollo.c
r23920	r23921
270	270	else if ((data & APOLLO_CSR_CR_FPU_TRAP_ENABLE) == 0)
271	271	{
272	272	// enable FPU (i.e. FPU opcodes in CPU)
273		apollo_set_cpu_has_fpu(~~&sp~~a~~ce.dev~~ic~~e()~~, 1);
	273	apollo_set_cpu_has_fpu(m_maincpu, 1);
274	274	}
275	275	else
276	276	{
277	277	// disable FPU (i.e. FPU opcodes in CPU)
278		apollo_set_cpu_has_fpu(~~&sp~~a~~ce.dev~~ic~~e()~~, 0);
	278	apollo_set_cpu_has_fpu(m_maincpu, 0);
279	279
280	280	if (!apollo_is_dn3000())
281	281	{

trunk/src/mess/includes/apollo.h
r23920	r23921
68	68	const char apollo_cpu_context(device_t cpu);
69	69
70	70	// enable/disable the FPU
71		void apollo_set_cpu_has_fpu(device_t *device, int onoff);
	71	void apollo_set_cpu_has_fpu(m68000_base_device *device, int onoff);
72	72
73	73	// check for excessive logging
74	74	void apollo_check_log();
r23920	r23921
86	86	UINT32 apollo_get_node_id(void);
87	87
88	88	// should be called by the CPU core before executing each instruction
89		int apollo_instruction_hook(device_t *device, offs_t curpc);
	89	int apollo_instruction_hook(m68000_base_device *device, offs_t curpc);
90	90
91	91	void apollo_set_cache_status_register(UINT8 mask, UINT8 data);
92	92
r23920	r23921
123	123	m_pic8259_slave(*this, "pic8259_slave")
124	124	{ }
125	125
126		required_device<~~cpu~~_device> m_maincpu;
	126	required_device<m68000_base_device> m_maincpu;
127	127	required_device<sc499_device> m_ctape;
128	128	required_shared_ptr<UINT32> m_messram_ptr;
129	129

trunk/src/mess/includes/abc1600.h
r23920	r23921
85	85	m_video_ram(*this, "video_ram")
86	86	{ }
87	87
88		required_device<~~cpu~~_device> m_maincpu;
	88	required_device<m68000_base_device> m_maincpu;
89	89	required_device<z80dma_device> m_dma0;
90	90	required_device<z80dma_device> m_dma1;
91	91	required_device<z80dma_device> m_dma2;

trunk/src/mess/includes/mac.h
r23920	r23921
21	21	#include "machine/macrtc.h"
22	22	#include "sound/asc.h"
23	23	#include "sound/awacs.h"
	24	#include "cpu/m68000/m68000.h"
24	25
25	26	#define MAC_SCREEN_NAME "screen"
26	27	#define MAC_539X_1_TAG "scsi:539x_1"
r23920	r23921
220	221	m_vram16(*this,"vram16")
221	222	{ }
222	223
223		required_device<~~cpu~~_device> m_maincpu;
	224	required_device<m68000_base_device> m_maincpu;
224	225	required_device<via6522_device> m_via1;
225	226	optional_device<via6522_device> m_via2;
226	227	optional_device<asc_device> m_asc;

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