MAME SVN History

199869 Revisions

r23916 Monday 24th June, 2013 at 20:26:29 UTC by Wilbert Pol
am29000.c: Modernized cpu core. (nw)

[src/emu/cpu/am29000]

am29000.c am29000.h am29ops.h

trunk/src/emu/cpu/am29000/am29000.h
r23915	r23916
429	429	#define AM29000_INTR3 3
430	430
431	431
432		/***************************************************************************
433		PUBLIC FUNCTIONS
434		***************************************************************************/
	432	class am29000_cpu_device : public cpu_device
	433	{
	434	public:
	435	// construction/destruction
	436	am29000_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
435	437
436		DECLARE_LEGACY_CPU_DEVICE(AM29000, am29000);
	438	protected:
	439	// device-level overrides
	440	virtual void device_start();
	441	virtual void device_reset();
437	442
	443	// device_execute_interface overrides
	444	virtual UINT32 execute_min_cycles() const { return 1; }
	445	virtual UINT32 execute_max_cycles() const { return 2; }
	446	virtual UINT32 execute_input_lines() const { return 1; }
	447	virtual void execute_run();
	448	virtual void execute_set_input(int inputnum, int state);
	449
	450	// device_memory_interface overrides
	451	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const
	452	{
	453	switch (spacenum)
	454	{
	455	case AS_PROGRAM: return &m_program_config;
	456	case AS_IO: return &m_io_config;
	457	case AS_DATA: return &m_data_config;
	458	default: return NULL;
	459	}
	460	}
	461
	462	// device_state_interface overrides
	463	void state_string_export(const device_state_entry &entry, astring &string);
	464
	465	// device_disasm_interface overrides
	466	virtual UINT32 disasm_min_opcode_bytes() const { return 4; }
	467	virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
	468	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	469
	470	void signal_exception(UINT32 type);
	471	void external_irq_check();
	472	UINT32 read_program_word(UINT32 address);
	473	UINT32 get_abs_reg(UINT8 r, UINT32 iptr);
	474	void fetch_decode();
	475	UINT32 read_spr(UINT32 idx);
	476	void write_spr(UINT32 idx, UINT32 val);
	477	void ADD();
	478	void ADDS();
	479	void ADDU();
	480	void ADDC();
	481	void ADDCS();
	482	void ADDCU();
	483	void SUB();
	484	void SUBS();
	485	void SUBU();
	486	void SUBC();
	487	void SUBCS();
	488	void SUBCU();
	489	void SUBR();
	490	void SUBRS();
	491	void SUBRU();
	492	void SUBRC();
	493	void SUBRCS();
	494	void SUBRCU();
	495	void MULTIPLU();
	496	void MULTIPLY();
	497	void MUL();
	498	void MULL();
	499	void MULU();
	500	void DIVIDE();
	501	void DIVIDU();
	502	void DIV0();
	503	void DIV();
	504	void DIVL();
	505	void DIVREM();
	506	void CPEQ();
	507	void CPNEQ();
	508	void CPLT();
	509	void CPLTU();
	510	void CPLE();
	511	void CPLEU();
	512	void CPGT();
	513	void CPGTU();
	514	void CPGE();
	515	void CPGEU();
	516	void CPBYTE();
	517	void ASEQ();
	518	void ASNEQ();
	519	void ASLT();
	520	void ASLTU();
	521	void ASLE();
	522	void ASLEU();
	523	void ASGT();
	524	void ASGTU();
	525	void ASGE();
	526	void ASGEU();
	527	void AND();
	528	void ANDN();
	529	void NAND();
	530	void OR();
	531	void NOR();
	532	void XOR();
	533	void XNOR();
	534	void SLL();
	535	void SRL();
	536	void SRA();
	537	void EXTRACT();
	538	void LOAD();
	539	void LOADL();
	540	void LOADSET();
	541	void LOADM();
	542	void STORE();
	543	void STOREL();
	544	void STOREM();
	545	void EXBYTE();
	546	void EXHW();
	547	void EXHWS();
	548	void INBYTE();
	549	void INHW();
	550	void MFSR();
	551	void MFTLB();
	552	void MTSR();
	553	void MTSRIM();
	554	void MTTLB();
	555	void CONST();
	556	void CONSTH();
	557	void CONSTN();
	558	void CALL();
	559	void CALLI();
	560	void JMP();
	561	void JMPI();
	562	void JMPT();
	563	void JMPTI();
	564	void JMPF();
	565	void JMPFI();
	566	void JMPFDEC();
	567	void CLZ();
	568	void SETIP();
	569	void EMULATE();
	570	void INV();
	571	void IRET();
	572	void IRETINV();
	573	void HALT();
	574	void ILLEGAL();
	575	void CONVERT();
	576	void SQRT();
	577	void CLASS();
	578	void MULTM();
	579	void MULTMU();
	580
	581	address_space_config m_program_config;
	582	address_space_config m_io_config;
	583	address_space_config m_data_config;
	584
	585	INT32 m_icount;
	586	UINT32 m_pc;
	587
	588	/* General purpose */
	589	UINT32 m_r[256]; // TODO: There's only 192 implemented!
	590
	591	/* TLB */
	592	UINT32 m_tlb[128];
	593
	594	/* Protected SPRs */
	595	UINT32 m_vab;
	596	UINT32 m_ops;
	597	UINT32 m_cps;
	598	UINT32 m_cfg;
	599	UINT32 m_cha;
	600	UINT32 m_chd;
	601	UINT32 m_chc;
	602	UINT32 m_rbp;
	603	UINT32 m_tmc;
	604	UINT32 m_tmr;
	605	UINT32 m_pc0;
	606	UINT32 m_pc1;
	607	UINT32 m_pc2;
	608	UINT32 m_mmu;
	609	UINT32 m_lru;
	610
	611	/* Unprotected SPRs */
	612	UINT32 m_ipc;
	613	UINT32 m_ipa;
	614	UINT32 m_ipb;
	615	UINT32 m_q;
	616	UINT32 m_alu;
	617	UINT32 m_fpe;
	618	UINT32 m_inte;
	619	UINT32 m_fps;
	620
	621	/* Pipeline state */
	622	UINT32 m_exceptions;
	623	UINT32 m_exception_queue[4];
	624
	625	UINT8 m_irq_active;
	626	UINT8 m_irq_lines;
	627
	628	UINT32 m_exec_ir;
	629	UINT32 m_next_ir;
	630
	631	UINT32 m_pl_flags;
	632	UINT32 m_next_pl_flags;
	633
	634	UINT32 m_iret_pc;
	635
	636	UINT32 m_exec_pc;
	637	UINT32 m_next_pc;
	638
	639	address_space *m_program;
	640	direct_read_data *m_direct;
	641	address_space *m_data;
	642	direct_read_data *m_datadirect;
	643	address_space *m_io;
	644
	645	typedef void ( am29000_cpu_device::*opcode_func ) ();
	646	struct op_info {
	647	opcode_func opcode;
	648	UINT32 flags;
	649	};
	650
	651	static const op_info op_table[256];
	652	};
	653
	654
	655	extern const device_type AM29000;
	656
	657
438	658	#endif /* __AM29000_H__ */

trunk/src/emu/cpu/am29000/am29ops.h
r23915	r23916
20	20	#define IFLAG_CONTROL (1 << 9)
21	21
22	22
23		#define GET_RA_VAL (am29000->r[RA])
24		#define GET_RB_VAL (am29000->r[RB])
	23	#define GET_RA_VAL (m_r[RA])
	24	#define GET_RB_VAL (m_r[RB])
25	25
26		#define RA (get_abs_reg(am29000, am29000->exec_ir >> 8, am29000->ipa))
27		#define RB (get_abs_reg(am29000, am29000->exec_ir >> 0, am29000->ipb))
28		#define RC (get_abs_reg(am29000, am29000->exec_ir >> 16, am29000->ipc))
	26	#define RA (get_abs_reg(m_exec_ir >> 8, m_ipa))
	27	#define RB (get_abs_reg(m_exec_ir >> 0, m_ipb))
	28	#define RC (get_abs_reg(m_exec_ir >> 16, m_ipc))
29	29
30		#define INST_SA ((am29000->exec_ir >> 8) & 0xff)
31		#define INST_VN ((am29000->exec_ir >> 16) & 0xff)
32		#define INST_M_BIT (am29000->exec_ir & (1 << 24))
33		#define INST_CE_BIT (am29000->exec_ir & (1 << 23))
34		#define INST_AS_BIT (am29000->exec_ir & (1 << 22))
35		#define INST_PA_BIT (am29000->exec_ir & (1 << 21))
36		#define INST_SB_BIT (am29000->exec_ir & (1 << 20))
37		#define INST_UA_BIT (am29000->exec_ir & (1 << 19))
	30	#define INST_SA ((m_exec_ir >> 8) & 0xff)
	31	#define INST_VN ((m_exec_ir >> 16) & 0xff)
	32	#define INST_M_BIT (m_exec_ir & (1 << 24))
	33	#define INST_CE_BIT (m_exec_ir & (1 << 23))
	34	#define INST_AS_BIT (m_exec_ir & (1 << 22))
	35	#define INST_PA_BIT (m_exec_ir & (1 << 21))
	36	#define INST_SB_BIT (m_exec_ir & (1 << 20))
	37	#define INST_UA_BIT (m_exec_ir & (1 << 19))
38	38	#define INST_OPT_MASK (7)
39	39	#define INST_OPT_SHIFT (16)
40		#define INST_OPT_FIELD (((am~~29000->~~exec_ir) >> INST_OPT_SHIFT) & INST_OPT_MASK)
	40	#define INST_OPT_FIELD (((m_exec_ir) >> INST_OPT_SHIFT) & INST_OPT_MASK)
41	41	#define INST_CNTL_MASK (0x7f)
42	42	#define INST_CNTL_SHIFT (16)
43	43
44		#define I8 (am29000->exec_ir & 0xff)
45		#define I16 (((am29000->exec_ir >> 8) & 0xff00) \| (am29000->exec_ir & 0xff))
	44	#define I8 (m_exec_ir & 0xff)
	45	#define I16 (((m_exec_ir >> 8) & 0xff00) \| (m_exec_ir & 0xff))
46	46	#define I16_ZEX ((UINT32)(I16))
47	47	#define I16_SEX ((INT32)(INT16)I16)
48	48	#define I16_OEX (0xffff0000 \| I16)
49	49
50	50	#define JMP_ZEX (I16 << 2)
51		#define JMP_SEX ((INT32)(INT16)(((am~~29000->~~exec_ir >> 8) & 0xff00) \| (am~~29000->~~exec_ir & 0xff)) << 2)
	51	#define JMP_SEX ((INT32)(INT16)(((m_exec_ir >> 8) & 0xff00) \| (m_exec_ir & 0xff)) << 2)
52	52
53	53	#define BOOLEAN_MASK (1 << 31)
54	54	#define BOOLEAN_TRUE (1 << 31)
55	55	#define BOOLEAN_FALSE (0)
56	56
57		#define UNHANDLED_OP fatalerror("Am29000: Unhandled inst %s at %x\n", __FUNCTION__, am~~29000->~~exec_pc);
	57	#define UNHANDLED_OP fatalerror("Am29000: Unhandled inst %s at %x\n", __FUNCTION__, m_exec_pc);
58	58
59	59
60	60	/***************************************************************************
61		STRUCTS
62		***************************************************************************/
63
64		struct op_info
65		{
66		void (opcode)(am29000_state );
67		UINT32 flags;
68		};
69
70
71		/***************************************************************************
72	61	ALU FLAG CALCULATION
73	62	***************************************************************************/
74	63
75		#define SET_ALU_Z(r) am29000->alu &= ~ALU_Z; \
76		am29000->alu \|= (r == 0) << ALU_Z_SHIFT;
	64	#define SET_ALU_Z(r) m_alu &= ~ALU_Z; \
	65	m_alu \|= (r == 0) << ALU_Z_SHIFT;
77	66
78		#define SET_ALU_N(r) am29000->alu &= ~ALU_N; \
79		am29000->alu \|= ((UINT32)r & 0x80000000) >> (31 - ALU_N_SHIFT);
	67	#define SET_ALU_N(r) m_alu &= ~ALU_N; \
	68	m_alu \|= ((UINT32)r & 0x80000000) >> (31 - ALU_N_SHIFT);
80	69
81	70	#define CALC_C_ADD(r, a) ((UINT32)(r) < (UINT32)(a))
82	71
83		#define SET_ALU_C_ADD(r, a) am29000->alu &= ~ALU_C; \
84		am29000->alu \|= CALC_C_ADD(r, a) << ALU_C_SHIFT;
	72	#define SET_ALU_C_ADD(r, a) m_alu &= ~ALU_C; \
	73	m_alu \|= CALC_C_ADD(r, a) << ALU_C_SHIFT;
85	74
86	75	#define CALC_C_SUB(a, b) (!((UINT32)(a) < (UINT32)(b)))
87	76
88		#define SET_ALU_C_SUB(a, b) am29000->alu &= ~ALU_C; \
89		am29000->alu \|= CALC_C_SUB(a, b) << ALU_C_SHIFT;
	77	#define SET_ALU_C_SUB(a, b) m_alu &= ~ALU_C; \
	78	m_alu \|= CALC_C_SUB(a, b) << ALU_C_SHIFT;
90	79
91		#define SET_ALU_V_ADD(r, a, b) am29000->alu &= ~ALU_V; \
92		am29000->alu \|= (((INT32)(~((a) ^ (b)) & ((a) ^ (r))) < 0)) << ALU_V_SHIFT;
	80	#define SET_ALU_V_ADD(r, a, b) m_alu &= ~ALU_V; \
	81	m_alu \|= (((INT32)(~((a) ^ (b)) & ((a) ^ (r))) < 0)) << ALU_V_SHIFT;
93	82
94		#define SET_ALU_V_SUB(r, a, b) am29000->alu &= ~ALU_V; \
95		am29000->alu \|= ((INT32)(((a) ^ (b)) & ((a) ^ (r))) < 0) << ALU_V_SHIFT;
	83	#define SET_ALU_V_SUB(r, a, b) m_alu &= ~ALU_V; \
	84	m_alu \|= ((INT32)(((a) ^ (b)) & ((a) ^ (r))) < 0) << ALU_V_SHIFT;
96	85
97		#define GET_CARRY ((am~~29000->~~alu >> ALU_C_SHIFT) & 1)
	86	#define GET_CARRY ((m_alu >> ALU_C_SHIFT) & 1)
98	87
99	88
100	89
101		~~static~~ UINT32 rea~~d_spr(a~~m29000_~~stat~~e *a~~m29000,~~ UINT32 idx)
	90	UINT32 am29000_cpu_device::read_spr(UINT32 idx)
102	91	{
103	92	UINT32 val = 0;
104	93
105	94	switch (idx)
106	95	{
107		case SPR_VAB: val = am29000->vab; break;
108		case SPR_OPS: val = am29000->ops; break;
109		case SPR_CPS: val = am29000->cps; break;
110		case SPR_CFG: val = am29000->cfg; break;
111		case SPR_CHA: val = am29000->cha; break;
112		case SPR_CHD: val = am29000->chd; break;
113		case SPR_CHC: val = am29000->chc; break;
114		case SPR_RBP: val = am29000->rbp; break;
115		case SPR_TMC: val = am29000->tmc; break;
116		case SPR_TMR: val = am29000->tmr; break;
117		case SPR_PC0: val = am29000->pc0; break;
118		case SPR_PC1: val = am29000->pc1; break;
119		case SPR_PC2: val = am29000->pc2; break;
120		case SPR_MMU: val = am29000->mmu; break;
121		case SPR_LRU: val = am29000->lru; break;
122		case SPR_IPC: val = am29000->ipc; break;
123		case SPR_IPA: val = am29000->ipa; break;
124		case SPR_IPB: val = am29000->ipb; break;
125		case SPR_Q: val = am29000->q; break;
126		case SPR_ALU: val = am29000->alu; break;
	96	case SPR_VAB: val = m_vab; break;
	97	case SPR_OPS: val = m_ops; break;
	98	case SPR_CPS: val = m_cps; break;
	99	case SPR_CFG: val = m_cfg; break;
	100	case SPR_CHA: val = m_cha; break;
	101	case SPR_CHD: val = m_chd; break;
	102	case SPR_CHC: val = m_chc; break;
	103	case SPR_RBP: val = m_rbp; break;
	104	case SPR_TMC: val = m_tmc; break;
	105	case SPR_TMR: val = m_tmr; break;
	106	case SPR_PC0: val = m_pc0; break;
	107	case SPR_PC1: val = m_pc1; break;
	108	case SPR_PC2: val = m_pc2; break;
	109	case SPR_MMU: val = m_mmu; break;
	110	case SPR_LRU: val = m_lru; break;
	111	case SPR_IPC: val = m_ipc; break;
	112	case SPR_IPA: val = m_ipa; break;
	113	case SPR_IPB: val = m_ipb; break;
	114	case SPR_Q: val = m_q; break;
	115	case SPR_ALU: val = m_alu; break;
127	116	case SPR_BP: val = GET_ALU_BP; break;
128	117	case SPR_FC: val = GET_ALU_FC; break;
129	118	case SPR_CR: val = GET_CHC_CR; break;
130		case SPR_FPE: val = am29000->fpe; break;
131		case SPR_INTE: val = am29000->inte; break;
132		case SPR_FPS: val = am29000->fps; break;
	119	case SPR_FPE: val = m_fpe; break;
	120	case SPR_INTE: val = m_inte; break;
	121	case SPR_FPS: val = m_fps; break;
133	122	default:
134	123	logerror("Unknown SPR read (%d)\n", idx);
135	124	}
r23915	r23916
138	127	}
139	128
140	129
141		~~static~~ void ~~write_spr(~~am29000_state *am29000, UINT32 idx, UINT32 val)
	130	void am29000_cpu_device::write_spr(UINT32 idx, UINT32 val)
142	131	{
143	132	switch (idx)
144	133	{
145		case SPR_VAB: am~~29000->~~vab = val & (VAB_MASK << VAB_SHIFT);
	134	case SPR_VAB: m_vab = val & (VAB_MASK << VAB_SHIFT);
146	135	break;
147		case SPR_OPS: am~~29000->~~ops = val & (CPS_CA \| CPS_IP \| CPS_TE \| CPS_TP \| CPS_TU \| CPS_FZ \| CPS_LK \| CPS_RE \|
	136	case SPR_OPS: m_ops = val & (CPS_CA \| CPS_IP \| CPS_TE \| CPS_TP \| CPS_TU \| CPS_FZ \| CPS_LK \| CPS_RE \|
148	137	CPS_WM \| CPS_PD \| CPS_PI \| CPS_SM \| (CPS_IM_MASK << CPS_IM_SHIFT) \| CPS_DI \| CPS_DA);
149	138	break;
150		case SPR_CPS: am~~29000->~~cps = val & (CPS_CA \| CPS_IP \| CPS_TE \| CPS_TP \| CPS_TU \| CPS_FZ \| CPS_LK \| CPS_RE \|
	139	case SPR_CPS: m_cps = val & (CPS_CA \| CPS_IP \| CPS_TE \| CPS_TP \| CPS_TU \| CPS_FZ \| CPS_LK \| CPS_RE \|
151	140	CPS_WM \| CPS_PD \| CPS_PI \| CPS_SM \| (CPS_IM_MASK << CPS_IM_SHIFT) \| CPS_DI \| CPS_DA);
152	141	break;
153		case SPR_CFG: am29000->cfg = val & (CFG_DW \| CFG_VF \| CFG_RV \| CFG_BO \| CFG_CP \| CFG_CD);
154		am29000->cfg \|= PROCESSOR_REL_FIELD << CFG_PRL_SHIFT;
	142	case SPR_CFG: m_cfg = val & (CFG_DW \| CFG_VF \| CFG_RV \| CFG_BO \| CFG_CP \| CFG_CD);
	143	m_cfg \|= PROCESSOR_REL_FIELD << CFG_PRL_SHIFT;
155	144	break;
156		case SPR_CHA: am~~29000->~~cha = val;
	145	case SPR_CHA: m_cha = val;
157	146	break;
158		case SPR_CHD: am~~29000->~~chd = val;
	147	case SPR_CHD: m_chd = val;
159	148	break;
160		case SPR_CHC: am~~29000->~~chc = val;
	149	case SPR_CHC: m_chc = val;
161	150	break;
162		case SPR_RBP: am~~29000->~~rbp = val & RBP_MASK;
	151	case SPR_RBP: m_rbp = val & RBP_MASK;
163	152	break;
164		case SPR_TMC: am~~29000->~~tmc = val & TCV_MASK;
	153	case SPR_TMC: m_tmc = val & TCV_MASK;
165	154	break;
166		case SPR_TMR: am~~29000->~~tmr = val & (TMR_OV \| TMR_IN \| TMR_IE \| TMR_TRV_MASK);
	155	case SPR_TMR: m_tmr = val & (TMR_OV \| TMR_IN \| TMR_IE \| TMR_TRV_MASK);
167	156	break;
168		case SPR_PC0: am~~29000->~~pc0 = val & PC_MASK;
	157	case SPR_PC0: m_pc0 = val & PC_MASK;
169	158	break;
170		case SPR_PC1: am~~29000->~~pc1 = val & PC_MASK;
	159	case SPR_PC1: m_pc1 = val & PC_MASK;
171	160	break;
172		case SPR_PC2: am~~29000->~~pc2 = val & PC_MASK;
	161	case SPR_PC2: m_pc2 = val & PC_MASK;
173	162	break;
174		case SPR_MMU: am~~29000->~~mmu = val & ((MMU_PS_MASK << MMU_PS_SHIFT) \| MMU_PID_MASK);
	163	case SPR_MMU: m_mmu = val & ((MMU_PS_MASK << MMU_PS_SHIFT) \| MMU_PID_MASK);
175	164	break;
176		case SPR_LRU: am~~29000->~~lru = val & (LRU_MASK << LRU_SHIFT);
	165	case SPR_LRU: m_lru = val & (LRU_MASK << LRU_SHIFT);
177	166	break;
178		case SPR_IPC: am~~29000->~~ipc = val;// & IPX_MASK;
	167	case SPR_IPC: m_ipc = val;// & IPX_MASK;
179	168	break;
180		case SPR_IPA: am~~29000->~~ipa = val;// & IPX_MASK;
	169	case SPR_IPA: m_ipa = val;// & IPX_MASK;
181	170	break;
182		case SPR_IPB: am~~29000->~~ipb = val;// & IPX_MASK;
	171	case SPR_IPB: m_ipb = val;// & IPX_MASK;
183	172	break;
184		case SPR_Q: am~~29000->~~q = val;
	173	case SPR_Q: m_q = val;
185	174	break;
186		case SPR_ALU: am~~29000->~~alu = val & (ALU_DF \| ALU_V \| ALU_N \| ALU_Z \| ALU_C \| (ALU_BP_MASK << ALU_BP_SHIFT) \| (ALU_FC_MASK << ALU_FC_SHIFT));
	175	case SPR_ALU: m_alu = val & (ALU_DF \| ALU_V \| ALU_N \| ALU_Z \| ALU_C \| (ALU_BP_MASK << ALU_BP_SHIFT) \| (ALU_FC_MASK << ALU_FC_SHIFT));
187	176	break;
188		case SPR_BP: am29000->alu &= ~(ALU_BP_MASK << ALU_BP_SHIFT);
189		am29000->alu \|= (val & ALU_BP_MASK) << ALU_BP_SHIFT;
	177	case SPR_BP: m_alu &= ~(ALU_BP_MASK << ALU_BP_SHIFT);
	178	m_alu \|= (val & ALU_BP_MASK) << ALU_BP_SHIFT;
190	179	break;
191		case SPR_FC: am29000->alu &= ~(ALU_FC_MASK << ALU_FC_SHIFT);
192		am29000->alu \|= (val & ALU_FC_MASK) << ALU_FC_SHIFT;
	180	case SPR_FC: m_alu &= ~(ALU_FC_MASK << ALU_FC_SHIFT);
	181	m_alu \|= (val & ALU_FC_MASK) << ALU_FC_SHIFT;
193	182	break;
194		case SPR_CR: am29000->chc &= ~(CHC_CR_MASK << CHC_CR_SHIFT);
195		am29000->chc \|= (val & CHC_CR_MASK) << CHC_CR_SHIFT;
	183	case SPR_CR: m_chc &= ~(CHC_CR_MASK << CHC_CR_SHIFT);
	184	m_chc \|= (val & CHC_CR_MASK) << CHC_CR_SHIFT;
196	185	break;
197	186	// case SPR_FPE:
198	187	// case SPR_INTE:
r23915	r23916
210	199	INTEGER ARITHMETIC
211	200	***************************************************************************/
212	201
213		~~static~~ void ~~ADD(~~am29000_~~stat~~e *am29000)
	202	void am29000_cpu_device::ADD()
214	203	{
215	204	UINT32 a = GET_RA_VAL;
216	205	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
r23915	r23916
224	213	SET_ALU_C_ADD(r, a);
225	214	}
226	215
227		am~~29000->~~r[RC] = r;
	216	m_r[RC] = r;
228	217	}
229	218
230		~~static~~ void ~~ADDS(~~am29000_~~stat~~e *am29000)
	219	void am29000_cpu_device::ADDS()
231	220	{
232	221	UNHANDLED_OP;
233	222	}
234	223
235		~~static~~ void ~~ADDU(~~am29000_~~stat~~e *am29000)
	224	void am29000_cpu_device::ADDU()
236	225	{
237	226	UNHANDLED_OP;
238	227	}
239	228
240		~~static~~ void ~~ADDC(~~am29000_~~stat~~e *am29000)
	229	void am29000_cpu_device::ADDC()
241	230	{
242	231	UNHANDLED_OP;
243	232	}
244	233
245		~~static~~ void ~~ADDCS(~~am29000_~~stat~~e *am29000)
	234	void am29000_cpu_device::ADDCS()
246	235	{
247	236	UINT32 a = GET_RA_VAL;
248	237	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
r23915	r23916
258	247	SET_ALU_N(r);
259	248
260	249	carry = CALC_C_ADD(tmp, a) \|\| CALC_C_ADD(tmp + carry, carry);
261		am29000->alu &= ~ALU_C;
262		am29000->alu \|= carry << ALU_C_SHIFT;
	250	m_alu &= ~ALU_C;
	251	m_alu \|= carry << ALU_C_SHIFT;
263	252	}
264	253
265	254	// TODO: Trap on signed overflow
266		am~~29000->~~r[RC] = r;
	255	m_r[RC] = r;
267	256	}
268	257
269		~~static~~ void ~~ADDCU(~~am29000_~~stat~~e *am29000)
	258	void am29000_cpu_device::ADDCU()
270	259	{
271	260	UNHANDLED_OP;
272	261	}
273	262
274		~~static~~ void ~~SUB(~~am29000_~~stat~~e *am29000)
	263	void am29000_cpu_device::SUB()
275	264	{
276	265	UINT32 a = GET_RA_VAL;
277	266	UINT32 b = INST_M_BIT ? I8 : GET_RB_VAL;
r23915	r23916
286	275	}
287	276
288	277	// TODO: Trap on unsigned overflow
289		am~~29000->~~r[RC] = r;
	278	m_r[RC] = r;
290	279	}
291	280
292		~~static~~ void ~~SUBS(~~am29000_~~stat~~e *am29000)
	281	void am29000_cpu_device::SUBS()
293	282	{
294	283	UINT32 a = GET_RA_VAL;
295	284	UINT32 b = INST_M_BIT ? I8 : GET_RB_VAL;
r23915	r23916
306	295	if ((INT32)(((a) ^ (b)) & ((a) ^ (r))) < 0)
307	296	SIGNAL_EXCEPTION(EXCEPTION_OUT_OF_RANGE);
308	297
309		am~~29000->~~r[RC] = r;
	298	m_r[RC] = r;
310	299	}
311	300
312		~~static~~ void ~~SUBU(~~am29000_~~stat~~e *am29000)
	301	void am29000_cpu_device::SUBU()
313	302	{
314	303	UNHANDLED_OP;
315	304	}
316	305
317		~~static~~ void ~~SUBC(~~am29000_~~stat~~e *am29000)
	306	void am29000_cpu_device::SUBC()
318	307	{
319	308	UNHANDLED_OP;
320	309	}
321	310
322		~~static~~ void ~~SUBCS(~~am29000_~~stat~~e *am29000)
	311	void am29000_cpu_device::SUBCS()
323	312	{
324	313	UNHANDLED_OP;
325	314	}
326	315
327		~~static~~ void ~~SUBCU(~~am29000_~~stat~~e *am29000)
	316	void am29000_cpu_device::SUBCU()
328	317	{
329	318	UNHANDLED_OP;
330	319	}
331	320
332		~~static~~ void ~~SUBR(~~am29000_~~stat~~e *am29000)
	321	void am29000_cpu_device::SUBR()
333	322	{
334	323	UINT32 a = GET_RA_VAL;
335	324	UINT32 b = INST_M_BIT ? I8 : GET_RB_VAL;
r23915	r23916
343	332	SET_ALU_C_SUB(a, b);
344	333	}
345	334
346		am~~29000->~~r[RC] = r;
	335	m_r[RC] = r;
347	336	}
348	337
349		~~static~~ void ~~SUBRS(~~am29000_~~stat~~e *am29000)
	338	void am29000_cpu_device::SUBRS()
350	339	{
351	340	UNHANDLED_OP;
352	341	}
353	342
354		~~static~~ void ~~SUBRU(~~am29000_~~stat~~e *am29000)
	343	void am29000_cpu_device::SUBRU()
355	344	{
356	345	UNHANDLED_OP;
357	346	}
358	347
359		~~static~~ void ~~SUBRC(~~am29000_~~stat~~e *am29000)
	348	void am29000_cpu_device::SUBRC()
360	349	{
361	350	UINT32 a = GET_RA_VAL;
362	351	UINT32 b = INST_M_BIT ? I8 : GET_RB_VAL;
r23915	r23916
370	359	SET_ALU_C_SUB(a, b);
371	360	}
372	361
373		am~~29000->~~r[RC] = r;
	362	m_r[RC] = r;
374	363	}
375	364
376		~~static~~ void ~~SUBRCS(~~am29000_~~stat~~e *am29000)
	365	void am29000_cpu_device::SUBRCS()
377	366	{
378	367	UNHANDLED_OP;
379	368	}
380	369
381		~~static~~ void ~~SUBRCU(~~am29000_~~stat~~e *am29000)
	370	void am29000_cpu_device::SUBRCU()
382	371	{
383	372	UNHANDLED_OP;
384	373	}
385	374
386		~~static~~ void ~~MULTIPLU(~~am29000_~~stat~~e *am29000)
	375	void am29000_cpu_device::MULTIPLU()
387	376	{
388	377	UNHANDLED_OP;
389	378	}
390	379
391		~~static~~ void ~~MULTIPLY(~~am29000_~~stat~~e *am29000)
	380	void am29000_cpu_device::MULTIPLY()
392	381	{
393	382	UNHANDLED_OP;
394	383	}
395	384
396		~~static~~ void ~~MUL(~~am29000_~~stat~~e *am29000)
	385	void am29000_cpu_device::MUL()
397	386	{
398	387	/* TODO: Zero/Neg flags ? */
399	388	UINT32 a = GET_RA_VAL;
r23915	r23916
402	391	UINT64 v;
403	392	UINT32 sign;
404	393
405		if (am~~29000->~~q & 1)
	394	if (m_q & 1)
406	395	{
407	396	r = a + b;
408	397	sign = (r >> 31) ^ (((INT32)(~((a) ^ (b)) & ((a) ^ (r))) < 0));
r23915	r23916
413	402	sign = b >> 31;
414	403	}
415	404
416		v = ((((UINT64)r << 32) \| am29000->q) >> 1) \| ((UINT64)sign << 63);
417		am29000->q = v & 0xffffffff;
	405	v = ((((UINT64)r << 32) \| m_q) >> 1) \| ((UINT64)sign << 63);
	406	m_q = v & 0xffffffff;
418	407
419		am~~29000->~~r[RC] = v >> 32;
	408	m_r[RC] = v >> 32;
420	409	}
421	410
422		~~static~~ void ~~MULL(~~am29000_~~stat~~e *am29000)
	411	void am29000_cpu_device::MULL()
423	412	{
424	413	/* TODO: Zero/Neg flags ? */
425	414	UINT32 a = GET_RA_VAL;
r23915	r23916
428	417	UINT64 v;
429	418	UINT32 sign;
430	419
431		if (am~~29000->~~q & 1)
	420	if (m_q & 1)
432	421	{
433	422	r = b - a;
434	423	sign = (r >> 31) ^ ((INT32)(((a) ^ (b)) & ((a) ^ (r))) < 0);
r23915	r23916
439	428	sign = b >> 31;
440	429	}
441	430
442		v = ((((UINT64)r << 32) \| am29000->q) >> 1) \| ((UINT64)sign << 63);
443		am29000->q = v & 0xffffffff;
	431	v = ((((UINT64)r << 32) \| m_q) >> 1) \| ((UINT64)sign << 63);
	432	m_q = v & 0xffffffff;
444	433
445		am~~29000->~~r[RC] = v >> 32;
	434	m_r[RC] = v >> 32;
446	435	}
447	436
448		~~static~~ void ~~MULU(~~am29000_~~stat~~e *am29000)
	437	void am29000_cpu_device::MULU()
449	438	{
450	439	/* TODO: Zero/Neg flags ? */
451	440	UINT32 a = GET_RA_VAL;
r23915	r23916
454	443	UINT64 v;
455	444	UINT32 c;
456	445
457		if (am~~29000->~~q & 1)
	446	if (m_q & 1)
458	447	{
459	448	r = a + b;
460	449	c = (UINT32)(r) < (UINT32)(a);
r23915	r23916
465	454	c = 0;
466	455	}
467	456
468		v = ((((UINT64)r << 32) \| am29000->q) >> 1) \| ((UINT64)c << 63);
469		am29000->q = v & 0xffffffff;
	457	v = ((((UINT64)r << 32) \| m_q) >> 1) \| ((UINT64)c << 63);
	458	m_q = v & 0xffffffff;
470	459
471		am~~29000->~~r[RC] = v >> 32;
	460	m_r[RC] = v >> 32;
472	461	}
473	462
474		~~static~~ void ~~DIVIDE(~~am29000_~~stat~~e *am29000)
	463	void am29000_cpu_device::DIVIDE()
475	464	{
476		am29000->ipa = RA << IPX_SHIFT;
477		am29000->ipb = RB << IPX_SHIFT;
478		am29000->ipc = RC << IPX_SHIFT;
	465	m_ipa = RA << IPX_SHIFT;
	466	m_ipb = RB << IPX_SHIFT;
	467	m_ipc = RC << IPX_SHIFT;
479	468
480	469	SIGNAL_EXCEPTION(EXCEPTION_DIVIDE);
481	470	}
482	471
483		~~static~~ void ~~DIVIDU(~~am29000_~~stat~~e *am29000)
	472	void am29000_cpu_device::DIVIDU()
484	473	{
485	474	UNHANDLED_OP;
486	475	}
487	476
488		~~static~~ void ~~DIV0(~~am29000_~~stat~~e *am29000)
	477	void am29000_cpu_device::DIV0()
489	478	{
490	479	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
491	480	UINT64 v;
492	481
493	482	if (!FREEZE_MODE)
494	483	{
495		am~~29000->~~alu \|= ALU_DF;
	484	m_alu \|= ALU_DF;
496	485	SET_ALU_N(b);
497	486	}
498	487
499		v = (((UINT64)b << 32) \| am~~29000->~~q) << 1;
	488	v = (((UINT64)b << 32) \| m_q) << 1;
500	489
501		am~~29000->~~q = v & 0xffffffff;
	490	m_q = v & 0xffffffff;
502	491
503		am~~29000->~~r[RC] = v >> 32;
	492	m_r[RC] = v >> 32;
504	493	}
505	494
506		~~static~~ void ~~DIV(~~am29000_~~stat~~e *am29000)
	495	void am29000_cpu_device::DIV()
507	496	{
508	497	UINT32 a = GET_RA_VAL;
509	498	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
r23915	r23916
512	501	UINT64 r64;
513	502	UINT32 df;
514	503
515		if (am~~29000->~~alu & ALU_DF)
	504	if (m_alu & ALU_DF)
516	505	{
517	506	r = a - b;
518	507	c = !((UINT32)(a) < (UINT32)(b));
r23915	r23916
524	513	}
525	514
526	515
527		df = (~(c ^ (am~~29000->~~alu >> ALU_DF_SHIFT) ^ (am~~29000->~~alu >> ALU_N_SHIFT)) & 1);
	516	df = (~(c ^ (m_alu >> ALU_DF_SHIFT) ^ (m_alu >> ALU_N_SHIFT)) & 1);
528	517
529	518	if (!FREEZE_MODE)
530	519	{
531		am29000->alu &= ~ALU_DF;
532		am29000->alu \|= df << ALU_DF_SHIFT;
	520	m_alu &= ~ALU_DF;
	521	m_alu \|= df << ALU_DF_SHIFT;
533	522	SET_ALU_N(r);
534	523	}
535	524
536		r64 = ((((UINT64)r << 32) \| am29000->q) << 1) \| df;
537		am29000->q = r64 & 0xffffffff;
	525	r64 = ((((UINT64)r << 32) \| m_q) << 1) \| df;
	526	m_q = r64 & 0xffffffff;
538	527
539		am~~29000->~~r[RC] = r64 >> 32;
	528	m_r[RC] = r64 >> 32;
540	529	}
541	530
542		~~static~~ void ~~DIVL(~~am29000_~~stat~~e *am29000)
	531	void am29000_cpu_device::DIVL()
543	532	{
544	533	UINT32 a = GET_RA_VAL;
545	534	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
r23915	r23916
547	536	UINT32 r;
548	537	UINT32 df;
549	538
550		if (am~~29000->~~alu & ALU_DF)
	539	if (m_alu & ALU_DF)
551	540	{
552	541	r = a - b;
553	542	c = !((UINT32)(a) < (UINT32)(b));
r23915	r23916
558	547	c = (UINT32)(r) < (UINT32)(a);
559	548	}
560	549
561		df = (~(c ^ (am~~29000->~~alu >> ALU_DF_SHIFT) ^ (am~~29000->~~alu >> ALU_N_SHIFT)) & 1);
	550	df = (~(c ^ (m_alu >> ALU_DF_SHIFT) ^ (m_alu >> ALU_N_SHIFT)) & 1);
562	551
563	552	if (!FREEZE_MODE)
564	553	{
565		am29000->alu &= ~ALU_DF;
566		am29000->alu \|= df << ALU_DF_SHIFT;
	554	m_alu &= ~ALU_DF;
	555	m_alu \|= df << ALU_DF_SHIFT;
567	556	SET_ALU_N(r);
568	557	}
569	558
570		am29000->q = (am29000->q << 1) \| df;
571		am29000->r[RC] = r;
	559	m_q = (m_q << 1) \| df;
	560	m_r[RC] = r;
572	561	}
573	562
574		~~static~~ void ~~DIVREM(~~am29000_~~stat~~e *am29000)
	563	void am29000_cpu_device::DIVREM()
575	564	{
576	565	UINT32 a = GET_RA_VAL;
577	566	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
578	567
579		if (am29000->alu & ALU_DF)
580		am29000->r[RC] = a;
	568	if (m_alu & ALU_DF)
	569	m_r[RC] = a;
581	570	else
582		am~~29000->~~r[RC] = a + b;
	571	m_r[RC] = a + b;
583	572	}
584	573
585	574
r23915	r23916
587	576	COMPARE
588	577	***************************************************************************/
589	578
590		~~static~~ void ~~CPEQ(~~am29000_~~stat~~e *am29000)
	579	void am29000_cpu_device::CPEQ()
591	580	{
592	581	UINT32 a = GET_RA_VAL;
593	582	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
594	583	UINT32 r = a == b ? BOOLEAN_TRUE : BOOLEAN_FALSE;
595	584
596		am~~29000->~~r[RC] = r;
	585	m_r[RC] = r;
597	586	}
598	587
599		~~static~~ void ~~CPNEQ(~~am29000_~~stat~~e *am29000)
	588	void am29000_cpu_device::CPNEQ()
600	589	{
601	590	UINT32 a = GET_RA_VAL;
602	591	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
603	592	UINT32 r = a != b ? BOOLEAN_TRUE : BOOLEAN_FALSE;
604	593
605		am~~29000->~~r[RC] = r;
	594	m_r[RC] = r;
606	595	}
607	596
608		~~static~~ void ~~CPLT(~~am29000_~~stat~~e *am29000)
	597	void am29000_cpu_device::CPLT()
609	598	{
610	599	UINT32 a = GET_RA_VAL;
611	600	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
612	601	UINT32 r = (INT32)a < (INT32)b ? BOOLEAN_TRUE : BOOLEAN_FALSE;
613	602
614		am~~29000->~~r[RC] = r;
	603	m_r[RC] = r;
615	604	}
616	605
617		~~static~~ void ~~CPLTU(~~am29000_~~stat~~e *am29000)
	606	void am29000_cpu_device::CPLTU()
618	607	{
619	608	UINT32 a = GET_RA_VAL;
620	609	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
621	610	UINT32 r = (UINT32)a < (UINT32)b ? BOOLEAN_TRUE : BOOLEAN_FALSE;
622	611
623		am~~29000->~~r[RC] = r;
	612	m_r[RC] = r;
624	613	}
625	614
626		~~static~~ void ~~CPLE(~~am29000_~~stat~~e *am29000)
	615	void am29000_cpu_device::CPLE()
627	616	{
628	617	UINT32 a = GET_RA_VAL;
629	618	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
630	619	UINT32 r = (INT32)a <= (INT32)b ? BOOLEAN_TRUE : BOOLEAN_FALSE;
631	620
632		am~~29000->~~r[RC] = r;
	621	m_r[RC] = r;
633	622	}
634	623
635		~~static~~ void ~~CPLEU(~~am29000_~~stat~~e *am29000)
	624	void am29000_cpu_device::CPLEU()
636	625	{
637	626	UINT32 a = GET_RA_VAL;
638	627	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
639	628	UINT32 r = (UINT32)a <= (UINT32)b ? BOOLEAN_TRUE : BOOLEAN_FALSE;
640	629
641		am~~29000->~~r[RC] = r;
	630	m_r[RC] = r;
642	631	}
643	632
644		~~static~~ void ~~CPGT(~~am29000_~~stat~~e *am29000)
	633	void am29000_cpu_device::CPGT()
645	634	{
646	635	UINT32 a = GET_RA_VAL;
647	636	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
648	637	UINT32 r = (INT32)a > (INT32)b ? BOOLEAN_TRUE : BOOLEAN_FALSE;
649	638
650		am~~29000->~~r[RC] = r;
	639	m_r[RC] = r;
651	640	}
652	641
653		~~static~~ void ~~CPGTU(~~am29000_~~stat~~e *am29000)
	642	void am29000_cpu_device::CPGTU()
654	643	{
655	644	UINT32 a = GET_RA_VAL;
656	645	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
657	646	UINT32 r = (UINT32)a > (UINT32)b ? BOOLEAN_TRUE : BOOLEAN_FALSE;
658	647
659		am~~29000->~~r[RC] = r;
	648	m_r[RC] = r;
660	649	}
661	650
662		~~static~~ void ~~CPGE(~~am29000_~~stat~~e *am29000)
	651	void am29000_cpu_device::CPGE()
663	652	{
664	653	UINT32 a = GET_RA_VAL;
665	654	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
666	655	UINT32 r = (INT32)a >= (INT32)b ? BOOLEAN_TRUE : BOOLEAN_FALSE;
667	656
668		am~~29000->~~r[RC] = r;
	657	m_r[RC] = r;
669	658	}
670	659
671		~~static~~ void ~~CPGEU(~~am29000_~~stat~~e *am29000)
	660	void am29000_cpu_device::CPGEU()
672	661	{
673	662	UINT32 a = GET_RA_VAL;
674	663	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
675	664	UINT32 r = (UINT32)a >= (UINT32)b ? BOOLEAN_TRUE : BOOLEAN_FALSE;
676	665
677		am~~29000->~~r[RC] = r;
	666	m_r[RC] = r;
678	667	}
679	668
680		~~static~~ void ~~CPBYTE(~~am29000_~~stat~~e *am29000)
	669	void am29000_cpu_device::CPBYTE()
681	670	{
682	671	UINT32 a = GET_RA_VAL;
683	672	UINT32 b = INST_M_BIT ? I8 : GET_RB_VAL;
r23915	r23916
688	677	((a & 0x000000ff) == (b & 0x000000ff))
689	678	? BOOLEAN_TRUE : BOOLEAN_FALSE;
690	679
691		am~~29000->~~r[RC] = r;
	680	m_r[RC] = r;
692	681	}
693	682
694		~~static~~ void ~~ASEQ(~~am29000_~~stat~~e *am29000)
	683	void am29000_cpu_device::ASEQ()
695	684	{
696	685	if (USER_MODE && INST_VN < 64)
697	686	SIGNAL_EXCEPTION(EXCEPTION_PROTECTION_VIOLATION);
r23915	r23916
699	688	SIGNAL_EXCEPTION(INST_VN);
700	689	}
701	690
702		~~static~~ void ~~ASNEQ(~~am29000_~~stat~~e *am29000)
	691	void am29000_cpu_device::ASNEQ()
703	692	{
704	693	if (USER_MODE && INST_VN < 64)
705	694	SIGNAL_EXCEPTION(EXCEPTION_PROTECTION_VIOLATION);
r23915	r23916
707	696	SIGNAL_EXCEPTION(INST_VN);
708	697	}
709	698
710		~~static~~ void ~~ASLT(~~am29000_~~stat~~e *am29000)
	699	void am29000_cpu_device::ASLT()
711	700	{
712	701	if (USER_MODE && INST_VN < 64)
713	702	SIGNAL_EXCEPTION(EXCEPTION_PROTECTION_VIOLATION);
r23915	r23916
715	704	SIGNAL_EXCEPTION(INST_VN);
716	705	}
717	706
718		~~static~~ void ~~ASLTU(~~am29000_~~stat~~e *am29000)
	707	void am29000_cpu_device::ASLTU()
719	708	{
720	709	if (USER_MODE && INST_VN < 64)
721	710	SIGNAL_EXCEPTION(EXCEPTION_PROTECTION_VIOLATION);
r23915	r23916
723	712	SIGNAL_EXCEPTION(INST_VN);
724	713	}
725	714
726		~~static~~ void ~~ASLE(~~am29000_~~stat~~e *am29000)
	715	void am29000_cpu_device::ASLE()
727	716	{
728	717	if (USER_MODE && INST_VN < 64)
729	718	SIGNAL_EXCEPTION(EXCEPTION_PROTECTION_VIOLATION);
r23915	r23916
731	720	SIGNAL_EXCEPTION(INST_VN);
732	721	}
733	722
734		~~static~~ void ~~ASLEU(~~am29000_~~stat~~e *am29000)
	723	void am29000_cpu_device::ASLEU()
735	724	{
736	725	if (USER_MODE && INST_VN < 64)
737	726	SIGNAL_EXCEPTION(EXCEPTION_PROTECTION_VIOLATION);
r23915	r23916
739	728	SIGNAL_EXCEPTION(INST_VN);
740	729	}
741	730
742		~~static~~ void ~~ASGT(~~am29000_~~stat~~e *am29000)
	731	void am29000_cpu_device::ASGT()
743	732	{
744	733	if (USER_MODE && INST_VN < 64)
745	734	SIGNAL_EXCEPTION(EXCEPTION_PROTECTION_VIOLATION);
r23915	r23916
747	736	SIGNAL_EXCEPTION(INST_VN);
748	737	}
749	738
750		~~static~~ void ~~ASGTU(~~am29000_~~stat~~e *am29000)
	739	void am29000_cpu_device::ASGTU()
751	740	{
752	741	if (USER_MODE && INST_VN < 64)
753	742	SIGNAL_EXCEPTION(EXCEPTION_PROTECTION_VIOLATION);
r23915	r23916
755	744	SIGNAL_EXCEPTION(INST_VN);
756	745	}
757	746
758		~~static~~ void ~~ASGE(~~am29000_~~stat~~e *am29000)
	747	void am29000_cpu_device::ASGE()
759	748	{
760	749	if (USER_MODE && INST_VN < 64)
761	750	SIGNAL_EXCEPTION(EXCEPTION_PROTECTION_VIOLATION);
r23915	r23916
763	752	SIGNAL_EXCEPTION(INST_VN);
764	753	}
765	754
766		~~static~~ void ~~ASGEU(~~am29000_~~stat~~e *am29000)
	755	void am29000_cpu_device::ASGEU()
767	756	{
768	757	if (USER_MODE && INST_VN < 64)
769	758	SIGNAL_EXCEPTION(EXCEPTION_PROTECTION_VIOLATION);
r23915	r23916
776	765	LOGICAL
777	766	***************************************************************************/
778	767
779		~~static~~ void ~~AND(~~am29000_~~stat~~e *am29000)
	768	void am29000_cpu_device::AND()
780	769	{
781	770	UINT32 a = GET_RA_VAL;
782	771	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
r23915	r23916
788	777	SET_ALU_N(r);
789	778	}
790	779
791		am~~29000->~~r[RC] = r;
	780	m_r[RC] = r;
792	781	}
793	782
794		~~static~~ void ~~ANDN(~~am29000_~~stat~~e *am29000)
	783	void am29000_cpu_device::ANDN()
795	784	{
796	785	UINT32 a = GET_RA_VAL;
797	786	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
r23915	r23916
803	792	SET_ALU_N(r);
804	793	}
805	794
806		am~~29000->~~r[RC] = r;
	795	m_r[RC] = r;
807	796	}
808	797
809		~~static~~ void ~~NAND(~~am29000_~~stat~~e *am29000)
	798	void am29000_cpu_device::NAND()
810	799	{
811	800	UINT32 a = GET_RA_VAL;
812	801	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
r23915	r23916
818	807	SET_ALU_N(r);
819	808	}
820	809
821		am~~29000->~~r[RC] = r;
	810	m_r[RC] = r;
822	811	}
823	812
824		~~static~~ void ~~OR(~~am29000_~~stat~~e *am29000)
	813	void am29000_cpu_device::OR()
825	814	{
826	815	UINT32 a = GET_RA_VAL;
827	816	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
r23915	r23916
833	822	SET_ALU_N(r);
834	823	}
835	824
836		am~~29000->~~r[RC] = r;
	825	m_r[RC] = r;
837	826	}
838	827
839		~~static~~ void ~~NOR(~~am29000_~~stat~~e *am29000)
	828	void am29000_cpu_device::NOR()
840	829	{
841	830	UINT32 a = GET_RA_VAL;
842	831	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
r23915	r23916
848	837	SET_ALU_N(r);
849	838	}
850	839
851		am~~29000->~~r[RC] = r;
	840	m_r[RC] = r;
852	841	}
853	842
854		~~static~~ void ~~XOR(~~am29000_~~stat~~e *am29000)
	843	void am29000_cpu_device::XOR()
855	844	{
856	845	UINT32 a = GET_RA_VAL;
857	846	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
r23915	r23916
863	852	SET_ALU_N(r);
864	853	}
865	854
866		am~~29000->~~r[RC] = r;
	855	m_r[RC] = r;
867	856	}
868	857
869		~~static~~ void ~~XNOR(~~am29000_~~stat~~e *am29000)
	858	void am29000_cpu_device::XNOR()
870	859	{
871	860	UINT32 a = GET_RA_VAL;
872	861	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
r23915	r23916
878	867	SET_ALU_N(r);
879	868	}
880	869
881		am~~29000->~~r[RC] = r;
	870	m_r[RC] = r;
882	871	}
883	872
884	873
r23915	r23916
886	875	SHIFT
887	876	***************************************************************************/
888	877
889		~~static~~ void ~~SLL(~~am29000_~~stat~~e *am29000)
	878	void am29000_cpu_device::SLL()
890	879	{
891	880	UINT32 a = GET_RA_VAL;
892	881	UINT32 b = (INST_M_BIT ? I8: GET_RB_VAL) & 0x1f;
893	882	UINT32 r = a << b;
894	883
895		am~~29000->~~r[RC] = r;
	884	m_r[RC] = r;
896	885	}
897	886
898		~~static~~ void ~~SRL(~~am29000_~~stat~~e *am29000)
	887	void am29000_cpu_device::SRL()
899	888	{
900	889	UINT32 a = GET_RA_VAL;
901	890	UINT32 b = (INST_M_BIT ? I8: GET_RB_VAL) & 0x1f;
902	891	UINT32 r = a >> b;
903	892
904		am~~29000->~~r[RC] = r;
	893	m_r[RC] = r;
905	894	}
906	895
907		~~static~~ void ~~SRA(~~am29000_~~stat~~e *am29000)
	896	void am29000_cpu_device::SRA()
908	897	{
909	898	INT32 a = GET_RA_VAL;
910	899	UINT32 b = (INST_M_BIT ? I8: GET_RB_VAL) & 0x1f;
911	900	UINT32 r = a >> b;
912	901
913		am~~29000->~~r[RC] = r;
	902	m_r[RC] = r;
914	903	}
915	904
916		~~static~~ void ~~EXTRACT(~~am29000_~~stat~~e *am29000)
	905	void am29000_cpu_device::EXTRACT()
917	906	{
918	907	INT32 a = GET_RA_VAL;
919	908	UINT32 b = (INST_M_BIT ? I8: GET_RB_VAL);
r23915	r23916
921	910
922	911	r = (((UINT64)a << 32) \| b) << GET_ALU_FC;
923	912
924		am~~29000->~~r[RC] = r >> 32;
	913	m_r[RC] = r >> 32;
925	914	}
926	915
927	916
r23915	r23916
929	918	DATA MOVEMENT
930	919	***************************************************************************/
931	920
932		~~static~~ void ~~LOAD(~~am29000_~~stat~~e *am29000)
	921	void am29000_cpu_device::LOAD()
933	922	{
934	923	UINT32 addr = INST_M_BIT ? I8: GET_RB_VAL;
935	924	UINT32 r;
r23915	r23916
944	933	}
945	934	else
946	935	{
947		if (!INST_PA_BIT && !(am~~29000->~~cps & CPS_PD))
	936	if (!INST_PA_BIT && !(m_cps & CPS_PD))
948	937	{
949	938	fatalerror("Am29000: Address translation on LOAD\n");
950	939	}
r23915	r23916
956	945	return;
957	946	}
958	947
959		r = am~~29000->~~data->read_dword(addr);
	948	r = m_data->read_dword(addr);
960	949	}
961	950	}
962	951
r23915	r23916
965	954
966	955	if (!FREEZE_MODE)
967	956	{
968		am~~29000->~~chc = ((am~~29000->~~exec_ir << 8) & 0xff) \|
	957	m_chc = ((m_exec_ir << 8) & 0xff) \|
969	958	CHC_LS \|
970	959	RA << CHC_TR_SHIFT \|
971	960	CHC_CV;
972	961
973		am29000->cha = addr;
974		am29000->chd = r;
	962	m_cha = addr;
	963	m_chd = r;
975	964
976		if (!(am~~29000->~~cfg & CFG_DW) && (am~~29000->~~exec_ir & INST_SB_BIT))
	965	if (!(m_cfg & CFG_DW) && (m_exec_ir & INST_SB_BIT))
977	966	SET_ALU_BP(addr & 3);
978	967	}
979	968
980		am~~29000->~~r[RA] = r;
	969	m_r[RA] = r;
981	970
982		if (am~~29000->~~cfg & CFG_DW)
	971	if (m_cfg & CFG_DW)
983	972	logerror("DW ON A STORE");
984	973	}
985	974
986		~~static~~ void ~~LOADL(~~am29000_~~stat~~e *am29000)
	975	void am29000_cpu_device::LOADL()
987	976	{
988	977	UNHANDLED_OP;
989	978	}
990	979
991		~~static~~ void ~~LOADSET(~~am29000_~~stat~~e *am29000)
	980	void am29000_cpu_device::LOADSET()
992	981	{
993	982	UNHANDLED_OP;
994	983	}
995	984
996		~~static~~ void ~~LOADM(~~am29000_~~stat~~e *am29000)
	985	void am29000_cpu_device::LOADM()
997	986	{
998	987	UINT32 addr = INST_M_BIT ? I8: GET_RB_VAL;
999	988	UINT32 r;
r23915	r23916
1008	997	}
1009	998	else
1010	999	{
1011		if (!INST_PA_BIT && !(am~~29000->~~cps & CPS_PD))
	1000	if (!INST_PA_BIT && !(m_cps & CPS_PD))
1012	1001	{
1013	1002	fatalerror("Am29000: Address translation on LOAD\n");
1014	1003	}
r23915	r23916
1020	1009	return;
1021	1010	}
1022	1011
1023		r = am~~29000->~~data->read_dword(addr);
	1012	r = m_data->read_dword(addr);
1024	1013	}
1025	1014	}
1026	1015
1027	1016	if (!FREEZE_MODE)
1028	1017	{
1029	1018	// TODO
1030		am29000->chc &= (CHC_CR_MASK << CHC_CR_SHIFT);
1031		am29000->chc \|= ((am29000->exec_ir << 8) & 0xff) \|
	1019	m_chc &= (CHC_CR_MASK << CHC_CR_SHIFT);
	1020	m_chc \|= ((m_exec_ir << 8) & 0xff) \|
1032	1021	RA << CHC_TR_SHIFT \|
1033	1022	CHC_CV;
1034	1023
1035		am29000->cha = addr;
1036		am29000->chd = r; // ?????
	1024	m_cha = addr;
	1025	m_chd = r; // ?????
1037	1026
1038		if (!(am~~29000->~~cfg & CFG_DW) && (am~~29000->~~exec_ir & INST_SB_BIT))
	1027	if (!(m_cfg & CFG_DW) && (m_exec_ir & INST_SB_BIT))
1039	1028	SET_ALU_BP(addr & 3);
1040	1029	}
1041	1030
r23915	r23916
1045	1034	int cnt;
1046	1035	for (cnt = 0; cnt <= GET_CHC_CR; ++cnt)
1047	1036	{
1048		am~~29000->~~r[r] = am~~29000->~~data->read_dword(addr);
	1037	m_r[r] = m_data->read_dword(addr);
1049	1038
1050	1039	// SET_CHC_CR(cnt - 1);
1051	1040	addr += 4;
r23915	r23916
1056	1045	}
1057	1046	}
1058	1047
1059		~~static~~ void ~~STORE(~~am29000_~~stat~~e *am29000)
	1048	void am29000_cpu_device::STORE()
1060	1049	{
1061	1050	UINT32 addr = INST_M_BIT ? I8: GET_RB_VAL;
1062	1051	// UINT32 r;
r23915	r23916
1071	1060	}
1072	1061	else
1073	1062	{
1074		if (!INST_PA_BIT && !(am~~29000->~~cps & CPS_PD))
	1063	if (!INST_PA_BIT && !(m_cps & CPS_PD))
1075	1064	{
1076	1065	fatalerror("Am29000: Address translation on LOAD\n");
1077	1066	}
r23915	r23916
1086	1075	}
1087	1076	}
1088	1077
1089		am~~29000->~~data->write_dword(addr, am~~29000->~~r[RA]);
	1078	m_data->write_dword(addr, m_r[RA]);
1090	1079
1091	1080	if (!FREEZE_MODE)
1092	1081	{
1093		am~~29000->~~chc = ((am~~29000->~~exec_ir << 8) & 0xff) \|
	1082	m_chc = ((m_exec_ir << 8) & 0xff) \|
1094	1083	RA << CHC_TR_SHIFT \|
1095	1084	CHC_CV;
1096	1085
1097		am~~29000->~~cha = addr;
	1086	m_cha = addr;
1098	1087
1099		if (!(am~~29000->~~cfg & CFG_DW) && (am~~29000->~~exec_ir & INST_SB_BIT))
	1088	if (!(m_cfg & CFG_DW) && (m_exec_ir & INST_SB_BIT))
1100	1089	SET_ALU_BP(addr & 3);
1101	1090	}
1102	1091
1103		if (am~~29000->~~cfg & CFG_DW)
	1092	if (m_cfg & CFG_DW)
1104	1093	logerror("DW ON A STORE");
1105	1094	}
1106	1095
1107		~~static~~ void ~~STOREL(~~am29000_~~stat~~e *am29000)
	1096	void am29000_cpu_device::STOREL()
1108	1097	{
1109	1098	UNHANDLED_OP;
1110	1099	}
1111	1100
1112		~~static~~ void ~~STOREM(~~am29000_~~stat~~e *am29000)
	1101	void am29000_cpu_device::STOREM()
1113	1102	{
1114	1103	UINT32 addr = INST_M_BIT ? I8: GET_RB_VAL;
1115	1104	UINT32 r;
r23915	r23916
1124	1113	}
1125	1114	else
1126	1115	{
1127		if (!INST_PA_BIT && !(am~~29000->~~cps & CPS_PD))
	1116	if (!INST_PA_BIT && !(m_cps & CPS_PD))
1128	1117	{
1129	1118	fatalerror("Am29000: Address translation on LOAD\n");
1130	1119	}
r23915	r23916
1142	1131	if (!FREEZE_MODE)
1143	1132	{
1144	1133	// TODO
1145		am29000->chc &= (CHC_CR_MASK << CHC_CR_SHIFT);
1146		am29000->chc \|= ((am29000->exec_ir << 8) & 0xff) \|
	1134	m_chc &= (CHC_CR_MASK << CHC_CR_SHIFT);
	1135	m_chc \|= ((m_exec_ir << 8) & 0xff) \|
1147	1136	RA << CHC_TR_SHIFT \|
1148	1137	CHC_CV;
1149	1138
1150		am~~29000->~~cha = addr;
	1139	m_cha = addr;
1151	1140
1152		if (!(am~~29000->~~cfg & CFG_DW) && (am~~29000->~~exec_ir & INST_SB_BIT))
	1141	if (!(m_cfg & CFG_DW) && (m_exec_ir & INST_SB_BIT))
1153	1142	SET_ALU_BP(addr & 3);
1154	1143	}
1155	1144
r23915	r23916
1159	1148	int cnt;
1160	1149	for (cnt = 0; cnt <= GET_CHC_CR; ++cnt)
1161	1150	{
1162		am~~29000->~~data->write_dword(addr, am~~29000->~~r[r]);
	1151	m_data->write_dword(addr, m_r[r]);
1163	1152
1164	1153	// SET_CHC_CR(cnt - 1);
1165	1154	addr += 4;
r23915	r23916
1170	1159	}
1171	1160	}
1172	1161
1173		~~static~~ void ~~EXBYTE(~~am29000_~~stat~~e *am29000)
	1162	void am29000_cpu_device::EXBYTE()
1174	1163	{
1175	1164	UINT32 a = GET_RA_VAL;
1176	1165	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
r23915	r23916
1178	1167	UINT8 srcbyte;
1179	1168	UINT32 r;
1180	1169
1181		if (am~~29000->~~cfg & CFG_BO)
	1170	if (m_cfg & CFG_BO)
1182	1171	srcbyte = a >> 8 * bp;
1183	1172	else
1184	1173	srcbyte = a >> (8 * (3 - bp));
1185	1174
1186	1175	r = (b & 0xffffff00) \| srcbyte;
1187	1176
1188		am~~29000->~~r[RC] = r;
	1177	m_r[RC] = r;
1189	1178	}
1190	1179
1191		~~static~~ void ~~EXHW(~~am29000_~~stat~~e *am29000)
	1180	void am29000_cpu_device::EXHW()
1192	1181	{
1193	1182	UINT32 a = GET_RA_VAL;
1194	1183	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
1195		UINT32 wp = ((am~~29000->~~alu >> ALU_BP_SHIFT) & ALU_BP_MASK) >> 1;
	1184	UINT32 wp = ((m_alu >> ALU_BP_SHIFT) & ALU_BP_MASK) >> 1;
1196	1185	UINT16 srcword;
1197	1186	UINT32 r;
1198	1187
1199		if (am~~29000->~~cfg & CFG_BO)
	1188	if (m_cfg & CFG_BO)
1200	1189	srcword = a >> 16 * wp;
1201	1190	else
1202	1191	srcword = a >> (16 * (1 - wp));
1203	1192
1204	1193	r = (b & 0xffff0000) \| srcword;
1205	1194
1206		am~~29000->~~r[RC] = r;
	1195	m_r[RC] = r;
1207	1196	}
1208	1197
1209		~~static~~ void ~~EXHWS(~~am29000_~~stat~~e *am29000)
	1198	void am29000_cpu_device::EXHWS()
1210	1199	{
1211	1200	UINT32 a = GET_RA_VAL;
1212		UINT32 wp = ((am~~29000->~~alu >> ALU_BP_SHIFT) & ALU_BP_MASK) >> 1;
	1201	UINT32 wp = ((m_alu >> ALU_BP_SHIFT) & ALU_BP_MASK) >> 1;
1213	1202	UINT16 srcword;
1214	1203	UINT32 r;
1215	1204
1216		if (am~~29000->~~cfg & CFG_BO)
	1205	if (m_cfg & CFG_BO)
1217	1206	srcword = a >> 16 * wp;
1218	1207	else
1219	1208	srcword = a >> (16 * (1 - wp));
1220	1209
1221	1210	r = (INT32)(INT16)srcword;
1222	1211
1223		am~~29000->~~r[RC] = r;
	1212	m_r[RC] = r;
1224	1213	}
1225	1214
1226		~~static~~ void ~~INBYTE(~~am29000_~~stat~~e *am29000)
	1215	void am29000_cpu_device::INBYTE()
1227	1216	{
1228	1217	UINT32 a = GET_RA_VAL;
1229	1218	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
1230	1219	UINT32 bp = GET_ALU_BP;
1231		UINT8 shift = (am~~29000->~~cfg & CFG_BO) ? 8 * bp : (8 * (3 - bp));
	1220	UINT8 shift = (m_cfg & CFG_BO) ? 8 * bp : (8 * (3 - bp));
1232	1221	UINT32 r;
1233	1222
1234	1223	r = (a & ~(0xff << shift)) \| ((b & 0xff) << shift);
1235	1224
1236		am~~29000->~~r[RC] = r;
	1225	m_r[RC] = r;
1237	1226	}
1238	1227
1239		~~static~~ void ~~INHW(~~am29000_~~stat~~e *am29000)
	1228	void am29000_cpu_device::INHW()
1240	1229	{
1241	1230	UINT32 a = GET_RA_VAL;
1242	1231	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
1243		UINT32 wp = ((am29000->alu >> ALU_BP_SHIFT) & ALU_BP_MASK) >> 1;
1244		UINT32 shift = (am29000->cfg & CFG_BO) ? 16 * wp : (16 * (1 - wp));
	1232	UINT32 wp = ((m_alu >> ALU_BP_SHIFT) & ALU_BP_MASK) >> 1;
	1233	UINT32 shift = (m_cfg & CFG_BO) ? 16 * wp : (16 * (1 - wp));
1245	1234	UINT32 r;
1246	1235
1247	1236	r = (a & ~(0xffff << shift)) \| ((b & 0xffff) << shift);
1248	1237
1249		am~~29000->~~r[RC] = r;
	1238	m_r[RC] = r;
1250	1239	}
1251	1240
1252		~~static~~ void ~~MFSR(~~am29000_~~stat~~e *am29000)
	1241	void am29000_cpu_device::MFSR()
1253	1242	{
1254		am~~29000->~~r[RC] = read_spr(~~am29000,~~ INST_SA);
	1243	m_r[RC] = read_spr(INST_SA);
1255	1244	}
1256	1245
1257		~~static~~ void ~~MFTLB(~~am29000_~~stat~~e *am29000)
	1246	void am29000_cpu_device::MFTLB()
1258	1247	{
1259		am~~29000->~~r[RC] = am~~29000->~~tlb[GET_RA_VAL & 0x7f];
	1248	m_r[RC] = m_tlb[GET_RA_VAL & 0x7f];
1260	1249	}
1261	1250
1262		~~static~~ void ~~MTSR(~~am29000_~~stat~~e *am29000)
	1251	void am29000_cpu_device::MTSR()
1263	1252	{
1264		write_spr(~~am29000,~~ INST_SA, GET_RB_VAL);
	1253	write_spr(INST_SA, GET_RB_VAL);
1265	1254	}
1266	1255
1267		~~static~~ void ~~MTSRIM(~~am29000_~~stat~~e *am29000)
	1256	void am29000_cpu_device::MTSRIM()
1268	1257	{
1269		write_spr(~~am29000,~~ INST_SA, I16_ZEX);
	1258	write_spr(INST_SA, I16_ZEX);
1270	1259	}
1271	1260
1272		~~static~~ void ~~MTTLB(~~am29000_~~stat~~e *am29000)
	1261	void am29000_cpu_device::MTTLB()
1273	1262	{
1274		am~~29000->~~tlb[GET_RA_VAL & 0x7f] = GET_RB_VAL;
	1263	m_tlb[GET_RA_VAL & 0x7f] = GET_RB_VAL;
1275	1264	}
1276	1265
1277	1266
r23915	r23916
1279	1268	CONSTANT
1280	1269	***************************************************************************/
1281	1270
1282		~~static~~ void ~~CONST(~~am29000_~~stat~~e *am29000)
	1271	void am29000_cpu_device::CONST()
1283	1272	{
1284		am~~29000->~~r[RA] = I16_ZEX;
	1273	m_r[RA] = I16_ZEX;
1285	1274	}
1286	1275
1287		~~static~~ void ~~CONSTH(~~am29000_~~stat~~e *am29000)
	1276	void am29000_cpu_device::CONSTH()
1288	1277	{
1289		am~~29000->~~r[RA] = (I16 << 16) \| GET_RA_VAL;
	1278	m_r[RA] = (I16 << 16) \| GET_RA_VAL;
1290	1279	}
1291	1280
1292		~~static~~ void ~~CONSTN(~~am29000_~~stat~~e *am29000)
	1281	void am29000_cpu_device::CONSTN()
1293	1282	{
1294		am~~29000->~~r[RA] = I16_OEX;
	1283	m_r[RA] = I16_OEX;
1295	1284	}
1296	1285
1297	1286
r23915	r23916
1299	1288	BRANCH INSTRUCTIONS
1300	1289	***************************************************************************/
1301	1290
1302		~~static~~ void ~~CALL(~~am29000_~~stat~~e *am29000)
	1291	void am29000_cpu_device::CALL()
1303	1292	{
1304		UINT32 ret = am~~29000->~~next_pc;
	1293	UINT32 ret = m_next_pc;
1305	1294
1306	1295	if (INST_M_BIT)
1307		am~~29000->~~next_pc = JMP_ZEX;
	1296	m_next_pc = JMP_ZEX;
1308	1297	else
1309		am~~29000->~~next_pc = am~~29000->~~exec_pc + JMP_SEX;
	1298	m_next_pc = m_exec_pc + JMP_SEX;
1310	1299
1311		am29000->r[RA] = ret;
1312		am29000->next_pl_flags \|= PFLAG_JUMP;
	1300	m_r[RA] = ret;
	1301	m_next_pl_flags \|= PFLAG_JUMP;
1313	1302	}
1314	1303
1315		~~static~~ void ~~CALLI(~~am29000_~~stat~~e *am29000)
	1304	void am29000_cpu_device::CALLI()
1316	1305	{
1317		UINT32 ret = am29000->next_pc;
1318		am29000->next_pc = GET_RB_VAL;
1319		am29000->r[RA] = ret;
1320		am29000->next_pl_flags \|= PFLAG_JUMP;
	1306	UINT32 ret = m_next_pc;
	1307	m_next_pc = GET_RB_VAL;
	1308	m_r[RA] = ret;
	1309	m_next_pl_flags \|= PFLAG_JUMP;
1321	1310	}
1322	1311
1323		~~static~~ void ~~JMP(~~am29000_~~stat~~e *am29000)
	1312	void am29000_cpu_device::JMP()
1324	1313	{
1325	1314	if (INST_M_BIT)
1326		am~~29000->~~next_pc = JMP_ZEX;
	1315	m_next_pc = JMP_ZEX;
1327	1316	else
1328		am~~29000->~~next_pc = am~~29000->~~exec_pc + JMP_SEX;
	1317	m_next_pc = m_exec_pc + JMP_SEX;
1329	1318
1330		am~~29000->~~next_pl_flags \|= PFLAG_JUMP;
	1319	m_next_pl_flags \|= PFLAG_JUMP;
1331	1320	}
1332	1321
1333		~~static~~ void ~~JMPI(~~am29000_~~stat~~e *am29000)
	1322	void am29000_cpu_device::JMPI()
1334	1323	{
1335		am~~29000->~~next_pc = GET_RB_VAL;
	1324	m_next_pc = GET_RB_VAL;
1336	1325
1337		am~~29000->~~next_pl_flags \|= PFLAG_JUMP;
	1326	m_next_pl_flags \|= PFLAG_JUMP;
1338	1327	}
1339	1328
1340		~~static~~ void ~~JMPT(~~am29000_~~stat~~e *am29000)
	1329	void am29000_cpu_device::JMPT()
1341	1330	{
1342	1331	if ((GET_RA_VAL & BOOLEAN_MASK) == BOOLEAN_TRUE)
1343	1332	{
1344	1333	if (INST_M_BIT)
1345		am~~29000->~~next_pc = JMP_ZEX;
	1334	m_next_pc = JMP_ZEX;
1346	1335	else
1347		am~~29000->~~next_pc = am~~29000->~~exec_pc + JMP_SEX;
	1336	m_next_pc = m_exec_pc + JMP_SEX;
1348	1337
1349		am~~29000->~~next_pl_flags \|= PFLAG_JUMP;
	1338	m_next_pl_flags \|= PFLAG_JUMP;
1350	1339	}
1351	1340	}
1352	1341
1353		~~static~~ void ~~JMPTI(~~am29000_~~stat~~e *am29000)
	1342	void am29000_cpu_device::JMPTI()
1354	1343	{
1355	1344	if ((GET_RA_VAL & BOOLEAN_MASK) == BOOLEAN_TRUE)
1356	1345	{
1357		am29000->next_pc = GET_RB_VAL;
1358		am29000->next_pl_flags \|= PFLAG_JUMP;
	1346	m_next_pc = GET_RB_VAL;
	1347	m_next_pl_flags \|= PFLAG_JUMP;
1359	1348	}
1360	1349	}
1361	1350
1362		~~static~~ void ~~JMPF(~~am29000_~~stat~~e *am29000)
	1351	void am29000_cpu_device::JMPF()
1363	1352	{
1364	1353	if ((GET_RA_VAL & BOOLEAN_MASK) == BOOLEAN_FALSE)
1365	1354	{
1366	1355	if (INST_M_BIT)
1367		am~~29000->~~next_pc = JMP_ZEX;
	1356	m_next_pc = JMP_ZEX;
1368	1357	else
1369		am~~29000->~~next_pc = am~~29000->~~exec_pc + JMP_SEX;
	1358	m_next_pc = m_exec_pc + JMP_SEX;
1370	1359
1371		am~~29000->~~next_pl_flags \|= PFLAG_JUMP;
	1360	m_next_pl_flags \|= PFLAG_JUMP;
1372	1361	}
1373	1362	}
1374	1363
1375		~~static~~ void ~~JMPFI(~~am29000_~~stat~~e *am29000)
	1364	void am29000_cpu_device::JMPFI()
1376	1365	{
1377	1366	if ((GET_RA_VAL & BOOLEAN_MASK) == BOOLEAN_FALSE)
1378	1367	{
1379		am29000->next_pc = GET_RB_VAL;
1380		am29000->next_pl_flags \|= PFLAG_JUMP;
	1368	m_next_pc = GET_RB_VAL;
	1369	m_next_pl_flags \|= PFLAG_JUMP;
1381	1370	}
1382	1371	}
1383	1372
1384		~~static~~ void ~~JMPFDEC(~~am29000_~~stat~~e *am29000)
	1373	void am29000_cpu_device::JMPFDEC()
1385	1374	{
1386	1375	UINT32 a = GET_RA_VAL;
1387	1376
1388	1377	if ((a & BOOLEAN_MASK) == BOOLEAN_FALSE)
1389	1378	{
1390	1379	if (INST_M_BIT)
1391		am~~29000->~~next_pc = JMP_ZEX;
	1380	m_next_pc = JMP_ZEX;
1392	1381	else
1393		am~~29000->~~next_pc = am~~29000->~~exec_pc + JMP_SEX;
	1382	m_next_pc = m_exec_pc + JMP_SEX;
1394	1383
1395		am~~29000->~~next_pl_flags \|= PFLAG_JUMP;
	1384	m_next_pl_flags \|= PFLAG_JUMP;
1396	1385	}
1397	1386
1398		am~~29000->~~r[RA] = a - 1;
	1387	m_r[RA] = a - 1;
1399	1388	}
1400	1389
1401	1390
r23915	r23916
1403	1392	MISCELLANEOUS INSTRUCTIONS
1404	1393	***************************************************************************/
1405	1394
1406		~~static~~ void ~~CLZ(~~am29000_~~stat~~e *am29000)
	1395	void am29000_cpu_device::CLZ()
1407	1396	{
1408	1397	UINT32 b = INST_M_BIT ? I8: GET_RB_VAL;
1409	1398
1410		am~~29000->~~r[RC] = count_leading_zeros(b);
	1399	m_r[RC] = count_leading_zeros(b);
1411	1400	}
1412	1401
1413		~~static~~ void ~~SETIP(~~am29000_~~stat~~e *am29000)
	1402	void am29000_cpu_device::SETIP()
1414	1403	{
1415		am29000->ipa = RA << IPX_SHIFT;
1416		am29000->ipb = RB << IPX_SHIFT;
1417		am29000->ipc = RC << IPX_SHIFT;
	1404	m_ipa = RA << IPX_SHIFT;
	1405	m_ipb = RB << IPX_SHIFT;
	1406	m_ipc = RC << IPX_SHIFT;
1418	1407	}
1419	1408
1420		~~static~~ void ~~EMULATE(~~am29000_~~stat~~e *am29000)
	1409	void am29000_cpu_device::EMULATE()
1421	1410	{
1422	1411	UNHANDLED_OP;
1423	1412	}
1424	1413
1425		~~static~~ void ~~INV(~~am29000_~~stat~~e *am29000)
	1414	void am29000_cpu_device::INV()
1426	1415	{
1427	1416	/* Nothing to do yet */
1428	1417	}
1429	1418
1430		~~static~~ void ~~IRET(~~am29000_~~stat~~e *am29000)
	1419	void am29000_cpu_device::IRET()
1431	1420	{
1432		am29000->iret_pc = am29000->pc0;
1433		am29000->next_pc = am29000->pc1;
1434		am29000->cps = am29000->ops;
1435		am29000->next_pl_flags = PFLAG_IRET;
	1421	m_iret_pc = m_pc0;
	1422	m_next_pc = m_pc1;
	1423	m_cps = m_ops;
	1424	m_next_pl_flags = PFLAG_IRET;
1436	1425	}
1437	1426
1438		~~static~~ void ~~IRETINV(~~am29000_~~stat~~e *am29000)
	1427	void am29000_cpu_device::IRETINV()
1439	1428	{
1440	1429	UNHANDLED_OP;
1441	1430	}
1442	1431
1443		~~static~~ void ~~HALT(~~am29000_~~stat~~e *am29000)
	1432	void am29000_cpu_device::HALT()
1444	1433	{
1445	1434	UNHANDLED_OP;
1446	1435	}
1447	1436
1448	1437
1449		~~static~~ void ~~ILLEGAL(~~am29000_~~stat~~e *am29000)
	1438	void am29000_cpu_device::ILLEGAL()
1450	1439	{
1451		fatalerror("Am29000: Executed illegal instruction - this should never happen! %x (%x)\n", am~~29000->~~pc2, am~~29000->~~exec_pc);
	1440	fatalerror("Am29000: Executed illegal instruction - this should never happen! %x (%x)\n", m_pc2, m_exec_pc);
1452	1441	}
1453	1442
1454	1443
r23915	r23916
1457	1446	UNHANDLED
1458	1447	***************************************************************************/
1459	1448
1460		~~static~~ void ~~CONVERT(~~am29000_~~stat~~e *am29000)
	1449	void am29000_cpu_device::CONVERT()
1461	1450	{
1462	1451	UNHANDLED_OP;
1463	1452	}
1464	1453
1465		~~static~~ void ~~SQRT(~~am29000_~~stat~~e *am29000)
	1454	void am29000_cpu_device::SQRT()
1466	1455	{
1467	1456	UNHANDLED_OP;
1468	1457	}
1469	1458
1470		~~static~~ void ~~CLASS(~~am29000_~~stat~~e *am29000)
	1459	void am29000_cpu_device::CLASS()
1471	1460	{
1472	1461	UNHANDLED_OP;
1473	1462	}
1474	1463
1475		~~static~~ void ~~MULTM(~~am29000_~~stat~~e *am29000)
	1464	void am29000_cpu_device::MULTM()
1476	1465	{
1477	1466	UNHANDLED_OP;
1478	1467	}
1479	1468
1480		~~static~~ void ~~MULTMU(~~am29000_~~stat~~e *am29000)
	1469	void am29000_cpu_device::MULTMU()
1481	1470	{
1482	1471	UNHANDLED_OP;
1483	1472	}
1484	1473
1485	1474
1486		const op_info op_table[256] =
	1475	const am29000_cpu_device::op_info am29000_cpu_device::op_table[256] =
1487	1476	{
1488		{ ILLEGAL, IFLAG_ILLEGAL },
1489		{ CONSTN, IFLAG_RA_PRESENT },
1490		{ CONSTH, IFLAG_RA_PRESENT },
1491		{ CONST, IFLAG_RA_PRESENT },
1492		{ MTSRIM, 0 },
1493		{ ILLEGAL, IFLAG_ILLEGAL },
1494		{ LOADL, 0 },
1495		{ LOADL, 0 },
1496		{ CLZ, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT },
1497		{ CLZ, IFLAG_RC_PRESENT },
1498		{ EXBYTE, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1499		{ EXBYTE, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1500		{ INBYTE, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1501		{ INBYTE, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1502		{ STOREL, 0 },
1503		{ STOREL, 0 },
1504		{ ADDS, 0 },
1505		{ ADDS, 0 },
1506		{ ADDU, 0 },
1507		{ ADDU, 0 },
1508		{ ADD, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1509		{ ADD, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1510		{ LOAD, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1511		{ LOAD, IFLAG_RA_PRESENT },
1512		{ ADDCS, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1513		{ ADDCS, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1514		{ ADDCU, 0 },
1515		{ ADDCU, 0 },
1516		{ ADDC, 0 },
1517		{ ADDC, 0 },
1518		{ STORE, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1519		{ STORE, IFLAG_RA_PRESENT },
1520		{ SUBS, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1521		{ SUBS, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1522		{ SUBU, 0 },
1523		{ SUBU, 0 },
1524		{ SUB, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1525		{ SUB, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1526		{ LOADSET, 0 },
1527		{ LOADSET, 0 },
1528		{ SUBCS, 0 },
1529		{ SUBCS, 0 },
1530		{ SUBCU, 0 },
1531		{ SUBCU, 0 },
1532		{ SUBC, 0 },
1533		{ SUBC, 0 },
1534		{ CPBYTE, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1535		{ CPBYTE, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1536		{ SUBRS, 0 },
1537		{ SUBRS, 0 },
1538		{ SUBRU, 0 },
1539		{ SUBRU, 0 },
1540		{ SUBR, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1541		{ SUBR, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1542		{ LOADM, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1543		{ LOADM, IFLAG_RA_PRESENT },
1544		{ SUBRCS, 0 },
1545		{ SUBRCS, 0 },
1546		{ SUBRCU, 0 },
1547		{ SUBRCU, 0 },
1548		{ SUBRC, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1549		{ SUBRC, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1550		{ STOREM, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1551		{ STOREM, IFLAG_RA_PRESENT },
1552		{ CPLT, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1553		{ CPLT, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1554		{ CPLTU, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1555		{ CPLTU, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1556		{ CPLE, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1557		{ CPLE, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1558		{ CPLEU, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1559		{ CPLEU, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1560		{ CPGT, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1561		{ CPGT, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1562		{ CPGTU, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1563		{ CPGTU, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1564		{ CPGE, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1565		{ CPGE, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1566		{ CPGEU, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1567		{ CPGEU, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1568		{ ASLT, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1569		{ ASLT, IFLAG_RA_PRESENT },
1570		{ ASLTU, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1571		{ ASLTU, IFLAG_RA_PRESENT },
1572		{ ASLE, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1573		{ ASLE, IFLAG_RA_PRESENT },
1574		{ ASLEU, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1575		{ ASLEU, IFLAG_RA_PRESENT },
1576		{ ASGT, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1577		{ ASGT, IFLAG_RA_PRESENT },
1578		{ ASGTU, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1579		{ ASGTU, IFLAG_RA_PRESENT },
1580		{ ASGE, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1581		{ ASGE, IFLAG_RA_PRESENT },
1582		{ ASGEU, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1583		{ ASGEU, IFLAG_RA_PRESENT },
1584		{ CPEQ, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1585		{ CPEQ, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1586		{ CPNEQ, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1587		{ CPNEQ, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1588		{ MUL, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1589		{ MUL, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1590		{ MULL, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1591		{ MULL, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1592		{ DIV0, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT },
1593		{ DIV0, IFLAG_RC_PRESENT },
1594		{ DIV, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1595		{ DIV, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1596		{ DIVL, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1597		{ DIVL, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1598		{ DIVREM, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1599		{ DIVREM, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1600		{ ASEQ, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1601		{ ASEQ, IFLAG_RA_PRESENT },
1602		{ ASNEQ, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1603		{ ASNEQ, IFLAG_RA_PRESENT },
1604		{ MULU, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1605		{ MULU, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1606		{ ILLEGAL, IFLAG_ILLEGAL },
1607		{ ILLEGAL, IFLAG_ILLEGAL },
1608		{ INHW, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1609		{ INHW, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1610		{ EXTRACT, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1611		{ EXTRACT, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1612		{ EXHW, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1613		{ EXHW, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1614		{ EXHWS, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1615		{ ILLEGAL, IFLAG_ILLEGAL },
1616		{ SLL, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1617		{ SLL, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1618		{ SRL, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1619		{ SRL, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1620		{ ILLEGAL, IFLAG_ILLEGAL },
1621		{ ILLEGAL, IFLAG_ILLEGAL },
1622		{ SRA, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1623		{ SRA, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1624		{ IRET, IFLAG_SUPERVISOR_ONLY },
1625		{ HALT, IFLAG_SUPERVISOR_ONLY },
1626		{ ILLEGAL, IFLAG_ILLEGAL },
1627		{ ILLEGAL, IFLAG_ILLEGAL },
1628		{ IRETINV, IFLAG_SUPERVISOR_ONLY },
1629		{ ILLEGAL, IFLAG_ILLEGAL },
1630		{ ILLEGAL, IFLAG_ILLEGAL },
1631		{ ILLEGAL, IFLAG_ILLEGAL },
1632		{ AND, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1633		{ AND, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1634		{ OR, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1635		{ OR, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1636		{ XOR, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1637		{ XOR, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1638		{ XNOR, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1639		{ XNOR, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1640		{ NOR, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1641		{ NOR, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1642		{ NAND, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1643		{ NAND, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1644		{ ANDN, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
1645		{ ANDN, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1646		{ SETIP, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RC_PRESENT },
1647		{ INV, IFLAG_SUPERVISOR_ONLY },
1648		{ JMP, 0 },
1649		{ JMP, 0 },
1650		{ ILLEGAL, IFLAG_ILLEGAL },
1651		{ ILLEGAL, IFLAG_ILLEGAL },
1652		{ JMPF, IFLAG_RA_PRESENT },
1653		{ JMPF, IFLAG_RA_PRESENT },
1654		{ ILLEGAL, IFLAG_ILLEGAL },
1655		{ ILLEGAL, IFLAG_ILLEGAL },
1656		{ CALL, IFLAG_RA_PRESENT },
1657		{ CALL, IFLAG_RA_PRESENT },
1658		{ ILLEGAL, IFLAG_ILLEGAL },
1659		{ ILLEGAL, IFLAG_ILLEGAL },
1660		{ JMPT, IFLAG_RA_PRESENT },
1661		{ JMPT, IFLAG_RA_PRESENT },
1662		{ ILLEGAL, IFLAG_ILLEGAL },
1663		{ ILLEGAL, IFLAG_ILLEGAL },
1664		{ ILLEGAL, IFLAG_ILLEGAL },
1665		{ ILLEGAL, IFLAG_ILLEGAL },
1666		{ ILLEGAL, IFLAG_ILLEGAL },
1667		{ ILLEGAL, IFLAG_ILLEGAL },
1668		{ JMPFDEC, IFLAG_RA_PRESENT },
1669		{ JMPFDEC, IFLAG_RA_PRESENT },
1670		{ MFTLB, IFLAG_SUPERVISOR_ONLY \| IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
1671		{ ILLEGAL, IFLAG_ILLEGAL },
1672		{ ILLEGAL, IFLAG_ILLEGAL },
1673		{ ILLEGAL, IFLAG_ILLEGAL },
1674		{ ILLEGAL, IFLAG_ILLEGAL },
1675		{ ILLEGAL, IFLAG_ILLEGAL },
1676		{ ILLEGAL, IFLAG_ILLEGAL },
1677		{ ILLEGAL, IFLAG_ILLEGAL },
1678		{ MTTLB, IFLAG_SUPERVISOR_ONLY \| IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1679		{ ILLEGAL, IFLAG_ILLEGAL },
1680		{ JMPI, IFLAG_RB_PRESENT },
1681		{ ILLEGAL, IFLAG_ILLEGAL },
1682		{ ILLEGAL, IFLAG_ILLEGAL },
1683		{ ILLEGAL, IFLAG_ILLEGAL },
1684		{ JMPFI, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1685		{ ILLEGAL, IFLAG_ILLEGAL },
1686		{ MFSR, IFLAG_RC_PRESENT },
1687		{ ILLEGAL, IFLAG_ILLEGAL },
1688		{ CALLI, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1689		{ ILLEGAL, IFLAG_ILLEGAL },
1690		{ ILLEGAL, IFLAG_ILLEGAL },
1691		{ ILLEGAL, IFLAG_ILLEGAL },
1692		{ JMPTI, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
1693		{ ILLEGAL, IFLAG_ILLEGAL },
1694		{ MTSR, IFLAG_RB_PRESENT },
1695		{ ILLEGAL, IFLAG_ILLEGAL },
1696		{ ILLEGAL, IFLAG_ILLEGAL },
1697		{ ILLEGAL, IFLAG_ILLEGAL },
1698		{ ILLEGAL, IFLAG_ILLEGAL },
1699		{ ILLEGAL, IFLAG_ILLEGAL },
1700		{ ILLEGAL, IFLAG_ILLEGAL },
1701		{ ILLEGAL, IFLAG_ILLEGAL },
1702		{ ILLEGAL, IFLAG_ILLEGAL },
1703		{ EMULATE, 0 },
1704		{ ILLEGAL, IFLAG_ILLEGAL },
1705		{ ILLEGAL, IFLAG_ILLEGAL },
1706		{ ILLEGAL, IFLAG_ILLEGAL },
1707		{ ILLEGAL, IFLAG_ILLEGAL },
1708		{ ILLEGAL, IFLAG_ILLEGAL },
1709		{ ILLEGAL, IFLAG_ILLEGAL },
1710		{ MULTM, 0 },
1711		{ MULTMU, 0 },
1712		{ MULTIPLY, 0 },
1713		{ DIVIDE, 0 },
1714		{ MULTIPLU, 0 },
1715		{ DIVIDU, 0 },
1716		{ CONVERT, 0 },
1717		{ SQRT, 0 },
1718		{ CLASS, 0 },
1719		{ ILLEGAL, IFLAG_ILLEGAL },
1720		{ ILLEGAL, IFLAG_ILLEGAL },
1721		{ ILLEGAL, IFLAG_ILLEGAL },
	1477	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1478	{ &am29000_cpu_device::CONSTN, IFLAG_RA_PRESENT },
	1479	{ &am29000_cpu_device::CONSTH, IFLAG_RA_PRESENT },
	1480	{ &am29000_cpu_device::CONST, IFLAG_RA_PRESENT },
	1481	{ &am29000_cpu_device::MTSRIM, 0 },
	1482	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1483	{ &am29000_cpu_device::LOADL, 0 },
	1484	{ &am29000_cpu_device::LOADL, 0 },
	1485	{ &am29000_cpu_device::CLZ, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT },
	1486	{ &am29000_cpu_device::CLZ, IFLAG_RC_PRESENT },
	1487	{ &am29000_cpu_device::EXBYTE, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1488	{ &am29000_cpu_device::EXBYTE, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1489	{ &am29000_cpu_device::INBYTE, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1490	{ &am29000_cpu_device::INBYTE, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1491	{ &am29000_cpu_device::STOREL, 0 },
	1492	{ &am29000_cpu_device::STOREL, 0 },
	1493	{ &am29000_cpu_device::ADDS, 0 },
	1494	{ &am29000_cpu_device::ADDS, 0 },
	1495	{ &am29000_cpu_device::ADDU, 0 },
	1496	{ &am29000_cpu_device::ADDU, 0 },
	1497	{ &am29000_cpu_device::ADD, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1498	{ &am29000_cpu_device::ADD, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1499	{ &am29000_cpu_device::LOAD, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1500	{ &am29000_cpu_device::LOAD, IFLAG_RA_PRESENT },
	1501	{ &am29000_cpu_device::ADDCS, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1502	{ &am29000_cpu_device::ADDCS, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1503	{ &am29000_cpu_device::ADDCU, 0 },
	1504	{ &am29000_cpu_device::ADDCU, 0 },
	1505	{ &am29000_cpu_device::ADDC, 0 },
	1506	{ &am29000_cpu_device::ADDC, 0 },
	1507	{ &am29000_cpu_device::STORE, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1508	{ &am29000_cpu_device::STORE, IFLAG_RA_PRESENT },
	1509	{ &am29000_cpu_device::SUBS, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1510	{ &am29000_cpu_device::SUBS, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1511	{ &am29000_cpu_device::SUBU, 0 },
	1512	{ &am29000_cpu_device::SUBU, 0 },
	1513	{ &am29000_cpu_device::SUB, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1514	{ &am29000_cpu_device::SUB, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1515	{ &am29000_cpu_device::LOADSET, 0 },
	1516	{ &am29000_cpu_device::LOADSET, 0 },
	1517	{ &am29000_cpu_device::SUBCS, 0 },
	1518	{ &am29000_cpu_device::SUBCS, 0 },
	1519	{ &am29000_cpu_device::SUBCU, 0 },
	1520	{ &am29000_cpu_device::SUBCU, 0 },
	1521	{ &am29000_cpu_device::SUBC, 0 },
	1522	{ &am29000_cpu_device::SUBC, 0 },
	1523	{ &am29000_cpu_device::CPBYTE, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1524	{ &am29000_cpu_device::CPBYTE, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1525	{ &am29000_cpu_device::SUBRS, 0 },
	1526	{ &am29000_cpu_device::SUBRS, 0 },
	1527	{ &am29000_cpu_device::SUBRU, 0 },
	1528	{ &am29000_cpu_device::SUBRU, 0 },
	1529	{ &am29000_cpu_device::SUBR, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1530	{ &am29000_cpu_device::SUBR, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1531	{ &am29000_cpu_device::LOADM, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1532	{ &am29000_cpu_device::LOADM, IFLAG_RA_PRESENT },
	1533	{ &am29000_cpu_device::SUBRCS, 0 },
	1534	{ &am29000_cpu_device::SUBRCS, 0 },
	1535	{ &am29000_cpu_device::SUBRCU, 0 },
	1536	{ &am29000_cpu_device::SUBRCU, 0 },
	1537	{ &am29000_cpu_device::SUBRC, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1538	{ &am29000_cpu_device::SUBRC, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1539	{ &am29000_cpu_device::STOREM, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1540	{ &am29000_cpu_device::STOREM, IFLAG_RA_PRESENT },
	1541	{ &am29000_cpu_device::CPLT, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1542	{ &am29000_cpu_device::CPLT, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1543	{ &am29000_cpu_device::CPLTU, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1544	{ &am29000_cpu_device::CPLTU, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1545	{ &am29000_cpu_device::CPLE, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1546	{ &am29000_cpu_device::CPLE, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1547	{ &am29000_cpu_device::CPLEU, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1548	{ &am29000_cpu_device::CPLEU, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1549	{ &am29000_cpu_device::CPGT, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1550	{ &am29000_cpu_device::CPGT, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1551	{ &am29000_cpu_device::CPGTU, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1552	{ &am29000_cpu_device::CPGTU, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1553	{ &am29000_cpu_device::CPGE, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1554	{ &am29000_cpu_device::CPGE, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1555	{ &am29000_cpu_device::CPGEU, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1556	{ &am29000_cpu_device::CPGEU, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1557	{ &am29000_cpu_device::ASLT, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1558	{ &am29000_cpu_device::ASLT, IFLAG_RA_PRESENT },
	1559	{ &am29000_cpu_device::ASLTU, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1560	{ &am29000_cpu_device::ASLTU, IFLAG_RA_PRESENT },
	1561	{ &am29000_cpu_device::ASLE, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1562	{ &am29000_cpu_device::ASLE, IFLAG_RA_PRESENT },
	1563	{ &am29000_cpu_device::ASLEU, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1564	{ &am29000_cpu_device::ASLEU, IFLAG_RA_PRESENT },
	1565	{ &am29000_cpu_device::ASGT, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1566	{ &am29000_cpu_device::ASGT, IFLAG_RA_PRESENT },
	1567	{ &am29000_cpu_device::ASGTU, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1568	{ &am29000_cpu_device::ASGTU, IFLAG_RA_PRESENT },
	1569	{ &am29000_cpu_device::ASGE, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1570	{ &am29000_cpu_device::ASGE, IFLAG_RA_PRESENT },
	1571	{ &am29000_cpu_device::ASGEU, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1572	{ &am29000_cpu_device::ASGEU, IFLAG_RA_PRESENT },
	1573	{ &am29000_cpu_device::CPEQ, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1574	{ &am29000_cpu_device::CPEQ, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1575	{ &am29000_cpu_device::CPNEQ, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1576	{ &am29000_cpu_device::CPNEQ, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1577	{ &am29000_cpu_device::MUL, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1578	{ &am29000_cpu_device::MUL, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1579	{ &am29000_cpu_device::MULL, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1580	{ &am29000_cpu_device::MULL, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1581	{ &am29000_cpu_device::DIV0, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT },
	1582	{ &am29000_cpu_device::DIV0, IFLAG_RC_PRESENT },
	1583	{ &am29000_cpu_device::DIV, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1584	{ &am29000_cpu_device::DIV, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1585	{ &am29000_cpu_device::DIVL, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1586	{ &am29000_cpu_device::DIVL, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1587	{ &am29000_cpu_device::DIVREM, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1588	{ &am29000_cpu_device::DIVREM, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1589	{ &am29000_cpu_device::ASEQ, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1590	{ &am29000_cpu_device::ASEQ, IFLAG_RA_PRESENT },
	1591	{ &am29000_cpu_device::ASNEQ, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1592	{ &am29000_cpu_device::ASNEQ, IFLAG_RA_PRESENT },
	1593	{ &am29000_cpu_device::MULU, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1594	{ &am29000_cpu_device::MULU, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1595	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1596	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1597	{ &am29000_cpu_device::INHW, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1598	{ &am29000_cpu_device::INHW, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1599	{ &am29000_cpu_device::EXTRACT, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1600	{ &am29000_cpu_device::EXTRACT, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1601	{ &am29000_cpu_device::EXHW, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1602	{ &am29000_cpu_device::EXHW, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1603	{ &am29000_cpu_device::EXHWS, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1604	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1605	{ &am29000_cpu_device::SLL, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1606	{ &am29000_cpu_device::SLL, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1607	{ &am29000_cpu_device::SRL, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1608	{ &am29000_cpu_device::SRL, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1609	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1610	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1611	{ &am29000_cpu_device::SRA, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1612	{ &am29000_cpu_device::SRA, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1613	{ &am29000_cpu_device::IRET, IFLAG_SUPERVISOR_ONLY },
	1614	{ &am29000_cpu_device::HALT, IFLAG_SUPERVISOR_ONLY },
	1615	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1616	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1617	{ &am29000_cpu_device::IRETINV, IFLAG_SUPERVISOR_ONLY },
	1618	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1619	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1620	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1621	{ &am29000_cpu_device::AND, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1622	{ &am29000_cpu_device::AND, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1623	{ &am29000_cpu_device::OR, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1624	{ &am29000_cpu_device::OR, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1625	{ &am29000_cpu_device::XOR, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1626	{ &am29000_cpu_device::XOR, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1627	{ &am29000_cpu_device::XNOR, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1628	{ &am29000_cpu_device::XNOR, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1629	{ &am29000_cpu_device::NOR, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1630	{ &am29000_cpu_device::NOR, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1631	{ &am29000_cpu_device::NAND, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1632	{ &am29000_cpu_device::NAND, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1633	{ &am29000_cpu_device::ANDN, IFLAG_RC_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RA_PRESENT },
	1634	{ &am29000_cpu_device::ANDN, IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1635	{ &am29000_cpu_device::SETIP, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT \| IFLAG_RC_PRESENT },
	1636	{ &am29000_cpu_device::INV, IFLAG_SUPERVISOR_ONLY },
	1637	{ &am29000_cpu_device::JMP, 0 },
	1638	{ &am29000_cpu_device::JMP, 0 },
	1639	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1640	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1641	{ &am29000_cpu_device::JMPF, IFLAG_RA_PRESENT },
	1642	{ &am29000_cpu_device::JMPF, IFLAG_RA_PRESENT },
	1643	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1644	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1645	{ &am29000_cpu_device::CALL, IFLAG_RA_PRESENT },
	1646	{ &am29000_cpu_device::CALL, IFLAG_RA_PRESENT },
	1647	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1648	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1649	{ &am29000_cpu_device::JMPT, IFLAG_RA_PRESENT },
	1650	{ &am29000_cpu_device::JMPT, IFLAG_RA_PRESENT },
	1651	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1652	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1653	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1654	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1655	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1656	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1657	{ &am29000_cpu_device::JMPFDEC, IFLAG_RA_PRESENT },
	1658	{ &am29000_cpu_device::JMPFDEC, IFLAG_RA_PRESENT },
	1659	{ &am29000_cpu_device::MFTLB, IFLAG_SUPERVISOR_ONLY \| IFLAG_RC_PRESENT \| IFLAG_RA_PRESENT },
	1660	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1661	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1662	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1663	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1664	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1665	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1666	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1667	{ &am29000_cpu_device::MTTLB, IFLAG_SUPERVISOR_ONLY \| IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1668	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1669	{ &am29000_cpu_device::JMPI, IFLAG_RB_PRESENT },
	1670	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1671	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1672	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1673	{ &am29000_cpu_device::JMPFI, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1674	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1675	{ &am29000_cpu_device::MFSR, IFLAG_RC_PRESENT },
	1676	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1677	{ &am29000_cpu_device::CALLI, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1678	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1679	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1680	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1681	{ &am29000_cpu_device::JMPTI, IFLAG_RA_PRESENT \| IFLAG_RB_PRESENT },
	1682	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1683	{ &am29000_cpu_device::MTSR, IFLAG_RB_PRESENT },
	1684	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1685	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1686	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1687	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1688	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1689	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1690	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1691	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1692	{ &am29000_cpu_device::EMULATE, 0 },
	1693	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1694	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1695	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1696	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1697	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1698	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1699	{ &am29000_cpu_device::MULTM, 0 },
	1700	{ &am29000_cpu_device::MULTMU, 0 },
	1701	{ &am29000_cpu_device::MULTIPLY, 0 },
	1702	{ &am29000_cpu_device::DIVIDE, 0 },
	1703	{ &am29000_cpu_device::MULTIPLU, 0 },
	1704	{ &am29000_cpu_device::DIVIDU, 0 },
	1705	{ &am29000_cpu_device::CONVERT, 0 },
	1706	{ &am29000_cpu_device::SQRT, 0 },
	1707	{ &am29000_cpu_device::CLASS, 0 },
	1708	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1709	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
	1710	{ &am29000_cpu_device::ILLEGAL, IFLAG_ILLEGAL },
1722	1711	// FEQ
1723	1712	// DEQ
1724	1713	// TODO! etc

trunk/src/emu/cpu/am29000/am29000.c
r23915	r23916
17	17	#include "am29000.h"
18	18
19	19
	20	const device_type AM29000 = &device_creator<am29000_cpu_device>;
	21
	22
20	23	/***************************************************************************
21	24	CONSTANTS
22	25	***************************************************************************/
23	26
24		#define MAX_EXCEPTIONS (4)
25
26	27	#define PFLAG_FETCH_EN (1 << 0)
27	28	#define PFLAG_DECODE_EN (1 << 1)
28	29	#define PFLAG_EXECUTE_EN (1 << 2)
r23915	r23916
45	46	#define MMU_PROGRAM_ACCESS (0)
46	47	#define MMU_DATA_ACCESS (1)
47	48
48		#define FREEZE_MODE (am29000->cps & CPS_FZ)
49		#define SUPERVISOR_MODE (am29000->cps & CPS_SM)
50		#define USER_MODE (~am29000->cps & CPS_SM)
51		#define REGISTER_IS_PROTECTED(x) (am29000->rbp & (1 << ((x) >> 4)))
	49	#define FREEZE_MODE (m_cps & CPS_FZ)
	50	#define SUPERVISOR_MODE (m_cps & CPS_SM)
	51	#define USER_MODE (~m_cps & CPS_SM)
	52	#define REGISTER_IS_PROTECTED(x) (m_rbp & (1 << ((x) >> 4)))
52	53
53	54	#define INST_RB_FIELD(x) ((x) & 0xff)
54	55	#define INST_RA_FIELD(x) (((x) >> 8) & 0xff)
r23915	r23916
59	60	#define FIELD_RB 1
60	61	#define FIELD_RC 2
61	62
62		#define SIGNAL_EXCEPTION(x) (signal_exception(~~am29000,~~ x))
	63	#define SIGNAL_EXCEPTION(x) (signal_exception(x))
63	64
64	65
65		#define GET_ALU_FC ((am29000->alu >> ALU_FC_SHIFT) & ALU_FC_MASK)
66		#define GET_ALU_BP ((am29000->alu >> ALU_BP_SHIFT) & ALU_BP_MASK)
67		#define GET_CHC_CR ((am29000->chc >> CHC_CR_SHIFT) & CHC_CR_MASK)
	66	#define GET_ALU_FC ((m_alu >> ALU_FC_SHIFT) & ALU_FC_MASK)
	67	#define GET_ALU_BP ((m_alu >> ALU_BP_SHIFT) & ALU_BP_MASK)
	68	#define GET_CHC_CR ((m_chc >> CHC_CR_SHIFT) & CHC_CR_MASK)
68	69
69		#define SET_ALU_FC(x) do { am29000->alu &= ~(ALU_FC_MASK << ALU_FC_SHIFT); am29000->alu \|= ((x) & ALU_FC_MASK) << ALU_FC_SHIFT; } while(0)
70		#define SET_ALU_BP(x) do { am29000->alu &= ~(ALU_BP_MASK << ALU_BP_SHIFT); am29000->alu \|= ((x) & ALU_BP_MASK) << ALU_BP_SHIFT; } while(0)
71		#define SET_CHC_CR(x) do { am29000->chc &= ~(CHC_CR_MASK << CHC_CR_SHIFT); am29000->chc \|= ((x) & CHC_CR_MASK) << CHC_CR_SHIFT; } while(0)
	70	#define SET_ALU_FC(x) do { m_alu &= ~(ALU_FC_MASK << ALU_FC_SHIFT); m_alu \|= ((x) & ALU_FC_MASK) << ALU_FC_SHIFT; } while(0)
	71	#define SET_ALU_BP(x) do { m_alu &= ~(ALU_BP_MASK << ALU_BP_SHIFT); m_alu \|= ((x) & ALU_BP_MASK) << ALU_BP_SHIFT; } while(0)
	72	#define SET_CHC_CR(x) do { m_chc &= ~(CHC_CR_MASK << CHC_CR_SHIFT); m_chc \|= ((x) & CHC_CR_MASK) << CHC_CR_SHIFT; } while(0)
72	73
73	74
74	75	/***************************************************************************
75		ST~~RUC~~TURES ~~& TYP~~E~~DEF~~S
	76	STATE ACCESSORS
76	77	***************************************************************************/
77	78
78		struct am29000_state
	79	am29000_cpu_device::am29000_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	80	: cpu_device(mconfig, AM29000, "AMD Am29000", tag, owner, clock, "am29000", __FILE__)
	81	, m_program_config("program", ENDIANNESS_BIG, 32, 32, 0)
	82	, m_io_config("io", ENDIANNESS_BIG, 32, 32, 0)
	83	, m_data_config("data", ENDIANNESS_BIG, 32, 32, 0)
79	84	{
80		INT32 icount;
81		UINT32 pc;
	85	}
82	86
83		/* General purpose */
84		UINT32 r[256]; // TODO: There's only 192 implemented!
85	87
86		/* TLB */
87		UINT32 tlb[128];
	88	void am29000_cpu_device::device_start()
	89	{
	90	m_program = &space(AS_PROGRAM);
	91	m_direct = &m_program->direct();
	92	m_data = &space(AS_DATA);
	93	m_datadirect = &m_data->direct();
	94	m_io = &space(AS_IO);
	95	m_cfg = (PRL_AM29000 \| PRL_REV_D) << CFG_PRL_SHIFT;
88	96
89		/* Protected SPRs */
90		UINT32 vab;
91		UINT32 ops;
92		UINT32 cps;
93		UINT32 cfg;
94		UINT32 cha;
95		UINT32 chd;
96		UINT32 chc;
97		UINT32 rbp;
98		UINT32 tmc;
99		UINT32 tmr;
100		UINT32 pc0;
101		UINT32 pc1;
102		UINT32 pc2;
103		UINT32 mmu;
104		UINT32 lru;
	97	/* Register state for saving */
	98	save_item(NAME(m_icount));
	99	save_item(NAME(m_pc));
	100	save_item(NAME(m_r));
	101	save_item(NAME(m_tlb));
105	102
106		/* Unprotected SPRs */
107		UINT32 ipc;
108		UINT32 ipa;
109		UINT32 ipb;
110		UINT32 q;
111		UINT32 alu;
112		UINT32 fpe;
113		UINT32 inte;
114		UINT32 fps;
	103	save_item(NAME(m_vab));
	104	save_item(NAME(m_ops));
	105	save_item(NAME(m_cps));
	106	save_item(NAME(m_cfg));
	107	save_item(NAME(m_cha));
	108	save_item(NAME(m_chd));
	109	save_item(NAME(m_chc));
	110	save_item(NAME(m_rbp));
	111	save_item(NAME(m_tmc));
	112	save_item(NAME(m_tmr));
	113	save_item(NAME(m_pc0));
	114	save_item(NAME(m_pc1));
	115	save_item(NAME(m_pc2));
	116	save_item(NAME(m_mmu));
	117	save_item(NAME(m_lru));
115	118
116		/* Pipeline state */
117		UINT32 exceptions;
118		UINT32 exception_queue[MAX_EXCEPTIONS];
	119	save_item(NAME(m_ipc));
	120	save_item(NAME(m_ipa));
	121	save_item(NAME(m_ipb));
	122	save_item(NAME(m_q));
119	123
120		UINT8 irq_active;
121		UINT8 irq_lines;
	124	save_item(NAME(m_alu));
	125	save_item(NAME(m_fpe));
	126	save_item(NAME(m_inte));
	127	save_item(NAME(m_fps));
122	128
123		UINT32 exec_ir;
124		UINT32 next_ir;
	129	save_item(NAME(m_exceptions));
	130	save_item(NAME(m_exception_queue));
125	131
126		UINT32 pl_flags;
127		UINT32 next_pl_flags;
	132	save_item(NAME(m_irq_active));
	133	save_item(NAME(m_irq_lines));
128	134
129		UINT32 iret_pc;
	135	save_item(NAME(m_exec_ir));
	136	save_item(NAME(m_next_ir));
130	137
131		UINT32 exec_pc;
132		UINT32 next_pc;
	138	save_item(NAME(m_pl_flags));
	139	save_item(NAME(m_next_pl_flags));
133	140
134		address_space *program;
135		direct_read_data *direct;
136		address_space *data;
137		direct_read_data *datadirect;
138		address_space *io;
139		};
	141	save_item(NAME(m_iret_pc));
	142	save_item(NAME(m_exec_pc));
	143	save_item(NAME(m_next_pc));
140	144
	145	// Register state for debugger
	146	state_add( AM29000_PC, "PC", m_pc ).formatstr("%08X");
	147	state_add( AM29000_VAB, "VAB", m_vab ).formatstr("%08X");
	148	state_add( AM29000_OPS, "OPS", m_ops ).formatstr("%08X");
	149	state_add( AM29000_CPS, "CPS", m_cps ).formatstr("%08X");
	150	state_add( AM29000_CFG, "CFG", m_cfg ).formatstr("%08X");
	151	state_add( AM29000_CHA, "CHA", m_cha ).formatstr("%08X");
	152	state_add( AM29000_CHD, "CHD", m_chd ).formatstr("%08X");
	153	state_add( AM29000_CHC, "CHC", m_chc ).formatstr("%08X");
	154	state_add( AM29000_RBP, "RBP", m_rbp ).formatstr("%08X");
	155	state_add( AM29000_TMC, "TMC", m_tmc ).formatstr("%08X");
	156	state_add( AM29000_TMR, "TMR", m_tmr ).formatstr("%08X");
	157	state_add( AM29000_PC0, "PC0", m_pc0 ).formatstr("%08X");
	158	state_add( AM29000_PC1, "PC1", m_pc1 ).formatstr("%08X");
	159	state_add( AM29000_PC2, "PC2", m_pc2 ).formatstr("%08X");
	160	state_add( AM29000_MMU, "MMU", m_mmu ).formatstr("%08X");
	161	state_add( AM29000_LRU, "LRU", m_lru ).formatstr("%08X");
	162	state_add( AM29000_IPC, "IPC", m_ipc ).formatstr("%08X");
	163	state_add( AM29000_IPA, "IPA", m_ipa ).formatstr("%08X");
	164	state_add( AM29000_IPB, "IPB", m_ipb ).formatstr("%08X");
	165	state_add( AM29000_Q, "Q", m_q ).formatstr("%08X");
	166	state_add( AM29000_ALU, "ALU", m_alu ).formatstr("%08X");
	167	// state_add( AM29000_BP, "BP", GET_ALU_BP).formatstr("%08X");
	168	// state_add( AM29000_FC, "FC", GET_ALU_FC).formatstr("%08X");
	169	// state_add( AM29000_CR, "CR", GET_CHC_CR).formatstr("%08X");
	170	state_add( AM29000_FPE, "FPE", m_fpe ).formatstr("%08X");
	171	state_add( AM29000_INTE, "INTE", m_inte ).formatstr("%08X");
	172	state_add( AM29000_FPS, "FPS", m_fps ).formatstr("%08X");
	173	state_add( AM29000_R1, "R1", m_r[1] ).formatstr("%08X");
	174	state_add( AM29000_R64, "R64", m_r[64] ).formatstr("%08X");
	175	state_add( AM29000_R65, "R65", m_r[65] ).formatstr("%08X");
	176	state_add( AM29000_R66, "R66", m_r[66] ).formatstr("%08X");
	177	state_add( AM29000_R67, "R67", m_r[67] ).formatstr("%08X");
	178	state_add( AM29000_R68, "R68", m_r[68] ).formatstr("%08X");
	179	state_add( AM29000_R69, "R69", m_r[69] ).formatstr("%08X");
	180	state_add( AM29000_R70, "R70", m_r[70] ).formatstr("%08X");
	181	state_add( AM29000_R71, "R71", m_r[71] ).formatstr("%08X");
	182	state_add( AM29000_R72, "R72", m_r[72] ).formatstr("%08X");
	183	state_add( AM29000_R73, "R73", m_r[73] ).formatstr("%08X");
	184	state_add( AM29000_R74, "R74", m_r[74] ).formatstr("%08X");
	185	state_add( AM29000_R75, "R75", m_r[75] ).formatstr("%08X");
	186	state_add( AM29000_R76, "R76", m_r[76] ).formatstr("%08X");
	187	state_add( AM29000_R77, "R77", m_r[77] ).formatstr("%08X");
	188	state_add( AM29000_R78, "R78", m_r[78] ).formatstr("%08X");
	189	state_add( AM29000_R79, "R79", m_r[79] ).formatstr("%08X");
	190	state_add( AM29000_R80, "R80", m_r[80] ).formatstr("%08X");
	191	state_add( AM29000_R81, "R81", m_r[81] ).formatstr("%08X");
	192	state_add( AM29000_R82, "R82", m_r[82] ).formatstr("%08X");
	193	state_add( AM29000_R83, "R83", m_r[83] ).formatstr("%08X");
	194	state_add( AM29000_R84, "R84", m_r[84] ).formatstr("%08X");
	195	state_add( AM29000_R85, "R85", m_r[85] ).formatstr("%08X");
	196	state_add( AM29000_R86, "R86", m_r[86] ).formatstr("%08X");
	197	state_add( AM29000_R87, "R87", m_r[87] ).formatstr("%08X");
	198	state_add( AM29000_R88, "R88", m_r[88] ).formatstr("%08X");
	199	state_add( AM29000_R89, "R89", m_r[89] ).formatstr("%08X");
	200	state_add( AM29000_R90, "R90", m_r[90] ).formatstr("%08X");
	201	state_add( AM29000_R91, "R91", m_r[91] ).formatstr("%08X");
	202	state_add( AM29000_R92, "R92", m_r[92] ).formatstr("%08X");
	203	state_add( AM29000_R93, "R93", m_r[93] ).formatstr("%08X");
	204	state_add( AM29000_R94, "R94", m_r[94] ).formatstr("%08X");
	205	state_add( AM29000_R95, "R95", m_r[95] ).formatstr("%08X");
	206	state_add( AM29000_R96, "R96", m_r[96] ).formatstr("%08X");
	207	state_add( AM29000_R97, "R97", m_r[97] ).formatstr("%08X");
	208	state_add( AM29000_R98, "R98", m_r[98] ).formatstr("%08X");
	209	state_add( AM29000_R99, "R99", m_r[99] ).formatstr("%08X");
	210	state_add( AM29000_R100, "R100", m_r[100] ).formatstr("%08X");
	211	state_add( AM29000_R101, "R101", m_r[101] ).formatstr("%08X");
	212	state_add( AM29000_R102, "R102", m_r[102] ).formatstr("%08X");
	213	state_add( AM29000_R103, "R103", m_r[103] ).formatstr("%08X");
	214	state_add( AM29000_R104, "R104", m_r[104] ).formatstr("%08X");
	215	state_add( AM29000_R105, "R105", m_r[105] ).formatstr("%08X");
	216	state_add( AM29000_R106, "R106", m_r[106] ).formatstr("%08X");
	217	state_add( AM29000_R107, "R107", m_r[107] ).formatstr("%08X");
	218	state_add( AM29000_R108, "R108", m_r[108] ).formatstr("%08X");
	219	state_add( AM29000_R109, "R109", m_r[109] ).formatstr("%08X");
	220	state_add( AM29000_R110, "R110", m_r[110] ).formatstr("%08X");
	221	state_add( AM29000_R111, "R111", m_r[111] ).formatstr("%08X");
	222	state_add( AM29000_R112, "R112", m_r[112] ).formatstr("%08X");
	223	state_add( AM29000_R113, "R113", m_r[113] ).formatstr("%08X");
	224	state_add( AM29000_R114, "R114", m_r[114] ).formatstr("%08X");
	225	state_add( AM29000_R115, "R115", m_r[115] ).formatstr("%08X");
	226	state_add( AM29000_R116, "R116", m_r[116] ).formatstr("%08X");
	227	state_add( AM29000_R117, "R117", m_r[117] ).formatstr("%08X");
	228	state_add( AM29000_R118, "R118", m_r[118] ).formatstr("%08X");
	229	state_add( AM29000_R119, "R119", m_r[119] ).formatstr("%08X");
	230	state_add( AM29000_R120, "R120", m_r[120] ).formatstr("%08X");
	231	state_add( AM29000_R121, "R121", m_r[121] ).formatstr("%08X");
	232	state_add( AM29000_R122, "R122", m_r[122] ).formatstr("%08X");
	233	state_add( AM29000_R123, "R123", m_r[123] ).formatstr("%08X");
	234	state_add( AM29000_R124, "R124", m_r[124] ).formatstr("%08X");
	235	state_add( AM29000_R125, "R125", m_r[125] ).formatstr("%08X");
	236	state_add( AM29000_R126, "R126", m_r[126] ).formatstr("%08X");
	237	state_add( AM29000_R127, "R127", m_r[127] ).formatstr("%08X");
	238	state_add( AM29000_R128, "R128", m_r[128] ).formatstr("%08X");
	239	state_add( AM29000_R129, "R129", m_r[129] ).formatstr("%08X");
	240	state_add( AM29000_R130, "R130", m_r[130] ).formatstr("%08X");
	241	state_add( AM29000_R131, "R131", m_r[131] ).formatstr("%08X");
	242	state_add( AM29000_R132, "R132", m_r[132] ).formatstr("%08X");
	243	state_add( AM29000_R133, "R133", m_r[133] ).formatstr("%08X");
	244	state_add( AM29000_R134, "R134", m_r[134] ).formatstr("%08X");
	245	state_add( AM29000_R135, "R135", m_r[135] ).formatstr("%08X");
	246	state_add( AM29000_R136, "R136", m_r[136] ).formatstr("%08X");
	247	state_add( AM29000_R137, "R137", m_r[137] ).formatstr("%08X");
	248	state_add( AM29000_R138, "R138", m_r[138] ).formatstr("%08X");
	249	state_add( AM29000_R139, "R139", m_r[139] ).formatstr("%08X");
	250	state_add( AM29000_R140, "R140", m_r[140] ).formatstr("%08X");
	251	state_add( AM29000_R141, "R141", m_r[141] ).formatstr("%08X");
	252	state_add( AM29000_R142, "R142", m_r[142] ).formatstr("%08X");
	253	state_add( AM29000_R143, "R143", m_r[143] ).formatstr("%08X");
	254	state_add( AM29000_R144, "R144", m_r[144] ).formatstr("%08X");
	255	state_add( AM29000_R145, "R145", m_r[145] ).formatstr("%08X");
	256	state_add( AM29000_R146, "R146", m_r[146] ).formatstr("%08X");
	257	state_add( AM29000_R147, "R147", m_r[147] ).formatstr("%08X");
	258	state_add( AM29000_R148, "R148", m_r[148] ).formatstr("%08X");
	259	state_add( AM29000_R149, "R149", m_r[149] ).formatstr("%08X");
	260	state_add( AM29000_R150, "R150", m_r[150] ).formatstr("%08X");
	261	state_add( AM29000_R151, "R151", m_r[151] ).formatstr("%08X");
	262	state_add( AM29000_R152, "R152", m_r[152] ).formatstr("%08X");
	263	state_add( AM29000_R153, "R153", m_r[153] ).formatstr("%08X");
	264	state_add( AM29000_R154, "R154", m_r[154] ).formatstr("%08X");
	265	state_add( AM29000_R155, "R155", m_r[155] ).formatstr("%08X");
	266	state_add( AM29000_R156, "R156", m_r[156] ).formatstr("%08X");
	267	state_add( AM29000_R157, "R157", m_r[157] ).formatstr("%08X");
	268	state_add( AM29000_R158, "R158", m_r[158] ).formatstr("%08X");
	269	state_add( AM29000_R159, "R159", m_r[159] ).formatstr("%08X");
	270	state_add( AM29000_R160, "R160", m_r[160] ).formatstr("%08X");
	271	state_add( AM29000_R161, "R161", m_r[161] ).formatstr("%08X");
	272	state_add( AM29000_R162, "R162", m_r[162] ).formatstr("%08X");
	273	state_add( AM29000_R163, "R163", m_r[163] ).formatstr("%08X");
	274	state_add( AM29000_R164, "R164", m_r[164] ).formatstr("%08X");
	275	state_add( AM29000_R165, "R165", m_r[165] ).formatstr("%08X");
	276	state_add( AM29000_R166, "R166", m_r[166] ).formatstr("%08X");
	277	state_add( AM29000_R167, "R167", m_r[167] ).formatstr("%08X");
	278	state_add( AM29000_R168, "R168", m_r[168] ).formatstr("%08X");
	279	state_add( AM29000_R169, "R169", m_r[169] ).formatstr("%08X");
	280	state_add( AM29000_R170, "R170", m_r[170] ).formatstr("%08X");
	281	state_add( AM29000_R171, "R171", m_r[171] ).formatstr("%08X");
	282	state_add( AM29000_R172, "R172", m_r[172] ).formatstr("%08X");
	283	state_add( AM29000_R173, "R173", m_r[173] ).formatstr("%08X");
	284	state_add( AM29000_R174, "R174", m_r[174] ).formatstr("%08X");
	285	state_add( AM29000_R175, "R175", m_r[175] ).formatstr("%08X");
	286	state_add( AM29000_R176, "R176", m_r[176] ).formatstr("%08X");
	287	state_add( AM29000_R177, "R177", m_r[177] ).formatstr("%08X");
	288	state_add( AM29000_R178, "R178", m_r[178] ).formatstr("%08X");
	289	state_add( AM29000_R179, "R179", m_r[179] ).formatstr("%08X");
	290	state_add( AM29000_R180, "R180", m_r[180] ).formatstr("%08X");
	291	state_add( AM29000_R181, "R181", m_r[181] ).formatstr("%08X");
	292	state_add( AM29000_R182, "R182", m_r[182] ).formatstr("%08X");
	293	state_add( AM29000_R183, "R183", m_r[183] ).formatstr("%08X");
	294	state_add( AM29000_R184, "R184", m_r[184] ).formatstr("%08X");
	295	state_add( AM29000_R185, "R185", m_r[185] ).formatstr("%08X");
	296	state_add( AM29000_R186, "R186", m_r[186] ).formatstr("%08X");
	297	state_add( AM29000_R187, "R187", m_r[187] ).formatstr("%08X");
	298	state_add( AM29000_R188, "R188", m_r[188] ).formatstr("%08X");
	299	state_add( AM29000_R189, "R189", m_r[189] ).formatstr("%08X");
	300	state_add( AM29000_R190, "R190", m_r[190] ).formatstr("%08X");
	301	state_add( AM29000_R191, "R191", m_r[191] ).formatstr("%08X");
	302	state_add( AM29000_R192, "R192", m_r[192] ).formatstr("%08X");
	303	state_add( AM29000_R193, "R193", m_r[193] ).formatstr("%08X");
	304	state_add( AM29000_R194, "R194", m_r[194] ).formatstr("%08X");
	305	state_add( AM29000_R195, "R195", m_r[195] ).formatstr("%08X");
	306	state_add( AM29000_R196, "R196", m_r[196] ).formatstr("%08X");
	307	state_add( AM29000_R197, "R197", m_r[197] ).formatstr("%08X");
	308	state_add( AM29000_R198, "R198", m_r[198] ).formatstr("%08X");
	309	state_add( AM29000_R199, "R199", m_r[199] ).formatstr("%08X");
	310	state_add( AM29000_R200, "R200", m_r[200] ).formatstr("%08X");
	311	state_add( AM29000_R201, "R201", m_r[201] ).formatstr("%08X");
	312	state_add( AM29000_R202, "R202", m_r[202] ).formatstr("%08X");
	313	state_add( AM29000_R203, "R203", m_r[203] ).formatstr("%08X");
	314	state_add( AM29000_R204, "R204", m_r[204] ).formatstr("%08X");
	315	state_add( AM29000_R205, "R205", m_r[205] ).formatstr("%08X");
	316	state_add( AM29000_R206, "R206", m_r[206] ).formatstr("%08X");
	317	state_add( AM29000_R207, "R207", m_r[207] ).formatstr("%08X");
	318	state_add( AM29000_R208, "R208", m_r[208] ).formatstr("%08X");
	319	state_add( AM29000_R209, "R209", m_r[209] ).formatstr("%08X");
	320	state_add( AM29000_R210, "R210", m_r[210] ).formatstr("%08X");
	321	state_add( AM29000_R211, "R211", m_r[211] ).formatstr("%08X");
	322	state_add( AM29000_R212, "R212", m_r[212] ).formatstr("%08X");
	323	state_add( AM29000_R213, "R213", m_r[213] ).formatstr("%08X");
	324	state_add( AM29000_R214, "R214", m_r[214] ).formatstr("%08X");
	325	state_add( AM29000_R215, "R215", m_r[215] ).formatstr("%08X");
	326	state_add( AM29000_R216, "R216", m_r[216] ).formatstr("%08X");
	327	state_add( AM29000_R217, "R217", m_r[217] ).formatstr("%08X");
	328	state_add( AM29000_R218, "R218", m_r[218] ).formatstr("%08X");
	329	state_add( AM29000_R219, "R219", m_r[219] ).formatstr("%08X");
	330	state_add( AM29000_R220, "R220", m_r[220] ).formatstr("%08X");
	331	state_add( AM29000_R221, "R221", m_r[221] ).formatstr("%08X");
	332	state_add( AM29000_R222, "R222", m_r[222] ).formatstr("%08X");
	333	state_add( AM29000_R223, "R223", m_r[223] ).formatstr("%08X");
	334	state_add( AM29000_R224, "R224", m_r[224] ).formatstr("%08X");
	335	state_add( AM29000_R225, "R225", m_r[225] ).formatstr("%08X");
	336	state_add( AM29000_R226, "R226", m_r[226] ).formatstr("%08X");
	337	state_add( AM29000_R227, "R227", m_r[227] ).formatstr("%08X");
	338	state_add( AM29000_R228, "R228", m_r[228] ).formatstr("%08X");
	339	state_add( AM29000_R229, "R229", m_r[229] ).formatstr("%08X");
	340	state_add( AM29000_R230, "R230", m_r[230] ).formatstr("%08X");
	341	state_add( AM29000_R231, "R231", m_r[231] ).formatstr("%08X");
	342	state_add( AM29000_R232, "R232", m_r[232] ).formatstr("%08X");
	343	state_add( AM29000_R233, "R233", m_r[233] ).formatstr("%08X");
	344	state_add( AM29000_R234, "R234", m_r[234] ).formatstr("%08X");
	345	state_add( AM29000_R235, "R235", m_r[235] ).formatstr("%08X");
	346	state_add( AM29000_R236, "R236", m_r[236] ).formatstr("%08X");
	347	state_add( AM29000_R237, "R237", m_r[237] ).formatstr("%08X");
	348	state_add( AM29000_R238, "R238", m_r[238] ).formatstr("%08X");
	349	state_add( AM29000_R239, "R239", m_r[239] ).formatstr("%08X");
	350	state_add( AM29000_R240, "R240", m_r[240] ).formatstr("%08X");
	351	state_add( AM29000_R241, "R241", m_r[241] ).formatstr("%08X");
	352	state_add( AM29000_R242, "R242", m_r[242] ).formatstr("%08X");
	353	state_add( AM29000_R243, "R243", m_r[243] ).formatstr("%08X");
	354	state_add( AM29000_R244, "R244", m_r[244] ).formatstr("%08X");
	355	state_add( AM29000_R245, "R245", m_r[245] ).formatstr("%08X");
	356	state_add( AM29000_R246, "R246", m_r[246] ).formatstr("%08X");
	357	state_add( AM29000_R247, "R247", m_r[247] ).formatstr("%08X");
	358	state_add( AM29000_R248, "R248", m_r[248] ).formatstr("%08X");
	359	state_add( AM29000_R249, "R249", m_r[249] ).formatstr("%08X");
	360	state_add( AM29000_R250, "R250", m_r[250] ).formatstr("%08X");
	361	state_add( AM29000_R251, "R251", m_r[251] ).formatstr("%08X");
	362	state_add( AM29000_R252, "R252", m_r[252] ).formatstr("%08X");
	363	state_add( AM29000_R253, "R253", m_r[253] ).formatstr("%08X");
	364	state_add( AM29000_R254, "R254", m_r[254] ).formatstr("%08X");
	365	state_add( AM29000_R255, "R255", m_r[255] ).formatstr("%08X");
141	366
142		/***************************************************************************
143		STATE ACCESSORS
144		***************************************************************************/
	367	state_add(STATE_GENPC, "curpc", m_pc).formatstr("%08X").noshow();
	368	state_add(STATE_GENFLAGS, "GENFLAGS", m_alu).formatstr("%13s").noshow();
145	369
146		INLINE am29000_state get_safe_token(device_t device)
147		{
148		assert(device != NULL);
149		assert(device->type() == AM29000);
150		return (am29000_state )downcast<legacy_cpu_device >(device)->token();
	370	m_icountptr = &m_icount;
151	371	}
152	372
153		static CPU_INIT( am29000 )
154		{
155		am29000_state *am29000 = get_safe_token(device);
156	373
157		am29000->program = &device->space(AS_PROGRAM);
158		am29000->direct = &am29000->program->direct();
159		am29000->data = &device->space(AS_DATA);
160		am29000->datadirect = &am29000->data->direct();
161		am29000->io = &device->space(AS_IO);
162		am29000->cfg = (PRL_AM29000 \| PRL_REV_D) << CFG_PRL_SHIFT;
163
164		/* Register state for saving */
165		device->save_item(NAME(am29000->icount));
166		device->save_item(NAME(am29000->pc));
167		device->save_item(NAME(am29000->r));
168		device->save_item(NAME(am29000->tlb));
169
170		device->save_item(NAME(am29000->vab));
171		device->save_item(NAME(am29000->ops));
172		device->save_item(NAME(am29000->cps));
173		device->save_item(NAME(am29000->cfg));
174		device->save_item(NAME(am29000->cha));
175		device->save_item(NAME(am29000->chd));
176		device->save_item(NAME(am29000->chc));
177		device->save_item(NAME(am29000->rbp));
178		device->save_item(NAME(am29000->tmc));
179		device->save_item(NAME(am29000->tmr));
180		device->save_item(NAME(am29000->pc0));
181		device->save_item(NAME(am29000->pc1));
182		device->save_item(NAME(am29000->pc2));
183		device->save_item(NAME(am29000->mmu));
184		device->save_item(NAME(am29000->lru));
185
186		device->save_item(NAME(am29000->ipc));
187		device->save_item(NAME(am29000->ipa));
188		device->save_item(NAME(am29000->ipb));
189		device->save_item(NAME(am29000->q));
190
191		device->save_item(NAME(am29000->alu));
192		device->save_item(NAME(am29000->fpe));
193		device->save_item(NAME(am29000->inte));
194		device->save_item(NAME(am29000->fps));
195
196		device->save_item(NAME(am29000->exceptions));
197		device->save_item(NAME(am29000->exception_queue));
198
199		device->save_item(NAME(am29000->irq_active));
200		device->save_item(NAME(am29000->irq_lines));
201
202		device->save_item(NAME(am29000->exec_ir));
203		device->save_item(NAME(am29000->next_ir));
204
205		device->save_item(NAME(am29000->pl_flags));
206		device->save_item(NAME(am29000->next_pl_flags));
207
208		device->save_item(NAME(am29000->iret_pc));
209		device->save_item(NAME(am29000->exec_pc));
210		device->save_item(NAME(am29000->next_pc));
	374	void am29000_cpu_device::state_string_export(const device_state_entry &entry, astring &string)
	375	{
	376	switch (entry.index())
	377	{
	378	case STATE_GENFLAGS:
	379	string.printf("%c%c%c%c%c%c%c%c%c\|%3d", m_alu & ALU_V ? 'V' : '.',
	380	m_alu & ALU_Z ? 'Z' : '.',
	381	m_alu & ALU_N ? 'N' : '.',
	382	m_alu & ALU_C ? 'C' : '.',
	383	m_cps & CPS_IP ? 'I' : '.',
	384	m_cps & CPS_FZ ? 'F' : '.',
	385	m_cps & CPS_SM ? 'S' : 'U',
	386	m_cps & CPS_DI ? 'I' : '.',
	387	m_cps & CPS_DA ? 'D' : '.',
	388	(m_r[1] >> 2) & 0x7f);
	389	break;
	390	}
211	391	}
212	392
213		static CPU_RESET( am29000 )
	393
	394	void am29000_cpu_device::device_reset()
214	395	{
215		am29000_state *am29000 = get_safe_token(device);
	396	memset( m_r, 0, sizeof(m_r) );
	397	memset( m_tlb, 0, sizeof(m_tlb) );
	398	m_vab = 0;
	399	m_ops = 0;
	400	m_cha = 0;
	401	m_chd = 0;
	402	m_chc = 0;
	403	m_rbp = 0;
	404	m_tmc = 0;
	405	m_tmr = 0;
	406	m_pc0 = 0;
	407	m_pc1 = 0;
	408	m_pc2 = 0;
	409	m_mmu = 0;
	410	m_lru = 0;
	411	m_ipc = 0;
	412	m_ipa = 0;
	413	m_ipb = 0;
	414	m_q = 0;
	415	m_alu = 0;
	416	m_fpe = 0;
	417	m_inte = 0;
	418	m_fps = 0;
	419	memset( m_exception_queue, 0, sizeof( m_exception_queue) );;
	420	m_irq_active = 0;
	421	m_irq_lines = 0;
	422	m_exec_ir = 0;
	423	m_next_ir = 0;
	424	m_pl_flags = 0;
	425	m_iret_pc = 0;
	426	m_exec_pc = 0;
	427	m_next_pc = 0;
216	428
217		am29000->cps = CPS_FZ \| CPS_RE \| CPS_PD \| CPS_PI \| CPS_SM \| CPS_DI \| CPS_DA;
218		am29000->cfg &= ~(CFG_DW \| CFG_CD);
219		am29000->chc &= ~CHC_CV;
	429	m_cps = CPS_FZ \| CPS_RE \| CPS_PD \| CPS_PI \| CPS_SM \| CPS_DI \| CPS_DA;
	430	m_cfg &= ~(CFG_DW \| CFG_CD);
	431	m_chc &= ~CHC_CV;
220	432
221		am29000->pc = 0;
222		am29000->next_pl_flags = 0;
223		am29000->exceptions = 0;
224		am29000->irq_lines = 0;
	433	m_pc = 0;
	434	m_next_pl_flags = 0;
	435	m_exceptions = 0;
	436	m_irq_lines = 0;
225	437	}
226	438
227	439
228		~~stat~~ic ~~CPU_EXIT(~~ am29000 )
	440	void am29000_cpu_device::signal_exception(UINT32 type)
229	441	{
	442	m_exception_queue[m_exceptions++] = type;
230	443	}
231	444
232	445
233		~~static~~ void ~~sign~~a~~l_exception(a~~m29000_state *a~~m29000, UINT32 typ~~e)
	446	void am29000_cpu_device::external_irq_check()
234	447	{
235		am29000->exception_queue[am29000->exceptions++] = type;
236		}
237
238		static void external_irq_check(am29000_state *am29000)
239		{
240		int mask = (am29000->cps >> CPS_IM_SHIFT) & CPS_IM_MASK;
241		int irq_en = !(am29000->cps & CPS_DI) && !(am29000->cps & CPS_DA);
	448	int mask = (m_cps >> CPS_IM_SHIFT) & CPS_IM_MASK;
	449	int irq_en = !(m_cps & CPS_DI) && !(m_cps & CPS_DA);
242	450	int i;
243	451
244	452	/* Clear interrupt pending bit to begin with */
245		am~~29000->~~cps &= ~CPS_IP;
	453	m_cps &= ~CPS_IP;
246	454
247	455	for (i = 0; i < 4; ++i)
248	456	{
249		if (!(am~~29000->~~irq_active & (1 << i)) && (am~~29000->~~irq_lines & (1 << i)))
	457	if (!(m_irq_active & (1 << i)) && (m_irq_lines & (1 << i)))
250	458	{
251	459	if (irq_en)
252	460	{
253	461	if (i <= mask)
254	462	{
255		am29000->irq_active \|= (1 << i);
256		SIGNAL_EXCEPTION(EXCEPTION_INTR0 + i);
257		am29000->pl_flags \|= PFLAG_IRQ;
	463	m_irq_active \|= (1 << i);
	464	signal_exception(EXCEPTION_INTR0 + i);
	465	m_pl_flags \|= PFLAG_IRQ;
258	466	return;
259	467	}
260	468	}
261	469	/* Set interrupt pending bit if interrupt was disabled */
262		am~~29000->~~cps \|= CPS_IP;
	470	m_cps \|= CPS_IP;
263	471	}
264	472	else
265		am~~29000->~~irq_active &= ~(1 << i);
	473	m_irq_active &= ~(1 << i);
266	474	}
267	475	}
268	476
269		static UINT32 read_program_word(am29000_state *state, UINT32 address)
	477
	478	UINT32 am29000_cpu_device::read_program_word(UINT32 address)
270	479	{
271	480	/* TODO: ROM enable? */
272		if (state->cps & CPS_PI \|\| state->cps & CPS_RE)
273		return state->direct->read_decrypted_dword(address);
	481	if (m_cps & CPS_PI \|\| m_cps & CPS_RE)
	482	return m_direct->read_decrypted_dword(address);
274	483	else
275	484	{
276	485	fatalerror("Am29000 instruction MMU translation enabled!\n");
r23915	r23916
282	491	HELPER FUNCTIONS
283	492	***************************************************************************/
284	493
285		~~INLINE~~ UINT32 get_abs_reg(~~am29000_state *am29000,~~ UINT8 r, UINT32 iptr)
	494	UINT32 am29000_cpu_device::get_abs_reg(UINT8 r, UINT32 iptr)
286	495	{
287	496	if (r & 0x80)
288	497	{
289	498	/* Stack pointer access */
290		r = ((am~~29000->~~r[1] >> 2) & 0x7f) + (r & 0x7f);
	499	r = ((m_r[1] >> 2) & 0x7f) + (r & 0x7f);
291	500	r \|= 0x80;
292	501	}
293	502	else if (r == 0)
r23915	r23916
314	523	PIPELINE STAGES
315	524	***************************************************************************/
316	525
317		~~INLINE~~ void fetch_decode(~~am29000_state *am29000~~)
	526	void am29000_cpu_device::fetch_decode()
318	527	{
319	528	UINT32 inst;
320		op_inf~~o op~~;
	529	UINT32 op_flags;
321	530
322		inst = read_program_word(am29000, am29000->pc);
323		am29000->next_ir = inst;
	531	inst = read_program_word(m_pc);
	532	m_next_ir = inst;
324	533
325		op = op_table[inst >> 24];
	534	op_flags = op_table[inst >> 24].flags;
326	535
327	536	/* Illegal instruction */
328	537	/* TODO: This should be checked at this point */
329	538	#if 0
330		if (op.flags & IFLAG_ILLEGAL)
	539	if (op_flags & IFLAG_ILLEGAL)
331	540	{
332		fatalerror("Illegal instruction: %x PC:%x PC0:%x PC1:%x\n", inst, am~~29000->~~pc, am~~29000->~~pc0, am~~29000->~~pc1);
	541	fatalerror("Illegal instruction: %x PC:%x PC0:%x PC1:%x\n", inst, m_pc, m_pc0, m_pc1);
333	542	SIGNAL_EXCEPTION(EXCEPTION_ILLEGAL_OPCODE);
334	543	return;
335	544	}
r23915	r23916
338	547	/* Privledge violations */
339	548	if (USER_MODE)
340	549	{
341		if ((op.flags & IFLAG_SUPERVISOR_ONLY))
	550	if ((op_flags & IFLAG_SUPERVISOR_ONLY))
342	551	{
343		~~SIGNAL~~_~~EXCEPTION~~(EXCEPTION_PROTECTION_VIOLATION);
	552	signal_exception(EXCEPTION_PROTECTION_VIOLATION);
344	553	return;
345	554	}
346	555
347		if ((op.flags & IFLAG_SPR_ACCESS))
	556	if ((op_flags & IFLAG_SPR_ACCESS))
348	557	{
349	558	/* TODO: Is this the right place to check this? */
350	559	if (INST_SA_FIELD(inst) < 128)
r23915	r23916
355	564	}
356	565
357	566	/* Register bank protection */
358		if ((op.flags & IFLAG_RA_PRESENT) && REGISTER_IS_PROTECTED(INST_RA_FIELD(inst)))
	567	if ((op_flags & IFLAG_RA_PRESENT) && REGISTER_IS_PROTECTED(INST_RA_FIELD(inst)))
359	568	{
360	569	SIGNAL_EXCEPTION(EXCEPTION_PROTECTION_VIOLATION);
361	570	return;
362	571	}
363	572
364		if ((op.flags & IFLAG_RB_PRESENT) && REGISTER_IS_PROTECTED(INST_RB_FIELD(inst)))
	573	if ((op_flags & IFLAG_RB_PRESENT) && REGISTER_IS_PROTECTED(INST_RB_FIELD(inst)))
365	574	{
366	575	SIGNAL_EXCEPTION(EXCEPTION_PROTECTION_VIOLATION);
367	576	return;
368	577	}
369	578
370		if ((op.flags & IFLAG_RC_PRESENT) && REGISTER_IS_PROTECTED(INST_RC_FIELD(inst)))
	579	if ((op_flags & IFLAG_RC_PRESENT) && REGISTER_IS_PROTECTED(INST_RC_FIELD(inst)))
371	580	{
372	581	SIGNAL_EXCEPTION(EXCEPTION_PROTECTION_VIOLATION);
373	582	return;
374	583	}
375	584	}
376	585
377		if (am29000->pl_flags & PFLAG_IRET)
378		am29000->next_pc = am29000->iret_pc;
	586	if (m_pl_flags & PFLAG_IRET)
	587	m_next_pc = m_iret_pc;
379	588	else
380		am~~29000->~~next_pc += 4;
	589	m_next_pc += 4;
381	590	}
382	591
383	592	/***************************************************************************
384	593	CORE EXECUTION LOOP
385	594	***************************************************************************/
386	595
387		~~stat~~ic ~~CPU_EXECUTE(~~ am29000 )
	596	void am29000_cpu_device::execute_run()
388	597	{
389		am29000_state *am29000 = get_safe_token(device);
390		UINT32 call_debugger = (device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0;
	598	UINT32 call_debugger = (machine().debug_flags & DEBUG_FLAG_ENABLED) != 0;
391	599
392		external_irq_check(~~am29000~~);
	600	external_irq_check();
393	601
394	602	do
395	603	{
396		am~~29000->~~next_pl_flags = PFLAG_EXECUTE_EN;
	604	m_next_pl_flags = PFLAG_EXECUTE_EN;
397	605
398	606	if (!FREEZE_MODE)
399	607	{
400		am29000->pc1 = am29000->pc0;
401		am29000->pc0 = am29000->pc;
	608	m_pc1 = m_pc0;
	609	m_pc0 = m_pc;
402	610	}
403	611
404		if (am~~29000->~~exceptions)
	612	if (m_exceptions)
405	613	{
406		am29000->ops = am29000->cps;
407		am29000->cps &= ~(CPS_TE \| CPS_TP \| CPS_TU \| CPS_FZ \| CPS_LK \| CPS_WM \| CPS_PD \| CPS_PI \| CPS_SM \| CPS_DI \| CPS_DA);
408		am29000->cps \|= (CPS_FZ \| CPS_PD \| CPS_PI \| CPS_SM \| CPS_DI \| CPS_DA);
	614	m_ops = m_cps;
	615	m_cps &= ~(CPS_TE \| CPS_TP \| CPS_TU \| CPS_FZ \| CPS_LK \| CPS_WM \| CPS_PD \| CPS_PI \| CPS_SM \| CPS_DI \| CPS_DA);
	616	m_cps \|= (CPS_FZ \| CPS_PD \| CPS_PI \| CPS_SM \| CPS_DI \| CPS_DA);
409	617
410		if (am~~29000->~~pl_flags & PFLAG_IRET)
	618	if (m_pl_flags & PFLAG_IRET)
411	619	{
412		am29000->pc0 = am29000->iret_pc;
413		am29000->pc1 = am29000->next_pc;
	620	m_pc0 = m_iret_pc;
	621	m_pc1 = m_next_pc;
414	622	}
415	623
416	624
417		if (am~~29000->~~cfg & CFG_VF)
	625	if (m_cfg & CFG_VF)
418	626	{
419		UINT32 vaddr = am29000->vab \| am29000->exception_queue[0] * 4;
420		UINT32 vect = am29000->datadirect->read_decrypted_dword(vaddr);
	627	UINT32 vaddr = m_vab \| m_exception_queue[0] * 4;
	628	UINT32 vect = m_datadirect->read_decrypted_dword(vaddr);
421	629
422		am29000->pc = vect & ~3;
423		am29000->next_pc = am29000->pc;
	630	m_pc = vect & ~3;
	631	m_next_pc = m_pc;
424	632	}
425	633	else
426	634	{
427	635	fatalerror("Am29000: Non vectored interrupt fetch!\n");
428	636	}
429	637
430		am29000->exceptions = 0;
431		am29000->pl_flags = 0;
	638	m_exceptions = 0;
	639	m_pl_flags = 0;
432	640	}
433	641
434	642	if (call_debugger)
435		debugger_instruction_hook(~~dev~~ice, am~~29000->~~pc);
	643	debugger_instruction_hook(this, m_pc);
436	644
437		fetch_decode(~~am29000~~);
	645	fetch_decode();
438	646
439		if (am~~29000->~~pl_flags & PFLAG_EXECUTE_EN)
	647	if (m_pl_flags & PFLAG_EXECUTE_EN)
440	648	{
441	649	if (!FREEZE_MODE)
442		am~~29000->~~pc2 = am~~29000->~~pc1;
	650	m_pc2 = m_pc1;
443	651
444		op_table[am~~29000->~~exec_ir >> 24].opcode(~~am29000~~);
	652	(this->*op_table[m_exec_ir >> 24].opcode)();
445	653	}
446	654
447		am29000->exec_ir = am29000->next_ir;
448		am29000->pl_flags = am29000->next_pl_flags;
449		am29000->exec_pc = am29000->pc;
450		am29000->pc = am29000->next_pc;
451		} while (--am29000->icount > 0);
	655	m_exec_ir = m_next_ir;
	656	m_pl_flags = m_next_pl_flags;
	657	m_exec_pc = m_pc;
	658	m_pc = m_next_pc;
	659	} while (--m_icount > 0);
452	660	}
453	661
454		static void set_irq_line(am29000_state *am29000, int line, int state)
	662
	663	void am29000_cpu_device::execute_set_input(int inputnum, int state)
455	664	{
456	665	if (state)
457		am~~29000->~~irq_lines \|= (1 << line);
	666	m_irq_lines \|= (1 << inputnum);
458	667	else
459		am~~29000->~~irq_lines &= ~(1 << line);
	668	m_irq_lines &= ~(1 << inputnum);
460	669
461	670	// TODO : CHECK IRQs
462	671	}
463	672
464		/***************************************************************************
465		DISASSEMBLY HOOK
466		***************************************************************************/
467	673
468		extern CPU_DISASSEMBLE( am29000 );
469
470
471		static CPU_SET_INFO( am29000 )
	674	offs_t am29000_cpu_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options)
472	675	{
473		am29000_state *am29000 = get_safe_token(device);
474
475		switch (state)
476		{
477		/* --- the following bits of info are set as 64-bit signed integers --- */
478		case CPUINFO_INT_INPUT_STATE + AM29000_INTR0: set_irq_line(am29000, AM29000_INTR0, info->i); break;
479		case CPUINFO_INT_INPUT_STATE + AM29000_INTR1: set_irq_line(am29000, AM29000_INTR1, info->i); break;
480		case CPUINFO_INT_INPUT_STATE + AM29000_INTR2: set_irq_line(am29000, AM29000_INTR2, info->i); break;
481		case CPUINFO_INT_INPUT_STATE + AM29000_INTR3: set_irq_line(am29000, AM29000_INTR3, info->i); break;
482
483		case CPUINFO_INT_PC:
484		case CPUINFO_INT_REGISTER + AM29000_PC: am29000->pc = info->i; break;
485		case CPUINFO_INT_REGISTER + AM29000_VAB: am29000->vab = info->i; break;
486		case CPUINFO_INT_REGISTER + AM29000_OPS: am29000->ops = info->i; break;
487		case CPUINFO_INT_REGISTER + AM29000_CPS: am29000->cps = info->i; break;
488		case CPUINFO_INT_REGISTER + AM29000_CFG: am29000->cfg = info->i; break;
489		case CPUINFO_INT_REGISTER + AM29000_CHA: am29000->cha = info->i; break;
490		case CPUINFO_INT_REGISTER + AM29000_CHD: am29000->chd = info->i; break;
491		case CPUINFO_INT_REGISTER + AM29000_CHC: am29000->chc = info->i; break;
492		case CPUINFO_INT_REGISTER + AM29000_RBP: am29000->rbp = info->i; break;
493		case CPUINFO_INT_REGISTER + AM29000_TMC: am29000->tmc = info->i; break;
494		case CPUINFO_INT_REGISTER + AM29000_TMR: am29000->tmr = info->i; break;
495		case CPUINFO_INT_REGISTER + AM29000_PC0: am29000->pc0 = info->i; break;
496		case CPUINFO_INT_REGISTER + AM29000_PC1: am29000->pc1 = info->i; break;
497		case CPUINFO_INT_REGISTER + AM29000_PC2: am29000->pc2 = info->i; break;
498		case CPUINFO_INT_REGISTER + AM29000_MMU: am29000->mmu = info->i; break;
499		case CPUINFO_INT_REGISTER + AM29000_LRU: am29000->lru = info->i; break;
500		case CPUINFO_INT_REGISTER + AM29000_IPC: am29000->ipc = info->i; break;
501		case CPUINFO_INT_REGISTER + AM29000_IPA: am29000->ipa = info->i; break;
502		case CPUINFO_INT_REGISTER + AM29000_IPB: am29000->ipb = info->i; break;
503		case CPUINFO_INT_REGISTER + AM29000_Q: am29000->q = info->i; break;
504		case CPUINFO_INT_REGISTER + AM29000_ALU: am29000->alu = info->i; break;
505		case CPUINFO_INT_REGISTER + AM29000_BP: SET_ALU_BP(info->i); break;
506		case CPUINFO_INT_REGISTER + AM29000_FC: SET_ALU_FC(info->i); break;
507		case CPUINFO_INT_REGISTER + AM29000_CR: SET_CHC_CR(info->i); break;
508		case CPUINFO_INT_REGISTER + AM29000_FPE: am29000->fpe = info->i; break;
509		case CPUINFO_INT_REGISTER + AM29000_INTE: am29000->inte = info->i; break;
510		case CPUINFO_INT_REGISTER + AM29000_FPS: am29000->fps = info->i; break;
511		case CPUINFO_INT_REGISTER + AM29000_R1: am29000->r[1] = info->i; break;
512		case CPUINFO_INT_REGISTER + AM29000_R64: am29000->r[64] = info->i; break;
513		case CPUINFO_INT_REGISTER + AM29000_R65: am29000->r[65] = info->i; break;
514		case CPUINFO_INT_REGISTER + AM29000_R66: am29000->r[66] = info->i; break;
515		case CPUINFO_INT_REGISTER + AM29000_R67: am29000->r[67] = info->i; break;
516		case CPUINFO_INT_REGISTER + AM29000_R68: am29000->r[68] = info->i; break;
517		case CPUINFO_INT_REGISTER + AM29000_R69: am29000->r[69] = info->i; break;
518		case CPUINFO_INT_REGISTER + AM29000_R70: am29000->r[70] = info->i; break;
519		case CPUINFO_INT_REGISTER + AM29000_R71: am29000->r[71] = info->i; break;
520		case CPUINFO_INT_REGISTER + AM29000_R72: am29000->r[72] = info->i; break;
521		case CPUINFO_INT_REGISTER + AM29000_R73: am29000->r[73] = info->i; break;
522		case CPUINFO_INT_REGISTER + AM29000_R74: am29000->r[74] = info->i; break;
523		case CPUINFO_INT_REGISTER + AM29000_R75: am29000->r[75] = info->i; break;
524		case CPUINFO_INT_REGISTER + AM29000_R76: am29000->r[76] = info->i; break;
525		case CPUINFO_INT_REGISTER + AM29000_R77: am29000->r[77] = info->i; break;
526		case CPUINFO_INT_REGISTER + AM29000_R78: am29000->r[78] = info->i; break;
527		case CPUINFO_INT_REGISTER + AM29000_R79: am29000->r[79] = info->i; break;
528		case CPUINFO_INT_REGISTER + AM29000_R80: am29000->r[80] = info->i; break;
529		case CPUINFO_INT_REGISTER + AM29000_R81: am29000->r[81] = info->i; break;
530		case CPUINFO_INT_REGISTER + AM29000_R82: am29000->r[82] = info->i; break;
531		case CPUINFO_INT_REGISTER + AM29000_R83: am29000->r[83] = info->i; break;
532		case CPUINFO_INT_REGISTER + AM29000_R84: am29000->r[84] = info->i; break;
533		case CPUINFO_INT_REGISTER + AM29000_R85: am29000->r[85] = info->i; break;
534		case CPUINFO_INT_REGISTER + AM29000_R86: am29000->r[86] = info->i; break;
535		case CPUINFO_INT_REGISTER + AM29000_R87: am29000->r[87] = info->i; break;
536		case CPUINFO_INT_REGISTER + AM29000_R88: am29000->r[88] = info->i; break;
537		case CPUINFO_INT_REGISTER + AM29000_R89: am29000->r[89] = info->i; break;
538		case CPUINFO_INT_REGISTER + AM29000_R90: am29000->r[90] = info->i; break;
539		case CPUINFO_INT_REGISTER + AM29000_R91: am29000->r[91] = info->i; break;
540		case CPUINFO_INT_REGISTER + AM29000_R92: am29000->r[92] = info->i; break;
541		case CPUINFO_INT_REGISTER + AM29000_R93: am29000->r[93] = info->i; break;
542		case CPUINFO_INT_REGISTER + AM29000_R94: am29000->r[94] = info->i; break;
543		case CPUINFO_INT_REGISTER + AM29000_R95: am29000->r[95] = info->i; break;
544		case CPUINFO_INT_REGISTER + AM29000_R96: am29000->r[96] = info->i; break;
545		case CPUINFO_INT_REGISTER + AM29000_R97: am29000->r[97] = info->i; break;
546		case CPUINFO_INT_REGISTER + AM29000_R98: am29000->r[98] = info->i; break;
547		case CPUINFO_INT_REGISTER + AM29000_R99: am29000->r[99] = info->i; break;
548		case CPUINFO_INT_REGISTER + AM29000_R100: am29000->r[100] = info->i; break;
549		case CPUINFO_INT_REGISTER + AM29000_R101: am29000->r[101] = info->i; break;
550		case CPUINFO_INT_REGISTER + AM29000_R102: am29000->r[102] = info->i; break;
551		case CPUINFO_INT_REGISTER + AM29000_R103: am29000->r[103] = info->i; break;
552		case CPUINFO_INT_REGISTER + AM29000_R104: am29000->r[104] = info->i; break;
553		case CPUINFO_INT_REGISTER + AM29000_R105: am29000->r[105] = info->i; break;
554		case CPUINFO_INT_REGISTER + AM29000_R106: am29000->r[106] = info->i; break;
555		case CPUINFO_INT_REGISTER + AM29000_R107: am29000->r[107] = info->i; break;
556		case CPUINFO_INT_REGISTER + AM29000_R108: am29000->r[108] = info->i; break;
557		case CPUINFO_INT_REGISTER + AM29000_R109: am29000->r[109] = info->i; break;
558		case CPUINFO_INT_REGISTER + AM29000_R110: am29000->r[110] = info->i; break;
559		case CPUINFO_INT_REGISTER + AM29000_R111: am29000->r[111] = info->i; break;
560		case CPUINFO_INT_REGISTER + AM29000_R112: am29000->r[112] = info->i; break;
561		case CPUINFO_INT_REGISTER + AM29000_R113: am29000->r[113] = info->i; break;
562		case CPUINFO_INT_REGISTER + AM29000_R114: am29000->r[114] = info->i; break;
563		case CPUINFO_INT_REGISTER + AM29000_R115: am29000->r[115] = info->i; break;
564		case CPUINFO_INT_REGISTER + AM29000_R116: am29000->r[116] = info->i; break;
565		case CPUINFO_INT_REGISTER + AM29000_R117: am29000->r[117] = info->i; break;
566		case CPUINFO_INT_REGISTER + AM29000_R118: am29000->r[118] = info->i; break;
567		case CPUINFO_INT_REGISTER + AM29000_R119: am29000->r[119] = info->i; break;
568		case CPUINFO_INT_REGISTER + AM29000_R120: am29000->r[120] = info->i; break;
569		case CPUINFO_INT_REGISTER + AM29000_R121: am29000->r[121] = info->i; break;
570		case CPUINFO_INT_REGISTER + AM29000_R122: am29000->r[122] = info->i; break;
571		case CPUINFO_INT_REGISTER + AM29000_R123: am29000->r[123] = info->i; break;
572		case CPUINFO_INT_REGISTER + AM29000_R124: am29000->r[124] = info->i; break;
573		case CPUINFO_INT_REGISTER + AM29000_R125: am29000->r[125] = info->i; break;
574		case CPUINFO_INT_REGISTER + AM29000_R126: am29000->r[126] = info->i; break;
575		case CPUINFO_INT_REGISTER + AM29000_R127: am29000->r[127] = info->i; break;
576		case CPUINFO_INT_REGISTER + AM29000_R128: am29000->r[128] = info->i; break;
577		case CPUINFO_INT_REGISTER + AM29000_R129: am29000->r[129] = info->i; break;
578		case CPUINFO_INT_REGISTER + AM29000_R130: am29000->r[130] = info->i; break;
579		case CPUINFO_INT_REGISTER + AM29000_R131: am29000->r[131] = info->i; break;
580		case CPUINFO_INT_REGISTER + AM29000_R132: am29000->r[132] = info->i; break;
581		case CPUINFO_INT_REGISTER + AM29000_R133: am29000->r[133] = info->i; break;
582		case CPUINFO_INT_REGISTER + AM29000_R134: am29000->r[134] = info->i; break;
583		case CPUINFO_INT_REGISTER + AM29000_R135: am29000->r[135] = info->i; break;
584		case CPUINFO_INT_REGISTER + AM29000_R136: am29000->r[136] = info->i; break;
585		case CPUINFO_INT_REGISTER + AM29000_R137: am29000->r[137] = info->i; break;
586		case CPUINFO_INT_REGISTER + AM29000_R138: am29000->r[138] = info->i; break;
587		case CPUINFO_INT_REGISTER + AM29000_R139: am29000->r[139] = info->i; break;
588		case CPUINFO_INT_REGISTER + AM29000_R140: am29000->r[140] = info->i; break;
589		case CPUINFO_INT_REGISTER + AM29000_R141: am29000->r[141] = info->i; break;
590		case CPUINFO_INT_REGISTER + AM29000_R142: am29000->r[142] = info->i; break;
591		case CPUINFO_INT_REGISTER + AM29000_R143: am29000->r[143] = info->i; break;
592		case CPUINFO_INT_REGISTER + AM29000_R144: am29000->r[144] = info->i; break;
593		case CPUINFO_INT_REGISTER + AM29000_R145: am29000->r[145] = info->i; break;
594		case CPUINFO_INT_REGISTER + AM29000_R146: am29000->r[146] = info->i; break;
595		case CPUINFO_INT_REGISTER + AM29000_R147: am29000->r[147] = info->i; break;
596		case CPUINFO_INT_REGISTER + AM29000_R148: am29000->r[148] = info->i; break;
597		case CPUINFO_INT_REGISTER + AM29000_R149: am29000->r[149] = info->i; break;
598		case CPUINFO_INT_REGISTER + AM29000_R150: am29000->r[150] = info->i; break;
599		case CPUINFO_INT_REGISTER + AM29000_R151: am29000->r[151] = info->i; break;
600		case CPUINFO_INT_REGISTER + AM29000_R152: am29000->r[152] = info->i; break;
601		case CPUINFO_INT_REGISTER + AM29000_R153: am29000->r[153] = info->i; break;
602		case CPUINFO_INT_REGISTER + AM29000_R154: am29000->r[154] = info->i; break;
603		case CPUINFO_INT_REGISTER + AM29000_R155: am29000->r[155] = info->i; break;
604		case CPUINFO_INT_REGISTER + AM29000_R156: am29000->r[156] = info->i; break;
605		case CPUINFO_INT_REGISTER + AM29000_R157: am29000->r[157] = info->i; break;
606		case CPUINFO_INT_REGISTER + AM29000_R158: am29000->r[158] = info->i; break;
607		case CPUINFO_INT_REGISTER + AM29000_R159: am29000->r[159] = info->i; break;
608		case CPUINFO_INT_REGISTER + AM29000_R160: am29000->r[160] = info->i; break;
609		case CPUINFO_INT_REGISTER + AM29000_R161: am29000->r[161] = info->i; break;
610		case CPUINFO_INT_REGISTER + AM29000_R162: am29000->r[162] = info->i; break;
611		case CPUINFO_INT_REGISTER + AM29000_R163: am29000->r[163] = info->i; break;
612		case CPUINFO_INT_REGISTER + AM29000_R164: am29000->r[164] = info->i; break;
613		case CPUINFO_INT_REGISTER + AM29000_R165: am29000->r[165] = info->i; break;
614		case CPUINFO_INT_REGISTER + AM29000_R166: am29000->r[166] = info->i; break;
615		case CPUINFO_INT_REGISTER + AM29000_R167: am29000->r[167] = info->i; break;
616		case CPUINFO_INT_REGISTER + AM29000_R168: am29000->r[168] = info->i; break;
617		case CPUINFO_INT_REGISTER + AM29000_R169: am29000->r[169] = info->i; break;
618		case CPUINFO_INT_REGISTER + AM29000_R170: am29000->r[170] = info->i; break;
619		case CPUINFO_INT_REGISTER + AM29000_R171: am29000->r[171] = info->i; break;
620		case CPUINFO_INT_REGISTER + AM29000_R172: am29000->r[172] = info->i; break;
621		case CPUINFO_INT_REGISTER + AM29000_R173: am29000->r[173] = info->i; break;
622		case CPUINFO_INT_REGISTER + AM29000_R174: am29000->r[174] = info->i; break;
623		case CPUINFO_INT_REGISTER + AM29000_R175: am29000->r[175] = info->i; break;
624		case CPUINFO_INT_REGISTER + AM29000_R176: am29000->r[176] = info->i; break;
625		case CPUINFO_INT_REGISTER + AM29000_R177: am29000->r[177] = info->i; break;
626		case CPUINFO_INT_REGISTER + AM29000_R178: am29000->r[178] = info->i; break;
627		case CPUINFO_INT_REGISTER + AM29000_R179: am29000->r[179] = info->i; break;
628		case CPUINFO_INT_REGISTER + AM29000_R180: am29000->r[180] = info->i; break;
629		case CPUINFO_INT_REGISTER + AM29000_R181: am29000->r[181] = info->i; break;
630		case CPUINFO_INT_REGISTER + AM29000_R182: am29000->r[182] = info->i; break;
631		case CPUINFO_INT_REGISTER + AM29000_R183: am29000->r[183] = info->i; break;
632		case CPUINFO_INT_REGISTER + AM29000_R184: am29000->r[184] = info->i; break;
633		case CPUINFO_INT_REGISTER + AM29000_R185: am29000->r[185] = info->i; break;
634		case CPUINFO_INT_REGISTER + AM29000_R186: am29000->r[186] = info->i; break;
635		case CPUINFO_INT_REGISTER + AM29000_R187: am29000->r[187] = info->i; break;
636		case CPUINFO_INT_REGISTER + AM29000_R188: am29000->r[188] = info->i; break;
637		case CPUINFO_INT_REGISTER + AM29000_R189: am29000->r[189] = info->i; break;
638		case CPUINFO_INT_REGISTER + AM29000_R190: am29000->r[190] = info->i; break;
639		case CPUINFO_INT_REGISTER + AM29000_R191: am29000->r[191] = info->i; break;
640		case CPUINFO_INT_REGISTER + AM29000_R192: am29000->r[192] = info->i; break;
641		case CPUINFO_INT_REGISTER + AM29000_R193: am29000->r[193] = info->i; break;
642		case CPUINFO_INT_REGISTER + AM29000_R194: am29000->r[194] = info->i; break;
643		case CPUINFO_INT_REGISTER + AM29000_R195: am29000->r[195] = info->i; break;
644		case CPUINFO_INT_REGISTER + AM29000_R196: am29000->r[196] = info->i; break;
645		case CPUINFO_INT_REGISTER + AM29000_R197: am29000->r[197] = info->i; break;
646		case CPUINFO_INT_REGISTER + AM29000_R198: am29000->r[198] = info->i; break;
647		case CPUINFO_INT_REGISTER + AM29000_R199: am29000->r[199] = info->i; break;
648		case CPUINFO_INT_REGISTER + AM29000_R200: am29000->r[200] = info->i; break;
649		case CPUINFO_INT_REGISTER + AM29000_R201: am29000->r[201] = info->i; break;
650		case CPUINFO_INT_REGISTER + AM29000_R202: am29000->r[202] = info->i; break;
651		case CPUINFO_INT_REGISTER + AM29000_R203: am29000->r[203] = info->i; break;
652		case CPUINFO_INT_REGISTER + AM29000_R204: am29000->r[204] = info->i; break;
653		case CPUINFO_INT_REGISTER + AM29000_R205: am29000->r[205] = info->i; break;
654		case CPUINFO_INT_REGISTER + AM29000_R206: am29000->r[206] = info->i; break;
655		case CPUINFO_INT_REGISTER + AM29000_R207: am29000->r[207] = info->i; break;
656		case CPUINFO_INT_REGISTER + AM29000_R208: am29000->r[208] = info->i; break;
657		case CPUINFO_INT_REGISTER + AM29000_R209: am29000->r[209] = info->i; break;
658		case CPUINFO_INT_REGISTER + AM29000_R210: am29000->r[210] = info->i; break;
659		case CPUINFO_INT_REGISTER + AM29000_R211: am29000->r[211] = info->i; break;
660		case CPUINFO_INT_REGISTER + AM29000_R212: am29000->r[212] = info->i; break;
661		case CPUINFO_INT_REGISTER + AM29000_R213: am29000->r[213] = info->i; break;
662		case CPUINFO_INT_REGISTER + AM29000_R214: am29000->r[214] = info->i; break;
663		case CPUINFO_INT_REGISTER + AM29000_R215: am29000->r[215] = info->i; break;
664		case CPUINFO_INT_REGISTER + AM29000_R216: am29000->r[216] = info->i; break;
665		case CPUINFO_INT_REGISTER + AM29000_R217: am29000->r[217] = info->i; break;
666		case CPUINFO_INT_REGISTER + AM29000_R218: am29000->r[218] = info->i; break;
667		case CPUINFO_INT_REGISTER + AM29000_R219: am29000->r[219] = info->i; break;
668		case CPUINFO_INT_REGISTER + AM29000_R220: am29000->r[220] = info->i; break;
669		case CPUINFO_INT_REGISTER + AM29000_R221: am29000->r[221] = info->i; break;
670		case CPUINFO_INT_REGISTER + AM29000_R222: am29000->r[222] = info->i; break;
671		case CPUINFO_INT_REGISTER + AM29000_R223: am29000->r[223] = info->i; break;
672		case CPUINFO_INT_REGISTER + AM29000_R224: am29000->r[224] = info->i; break;
673		case CPUINFO_INT_REGISTER + AM29000_R225: am29000->r[225] = info->i; break;
674		case CPUINFO_INT_REGISTER + AM29000_R226: am29000->r[226] = info->i; break;
675		case CPUINFO_INT_REGISTER + AM29000_R227: am29000->r[227] = info->i; break;
676		case CPUINFO_INT_REGISTER + AM29000_R228: am29000->r[228] = info->i; break;
677		case CPUINFO_INT_REGISTER + AM29000_R229: am29000->r[229] = info->i; break;
678		case CPUINFO_INT_REGISTER + AM29000_R230: am29000->r[230] = info->i; break;
679		case CPUINFO_INT_REGISTER + AM29000_R231: am29000->r[231] = info->i; break;
680		case CPUINFO_INT_REGISTER + AM29000_R232: am29000->r[232] = info->i; break;
681		case CPUINFO_INT_REGISTER + AM29000_R233: am29000->r[233] = info->i; break;
682		case CPUINFO_INT_REGISTER + AM29000_R234: am29000->r[234] = info->i; break;
683		case CPUINFO_INT_REGISTER + AM29000_R235: am29000->r[235] = info->i; break;
684		case CPUINFO_INT_REGISTER + AM29000_R236: am29000->r[236] = info->i; break;
685		case CPUINFO_INT_REGISTER + AM29000_R237: am29000->r[237] = info->i; break;
686		case CPUINFO_INT_REGISTER + AM29000_R238: am29000->r[238] = info->i; break;
687		case CPUINFO_INT_REGISTER + AM29000_R239: am29000->r[239] = info->i; break;
688		case CPUINFO_INT_REGISTER + AM29000_R240: am29000->r[240] = info->i; break;
689		case CPUINFO_INT_REGISTER + AM29000_R241: am29000->r[241] = info->i; break;
690		case CPUINFO_INT_REGISTER + AM29000_R242: am29000->r[242] = info->i; break;
691		case CPUINFO_INT_REGISTER + AM29000_R243: am29000->r[243] = info->i; break;
692		case CPUINFO_INT_REGISTER + AM29000_R244: am29000->r[244] = info->i; break;
693		case CPUINFO_INT_REGISTER + AM29000_R245: am29000->r[245] = info->i; break;
694		case CPUINFO_INT_REGISTER + AM29000_R246: am29000->r[246] = info->i; break;
695		case CPUINFO_INT_REGISTER + AM29000_R247: am29000->r[247] = info->i; break;
696		case CPUINFO_INT_REGISTER + AM29000_R248: am29000->r[248] = info->i; break;
697		case CPUINFO_INT_REGISTER + AM29000_R249: am29000->r[249] = info->i; break;
698		case CPUINFO_INT_REGISTER + AM29000_R250: am29000->r[250] = info->i; break;
699		case CPUINFO_INT_REGISTER + AM29000_R251: am29000->r[251] = info->i; break;
700		case CPUINFO_INT_REGISTER + AM29000_R252: am29000->r[252] = info->i; break;
701		case CPUINFO_INT_REGISTER + AM29000_R253: am29000->r[253] = info->i; break;
702		case CPUINFO_INT_REGISTER + AM29000_R254: am29000->r[254] = info->i; break;
703		case CPUINFO_INT_REGISTER + AM29000_R255: am29000->r[255] = info->i; break;
704		}
	676	extern CPU_DISASSEMBLE( am29000 );
	677	return CPU_DISASSEMBLE_NAME(am29000)(this, buffer, pc, oprom, opram, options);
705	678	}
706	679
707
708		/**************************************************************************
709		* Generic get_info
710		**************************************************************************/
711
712		CPU_GET_INFO( am29000 )
713		{
714		am29000_state *am29000 = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
715
716		switch (state)
717		{
718		/* --- the following bits of info are returned as 64-bit signed integers --- */
719		case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(am29000_state); break;
720		case CPUINFO_INT_INPUT_LINES: info->i = 1; break;
721		case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
722		case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
723		case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
724		case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
725		case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 4; break;
726		case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
727		case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
728		case CPUINFO_INT_MAX_CYCLES: info->i = 2; break;
729
730		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 32; break;
731		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break;
732		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
733		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 32; break;
734		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 32; break;
735		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
736		case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 32; break;
737		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 32; break;
738		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
739
740		case CPUINFO_INT_PC:
741		case CPUINFO_INT_REGISTER + AM29000_PC: info->i = am29000->pc; break;
742		case CPUINFO_INT_REGISTER + AM29000_VAB: info->i = am29000->vab; break;
743		case CPUINFO_INT_REGISTER + AM29000_OPS: info->i = am29000->ops; break;
744		case CPUINFO_INT_REGISTER + AM29000_CPS: info->i = am29000->cps; break;
745		case CPUINFO_INT_REGISTER + AM29000_CFG: info->i = am29000->cfg; break;
746		case CPUINFO_INT_REGISTER + AM29000_CHA: info->i = am29000->cha; break;
747		case CPUINFO_INT_REGISTER + AM29000_CHD: info->i = am29000->chd; break;
748		case CPUINFO_INT_REGISTER + AM29000_CHC: info->i = am29000->chc; break;
749		case CPUINFO_INT_REGISTER + AM29000_RBP: info->i = am29000->rbp; break;
750		case CPUINFO_INT_REGISTER + AM29000_TMC: info->i = am29000->tmc; break;
751		case CPUINFO_INT_REGISTER + AM29000_TMR: info->i = am29000->tmr; break;
752		case CPUINFO_INT_REGISTER + AM29000_PC0: info->i = am29000->pc0; break;
753		case CPUINFO_INT_REGISTER + AM29000_PC1: info->i = am29000->pc1; break;
754		case CPUINFO_INT_REGISTER + AM29000_PC2: info->i = am29000->pc2; break;
755		case CPUINFO_INT_REGISTER + AM29000_MMU: info->i = am29000->mmu; break;
756		case CPUINFO_INT_REGISTER + AM29000_LRU: info->i = am29000->lru; break;
757		case CPUINFO_INT_REGISTER + AM29000_IPC: info->i = am29000->ipc; break;
758		case CPUINFO_INT_REGISTER + AM29000_IPA: info->i = am29000->ipa; break;
759		case CPUINFO_INT_REGISTER + AM29000_IPB: info->i = am29000->ipb; break;
760		case CPUINFO_INT_REGISTER + AM29000_Q: info->i = am29000->q; break;
761		case CPUINFO_INT_REGISTER + AM29000_ALU: info->i = am29000->alu; break;
762		case CPUINFO_INT_REGISTER + AM29000_BP: info->i = GET_ALU_BP; break;
763		case CPUINFO_INT_REGISTER + AM29000_FC: info->i = GET_ALU_FC; break;
764		case CPUINFO_INT_REGISTER + AM29000_CR: info->i = GET_CHC_CR; break;
765		case CPUINFO_INT_REGISTER + AM29000_FPE: info->i = am29000->fpe; break;
766		case CPUINFO_INT_REGISTER + AM29000_INTE: info->i = am29000->inte; break;
767		case CPUINFO_INT_REGISTER + AM29000_FPS: info->i = am29000->fps; break;
768		case CPUINFO_INT_REGISTER + AM29000_R1: info->i = am29000->r[1]; break;
769		case CPUINFO_INT_REGISTER + AM29000_R64: info->i = am29000->r[64]; break;
770		case CPUINFO_INT_REGISTER + AM29000_R65: info->i = am29000->r[65]; break;
771		case CPUINFO_INT_REGISTER + AM29000_R66: info->i = am29000->r[66]; break;
772		case CPUINFO_INT_REGISTER + AM29000_R67: info->i = am29000->r[67]; break;
773		case CPUINFO_INT_REGISTER + AM29000_R68: info->i = am29000->r[68]; break;
774		case CPUINFO_INT_REGISTER + AM29000_R69: info->i = am29000->r[69]; break;
775		case CPUINFO_INT_REGISTER + AM29000_R70: info->i = am29000->r[70]; break;
776		case CPUINFO_INT_REGISTER + AM29000_R71: info->i = am29000->r[71]; break;
777		case CPUINFO_INT_REGISTER + AM29000_R72: info->i = am29000->r[72]; break;
778		case CPUINFO_INT_REGISTER + AM29000_R73: info->i = am29000->r[73]; break;
779		case CPUINFO_INT_REGISTER + AM29000_R74: info->i = am29000->r[74]; break;
780		case CPUINFO_INT_REGISTER + AM29000_R75: info->i = am29000->r[75]; break;
781		case CPUINFO_INT_REGISTER + AM29000_R76: info->i = am29000->r[76]; break;
782		case CPUINFO_INT_REGISTER + AM29000_R77: info->i = am29000->r[77]; break;
783		case CPUINFO_INT_REGISTER + AM29000_R78: info->i = am29000->r[78]; break;
784		case CPUINFO_INT_REGISTER + AM29000_R79: info->i = am29000->r[79]; break;
785		case CPUINFO_INT_REGISTER + AM29000_R80: info->i = am29000->r[80]; break;
786		case CPUINFO_INT_REGISTER + AM29000_R81: info->i = am29000->r[81]; break;
787		case CPUINFO_INT_REGISTER + AM29000_R82: info->i = am29000->r[82]; break;
788		case CPUINFO_INT_REGISTER + AM29000_R83: info->i = am29000->r[83]; break;
789		case CPUINFO_INT_REGISTER + AM29000_R84: info->i = am29000->r[84]; break;
790		case CPUINFO_INT_REGISTER + AM29000_R85: info->i = am29000->r[85]; break;
791		case CPUINFO_INT_REGISTER + AM29000_R86: info->i = am29000->r[86]; break;
792		case CPUINFO_INT_REGISTER + AM29000_R87: info->i = am29000->r[87]; break;
793		case CPUINFO_INT_REGISTER + AM29000_R88: info->i = am29000->r[88]; break;
794		case CPUINFO_INT_REGISTER + AM29000_R89: info->i = am29000->r[89]; break;
795		case CPUINFO_INT_REGISTER + AM29000_R90: info->i = am29000->r[90]; break;
796		case CPUINFO_INT_REGISTER + AM29000_R91: info->i = am29000->r[91]; break;
797		case CPUINFO_INT_REGISTER + AM29000_R92: info->i = am29000->r[92]; break;
798		case CPUINFO_INT_REGISTER + AM29000_R93: info->i = am29000->r[93]; break;
799		case CPUINFO_INT_REGISTER + AM29000_R94: info->i = am29000->r[94]; break;
800		case CPUINFO_INT_REGISTER + AM29000_R95: info->i = am29000->r[95]; break;
801		case CPUINFO_INT_REGISTER + AM29000_R96: info->i = am29000->r[96]; break;
802		case CPUINFO_INT_REGISTER + AM29000_R97: info->i = am29000->r[97]; break;
803		case CPUINFO_INT_REGISTER + AM29000_R98: info->i = am29000->r[98]; break;
804		case CPUINFO_INT_REGISTER + AM29000_R99: info->i = am29000->r[99]; break;
805		case CPUINFO_INT_REGISTER + AM29000_R100: info->i = am29000->r[100]; break;
806		case CPUINFO_INT_REGISTER + AM29000_R101: info->i = am29000->r[101]; break;
807		case CPUINFO_INT_REGISTER + AM29000_R102: info->i = am29000->r[102]; break;
808		case CPUINFO_INT_REGISTER + AM29000_R103: info->i = am29000->r[103]; break;
809		case CPUINFO_INT_REGISTER + AM29000_R104: info->i = am29000->r[104]; break;
810		case CPUINFO_INT_REGISTER + AM29000_R105: info->i = am29000->r[105]; break;
811		case CPUINFO_INT_REGISTER + AM29000_R106: info->i = am29000->r[106]; break;
812		case CPUINFO_INT_REGISTER + AM29000_R107: info->i = am29000->r[107]; break;
813		case CPUINFO_INT_REGISTER + AM29000_R108: info->i = am29000->r[108]; break;
814		case CPUINFO_INT_REGISTER + AM29000_R109: info->i = am29000->r[109]; break;
815		case CPUINFO_INT_REGISTER + AM29000_R110: info->i = am29000->r[110]; break;
816		case CPUINFO_INT_REGISTER + AM29000_R111: info->i = am29000->r[111]; break;
817		case CPUINFO_INT_REGISTER + AM29000_R112: info->i = am29000->r[112]; break;
818		case CPUINFO_INT_REGISTER + AM29000_R113: info->i = am29000->r[113]; break;
819		case CPUINFO_INT_REGISTER + AM29000_R114: info->i = am29000->r[114]; break;
820		case CPUINFO_INT_REGISTER + AM29000_R115: info->i = am29000->r[115]; break;
821		case CPUINFO_INT_REGISTER + AM29000_R116: info->i = am29000->r[116]; break;
822		case CPUINFO_INT_REGISTER + AM29000_R117: info->i = am29000->r[117]; break;
823		case CPUINFO_INT_REGISTER + AM29000_R118: info->i = am29000->r[118]; break;
824		case CPUINFO_INT_REGISTER + AM29000_R119: info->i = am29000->r[119]; break;
825		case CPUINFO_INT_REGISTER + AM29000_R120: info->i = am29000->r[120]; break;
826		case CPUINFO_INT_REGISTER + AM29000_R121: info->i = am29000->r[121]; break;
827		case CPUINFO_INT_REGISTER + AM29000_R122: info->i = am29000->r[122]; break;
828		case CPUINFO_INT_REGISTER + AM29000_R123: info->i = am29000->r[123]; break;
829		case CPUINFO_INT_REGISTER + AM29000_R124: info->i = am29000->r[124]; break;
830		case CPUINFO_INT_REGISTER + AM29000_R125: info->i = am29000->r[125]; break;
831		case CPUINFO_INT_REGISTER + AM29000_R126: info->i = am29000->r[126]; break;
832		case CPUINFO_INT_REGISTER + AM29000_R127: info->i = am29000->r[127]; break;
833		case CPUINFO_INT_REGISTER + AM29000_R128: info->i = am29000->r[128]; break;
834		case CPUINFO_INT_REGISTER + AM29000_R129: info->i = am29000->r[129]; break;
835		case CPUINFO_INT_REGISTER + AM29000_R130: info->i = am29000->r[130]; break;
836		case CPUINFO_INT_REGISTER + AM29000_R131: info->i = am29000->r[131]; break;
837		case CPUINFO_INT_REGISTER + AM29000_R132: info->i = am29000->r[132]; break;
838		case CPUINFO_INT_REGISTER + AM29000_R133: info->i = am29000->r[133]; break;
839		case CPUINFO_INT_REGISTER + AM29000_R134: info->i = am29000->r[134]; break;
840		case CPUINFO_INT_REGISTER + AM29000_R135: info->i = am29000->r[135]; break;
841		case CPUINFO_INT_REGISTER + AM29000_R136: info->i = am29000->r[136]; break;
842		case CPUINFO_INT_REGISTER + AM29000_R137: info->i = am29000->r[137]; break;
843		case CPUINFO_INT_REGISTER + AM29000_R138: info->i = am29000->r[138]; break;
844		case CPUINFO_INT_REGISTER + AM29000_R139: info->i = am29000->r[139]; break;
845		case CPUINFO_INT_REGISTER + AM29000_R140: info->i = am29000->r[140]; break;
846		case CPUINFO_INT_REGISTER + AM29000_R141: info->i = am29000->r[141]; break;
847		case CPUINFO_INT_REGISTER + AM29000_R142: info->i = am29000->r[142]; break;
848		case CPUINFO_INT_REGISTER + AM29000_R143: info->i = am29000->r[143]; break;
849		case CPUINFO_INT_REGISTER + AM29000_R144: info->i = am29000->r[144]; break;
850		case CPUINFO_INT_REGISTER + AM29000_R145: info->i = am29000->r[145]; break;
851		case CPUINFO_INT_REGISTER + AM29000_R146: info->i = am29000->r[146]; break;
852		case CPUINFO_INT_REGISTER + AM29000_R147: info->i = am29000->r[147]; break;
853		case CPUINFO_INT_REGISTER + AM29000_R148: info->i = am29000->r[148]; break;
854		case CPUINFO_INT_REGISTER + AM29000_R149: info->i = am29000->r[149]; break;
855		case CPUINFO_INT_REGISTER + AM29000_R150: info->i = am29000->r[150]; break;
856		case CPUINFO_INT_REGISTER + AM29000_R151: info->i = am29000->r[151]; break;
857		case CPUINFO_INT_REGISTER + AM29000_R152: info->i = am29000->r[152]; break;
858		case CPUINFO_INT_REGISTER + AM29000_R153: info->i = am29000->r[153]; break;
859		case CPUINFO_INT_REGISTER + AM29000_R154: info->i = am29000->r[154]; break;
860		case CPUINFO_INT_REGISTER + AM29000_R155: info->i = am29000->r[155]; break;
861		case CPUINFO_INT_REGISTER + AM29000_R156: info->i = am29000->r[156]; break;
862		case CPUINFO_INT_REGISTER + AM29000_R157: info->i = am29000->r[157]; break;
863		case CPUINFO_INT_REGISTER + AM29000_R158: info->i = am29000->r[158]; break;
864		case CPUINFO_INT_REGISTER + AM29000_R159: info->i = am29000->r[159]; break;
865		case CPUINFO_INT_REGISTER + AM29000_R160: info->i = am29000->r[160]; break;
866		case CPUINFO_INT_REGISTER + AM29000_R161: info->i = am29000->r[161]; break;
867		case CPUINFO_INT_REGISTER + AM29000_R162: info->i = am29000->r[162]; break;
868		case CPUINFO_INT_REGISTER + AM29000_R163: info->i = am29000->r[163]; break;
869		case CPUINFO_INT_REGISTER + AM29000_R164: info->i = am29000->r[164]; break;
870		case CPUINFO_INT_REGISTER + AM29000_R165: info->i = am29000->r[165]; break;
871		case CPUINFO_INT_REGISTER + AM29000_R166: info->i = am29000->r[166]; break;
872		case CPUINFO_INT_REGISTER + AM29000_R167: info->i = am29000->r[167]; break;
873		case CPUINFO_INT_REGISTER + AM29000_R168: info->i = am29000->r[168]; break;
874		case CPUINFO_INT_REGISTER + AM29000_R169: info->i = am29000->r[169]; break;
875		case CPUINFO_INT_REGISTER + AM29000_R170: info->i = am29000->r[170]; break;
876		case CPUINFO_INT_REGISTER + AM29000_R171: info->i = am29000->r[171]; break;
877		case CPUINFO_INT_REGISTER + AM29000_R172: info->i = am29000->r[172]; break;
878		case CPUINFO_INT_REGISTER + AM29000_R173: info->i = am29000->r[173]; break;
879		case CPUINFO_INT_REGISTER + AM29000_R174: info->i = am29000->r[174]; break;
880		case CPUINFO_INT_REGISTER + AM29000_R175: info->i = am29000->r[175]; break;
881		case CPUINFO_INT_REGISTER + AM29000_R176: info->i = am29000->r[176]; break;
882		case CPUINFO_INT_REGISTER + AM29000_R177: info->i = am29000->r[177]; break;
883		case CPUINFO_INT_REGISTER + AM29000_R178: info->i = am29000->r[178]; break;
884		case CPUINFO_INT_REGISTER + AM29000_R179: info->i = am29000->r[179]; break;
885		case CPUINFO_INT_REGISTER + AM29000_R180: info->i = am29000->r[180]; break;
886		case CPUINFO_INT_REGISTER + AM29000_R181: info->i = am29000->r[181]; break;
887		case CPUINFO_INT_REGISTER + AM29000_R182: info->i = am29000->r[182]; break;
888		case CPUINFO_INT_REGISTER + AM29000_R183: info->i = am29000->r[183]; break;
889		case CPUINFO_INT_REGISTER + AM29000_R184: info->i = am29000->r[184]; break;
890		case CPUINFO_INT_REGISTER + AM29000_R185: info->i = am29000->r[185]; break;
891		case CPUINFO_INT_REGISTER + AM29000_R186: info->i = am29000->r[186]; break;
892		case CPUINFO_INT_REGISTER + AM29000_R187: info->i = am29000->r[187]; break;
893		case CPUINFO_INT_REGISTER + AM29000_R188: info->i = am29000->r[188]; break;
894		case CPUINFO_INT_REGISTER + AM29000_R189: info->i = am29000->r[189]; break;
895		case CPUINFO_INT_REGISTER + AM29000_R190: info->i = am29000->r[190]; break;
896		case CPUINFO_INT_REGISTER + AM29000_R191: info->i = am29000->r[191]; break;
897		case CPUINFO_INT_REGISTER + AM29000_R192: info->i = am29000->r[192]; break;
898		case CPUINFO_INT_REGISTER + AM29000_R193: info->i = am29000->r[193]; break;
899		case CPUINFO_INT_REGISTER + AM29000_R194: info->i = am29000->r[194]; break;
900		case CPUINFO_INT_REGISTER + AM29000_R195: info->i = am29000->r[195]; break;
901		case CPUINFO_INT_REGISTER + AM29000_R196: info->i = am29000->r[196]; break;
902		case CPUINFO_INT_REGISTER + AM29000_R197: info->i = am29000->r[197]; break;
903		case CPUINFO_INT_REGISTER + AM29000_R198: info->i = am29000->r[198]; break;
904		case CPUINFO_INT_REGISTER + AM29000_R199: info->i = am29000->r[199]; break;
905		case CPUINFO_INT_REGISTER + AM29000_R200: info->i = am29000->r[200]; break;
906		case CPUINFO_INT_REGISTER + AM29000_R201: info->i = am29000->r[201]; break;
907		case CPUINFO_INT_REGISTER + AM29000_R202: info->i = am29000->r[202]; break;
908		case CPUINFO_INT_REGISTER + AM29000_R203: info->i = am29000->r[203]; break;
909		case CPUINFO_INT_REGISTER + AM29000_R204: info->i = am29000->r[204]; break;
910		case CPUINFO_INT_REGISTER + AM29000_R205: info->i = am29000->r[205]; break;
911		case CPUINFO_INT_REGISTER + AM29000_R206: info->i = am29000->r[206]; break;
912		case CPUINFO_INT_REGISTER + AM29000_R207: info->i = am29000->r[207]; break;
913		case CPUINFO_INT_REGISTER + AM29000_R208: info->i = am29000->r[208]; break;
914		case CPUINFO_INT_REGISTER + AM29000_R209: info->i = am29000->r[209]; break;
915		case CPUINFO_INT_REGISTER + AM29000_R210: info->i = am29000->r[210]; break;
916		case CPUINFO_INT_REGISTER + AM29000_R211: info->i = am29000->r[211]; break;
917		case CPUINFO_INT_REGISTER + AM29000_R212: info->i = am29000->r[212]; break;
918		case CPUINFO_INT_REGISTER + AM29000_R213: info->i = am29000->r[213]; break;
919		case CPUINFO_INT_REGISTER + AM29000_R214: info->i = am29000->r[214]; break;
920		case CPUINFO_INT_REGISTER + AM29000_R215: info->i = am29000->r[215]; break;
921		case CPUINFO_INT_REGISTER + AM29000_R216: info->i = am29000->r[216]; break;
922		case CPUINFO_INT_REGISTER + AM29000_R217: info->i = am29000->r[217]; break;
923		case CPUINFO_INT_REGISTER + AM29000_R218: info->i = am29000->r[218]; break;
924		case CPUINFO_INT_REGISTER + AM29000_R219: info->i = am29000->r[219]; break;
925		case CPUINFO_INT_REGISTER + AM29000_R220: info->i = am29000->r[220]; break;
926		case CPUINFO_INT_REGISTER + AM29000_R221: info->i = am29000->r[221]; break;
927		case CPUINFO_INT_REGISTER + AM29000_R222: info->i = am29000->r[222]; break;
928		case CPUINFO_INT_REGISTER + AM29000_R223: info->i = am29000->r[223]; break;
929		case CPUINFO_INT_REGISTER + AM29000_R224: info->i = am29000->r[224]; break;
930		case CPUINFO_INT_REGISTER + AM29000_R225: info->i = am29000->r[225]; break;
931		case CPUINFO_INT_REGISTER + AM29000_R226: info->i = am29000->r[226]; break;
932		case CPUINFO_INT_REGISTER + AM29000_R227: info->i = am29000->r[227]; break;
933		case CPUINFO_INT_REGISTER + AM29000_R228: info->i = am29000->r[228]; break;
934		case CPUINFO_INT_REGISTER + AM29000_R229: info->i = am29000->r[229]; break;
935		case CPUINFO_INT_REGISTER + AM29000_R230: info->i = am29000->r[230]; break;
936		case CPUINFO_INT_REGISTER + AM29000_R231: info->i = am29000->r[231]; break;
937		case CPUINFO_INT_REGISTER + AM29000_R232: info->i = am29000->r[232]; break;
938		case CPUINFO_INT_REGISTER + AM29000_R233: info->i = am29000->r[233]; break;
939		case CPUINFO_INT_REGISTER + AM29000_R234: info->i = am29000->r[234]; break;
940		case CPUINFO_INT_REGISTER + AM29000_R235: info->i = am29000->r[235]; break;
941		case CPUINFO_INT_REGISTER + AM29000_R236: info->i = am29000->r[236]; break;
942		case CPUINFO_INT_REGISTER + AM29000_R237: info->i = am29000->r[237]; break;
943		case CPUINFO_INT_REGISTER + AM29000_R238: info->i = am29000->r[238]; break;
944		case CPUINFO_INT_REGISTER + AM29000_R239: info->i = am29000->r[239]; break;
945		case CPUINFO_INT_REGISTER + AM29000_R240: info->i = am29000->r[240]; break;
946		case CPUINFO_INT_REGISTER + AM29000_R241: info->i = am29000->r[241]; break;
947		case CPUINFO_INT_REGISTER + AM29000_R242: info->i = am29000->r[242]; break;
948		case CPUINFO_INT_REGISTER + AM29000_R243: info->i = am29000->r[243]; break;
949		case CPUINFO_INT_REGISTER + AM29000_R244: info->i = am29000->r[244]; break;
950		case CPUINFO_INT_REGISTER + AM29000_R245: info->i = am29000->r[245]; break;
951		case CPUINFO_INT_REGISTER + AM29000_R246: info->i = am29000->r[246]; break;
952		case CPUINFO_INT_REGISTER + AM29000_R247: info->i = am29000->r[247]; break;
953		case CPUINFO_INT_REGISTER + AM29000_R248: info->i = am29000->r[248]; break;
954		case CPUINFO_INT_REGISTER + AM29000_R249: info->i = am29000->r[249]; break;
955		case CPUINFO_INT_REGISTER + AM29000_R250: info->i = am29000->r[250]; break;
956		case CPUINFO_INT_REGISTER + AM29000_R251: info->i = am29000->r[251]; break;
957		case CPUINFO_INT_REGISTER + AM29000_R252: info->i = am29000->r[252]; break;
958		case CPUINFO_INT_REGISTER + AM29000_R253: info->i = am29000->r[253]; break;
959		case CPUINFO_INT_REGISTER + AM29000_R254: info->i = am29000->r[254]; break;
960		case CPUINFO_INT_REGISTER + AM29000_R255: info->i = am29000->r[255]; break;
961
962		/* --- the following bits of info are returned as pointers to data or functions --- */
963		case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(am29000); break;
964		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(am29000); break;
965		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(am29000); break;
966		case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(am29000); break;
967		case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(am29000); break;
968		case CPUINFO_FCT_BURN: info->burn = NULL; break;
969		case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(am29000); break;
970		case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &am29000->icount; break;
971
972		/* --- the following bits of info are returned as NULL-terminated strings --- */
973		case CPUINFO_STR_NAME: strcpy(info->s, "Am29000"); break;
974		case CPUINFO_STR_FAMILY: strcpy(info->s, "AMD Am29000"); break;
975		case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break;
976		case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
977		case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Philip Bennett"); break;
978
979		case CPUINFO_STR_FLAGS: sprintf(info->s, "%c%c%c%c%c%c%c%c%c\|%3d", am29000->alu & ALU_V ? 'V' : '.',
980		am29000->alu & ALU_Z ? 'Z' : '.',
981		am29000->alu & ALU_N ? 'N' : '.',
982		am29000->alu & ALU_C ? 'C' : '.',
983
984		am29000->cps & CPS_IP ? 'I' : '.',
985		am29000->cps & CPS_FZ ? 'F' : '.',
986		am29000->cps & CPS_SM ? 'S' : 'U',
987		am29000->cps & CPS_DI ? 'I' : '.',
988		am29000->cps & CPS_DA ? 'D' : '.',
989		(am29000->r[1] >> 2) & 0x7f); break;
990
991		case CPUINFO_STR_REGISTER + AM29000_PC: sprintf(info->s, "PC: %08X", am29000->pc); break;
992		case CPUINFO_STR_REGISTER + AM29000_VAB: sprintf(info->s, "VAB: %08X", am29000->vab); break;
993		case CPUINFO_STR_REGISTER + AM29000_OPS: sprintf(info->s, "OPS: %08X", am29000->ops); break;
994		case CPUINFO_STR_REGISTER + AM29000_CPS: sprintf(info->s, "CPS: %08X", am29000->cps); break;
995		case CPUINFO_STR_REGISTER + AM29000_CFG: sprintf(info->s, "CFG: %08X", am29000->cfg); break;
996		case CPUINFO_STR_REGISTER + AM29000_CHA: sprintf(info->s, "CHA: %08X", am29000->cha); break;
997		case CPUINFO_STR_REGISTER + AM29000_CHD: sprintf(info->s, "CHD: %08X", am29000->chd); break;
998		case CPUINFO_STR_REGISTER + AM29000_CHC: sprintf(info->s, "CHC: %08X", am29000->chc); break;
999		case CPUINFO_STR_REGISTER + AM29000_RBP: sprintf(info->s, "RBP: %08X", am29000->rbp); break;
1000		case CPUINFO_STR_REGISTER + AM29000_TMC: sprintf(info->s, "TMC: %08X", am29000->tmc); break;
1001		case CPUINFO_STR_REGISTER + AM29000_TMR: sprintf(info->s, "TMR: %08X", am29000->tmr); break;
1002		case CPUINFO_STR_REGISTER + AM29000_PC0: sprintf(info->s, "PC0: %08X", am29000->pc0); break;
1003		case CPUINFO_STR_REGISTER + AM29000_PC1: sprintf(info->s, "PC1: %08X", am29000->pc1); break;
1004		case CPUINFO_STR_REGISTER + AM29000_PC2: sprintf(info->s, "PC2: %08X", am29000->pc2); break;
1005		case CPUINFO_STR_REGISTER + AM29000_MMU: sprintf(info->s, "MMU: %08X", am29000->mmu); break;
1006		case CPUINFO_STR_REGISTER + AM29000_LRU: sprintf(info->s, "LRU: %08X", am29000->lru); break;
1007		case CPUINFO_STR_REGISTER + AM29000_IPC: sprintf(info->s, "IPC: %08X", am29000->ipc); break;
1008		case CPUINFO_STR_REGISTER + AM29000_IPA: sprintf(info->s, "IPA: %08X", am29000->ipa); break;
1009		case CPUINFO_STR_REGISTER + AM29000_IPB: sprintf(info->s, "IPB: %08X", am29000->ipb); break;
1010		case CPUINFO_STR_REGISTER + AM29000_Q: sprintf(info->s, "Q: %08X", am29000->q); break;
1011		case CPUINFO_STR_REGISTER + AM29000_ALU: sprintf(info->s, "ALU: %08X", am29000->alu); break;
1012		case CPUINFO_STR_REGISTER + AM29000_BP: sprintf(info->s, "BP: %08X", GET_ALU_BP); break;
1013		case CPUINFO_STR_REGISTER + AM29000_FC: sprintf(info->s, "FC: %08X", GET_ALU_FC); break;
1014		case CPUINFO_STR_REGISTER + AM29000_CR: sprintf(info->s, "CR: %08X", GET_CHC_CR); break;
1015		case CPUINFO_STR_REGISTER + AM29000_FPE: sprintf(info->s, "FPE: %08X", am29000->fpe); break;
1016		case CPUINFO_STR_REGISTER + AM29000_INTE: sprintf(info->s, "INTE: %08X", am29000->inte); break;
1017		case CPUINFO_STR_REGISTER + AM29000_FPS: sprintf(info->s, "FPS: %08X", am29000->fps); break;
1018		case CPUINFO_STR_REGISTER + AM29000_R1: sprintf(info->s, "R1: %08X", am29000->r[1]); break;
1019		case CPUINFO_STR_REGISTER + AM29000_R64: sprintf(info->s, "R64: %08X", am29000->r[64]); break;
1020		case CPUINFO_STR_REGISTER + AM29000_R65: sprintf(info->s, "R65: %08X", am29000->r[65]); break;
1021		case CPUINFO_STR_REGISTER + AM29000_R66: sprintf(info->s, "R66: %08X", am29000->r[66]); break;
1022		case CPUINFO_STR_REGISTER + AM29000_R67: sprintf(info->s, "R67: %08X", am29000->r[67]); break;
1023		case CPUINFO_STR_REGISTER + AM29000_R68: sprintf(info->s, "R68: %08X", am29000->r[68]); break;
1024		case CPUINFO_STR_REGISTER + AM29000_R69: sprintf(info->s, "R69: %08X", am29000->r[69]); break;
1025		case CPUINFO_STR_REGISTER + AM29000_R70: sprintf(info->s, "R70: %08X", am29000->r[70]); break;
1026		case CPUINFO_STR_REGISTER + AM29000_R71: sprintf(info->s, "R71: %08X", am29000->r[71]); break;
1027		case CPUINFO_STR_REGISTER + AM29000_R72: sprintf(info->s, "R72: %08X", am29000->r[72]); break;
1028		case CPUINFO_STR_REGISTER + AM29000_R73: sprintf(info->s, "R73: %08X", am29000->r[73]); break;
1029		case CPUINFO_STR_REGISTER + AM29000_R74: sprintf(info->s, "R74: %08X", am29000->r[74]); break;
1030		case CPUINFO_STR_REGISTER + AM29000_R75: sprintf(info->s, "R75: %08X", am29000->r[75]); break;
1031		case CPUINFO_STR_REGISTER + AM29000_R76: sprintf(info->s, "R76: %08X", am29000->r[76]); break;
1032		case CPUINFO_STR_REGISTER + AM29000_R77: sprintf(info->s, "R77: %08X", am29000->r[77]); break;
1033		case CPUINFO_STR_REGISTER + AM29000_R78: sprintf(info->s, "R78: %08X", am29000->r[78]); break;
1034		case CPUINFO_STR_REGISTER + AM29000_R79: sprintf(info->s, "R79: %08X", am29000->r[79]); break;
1035		case CPUINFO_STR_REGISTER + AM29000_R80: sprintf(info->s, "R80: %08X", am29000->r[80]); break;
1036		case CPUINFO_STR_REGISTER + AM29000_R81: sprintf(info->s, "R81: %08X", am29000->r[81]); break;
1037		case CPUINFO_STR_REGISTER + AM29000_R82: sprintf(info->s, "R82: %08X", am29000->r[82]); break;
1038		case CPUINFO_STR_REGISTER + AM29000_R83: sprintf(info->s, "R83: %08X", am29000->r[83]); break;
1039		case CPUINFO_STR_REGISTER + AM29000_R84: sprintf(info->s, "R84: %08X", am29000->r[84]); break;
1040		case CPUINFO_STR_REGISTER + AM29000_R85: sprintf(info->s, "R85: %08X", am29000->r[85]); break;
1041		case CPUINFO_STR_REGISTER + AM29000_R86: sprintf(info->s, "R86: %08X", am29000->r[86]); break;
1042		case CPUINFO_STR_REGISTER + AM29000_R87: sprintf(info->s, "R87: %08X", am29000->r[87]); break;
1043		case CPUINFO_STR_REGISTER + AM29000_R88: sprintf(info->s, "R88: %08X", am29000->r[88]); break;
1044		case CPUINFO_STR_REGISTER + AM29000_R89: sprintf(info->s, "R89: %08X", am29000->r[89]); break;
1045		case CPUINFO_STR_REGISTER + AM29000_R90: sprintf(info->s, "R90: %08X", am29000->r[90]); break;
1046		case CPUINFO_STR_REGISTER + AM29000_R91: sprintf(info->s, "R91: %08X", am29000->r[91]); break;
1047		case CPUINFO_STR_REGISTER + AM29000_R92: sprintf(info->s, "R92: %08X", am29000->r[92]); break;
1048		case CPUINFO_STR_REGISTER + AM29000_R93: sprintf(info->s, "R93: %08X", am29000->r[93]); break;
1049		case CPUINFO_STR_REGISTER + AM29000_R94: sprintf(info->s, "R94: %08X", am29000->r[94]); break;
1050		case CPUINFO_STR_REGISTER + AM29000_R95: sprintf(info->s, "R95: %08X", am29000->r[95]); break;
1051		case CPUINFO_STR_REGISTER + AM29000_R96: sprintf(info->s, "R96: %08X", am29000->r[96]); break;
1052		case CPUINFO_STR_REGISTER + AM29000_R97: sprintf(info->s, "R97: %08X", am29000->r[97]); break;
1053		case CPUINFO_STR_REGISTER + AM29000_R98: sprintf(info->s, "R98: %08X", am29000->r[98]); break;
1054		case CPUINFO_STR_REGISTER + AM29000_R99: sprintf(info->s, "R99: %08X", am29000->r[99]); break;
1055		case CPUINFO_STR_REGISTER + AM29000_R100: sprintf(info->s, "R100: %08X", am29000->r[100]); break;
1056		case CPUINFO_STR_REGISTER + AM29000_R101: sprintf(info->s, "R101: %08X", am29000->r[101]); break;
1057		case CPUINFO_STR_REGISTER + AM29000_R102: sprintf(info->s, "R102: %08X", am29000->r[102]); break;
1058		case CPUINFO_STR_REGISTER + AM29000_R103: sprintf(info->s, "R103: %08X", am29000->r[103]); break;
1059		case CPUINFO_STR_REGISTER + AM29000_R104: sprintf(info->s, "R104: %08X", am29000->r[104]); break;
1060		case CPUINFO_STR_REGISTER + AM29000_R105: sprintf(info->s, "R105: %08X", am29000->r[105]); break;
1061		case CPUINFO_STR_REGISTER + AM29000_R106: sprintf(info->s, "R106: %08X", am29000->r[106]); break;
1062		case CPUINFO_STR_REGISTER + AM29000_R107: sprintf(info->s, "R107: %08X", am29000->r[107]); break;
1063		case CPUINFO_STR_REGISTER + AM29000_R108: sprintf(info->s, "R108: %08X", am29000->r[108]); break;
1064		case CPUINFO_STR_REGISTER + AM29000_R109: sprintf(info->s, "R109: %08X", am29000->r[109]); break;
1065		case CPUINFO_STR_REGISTER + AM29000_R110: sprintf(info->s, "R110: %08X", am29000->r[110]); break;
1066		case CPUINFO_STR_REGISTER + AM29000_R111: sprintf(info->s, "R111: %08X", am29000->r[111]); break;
1067		case CPUINFO_STR_REGISTER + AM29000_R112: sprintf(info->s, "R112: %08X", am29000->r[112]); break;
1068		case CPUINFO_STR_REGISTER + AM29000_R113: sprintf(info->s, "R113: %08X", am29000->r[113]); break;
1069		case CPUINFO_STR_REGISTER + AM29000_R114: sprintf(info->s, "R114: %08X", am29000->r[114]); break;
1070		case CPUINFO_STR_REGISTER + AM29000_R115: sprintf(info->s, "R115: %08X", am29000->r[115]); break;
1071		case CPUINFO_STR_REGISTER + AM29000_R116: sprintf(info->s, "R116: %08X", am29000->r[116]); break;
1072		case CPUINFO_STR_REGISTER + AM29000_R117: sprintf(info->s, "R117: %08X", am29000->r[117]); break;
1073		case CPUINFO_STR_REGISTER + AM29000_R118: sprintf(info->s, "R118: %08X", am29000->r[118]); break;
1074		case CPUINFO_STR_REGISTER + AM29000_R119: sprintf(info->s, "R119: %08X", am29000->r[119]); break;
1075		case CPUINFO_STR_REGISTER + AM29000_R120: sprintf(info->s, "R120: %08X", am29000->r[120]); break;
1076		case CPUINFO_STR_REGISTER + AM29000_R121: sprintf(info->s, "R121: %08X", am29000->r[121]); break;
1077		case CPUINFO_STR_REGISTER + AM29000_R122: sprintf(info->s, "R122: %08X", am29000->r[122]); break;
1078		case CPUINFO_STR_REGISTER + AM29000_R123: sprintf(info->s, "R123: %08X", am29000->r[123]); break;
1079		case CPUINFO_STR_REGISTER + AM29000_R124: sprintf(info->s, "R124: %08X", am29000->r[124]); break;
1080		case CPUINFO_STR_REGISTER + AM29000_R125: sprintf(info->s, "R125: %08X", am29000->r[125]); break;
1081		case CPUINFO_STR_REGISTER + AM29000_R126: sprintf(info->s, "R126: %08X", am29000->r[126]); break;
1082		case CPUINFO_STR_REGISTER + AM29000_R127: sprintf(info->s, "R127: %08X", am29000->r[127]); break;
1083		case CPUINFO_STR_REGISTER + AM29000_R128: sprintf(info->s, "R128: %08X", am29000->r[128]); break;
1084		case CPUINFO_STR_REGISTER + AM29000_R129: sprintf(info->s, "R129: %08X", am29000->r[129]); break;
1085		case CPUINFO_STR_REGISTER + AM29000_R130: sprintf(info->s, "R130: %08X", am29000->r[130]); break;
1086		case CPUINFO_STR_REGISTER + AM29000_R131: sprintf(info->s, "R131: %08X", am29000->r[131]); break;
1087		case CPUINFO_STR_REGISTER + AM29000_R132: sprintf(info->s, "R132: %08X", am29000->r[132]); break;
1088		case CPUINFO_STR_REGISTER + AM29000_R133: sprintf(info->s, "R133: %08X", am29000->r[133]); break;
1089		case CPUINFO_STR_REGISTER + AM29000_R134: sprintf(info->s, "R134: %08X", am29000->r[134]); break;
1090		case CPUINFO_STR_REGISTER + AM29000_R135: sprintf(info->s, "R135: %08X", am29000->r[135]); break;
1091		case CPUINFO_STR_REGISTER + AM29000_R136: sprintf(info->s, "R136: %08X", am29000->r[136]); break;
1092		case CPUINFO_STR_REGISTER + AM29000_R137: sprintf(info->s, "R137: %08X", am29000->r[137]); break;
1093		case CPUINFO_STR_REGISTER + AM29000_R138: sprintf(info->s, "R138: %08X", am29000->r[138]); break;
1094		case CPUINFO_STR_REGISTER + AM29000_R139: sprintf(info->s, "R139: %08X", am29000->r[139]); break;
1095		case CPUINFO_STR_REGISTER + AM29000_R140: sprintf(info->s, "R140: %08X", am29000->r[140]); break;
1096		case CPUINFO_STR_REGISTER + AM29000_R141: sprintf(info->s, "R141: %08X", am29000->r[141]); break;
1097		case CPUINFO_STR_REGISTER + AM29000_R142: sprintf(info->s, "R142: %08X", am29000->r[142]); break;
1098		case CPUINFO_STR_REGISTER + AM29000_R143: sprintf(info->s, "R143: %08X", am29000->r[143]); break;
1099		case CPUINFO_STR_REGISTER + AM29000_R144: sprintf(info->s, "R144: %08X", am29000->r[144]); break;
1100		case CPUINFO_STR_REGISTER + AM29000_R145: sprintf(info->s, "R145: %08X", am29000->r[145]); break;
1101		case CPUINFO_STR_REGISTER + AM29000_R146: sprintf(info->s, "R146: %08X", am29000->r[146]); break;
1102		case CPUINFO_STR_REGISTER + AM29000_R147: sprintf(info->s, "R147: %08X", am29000->r[147]); break;
1103		case CPUINFO_STR_REGISTER + AM29000_R148: sprintf(info->s, "R148: %08X", am29000->r[148]); break;
1104		case CPUINFO_STR_REGISTER + AM29000_R149: sprintf(info->s, "R149: %08X", am29000->r[149]); break;
1105		case CPUINFO_STR_REGISTER + AM29000_R150: sprintf(info->s, "R150: %08X", am29000->r[150]); break;
1106		case CPUINFO_STR_REGISTER + AM29000_R151: sprintf(info->s, "R151: %08X", am29000->r[151]); break;
1107		case CPUINFO_STR_REGISTER + AM29000_R152: sprintf(info->s, "R152: %08X", am29000->r[152]); break;
1108		case CPUINFO_STR_REGISTER + AM29000_R153: sprintf(info->s, "R153: %08X", am29000->r[153]); break;
1109		case CPUINFO_STR_REGISTER + AM29000_R154: sprintf(info->s, "R154: %08X", am29000->r[154]); break;
1110		case CPUINFO_STR_REGISTER + AM29000_R155: sprintf(info->s, "R155: %08X", am29000->r[155]); break;
1111		case CPUINFO_STR_REGISTER + AM29000_R156: sprintf(info->s, "R156: %08X", am29000->r[156]); break;
1112		case CPUINFO_STR_REGISTER + AM29000_R157: sprintf(info->s, "R157: %08X", am29000->r[157]); break;
1113		case CPUINFO_STR_REGISTER + AM29000_R158: sprintf(info->s, "R158: %08X", am29000->r[158]); break;
1114		case CPUINFO_STR_REGISTER + AM29000_R159: sprintf(info->s, "R159: %08X", am29000->r[159]); break;
1115		case CPUINFO_STR_REGISTER + AM29000_R160: sprintf(info->s, "R160: %08X", am29000->r[160]); break;
1116		case CPUINFO_STR_REGISTER + AM29000_R161: sprintf(info->s, "R161: %08X", am29000->r[161]); break;
1117		case CPUINFO_STR_REGISTER + AM29000_R162: sprintf(info->s, "R162: %08X", am29000->r[162]); break;
1118		case CPUINFO_STR_REGISTER + AM29000_R163: sprintf(info->s, "R163: %08X", am29000->r[163]); break;
1119		case CPUINFO_STR_REGISTER + AM29000_R164: sprintf(info->s, "R164: %08X", am29000->r[164]); break;
1120		case CPUINFO_STR_REGISTER + AM29000_R165: sprintf(info->s, "R165: %08X", am29000->r[165]); break;
1121		case CPUINFO_STR_REGISTER + AM29000_R166: sprintf(info->s, "R166: %08X", am29000->r[166]); break;
1122		case CPUINFO_STR_REGISTER + AM29000_R167: sprintf(info->s, "R167: %08X", am29000->r[167]); break;
1123		case CPUINFO_STR_REGISTER + AM29000_R168: sprintf(info->s, "R168: %08X", am29000->r[168]); break;
1124		case CPUINFO_STR_REGISTER + AM29000_R169: sprintf(info->s, "R169: %08X", am29000->r[169]); break;
1125		case CPUINFO_STR_REGISTER + AM29000_R170: sprintf(info->s, "R170: %08X", am29000->r[170]); break;
1126		case CPUINFO_STR_REGISTER + AM29000_R171: sprintf(info->s, "R171: %08X", am29000->r[171]); break;
1127		case CPUINFO_STR_REGISTER + AM29000_R172: sprintf(info->s, "R172: %08X", am29000->r[172]); break;
1128		case CPUINFO_STR_REGISTER + AM29000_R173: sprintf(info->s, "R173: %08X", am29000->r[173]); break;
1129		case CPUINFO_STR_REGISTER + AM29000_R174: sprintf(info->s, "R174: %08X", am29000->r[174]); break;
1130		case CPUINFO_STR_REGISTER + AM29000_R175: sprintf(info->s, "R175: %08X", am29000->r[175]); break;
1131		case CPUINFO_STR_REGISTER + AM29000_R176: sprintf(info->s, "R176: %08X", am29000->r[176]); break;
1132		case CPUINFO_STR_REGISTER + AM29000_R177: sprintf(info->s, "R177: %08X", am29000->r[177]); break;
1133		case CPUINFO_STR_REGISTER + AM29000_R178: sprintf(info->s, "R178: %08X", am29000->r[178]); break;
1134		case CPUINFO_STR_REGISTER + AM29000_R179: sprintf(info->s, "R179: %08X", am29000->r[179]); break;
1135		case CPUINFO_STR_REGISTER + AM29000_R180: sprintf(info->s, "R180: %08X", am29000->r[180]); break;
1136		case CPUINFO_STR_REGISTER + AM29000_R181: sprintf(info->s, "R181: %08X", am29000->r[181]); break;
1137		case CPUINFO_STR_REGISTER + AM29000_R182: sprintf(info->s, "R182: %08X", am29000->r[182]); break;
1138		case CPUINFO_STR_REGISTER + AM29000_R183: sprintf(info->s, "R183: %08X", am29000->r[183]); break;
1139		case CPUINFO_STR_REGISTER + AM29000_R184: sprintf(info->s, "R184: %08X", am29000->r[184]); break;
1140		case CPUINFO_STR_REGISTER + AM29000_R185: sprintf(info->s, "R185: %08X", am29000->r[185]); break;
1141		case CPUINFO_STR_REGISTER + AM29000_R186: sprintf(info->s, "R186: %08X", am29000->r[186]); break;
1142		case CPUINFO_STR_REGISTER + AM29000_R187: sprintf(info->s, "R187: %08X", am29000->r[187]); break;
1143		case CPUINFO_STR_REGISTER + AM29000_R188: sprintf(info->s, "R188: %08X", am29000->r[188]); break;
1144		case CPUINFO_STR_REGISTER + AM29000_R189: sprintf(info->s, "R189: %08X", am29000->r[189]); break;
1145		case CPUINFO_STR_REGISTER + AM29000_R190: sprintf(info->s, "R190: %08X", am29000->r[190]); break;
1146		case CPUINFO_STR_REGISTER + AM29000_R191: sprintf(info->s, "R191: %08X", am29000->r[191]); break;
1147		case CPUINFO_STR_REGISTER + AM29000_R192: sprintf(info->s, "R192: %08X", am29000->r[192]); break;
1148		case CPUINFO_STR_REGISTER + AM29000_R193: sprintf(info->s, "R193: %08X", am29000->r[193]); break;
1149		case CPUINFO_STR_REGISTER + AM29000_R194: sprintf(info->s, "R194: %08X", am29000->r[194]); break;
1150		case CPUINFO_STR_REGISTER + AM29000_R195: sprintf(info->s, "R195: %08X", am29000->r[195]); break;
1151		case CPUINFO_STR_REGISTER + AM29000_R196: sprintf(info->s, "R196: %08X", am29000->r[196]); break;
1152		case CPUINFO_STR_REGISTER + AM29000_R197: sprintf(info->s, "R197: %08X", am29000->r[197]); break;
1153		case CPUINFO_STR_REGISTER + AM29000_R198: sprintf(info->s, "R198: %08X", am29000->r[198]); break;
1154		case CPUINFO_STR_REGISTER + AM29000_R199: sprintf(info->s, "R199: %08X", am29000->r[199]); break;
1155		case CPUINFO_STR_REGISTER + AM29000_R200: sprintf(info->s, "R200: %08X", am29000->r[200]); break;
1156		case CPUINFO_STR_REGISTER + AM29000_R201: sprintf(info->s, "R201: %08X", am29000->r[201]); break;
1157		case CPUINFO_STR_REGISTER + AM29000_R202: sprintf(info->s, "R202: %08X", am29000->r[202]); break;
1158		case CPUINFO_STR_REGISTER + AM29000_R203: sprintf(info->s, "R203: %08X", am29000->r[203]); break;
1159		case CPUINFO_STR_REGISTER + AM29000_R204: sprintf(info->s, "R204: %08X", am29000->r[204]); break;
1160		case CPUINFO_STR_REGISTER + AM29000_R205: sprintf(info->s, "R205: %08X", am29000->r[205]); break;
1161		case CPUINFO_STR_REGISTER + AM29000_R206: sprintf(info->s, "R206: %08X", am29000->r[206]); break;
1162		case CPUINFO_STR_REGISTER + AM29000_R207: sprintf(info->s, "R207: %08X", am29000->r[207]); break;
1163		case CPUINFO_STR_REGISTER + AM29000_R208: sprintf(info->s, "R208: %08X", am29000->r[208]); break;
1164		case CPUINFO_STR_REGISTER + AM29000_R209: sprintf(info->s, "R209: %08X", am29000->r[209]); break;
1165		case CPUINFO_STR_REGISTER + AM29000_R210: sprintf(info->s, "R210: %08X", am29000->r[210]); break;
1166		case CPUINFO_STR_REGISTER + AM29000_R211: sprintf(info->s, "R211: %08X", am29000->r[211]); break;
1167		case CPUINFO_STR_REGISTER + AM29000_R212: sprintf(info->s, "R212: %08X", am29000->r[212]); break;
1168		case CPUINFO_STR_REGISTER + AM29000_R213: sprintf(info->s, "R213: %08X", am29000->r[213]); break;
1169		case CPUINFO_STR_REGISTER + AM29000_R214: sprintf(info->s, "R214: %08X", am29000->r[214]); break;
1170		case CPUINFO_STR_REGISTER + AM29000_R215: sprintf(info->s, "R215: %08X", am29000->r[215]); break;
1171		case CPUINFO_STR_REGISTER + AM29000_R216: sprintf(info->s, "R216: %08X", am29000->r[216]); break;
1172		case CPUINFO_STR_REGISTER + AM29000_R217: sprintf(info->s, "R217: %08X", am29000->r[217]); break;
1173		case CPUINFO_STR_REGISTER + AM29000_R218: sprintf(info->s, "R218: %08X", am29000->r[218]); break;
1174		case CPUINFO_STR_REGISTER + AM29000_R219: sprintf(info->s, "R219: %08X", am29000->r[219]); break;
1175		case CPUINFO_STR_REGISTER + AM29000_R220: sprintf(info->s, "R220: %08X", am29000->r[220]); break;
1176		case CPUINFO_STR_REGISTER + AM29000_R221: sprintf(info->s, "R221: %08X", am29000->r[221]); break;
1177		case CPUINFO_STR_REGISTER + AM29000_R222: sprintf(info->s, "R222: %08X", am29000->r[222]); break;
1178		case CPUINFO_STR_REGISTER + AM29000_R223: sprintf(info->s, "R223: %08X", am29000->r[223]); break;
1179		case CPUINFO_STR_REGISTER + AM29000_R224: sprintf(info->s, "R224: %08X", am29000->r[224]); break;
1180		case CPUINFO_STR_REGISTER + AM29000_R225: sprintf(info->s, "R225: %08X", am29000->r[225]); break;
1181		case CPUINFO_STR_REGISTER + AM29000_R226: sprintf(info->s, "R226: %08X", am29000->r[226]); break;
1182		case CPUINFO_STR_REGISTER + AM29000_R227: sprintf(info->s, "R227: %08X", am29000->r[227]); break;
1183		case CPUINFO_STR_REGISTER + AM29000_R228: sprintf(info->s, "R228: %08X", am29000->r[228]); break;
1184		case CPUINFO_STR_REGISTER + AM29000_R229: sprintf(info->s, "R229: %08X", am29000->r[229]); break;
1185		case CPUINFO_STR_REGISTER + AM29000_R230: sprintf(info->s, "R230: %08X", am29000->r[230]); break;
1186		case CPUINFO_STR_REGISTER + AM29000_R231: sprintf(info->s, "R231: %08X", am29000->r[231]); break;
1187		case CPUINFO_STR_REGISTER + AM29000_R232: sprintf(info->s, "R232: %08X", am29000->r[232]); break;
1188		case CPUINFO_STR_REGISTER + AM29000_R233: sprintf(info->s, "R233: %08X", am29000->r[233]); break;
1189		case CPUINFO_STR_REGISTER + AM29000_R234: sprintf(info->s, "R234: %08X", am29000->r[234]); break;
1190		case CPUINFO_STR_REGISTER + AM29000_R235: sprintf(info->s, "R235: %08X", am29000->r[235]); break;
1191		case CPUINFO_STR_REGISTER + AM29000_R236: sprintf(info->s, "R236: %08X", am29000->r[236]); break;
1192		case CPUINFO_STR_REGISTER + AM29000_R237: sprintf(info->s, "R237: %08X", am29000->r[237]); break;
1193		case CPUINFO_STR_REGISTER + AM29000_R238: sprintf(info->s, "R238: %08X", am29000->r[238]); break;
1194		case CPUINFO_STR_REGISTER + AM29000_R239: sprintf(info->s, "R239: %08X", am29000->r[239]); break;
1195		case CPUINFO_STR_REGISTER + AM29000_R240: sprintf(info->s, "R240: %08X", am29000->r[240]); break;
1196		case CPUINFO_STR_REGISTER + AM29000_R241: sprintf(info->s, "R241: %08X", am29000->r[241]); break;
1197		case CPUINFO_STR_REGISTER + AM29000_R242: sprintf(info->s, "R242: %08X", am29000->r[242]); break;
1198		case CPUINFO_STR_REGISTER + AM29000_R243: sprintf(info->s, "R243: %08X", am29000->r[243]); break;
1199		case CPUINFO_STR_REGISTER + AM29000_R244: sprintf(info->s, "R244: %08X", am29000->r[244]); break;
1200		case CPUINFO_STR_REGISTER + AM29000_R245: sprintf(info->s, "R245: %08X", am29000->r[245]); break;
1201		case CPUINFO_STR_REGISTER + AM29000_R246: sprintf(info->s, "R246: %08X", am29000->r[246]); break;
1202		case CPUINFO_STR_REGISTER + AM29000_R247: sprintf(info->s, "R247: %08X", am29000->r[247]); break;
1203		case CPUINFO_STR_REGISTER + AM29000_R248: sprintf(info->s, "R248: %08X", am29000->r[248]); break;
1204		case CPUINFO_STR_REGISTER + AM29000_R249: sprintf(info->s, "R249: %08X", am29000->r[249]); break;
1205		case CPUINFO_STR_REGISTER + AM29000_R250: sprintf(info->s, "R250: %08X", am29000->r[250]); break;
1206		case CPUINFO_STR_REGISTER + AM29000_R251: sprintf(info->s, "R251: %08X", am29000->r[251]); break;
1207		case CPUINFO_STR_REGISTER + AM29000_R252: sprintf(info->s, "R252: %08X", am29000->r[252]); break;
1208		case CPUINFO_STR_REGISTER + AM29000_R253: sprintf(info->s, "R253: %08X", am29000->r[253]); break;
1209		case CPUINFO_STR_REGISTER + AM29000_R254: sprintf(info->s, "R254: %08X", am29000->r[254]); break;
1210		case CPUINFO_STR_REGISTER + AM29000_R255: sprintf(info->s, "R255: %08X", am29000->r[255]); break;
1211		}
1212		}
1213
1214
1215		DEFINE_LEGACY_CPU_DEVICE(AM29000, am29000);

199869 Revisions