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r23869 Sunday 23rd June, 2013 at 07:02:14 UTC by smf
added IDE_CONTROLLER_32 for systems that have 32 bit prefetch (nw)

[src/emu/machine]	ataintf.c idectrl.c idectrl.h vt83c461.c vt83c461.h
[src/mame/drivers]	calchase.c chihiro.c mediagx.c savquest.c seattle.c vegas.c

trunk/src/emu/machine/ataintf.c

r23868	r23869
24	24
25	25	void ata_interface_device::set_irq(int state)
26	26	{
	27	//  printf( "irq %d\n", state );
	28
27	29	if (state == ASSERT_LINE)
28	30	LOG(("ATA interrupt assert\n"));
29	31	else
r23868	r23869
35	37
36	38	void ata_interface_device::set_dmarq(int state)
37	39	{
	40	//  printf( "dmarq %d\n", state );
	41
38	42	m_dmarq_handler(state);
39	43	}
40	44

trunk/src/emu/machine/vt83c461.c

r23868	r23869
17	17	const device_type VT83C461 = &device_creator<vt83c461_device>;
18	18
19	19	vt83c461_device::vt83c461_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
20		ide_controller_device(mconfig, VT83C461, "VIA VT83C461", tag, owner, clock, "vt83c461", __FILE__),
	20	ide_controller_32_device(mconfig, VT83C461, "VIA VT83C461", tag, owner, clock, "vt83c461", __FILE__),
21	21	m_config_unknown(0),
22	22	m_config_register_num(0)
23	23	{
r23868	r23869
29	29
30	30	void vt83c461_device::device_start()
31	31	{
32		ide_controller_device::device_start();
	32	ide_controller_32_device::device_start();
33	33
34	34	/* register ide states */
35	35	save_item(NAME(m_config_unknown));
r23868	r23869
101	101	break;
102	102	}
103	103	}
104
105		READ32_MEMBER(vt83c461_device::read_cs0)
106		{
107		UINT32 data = 0;
108
109		if (ACCESSING_BITS_0_15)
110		{
111		data = ide_controller_device::read_cs0(space, (offset * 2), mem_mask);
112
113		if (offset == 0 && ACCESSING_BITS_16_31)
114		data |= ide_controller_device::read_cs0(space, (offset * 2), mem_mask >> 16) << 16;
115		}
116		else if (ACCESSING_BITS_16_31)
117		{
118		data = ide_controller_device::read_cs0(space, (offset * 2) + 1, mem_mask >> 16) << 16;
119		}
120
121		//   printf( "vt83c461 read cs0 %08x %08x %08x\n", offset, data, mem_mask );
122
123		return data;
124		}
125
126		READ32_MEMBER(vt83c461_device::read_cs1)
127		{
128		UINT32 data = 0;
129
130		if (ACCESSING_BITS_0_15)
131		{
132		data = ide_controller_device::read_cs1(space, (offset * 2), mem_mask);
133		}
134		else if (ACCESSING_BITS_16_23)
135		{
136		data = ide_controller_device::read_cs1(space, (offset * 2) + 1, mem_mask >> 16) << 16;
137		}
138
139		//   printf( "vt83c461 read cs1 %08x %08x %08x\n", offset, data, mem_mask );
140
141		return data;
142		}
143
144		WRITE32_MEMBER(vt83c461_device::write_cs0)
145		{
146		//   printf( "vt83c461 write cs0 %08x %08x %08x\n", offset, data, mem_mask );
147
148		if (ACCESSING_BITS_0_15)
149		{
150		ide_controller_device::write_cs0(space, (offset * 2), data, mem_mask);
151
152		if (offset == 0 && ACCESSING_BITS_16_31)
153		ata_interface_device::write_cs0(space, (offset * 2), data >> 16, mem_mask >> 16);
154		}
155		else if (ACCESSING_BITS_16_31)
156		{
157		ide_controller_device::write_cs0(space, (offset * 2) + 1, data >> 16, mem_mask >> 16);
158		}
159		}
160
161		WRITE32_MEMBER(vt83c461_device::write_cs1)
162		{
163		//   printf( "vt83c461 write cs1 %08x %08x %08x\n", offset, data, mem_mask );
164
165		if (ACCESSING_BITS_0_7)
166		{
167		ide_controller_device::write_cs1(space, (offset * 2), data, mem_mask);
168		}
169		else if (ACCESSING_BITS_16_23)
170		{
171		ide_controller_device::write_cs1(space, (offset * 2) + 1, data >> 16, mem_mask >> 16);
172		}
173		}

trunk/src/emu/machine/vt83c461.h

r23868	r23869
28	28
29	29	#define IDE_CONFIG_REGISTERS                0x10
30	30
31		class vt83c461_device : public ide_controller_device
	31	class vt83c461_device : public ide_controller_32_device
32	32	{
33	33	public:
34	34	vt83c461_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
r23868	r23869
36	36	DECLARE_READ32_MEMBER(read_config);
37	37	DECLARE_WRITE32_MEMBER(write_config);
38	38
39		virtual DECLARE_READ32_MEMBER(read_cs0);
40		virtual DECLARE_READ32_MEMBER(read_cs1);
41		virtual DECLARE_WRITE32_MEMBER(write_cs0);
42		virtual DECLARE_WRITE32_MEMBER(write_cs1);
43
44	39	protected:
45	40	virtual void device_start();
46	41
47	42	private:
48		using ide_controller_device::read_cs0;
49		using ide_controller_device::read_cs1;
50		using ide_controller_device::write_cs0;
51		using ide_controller_device::write_cs1;
52
53	43	UINT8           m_config_unknown;
54	44	UINT8           m_config_register[IDE_CONFIG_REGISTERS];
55	45	UINT8           m_config_register_num;

trunk/src/emu/machine/idectrl.c

r23868	r23869
39	39
40	40	READ16_MEMBER( ide_controller_device::read_cs0 )
41	41	{
	42	if (mem_mask == 0xffff && offset == 1 ){ offset = 0; popmessage( "requires ide_controller_32_device" ); }
42	43	if (mem_mask == 0xff00)
43	44	{
44	45	return ata_interface_device::read_cs0(space, (offset * 2) + 1, 0xff) << 8;
r23868	r23869
63	64
64	65	WRITE16_MEMBER( ide_controller_device::write_cs0 )
65	66	{
	67	if (mem_mask == 0xffff && offset == 1 ){ offset = 0; popmessage( "requires ide_controller_32_device" ); }
66	68	if (mem_mask == 0xff00)
67	69	{
68	70	return ata_interface_device::write_cs0(space, (offset * 2) + 1, data >> 8, 0xff);
r23868	r23869
85	87	}
86	88	}
87	89
	90
	91	const device_type IDE_CONTROLLER_32 = &device_creator<ide_controller_32_device>;
	92
	93	ide_controller_32_device::ide_controller_32_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	94	ide_controller_device(mconfig, IDE_CONTROLLER, "IDE Controller (32 bit)", tag, owner, clock, "ide_controller", __FILE__)
	95	{
	96	}
	97
	98	ide_controller_32_device::ide_controller_32_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) :
	99	ide_controller_device(mconfig, type, name, tag, owner, clock, shortname, source)
	100	{
	101	}
	102
	103	READ32_MEMBER(ide_controller_32_device::read_cs0)
	104	{
	105	UINT32 data = 0;
	106
	107	if (ACCESSING_BITS_0_15)
	108	{
	109	data = ide_controller_device::read_cs0(space, (offset * 2), mem_mask);
	110
	111	if (offset == 0 && ACCESSING_BITS_16_31)
	112	data |= ide_controller_device::read_cs0(space, (offset * 2), mem_mask >> 16) << 16;
	113	}
	114	else if (ACCESSING_BITS_16_31)
	115	{
	116	data = ide_controller_device::read_cs0(space, (offset * 2) + 1, mem_mask >> 16) << 16;
	117	}
	118
	119	return data;
	120	}
	121
	122	READ32_MEMBER(ide_controller_32_device::read_cs1)
	123	{
	124	UINT32 data = 0;
	125
	126	if (ACCESSING_BITS_0_15)
	127	{
	128	data = ide_controller_device::read_cs1(space, (offset * 2), mem_mask);
	129	}
	130	else if (ACCESSING_BITS_16_23)
	131	{
	132	data = ide_controller_device::read_cs1(space, (offset * 2) + 1, mem_mask >> 16) << 16;
	133	}
	134
	135	return data;
	136	}
	137
	138	WRITE32_MEMBER(ide_controller_32_device::write_cs0)
	139	{
	140	if (ACCESSING_BITS_0_15)
	141	{
	142	ide_controller_device::write_cs0(space, (offset * 2), data, mem_mask);
	143
	144	if (offset == 0 && ACCESSING_BITS_16_31)
	145	ata_interface_device::write_cs0(space, (offset * 2), data >> 16, mem_mask >> 16);
	146	}
	147	else if (ACCESSING_BITS_16_31)
	148	{
	149	ide_controller_device::write_cs0(space, (offset * 2) + 1, data >> 16, mem_mask >> 16);
	150	}
	151	}
	152
	153	WRITE32_MEMBER(ide_controller_32_device::write_cs1)
	154	{
	155	if (ACCESSING_BITS_0_7)
	156	{
	157	ide_controller_device::write_cs1(space, (offset * 2), data, mem_mask);
	158	}
	159	else if (ACCESSING_BITS_16_23)
	160	{
	161	ide_controller_device::write_cs1(space, (offset * 2) + 1, data >> 16, mem_mask >> 16);
	162	}
	163	}
	164
	165
88	166	#define IDE_BUSMASTER_STATUS_ACTIVE         0x01
89	167	#define IDE_BUSMASTER_STATUS_ERROR          0x02
90	168	#define IDE_BUSMASTER_STATUS_IRQ            0x04
r23868	r23869
92	170	const device_type BUS_MASTER_IDE_CONTROLLER = &device_creator<bus_master_ide_controller_device>;
93	171
94	172	bus_master_ide_controller_device::bus_master_ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
95		ide_controller_device(mconfig, BUS_MASTER_IDE_CONTROLLER, "Bus Master IDE Controller", tag, owner, clock, "bus_master_ide_controller", __FILE__),
96		dma_address(0),
97		dma_bytes_left(0),
98		dma_descriptor(0),
99		dma_last_buffer(0),
100		bus_master_command(0),
101		bus_master_status(0),
102		bus_master_descriptor(0),
	173	ide_controller_32_device(mconfig, BUS_MASTER_IDE_CONTROLLER, "Bus Master IDE Controller", tag, owner, clock, "bus_master_ide_controller", __FILE__),
	174	m_dma_address(0),
	175	m_dma_bytes_left(0),
	176	m_dma_descriptor(0),
	177	m_dma_last_buffer(0),
	178	m_bus_master_command(0),
	179	m_bus_master_status(0),
	180	m_bus_master_descriptor(0),
103	181	m_irq(0),
104	182	m_dmarq(0)
105	183	{
r23868	r23869
107	185
108	186	void bus_master_ide_controller_device::device_start()
109	187	{
110		ide_controller_device::device_start();
	188	ide_controller_32_device::device_start();
111	189
112	190	/* find the bus master space */
113		if (bmcpu != NULL)
	191	if (m_bmcpu != NULL)
114	192	{
115		device_t *bmtarget = machine().device(bmcpu);
	193	device_t *bmtarget = machine().device(m_bmcpu);
116	194	if (bmtarget == NULL)
117		throw emu_fatalerror("IDE controller '%s' bus master target '%s' doesn't exist!", tag(), bmcpu);
	195	throw emu_fatalerror("IDE controller '%s' bus master target '%s' doesn't exist!", tag(), m_bmcpu);
118	196	device_memory_interface *memory;
119	197	if (!bmtarget->interface(memory))
120		throw emu_fatalerror("IDE controller '%s' bus master target '%s' has no memory!", tag(), bmcpu);
121		dma_space = &memory->space(bmspace);
122		dma_address_xor = (dma_space->endianness() == ENDIANNESS_LITTLE) ? 0 : 3;
	198	throw emu_fatalerror("IDE controller '%s' bus master target '%s' has no memory!", tag(), m_bmcpu);
	199	m_dma_space = &memory->space(m_bmspace);
	200	m_dma_address_xor = (m_dma_space->endianness() == ENDIANNESS_LITTLE) ? 0 : 3;
123	201	}
124	202
125		save_item(NAME(dma_address));
126		save_item(NAME(dma_bytes_left));
127		save_item(NAME(dma_descriptor));
128		save_item(NAME(dma_last_buffer));
129		save_item(NAME(bus_master_command));
130		save_item(NAME(bus_master_status));
131		save_item(NAME(bus_master_descriptor));
	203	save_item(NAME(m_dma_address));
	204	save_item(NAME(m_dma_bytes_left));
	205	save_item(NAME(m_dma_descriptor));
	206	save_item(NAME(m_dma_last_buffer));
	207	save_item(NAME(m_bus_master_command));
	208	save_item(NAME(m_bus_master_status));
	209	save_item(NAME(m_bus_master_descriptor));
132	210	}
133	211
134	212	void bus_master_ide_controller_device::set_irq(int state)
r23868	r23869
140	218	m_irq = state;
141	219
142	220	if( m_irq )
143		bus_master_status |= IDE_BUSMASTER_STATUS_IRQ;
	221	m_bus_master_status |= IDE_BUSMASTER_STATUS_IRQ;
144	222	}
145	223	}
146	224
r23868	r23869
162	240	*
163	241	*************************************/
164	242
165		READ32_MEMBER( bus_master_ide_controller_device::ide_bus_master32_r )
	243	READ32_MEMBER( bus_master_ide_controller_device::bmdma_r )
166	244	{
167	245	LOG(("%s:ide_bus_master32_r(%d, %08x)\n", machine().describe_context(), offset, mem_mask));
168	246
r23868	r23869
170	248	{
171	249	case 0:
172	250	/* command register/status register */
173		return bus_master_command | (bus_master_status << 16);
	251	return m_bus_master_command | (m_bus_master_status << 16);
174	252
175	253	case 1:
176	254	/* descriptor table register */
177		return bus_master_descriptor;
	255	return m_bus_master_descriptor;
178	256	}
179	257
180	258	return 0xffffffff;
r23868	r23869
188	266	*
189	267	*************************************/
190	268
191		WRITE32_MEMBER( bus_master_ide_controller_device::ide_bus_master32_w )
	269	WRITE32_MEMBER( bus_master_ide_controller_device::bmdma_w )
192	270	{
193	271	LOG(("%s:ide_bus_master32_w(%d, %08x, %08X)\n", machine().describe_context(), offset, mem_mask, data));
194	272
r23868	r23869
198	276	if( ACCESSING_BITS_0_7 )
199	277	{
200	278	/* command register */
201		UINT8 old = bus_master_command;
	279	UINT8 old = m_bus_master_command;
202	280	UINT8 val = data & 0xff;
203	281
204	282	/* save the read/write bit and the start/stop bit */
205		bus_master_command = (old & 0xf6) | (val & 0x09);
	283	m_bus_master_command = (old & 0xf6) | (val & 0x09);
206	284
207		if ((old ^ bus_master_command) & 1)
	285	if ((old ^ m_bus_master_command) & 1)
208	286	{
209		if (bus_master_command & 1)
	287	if (m_bus_master_command & 1)
210	288	{
211	289	/* handle starting a transfer */
212		bus_master_status |= IDE_BUSMASTER_STATUS_ACTIVE;
	290	m_bus_master_status |= IDE_BUSMASTER_STATUS_ACTIVE;
213	291
214	292	/* reset all the DMA data */
215		dma_bytes_left = 0;
216		dma_descriptor = bus_master_descriptor;
	293	m_dma_bytes_left = 0;
	294	m_dma_descriptor = m_bus_master_descriptor;
217	295
218	296	/* if we're going live, start the pending read/write */
219	297	execute_dma();
220	298	}
221		else if (bus_master_status & IDE_BUSMASTER_STATUS_ACTIVE)
	299	else if (m_bus_master_status & IDE_BUSMASTER_STATUS_ACTIVE)
222	300	{
223		bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE;
	301	m_bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE;
224	302
225	303	LOG(("DMA Aborted!\n"));
226	304	}
r23868	r23869
230	308	if( ACCESSING_BITS_16_23 )
231	309	{
232	310	/* status register */
233		UINT8 old = bus_master_status;
	311	UINT8 old = m_bus_master_status;
234	312	UINT8 val = data >> 16;
235	313
236	314	/* save the DMA capable bits */
237		bus_master_status = (old & 0x9f) | (val & 0x60);
	315	m_bus_master_status = (old & 0x9f) | (val & 0x60);
238	316
239	317	/* clear interrupt and error bits */
240	318	if (val & IDE_BUSMASTER_STATUS_IRQ)
241		bus_master_status &= ~IDE_BUSMASTER_STATUS_IRQ;
	319	m_bus_master_status &= ~IDE_BUSMASTER_STATUS_IRQ;
242	320	if (val & IDE_BUSMASTER_STATUS_ERROR)
243		bus_master_status &= ~IDE_BUSMASTER_STATUS_ERROR;
	321	m_bus_master_status &= ~IDE_BUSMASTER_STATUS_ERROR;
244	322	}
245	323	break;
246	324
247	325	case 1:
248	326	/* descriptor table register */
249		bus_master_descriptor = data & 0xfffffffc;
	327	m_bus_master_descriptor = data & 0xfffffffc;
250	328	break;
251	329	}
252	330	}
r23868	r23869
255	333	{
256	334	write_dmack(ASSERT_LINE);
257	335
258		while (m_dmarq && (bus_master_status & IDE_BUSMASTER_STATUS_ACTIVE))
	336	while (m_dmarq && (m_bus_master_status & IDE_BUSMASTER_STATUS_ACTIVE))
259	337	{
260	338	/* if we're out of space, grab the next descriptor */
261		if (dma_bytes_left == 0)
	339	if (m_dma_bytes_left == 0)
262	340	{
263	341	/* fetch the address */
264		dma_address = dma_space->read_byte(dma_descriptor++ ^ dma_address_xor);
265		dma_address |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 8;
266		dma_address |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 16;
267		dma_address |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 24;
268		dma_address &= 0xfffffffe;
	342	m_dma_address = m_dma_space->read_byte(m_dma_descriptor++ ^ m_dma_address_xor);
	343	m_dma_address |= m_dma_space->read_byte(m_dma_descriptor++ ^ m_dma_address_xor) << 8;
	344	m_dma_address |= m_dma_space->read_byte(m_dma_descriptor++ ^ m_dma_address_xor) << 16;
	345	m_dma_address |= m_dma_space->read_byte(m_dma_descriptor++ ^ m_dma_address_xor) << 24;
	346	m_dma_address &= 0xfffffffe;
269	347
270	348	/* fetch the length */
271		dma_bytes_left = dma_space->read_byte(dma_descriptor++ ^ dma_address_xor);
272		dma_bytes_left |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 8;
273		dma_bytes_left |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 16;
274		dma_bytes_left |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 24;
275		dma_last_buffer = (dma_bytes_left >> 31) & 1;
276		dma_bytes_left &= 0xfffe;
277		if (dma_bytes_left == 0)
278		dma_bytes_left = 0x10000;
	349	m_dma_bytes_left = m_dma_space->read_byte(m_dma_descriptor++ ^ m_dma_address_xor);
	350	m_dma_bytes_left |= m_dma_space->read_byte(m_dma_descriptor++ ^ m_dma_address_xor) << 8;
	351	m_dma_bytes_left |= m_dma_space->read_byte(m_dma_descriptor++ ^ m_dma_address_xor) << 16;
	352	m_dma_bytes_left |= m_dma_space->read_byte(m_dma_descriptor++ ^ m_dma_address_xor) << 24;
	353	m_dma_last_buffer = (m_dma_bytes_left >> 31) & 1;
	354	m_dma_bytes_left &= 0xfffe;
	355	if (m_dma_bytes_left == 0)
	356	m_dma_bytes_left = 0x10000;
279	357
280		//          LOG(("New DMA descriptor: address = %08X  bytes = %04X  last = %d\n", dma_address, dma_bytes_left, dma_last_buffer));
	358	//          LOG(("New DMA descriptor: address = %08X  bytes = %04X  last = %d\n", m_dma_address, m_dma_bytes_left, m_dma_last_buffer));
281	359	}
282	360
283		if (bus_master_command & 8)
	361	if (m_bus_master_command & 8)
284	362	{
285	363	// read from ata bus
286	364	UINT16 data = read_dma();
287	365
288	366	// write to memory
289		dma_space->write_byte(dma_address++, data & 0xff);
290		dma_space->write_byte(dma_address++, data >> 8);
	367	m_dma_space->write_byte(m_dma_address++, data & 0xff);
	368	m_dma_space->write_byte(m_dma_address++, data >> 8);
291	369	}
292	370	else
293	371	{
294	372	// read from memory;
295		UINT16 data = dma_space->read_byte(dma_address++);
296		data |= dma_space->read_byte(dma_address++) << 8;
	373	UINT16 data = m_dma_space->read_byte(m_dma_address++);
	374	data |= m_dma_space->read_byte(m_dma_address++) << 8;
297	375
298	376	// write to ata bus
299	377	write_dma(data);
300	378	}
301	379
302		dma_bytes_left -= 2;
	380	m_dma_bytes_left -= 2;
303	381
304		if (dma_bytes_left == 0 && dma_last_buffer)
	382	if (m_dma_bytes_left == 0 && m_dma_last_buffer)
305	383	{
306		bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE;
	384	m_bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE;
307	385
308	386	if (m_dmarq)
309	387	{

trunk/src/emu/machine/idectrl.h

r23868	r23869
41	41	extern const device_type IDE_CONTROLLER;
42	42
43	43
	44	#define MCFG_IDE_CONTROLLER_32_ADD(_tag, _slotintf, _master, _slave, _fixed) \
	45	MCFG_DEVICE_ADD(_tag, IDE_CONTROLLER_32, 0) \
	46	MCFG_ATA_SLOT_ADD(_tag ":0", _slotintf, _master, _fixed) \
	47	MCFG_ATA_SLOT_ADD(_tag ":1", _slotintf, _slave, _fixed) \
	48	MCFG_DEVICE_MODIFY(_tag)
	49
	50	class ide_controller_32_device : public ide_controller_device
	51	{
	52	public:
	53	ide_controller_32_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	54	ide_controller_32_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
	55
	56	virtual DECLARE_READ32_MEMBER(read_cs0);
	57	virtual DECLARE_READ32_MEMBER(read_cs1);
	58	virtual DECLARE_WRITE32_MEMBER(write_cs0);
	59	virtual DECLARE_WRITE32_MEMBER(write_cs1);
	60
	61	private:
	62	using ide_controller_device::read_cs0;
	63	using ide_controller_device::read_cs1;
	64	using ide_controller_device::write_cs0;
	65	using ide_controller_device::write_cs1;
	66	};
	67
	68	extern const device_type IDE_CONTROLLER_32;
	69
	70
44	71	#define MCFG_BUS_MASTER_IDE_CONTROLLER_ADD(_tag, _slotintf, _master, _slave, _fixed) \
45	72	MCFG_DEVICE_ADD(_tag, BUS_MASTER_IDE_CONTROLLER, 0) \
46	73	MCFG_ATA_SLOT_ADD(_tag ":0", _slotintf, _master, _fixed) \
r23868	r23869
50	77	#define MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(bmcpu, bmspace) \
51	78	bus_master_ide_controller_device::set_bus_master_space(*device, bmcpu, bmspace);
52	79
53		class bus_master_ide_controller_device : public ide_controller_device
	80	class bus_master_ide_controller_device : public ide_controller_32_device
54	81	{
55	82	public:
56	83	bus_master_ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
57		static void set_bus_master_space(device_t &device, const char *bmcpu, UINT32 bmspace) {bus_master_ide_controller_device &ide = downcast<bus_master_ide_controller_device &>(device); ide.bmcpu = bmcpu; ide.bmspace = bmspace; }
	84	static void set_bus_master_space(device_t &device, const char *bmcpu, UINT32 bmspace) {bus_master_ide_controller_device &ide = downcast<bus_master_ide_controller_device &>(device); ide.m_bmcpu = bmcpu; ide.m_bmspace = bmspace; }
58	85
59		DECLARE_READ32_MEMBER( ide_bus_master32_r );
60		DECLARE_WRITE32_MEMBER( ide_bus_master32_w );
	86	DECLARE_READ32_MEMBER( bmdma_r );
	87	DECLARE_WRITE32_MEMBER( bmdma_w );
61	88
62	89	protected:
63	90	virtual void device_start();
r23868	r23869
68	95	private:
69	96	void execute_dma();
70	97
71		const char *bmcpu;
72		UINT32 bmspace;
73		address_space * dma_space;
74		UINT8           dma_address_xor;
	98	const char *m_bmcpu;
	99	UINT32 m_bmspace;
	100	address_space * m_dma_space;
	101	UINT8 m_dma_address_xor;
75	102
76		offs_t          dma_address;
77		UINT32          dma_bytes_left;
78		offs_t          dma_descriptor;
79		UINT8           dma_last_buffer;
80		UINT8           bus_master_command;
81		UINT8           bus_master_status;
82		UINT32          bus_master_descriptor;
	103	offs_t m_dma_address;
	104	UINT32 m_dma_bytes_left;
	105	offs_t m_dma_descriptor;
	106	UINT8 m_dma_last_buffer;
	107	UINT8 m_bus_master_command;
	108	UINT8 m_bus_master_status;
	109	UINT32 m_bus_master_descriptor;
83	110	int m_irq;
84	111	int m_dmarq;
85	112	};

trunk/src/mame/drivers/chihiro.c

r23868	r23869
2949	2949	AM_RANGE(0x0020, 0x0023) AM_DEVREADWRITE8("pic8259_1", pic8259_device, read, write, 0xffffffff)
2950	2950	AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("pit8254", pit8254_device, read, write, 0xffffffff)
2951	2951	AM_RANGE(0x00a0, 0x00a3) AM_DEVREADWRITE8("pic8259_2", pic8259_device, read, write, 0xffffffff)
2952		AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", bus_master_ide_controller_device, read_cs0, write_cs0, 0xffffffff)
	2952	AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, read_cs0, write_cs0)
2953	2953	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
2954	2954	AM_RANGE(0x8000, 0x80ff) AM_READWRITE(dummy_r, dummy_w)
2955	2955	AM_RANGE(0xc000, 0xc0ff) AM_READWRITE(smbus_r, smbus_w)
2956		AM_RANGE(0xff60, 0xff67) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, ide_bus_master32_r, ide_bus_master32_w)
	2956	AM_RANGE(0xff60, 0xff67) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, bmdma_r, bmdma_w)
2957	2957	ADDRESS_MAP_END
2958	2958
2959	2959	static INPUT_PORTS_START( chihiro )

trunk/src/mame/drivers/vegas.c

r23868	r23869
1459	1459	static READ32_DEVICE_HANDLER( ide_main_r )
1460	1460	{
1461	1461	bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1462
1463		UINT32 data = 0;
1464		if (ACCESSING_BITS_0_15)
1465		data |= ide->read_cs0(space, offset * 2, mem_mask);
1466		if (ACCESSING_BITS_16_31)
1467		data |= ide->read_cs0(space, (offset * 2) + 1, mem_mask >> 16) << 16;
1468
1469		return data;
	1462	return ide->read_cs0(space, offset, mem_mask);
1470	1463	}
1471	1464
1472	1465
1473	1466	static WRITE32_DEVICE_HANDLER( ide_main_w )
1474	1467	{
1475	1468	bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1476
1477		if (ACCESSING_BITS_0_15)
1478		ide->write_cs0(space, offset * 2, data, mem_mask);
1479		if (ACCESSING_BITS_16_31)
1480		ide->write_cs0(space, (offset * 2) + 1, data >> 16, mem_mask >> 16);
	1469	ide->write_cs0(space, offset, data, mem_mask);
1481	1470	}
1482	1471
1483	1472
1484	1473	static READ32_DEVICE_HANDLER( ide_alt_r )
1485	1474	{
1486	1475	bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1487
1488		UINT32 data = 0;
1489		if (ACCESSING_BITS_0_15)
1490		data |= ide->read_cs1(space, (4/2) + (offset * 2), mem_mask);
1491		if (ACCESSING_BITS_16_31)
1492		data |= ide->read_cs1(space, (4/2) + (offset * 2) + 1, mem_mask >> 16) << 16;
1493
1494		return data;
	1476	return ide->read_cs1(space, offset + 1, mem_mask);
1495	1477	}
1496	1478
1497	1479
1498	1480	static WRITE32_DEVICE_HANDLER( ide_alt_w )
1499	1481	{
1500	1482	bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1501
1502		if (ACCESSING_BITS_0_15)
1503		ide->write_cs1(space, 6/2 + offset * 2, data, mem_mask);
1504		if (ACCESSING_BITS_16_31)
1505		ide->write_cs1(space, 6/2 + (offset * 2) + 1, data >> 16, mem_mask >> 16);
	1483	ide->write_cs1(space, offset + 1, data, mem_mask);
1506	1484	}
1507	1485
1508	1486
1509	1487	static READ32_DEVICE_HANDLER( ide_bus_master32_r )
1510	1488	{
1511	1489	bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1512		return ide->ide_bus_master32_r(space, offset, mem_mask);
	1490	return ide->bmdma_r(space, offset, mem_mask);
1513	1491	}
1514	1492
1515	1493
1516	1494	static WRITE32_DEVICE_HANDLER( ide_bus_master32_w )
1517	1495	{
1518	1496	bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1519		ide->ide_bus_master32_w(space, offset, data, mem_mask);
	1497	ide->bmdma_w(space, offset, data, mem_mask);
1520	1498	}
1521	1499
1522	1500

trunk/src/mame/drivers/seattle.c

r23868	r23869
482	482	DECLARE_WRITE32_MEMBER(ethernet_w);
483	483	DECLARE_READ32_MEMBER(widget_r);
484	484	DECLARE_WRITE32_MEMBER(widget_w);
485		DECLARE_READ16_MEMBER(seattle_ide_r);
	485	DECLARE_READ32_MEMBER(seattle_ide_r);
486	486	DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
487	487	DECLARE_WRITE_LINE_MEMBER(vblank_assert);
488	488	DECLARE_WRITE_LINE_MEMBER(voodoo_stall);
r23868	r23869
1773	1773
1774	1774	*/
1775	1775
1776		READ16_MEMBER(seattle_state::seattle_ide_r)
	1776	READ32_MEMBER(seattle_state::seattle_ide_r)
1777	1777	{
1778	1778	/* note that blitz times out if we don't have this cycle stealing */
1779		if (offset == 6/2)
	1779	if (offset == 6/4)
1780	1780	m_maincpu->eat_cycles(100);
1781	1781	return m_ide->read_cs1(space, offset, mem_mask);
1782	1782	}
r23868	r23869
1785	1785	ADDRESS_MAP_UNMAP_HIGH
1786	1786	AM_RANGE(0x00000000, 0x007fffff) AM_RAM AM_SHARE("rambase") // wg3dh only has 4MB; sfrush, blitz99 8MB
1787	1787	AM_RANGE(0x08000000, 0x08ffffff) AM_DEVREAD_LEGACY("voodoo", voodoo_r) AM_WRITE(seattle_voodoo_w)
1788		AM_RANGE(0x0a0001f0, 0x0a0001f7) AM_DEVREADWRITE16("ide", bus_master_ide_controller_device, read_cs0, write_cs0, 0xffffffff)
1789		AM_RANGE(0x0a0003f0, 0x0a0003f7) AM_READ16(seattle_ide_r, 0xffffffff) AM_DEVWRITE16("ide", bus_master_ide_controller_device, write_cs1, 0xffffffff)
	1788	AM_RANGE(0x0a0001f0, 0x0a0001f7) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, read_cs0, write_cs0)
	1789	AM_RANGE(0x0a0003f0, 0x0a0003f7) AM_READ(seattle_ide_r) AM_DEVWRITE("ide", bus_master_ide_controller_device, write_cs1)
1790	1790	AM_RANGE(0x0a00040c, 0x0a00040f) AM_NOP                     // IDE-related, but annoying
1791		AM_RANGE(0x0a000f00, 0x0a000f07) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, ide_bus_master32_r, ide_bus_master32_w)
	1791	AM_RANGE(0x0a000f00, 0x0a000f07) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, bmdma_r, bmdma_w)
1792	1792	AM_RANGE(0x0c000000, 0x0c000fff) AM_READWRITE(galileo_r, galileo_w)
1793	1793	AM_RANGE(0x13000000, 0x13000003) AM_WRITE(asic_fifo_w)
1794	1794	AM_RANGE(0x16000000, 0x1600003f) AM_READWRITE_LEGACY(midway_ioasic_r, midway_ioasic_w)

trunk/src/mame/drivers/savquest.c

r23868	r23869
613	613
614	614	AM_RANGE(0x00e8, 0x00ef) AM_NOP
615	615
616		AM_RANGE(0x0170, 0x0177) AM_DEVREADWRITE16("ide2", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
617		AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
	616	AM_RANGE(0x0170, 0x0177) AM_DEVREADWRITE("ide2", ide_controller_32_device, read_cs0, write_cs0)
	617	AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs0, write_cs0)
618	618	AM_RANGE(0x0378, 0x037b) AM_READWRITE(parallel_port_r, parallel_port_w)
619	619	AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
620	620	AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
621	621	AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
622		AM_RANGE(0x0370, 0x0377) AM_DEVREADWRITE16("ide2", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
623		AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
	622	AM_RANGE(0x0370, 0x0377) AM_DEVREADWRITE("ide2", ide_controller_32_device, read_cs1, write_cs1)
	623	AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs1, write_cs1)
624	624
625	625	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
626	626
r23868	r23869
682	682	MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
683	683	MCFG_PCI_BUS_LEGACY_DEVICE(7, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
684	684
685		MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	685	MCFG_IDE_CONTROLLER_32_ADD("ide", ata_devices, "hdd", NULL, true)
686	686	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
687	687
688		MCFG_IDE_CONTROLLER_ADD("ide2", ata_devices, NULL, NULL, true)
	688	MCFG_IDE_CONTROLLER_32_ADD("ide2", ata_devices, NULL, NULL, true)
689	689	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir7_w))
690	690
691	691	/* video hardware */

trunk/src/mame/drivers/mediagx.c

r23868	r23869
92	92	m_bios_ram(*this, "bios_ram"),
93	93	m_vram(*this, "vram") { }
94	94
95		required_device<ide_controller_device> m_ide;
	95	required_device<ide_controller_32_device> m_ide;
96	96	required_shared_ptr<UINT32> m_main_ram;
97	97	required_shared_ptr<UINT32> m_cga_ram;
98	98	required_shared_ptr<UINT32> m_bios_ram;
r23868	r23869
750	750	AM_RANGE(0x0020, 0x0023) AM_READWRITE8(io20_r, io20_w, 0xffff0000)
751	751	AM_IMPORT_FROM(pcat32_io_common)
752	752	AM_RANGE(0x00e8, 0x00eb) AM_NOP     // I/O delay port
753		AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
	753	AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs0, write_cs0)
754	754	AM_RANGE(0x0378, 0x037b) AM_READWRITE(parallel_port_r, parallel_port_w)
755		AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
	755	AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs1, write_cs1)
756	756	AM_RANGE(0x0400, 0x04ff) AM_READWRITE(ad1847_r, ad1847_w)
757	757	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
758	758	ADDRESS_MAP_END
r23868	r23869
881	881	MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
882	882	MCFG_PCI_BUS_LEGACY_DEVICE(18, NULL, cx5510_pci_r, cx5510_pci_w)
883	883
884		MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	884	MCFG_IDE_CONTROLLER_32_ADD("ide", ata_devices, "hdd", NULL, true)
885	885	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
886	886
887	887	MCFG_TIMER_DRIVER_ADD("sound_timer", mediagx_state, sound_timer_callback)

trunk/src/mame/drivers/calchase.c

r23868	r23869
409	409	//AM_RANGE(0x00e8, 0x00eb) AM_NOP
410	410	AM_RANGE(0x00e8, 0x00ef) AM_NOP //AMI BIOS write to this ports as delays between I/O ports operations sending al value -> NEWIODELAY
411	411	AM_RANGE(0x0170, 0x0177) AM_NOP //To debug
412		AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
	412	AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs0, write_cs0)
413	413	AM_RANGE(0x0200, 0x021f) AM_NOP //To debug
414	414	AM_RANGE(0x0260, 0x026f) AM_NOP //To debug
415	415	AM_RANGE(0x0278, 0x027b) AM_WRITENOP//AM_WRITE(pnp_config_w)
r23868	r23869
428	428	AM_RANGE(0x0378, 0x037f) AM_NOP //To debug
429	429	// AM_RANGE(0x0300, 0x03af) AM_NOP
430	430	// AM_RANGE(0x03b0, 0x03df) AM_NOP
431		AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
	431	AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs1, write_cs1)
432	432	AM_RANGE(0x03f8, 0x03ff) AM_NOP // To debug Serial Port COM1:
433	433	AM_RANGE(0x0a78, 0x0a7b) AM_WRITENOP//AM_WRITE(pnp_data_w)
434	434	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
r23868	r23869
644	644
645	645	MCFG_FRAGMENT_ADD( pcat_common )
646	646
647		MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	647	MCFG_IDE_CONTROLLER_32_ADD("ide", ata_devices, "hdd", NULL, true)
648	648	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
649	649
650	650	MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)

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