Previous

199869 Revisions

Next

r23792 Wednesday 19th June, 2013 at 13:23:20 UTC by Miodrag Milanović
(MESS)-bml3: split into three variants (bml3, bml3a and bml3b) according to floppy disk support. Only bml3a (5.25" disk) is considered working. [jedwidz] -m6809: Initially setting S with a 'TFR *,S' evidently should enable NMI [jedwidz] -mc6845: Add rudimentary support for 'interlace and video' mode [jedwidz]

[src/emu/cpu/m6809]	m6809.ops
[src/emu/video]	mc6845.c
[src/lib]	lib.mak
[src/lib/formats]	bml3_dsk.c bml3_dsk.h
[src/mess]	mess.lst
[src/mess/drivers]	bml3.c

trunk/src/lib/formats/bml3_dsk.c

r23791	r23792
1		/*********************************************************************
2
3		formats/bml3_dsk.c
4
5		BML3 disk images
6
7		*********************************************************************/
8
9		#include <string.h>
10
11		#include "bml3_dsk.h"
12		#include "basicdsk.h"
13
14		static FLOPPY_IDENTIFY(bml3_dsk_identify)
15		{
16		*vote = 100;
17		return FLOPPY_ERROR_SUCCESS;
18		}
19
20		static FLOPPY_CONSTRUCT(bml3_dsk_construct)
21		{
22		struct basicdsk_geometry geometry;
23
24		memset(&geometry, 0, sizeof(geometry));
25		geometry.heads = 2;
26		geometry.first_sector_id = 1;
27		geometry.sector_length = 256;
28		geometry.tracks = 40;
29		geometry.sectors = 16;
30		return basicdsk_construct(floppy, &geometry);
31		}
32
33
34
35		/* ----------------------------------------------------------------------- */
36
37
38		LEGACY_FLOPPY_OPTIONS_START( bml3 )
39		LEGACY_FLOPPY_OPTION( bml3_dsk, "bm3",      "BML3 floppy disk image",   bml3_dsk_identify, bml3_dsk_construct, NULL,
40		HEADS([2])
41		TRACKS([40])
42		SECTORS([16])
43		SECTOR_LENGTH([256])
44		FIRST_SECTOR_ID([1]))
45		LEGACY_FLOPPY_OPTIONS_END

trunk/src/lib/formats/bml3_dsk.h

r23791	r23792
1		/*********************************************************************
2
3		formats/bml3_dsk.h
4
5		BML3 disk images
6
7		*********************************************************************/
8
9		#ifndef BML3_DSK_H
10		#define BML3_DSK_H
11
12		#include "flopimg.h"
13
14		/**************************************************************************/
15
16		LEGACY_FLOPPY_OPTIONS_EXTERN(bml3);
17
18		#endif /* BML3_DSK_H */

trunk/src/lib/lib.mak

r23791	r23792
109	109	$(LIBOBJ)/formats/atari_dsk.o   \
110	110	$(LIBOBJ)/formats/atarist_dsk.o \
111	111	$(LIBOBJ)/formats/atom_tap.o    \
112		$(LIBOBJ)/formats/bml3_dsk.o    \
113	112	$(LIBOBJ)/formats/bw2_dsk.o     \
114	113	$(LIBOBJ)/formats/bw12_dsk.o    \
115	114	$(LIBOBJ)/formats/cbm_tap.o     \

trunk/src/emu/cpu/m6809/m6809.ops

r23791	r23792
570	570	UINT8 param = read_opcode_arg();
571	571	exgtfr_register reg = read_exgtfr_register(param >> 4);
572	572	write_exgtfr_register(param >> 0, reg);
	573	if ((param & 0x0F) == 4) {
	574	m_lds_encountered = true;
	575	}
573	576	}
574	577	eat(hd6309_native_mode() ? 2 : 4);
575	578	return;

trunk/src/emu/video/mc6845.c

r23791	r23792
28	28
29	29	- Change device video emulation x/y offsets when "show border color"
30	30	is true
	31	- Support 'interlace and video' mode
31	32
32	33	- mos8563
33	34
r23791	r23792
68	69	#define MODE_CURSOR_SKEW            ((m_mode_control & 0x20) != 0)
69	70	#define MODE_DISPLAY_ENABLE_SKEW    ((m_mode_control & 0x10) != 0)
70	71	#define MODE_ROW_COLUMN_ADDRESSING  ((m_mode_control & 0x04) != 0)
	72	#define MODE_INTERLACE_AND_VIDEO    ((m_mode_control & 0x03) == 3)
71	73
72	74	#define VSS_CBRATE                  BIT(m_vert_scroll, 5)
73	75	#define VSS_RVS                     BIT(m_vert_scroll, 6)
r23791	r23792
455	457	void mc6845_device::recompute_parameters(bool postload)
456	458	{
457	459	UINT16 hsync_on_pos, hsync_off_pos, vsync_on_pos, vsync_off_pos;
	460	UINT16 video_char_height = (MODE_INTERLACE_AND_VIDEO ? m_max_ras_addr + 1 : m_max_ras_addr) + 1;
	461	// Would be useful for 'interlace and video' mode support...
	462	// UINT16 frame_char_height = (MODE_INTERLACE_AND_VIDEO ? m_max_ras_addr / 2 : m_max_ras_addr) + 1;
458	463
459	464	/* compute the screen sizes */
460	465	UINT16 horiz_pix_total = (m_horiz_char_total + 1) * m_hpixels_per_column;
461		UINT16 vert_pix_total = (m_vert_char_total + 1) * (m_max_ras_addr + 1) + m_vert_total_adj;
	466	UINT16 vert_pix_total = (m_vert_char_total + 1) * video_char_height + m_vert_total_adj;
462	467
463	468	/* determine the visible area, avoid division by 0 */
464	469	UINT16 max_visible_x = m_horiz_disp * m_hpixels_per_column - 1;
465		UINT16 max_visible_y = m_vert_disp * (m_max_ras_addr + 1) - 1;
	470	UINT16 max_visible_y = m_vert_disp * video_char_height - 1;
466	471
467	472	/* determine the syncing positions */
468	473	UINT8 horiz_sync_char_width = m_sync_width & 0x0f;
r23791	r23792
479	484
480	485	hsync_on_pos = m_horiz_sync_pos * m_hpixels_per_column;
481	486	hsync_off_pos = hsync_on_pos + (horiz_sync_char_width * m_hpixels_per_column);
482		vsync_on_pos = m_vert_sync_pos * (m_max_ras_addr + 1);
	487	vsync_on_pos = m_vert_sync_pos * video_char_height;
483	488	vsync_off_pos = vsync_on_pos + vert_sync_pix_width;
484	489
485	490	/* the Commodore PET computers program a horizontal synch pulse that extends
r23791	r23792
639	644	}
640	645	}
641	646
642		if ( m_raster_counter == m_max_ras_addr )
	647	// For rudimentary 'interlace and video' support, m_raster_counter increments by 1 rather than the correct 2.
	648	// The correct test would be:
	649	// if ( m_raster_counter == m_max_ras_addr )
	650	if ( m_raster_counter == (MODE_INTERLACE_AND_VIDEO ? m_max_ras_addr + 1 : m_max_ras_addr) )
643	651	{
644	652	/* Check if we have reached the end of the vertical area */
645	653	if ( m_line_counter == m_vert_char_total )
r23791	r23792
669	677	}
670	678	else
671	679	{
	680	// For rudimentary 'interlace and video' support, m_raster_counter increments by 1 rather than the correct 2.
	681	// m_raster_counter = ( m_raster_counter + (MODE_INTERLACE_AND_VIDEO ? 2 : 1) ) & 0x1F;
672	682	m_raster_counter = ( m_raster_counter + 1 ) & 0x1F;
673	683	}
674	684

trunk/src/mess/mess.lst

r23791	r23792
2089	2089	rx78
2090	2090	bmjr
2091	2091	bml3
	2092	bml3a
	2093	bml3b
2092	2094	b16
2093	2095	psioncm
2094	2096	psionla

trunk/src/mess/drivers/bml3.c

r23791	r23792
2	2
3	3	Basic Master Level 3 (MB-6890) (c) 1980 Hitachi
4	4
5		preliminary driver by Angelo Salese
	5	Driver by Angelo Salese, Jonathan Edwards and Christopher Edwards
6	6
7	7	TODO:
8		- keyboard is actually tied to crtc hsync timer
9		- understand how to load a tape
10		- some NEWON commands now makes the keyboard to not work anymore (it does if you
11		soft reset)
12		- video bugs for the interlaced video modes.
13		- LINE command doesn't work? It says "type mismatch"
	8	- tape support
	9	- disk support in bml3b machine
14	10
15		NOTES:
16		- NEWON changes the video mode, they are:
17		0: 320 x 200, bit 5 active
18		1: 320 x 200, bit 5 unactive
19		2: 320 x 375, bit 5 active
20		3: 320 x 375, bit 5 unactive
21		4: 640 x 200, bit 5 active
22		5: 640 x 200, bit 5 unactive
23		6: 640 x 375, bit 5 active
24		7: 640 x 375, bit 5 unactive
25		8-15: same as above plus sets bit 4
26		16-31: same as above plus shows the bar at the bottom
27
28	11	**************************************************************************************/
29	12
30	13	#include "emu.h"
31	14	#include "cpu/m6809/m6809.h"
32	15	#include "video/mc6845.h"
33		// #$# ? remove if not using proper mc6843?
34		// #include "machine/mc6843.h"
	16	#include "machine/wd_fdc.h"
	17	#include "machine/mc6843.h"
35	18	#include "sound/beep.h"
36	19	#include "machine/6821pia.h"
37	20	#include "machine/6850acia.h"
r23791	r23792
39	22
40	23	//#include "imagedev/cassette.h"
41	24	#include "imagedev/flopdrv.h"
42		// #$# ? needed
43		// #include "formats/basicdsk.h"
44		#include "formats/bml3_dsk.h"
45		#include "machine/wd17xx.h"
	25	//#include "formats/basicdsk.h"
	26	//#include "imagedev/floppy.h"
46	27
	28	// System clock definitions, from the MB-6890 servce manual, p.48:
	29
	30	#define MASTER_CLOCK ( 32256000 )   // Master clock crystal (X1) frequency, 32.256 MHz.  "fx" in the manual.
	31
	32	#define D80_CLOCK ( MASTER_CLOCK / 2 )   // Graphics dot clock in 80-column mode. ~16 MHz.
	33	#define D40_CLOCK ( D80_CLOCK / 2 )      // Graphics dot clock in 40-column mode.  ~8 MHz.
	34
	35	#define CPU_EXT_CLOCK ( D40_CLOCK / 2 )   // IC37, 4.032 MHz signal to EXTAL on the 6809 MPU.
	36	#define CPU_CLOCK     ( CPU_EXT_CLOCK / 4 )   // Actual MPU clock frequency ("fE" in the manual). The division yielding CPU_CLOCK is done in the 6809 itself.  Also used as the 40-column character clock.
	37
	38	#define C80_CLOCK ( CPU_EXT_CLOCK / 2 )   // 80-column character mode.  IC37, "80CHRCK"; ~2 MHz.
	39	#define C40_CLOCK ( CPU_CLOCK )         // 40-column character mode; same as MPU clock.  "40CHRCK";       ~1 MHz.
	40
	41	// Video signal clocks from the HD4650SSP CRTC (IC36)
	42	// In the real hardware, the 80-/40-column Mode switch changes the CRTC character clock input source.  However, it just uses a different divider, so the end result is the same horizontal vsync frequency.
	43	#define H_CLOCK ( C80_CLOCK / 128 )   // in 80-column mode
	44	//#define H_CLOCK ( C40_CLOCK / 64 )   // in 40-column mode (either way the frequency is the same: 15.75 kHz)
	45	#define V_CLOCK ( 2 * H_CLOCK / 525 )   // Vertical refresh rate comes out at exactly 60 Hz.
	46
	47	// TODO: ACIA RS-232C and cassette interface clocks (service manual p.67); perhaps reverse the order and simply divide by 2 from each previous frequency.
	48	// IC111 (74LS157P) takes 16.128 MHz and 1.008 MHz TTL clock inputs.  The RS/C SW input line determines the mode (high -> RS-232C).
	49
	50	// Frequencies for RS-232C mode:
	51	// D80_CLOCK / 840.0   // 19200 Hz
	52	// D80_CLOCK / 420   // 38400 Hz
	53	// D80_CLOCK / 210   // 76800 Hz
	54	// D80_CLOCK / 105.0   // 153600 Hz
	55
	56	// Frequencies for cassette mode:
	57	// / 13440   //1200
	58	// / 6720   // 2400
	59	// / 3360   // 4800
	60	// / 1680   // 9600
	61
	62
47	63	class bml3_state : public driver_device
48	64	{
49	65	public:
r23791	r23792
53	69	m_crtc(*this, "crtc"),
54	70	//m_cass(*this, "cassette"),
55	71	m_beep(*this, "beeper"),
56		m_ym2203(*this, "ym2203")
	72	m_ym2203(*this, "ym2203"),
	73	m_wd17xx(*this, "wd17xx"),
	74	m_wd17xx_0(*this, "wd17xx:0"),
	75	m_wd17xx_1(*this, "wd17xx:1"),
	76	m_mc6843(*this, "mc6843")
57	77	{
58	78	}
59	79
r23791	r23792
61	81	required_device<mc6845_device> m_crtc;
62	82	//required_device<cassette_image_device> m_cass;
63	83	required_device<beep_device> m_beep;
64		required_device<ym2203_device> m_ym2203;
	84	optional_device<ym2203_device> m_ym2203;
	85	optional_device<mb8866_t> m_wd17xx;
	86	optional_device<floppy_connector> m_wd17xx_0;
	87	optional_device<floppy_connector> m_wd17xx_1;
	88	optional_device<mc6843_device> m_mc6843;
65	89	DECLARE_WRITE8_MEMBER(bml3_6845_w);
66	90	DECLARE_READ8_MEMBER(bml3_keyboard_r);
67	91	DECLARE_WRITE8_MEMBER(bml3_keyboard_w);
r23791	r23792
69	93	DECLARE_WRITE8_MEMBER(bml3_vres_reg_w);
70	94	DECLARE_READ8_MEMBER(bml3_vram_r);
71	95	DECLARE_WRITE8_MEMBER(bml3_vram_w);
72		DECLARE_READ8_MEMBER(bml3_wd179x_r);
73		DECLARE_WRITE8_MEMBER(bml3_wd179x_w);
74		DECLARE_READ8_MEMBER(bml3_mc6843_r);
75		DECLARE_WRITE8_MEMBER(bml3_mc6843_w);
76		DECLARE_READ8_MEMBER(bml3_fdd_r);
77		DECLARE_WRITE8_MEMBER(bml3_fdd_w);
	96	DECLARE_READ8_MEMBER(bml3_mp1802_r);
	97	DECLARE_WRITE8_MEMBER(bml3_mp1802_w);
	98	DECLARE_READ8_MEMBER(bml3_mp1805_r);
	99	DECLARE_WRITE8_MEMBER(bml3_mp1805_w);
78	100	DECLARE_READ8_MEMBER(bml3_kanji_r);
79	101	DECLARE_WRITE8_MEMBER(bml3_kanji_w);
80	102	DECLARE_READ8_MEMBER(bml3_psg_latch_r);
r23791	r23792
106	128	UINT8 m_io_latch;
107	129	UINT8 m_hres_reg;
108	130	UINT8 m_vres_reg;
109		UINT8 m_keyb_press;
110		UINT8 m_keyb_press_flag;
111		// #$# change to UINT8?
112		int m_keyb_interrupt_disabled;
113		int m_keyb_nmi_disabled;
114		int m_keyb_counter_operation_disabled;
115		int m_keyb_empty_scan;
116		int m_keyb_scancode;
117		int m_keyb_capslock_led_on;
118		int m_keyb_hiragana_led_on;
119		int m_keyb_katakana_led_on;
	131	UINT8 m_keyb_interrupt_disabled;
	132	UINT8 m_keyb_nmi_disabled;
	133	UINT8 m_keyb_counter_operation_disabled;
	134	UINT8 m_keyb_empty_scan;
	135	UINT8 m_keyb_scancode;
	136	UINT8 m_keyb_capslock_led_on;
	137	UINT8 m_keyb_hiragana_led_on;
	138	UINT8 m_keyb_katakana_led_on;
120	139	UINT8 *m_p_chargen;
121	140	UINT8 m_psg_latch;
122	141	void m6845_change_clock(UINT8 setting);
r23791	r23792
133	152	virtual void palette_init();
134	153	public:
135	154	UINT32 screen_update_bml3(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
136		INTERRUPT_GEN_MEMBER(bml3_irq);
	155	// INTERRUPT_GEN_MEMBER(bml3_irq);
137	156	INTERRUPT_GEN_MEMBER(bml3_timer_firq);
138	157	TIMER_DEVICE_CALLBACK_MEMBER(keyboard_callback);
139	158	DECLARE_READ8_MEMBER(bml3_ym2203_r);
140	159	DECLARE_WRITE8_MEMBER(bml3_ym2203_w);
	160	void bml3_wd17xx_intrq_w(bool state);
141	161	};
142	162
143	163	#define mc6845_h_char_total     (m_crtc_vreg[0])
r23791	r23792
165	185
166	186	UINT32 bml3_state::screen_update_bml3(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
167	187	{
	188	// The MB-6890 has a 5-bit colour RAM region.  The meaning of the bits are:
	189	// 0: blue
	190	// 1: red
	191	// 2: green
	192	// 3: reverse/inverse video
	193	// 4: graphic (not character)
	194
168	195	int x,y,hf,count;
169	196	int xi,yi;
170	197	int width,interlace,lowres;
	198	int bgcolor;
171	199	int rawbits,dots[2],color,reverse,graphic;
172	200	UINT8 *vram = memregion("vram")->base();
173	201
r23791	r23792
176	204	width = (m_hres_reg & 0x80) ? 80 : 40;
177	205	interlace = (m_vres_reg & 0x08) ? 1 : 0;
178	206	lowres = (m_hres_reg & 0x40) ? 1 : 0;
	207	bgcolor = m_hres_reg & 0x07;
179	208
180	209	// redundant initializers to keep compiler happy
181	210	rawbits = dots[0] = dots[1] = color = reverse = graphic = 0;
r23791	r23792
233	262	int pen;
234	263
235	264	if(reverse)
236		pen = (dots[hf] >> (7-xi) & 1) ? 0 : color;
	265	pen = (dots[hf] >> (7-xi) & 1) ? bgcolor : color;
237	266	else
238		pen = (dots[hf] >> (7-xi) & 1) ? color : 0;
	267	pen = (dots[hf] >> (7-xi) & 1) ? color : bgcolor;
239	268
240	269	bitmap.pix16((y*8+yi)*(interlace+1)+hf, x*8+xi) = pen;
241	270	}
r23791	r23792
296	325
297	326	READ8_MEMBER( bml3_state::bml3_keyboard_r )
298	327	{
299		m_keyb_press_flag = 0;
300		logerror("bml_keyboard_r %02x\n", m_keyb_press);
301		// #$# not sure what to return if no key pressed, some number from 0-9?  maybe low three bits of scancode?
302		return m_keyb_press;
	328	UINT8 ret = m_keyb_scancode;
	329	m_keyb_scancode &= 0x7f;
	330	return ret;
303	331	}
304	332
305	333	WRITE8_MEMBER( bml3_state::bml3_keyboard_w )
306	334	{
307		logerror("bml_keyboard_w %02x\n", data);
308	335	m_keyb_katakana_led_on = (data & 0x01) != 0;
309	336	m_keyb_hiragana_led_on = (data & 0x02) != 0;
310	337	m_keyb_capslock_led_on = (data & 0x04) != 0;
r23791	r23792
315	342
316	343	void bml3_state::m6845_change_clock(UINT8 setting)
317	344	{
318		int m6845_clock = XTAL_1MHz;
	345	int m6845_clock = CPU_CLOCK;   // CRTC and MPU are synchronous by default
319	346
320	347	switch(setting & 0x88)
321	348	{
322		case 0x00: m6845_clock = XTAL_1MHz; break; //320 x 200
323		case 0x08: m6845_clock = XTAL_1MHz*2; break; //320 x 375
324		case 0x80: m6845_clock = XTAL_1MHz*2; break; //640 x 200
325		case 0x88: m6845_clock = XTAL_1MHz*4; break; //640 x 375
	349	case 0x00: m6845_clock = C40_CLOCK; break; //320 x 200
	350	case 0x08: m6845_clock = C40_CLOCK; break; //320 x 200, interlace
	351	case 0x80: m6845_clock = C80_CLOCK; break; //640 x 200
	352	case 0x88: m6845_clock = C80_CLOCK; break; //640 x 200, interlace
326	353	}
327	354
328	355	m_crtc->set_clock(m6845_clock);
r23791	r23792
330	357
331	358	WRITE8_MEMBER( bml3_state::bml3_hres_reg_w )
332	359	{
	360	// MODE SEL register (see service manual p.43).
333	361	/*
334		x--- ---- width (1) 80 / (0) 40
335		-x-- ---- used in some modes, unknown purpose
336		--x- ---- used in some modes, unknown purpose (also wants $ffc4 to be 0xff), color / monochrome switch?
337		*/
	362	x--- ---- "W" bit: 0 = 40 columns, 1 = 80 columns
	363	-x-- ---- "HR" bit: 0 = high resolution, 1 = normal
	364	--x- ---- "C" bit - ACIA mode: 0 = cassette, 1 = RS-232C
	365	---- -RGB Background colour
	366	*/
338	367
339	368	m_hres_reg = data;
340	369
r23791	r23792
343	372
344	373	WRITE8_MEMBER( bml3_state::bml3_vres_reg_w )
345	374	{
	375	// The MB-6890 had an interlaced video mode which was used for displaying Japanese (Hiragana and Katakana) text (8x16 character glyph bitmaps).
346	376	/*
347		---- x--- char height
	377	---- x--- Interlace select: 0 = non-interlace, 1 = interlace
348	378	*/
349	379	m_vres_reg = data;
350	380
r23791	r23792
373	403	vram[offset+0x4000] = m_attr_latch & 0x1F;
374	404	}
375	405
376		READ8_MEMBER( bml3_state::bml3_wd179x_r)
	406	READ8_MEMBER( bml3_state::bml3_mp1802_r)
377	407	{
378		device_t* dev = machine().device("fdc");
379		switch(offset)
380		{
381		case 0:
382		return ~wd17xx_status_r(dev,space,offset);
383		case 1:
384		return ~wd17xx_track_r(dev,space,offset);
385		case 2:
386		return ~wd17xx_sector_r(dev,space,offset);
387		case 3:
388		return ~wd17xx_data_r(dev,space,offset);
389		case 4:
390		return wd17xx_drq_r(dev) ? 0x00 : 0x80;
391		default:
392		return -1;
393		}
	408	return m_wd17xx->drq_r() ? 0x00 : 0x80;
394	409	}
395	410
396		WRITE8_MEMBER( bml3_state::bml3_wd179x_w)
	411	WRITE8_MEMBER( bml3_state::bml3_mp1802_w)
397	412	{
398		device_t* dev = machine().device("fdc");
399		switch(offset)
400		{
401		case 0:
402		wd17xx_command_w(dev,space,offset,~data);
403		break;
404		case 1:
405		wd17xx_track_w(dev,space,offset,~data);
406		break;
407		case 2:
408		wd17xx_sector_w(dev,space,offset,~data);
409		break;
410		case 3:
411		wd17xx_data_w(dev,space,offset,~data);
412		break;
413		case 4:
414		// #$# support four drives - should be & 0x03 here?
415		int drive = data & 0x01;
416		int side = BIT(data, 4);
417		int motor = BIT(data, 3);
418		wd17xx_set_drive(dev,drive);
419		floppy_mon_w(floppy_get_device(machine(),drive), !motor);
420		floppy_drive_set_ready_state(floppy_get_device(machine(), drive), ASSERT_LINE, 0);
421		wd17xx_set_side(dev,side);
422		break;
423		}
424		}
	413	int drive = data & 0x03;
	414	int side = BIT(data, 4);
	415	int motor = BIT(data, 3);
425	416
426		READ8_MEMBER( bml3_state::bml3_mc6843_r)
427		{
428		device_t* dev = machine().device("fdc");
429		// #$# JME debug
430		logerror("bml3_state::bml3_mc6843_r(offset=%04X)\n", offset);
431		switch(offset)
432		{
433		case 0:
434		return wd17xx_data_r(dev,space,offset);
435		case 1:
436		return m_io_latch;
437		case 2:
438		// b3 is something?
439		return 0;
440		case 3:
441		// ???
442		// return 0x04;
443		// return wd17xx_status_r(dev,offset);
444		return 0x04 | (wd17xx_drq_r(dev) ? 0x01 : 0x00) | (wd17xx_status_r(dev,space,offset) & 0x01 ? 0x80 : 0x00);
445		case 4:
446		// ???
447		return 0;
448		default:
449		return 0;
	417	// drive select
	418	floppy_image_device *floppy = (drive == 0 ? m_wd17xx_0 : m_wd17xx_1)->get_device();
	419
	420	// side select
	421	if(floppy) {
	422	floppy->ss_w(side);
	423	floppy->mon_w(!motor);
450	424	}
451		}
452	425
453		WRITE8_MEMBER( bml3_state::bml3_mc6843_w)
454		{
455		device_t* dev = machine().device("fdc");
456		// #$# JME debug
457		logerror("bml3_state::bml3_mc6843_w(offset=%04X, data=%02X)\n", offset, data);
458		switch(offset)
459		{
460		case 0:
461		break;
462		case 1:
463		// ???
464		m_io_latch = data;
465		break;
466		case 2:
467		// not sure if this is wd17xx command or something a bit different...
468		if (data == 0xE4)
469		// read a sector
470		wd17xx_command_w(dev,space,offset,0x80);
471		else
472		// ROM also uses data == 0xC2, not sure what for
473		wd17xx_command_w(dev,space,offset,data);
474		break;
475		case 3:
476		// ? something here, gets 0x66 written to it
477		{
478		// Nasty hack... code in boot sector sets an NMI handler address
479		// at 010A, but it assumes a JMP opcode (7E) is already in 0109.
480		// But nothing ever writes the opcode 8-(
481		// The workaround here is to write the following NMI handler, which
482		// simply jumps to an RTI instruction in ROM.
483		// JMP $EAD5
484		address_space &mem = machine().device("maincpu")->memory().space(AS_PROGRAM);
485		mem.write_byte(0x0109, 0x7E);
486		mem.write_byte(0x010A, 0xEA);
487		mem.write_byte(0x010B, 0xD5);
488		}
489		break;
490		case 4:
491		wd17xx_sector_w(dev,space,offset,data);
492		break;
493		case 7:
494		wd17xx_track_w(dev,space,offset,data);
495		break;
496		default:
497		break;
498		}
	426	m_wd17xx->set_floppy(floppy);
499	427	}
500	428
501		READ8_MEMBER( bml3_state::bml3_fdd_r )
	429	READ8_MEMBER( bml3_state::bml3_mp1805_r )
502	430	{
503		//printf("FDD 0xff20 R\n");
	431	//logerror("FDD 0xff20 R\n");
504	432	return -1;
505	433	}
506	434
507		WRITE8_MEMBER( bml3_state::bml3_fdd_w )
	435	WRITE8_MEMBER( bml3_state::bml3_mp1805_w )
508	436	{
509		//printf("FDD 0xff20 W %02x\n",data);
510		device_t* dev = machine().device("fdc");
	437	//logerror("FDD 0xff20 W %02x\n",data);
511	438	// ? something here, gets 0x81 written to it if latch found at FF19, or 0x00 if not
512	439	// don't know which bits are what
513		int drive = 0;
514		int side = 0;
515		int motor = BIT(data, 7);
516		wd17xx_set_drive(dev,drive);
517		floppy_mon_w(floppy_get_device(machine(),drive), motor);
518		floppy_drive_set_ready_state(floppy_get_device(machine(), drive), ASSERT_LINE, 0);
519		wd17xx_set_side(dev,side);
	440	//   int drive = ?;
	441	//   int side = ?;
	442	//   int motor = ?;
	443	//   mc6843_set_drive( machine().device("mc6843"), drive );
	444	//   mc6843_set_side( machine().device("mc6843"), side );
	445	//   floppy_mon_w(floppy_get_device(machine(),drive), motor);
	446	//   floppy_drive_set_ready_state(floppy_get_device(machine(), drive), ASSERT_LINE, 0);
520	447	}
521	448
522	449	READ8_MEMBER( bml3_state::bml3_kanji_r )
r23791	r23792
557	484
558	485	READ8_MEMBER( bml3_state::bml3_vram_attr_r)
559	486	{
	487	// C-REG-SELECT register
	488	// Reads from a VRAM address copy the corresponding 'colour RAM' address to the low-order 5 bits of this register as a side-effect
	489	// (unless MK bit indicates 'prohibit write')
560	490	return m_attr_latch;
561	491	}
562	492
563	493	WRITE8_MEMBER( bml3_state::bml3_vram_attr_w)
564	494	{
	495	// C-REG-SELECT register
	496	// Writes to a VRAM address copy the low-order 5 bits of this register to the corresponding 'colour RAM' address as a side-effect
	497	/*
	498	x--- ---- "MK" bit: 0 = enable write, 1 = prohibit write
	499	---x ---- "GC" bit: 0 = character, 1 = graphic
	500	---- x--- "RV" bit: 0 = normal, 1 - reverse
	501	---- -RGB Foreground colour
	502	*/
565	503	m_attr_latch = data;
566	504	}
567	505
r23791	r23792
614	552	AM_RANGE(0x0000, 0x03ff) AM_RAM
615	553	AM_RANGE(0x0400, 0x43ff) AM_READWRITE(bml3_vram_r,bml3_vram_w)
616	554	AM_RANGE(0x4400, 0x9fff) AM_RAM
617		// Floppy boot block code and disk basic use this controller
618		AM_RANGE(0xff00, 0xff04) AM_READWRITE(bml3_wd179x_r,bml3_wd179x_w)
619		// #$# WD179X floppy controller also occupies this address space... maybe ym2203 can be relocated?
620		// AM_RANGE(0xff00, 0xff00) AM_READWRITE(bml3_ym2203_r,bml3_ym2203_w)
621		// AM_RANGE(0xff02, 0xff02) AM_READWRITE(bml3_psg_latch_r,bml3_psg_latch_w) // PSG address/data select
622		// #$# ? is it possible to use a proper mc6843 driver here? Apparently the wd179x and mc6843 both control the same drive.
623		// Disk bootstrap in ROM uses this controller to load boot blocks from disk
624		AM_RANGE(0xff18, 0xff1f) AM_READWRITE(bml3_mc6843_r,bml3_mc6843_w)
625		// AM_RANGE(0xff18, 0xff1f) AM_DEVREADWRITE_LEGACY("mc6843",mc6843_r,mc6843_w)
626		AM_RANGE(0xff20, 0xff20) AM_READWRITE(bml3_fdd_r,bml3_fdd_w) // FDD drive select
627	555	AM_RANGE(0xff75, 0xff76) AM_READWRITE(bml3_kanji_r,bml3_kanji_w)// kanji i/f
628	556	AM_RANGE(0xffc0, 0xffc3) AM_DEVREADWRITE("pia6821", pia6821_device, read, write)
629	557	AM_RANGE(0xffc4, 0xffc4) AM_DEVREADWRITE("acia6850", acia6850_device, status_read, control_write)
630	558	AM_RANGE(0xffc5, 0xffc5) AM_DEVREADWRITE("acia6850", acia6850_device, data_read, data_write)
631	559	AM_RANGE(0xffc6, 0xffc7) AM_WRITE(bml3_6845_w)
	560	// KBNMI - Keyboard "Break" key non-maskable interrupt
632	561	AM_RANGE(0xffc8, 0xffc8) AM_READ(bml3_keyb_nmi_r) // keyboard nmi
	562	// DIPSW - DIP switches on system mainboard
633	563	AM_RANGE(0xffc9, 0xffc9) AM_READ_PORT("DSW")
	564	// TIMER - System timer enable
634	565	AM_RANGE(0xffca, 0xffca) AM_READ(bml3_firq_status_r) // timer irq
635		//  AM_RANGE(0xffcb, 0xffcb) light pen flag
636		AM_RANGE(0xffd0, 0xffd0) AM_WRITE(bml3_hres_reg_w) // mode select
637		//  AM_RANGE(0xffd1, 0xffd1) trace counter
638		//  AM_RANGE(0xffd2, 0xffd2) remote switch
639		AM_RANGE(0xffd3, 0xffd3) AM_READWRITE(bml3_beep_r,bml3_beep_w) // music select
	566	// LPFLG - Light pen interrupt
	567	//  AM_RANGE(0xffcb, 0xffcb)
	568	// MODE_SEL - Graphics mode select
	569	AM_RANGE(0xffd0, 0xffd0) AM_WRITE(bml3_hres_reg_w)
	570	// TRACE - Trace counter
	571	//  AM_RANGE(0xffd1, 0xffd1)
	572	// REMOTE - Remote relay control for cassette?
	573	//  AM_RANGE(0xffd2, 0xffd2)
	574	// MUSIC_SEL - Music select: toggle audio output level when rising
	575	AM_RANGE(0xffd3, 0xffd3) AM_READWRITE(bml3_beep_r,bml3_beep_w)
	576	// TIME_MASK - Prohibit timer IRQ
640	577	AM_RANGE(0xffd4, 0xffd4) AM_WRITE(bml3_firq_mask_w)
641		//  AM_RANGE(0xffd5, 0xffd5) light pen
642		AM_RANGE(0xffd6, 0xffd6) AM_WRITE(bml3_vres_reg_w) // interlace select
	578	// LPENBL - Light pen operation enable
	579	//  AM_RANGE(0xffd5, 0xffd5)
	580	// INTERLACE_SEL - Interlaced video mode (manual has "INTERACE SEL"!)
	581	AM_RANGE(0xffd6, 0xffd6) AM_WRITE(bml3_vres_reg_w)
643	582	//  AM_RANGE(0xffd7, 0xffd7) baud select
644		AM_RANGE(0xffd8, 0xffd8) AM_READWRITE(bml3_vram_attr_r,bml3_vram_attr_w) // attribute register
645		AM_RANGE(0xffe0, 0xffe0) AM_READWRITE(bml3_keyboard_r,bml3_keyboard_w) // keyboard mode register
	583	// C_REG_SEL - Attribute register (character/video mode and colours)
	584	AM_RANGE(0xffd8, 0xffd8) AM_READWRITE(bml3_vram_attr_r,bml3_vram_attr_w)
	585	// KB - Keyboard mode register, interrupt control, keyboard LEDs
	586	AM_RANGE(0xffe0, 0xffe0) AM_READWRITE(bml3_keyboard_r,bml3_keyboard_w)
646	587	//  AM_RANGE(0xffe8, 0xffe8) bank register
647	588	//  AM_RANGE(0xffe9, 0xffe9) IG mode register
648	589	//  AM_RANGE(0xffea, 0xffea) IG enable register
r23791	r23792
655	596	AM_RANGE(0xfff0, 0xffff) AM_WRITE(bml3_fff0_w)
656	597	ADDRESS_MAP_END
657	598
	599	static ADDRESS_MAP_START(bml3a_mem, AS_PROGRAM, 8, bml3_state)
	600	AM_IMPORT_FROM(bml3_mem)
658	601
	602	AM_RANGE(0xff00, 0xff03) AM_DEVREADWRITE("wd17xx", mb8866_t, read, write)
	603	AM_RANGE(0xff04, 0xff04) AM_READWRITE(bml3_mp1802_r,bml3_mp1802_w)
	604	ADDRESS_MAP_END
	605
	606	static ADDRESS_MAP_START(bml3b_mem, AS_PROGRAM, 8, bml3_state)
	607	AM_IMPORT_FROM(bml3_mem)
	608
	609	AM_RANGE(0xff00, 0xff00) AM_READWRITE(bml3_ym2203_r,bml3_ym2203_w)
	610	// TODO: what's this?
	611	// AM_RANGE(0xff02, 0xff02) AM_READWRITE(bml3_psg_latch_r,bml3_psg_latch_w) // PSG address/data select
	612	AM_RANGE(0xff18, 0xff1f) AM_DEVREADWRITE_LEGACY("mc6843",mc6843_r,mc6843_w)
	613	AM_RANGE(0xff20, 0xff20) AM_READWRITE(bml3_mp1805_r,bml3_mp1805_w) // FDD drive select
	614	ADDRESS_MAP_END
	615
	616
659	617	/* Input ports */
660	618
661	619	static INPUT_PORTS_START( bml3 )
	620
	621	// DIP switches (service manual p.88)
	622	// Note the NEWON command reboots with a soft override for the DIP switch
662	623	PORT_START("DSW")
663		PORT_DIPNAME( 0x07, 0x01, "NewOn" ) // TODO
664		PORT_DIPSETTING(    0x00, "0" )
665		PORT_DIPSETTING(    0x01, "1" )
666		PORT_DIPSETTING(    0x02, "2" )
667		PORT_DIPSETTING(    0x03, "3" )
668		PORT_DIPSETTING(    0x04, "4" )
669		PORT_DIPSETTING(    0x05, "5" )
670		PORT_DIPSETTING(    0x06, "6" )
671		PORT_DIPSETTING(    0x07, "7" )
672		PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
673		PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
674		PORT_DIPSETTING(    0x08, DEF_STR( On ) )
675		PORT_DIPNAME( 0x10, 0x10, "Show F help" )
676		PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
677		PORT_DIPSETTING(    0x10, DEF_STR( On ) )
678		PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
679		PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
680		PORT_DIPSETTING(    0x20, DEF_STR( On ) )
681		PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
682		PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
683		PORT_DIPSETTING(    0x40, DEF_STR( On ) )
684		PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) )
685		PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
686		PORT_DIPSETTING(    0x80, DEF_STR( On ) )
	624	PORT_DIPNAME(     0x01, 0x01, "BASIC/terminal mode")
	625	PORT_DIPSETTING(0x00, "Terminal mode")
	626	PORT_DIPSETTING(0x01, "BASIC mode")
	627	PORT_DIPNAME(     0x02, 0x02, "Interlaced video")
	628	PORT_DIPSETTING(0x00, DEF_STR( Off ) )
	629	PORT_DIPSETTING(0x02, DEF_STR( On ))
	630	// This is overridden by the 'Mode' toggle button
	631	PORT_DIPNAME(     0x04, 0x04, "40-/80-column")
	632	PORT_DIPSETTING(0x00, "40 chars/line")
	633	PORT_DIPSETTING(0x04, "80 chars/line")
	634	PORT_DIPNAME(     0x08, 0x00, "Video resolution")
	635	PORT_DIPSETTING(0x00, "High")
	636	PORT_DIPSETTING(0x08, "Low")
	637	PORT_DIPNAME(     0x10, 0x00, "Show PF key content")
	638	PORT_DIPSETTING(0x00, DEF_STR ( Off ) )
	639	PORT_DIPSETTING(0x10, DEF_STR ( On ))
	640	PORT_DIPNAME(     0x20, 0x00, "Terminal duplex")
	641	PORT_DIPSETTING(0x00, "Full duplex")
	642	PORT_DIPSETTING(0x20, "Half duplex")
	643	PORT_DIPNAME(     0x40, 0x00, "Terminal bits")
	644	PORT_DIPSETTING(0x00, "8 bits/char")
	645	PORT_DIPSETTING(0x40, "7 bits/char")
	646	PORT_DIPNAME(     0x80, 0x00, "Hiragana->Katakana")
	647	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
	648	PORT_DIPSETTING(    0x80, DEF_STR( On ) )
687	649
	650	// TODO: also model the CS jumper block?
	651
	652	// RAM expansion configurations (see service manual p.76)
	653	/*
	654	PORT_START("RAM")
	655	PORT_DIPNAME( 0x0003, 0x0002, "RAM size" )
	656	PORT_DIPSETTING(   0x0000, "32 kiB (standard)" )
	657	PORT_DIPSETTING(   0x0001, "40 kiB (32 kiB + 8 kiB)" )
	658	PORT_DIPSETTING(   0x0002, "60 kiB (32 kiB + 28 kiB)" )
	659	*/
	660
688	661	PORT_START("key1") //0x00-0x1f
689	662	PORT_BIT(0x00000001,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("Space") PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
690	663	PORT_BIT(0x00000002,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("Up") PORT_CODE(KEYCODE_UP)
691		PORT_BIT(0x00000004,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("? PAD")
	664	PORT_BIT(0x00000004,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("? PAD") PORT_CHAR('?')
692	665	PORT_BIT(0x00000008,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("Left") PORT_CODE(KEYCODE_LEFT)
693	666	PORT_BIT(0x00000010,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("Down") PORT_CODE(KEYCODE_DOWN)
694	667	PORT_BIT(0x00000020,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("Right") PORT_CODE(KEYCODE_RIGHT)
695		PORT_BIT(0x00000040,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("X1") PORT_CODE(KEYCODE_LCONTROL)
	668	PORT_BIT(0x00000040,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("Control") PORT_CODE(KEYCODE_LCONTROL)
696	669	PORT_BIT(0x00000080,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("Shift")PORT_CODE(KEYCODE_LSHIFT)
697		PORT_BIT(0x00000100,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("X2")
	670	PORT_BIT(0x00000100,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("X2")  // ???
698	671	PORT_BIT(0x00000200,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("Caps Lock") PORT_CODE(KEYCODE_CAPSLOCK)
699	672	PORT_BIT(0x00000400,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("Kana Lock") PORT_CODE(KEYCODE_NUMLOCK)
700	673	PORT_BIT(0x00000800,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("Kana Shift")  PORT_CODE(KEYCODE_LALT)
r23791	r23792
710	683	PORT_BIT(0x00200000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("^") PORT_CODE(KEYCODE_BACKSLASH)
711	684	PORT_BIT(0x00400000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("-") PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-')
712	685	PORT_BIT(0x00800000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("3") PORT_CODE(KEYCODE_3) PORT_CHAR('3')
713		PORT_BIT(0x01000000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("Backspace") PORT_CODE(KEYCODE_BACKSPACE)
	686	PORT_BIT(0x01000000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("Delete") PORT_CODE(KEYCODE_BACKSPACE)
714	687	PORT_BIT(0x02000000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("5") PORT_CODE(KEYCODE_5) PORT_CHAR('5')
715	688	PORT_BIT(0x04000000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("1") PORT_CODE(KEYCODE_1) PORT_CHAR('1')
716	689	PORT_BIT(0x08000000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("2") PORT_CODE(KEYCODE_2) PORT_CHAR('2')
717	690	PORT_BIT(0x10000000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("9") PORT_CODE(KEYCODE_9) PORT_CHAR('9')
718	691	PORT_BIT(0x20000000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("7 PAD") PORT_CODE(KEYCODE_7_PAD) PORT_CHAR('7')
719		PORT_BIT(0x40000000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("X7") //backspace
720		PORT_BIT(0x80000000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("\xC2\xA5") //PORT_NAME("?")
	692	PORT_BIT(0x40000000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("Delete PAD") //backspace
	693	PORT_BIT(0x80000000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("\xC2\xA5") PORT_CODE(KEYCODE_TAB) // yen sign
721	694
722	695	PORT_START("key2") //0x20-0x3f
723	696	PORT_BIT(0x00000001,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("U") PORT_CODE(KEYCODE_U)
r23791	r23792
733	706	PORT_BIT(0x00000400,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("W") PORT_CODE(KEYCODE_W)
734	707	PORT_BIT(0x00000800,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("E") PORT_CODE(KEYCODE_E)
735	708	PORT_BIT(0x00001000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("O") PORT_CODE(KEYCODE_O)
736		PORT_BIT(0x00002000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME(".")
	709	PORT_BIT(0x00002000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME(". PAD")  PORT_CODE(KEYCODE_DEL_PAD) PORT_CHAR('.')
737	710	PORT_BIT(0x00004000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("HOME") PORT_CODE(KEYCODE_HOME) //or cls?
738	711	PORT_BIT(0x00008000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("ENTER") PORT_CODE(KEYCODE_ENTER)
739	712	PORT_BIT(0x00010000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("J") PORT_CODE(KEYCODE_J)
r23791	r23792
751	724	PORT_BIT(0x10000000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("L") PORT_CODE(KEYCODE_L)
752	725	PORT_BIT(0x20000000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("5 PAD") PORT_CODE(KEYCODE_5_PAD) PORT_CHAR('5')
753	726	PORT_BIT(0x40000000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("6 PAD") PORT_CODE(KEYCODE_6_PAD) PORT_CHAR('6')
754		PORT_BIT(0x80000000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("-") PORT_CODE(KEYCODE_MINUS_PAD) PORT_CHAR('-')
	727	PORT_BIT(0x80000000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("- PAD") PORT_CODE(KEYCODE_MINUS_PAD) PORT_CHAR('-')
755	728
756	729	PORT_START("key3") //0x40-0x5f
757	730	PORT_BIT(0x00000001,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("M") PORT_CODE(KEYCODE_M)
r23791	r23792
759	732	PORT_BIT(0x00000004,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("N") PORT_CODE(KEYCODE_N)
760	733	PORT_BIT(0x00000008,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME(",") PORT_CODE(KEYCODE_COMMA)
761	734	PORT_BIT(0x00000010,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("/") PORT_CODE(KEYCODE_SLASH)
762		PORT_BIT(0x00000020,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("/ PAD") PORT_CODE(KEYCODE_SLASH_PAD)
763		PORT_BIT(0x00000040,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("_")
764		PORT_BIT(0x00000080,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("1") PORT_CODE(KEYCODE_1_PAD) PORT_CHAR('1')
	735	PORT_BIT(0x00000020,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("/ PAD") PORT_CODE(KEYCODE_SLASH_PAD) PORT_CHAR('/')
	736	PORT_BIT(0x00000040,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("_") PORT_CODE(KEYCODE_TILDE)
	737	PORT_BIT(0x00000080,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("1 PAD") PORT_CODE(KEYCODE_1_PAD) PORT_CHAR('1')
765	738	PORT_BIT(0x00000100,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("Z") PORT_CODE(KEYCODE_Z)
766	739	PORT_BIT(0x00000200,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("B") PORT_CODE(KEYCODE_B)
767	740	PORT_BIT(0x00000400,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("X") PORT_CODE(KEYCODE_X)
768	741	PORT_BIT(0x00000800,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("C") PORT_CODE(KEYCODE_C)
769	742	PORT_BIT(0x00001000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME(".") PORT_CODE(KEYCODE_STOP)
770		PORT_BIT(0x00002000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("X8")
	743	PORT_BIT(0x00002000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("2 PAD") PORT_CODE(KEYCODE_2_PAD) PORT_CHAR('2')
771	744	PORT_BIT(0x00004000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("3 PAD") PORT_CODE(KEYCODE_3_PAD) PORT_CHAR('3')
772	745	PORT_BIT(0x00008000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("+") PORT_CODE(KEYCODE_PLUS_PAD)
773	746	PORT_BIT(0x00010000,IP_ACTIVE_HIGH,IPT_KEYBOARD) PORT_NAME("PF1") PORT_CODE(KEYCODE_F1)
r23791	r23792
794	767	NULL        /* update address callback */
795	768	};
796	769
797		static WRITE_LINE_DEVICE_HANDLER( bml3_fdc_intrq_w )
	770	void bml3_state::bml3_wd17xx_intrq_w(bool state)
798	771	{
799		// #$# ? HOLD_LINE or PULSE_LINE
800		// #$#debug
801		logerror("bml3_fdc_intrq_w called %d\n", state);
802	772	if (state)
803		device->machine().device("maincpu")->execute().set_input_line(INPUT_LINE_NMI, PULSE_LINE);
	773	m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
804	774	}
805	775
806	776	TIMER_DEVICE_CALLBACK_MEMBER(bml3_state::keyboard_callback)
807	777	{
808	778	static const char *const portnames[3] = { "key1","key2","key3" };
809		int i,port_i,scancode,trigger = 0;
	779	int i,port_i,trigger = 0;
810	780
811		if(!m_keyb_press_flag)
	781	if(!(m_keyb_scancode & 0x80))
812	782	{
813	783	m_keyb_scancode = (m_keyb_scancode + 1) & 0x7F;
814		scancode = m_keyb_scancode;
	784	if (m_keyb_counter_operation_disabled) {
	785	m_keyb_scancode &= 0xF;
	786	}
815	787
816		if (scancode == 0x7F)
	788	if (m_keyb_scancode == 0x7F)
817	789	{
818	790	if (m_keyb_empty_scan == 1)
819	791	{
820	792	// full scan completed with no keypress
821		m_keyb_press = 0;
822		if (!m_keyb_counter_operation_disabled)
823		trigger = !0;
	793	trigger = !0;
824	794	}
825	795	if (m_keyb_empty_scan > 0)
826	796	m_keyb_empty_scan--;
827	797	}
828		else if (scancode < 32*3)
	798	else if (m_keyb_scancode < 32*3)
829	799	{
830		port_i = scancode / 32;
831		i = scancode % 32;
	800	port_i = m_keyb_scancode / 32;
	801	i = m_keyb_scancode % 32;
832	802	if((ioport(portnames[port_i])->read()>>i) & 1)
833	803	{
834	804	m_keyb_empty_scan = 2;
r23791	r23792
837	807	}
838	808	if (trigger)
839	809	{
840		m_keyb_press_flag = 1;
841		m_keyb_press = m_keyb_scancode | 0x80;
	810	m_keyb_scancode |= 0x80;
842	811	if (!m_keyb_interrupt_disabled)
843	812	m_maincpu->set_input_line(M6809_IRQ_LINE, HOLD_LINE);
844	813	}
845		/*
	814	/* Don't need this apparently...
846	815	else {
847		// #$# ? don't need this
848		m_maincpu->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
	816	m_maincpu->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
849	817	}
850	818	*/
851	819	}
r23791	r23792
882	850	m_beep->set_frequency(1200); //guesswork
883	851	m_beep->set_state(0);
884	852	m_extram = auto_alloc_array(machine(),UINT8,0x10000);
	853
	854	// floppy callbacks
	855	if (m_wd17xx) {
	856	m_wd17xx->setup_intrq_cb(wd_fdc_t::line_cb(FUNC(bml3_state::bml3_wd17xx_intrq_w), this));
	857	}
885	858	}
886	859
887	860	void bml3_state::machine_reset()
r23791	r23792
900	873	m_firq_mask = -1; // disable firq
901	874	}
902	875
903		/* F4 Character Displayer */
904		static const gfx_layout bml3_charlayout8x8even =
905		{
906		8, 8,                   /* 8 x 8 characters */
907		RGN_FRAC(1,1),                  /* 256 characters */
908		1,                  /* 1 bits per pixel */
909		{ 0 },                  /* no bitplanes */
910		/* x offsets */
911		{ 0, 1, 2, 3, 4, 5, 6, 7 },
912		/* y offsets */
913		{ 0*8, 2*8,4*8, 6*8, 8*8, 10*8, 12*8, 14*8 },
914		8*16                    /* every char takes 8 bytes */
915		};
	876	const mc6843_interface bml3_6843_if = { NULL };
916	877
917		static const gfx_layout bml3_charlayout8x8odd =
918		{
919		8, 8,                   /* 8 x 8 characters */
920		RGN_FRAC(1,1),                  /* 256 characters */
921		1,                  /* 1 bits per pixel */
922		{ 0 },                  /* no bitplanes */
923		/* x offsets */
924		{ 0, 1, 2, 3, 4, 5, 6, 7 },
925		/* y offsets */
926		{ 1*8, 3*8, 5*8, 7*8, 9*8, 11*8, 13*8, 15*8 },
927		8*16                    /* every char takes 8 bytes */
928		};
929
930		static const gfx_layout bml3_charlayout8x16 =
931		{
932		8, 16,                  /* 8 x 8 characters */
933		RGN_FRAC(1,1),                  /* 256 characters */
934		1,                  /* 1 bits per pixel */
935		{ 0 },                  /* no bitplanes */
936		/* x offsets */
937		{ 0, 1, 2, 3, 4, 5, 6, 7 },
938		/* y offsets */
939		{ 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8, 8*8, 9*8, 10*8, 11*8, 12*8, 13*8, 14*8, 15*8 },
940		8*16                    /* every char takes 8 bytes */
941		};
942
943		static GFXDECODE_START( bml3 )
944		GFXDECODE_ENTRY( "chargen", 0, bml3_charlayout8x8even, 0, 4 )
945		GFXDECODE_ENTRY( "chargen", 0, bml3_charlayout8x8odd, 0, 4 )
946		GFXDECODE_ENTRY( "chargen", 0, bml3_charlayout8x16, 0, 4 )
947		GFXDECODE_END
948
949		// #$# ? remove if not using proper mc6843?
950		// const mc6843_interface bml3_6843_if = { NULL };
951
952	878	WRITE8_MEMBER(bml3_state::bml3_piaA_w)
953	879	{
954	880	address_space &mem = m_maincpu->space(AS_PROGRAM);
r23791	r23792
965	891	---- ---x 0xf000 - 0xfeff (0) ROM R RAM W (1) RAM R/W
966	892	---- --x- 0xfff0 - 0xffff (0) ROM R RAM W (1) RAM R/W
967	893	*/
968		printf("Check banking PIA A -> %02x\n",data);
	894	logerror("Check banking PIA A -> %02x\n",data);
969	895
970	896	if(!(data & 0x2))
971	897	{
r23791	r23792
1064	990
1065	991	READ_LINE_MEMBER( bml3_state::bml3_acia_rx_r )
1066	992	{
1067		printf("TAPE R\n");
	993	logerror("TAPE R\n");
1068	994	return 1;
1069	995	}
1070	996
1071	997	WRITE_LINE_MEMBER( bml3_state::bml3_acia_tx_w )
1072	998	{
1073		printf("%02x TAPE\n",state);
	999	logerror("%02x TAPE\n",state);
1074	1000	}
1075	1001
1076	1002
1077	1003	READ_LINE_MEMBER( bml3_state::bml3_acia_dts_r )
1078	1004	{
1079		printf("TAPE R DTS\n");
	1005	logerror("TAPE R DTS\n");
1080	1006	return 1;
1081	1007	}
1082	1008
1083	1009	WRITE_LINE_MEMBER( bml3_state::bml3_acia_rts_w )
1084	1010	{
1085		printf("%02x TAPE RTS\n",state);
	1011	logerror("%02x TAPE RTS\n",state);
1086	1012	}
1087	1013
1088	1014	READ_LINE_MEMBER( bml3_state::bml3_acia_dcd_r )
1089	1015	{
1090		printf("TAPE R DCD\n");
	1016	logerror("TAPE R DCD\n");
1091	1017	return 1;
1092	1018	}
1093	1019
1094	1020	WRITE_LINE_MEMBER( bml3_state::bml3_acia_irq_w )
1095	1021	{
1096		printf("%02x TAPE IRQ\n",state);
	1022	logerror("%02x TAPE IRQ\n",state);
1097	1023	}
1098	1024
1099	1025
r23791	r23792
1119	1045	DEVCB_NULL  // write B
1120	1046	};
1121	1047
1122		static const floppy_interface bml3_floppy_interface =
	1048	static const floppy_format_type bml3_floppy_formats[] = {
	1049	FLOPPY_D88_FORMAT,
	1050	NULL
	1051	};
	1052
	1053	static SLOT_INTERFACE_START( bml3_mp1802_floppies )
	1054	SLOT_INTERFACE( "525dd", FLOPPY_525_DD )
	1055	SLOT_INTERFACE_END
	1056
	1057	static const floppy_interface bml3_mp1805_floppy_interface =
1123	1058	{
1124	1059	DEVCB_NULL,
1125	1060	DEVCB_NULL,
1126	1061	DEVCB_NULL,
1127	1062	DEVCB_NULL,
1128	1063	DEVCB_NULL,
1129		FLOPPY_STANDARD_5_25_DSDD,
1130		LEGACY_FLOPPY_OPTIONS_NAME(bml3),
	1064	FLOPPY_STANDARD_3_SSDD,
	1065	LEGACY_FLOPPY_OPTIONS_NAME(default),
1131	1066	NULL
1132	1067	};
1133	1068
1134		const wd17xx_interface bml3_wd17xx_interface =
1135		{
1136		DEVCB_NULL,
1137		DEVCB_LINE(bml3_fdc_intrq_w),
1138		DEVCB_NULL,
1139		{FLOPPY_0, FLOPPY_1}
1140		};
	1069	//static SLOT_INTERFACE_START( bml3_mp1805_floppies )
	1070	//   SLOT_INTERFACE( "3ssdd", FLOPPY_3_SSDD )
	1071	//SLOT_INTERFACE_END
1141	1072
1142		static MACHINE_CONFIG_START( bml3, bml3_state )
	1073	static MACHINE_CONFIG_START( bml3_common, bml3_state )
1143	1074	/* basic machine hardware */
1144		MCFG_CPU_ADD("maincpu",M6809, XTAL_1MHz)
1145		MCFG_CPU_PROGRAM_MAP(bml3_mem)
	1075	MCFG_CPU_ADD("maincpu",M6809, CPU_CLOCK)
1146	1076	MCFG_CPU_VBLANK_INT_DRIVER("screen", bml3_state,  bml3_timer_firq)
1147	1077	//  MCFG_CPU_PERIODIC_INT_DRIVER(bml3_state, bml3_firq, 45)
1148	1078
r23791	r23792
1151	1081	/* video hardware */
1152	1082	MCFG_SCREEN_ADD("screen", RASTER)
1153	1083	MCFG_SCREEN_REFRESH_RATE(60)
1154		MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
1155		MCFG_SCREEN_SIZE(640, 480)
	1084	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2400)) /* Service manual specifies "Raster return period" as 2.4 ms (p.64), although the total vertical non-displaying time seems to be 4 ms. */
	1085	MCFG_SCREEN_SIZE(640, 400)
1156	1086	MCFG_SCREEN_VISIBLE_AREA(0, 320-1, 0, 200-1)
1157	1087	MCFG_SCREEN_UPDATE_DRIVER(bml3_state, screen_update_bml3)
1158	1088	MCFG_PALETTE_LENGTH(8)
1159		MCFG_GFXDECODE(bml3)
1160	1089
1161	1090	/* Devices */
1162		MCFG_MC6845_ADD("crtc", H46505, XTAL_1MHz, mc6845_intf)
	1091	// CRTC clock should be synchronous with the CPU clock.
	1092	MCFG_MC6845_ADD("crtc", H46505, CPU_CLOCK, mc6845_intf)
1163	1093	// fire once per scan of an individual key
1164		MCFG_TIMER_DRIVER_ADD_PERIODIC("keyboard_timer", bml3_state, keyboard_callback, attotime::from_hz(15750/2))
1165		// #$# ? remove if not using proper mc6843?
1166		// MCFG_MC6843_ADD( "mc6843", bml3_6843_if )
	1094	// According to the service manual (p.65), the keyboard timer is driven by the horizontal video sync clock.
	1095	MCFG_TIMER_DRIVER_ADD_PERIODIC("keyboard_timer", bml3_state, keyboard_callback, attotime::from_hz(H_CLOCK/2))
1167	1096	MCFG_PIA6821_ADD("pia6821", bml3_pia_config)
1168	1097	MCFG_ACIA6850_ADD("acia6850", bml3_acia_if)
1169	1098
1170		/* floppy */
1171		// #$# not sure what wd17xx model, this is just a guess
1172		MCFG_WD1773_ADD("fdc", bml3_wd17xx_interface )
1173		MCFG_LEGACY_FLOPPY_2_DRIVES_ADD(bml3_floppy_interface)
1174
1175	1099	/* Audio */
1176	1100	MCFG_SPEAKER_STANDARD_MONO("mono")
1177	1101	MCFG_SOUND_ADD("beeper", BEEP, 0)
1178	1102	MCFG_SOUND_ROUTE(ALL_OUTPUTS,"mono",0.50)
1179	1103
	1104	MACHINE_CONFIG_END
	1105
	1106	static MACHINE_CONFIG_DERIVED( bml3, bml3_common )
	1107	MCFG_CPU_MODIFY( "maincpu" )
	1108	MCFG_CPU_PROGRAM_MAP(bml3_mem)
	1109
	1110	// MCFG_MACHINE_START_OVERRIDE( bml3_state, bml3 )
	1111	MACHINE_CONFIG_END
	1112
	1113	static MACHINE_CONFIG_DERIVED( bml3a, bml3_common )
	1114	MCFG_CPU_MODIFY( "maincpu" )
	1115	MCFG_CPU_PROGRAM_MAP(bml3a_mem)
	1116	/* floppy */
	1117	MCFG_MB8866x_ADD("wd17xx", CPU_CLOCK )
	1118	MCFG_FLOPPY_DRIVE_ADD("wd17xx:0", bml3_mp1802_floppies, "525dd", bml3_floppy_formats)
	1119	MCFG_FLOPPY_DRIVE_ADD("wd17xx:1", bml3_mp1802_floppies, "525dd", bml3_floppy_formats)
	1120	MACHINE_CONFIG_END
	1121
	1122	static MACHINE_CONFIG_DERIVED( bml3b, bml3_common )
	1123	MCFG_CPU_MODIFY( "maincpu" )
	1124	MCFG_CPU_PROGRAM_MAP(bml3b_mem)
	1125	/* floppy */
	1126	MCFG_MC6843_ADD( "mc6843", bml3_6843_if )
	1127	MCFG_LEGACY_FLOPPY_4_DRIVES_ADD(bml3_mp1805_floppy_interface)
	1128	//   MCFG_FLOPPY_DRIVE_ADD("mc6843:0", bml3_mp1805_floppies, "3ssdd", bml3_floppy_formats)
	1129	//   MCFG_FLOPPY_DRIVE_ADD("mc6843:1", bml3_mp1805_floppies, "3ssdd", bml3_floppy_formats)
	1130
	1131	// audio
1180	1132	MCFG_SOUND_ADD("ym2203", YM2203, 2000000) //unknown clock / divider
1181	1133	MCFG_YM2203_AY8910_INTF(&ay8910_config)
1182	1134	MCFG_SOUND_ROUTE(0, "mono", 0.25)
r23791	r23792
1185	1137	MCFG_SOUND_ROUTE(3, "mono", 0.50)
1186	1138	MACHINE_CONFIG_END
1187	1139
	1140
	1141
1188	1142	/* ROM definition */
1189	1143	ROM_START( bml3 )
1190	1144	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASEFF )
r23791	r23792
1192	1146	/* Handcrafted ROMs, rom labels and contents might not match */
1193	1147	ROM_LOAD( "598 p16611.ic3", 0xa000, 0x2000, BAD_DUMP CRC(954b9bad) SHA1(047948fac6808717c60a1d0ac9205a5725362430))
1194	1148	ROM_LOAD( "599 p16561.ic4", 0xc000, 0x2000, BAD_DUMP CRC(b27a48f5) SHA1(94cb616df4caa6415c5076f9acdf675acb7453e2))
	1149	// TODO: Replace checksums with a ROM dump without a disk controller patch (checksums here are inclusive of the MP1805 patch)
1195	1150	ROM_LOAD( "600 p16681.ic5", 0xe000, 0x2000, BAD_DUMP CRC(fe3988a5) SHA1(edc732f1cd421e0cf45ffcfc71c5589958ceaae7))
1196	1151
1197	1152	ROM_REGION( 0x1000, "chargen", 0 )
r23791	r23792
1203	1158	ROM_LOAD("kanji.rom", 0x00000, 0x20000, NO_DUMP )
1204	1159	ROM_END
1205	1160
	1161	ROM_START( bml3a )
	1162	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASEFF )
	1163	//  ROM_LOAD( "l3bas.rom", 0xa000, 0x6000, BAD_DUMP CRC(d81baa07) SHA1(a8fd6b29d8c505b756dbf5354341c48f9ac1d24d)) //original, 24k isn't a proper rom size!
	1164	/* Handcrafted ROMs, rom labels and contents might not match */
	1165	ROM_LOAD( "598 p16611.ic3", 0xa000, 0x2000, BAD_DUMP CRC(954b9bad) SHA1(047948fac6808717c60a1d0ac9205a5725362430))
	1166	ROM_LOAD( "599 p16561.ic4", 0xc000, 0x2000, BAD_DUMP CRC(b27a48f5) SHA1(94cb616df4caa6415c5076f9acdf675acb7453e2))
	1167	// TODO: Replace checksums with a ROM dump without a disk controller patch (checksums here are inclusive of the MP1805 patch)
	1168	ROM_LOAD( "600 p16681.ic5", 0xe000, 0x2000, BAD_DUMP CRC(fe3988a5) SHA1(edc732f1cd421e0cf45ffcfc71c5589958ceaae7))
	1169
	1170	// MP-1502 disk controller ROM, which replaces part of the system ROM
	1171	ROM_LOAD( "mp1802.rom", 0xf800, 0x0800, BAD_DUMP CRC(8d0dc101) SHA1(92f7d1cebecafa7472e45c4999520de5c01c6dbc))
	1172
	1173	ROM_REGION( 0x1000, "chargen", 0 )
	1174	ROM_LOAD("font.rom", 0x00000, 0x1000, BAD_DUMP CRC(0b6f2f10) SHA1(dc411b447ca414e94843636d8b5f910c954581fb) ) // handcrafted
	1175
	1176	ROM_REGION( 0x8000, "vram", ROMREGION_ERASEFF )
	1177
	1178	ROM_REGION( 0x20000, "kanji", ROMREGION_ERASEFF )
	1179	ROM_LOAD("kanji.rom", 0x00000, 0x20000, NO_DUMP )
	1180	ROM_END
	1181
	1182	ROM_START( bml3b )
	1183	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASEFF )
	1184	//  ROM_LOAD( "l3bas.rom", 0xa000, 0x6000, BAD_DUMP CRC(d81baa07) SHA1(a8fd6b29d8c505b756dbf5354341c48f9ac1d24d)) //original, 24k isn't a proper rom size!
	1185	/* Handcrafted ROMs, rom labels and contents might not match */
	1186	ROM_LOAD( "598 p16611.ic3", 0xa000, 0x2000, BAD_DUMP CRC(954b9bad) SHA1(047948fac6808717c60a1d0ac9205a5725362430))
	1187	ROM_LOAD( "599 p16561.ic4", 0xc000, 0x2000, BAD_DUMP CRC(b27a48f5) SHA1(94cb616df4caa6415c5076f9acdf675acb7453e2))
	1188	// TODO: Replace checksums with a ROM dump without a disk controller patch (checksums here are inclusive of the MP1805 patch)
	1189	ROM_LOAD( "600 p16681.ic5", 0xe000, 0x2000, BAD_DUMP CRC(fe3988a5) SHA1(edc732f1cd421e0cf45ffcfc71c5589958ceaae7))
	1190
	1191	// MP-1505 disk controller ROM, which replaces part of the system ROM
	1192	ROM_LOAD( "mp1805.rom", 0xf800, 0x0800, BAD_DUMP CRC(b532d8d9) SHA1(6f1160356d5bf64b5926b1fdb60db414edf65f22))
	1193
	1194	ROM_REGION( 0x1000, "chargen", 0 )
	1195	ROM_LOAD("font.rom", 0x00000, 0x1000, BAD_DUMP CRC(0b6f2f10) SHA1(dc411b447ca414e94843636d8b5f910c954581fb) ) // handcrafted
	1196
	1197	ROM_REGION( 0x8000, "vram", ROMREGION_ERASEFF )
	1198
	1199	ROM_REGION( 0x20000, "kanji", ROMREGION_ERASEFF )
	1200	ROM_LOAD("kanji.rom", 0x00000, 0x20000, NO_DUMP )
	1201	ROM_END
	1202
1206	1203	/* Driver */
1207	1204
1208		/*    YEAR  NAME    PARENT  COMPAT   MACHINE    INPUT    INIT     COMPANY         FULLNAME           FLAGS */
1209		COMP( 1980, bml3,   0,      0,       bml3,      bml3, driver_device,    0,      "Hitachi", "Basic Master Level 3", GAME_NOT_WORKING | GAME_NO_SOUND)
	1205	/* Configurations are focussed on disk support rather than computer model.
	1206	* The following three models were produced:
	1207	*
	1208	* <year> / <model> / <name>
	1209	* 1980 / MB-6890 / Basic Master Level 3
	1210	* 1982 / MB-6891 / Basic Master Level 3 Mark 2
	1211	* 1983 / MB-6892 / Basic Master Level 3 Mark 5
	1212	*
	1213	* If it turns out that these models had different ROMs or significant base hardware changes, then a model-oriented configuration
	1214	* set might be more appropriate.
	1215	*/
	1216
	1217	/*    YEAR  NAME    PARENT  COMPAT   MACHINE    INPUT    INIT                      COMPANY    FULLNAME                        FLAGS */
	1218	COMP( 1980, bml3,   0,      0,       bml3,      bml3,    driver_device,    0,      "Hitachi", "MB-6890 Basic Master Level 3", GAME_NOT_WORKING)
	1219	COMP( 1980, bml3a,  bml3,   0,       bml3a,     bml3,    driver_device,    0,      "Hitachi", "MB-6890 Basic Master Level 3 + MP-1502 (5.25\" disk)", 0)
	1220	COMP( 1980, bml3b,  bml3,   0,       bml3b,     bml3,    driver_device,    0,      "Hitachi", "MB-6890 Basic Master Level 3 + MP-1505 (3\" disk) + YM-2203 (sound)", GAME_NOT_WORKING)

Previous

199869 Revisions

Next

---

© 1997-2024 The MAME Team