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r23787 Wednesday 19th June, 2013 at 10:35:43 UTC by smf
Added ata_interface_device, ide_controller_device is now only for pc register mapping. Renamed ide_mass_storage_device to ata_mass_storage_device. Changed ide_hdd_device so it only picks up it's image from the harddisk_image_device, which does a lookup to see if there is a region itself. (nw)

[src/emu/imagedev]	harddriv.c
[src/emu/machine]	atadev.c* atadev.h* ataflash.h ataintf.c* ataintf.h* {idectrl.c} {idectrl.h} idehd.c idehd.h machine.mak
[src/mame/drivers]	atlantis.c calchase.c chihiro.c cobra.c djmain.c extrema.c fruitpc.c funkball.c gamecstl.c globalvr.c iteagle.c jaguar.c kinst.c maygayep.c mediagx.c midqslvr.c midvunit.c photoply.c pinball2k.c pyson.c qdrmfgp.c quakeat.c queen.c savquest.c seattle.c taitogn.c taitotz.c twinkle.c vegas.c viper.c voyager.c vp101.c zn.c
[src/mame/includes]	djmain.h qdrmfgp.h
[src/mess/drivers]	bebox.c
[src/mess/machine]	a2cffa.c a2cffa.h a2vulcan.c a2vulcan.h a2zipdrive.c a2zipdrive.h adam_ide.c adam_ide.h bebox.c c64_ide64.c c64_ide64.h isa_fdc.c isa_ide.c isa_ide8.c kc_d004.c kc_d004.h southbridge.h
[src/mess/machine/ti99]	tn_ide.c tn_ide.h

trunk/src/emu/imagedev/harddriv.c

r23786	r23787
102	102	m_chd = NULL;
103	103
104	104	// try to locate the CHD from a DISK_REGION
105		chd_file *handle = get_disk_handle(machine(), owner()->tag());
	105	chd_file *handle = get_disk_handle(machine(), tag());
106	106	if (handle != NULL)
107	107	{
108	108	m_hard_disk_handle = hard_disk_open(handle);

trunk/src/emu/machine/ataintf.c

r0	r23787
	1	/***************************************************************************
	2
	3	ataintf.c
	4
	5	ATA Interface implementation.
	6
	7	Copyright Nicola Salmoria and the MAME Team.
	8	Visit http://mamedev.org for licensing and usage restrictions.
	9
	10	***************************************************************************/
	11
	12	#include "emu.h"
	13	#include "ataintf.h"
	14	#include "debugger.h"
	15	#include "idehd.h"
	16
	17	/***************************************************************************
	18	DEBUGGING
	19	***************************************************************************/
	20
	21	#define VERBOSE                     0
	22
	23	#define LOG(x)  do { if (VERBOSE) logerror x; } while (0)
	24
	25	void ata_interface_device::set_irq(int state)
	26	{
	27	if (state == ASSERT_LINE)
	28	LOG(("ATA interrupt assert\n"));
	29	else
	30	LOG(("ATA interrupt clear\n"));
	31
	32	/* signal an interrupt */
	33	m_irq_handler(state);
	34	}
	35
	36	void ata_interface_device::set_dmarq(int state)
	37	{
	38	m_dmarq_handler(state);
	39	}
	40
	41	WRITE_LINE_MEMBER( ata_interface_device::irq0_write_line )
	42	{
	43	m_irq[0] = state;
	44
	45	set_irq(m_irq[0] == ASSERT_LINE || m_irq[1] == ASSERT_LINE);
	46	}
	47
	48	WRITE_LINE_MEMBER( ata_interface_device::irq1_write_line )
	49	{
	50	m_irq[1] = state;
	51
	52	set_irq(m_irq[0] == ASSERT_LINE || m_irq[1] == ASSERT_LINE);
	53	}
	54
	55	WRITE_LINE_MEMBER( ata_interface_device::dmarq0_write_line )
	56	{
	57	m_dmarq[0] = state;
	58
	59	set_dmarq(m_dmarq[0] == ASSERT_LINE || m_dmarq[1] == ASSERT_LINE);
	60	}
	61
	62	WRITE_LINE_MEMBER( ata_interface_device::dmarq1_write_line )
	63	{
	64	m_dmarq[1] = state;
	65
	66	set_dmarq(m_dmarq[0] == ASSERT_LINE || m_dmarq[1] == ASSERT_LINE);
	67	}
	68
	69
	70	/***************************************************************************
	71	INITIALIZATION AND RESET
	72	***************************************************************************/
	73
	74	UINT8 *ata_interface_device::identify_device_buffer(int _drive)
	75	{
	76	return m_slot[_drive]->dev()->identify_device_buffer();
	77	}
	78
	79	void ata_interface_device::set_master_password(int _drive, const UINT8 *password)
	80	{
	81	m_slot[_drive]->dev()->m_master_password = password;
	82	m_slot[_drive]->dev()->m_master_password_enable = (password != NULL);
	83	}
	84
	85
	86	void ata_interface_device::set_user_password(int _drive, const UINT8 *password)
	87	{
	88	m_slot[_drive]->dev()->m_user_password = password;
	89	m_slot[_drive]->dev()->m_user_password_enable = (password != NULL);
	90	}
	91
	92	/*************************************
	93	*
	94	*  ATA interface read
	95	*
	96	*************************************/
	97
	98	UINT16 ata_interface_device::read_dma()
	99	{
	100	UINT16 result = 0xffff;
	101	for (int i = 0; i < 2; i++)
	102	if (m_slot[i]->dev() != NULL)
	103	result &= m_slot[i]->dev()->read_dma();
	104
	105	//  printf( "read_dma %04x\n", result );
	106	return result;
	107	}
	108
	109	READ16_MEMBER( ata_interface_device::read_cs0 )
	110	{
	111	UINT16 result = mem_mask;
	112	for (int i = 0; i < 2; i++)
	113	if (m_slot[i]->dev() != NULL)
	114	result &= m_slot[i]->dev()->read_cs0(space, offset, mem_mask);
	115
	116	//  printf( "read cs0 %04x %04x %04x\n", offset, result, mem_mask );
	117
	118	return result;
	119	}
	120
	121	READ16_MEMBER( ata_interface_device::read_cs1 )
	122	{
	123	UINT16 result = mem_mask;
	124	for (int i = 0; i < 2; i++)
	125	if (m_slot[i]->dev() != NULL)
	126	result &= m_slot[i]->dev()->read_cs1(space, offset, mem_mask);
	127
	128	//  printf( "read cs1 %04x %04x %04x\n", offset, result, mem_mask );
	129
	130	return result;
	131	}
	132
	133
	134	/*************************************
	135	*
	136	*  ATA interface write
	137	*
	138	*************************************/
	139
	140	void ata_interface_device::write_dma( UINT16 data )
	141	{
	142	//  printf( "write_dma %04x\n", data );
	143
	144	for (int i = 0; i < 2; i++)
	145	if (m_slot[i]->dev() != NULL)
	146	m_slot[i]->dev()->write_dma(data);
	147	}
	148
	149	WRITE16_MEMBER( ata_interface_device::write_cs0 )
	150	{
	151	//  printf( "write cs0 %04x %04x %04x\n", offset, data, mem_mask );
	152
	153	for (int i = 0; i < 2; i++)
	154	if (m_slot[i]->dev() != NULL)
	155	m_slot[i]->dev()->write_cs0(space, offset, data, mem_mask);
	156	}
	157
	158	WRITE16_MEMBER( ata_interface_device::write_cs1 )
	159	{
	160	//  printf( "write cs1 %04x %04x %04x\n", offset, data, mem_mask );
	161
	162	for (int i = 0; i < 2; i++)
	163	if (m_slot[i]->dev() != NULL)
	164	m_slot[i]->dev()->write_cs1(space, offset, data, mem_mask);
	165	}
	166
	167	WRITE_LINE_MEMBER( ata_interface_device::write_dmack )
	168	{
	169	//  printf( "write_dmack %04x\n", state );
	170
	171	for (int i = 0; i < 2; i++)
	172	if (m_slot[i]->dev() != NULL)
	173	m_slot[i]->dev()->write_dmack(state);
	174	}
	175
	176	SLOT_INTERFACE_START(ata_devices)
	177	SLOT_INTERFACE("hdd", IDE_HARDDISK)
	178	SLOT_INTERFACE_END
	179
	180	ata_interface_device::ata_interface_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) :
	181	device_t(mconfig, type, name, tag, owner, clock),
	182	m_irq_handler(*this),
	183	m_dmarq_handler(*this)
	184	{
	185	}
	186
	187
	188	const device_type ATA_INTERFACE = &device_creator<ata_interface_device>;
	189
	190	ata_interface_device::ata_interface_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	191	device_t(mconfig, ATA_INTERFACE, "ATA Interface", tag, owner, clock),
	192	m_irq_handler(*this),
	193	m_dmarq_handler(*this)
	194	{
	195	}
	196
	197	//-------------------------------------------------
	198	//  device_start - device-specific startup
	199	//-------------------------------------------------
	200
	201	void ata_interface_device::device_start()
	202	{
	203	m_irq_handler.resolve_safe();
	204	m_dmarq_handler.resolve_safe();
	205
	206	/* set MAME harddisk handle */
	207	m_slot[0] = subdevice<ata_slot_device>("0");
	208	m_slot[1] = subdevice<ata_slot_device>("1");
	209
	210	for (int i = 0; i < 2; i++)
	211	{
	212	m_irq[i] = 0;
	213	m_dmarq[i] = 0;
	214
	215	ata_device_interface *dev = m_slot[i]->dev();
	216	if (dev != NULL)
	217	{
	218	if (i == 0)
	219	{
	220	dev->m_irq_handler.set_callback(DEVCB2_DEVWRITELINE("^", ata_interface_device, irq0_write_line));
	221	dev->m_dmarq_handler.set_callback(DEVCB2_DEVWRITELINE("^", ata_interface_device, dmarq0_write_line));
	222	}
	223	else
	224	{
	225	dev->m_irq_handler.set_callback(DEVCB2_DEVWRITELINE("^", ata_interface_device, irq1_write_line));
	226	dev->m_dmarq_handler.set_callback(DEVCB2_DEVWRITELINE("^", ata_interface_device, dmarq1_write_line));
	227	}
	228
	229	dev->write_csel(i);
	230	dev->write_dasp(m_slot[1]->dev() != NULL);
	231	}
	232	}
	233	}
	234
	235	//-------------------------------------------------
	236	//  device_reset - device-specific reset
	237	//-------------------------------------------------
	238
	239	void ata_interface_device::device_reset()
	240	{
	241	LOG(("ATA interface reset\n"));
	242	}
	243
	244
	245
	246	//**************************************************************************
	247	//  ATA SLOT DEVICE
	248	//**************************************************************************
	249
	250	// device type definition
	251	const device_type ATA_SLOT = &device_creator<ata_slot_device>;
	252
	253	//-------------------------------------------------
	254	//  ata_slot_device - constructor
	255	//-------------------------------------------------
	256
	257	ata_slot_device::ata_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	258	: device_t(mconfig, ATA_SLOT, "ATA Connector", tag, owner, clock),
	259	device_slot_interface(mconfig, *this),
	260	m_dev(NULL)
	261	{
	262	}
	263
	264	//-------------------------------------------------
	265	//  device_config_complete - perform any
	266	//  operations now that the configuration is
	267	//  complete
	268	//-------------------------------------------------
	269
	270	void ata_slot_device::device_config_complete()
	271	{
	272	m_dev = dynamic_cast<ata_device_interface *>(get_card_device());
	273	}
	274
	275	//-------------------------------------------------
	276	//  device_start - device-specific startup
	277	//-------------------------------------------------
	278
	279	void ata_slot_device::device_start()
	280	{
	281	}

Property changes on: trunk/src/emu/machine/ataintf.c

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trunk/src/emu/machine/ataintf.h

r0	r23787
	1	/***************************************************************************
	2
	3	ataintf.h
	4
	5	ATA Interface implementation.
	6
	7	Copyright Nicola Salmoria and the MAME Team.
	8	Visit http://mamedev.org for licensing and usage restrictions.
	9
	10	***************************************************************************/
	11
	12	#pragma once
	13
	14	#ifndef __ATAINTF_H__
	15	#define __ATAINTF_H__
	16
	17	#include "atadev.h"
	18
	19	/***************************************************************************
	20	TYPE DEFINITIONS
	21	***************************************************************************/
	22
	23	// ======================> ata_slot_device
	24
	25	class ata_slot_device : public device_t,
	26	public device_slot_interface
	27	{
	28	public:
	29	// construction/destruction
	30	ata_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	31
	32	ata_device_interface *dev() { return m_dev; }
	33	protected:
	34	// device-level overrides
	35	virtual void device_start();
	36	virtual void device_config_complete();
	37	private:
	38	ata_device_interface *m_dev;
	39	};
	40
	41	// device type definition
	42	extern const device_type ATA_SLOT;
	43
	44	/***************************************************************************
	45	TYPE DEFINITIONS
	46	***************************************************************************/
	47
	48	#define MCFG_ATA_INTERFACE_IRQ_HANDLER(_devcb) \
	49	devcb = &ata_interface_device::set_irq_handler(*device, DEVCB2_##_devcb);
	50
	51	#define MCFG_ATA_INTERFACE_DMARQ_HANDLER(_devcb) \
	52	devcb = &ata_interface_device::set_dmarq_handler(*device, DEVCB2_##_devcb);
	53
	54	SLOT_INTERFACE_EXTERN(ata_devices);
	55
	56	/***************************************************************************
	57	DEVICE CONFIGURATION MACROS
	58	***************************************************************************/
	59
	60	#define MCFG_ATA_INTERFACE_ADD(_tag, _slotintf, _master, _slave, _fixed) \
	61	MCFG_DEVICE_ADD(_tag, ATA_INTERFACE, 0) \
	62	MCFG_ATA_SLOT_ADD(_tag ":0", _slotintf, _master, _fixed) \
	63	MCFG_ATA_SLOT_ADD(_tag ":1", _slotintf, _slave, _fixed) \
	64	MCFG_DEVICE_MODIFY(_tag)
	65
	66	#define MCFG_ATA_SLOT_ADD(_tag, _slot_intf, _def_slot, _fixed) \
	67	MCFG_DEVICE_ADD(_tag, ATA_SLOT, 0) \
	68	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, _fixed)
	69
	70	/***************************************************************************
	71	TYPE DEFINITIONS
	72	***************************************************************************/
	73
	74	/* ----- device interface ----- */
	75
	76	class ata_interface_device : public device_t
	77	{
	78	public:
	79	ata_interface_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	80	ata_interface_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
	81
	82	// static configuration helpers
	83	template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<ata_interface_device &>(device).m_irq_handler.set_callback(object); }
	84	template<class _Object> static devcb2_base &set_dmarq_handler(device_t &device, _Object object) { return downcast<ata_interface_device &>(device).m_dmarq_handler.set_callback(object); }
	85
	86	UINT8 *identify_device_buffer(int drive);
	87	void set_master_password(int drive, const UINT8 *password);
	88	void set_user_password(int drive, const UINT8 *password);
	89
	90	UINT16 read_dma();
	91	virtual DECLARE_READ16_MEMBER(read_cs0);
	92	virtual DECLARE_READ16_MEMBER(read_cs1);
	93
	94	void write_dma(UINT16 data);
	95	virtual DECLARE_WRITE16_MEMBER(write_cs0);
	96	virtual DECLARE_WRITE16_MEMBER(write_cs1);
	97	DECLARE_WRITE_LINE_MEMBER(write_dmack);
	98
	99	protected:
	100	// device-level overrides
	101	virtual void device_start();
	102	virtual void device_reset();
	103
	104	virtual void set_irq(int state);
	105	virtual void set_dmarq(int state);
	106
	107	private:
	108	DECLARE_WRITE_LINE_MEMBER(irq0_write_line);
	109	DECLARE_WRITE_LINE_MEMBER(dmarq0_write_line);
	110
	111	DECLARE_WRITE_LINE_MEMBER(irq1_write_line);
	112	DECLARE_WRITE_LINE_MEMBER(dmarq1_write_line);
	113
	114	ata_slot_device *m_slot[2];
	115	int m_irq[2];
	116	int m_dmarq[2];
	117
	118	devcb2_write_line m_irq_handler;
	119	devcb2_write_line m_dmarq_handler;
	120	};
	121
	122	extern const device_type ATA_INTERFACE;
	123
	124	#endif  /* __ATAINTF_H__ */

Property changes on: trunk/src/emu/machine/ataintf.h

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trunk/src/emu/machine/ataflash.h

r23786	r23787
4	4	#define __ATAFLASH_H__
5	5
6	6	#include "pccard.h"
7		#include "machine/idectrl.h"
	7	#include "machine/idehd.h"
8	8
9	9	extern const device_type ATA_FLASH_PCCARD;
10	10

trunk/src/emu/machine/idehd.c

r23786	r23787
48	48	#define IDE_COMMAND_IDENTIFY_DEVICE         0xec
49	49	#define IDE_COMMAND_SET_FEATURES            0xef
50	50	#define IDE_COMMAND_SECURITY_UNLOCK         0xf2
51		#define IDE_COMMAND_UNKNOWN_F9              0xf9
	51	#define IDE_COMMAND_SET_MAX              0xf9
52	52	#define IDE_COMMAND_VERIFY_SECTORS          0x40
53	53	#define IDE_COMMAND_VERIFY_SECTORS_NORETRY  0x41
54	54	#define IDE_COMMAND_ATAPI_IDENTIFY          0xa1
r23786	r23787
70	70	TID_WRITE_SECTOR_DONE_CALLBACK
71	71	};
72	72
73		//**************************************************************************
74		//  IDE DEVICE INTERFACE
75		//**************************************************************************
76
77		//-------------------------------------------------
78		//  ide_device_interface - constructor
79		//-------------------------------------------------
80
81		ide_device_interface::ide_device_interface(const machine_config &mconfig, device_t &device) :
82		m_master_password(NULL),
83		m_user_password(NULL),
84		m_irq_handler(device),
85		m_dmarq_handler(device)
86		{
87		}
88
89		ide_mass_storage_device::ide_mass_storage_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock,const char *shortname, const char *source)
	73	ata_mass_storage_device::ata_mass_storage_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock,const char *shortname, const char *source)
90	74	: device_t(mconfig, type, name, tag, owner, clock, shortname, source),
91		ide_device_interface(mconfig, *this),
	75	ata_device_interface(mconfig, *this),
92	76	device_slot_card_interface(mconfig, *this),
93	77	m_csel(0),
94	78	m_dasp(0),
r23786	r23787
98	82	{
99	83	}
100	84
101		void ide_mass_storage_device::update_irq()
	85	void ata_mass_storage_device::update_irq()
102	86	{
103	87	if (device_selected() && (m_device_control & IDE_DEVICE_CONTROL_NIEN) == 0)
104	88	m_irq_handler(m_irq);
r23786	r23787
106	90	m_irq_handler(CLEAR_LINE);
107	91	}
108	92
109		void ide_mass_storage_device::set_irq(int state)
	93	void ata_mass_storage_device::set_irq(int state)
110	94	{
111	95	if (m_irq != state)
112	96	{
r23786	r23787
121	105	}
122	106	}
123	107
124		void ide_mass_storage_device::set_dmarq(int state)
	108	void ata_mass_storage_device::set_dmarq(int state)
125	109	{
126	110	if (m_dmarq != state)
127	111	{
r23786	r23787
131	115	}
132	116	}
133	117
134		WRITE_LINE_MEMBER( ide_mass_storage_device::write_csel )
	118	WRITE_LINE_MEMBER( ata_mass_storage_device::write_csel )
135	119	{
136	120	m_csel = state;
137	121	}
138	122
139		WRITE_LINE_MEMBER( ide_mass_storage_device::write_dasp )
	123	WRITE_LINE_MEMBER( ata_mass_storage_device::write_dasp )
140	124	{
141	125	m_dasp = state;
142	126	}
143	127
144		WRITE_LINE_MEMBER( ide_mass_storage_device::write_dmack )
	128	WRITE_LINE_MEMBER( ata_mass_storage_device::write_dmack )
145	129	{
146	130	m_dmack = state;
147	131	}
r23786	r23787
152	136	*
153	137	*************************************/
154	138
155		UINT32 ide_mass_storage_device::lba_address()
	139	UINT32 ata_mass_storage_device::lba_address()
156	140	{
157	141	/* LBA direct? */
158	142	if (m_device_head & IDE_DEVICE_HEAD_L)
r23786	r23787
183	167	}
184	168
185	169
186		void ide_mass_storage_device::ide_build_identify_device()
	170	void ata_mass_storage_device::ide_build_identify_device()
187	171	{
188	172	memset(m_identify_device, 0, IDE_DISK_SECTOR_SIZE);
189	173	int total_sectors = m_num_cylinders * m_num_heads * m_num_sectors;
r23786	r23787
343	327	//  device_start - device-specific startup
344	328	//-------------------------------------------------
345	329
346		void ide_mass_storage_device::device_start()
	330	void ata_mass_storage_device::device_start()
347	331	{
348	332	m_irq_handler.resolve_safe();
349	333	m_dmarq_handler.resolve_safe();
r23786	r23787
376	360	m_reset_timer = timer_alloc(TID_RESET_CALLBACK);
377	361	}
378	362
379		void ide_mass_storage_device::device_reset()
	363	void ata_mass_storage_device::device_reset()
380	364	{
381	365	m_buffer_offset = 0;
382	366	m_master_password_enable = (m_master_password != NULL);
r23786	r23787
405	389	set_dmarq(CLEAR_LINE);
406	390	}
407	391
408		void ide_mass_storage_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
	392	void ata_mass_storage_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
409	393	{
410	394	switch(id)
411	395	{
r23786	r23787
442	426	*
443	427	*************************************/
444	428
445		void ide_mass_storage_device::next_sector()
	429	void ata_mass_storage_device::next_sector()
446	430	{
447	431	UINT8 cur_head = m_device_head & IDE_DEVICE_HEAD_HS;
448	432
r23786	r23787
495	479	*
496	480	*************************************/
497	481
498		void ide_mass_storage_device::security_error()
	482	void ata_mass_storage_device::security_error()
499	483	{
500	484	/* set error state */
501	485	m_status |= IDE_STATUS_ERR;
r23786	r23787
511	495	*
512	496	*************************************/
513	497
514		void ide_mass_storage_device::read_buffer_empty()
	498	void ata_mass_storage_device::read_buffer_empty()
515	499	{
516	500	/* reset the totals */
517	501	m_buffer_offset = 0;
r23786	r23787
522	506	fill_buffer();
523	507	}
524	508
525		void ide_mass_storage_device::fill_buffer()
	509	void ata_mass_storage_device::fill_buffer()
526	510	{
527	511	switch (m_command)
528	512	{
r23786	r23787
548	532	}
549	533
550	534
551		void ide_mass_storage_device::read_sector_done()
	535	void ata_mass_storage_device::read_sector_done()
552	536	{
553	537	int lba = lba_address(), count = 0;
554	538
r23786	r23787
600	584	}
601	585
602	586
603		void ide_mass_storage_device::read_first_sector()
	587	void ata_mass_storage_device::read_first_sector()
604	588	{
605	589	/* mark ourselves busy */
606	590	m_status |= IDE_STATUS_BSY;
r23786	r23787
624	608	}
625	609
626	610
627		void ide_mass_storage_device::read_next_sector()
	611	void ata_mass_storage_device::read_next_sector()
628	612	{
629	613	/* mark ourselves busy */
630	614	m_status |= IDE_STATUS_BSY;
r23786	r23787
651	635	*
652	636	*************************************/
653	637
654		void ide_mass_storage_device::continue_write()
	638	void ata_mass_storage_device::continue_write()
655	639	{
656	640	/* reset the totals */
657	641	m_buffer_offset = 0;
r23786	r23787
680	664	}
681	665
682	666
683		void ide_mass_storage_device::write_buffer_full()
	667	void ata_mass_storage_device::write_buffer_full()
684	668	{
685	669	m_status &= ~IDE_STATUS_DRQ;
686	670	set_dmarq(CLEAR_LINE);
r23786	r23787
688	672	process_buffer();
689	673	}
690	674
691		void ide_mass_storage_device::process_buffer()
	675	void ata_mass_storage_device::process_buffer()
692	676	{
693	677	if (m_command == IDE_COMMAND_SECURITY_UNLOCK)
694	678	{
r23786	r23787
727	711	}
728	712
729	713
730		void ide_mass_storage_device::write_sector_done()
	714	void ata_mass_storage_device::write_sector_done()
731	715	{
732	716	int lba = lba_address(), count = 0;
733	717
r23786	r23787
783	767	*
784	768	*************************************/
785	769
786		bool ide_mass_storage_device::process_command()
	770	bool ata_mass_storage_device::process_command()
787	771	{
788	772	switch (m_command)
789	773	{
r23786	r23787
923	907	timer_set(MINIMUM_COMMAND_TIME, TID_DELAYED_INTERRUPT);
924	908	return true;
925	909
926		case IDE_COMMAND_UNKNOWN_F9:
927		/* only used by Killer Instinct AFAICT */
928		LOGPRINT(("IDE unknown command (F9)\n"));
	910	case IDE_COMMAND_SET_MAX:
	911	LOGPRINT(("IDE Set max (%02X %02X %02X %02X %02X)\n", m_feature, m_sector_count & 0xff, m_sector_number, m_cylinder_low, m_cylinder_high));
929	912
930	913	/* signal an interrupt */
931	914	set_irq(ASSERT_LINE);
r23786	r23787
957	940	}
958	941	}
959	942
960		UINT16 ide_mass_storage_device::read_dma()
	943	UINT16 ata_mass_storage_device::read_dma()
961	944	{
962	945	UINT16 result = 0xffff;
963	946
r23786	r23787
995	978	return result;
996	979	}
997	980
998		READ16_MEMBER( ide_mass_storage_device::read_cs0 )
	981	READ16_MEMBER( ata_mass_storage_device::read_cs0 )
999	982	{
1000	983	/* logit */
1001	984	//  if (offset != IDE_CS0_DATA_RW && offset != IDE_CS0_STATUS_R)
r23786	r23787
1131	1114	return result;
1132	1115	}
1133	1116
1134		READ16_MEMBER( ide_mass_storage_device::read_cs1 )
	1117	READ16_MEMBER( ata_mass_storage_device::read_cs1 )
1135	1118	{
1136	1119	/* logit */
1137	1120	//  if (offset != IDE_CS1_ALTERNATE_STATUS_R)
r23786	r23787
1178	1161	return result;
1179	1162	}
1180	1163
1181		void ide_mass_storage_device::write_dma( UINT16 data )
	1164	void ata_mass_storage_device::write_dma( UINT16 data )
1182	1165	{
1183	1166	if (device_selected())
1184	1167	{
r23786	r23787
1213	1196	}
1214	1197	}
1215	1198
1216		WRITE16_MEMBER( ide_mass_storage_device::write_cs0 )
	1199	WRITE16_MEMBER( ata_mass_storage_device::write_cs0 )
1217	1200	{
1218	1201	/* logit */
1219	1202	if (offset != IDE_CS0_DATA_RW)
r23786	r23787
1327	1310	}
1328	1311	}
1329	1312
1330		WRITE16_MEMBER( ide_mass_storage_device::write_cs1 )
	1313	WRITE16_MEMBER( ata_mass_storage_device::write_cs1 )
1331	1314	{
1332	1315	/* logit */
1333	1316	LOG(("%s:IDE cs1 write to %X = %08X, mem_mask=%d\n", machine().describe_context(), offset, data, mem_mask));
r23786	r23787
1376	1359	//-------------------------------------------------
1377	1360
1378	1361	ide_hdd_device::ide_hdd_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
1379		: ide_mass_storage_device(mconfig, IDE_HARDDISK, "IDE Hard Disk", tag, owner, clock, "hdd", __FILE__)
	1362	: ata_mass_storage_device(mconfig, IDE_HARDDISK, "IDE Hard Disk", tag, owner, clock, "hdd", __FILE__),
	1363	m_image(*this, "image")
1380	1364	{
1381	1365	}
1382	1366
1383	1367	ide_hdd_device::ide_hdd_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
1384		: ide_mass_storage_device(mconfig, type, name, tag, owner, clock, shortname, source)
	1368	: ata_mass_storage_device(mconfig, type, name, tag, owner, clock, shortname, source),
	1369	m_image(*this, "image")
1385	1370	{
1386	1371	}
1387	1372
r23786	r23787
1391	1376
1392	1377	void ide_hdd_device::device_reset()
1393	1378	{
1394		m_handle = subdevice<harddisk_image_device>("harddisk")->get_chd_file();
	1379	ata_mass_storage_device::device_reset();
1395	1380
1396		if (m_handle)
1397		{
1398		m_disk = subdevice<harddisk_image_device>("harddisk")->get_hard_disk_file();
1399		}
1400		else
1401		{
1402		m_handle = get_disk_handle(machine(), tag());
1403		m_disk = hard_disk_open(m_handle);
1404		}
	1381	m_handle = m_image->get_chd_file();
	1382	m_disk = m_image->get_hard_disk_file();
1405	1383
1406		ide_mass_storage_device::device_reset();
1407
1408	1384	if (m_disk != NULL)
1409	1385	{
1410	1386	const hard_disk_info *hdinfo = hard_disk_get_info(m_disk);
r23786	r23787
1416	1392	if (PRINTF_IDE_COMMANDS) mame_printf_debug("CHS: %d %d %d\n", m_num_cylinders, m_num_heads, m_num_sectors);
1417	1393	mame_printf_debug("CHS: %d %d %d\n", m_num_cylinders, m_num_heads, m_num_sectors);
1418	1394	}
	1395
1419	1396	// build the features page
1420	1397	UINT32 metalength;
1421	1398	if (m_handle->read_metadata (HARD_DISK_IDENT_METADATA_TAG, 0, m_identify_device, IDE_DISK_SECTOR_SIZE, metalength) != CHDERR_NONE)
r23786	r23787
1430	1407	//  machine configurations
1431	1408	//-------------------------------------------------
1432	1409	static MACHINE_CONFIG_FRAGMENT( hdd_image )
1433		MCFG_HARDDISK_ADD( "harddisk" )
	1410	MCFG_HARDDISK_ADD( "image" )
1434	1411	MACHINE_CONFIG_END
1435	1412
1436	1413	machine_config_constructor ide_hdd_device::device_mconfig_additions() const

trunk/src/emu/machine/idehd.h

r23786	r23787
1	1	#include "emu.h"
	2	#include "atadev.h"
	3	#include "harddisk.h"
2	4	#include "imagedev/harddriv.h"
3	5
4	6	#define IDE_DISK_SECTOR_SIZE            512
r23786	r23787
42	44	#define IDE_DEVICE_HEAD_DRV  0x10
43	45	#define IDE_DEVICE_HEAD_L    0x40
44	46
45		// ======================> ide_device_interface
46
47		class ide_device_interface
48		{
49		public:
50		ide_device_interface(const machine_config &mconfig, device_t &device);
51		virtual ~ide_device_interface() {}
52
53		virtual UINT16 read_dma() = 0;
54		virtual DECLARE_READ16_MEMBER(read_cs0) = 0;
55		virtual DECLARE_READ16_MEMBER(read_cs1) = 0;
56
57		virtual void write_dma(UINT16 data) = 0;
58		virtual DECLARE_WRITE16_MEMBER(write_cs0) = 0;
59		virtual DECLARE_WRITE16_MEMBER(write_cs1) = 0;
60		virtual DECLARE_WRITE_LINE_MEMBER(write_dmack) = 0;
61		virtual DECLARE_WRITE_LINE_MEMBER(write_csel) = 0;
62		virtual DECLARE_WRITE_LINE_MEMBER(write_dasp) = 0;
63
64		virtual bool is_ready() { return true; }
65		virtual UINT8 *identify_device_buffer() = 0;
66
67		UINT8           m_master_password_enable;
68		UINT8           m_user_password_enable;
69		const UINT8 *   m_master_password;
70		const UINT8 *   m_user_password;
71
72		devcb2_write_line m_irq_handler;
73		devcb2_write_line m_dmarq_handler;
74		};
75
76		class ide_mass_storage_device : public device_t,
77		public ide_device_interface,
	47	class ata_mass_storage_device : public device_t,
	48	public ata_device_interface,
78	49	public device_slot_card_interface
79	50	{
80	51	public:
81		ide_mass_storage_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock,const char *shortname = "", const char *source = __FILE__);
	52	ata_mass_storage_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock,const char *shortname = "", const char *source = __FILE__);
82	53
83	54	virtual UINT16 read_dma();
84	55	virtual DECLARE_READ16_MEMBER(read_cs0);
r23786	r23787
98	69	virtual void device_reset();
99	70	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
100	71
	72	virtual bool is_ready() { return true; }
101	73	virtual int read_sector(UINT32 lba, void *buffer) = 0;
102	74	virtual int write_sector(UINT32 lba, const void *buffer) = 0;
103	75
r23786	r23787
163	135
164	136	// ======================> ide_hdd_device
165	137
166		class ide_hdd_device : public ide_mass_storage_device
	138	class ide_hdd_device : public ata_mass_storage_device
167	139	{
168	140	public:
169	141	// construction/destruction
r23786	r23787
182	154
183	155	chd_file       *m_handle;
184	156	hard_disk_file *m_disk;
	157
	158	private:
	159	required_device<harddisk_image_device> m_image;
185	160	};
186	161
187	162	// device type definition

trunk/src/emu/machine/idectrl.c

r23786	r23787
1	1	/***************************************************************************
2	2
3		Generic (PC-style) IDE controller implementation
	3	idectrl.c
4	4
	5	Generic (PC-style) IDE controller implementation.
	6
	7	Copyright Nicola Salmoria and the MAME Team.
	8	Visit http://mamedev.org for licensing and usage restrictions.
	9
5	10	***************************************************************************/
6	11
7		#include "emu.h"
8	12	#include "idectrl.h"
9		#include "debugger.h"
10	13
	14
11	15	/***************************************************************************
12	16	DEBUGGING
13	17	***************************************************************************/
14	18
15	19	#define VERBOSE                     0
16		#define PRINTF_IDE_COMMANDS         0
17		#define PRINTF_IDE_PASSWORD         0
18	20
19	21	#define LOG(x)  do { if (VERBOSE) logerror x; } while (0)
20	22
21		#define LOGPRINT(x) do { if (VERBOSE) logerror x; if (PRINTF_IDE_COMMANDS) mame_printf_debug x; } while (0)
22	23
23
24
25	24	/***************************************************************************
26	25	CONSTANTS
27	26	***************************************************************************/
r23786	r23787
30	29	#define IDE_BANK2_CONFIG_REGISTER           8
31	30	#define IDE_BANK2_CONFIG_DATA               0xc
32	31
	32	const device_type IDE_CONTROLLER = &device_creator<ide_controller_device>;
33	33
34		void ide_controller_device::set_irq(int state)
	34	ide_controller_device::ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	35	ata_interface_device(mconfig, IDE_CONTROLLER, "IDE Controller", tag, owner, clock),
	36	m_config_unknown(0),
	37	m_config_register_num(0)
35	38	{
36		if (state == ASSERT_LINE)
37		LOG(("IDE interrupt assert\n"));
38		else
39		LOG(("IDE interrupt clear\n"));
40
41		/* signal an interrupt */
42		m_irq_handler(state);
43	39	}
44	40
45		void ide_controller_device::set_dmarq(int state)
	41	ide_controller_device::ide_controller_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) :
	42	ata_interface_device(mconfig, type, name, tag, owner, clock),
	43	m_config_unknown(0),
	44	m_config_register_num(0)
46	45	{
47		m_dmarq_handler(state);
48	46	}
49	47
50		WRITE_LINE_MEMBER( ide_controller_device::irq0_write_line )
51		{
52		m_irq[0] = state;
	48	//-------------------------------------------------
	49	//  device_start - device-specific startup
	50	//-------------------------------------------------
53	51
54		set_irq(m_irq[0] == ASSERT_LINE || m_irq[1] == ASSERT_LINE);
55		}
56
57		WRITE_LINE_MEMBER( ide_controller_device::irq1_write_line )
	52	void ide_controller_device::device_start()
58	53	{
59		m_irq[1] = state;
	54	ata_interface_device::device_start();
60	55
61		set_irq(m_irq[0] == ASSERT_LINE || m_irq[1] == ASSERT_LINE);
	56	/* register ide states */
	57	save_item(NAME(m_config_unknown));
	58	save_item(NAME(m_config_register));
	59	save_item(NAME(m_config_register_num));
62	60	}
63	61
64		WRITE_LINE_MEMBER( ide_controller_device::dmarq0_write_line )
65		{
66		m_dmarq[0] = state;
67
68		set_dmarq(m_dmarq[0] == ASSERT_LINE || m_dmarq[1] == ASSERT_LINE);
69		}
70
71		WRITE_LINE_MEMBER( ide_controller_device::dmarq1_write_line )
72		{
73		m_dmarq[1] = state;
74
75		set_dmarq(m_dmarq[0] == ASSERT_LINE || m_dmarq[1] == ASSERT_LINE);
76		}
77
78
79		/***************************************************************************
80		INITIALIZATION AND RESET
81		***************************************************************************/
82
83		UINT8 *ide_controller_device::identify_device_buffer(int _drive)
84		{
85		return m_slot[_drive]->dev()->identify_device_buffer();
86		}
87
88		void ide_controller_device::ide_set_master_password(int _drive, const UINT8 *password)
89		{
90		m_slot[_drive]->dev()->m_master_password = password;
91		m_slot[_drive]->dev()->m_master_password_enable = (password != NULL);
92		}
93
94
95		void ide_controller_device::ide_set_user_password(int _drive, const UINT8 *password)
96		{
97		m_slot[_drive]->dev()->m_user_password = password;
98		m_slot[_drive]->dev()->m_user_password_enable = (password != NULL);
99		}
100
101		/*************************************
102		*
103		*  IDE controller read
104		*
105		*************************************/
106
107		UINT16 ide_controller_device::read_dma()
108		{
109		UINT16 result = 0xffff;
110		for (int i = 0; i < 2; i++)
111		if (m_slot[i]->dev() != NULL)
112		result &= m_slot[i]->dev()->read_dma();
113
114		//  printf( "read_dma %04x\n", result );
115		return result;
116		}
117
118		READ16_MEMBER( ide_controller_device::read_cs0 )
119		{
120		UINT16 result = mem_mask;
121		for (int i = 0; i < 2; i++)
122		if (m_slot[i]->dev() != NULL)
123		result &= m_slot[i]->dev()->read_cs0(space, offset, mem_mask);
124
125		//  printf( "read cs0 %04x %04x %04x\n", offset, result, mem_mask );
126
127		return result;
128		}
129
130		READ16_MEMBER( ide_controller_device::read_cs1 )
131		{
132		UINT16 result = mem_mask;
133		for (int i = 0; i < 2; i++)
134		if (m_slot[i]->dev() != NULL)
135		result &= m_slot[i]->dev()->read_cs1(space, offset, mem_mask);
136
137		//  printf( "read cs1 %04x %04x %04x\n", offset, result, mem_mask );
138
139		return result;
140		}
141
142	62	READ8_MEMBER( ide_controller_device::read_via_config )
143	63	{
144	64	UINT16 result = 0;
r23786	r23787
173	93	return result;
174	94	}
175	95
176		READ16_MEMBER( ide_controller_device::read_cs0_pc )
	96	READ16_MEMBER( ide_controller_device::read_cs0 )
177	97	{
178	98	if (mem_mask == 0xffff && offset == 1 ) offset = 0; // hack for 32 bit read of data register
179	99	if (mem_mask == 0xff00)
180	100	{
181		return read_cs0(space, (offset * 2) + 1, 0xff) << 8;
	101	return ata_interface_device::read_cs0(space, (offset * 2) + 1, 0xff) << 8;
182	102	}
183	103	else
184	104	{
185		return read_cs0(space, offset * 2, mem_mask);
	105	return ata_interface_device::read_cs0(space, offset * 2, mem_mask);
186	106	}
187	107	}
188	108
189		READ16_MEMBER( ide_controller_device::read_cs1_pc )
	109	READ16_MEMBER( ide_controller_device::read_cs1 )
190	110	{
191	111	if (mem_mask == 0xff00)
192	112	{
193		return read_cs1(space, (offset * 2) + 1, 0xff) << 8;
	113	return ata_interface_device::read_cs1(space, (offset * 2) + 1, 0xff) << 8;
194	114	}
195	115	else
196	116	{
197		return read_cs1(space, offset * 2, mem_mask);
	117	return ata_interface_device::read_cs1(space, offset * 2, mem_mask);
198	118	}
199	119	}
200	120
201
202		/*************************************
203		*
204		*  IDE controller write
205		*
206		*************************************/
207
208		void ide_controller_device::write_dma( UINT16 data )
209		{
210		//  printf( "write_dma %04x\n", data );
211
212		for (int i = 0; i < 2; i++)
213		if (m_slot[i]->dev() != NULL)
214		m_slot[i]->dev()->write_dma(data);
215		}
216
217		WRITE16_MEMBER( ide_controller_device::write_cs0 )
218		{
219		//  printf( "write cs0 %04x %04x %04x\n", offset, data, mem_mask );
220
221		for (int i = 0; i < 2; i++)
222		if (m_slot[i]->dev() != NULL)
223		m_slot[i]->dev()->write_cs0(space, offset, data, mem_mask);
224		}
225
226		WRITE16_MEMBER( ide_controller_device::write_cs1 )
227		{
228		//  printf( "write cs1 %04x %04x %04x\n", offset, data, mem_mask );
229
230		for (int i = 0; i < 2; i++)
231		if (m_slot[i]->dev() != NULL)
232		m_slot[i]->dev()->write_cs1(space, offset, data, mem_mask);
233		}
234
235		WRITE_LINE_MEMBER( ide_controller_device::write_dmack )
236		{
237		//  printf( "write_dmack %04x\n", state );
238
239		for (int i = 0; i < 2; i++)
240		if (m_slot[i]->dev() != NULL)
241		m_slot[i]->dev()->write_dmack(state);
242		}
243
244	121	WRITE8_MEMBER( ide_controller_device::write_via_config )
245	122	{
246	123	//  printf( "write via config %04x %04x %04x\n", offset, data, mem_mask );
r23786	r23787
268	145	}
269	146	}
270	147
271		WRITE16_MEMBER( ide_controller_device::write_cs0_pc )
	148	WRITE16_MEMBER( ide_controller_device::write_cs0 )
272	149	{
273	150	if (mem_mask == 0xffff && offset == 1 ) offset = 0; // hack for 32 bit write to data register
274	151	if (mem_mask == 0xff00)
275	152	{
276		return write_cs0(space, (offset * 2) + 1, data >> 8, 0xff);
	153	return ata_interface_device::write_cs0(space, (offset * 2) + 1, data >> 8, 0xff);
277	154	}
278	155	else
279	156	{
280		return write_cs0(space, offset * 2, data, mem_mask);
	157	return ata_interface_device::write_cs0(space, offset * 2, data, mem_mask);
281	158	}
282	159	}
283	160
284		WRITE16_MEMBER( ide_controller_device::write_cs1_pc )
	161	WRITE16_MEMBER( ide_controller_device::write_cs1 )
285	162	{
286	163	if (mem_mask == 0xff00)
287	164	{
288		return write_cs1(space, (offset * 2) + 1, data >> 8, 0xff);
	165	return ata_interface_device::write_cs1(space, (offset * 2) + 1, data >> 8, 0xff);
289	166	}
290	167	else
291	168	{
292		return write_cs1(space, offset * 2, data, mem_mask);
	169	return ata_interface_device::write_cs1(space, offset * 2, data, mem_mask);
293	170	}
294	171	}
295	172
296		SLOT_INTERFACE_START(ide_devices)
297		SLOT_INTERFACE("hdd", IDE_HARDDISK)
298		SLOT_INTERFACE_END
299
300		ide_controller_device::ide_controller_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) :
301		device_t(mconfig, type, name, tag, owner, clock),
302		m_config_unknown(0),
303		m_config_register_num(0),
304		m_irq_handler(*this),
305		m_dmarq_handler(*this)
306		{
307		}
308
309
310		const device_type IDE_CONTROLLER = &device_creator<ide_controller_device>;
311
312		ide_controller_device::ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
313		device_t(mconfig, IDE_CONTROLLER, "IDE Controller", tag, owner, clock),
314		m_config_unknown(0),
315		m_config_register_num(0),
316		m_irq_handler(*this),
317		m_dmarq_handler(*this)
318		{
319		}
320
321		//-------------------------------------------------
322		//  device_start - device-specific startup
323		//-------------------------------------------------
324
325		void ide_controller_device::device_start()
326		{
327		m_irq_handler.resolve_safe();
328		m_dmarq_handler.resolve_safe();
329
330		/* set MAME harddisk handle */
331		m_slot[0] = subdevice<ide_slot_device>("0");
332		m_slot[1] = subdevice<ide_slot_device>("1");
333
334		for (int i = 0; i < 2; i++)
335		{
336		m_irq[i] = 0;
337		m_dmarq[i] = 0;
338
339		ide_device_interface *dev = m_slot[i]->dev();
340		if (dev != NULL)
341		{
342		if (i == 0)
343		{
344		dev->m_irq_handler.set_callback(DEVCB2_DEVWRITELINE("^", ide_controller_device, irq0_write_line));
345		dev->m_dmarq_handler.set_callback(DEVCB2_DEVWRITELINE("^", ide_controller_device, dmarq0_write_line));
346		}
347		else
348		{
349		dev->m_irq_handler.set_callback(DEVCB2_DEVWRITELINE("^", ide_controller_device, irq1_write_line));
350		dev->m_dmarq_handler.set_callback(DEVCB2_DEVWRITELINE("^", ide_controller_device, dmarq1_write_line));
351		}
352
353		dev->write_csel(i);
354		dev->write_dasp(m_slot[1]->dev() != NULL);
355		}
356		}
357
358		/* register ide states */
359		save_item(NAME(m_config_unknown));
360		save_item(NAME(m_config_register));
361		save_item(NAME(m_config_register_num));
362		}
363
364		//-------------------------------------------------
365		//  device_reset - device-specific reset
366		//-------------------------------------------------
367
368		void ide_controller_device::device_reset()
369		{
370		LOG(("IDE controller reset performed\n"));
371		}
372
373
374
375		//**************************************************************************
376		//  IDE SLOT DEVICE
377		//**************************************************************************
378
379		// device type definition
380		const device_type IDE_SLOT = &device_creator<ide_slot_device>;
381
382		//-------------------------------------------------
383		//  ide_slot_device - constructor
384		//-------------------------------------------------
385
386		ide_slot_device::ide_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
387		: device_t(mconfig, IDE_SLOT, "IDE Connector", tag, owner, clock),
388		device_slot_interface(mconfig, *this),
389		m_dev(NULL)
390		{
391		}
392
393		//-------------------------------------------------
394		//  device_config_complete - perform any
395		//  operations now that the configuration is
396		//  complete
397		//-------------------------------------------------
398
399		void ide_slot_device::device_config_complete()
400		{
401		m_dev = dynamic_cast<ide_device_interface *>(get_card_device());
402		}
403
404		//-------------------------------------------------
405		//  device_start - device-specific startup
406		//-------------------------------------------------
407
408		void ide_slot_device::device_start()
409		{
410		}
411
412
413
414	173	#define IDE_BUSMASTER_STATUS_ACTIVE         0x01
415	174	#define IDE_BUSMASTER_STATUS_ERROR          0x02
416	175	#define IDE_BUSMASTER_STATUS_IRQ            0x04
r23786	r23787
459	218
460	219	void bus_master_ide_controller_device::set_irq(int state)
461	220	{
462		ide_controller_device::set_irq(state);
	221	ata_interface_device::set_irq(state);
463	222
464	223	if (m_irq != state)
465	224	{
r23786	r23787
472	231
473	232	void bus_master_ide_controller_device::set_dmarq(int state)
474	233	{
475		ide_controller_device::set_dmarq(state);
	234	ata_interface_device::set_dmarq(state);
476	235
477	236	if (m_dmarq != state)
478	237	{

trunk/src/emu/machine/idectrl.h

r23786	r23787
14	14	#ifndef __IDECTRL_H__
15	15	#define __IDECTRL_H__
16	16
17		#include "idehd.h"
18		#include "harddisk.h"
	17	#include "ataintf.h"
19	18
20	19	/***************************************************************************
21		TYPE DEFINITIONS
22		***************************************************************************/
23
24		// ======================> ide_slot_device
25
26		class ide_slot_device : public device_t,
27		public device_slot_interface
28		{
29		public:
30		// construction/destruction
31		ide_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
32
33		ide_device_interface *dev() { return m_dev; }
34		protected:
35		// device-level overrides
36		virtual void device_start();
37		virtual void device_config_complete();
38		private:
39		ide_device_interface *m_dev;
40		};
41
42		// device type definition
43		extern const device_type IDE_SLOT;
44
45		/***************************************************************************
46		TYPE DEFINITIONS
47		***************************************************************************/
48
49		#define MCFG_IDE_CONTROLLER_IRQ_HANDLER(_devcb) \
50		devcb = &ide_controller_device::set_irq_handler(*device, DEVCB2_##_devcb);
51
52		#define MCFG_IDE_CONTROLLER_DMARQ_HANDLER(_devcb) \
53		devcb = &ide_controller_device::set_dmarq_handler(*device, DEVCB2_##_devcb);
54
55		SLOT_INTERFACE_EXTERN(ide_devices);
56		SLOT_INTERFACE_EXTERN(ide_devices);
57
58		/***************************************************************************
59	20	DEVICE CONFIGURATION MACROS
60	21	***************************************************************************/
61	22
62	23	#define MCFG_IDE_CONTROLLER_ADD(_tag, _slotintf, _master, _slave, _fixed) \
63	24	MCFG_DEVICE_ADD(_tag, IDE_CONTROLLER, 0) \
64		MCFG_IDE_SLOT_ADD(_tag ":0", _slotintf, _master, _fixed) \
65		MCFG_IDE_SLOT_ADD(_tag ":1", _slotintf, _slave, _fixed) \
	25	MCFG_ATA_SLOT_ADD(_tag ":0", _slotintf, _master, _fixed) \
	26	MCFG_ATA_SLOT_ADD(_tag ":1", _slotintf, _slave, _fixed) \
66	27	MCFG_DEVICE_MODIFY(_tag)
67	28
68		#define MCFG_IDE_SLOT_ADD(_tag, _slot_intf, _def_slot, _fixed) \
69		MCFG_DEVICE_ADD(_tag, IDE_SLOT, 0) \
70		MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, _fixed)
71
72		/***************************************************************************
73		TYPE DEFINITIONS
74		***************************************************************************/
75
76	29	#define IDE_CONFIG_REGISTERS                0x10
77	30
78		/* ----- device interface ----- */
79
80		class ide_controller_device : public device_t
	31	class ide_controller_device : public ata_interface_device
81	32	{
82	33	public:
83	34	ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
84	35	ide_controller_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
85	36
86		// static configuration helpers
87		template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<ide_controller_device &>(device).m_irq_handler.set_callback(object); }
88		template<class _Object> static devcb2_base &set_dmarq_handler(device_t &device, _Object object) { return downcast<ide_controller_device &>(device).m_dmarq_handler.set_callback(object); }
89
90		UINT8 *identify_device_buffer(int drive);
91		void ide_set_master_password(int drive, const UINT8 *password);
92		void ide_set_user_password(int drive, const UINT8 *password);
93
94		UINT16 read_dma();
95		DECLARE_READ16_MEMBER(read_cs0);
96		DECLARE_READ16_MEMBER(read_cs1);
97
98		void write_dma(UINT16 data);
99		DECLARE_WRITE16_MEMBER(write_cs0);
100		DECLARE_WRITE16_MEMBER(write_cs1);
101		DECLARE_WRITE_LINE_MEMBER(write_dmack);
102
103	37	DECLARE_READ8_MEMBER(read_via_config);
104	38	DECLARE_WRITE8_MEMBER(write_via_config);
105		DECLARE_READ16_MEMBER(read_cs0_pc);
106		DECLARE_READ16_MEMBER(read_cs1_pc);
107		DECLARE_WRITE16_MEMBER(write_cs0_pc);
108		DECLARE_WRITE16_MEMBER(write_cs1_pc);
	39	virtual DECLARE_READ16_MEMBER(read_cs0);
	40	virtual DECLARE_READ16_MEMBER(read_cs1);
	41	virtual DECLARE_WRITE16_MEMBER(write_cs0);
	42	virtual DECLARE_WRITE16_MEMBER(write_cs1);
109	43
110	44	protected:
111		// device-level overrides
112	45	virtual void device_start();
113		virtual void device_reset();
114	46
115		virtual void set_irq(int state);
116		virtual void set_dmarq(int state);
117
118	47	private:
119		DECLARE_WRITE_LINE_MEMBER(irq0_write_line);
120		DECLARE_WRITE_LINE_MEMBER(dmarq0_write_line);
121
122		DECLARE_WRITE_LINE_MEMBER(irq1_write_line);
123		DECLARE_WRITE_LINE_MEMBER(dmarq1_write_line);
124
125	48	UINT8           m_config_unknown;
126	49	UINT8           m_config_register[IDE_CONFIG_REGISTERS];
127	50	UINT8           m_config_register_num;
128
129		ide_slot_device *m_slot[2];
130		int m_irq[2];
131		int m_dmarq[2];
132
133		devcb2_write_line m_irq_handler;
134		devcb2_write_line m_dmarq_handler;
135	51	};
136	52
137	53	extern const device_type IDE_CONTROLLER;
r23786	r23787
139	55
140	56	#define MCFG_BUS_MASTER_IDE_CONTROLLER_ADD(_tag, _slotintf, _master, _slave, _fixed) \
141	57	MCFG_DEVICE_ADD(_tag, BUS_MASTER_IDE_CONTROLLER, 0) \
142		MCFG_IDE_SLOT_ADD(_tag ":0", _slotintf, _master, _fixed) \
143		MCFG_IDE_SLOT_ADD(_tag ":1", _slotintf, _slave, _fixed) \
	58	MCFG_ATA_SLOT_ADD(_tag ":0", _slotintf, _master, _fixed) \
	59	MCFG_ATA_SLOT_ADD(_tag ":1", _slotintf, _slave, _fixed) \
144	60	MCFG_DEVICE_MODIFY(_tag)
145	61
146	62	#define MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(bmcpu, bmspace) \

trunk/src/emu/machine/atadev.c

r0	r23787
	1	/***************************************************************************
	2
	3	ATA Device implementation.
	4
	5	***************************************************************************/
	6
	7	#include "atadev.h"
	8
	9	//-------------------------------------------------
	10	//  ata_device_interface - constructor
	11	//-------------------------------------------------
	12
	13	ata_device_interface::ata_device_interface(const machine_config &mconfig, device_t &device) :
	14	m_master_password(NULL),
	15	m_user_password(NULL),
	16	m_irq_handler(device),
	17	m_dmarq_handler(device)
	18	{
	19	}

Property changes on: trunk/src/emu/machine/atadev.c

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trunk/src/emu/machine/atadev.h

r0	r23787
	1	/***************************************************************************
	2
	3	atadev.h
	4
	5	ATA Device implementation.
	6
	7	Copyright Nicola Salmoria and the MAME Team.
	8	Visit http://mamedev.org for licensing and usage restrictions.
	9
	10	***************************************************************************/
	11
	12	#pragma once
	13
	14	#ifndef __ATADEV_H__
	15	#define __ATADEV_H__
	16
	17	#include "emu.h"
	18
	19	// ======================> ata_device_interface
	20
	21	class ata_device_interface
	22	{
	23	public:
	24	ata_device_interface(const machine_config &mconfig, device_t &device);
	25	virtual ~ata_device_interface() {}
	26
	27	virtual UINT16 read_dma() = 0;
	28	virtual DECLARE_READ16_MEMBER(read_cs0) = 0;
	29	virtual DECLARE_READ16_MEMBER(read_cs1) = 0;
	30
	31	virtual void write_dma(UINT16 data) = 0;
	32	virtual DECLARE_WRITE16_MEMBER(write_cs0) = 0;
	33	virtual DECLARE_WRITE16_MEMBER(write_cs1) = 0;
	34	virtual DECLARE_WRITE_LINE_MEMBER(write_dmack) = 0;
	35	virtual DECLARE_WRITE_LINE_MEMBER(write_csel) = 0;
	36	virtual DECLARE_WRITE_LINE_MEMBER(write_dasp) = 0;
	37
	38	virtual UINT8 *identify_device_buffer() = 0;
	39
	40	UINT8           m_master_password_enable;
	41	UINT8           m_user_password_enable;
	42	const UINT8 *   m_master_password;
	43	const UINT8 *   m_user_password;
	44
	45	devcb2_write_line m_irq_handler;
	46	devcb2_write_line m_dmarq_handler;
	47	};
	48
	49	#endif

Property changes on: trunk/src/emu/machine/atadev.h

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/emu/machine/machine.mak

r23786	r23787
473	473	#-------------------------------------------------
474	474
475	475	ifneq ($(filter IDE,$(MACHINES)),)
	476	MACHINEOBJS += $(MACHINEOBJ)/ataintf.o
	477	MACHINEOBJS += $(MACHINEOBJ)/atadev.o
476	478	MACHINEOBJS += $(MACHINEOBJ)/idectrl.o
477	479	MACHINEOBJS += $(MACHINEOBJ)/idehd.o
478	480	endif

trunk/src/mess/drivers/bebox.c

r23786	r23787
53	53	AM_RANGE(0x80000080, 0x8000009F) AM_READWRITE8(bebox_page_r, bebox_page_w, U64(0xffffffffffffffff) )
54	54	AM_RANGE(0x800000A0, 0x800000BF) AM_DEVREADWRITE8("pic8259_2", pic8259_device, read, write, U64(0xffffffffffffffff) )
55	55	AM_RANGE(0x800000C0, 0x800000DF) AM_READWRITE8(at_dma8237_1_r, at_dma8237_1_w, U64(0xffffffffffffffff))
56		AM_RANGE(0x800001F0, 0x800001F7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, U64(0xffffffffffffffff) )
	56	AM_RANGE(0x800001F0, 0x800001F7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, U64(0xffffffffffffffff) )
57	57	AM_RANGE(0x800002F8, 0x800002FF) AM_DEVREADWRITE8( "ns16550_1", ns16550_device, ins8250_r, ins8250_w, U64(0xffffffffffffffff) )
58	58	AM_RANGE(0x80000380, 0x80000387) AM_DEVREADWRITE8( "ns16550_2", ns16550_device, ins8250_r, ins8250_w, U64(0xffffffffffffffff) )
59	59	AM_RANGE(0x80000388, 0x8000038F) AM_DEVREADWRITE8( "ns16550_3", ns16550_device, ins8250_r, ins8250_w, U64(0xffffffffffffffff) )
60	60	AM_RANGE(0x800003b0, 0x800003bf) AM_DEVREADWRITE8("vga", cirrus_vga_device, port_03b0_r, port_03b0_w, U64(0xffffffffffffffff))
61	61	AM_RANGE(0x800003c0, 0x800003cf) AM_DEVREADWRITE8("vga", cirrus_vga_device, port_03c0_r, port_03c0_w, U64(0xffffffffffffffff))
62	62	AM_RANGE(0x800003d0, 0x800003df) AM_DEVREADWRITE8("vga", cirrus_vga_device, port_03d0_r, port_03d0_w, U64(0xffffffffffffffff))
63		AM_RANGE(0x800003F0, 0x800003F7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, U64(0xffffffffffffffff) )
	63	AM_RANGE(0x800003F0, 0x800003F7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, U64(0xffffffffffffffff) )
64	64	AM_RANGE(0x800003F0, 0x800003F7) AM_DEVICE8( "smc37c78", smc37c78_device, map, U64(0xffffffffffffffff) )
65	65	AM_RANGE(0x800003F8, 0x800003FF) AM_DEVREADWRITE8( "ns16550_0",ns16550_device,  ins8250_r, ins8250_w, U64(0xffffffffffffffff) )
66	66	AM_RANGE(0x80000480, 0x8000048F) AM_READWRITE8(bebox_80000480_r, bebox_80000480_w, U64(0xffffffffffffffff) )
r23786	r23787
218	218	MCFG_SCSIDEV_ADD("scsi:cdrom", SCSICD, SCSI_ID_3)
219	219	MCFG_LSI53C810_ADD( "scsi:lsi53c810", lsi53c810_intf)
220	220
221		MCFG_IDE_CONTROLLER_ADD( "ide", ide_devices, "hdd", NULL, false ) /* FIXME */
222		MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(bebox_state, bebox_ide_interrupt))
	221	MCFG_IDE_CONTROLLER_ADD( "ide", ata_devices, "hdd", NULL, false ) /* FIXME */
	222	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(bebox_state, bebox_ide_interrupt))
223	223
224	224	/* pci */
225	225	MCFG_PCI_BUS_ADD("pcibus", 0)

trunk/src/mess/machine/kc_d004.c

r23786	r23787
14	14	#define Z80_TAG         "disk"
15	15	#define Z80CTC_TAG      "z80ctc"
16	16	#define UPD765_TAG      "upd765"
17		#define IDE_TAG         "ide"
	17	#define ATA_TAG         "ata"
18	18
19	19	/***************************************************************************
20	20	IMPLEMENTATION
r23786	r23787
90	90	MCFG_CPU_MODIFY(Z80_TAG)
91	91	MCFG_CPU_IO_MAP(kc_d004_gide_io)
92	92
93		MCFG_IDE_CONTROLLER_ADD(IDE_TAG, ide_devices, "hdd", "hdd", false)
	93	MCFG_ATA_INTERFACE_ADD(ATA_TAG, ata_devices, "hdd", "hdd", false)
94	94	MACHINE_CONFIG_END
95	95
96	96
r23786	r23787
390	390
391	391	kc_d004_gide_device::kc_d004_gide_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
392	392	: kc_d004_device(mconfig, KC_D004, "D004 Floppy Disk + GIDE Interface", tag, owner, clock, "kc_d004gide", __FILE__),
393		m_ide(*this, IDE_TAG)
	393	m_ata(*this, ATA_TAG)
394	394	{
395	395	}
396	396
r23786	r23787
421	421	{
422	422	kc_d004_device::device_reset();
423	423
424		m_ide_data  = 0;
	424	m_ata_data  = 0;
425	425	m_lh        = 0;
426	426	}
427	427
r23786	r23787
457	457	{
458	458	if (ide_cs == 0 )
459	459	{
460		m_ide_data = m_ide->read_cs0(space, io_addr & 0x07, 0xffff);
	460	m_ata_data = m_ata->read_cs0(space, io_addr & 0x07, 0xffff);
461	461	}
462	462	else
463	463	{
464		m_ide_data = m_ide->read_cs1(space, io_addr & 0x07, 0xffff);
	464	m_ata_data = m_ata->read_cs1(space, io_addr & 0x07, 0xffff);
465	465	}
466	466	}
467	467
468		data = (m_ide_data >> data_shift) & 0xff;
	468	data = (m_ata_data >> data_shift) & 0xff;
469	469	}
470	470
471	471	m_lh = (io_addr == 0x08) ? !m_lh : ((io_addr > 0x08) ? 0 : m_lh);
r23786	r23787
500	500	if (io_addr == 0x08 && m_lh)
501	501	data_shift = 8;
502	502
503		m_ide_data = (data << data_shift) | (m_ide_data & (0xff00 >> data_shift));
	503	m_ata_data = (data << data_shift) | (m_ata_data & (0xff00 >> data_shift));
504	504
505	505	if (io_addr == 0x06 || io_addr == 0x07 || io_addr > 0x08 || (io_addr == 0x08 && m_lh))
506	506	{
507	507	if (ide_cs == 0)
508	508	{
509		m_ide->write_cs0(space, io_addr & 0x07, m_ide_data, 0xffff);
	509	m_ata->write_cs0(space, io_addr & 0x07, m_ata_data, 0xffff);
510	510	}
511	511	else
512	512	{
513		m_ide->write_cs1(space, io_addr & 0x07, m_ide_data, 0xffff);
	513	m_ata->write_cs1(space, io_addr & 0x07, m_ata_data, 0xffff);
514	514	}
515	515	}
516	516	}

trunk/src/mess/machine/kc_d004.h

r23786	r23787
8	8	#include "machine/z80ctc.h"
9	9	#include "cpu/z80/z80.h"
10	10	#include "machine/upd765.h"
11		#include "machine/idectrl.h"
	11	#include "machine/ataintf.h"
12	12	#include "formats/basicdsk.h"
13	13	#include "imagedev/harddriv.h"
14	14
r23786	r23787
100	100	DECLARE_WRITE8_MEMBER(gide_w);
101	101
102	102	private:
103		required_device<ide_controller_device> m_ide;
	103	required_device<ata_interface_device> m_ata;
104	104
105		UINT16              m_ide_data;
	105	UINT16              m_ata_data;
106	106	int                 m_lh;
107	107	};
108	108

trunk/src/mess/machine/isa_fdc.c

r23786	r23787
9	9	#include "machine/pc_fdc.h"
10	10	#include "imagedev/flopdrv.h"
11	11	#include "formats/pc_dsk.h"
12		#include "machine/idectrl.h"
	12	#include "machine/ataintf.h"
13	13	#include "formats/pc_dsk.h"
14	14	#include "formats/mfi_dsk.h"
15	15

trunk/src/mess/machine/a2zipdrive.c

r23786	r23787
19	19
20	20	#include "a2zipdrive.h"
21	21	#include "includes/apple2.h"
22		#include "machine/idectrl.h"
	22	#include "machine/ataintf.h"
23	23	#include "imagedev/harddriv.h"
24	24
25	25	//**************************************************************************
r23786	r23787
29	29	const device_type A2BUS_ZIPDRIVE = &device_creator<a2bus_zipdrive_device>;
30	30
31	31	#define ZIPDRIVE_ROM_REGION  "zipdrive_rom"
32		#define ZIPDRIVE_IDE_TAG     "zipdrive_ide"
	32	#define ZIPDRIVE_ATA_TAG     "zipdrive_ata"
33	33
34	34	static MACHINE_CONFIG_FRAGMENT( zipdrive )
35		MCFG_IDE_CONTROLLER_ADD(ZIPDRIVE_IDE_TAG, ide_devices, "hdd", "hdd", false)
	35	MCFG_ATA_INTERFACE_ADD(ZIPDRIVE_ATA_TAG, ata_devices, "hdd", "hdd", false)
36	36	MACHINE_CONFIG_END
37	37
38	38	ROM_START( zipdrive )
r23786	r23787
70	70	a2bus_zipdrivebase_device::a2bus_zipdrivebase_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) :
71	71	device_t(mconfig, type, name, tag, owner, clock, shortname, source),
72	72	device_a2bus_card_interface(mconfig, *this),
73		m_ide(*this, ZIPDRIVE_IDE_TAG)
	73	m_ata(*this, ZIPDRIVE_ATA_TAG)
74	74	{
75	75	}
76	76
r23786	r23787
116	116	case 5:
117	117	case 6:
118	118	case 7:
119		return m_ide->read_cs0(space, offset, 0xff);
	119	return m_ata->read_cs0(space, offset, 0xff);
120	120
121	121	case 8: // data port
122		m_lastdata = m_ide->read_cs0(space, offset, 0xffff);
	122	m_lastdata = m_ata->read_cs0(space, offset, 0xffff);
123	123	//          printf("%04x @ IDE data\n", m_lastdata);
124	124	return m_lastdata&0xff;
125	125
r23786	r23787
152	152	case 6:
153	153	case 7:
154	154	//          printf("%02x to IDE controller @ %x\n", data, offset);
155		m_ide->write_cs0(space, offset, data, 0xff);
	155	m_ata->write_cs0(space, offset, data, 0xff);
156	156	break;
157	157
158	158	case 8:
r23786	r23787
164	164	//          printf("%02x to IDE data hi\n", data);
165	165	m_lastdata &= 0x00ff;
166	166	m_lastdata |= (data << 8);
167		m_ide->write_cs0(space, offset, m_lastdata, 0xffff);
	167	m_ata->write_cs0(space, offset, m_lastdata, 0xffff);
168	168	break;
169	169
170	170	default:

trunk/src/mess/machine/a2zipdrive.h

r23786	r23787
13	13
14	14	#include "emu.h"
15	15	#include "machine/a2bus.h"
16		#include "machine/idectrl.h"
	16	#include "machine/ataintf.h"
17	17
18	18	//**************************************************************************
19	19	//  TYPE DEFINITIONS
r23786	r23787
41	41	virtual UINT8 read_cnxx(address_space &space, UINT8 offset);
42	42	virtual UINT8 read_c800(address_space &space, UINT16 offset);
43	43
44		required_device<ide_controller_device> m_ide;
	44	required_device<ata_interface_device> m_ata;
45	45
46	46	UINT8 *m_rom;
47	47

trunk/src/mess/machine/isa_ide.c

r23786	r23787
11	11
12	12	READ8_MEMBER(isa16_ide_device::ide16_alt_r )
13	13	{
14		return m_ide->read_cs1_pc(space, 6/2, 0xff);
	14	return m_ide->read_cs1(space, 6/2, 0xff);
15	15	}
16	16
17	17	WRITE8_MEMBER(isa16_ide_device::ide16_alt_w )
18	18	{
19		m_ide->write_cs1_pc(space, 6/2, data, 0xff);
	19	m_ide->write_cs1(space, 6/2, data, 0xff);
20	20	}
21	21
22	22	DEVICE_ADDRESS_MAP_START(map, 16, isa16_ide_device)
23		AM_RANGE(0x0, 0x7) AM_DEVREADWRITE("ide", ide_controller_device, read_cs0_pc, write_cs0_pc)
	23	AM_RANGE(0x0, 0x7) AM_DEVREADWRITE("ide", ide_controller_device, read_cs0, write_cs0)
24	24	ADDRESS_MAP_END
25	25
26	26	DEVICE_ADDRESS_MAP_START(alt_map, 8, isa16_ide_device)
r23786	r23787
40	40	}
41	41
42	42	static MACHINE_CONFIG_FRAGMENT( ide )
43		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", "hdd", false)
44		MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(isa16_ide_device, ide_interrupt))
	43	MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", "hdd", false)
	44	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(isa16_ide_device, ide_interrupt))
45	45	MACHINE_CONFIG_END
46	46
47	47	static INPUT_PORTS_START( ide )

trunk/src/mess/machine/ti99/tn_ide.c

r23786	r23787
27	27
28	28	#include "emu.h"
29	29	#include "peribox.h"
30		#include "machine/idectrl.h"
	30	#include "machine/ataintf.h"
31	31	#include "tn_ide.h"
32	32	#include "ti99_hd.h"
33	33
r23786	r23787
49	49	};
50	50
51	51	nouspikel_ide_interface_device::nouspikel_ide_interface_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
52		: ti_expansion_card_device(mconfig, TI99_IDE, "Nouspikel IDE interface card", tag, owner, clock, "ti99_ide", __FILE__)
	52	: ti_expansion_card_device(mconfig, TI99_IDE, "Nouspikel IDE interface card", tag, owner, clock, "ti99_ide", __FILE__),
	53	m_ata(*this, "ata")
53	54	{
54	55	}
55	56
r23786	r23787
71	72	reply |= 4;
72	73	if (m_sram_enable_dip)
73	74	reply |= 2;
74		if (!m_ide_irq)
	75	if (!m_ata_irq)
75	76	reply |= 1;
76	77	}
77	78	*value = reply;
r23786	r23787
107	108	m_cru_register &= ~(1 << bit);
108	109
109	110	if (bit == 6)
110		m_slot->set_inta((m_cru_register & cru_reg_int_en) && m_ide_irq);
	111	m_slot->set_inta((m_cru_register & cru_reg_int_en) && m_ata_irq);
111	112
112	113	if ((bit == 6) || (bit == 7))
113	114	if ((m_cru_register & cru_reg_int_en) && !(m_cru_register & cru_reg_reset))
114		m_ide->reset();
	115	m_ata->reset();
115	116	break;
116	117	}
117	118	}
r23786	r23787
151	152	case 2:     /* IDE registers set 1 (CS1Fx) */
152	153	if (m_tms9995_mode ? (!(addr & 1)) : (addr & 1))
153	154	{   /* first read triggers 16-bit read cycle */
154		m_input_latch = (! (addr & 0x10)) ? m_ide->read_cs0(space, (addr >> 1) & 0x7, 0xffff) : 0;
	155	m_input_latch = (! (addr & 0x10)) ? m_ata->read_cs0(space, (addr >> 1) & 0x7, 0xffff) : 0;
155	156	}
156	157
157	158	/* return latched input */
r23786	r23787
162	163	case 3:     /* IDE registers set 2 (CS3Fx) */
163	164	if (m_tms9995_mode ? (!(addr & 1)) : (addr & 1))
164	165	{   /* first read triggers 16-bit read cycle */
165		m_input_latch = (! (addr & 0x10)) ? m_ide->read_cs1(space, (addr >> 1) & 0x7, 0xffff) : 0;
	166	m_input_latch = (! (addr & 0x10)) ? m_ata->read_cs1(space, (addr >> 1) & 0x7, 0xffff) : 0;
166	167	}
167	168
168	169	/* return latched input */
r23786	r23787
232	233
233	234	if (m_tms9995_mode ? (addr & 1) : (!(addr & 1)))
234	235	{   /* second write triggers 16-bit write cycle */
235		m_ide->write_cs0(space, (addr >> 1) & 0x7, m_output_latch, 0xffff);
	236	m_ata->write_cs0(space, (addr >> 1) & 0x7, m_output_latch, 0xffff);
236	237	}
237	238	break;
238	239	case 3:     /* IDE registers set 2 (CS3Fx) */
r23786	r23787
250	251
251	252	if (m_tms9995_mode ? (addr & 1) : (!(addr & 1)))
252	253	{   /* second write triggers 16-bit write cycle */
253		m_ide->write_cs1(space, (addr >> 1) & 0x7, m_output_latch, 0xffff);
	254	m_ata->write_cs1(space, (addr >> 1) & 0x7, m_output_latch, 0xffff);
254	255	}
255	256	break;
256	257	}
r23786	r23787
279	280	*/
280	281	WRITE_LINE_MEMBER(nouspikel_ide_interface_device::ide_interrupt_callback)
281	282	{
282		m_ide_irq = state;
	283	m_ata_irq = state;
283	284	if (m_cru_register & cru_reg_int_en)
284	285	do_inta(state);
285	286	}
r23786	r23787
297	298	void nouspikel_ide_interface_device::device_start()
298	299	{
299	300	m_rtc = subdevice<rtc65271_device>("ide_rtc");
300		m_ide = subdevice<ide_controller_device>("ide");
301	301
302	302	m_ram = memregion(BUFFER_TAG)->base();
303	303	m_sram_enable_dip = false; // TODO: what is this?
r23786	r23787
334	334
335	335	MACHINE_CONFIG_FRAGMENT( tn_ide )
336	336	MCFG_RTC65271_ADD( "ide_rtc", ide_rtc_cfg )
337		MCFG_IDE_CONTROLLER_ADD( "ide", ide_devices, "hdd", NULL, false)  // see idectrl.c
338		MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(nouspikel_ide_interface_device, ide_interrupt_callback))
339		//  MCFG_IDE_CONTROLLER_REGIONS(":peribox:idehd0:drive", NULL)
	337	MCFG_ATA_INTERFACE_ADD( "ata", ata_devices, "hdd", NULL, false)
	338	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(nouspikel_ide_interface_device, ide_interrupt_callback))
340	339	MACHINE_CONFIG_END
341	340
342	341	ROM_START( tn_ide )

trunk/src/mess/machine/ti99/tn_ide.h

r23786	r23787
14	14
15	15	#include "emu.h"
16	16	#include "ti99defs.h"
17		#include "machine/idectrl.h"
	17	#include "machine/ataintf.h"
18	18	#include "machine/rtc65271.h"
19	19
20	20	extern const device_type TI99_IDE;
r23786	r23787
30	30	void    cruwrite(offs_t offset, UINT8 value);
31	31
32	32	void    do_inta(int state);
33		bool    m_ide_irq;
	33	bool    m_ata_irq;
34	34	int     m_cru_register;
35	35
36	36	DECLARE_WRITE_LINE_MEMBER(clock_interrupt_callback);
r23786	r23787
45	45
46	46	private:
47	47	rtc65271_device*    m_rtc;
48		ide_controller_device* m_ide;
	48	required_device<ata_interface_device> m_ata;
49	49
50	50	bool    m_clk_irq;
51	51	bool    m_sram_enable;

trunk/src/mess/machine/a2cffa.c

r23786	r23787
11	11
12	12	#include "a2cffa.h"
13	13	#include "includes/apple2.h"
14		#include "machine/idectrl.h"
	14	#include "machine/ataintf.h"
15	15	#include "imagedev/harddriv.h"
16	16
17	17
r23786	r23787
29	29	const device_type A2BUS_CFFA2_6502 = &device_creator<a2bus_cffa2_6502_device>;
30	30
31	31	#define CFFA2_ROM_REGION  "cffa2_rom"
32		#define CFFA2_IDE_TAG     "cffa2_ide"
	32	#define CFFA2_ATA_TAG     "cffa2_ata"
33	33
34	34	MACHINE_CONFIG_FRAGMENT( cffa2 )
35		MCFG_IDE_CONTROLLER_ADD(CFFA2_IDE_TAG, ide_devices, "hdd", "hdd", false)
	35	MCFG_ATA_INTERFACE_ADD(CFFA2_ATA_TAG, ata_devices, "hdd", "hdd", false)
36	36	MACHINE_CONFIG_END
37	37
38	38	ROM_START( cffa2 )
r23786	r23787
81	81	a2bus_cffa2000_device::a2bus_cffa2000_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) :
82	82	device_t(mconfig, type, name, tag, owner, clock, shortname, source),
83	83	device_a2bus_card_interface(mconfig, *this),
84		m_ide(*this, CFFA2_IDE_TAG)
	84	m_ata(*this, CFFA2_ATA_TAG)
85	85	{
86	86	}
87	87
r23786	r23787
143	143	break;
144	144
145	145	case 8:
146		m_lastdata = m_ide->read_cs0(space, offset-8, 0xffff);
	146	m_lastdata = m_ata->read_cs0(space, offset-8, 0xffff);
147	147	return m_lastdata & 0xff;
148	148
149	149	case 9:
r23786	r23787
153	153	case 0xd:
154	154	case 0xe:
155	155	case 0xf:
156		return m_ide->read_cs0(space, offset-8, 0xff);
	156	return m_ata->read_cs0(space, offset-8, 0xff);
157	157	}
158	158
159	159	return 0xff;
r23786	r23787
184	184	case 8:
185	185	m_lastdata &= 0xff00;
186	186	m_lastdata |= data;
187		m_ide->write_cs0(space, offset-8, m_lastdata, 0xffff);
	187	m_ata->write_cs0(space, offset-8, m_lastdata, 0xffff);
188	188	break;
189	189
190	190	case 9:
r23786	r23787
194	194	case 0xd:
195	195	case 0xe:
196	196	case 0xf:
197		m_ide->write_cs0(space, offset-8, data, 0xff);
	197	m_ata->write_cs0(space, offset-8, data, 0xff);
198	198	break;
199	199	}
200	200	}

trunk/src/mess/machine/southbridge.h

r23786	r23787
10	10	#include "machine/pic8259.h"
11	11	#include "machine/pit8253.h"
12	12
13		#include "machine/idectrl.h"
	13	#include "machine/ataintf.h"
14	14	#include "machine/at_keybc.h"
15	15
16	16	#include "imagedev/harddriv.h"

trunk/src/mess/machine/a2cffa.h

r23786	r23787
12	12
13	13	#include "emu.h"
14	14	#include "machine/a2bus.h"
15		#include "machine/idectrl.h"
	15	#include "machine/ataintf.h"
16	16
17	17	//**************************************************************************
18	18	//  TYPE DEFINITIONS
r23786	r23787
41	41	virtual UINT8 read_c800(address_space &space, UINT16 offset);
42	42	virtual void write_c800(address_space &space, UINT16 offset, UINT8 data);
43	43
44		required_device<ide_controller_device> m_ide;
	44	required_device<ata_interface_device> m_ata;
45	45
46	46	UINT8 *m_rom;
47	47	UINT8 m_eeprom[0x1000];

trunk/src/mess/machine/isa_ide8.c

r23786	r23787
55	55
56	56	static READ8_DEVICE_HANDLER( ide8_r )
57	57	{
58		ide_controller_device   *ide = (ide_controller_device *) device;
	58	ata_interface_device   *ide = (ata_interface_device *) device;
59	59	isa8_ide_device         *ide8_d = downcast<isa8_ide_device *>(device->owner());
60	60	UINT8   result  = 0;
61	61
r23786	r23787
80	80
81	81	static WRITE8_DEVICE_HANDLER( ide8_w )
82	82	{
83		ide_controller_device   *ide = (ide_controller_device *) device;
	83	ata_interface_device   *ide = (ata_interface_device *) device;
84	84	isa8_ide_device         *ide8_d = downcast<isa8_ide_device *>(device->owner());
85	85
86	86	//  logerror("%s ide8_w: offset=%d, data=%2X\n",device->machine().describe_context(),offset,data);
r23786	r23787
114	114	}
115	115
116	116	static MACHINE_CONFIG_FRAGMENT( ide8_config )
117		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", "hdd", false)
118		MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(isa8_ide_device, ide_interrupt))
	117	MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", "hdd", false)
	118	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(isa8_ide_device, ide_interrupt))
119	119	MACHINE_CONFIG_END
120	120
121	121	static INPUT_PORTS_START( ide8_port )

trunk/src/mess/machine/bebox.c

r23786	r23787
100	100	#include "machine/mc146818.h"
101	101	#include "machine/pic8259.h"
102	102	#include "machine/am9517a.h"
103		#include "machine/idectrl.h"
	103	#include "machine/ataintf.h"
104	104	#include "machine/pci.h"
105	105	#include "machine/intelfsh.h"
106	106	#include "machine/53c810.h"

trunk/src/mess/machine/adam_ide.c

r23786	r23787
25	25	//  MACROS/CONSTANTS
26	26	//**************************************************************************
27	27
28		#define IDE_TAG             "ide"
	28	#define ATA_TAG             "ata"
29	29	#define CENTRONICS_TAG      "centronics"
30	30
31	31
r23786	r23787
38	38
39	39
40	40	//-------------------------------------------------
41		//  ROM( adam_ide )
	41	//  ROM( adam_ata )
42	42	//-------------------------------------------------
43	43
44		ROM_START( adam_ide )
	44	ROM_START( adam_ata )
45	45	ROM_REGION( 0x1000, "rom", 0 )
46	46	ROM_LOAD( "exp.rom", 0x0000, 0x1000, NO_DUMP )
47	47	ROM_END
r23786	r23787
53	53
54	54	const rom_entry *powermate_ide_device::device_rom_region() const
55	55	{
56		return ROM_NAME( adam_ide );
	56	return ROM_NAME( adam_ata );
57	57	}
58	58
59	59
60	60	//-------------------------------------------------
61		//  MACHINE_CONFIG_FRAGMENT( adam_ide )
	61	//  MACHINE_CONFIG_FRAGMENT( adam_ata )
62	62	//-------------------------------------------------
63		static MACHINE_CONFIG_FRAGMENT( adam_ide )
64		MCFG_IDE_CONTROLLER_ADD(IDE_TAG, ide_devices, "hdd", NULL, false)
	63	static MACHINE_CONFIG_FRAGMENT( adam_ata )
	64	MCFG_ATA_INTERFACE_ADD(ATA_TAG, ata_devices, "hdd", NULL, false)
65	65	MCFG_CENTRONICS_PRINTER_ADD(CENTRONICS_TAG, standard_centronics)
66	66	MACHINE_CONFIG_END
67	67
r23786	r23787
73	73
74	74	machine_config_constructor powermate_ide_device::device_mconfig_additions() const
75	75	{
76		return MACHINE_CONFIG_NAME( adam_ide );
	76	return MACHINE_CONFIG_NAME( adam_ata );
77	77	}
78	78
79	79
r23786	r23787
87	87	//-------------------------------------------------
88	88
89	89	powermate_ide_device::powermate_ide_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
90		: device_t(mconfig, ADAM_IDE, "Powermate HP IDE", tag, owner, clock, "adam_ide", __FILE__),
	90	: device_t(mconfig, ADAM_IDE, "Powermate HP IDE", tag, owner, clock, "adam_ata", __FILE__),
91	91	device_adam_expansion_slot_card_interface(mconfig, *this),
92		m_ide(*this, IDE_TAG),
	92	m_ata(*this, ATA_TAG),
93	93	m_centronics(*this, CENTRONICS_TAG)
94	94	{
95	95	}
r23786	r23787
121	121	case 0x05:
122	122	case 0x06:
123	123	case 0x07:
124		data = m_ide->read_cs0(space, offset & 0x07, 0xff);
	124	data = m_ata->read_cs0(space, offset & 0x07, 0xff);
125	125	break;
126	126
127	127	case 0x40: // Printer status
r23786	r23787
142	142	break;
143	143
144	144	case 0x58:
145		m_ide_data = m_ide->read_cs0(space, 0, 0xffff);
	145	m_ata_data = m_ata->read_cs0(space, 0, 0xffff);
146	146
147		data = m_ide_data & 0xff;
	147	data = m_ata_data & 0xff;
148	148	break;
149	149
150	150	case 0x59:
151		data = m_ide_data >> 8;
	151	data = m_ata_data >> 8;
152	152	break;
153	153
154	154	case 0x5a:
155		data = m_ide->read_cs1(space, 6, 0xff);
	155	data = m_ata->read_cs1(space, 6, 0xff);
156	156	break;
157	157
158	158	case 0x5b: // Digital Input Register
r23786	r23787
181	181	case 0x05:
182	182	case 0x06:
183	183	case 0x07:
184		m_ide->write_cs0(space, offset & 0x07, data, 0xff);
	184	m_ata->write_cs0(space, offset & 0x07, data, 0xff);
185	185	break;
186	186
187	187	case 0x40:
r23786	r23787
192	192	break;
193	193
194	194	case 0x58:
195		m_ide_data |= data;
196		m_ide->write_cs0(space, 0, m_ide_data, 0xffff);
	195	m_ata_data |= data;
	196	m_ata->write_cs0(space, 0, m_ata_data, 0xffff);
197	197	break;
198	198
199	199	case 0x59:
200		m_ide_data = data << 8;
	200	m_ata_data = data << 8;
201	201	break;
202	202
203	203	case 0x5a: // Fixed Disk Control Register

trunk/src/mess/machine/c64_ide64.c

r23786	r23787
31	31	#define AT29C010A_TAG       "u3"
32	32	#define DS1302_TAG          "u4"
33	33	#define FT245R_TAG          "u21"
34		#define IDE_TAG             "ide"
	34	#define ATA_TAG             "ata"
35	35
36	36
37	37
r23786	r23787
49	49	MCFG_ATMEL_29C010_ADD(AT29C010A_TAG)
50	50	MCFG_DS1302_ADD(DS1302_TAG, XTAL_32_768kHz)
51	51
52		MCFG_IDE_CONTROLLER_ADD(IDE_TAG, ide_devices, "hdd", "hdd", false)
	52	MCFG_ATA_INTERFACE_ADD(ATA_TAG, ata_devices, "hdd", "hdd", false)
53	53	MACHINE_CONFIG_END
54	54
55	55
r23786	r23787
100	100	device_c64_expansion_card_interface(mconfig, *this),
101	101	m_flash_rom(*this, AT29C010A_TAG),
102	102	m_rtc(*this, DS1302_TAG),
103		m_ide(*this, IDE_TAG),
	103	m_ata(*this, ATA_TAG),
104	104	m_jp1(*this, "JP1")
105	105	{
106	106	}
r23786	r23787
117	117
118	118	// state saving
119	119	save_item(NAME(m_bank));
120		save_item(NAME(m_ide_data));
	120	save_item(NAME(m_ata_data));
121	121	save_item(NAME(m_enable));
122	122	}
123	123
r23786	r23787
181	181
182	182	if (io1_offset >= 0x20 && io1_offset < 0x28)
183	183	{
184		m_ide_data = m_ide->read_cs0(space, offset & 0x07, 0xffff);
	184	m_ata_data = m_ata->read_cs0(space, offset & 0x07, 0xffff);
185	185
186		data = m_ide_data & 0xff;
	186	data = m_ata_data & 0xff;
187	187	}
188	188	else if (io1_offset >= 0x28 && io1_offset < 0x30)
189	189	{
190		m_ide_data = m_ide->read_cs1(space, offset & 0x07, 0xffff);
	190	m_ata_data = m_ata->read_cs1(space, offset & 0x07, 0xffff);
191	191
192		data = m_ide_data & 0xff;
	192	data = m_ata_data & 0xff;
193	193	}
194	194	else if (io1_offset == 0x31)
195	195	{
196		data = m_ide_data >> 8;
	196	data = m_ata_data >> 8;
197	197	}
198	198	else if (io1_offset == 0x32)
199	199	{
r23786	r23787
282	282
283	283	if (io1_offset >= 0x20 && io1_offset < 0x28)
284	284	{
285		m_ide_data = (m_ide_data & 0xff00) | data;
	285	m_ata_data = (m_ata_data & 0xff00) | data;
286	286
287		m_ide->write_cs0(space, offset & 0x07, m_ide_data, 0xffff);
	287	m_ata->write_cs0(space, offset & 0x07, m_ata_data, 0xffff);
288	288	}
289	289	else if (io1_offset >= 0x28 && io1_offset < 0x30)
290	290	{
291		m_ide_data = (m_ide_data & 0xff00) | data;
	291	m_ata_data = (m_ata_data & 0xff00) | data;
292	292
293		m_ide->write_cs1(space, offset & 0x07, m_ide_data, 0xffff);
	293	m_ata->write_cs1(space, offset & 0x07, m_ata_data, 0xffff);
294	294	}
295	295	else if (io1_offset == 0x31)
296	296	{
297		m_ide_data = (data << 8) | (m_ide_data & 0xff);
	297	m_ata_data = (data << 8) | (m_ata_data & 0xff);
298	298	}
299	299	else if (io1_offset == 0x5f)
300	300	{

trunk/src/mess/machine/adam_ide.h

r23786	r23787
15	15	#include "emu.h"
16	16	#include "machine/adamexp.h"
17	17	#include "machine/ctronics.h"
18		#include "machine/idectrl.h"
	18	#include "machine/ataintf.h"
19	19
20	20
21	21
r23786	r23787
45	45	virtual void adam_bd_w(address_space &space, offs_t offset, UINT8 data, int bmreq, int biorq, int aux_rom_cs, int cas1, int cas2);
46	46
47	47	private:
48		required_device<ide_controller_device> m_ide;
	48	required_device<ata_interface_device> m_ata;
49	49	required_device<centronics_device> m_centronics;
50	50
51		UINT16 m_ide_data;
	51	UINT16 m_ata_data;
52	52	};
53	53
54	54

trunk/src/mess/machine/c64_ide64.h

r23786	r23787
16	16	#include "emu.h"
17	17	#include "machine/c64exp.h"
18	18	#include "machine/ds1302.h"
19		#include "machine/idectrl.h"
	19	#include "machine/ataintf.h"
20	20	#include "machine/intelfsh.h"
21	21	#include "imagedev/harddriv.h"
22	22
r23786	r23787
53	53	private:
54	54	required_device<atmel_29c010_device> m_flash_rom;
55	55	required_device<ds1302_device> m_rtc;
56		required_device<ide_controller_device> m_ide;
	56	required_device<ata_interface_device> m_ata;
57	57	required_ioport m_jp1;
58	58
59	59	UINT8 m_bank;
60		UINT16 m_ide_data;
	60	UINT16 m_ata_data;
61	61	int m_wp;
62	62	int m_enable;
63	63	};

trunk/src/mess/machine/a2vulcan.c

r23786	r23787
53	53
54	54	#include "a2vulcan.h"
55	55	#include "includes/apple2.h"
56		#include "machine/idectrl.h"
	56	#include "machine/ataintf.h"
57	57	#include "imagedev/harddriv.h"
58	58
59	59	//**************************************************************************
r23786	r23787
63	63	const device_type A2BUS_VULCAN = &device_creator<a2bus_vulcan_device>;
64	64
65	65	#define VULCAN_ROM_REGION  "vulcan_rom"
66		#define VULCAN_IDE_TAG     "vulcan_ide"
	66	#define VULCAN_ATA_TAG     "vulcan_ata"
67	67
68	68	static MACHINE_CONFIG_FRAGMENT( vulcan )
69		MCFG_IDE_CONTROLLER_ADD(VULCAN_IDE_TAG, ide_devices, "hdd", "hdd", false)
	69	MCFG_ATA_INTERFACE_ADD(VULCAN_ATA_TAG, ata_devices, "hdd", "hdd", false)
70	70	MACHINE_CONFIG_END
71	71
72	72	ROM_START( vulcan )
r23786	r23787
104	104	a2bus_vulcanbase_device::a2bus_vulcanbase_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) :
105	105	device_t(mconfig, type, name, tag, owner, clock, shortname, source),
106	106	device_a2bus_card_interface(mconfig, *this),
107		m_ide(*this, VULCAN_IDE_TAG)
	107	m_ata(*this, VULCAN_ATA_TAG)
108	108	{
109	109	}
110	110
r23786	r23787
151	151	switch (offset)
152	152	{
153	153	case 0:
154		m_lastdata = m_ide->read_cs0(space, offset, 0xffff);
	154	m_lastdata = m_ata->read_cs0(space, offset, 0xffff);
155	155	//          printf("IDE: read %04x\n", m_lastdata);
156	156	m_last_read_was_0 = true;
157	157	return m_lastdata&0xff;
r23786	r23787
164	164	}
165	165	else
166	166	{
167		return m_ide->read_cs0(space, offset, 0xff);
	167	return m_ata->read_cs0(space, offset, 0xff);
168	168	}
169	169	break;
170	170
r23786	r23787
174	174	case 5:
175	175	case 6:
176	176	case 7:
177		return m_ide->read_cs0(space, offset, 0xff);
	177	return m_ata->read_cs0(space, offset, 0xff);
178	178
179	179	default:
180	180	//          printf("Read @ C0n%x\n", offset);
r23786	r23787
206	206	m_lastdata &= 0x00ff;
207	207	m_lastdata |= (data << 8);
208	208	//              printf("IDE: write %04x\n", m_lastdata);
209		m_ide->write_cs0(space, offset, m_lastdata, 0xffff);
	209	m_ata->write_cs0(space, offset, m_lastdata, 0xffff);
210	210	}
211	211	else
212	212	{
213		m_ide->write_cs0(space, offset, data, 0xff);
	213	m_ata->write_cs0(space, offset, data, 0xff);
214	214	}
215	215	break;
216	216
r23786	r23787
221	221	case 6:
222	222	case 7:
223	223	//          printf("%02x to IDE controller @ %x\n", data, offset);
224		m_ide->write_cs0(space, offset, data, 0xff);
	224	m_ata->write_cs0(space, offset, data, 0xff);
225	225	break;
226	226
227	227	case 9: // ROM bank

trunk/src/mess/machine/a2vulcan.h

r23786	r23787
11	11
12	12	#include "emu.h"
13	13	#include "machine/a2bus.h"
14		#include "machine/idectrl.h"
	14	#include "machine/ataintf.h"
15	15
16	16	//**************************************************************************
17	17	//  TYPE DEFINITIONS
r23786	r23787
40	40	virtual UINT8 read_c800(address_space &space, UINT16 offset);
41	41	virtual void write_c800(address_space &space, UINT16 offset, UINT8 data);
42	42
43		required_device<ide_controller_device> m_ide;
	43	required_device<ata_interface_device> m_ata;
44	44
45	45	UINT8 *m_rom;
46	46	UINT8 m_ram[8*1024];

trunk/src/mame/drivers/pinball2k.c

r23786	r23787
579	579	MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
580	580	MCFG_PCI_BUS_LEGACY_DEVICE(18, NULL, cx5510_pci_r, cx5510_pci_w)
581	581
582		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
583		MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
	582	MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	583	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
584	584
585	585	MCFG_RAMDAC_ADD("ramdac", ramdac_intf, ramdac_map)
586	586

trunk/src/mame/drivers/midvunit.c

r23786	r23787
29	29	#include "cpu/tms32031/tms32031.h"
30	30	#include "cpu/adsp2100/adsp2100.h"
31	31	#include "audio/dcs.h"
32		#include "machine/idectrl.h"
	32	#include "machine/ataintf.h"
33	33	#include "machine/midwayic.h"
34	34	#include "machine/nvram.h"
35	35	#include "includes/midvunit.h"
r23786	r23787
80	80	m_timer[0] = machine().device<timer_device>("timer0");
81	81	m_timer[1] = machine().device<timer_device>("timer1");
82	82
83		machine().device("ide")->reset();
	83	machine().device("ata")->reset();
84	84	}
85	85
86	86
r23786	r23787
508	508	AM_RANGE(0x990000, 0x99000f) AM_READWRITE_LEGACY(midway_ioasic_r, midway_ioasic_w)
509	509	AM_RANGE(0x994000, 0x994000) AM_WRITE(midvunit_control_w)
510	510	AM_RANGE(0x995020, 0x995020) AM_WRITE(midvunit_cmos_protect_w)
511		AM_RANGE(0x9a0000, 0x9a0007) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0x0000ffff)
	511	AM_RANGE(0x9a0000, 0x9a0007) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs0, write_cs0, 0x0000ffff)
512	512	AM_RANGE(0x9c0000, 0x9c7fff) AM_RAM_WRITE(midvunit_paletteram_w) AM_SHARE("paletteram")
513	513	AM_RANGE(0x9d0000, 0x9d000f) AM_READWRITE(midvplus_misc_r, midvplus_misc_w) AM_SHARE("midvplus_misc")
514	514	AM_RANGE(0xa00000, 0xbfffff) AM_READWRITE(midvunit_textureram_r, midvunit_textureram_w) AM_SHARE("textureram")
r23786	r23787
1042	1042	MCFG_DEVICE_REMOVE("nvram")
1043	1043	MCFG_NVRAM_HANDLER(midway_serial_pic2)
1044	1044
1045		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
	1045	MCFG_ATA_INTERFACE_ADD("ata", ata_devices, "hdd", NULL, true)
1046	1046
1047	1047	/* sound hardware */
1048	1048	MCFG_FRAGMENT_ADD(dcs2_audio_2115)
r23786	r23787
1665	1665	ROM_REGION32_LE( 0x1000000, "user1", 0 )
1666	1666	ROM_LOAD( "u41.rom", 0x000000, 0x20000, CRC(398c54cc) SHA1(6c4b5d6ec5c844dcbf181f9d86a9196a088ed2db) )
1667	1667
1668		DISK_REGION( "ide:0:hdd" )
	1668	DISK_REGION( "ata:0:hdd:image" )
1669	1669	DISK_IMAGE( "wargods_10-09-1996", 0, SHA1(7585bc65b1038589cb59d3e7c56e08ca9d7015b8) )
1670	1670	ROM_END
1671	1671
r23786	r23787
1676	1676	ROM_REGION32_LE( 0x1000000, "user1", 0 )
1677	1677	ROM_LOAD( "u41.rom", 0x000000, 0x20000, CRC(398c54cc) SHA1(6c4b5d6ec5c844dcbf181f9d86a9196a088ed2db) )
1678	1678
1679		DISK_REGION( "ide:0:hdd" )
	1679	DISK_REGION( "ata:0:hdd:image" )
1680	1680	DISK_IMAGE( "wargods_08-15-1996", 0, SHA1(5dee00be40c315fbb1d6e3994dae8e498ab87fb2) )
1681	1681	ROM_END
1682	1682
r23786	r23787
1687	1687	ROM_REGION32_LE( 0x1000000, "user1", 0 )
1688	1688	ROM_LOAD( "u41.rom", 0x000000, 0x20000, CRC(398c54cc) SHA1(6c4b5d6ec5c844dcbf181f9d86a9196a088ed2db) )
1689	1689
1690		DISK_REGION( "ide:0:hdd" )
	1690	DISK_REGION( "ata:0:hdd:image" )
1691	1691	DISK_IMAGE( "wargods_12-11-1995", 0, SHA1(141063f95867fdcc4b15c844e510696604a70c6a) )
1692	1692	ROM_END
1693	1693

trunk/src/mame/drivers/mediagx.c

r23786	r23787
750	750	AM_RANGE(0x0020, 0x0023) AM_READWRITE8(io20_r, io20_w, 0xffff0000)
751	751	AM_IMPORT_FROM(pcat32_io_common)
752	752	AM_RANGE(0x00e8, 0x00eb) AM_NOP     // I/O delay port
753		AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
	753	AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
754	754	AM_RANGE(0x0378, 0x037b) AM_READWRITE(parallel_port_r, parallel_port_w)
755		AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
	755	AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
756	756	AM_RANGE(0x0400, 0x04ff) AM_READWRITE(ad1847_r, ad1847_w)
757	757	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
758	758	ADDRESS_MAP_END
r23786	r23787
858	858	m_dmadac[0] = machine().device<dmadac_sound_device>("dac1");
859	859	m_dmadac[1] = machine().device<dmadac_sound_device>("dac2");
860	860	dmadac_enable(&m_dmadac[0], 2, 1);
861		m_ide->reset();
862	861	}
863	862
864	863	static ADDRESS_MAP_START( ramdac_map, AS_0, 8, mediagx_state )
r23786	r23787
882	881	MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
883	882	MCFG_PCI_BUS_LEGACY_DEVICE(18, NULL, cx5510_pci_r, cx5510_pci_w)
884	883
885		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
886		MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
	884	MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	885	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
887	886
888	887	MCFG_TIMER_DRIVER_ADD("sound_timer", mediagx_state, sound_timer_callback)
889	888
r23786	r23787
1014	1013	ROM_REGION(0x08100, "gfx1", 0)
1015	1014	ROM_LOAD("cga.chr",     0x00000, 0x01000, CRC(42009069) SHA1(ed08559ce2d7f97f68b9f540bddad5b6295294dd))
1016	1015
1017		DISK_REGION( "ide:0:hdd" )
	1016	DISK_REGION( "ide:0:hdd:image" )
1018	1017	DISK_IMAGE( "a51site4-2_01", 0, SHA1(48496666d1613700ae9274f9a5361ea5bbaebea0) ) /* Happ replacement drive "A-22509", sticker on drive shows REV 2.01 and Test Mode screen shows the date September 7, 1998 */
1019	1018	ROM_END
1020	1019
r23786	r23787
1028	1027	ROM_REGION(0x08100, "gfx1", 0)
1029	1028	ROM_LOAD("cga.chr",     0x00000, 0x01000, CRC(42009069) SHA1(ed08559ce2d7f97f68b9f540bddad5b6295294dd))
1030	1029
1031		DISK_REGION( "ide:0:hdd" )
	1030	DISK_REGION( "ide:0:hdd:image" )
1032	1031	DISK_IMAGE( "a51site4-2_0", 0, SHA1(4de421e4d1708ecbdfb50730000814a1ea36a044) ) /* Stock drive, sticker on drive shows REV 2.0 and Test Mode screen shows the date September 11, 1998 */
1033	1032	ROM_END
1034	1033

trunk/src/mame/drivers/viper.c

r23786	r23787
284	284	#include "emu.h"
285	285	#include "cpu/powerpc/ppc.h"
286	286	#include "machine/pci.h"
287		#include "machine/idectrl.h"
	287	#include "machine/ataintf.h"
288	288	#include "machine/timekpr.h"
289	289	#include "video/voodoo.h"
290	290
r23786	r23787
310	310	viper_state(const machine_config &mconfig, device_type type, const char *tag)
311	311	: driver_device(mconfig, type, tag),
312	312	m_maincpu(*this, "maincpu"),
313		m_ide(*this, "ide")
	313	m_ata(*this, "ata")
314	314	{
315	315	}
316	316
r23786	r23787
363	363	int ds2430_insert_cmd_bit(int bit);
364	364	void DS2430_w(int bit);
365	365	required_device<cpu_device> m_maincpu;
366		required_device<ide_controller_device> m_ide;
	366	required_device<ata_interface_device> m_ata;
367	367	};
368	368
369	369	UINT32 viper_state::screen_update_viper(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
r23786	r23787
1266	1266	{
1267	1267	case 0x8:   // Duplicate Even RD Data
1268	1268	{
1269		r |= m_ide->read_cs0(space, 0, mem_mask >> 16) << 16;
	1269	r |= m_ata->read_cs0(space, 0, mem_mask >> 16) << 16;
1270	1270	break;
1271	1271	}
1272	1272
r23786	r23787
1287	1287	{
1288	1288	case 0x8:   // Duplicate Even RD Data
1289	1289	{
1290		m_ide->write_cs0(space, 0, data >> 16, mem_mask >> 16);
	1290	m_ata->write_cs0(space, 0, data >> 16, mem_mask >> 16);
1291	1291	break;
1292	1292	}
1293	1293
r23786	r23787
1318	1318	case 0x6:   // Select Card/Head
1319	1319	case 0x7:   // Status
1320	1320	{
1321		r |= m_ide->read_cs0(space, offset & 7, mem_mask >> 16) << 16;
	1321	r |= m_ata->read_cs0(space, offset & 7, mem_mask >> 16) << 16;
1322	1322	break;
1323	1323	}
1324	1324
r23786	r23787
1327	1327
1328	1328	case 0xd:   // Duplicate Error
1329	1329	{
1330		r |= m_ide->read_cs0(space, 1, mem_mask >> 16) << 16;
	1330	r |= m_ata->read_cs0(space, 1, mem_mask >> 16) << 16;
1331	1331	break;
1332	1332	}
1333	1333	case 0xe:   // Alt Status
1334	1334	case 0xf:   // Drive Address
1335	1335	{
1336		r |= m_ide->read_cs1(space, offset & 7, mem_mask >> 16) << 16;
	1336	r |= m_ata->read_cs1(space, offset & 7, mem_mask >> 16) << 16;
1337	1337	break;
1338	1338	}
1339	1339
r23786	r23787
1383	1383	case 0x6:   // Select Card/Head
1384	1384	case 0x7:   // Command
1385	1385	{
1386		m_ide->write_cs0(space, offset & 7, data >> 16, mem_mask >> 16);
	1386	m_ata->write_cs0(space, offset & 7, data >> 16, mem_mask >> 16);
1387	1387	break;
1388	1388	}
1389	1389
r23786	r23787
1392	1392
1393	1393	case 0xd:   // Duplicate Features
1394	1394	{
1395		m_ide->write_cs0(space, 1, data >> 16, mem_mask >> 16);
	1395	m_ata->write_cs0(space, 1, data >> 16, mem_mask >> 16);
1396	1396	break;
1397	1397	}
1398	1398	case 0xe:   // Device Ctl
1399	1399	case 0xf:   // Reserved
1400	1400	{
1401		m_ide->write_cs1(space, offset & 7, data >> 16, mem_mask >> 16);
	1401	m_ata->write_cs1(space, offset & 7, data >> 16, mem_mask >> 16);
1402	1402	break;
1403	1403	}
1404	1404
r23786	r23787
1419	1419	m_cf_card_ide = 1;
1420	1420
1421	1421	// soft reset
1422		m_ide->write_cs1(space, 6, 0x04, 0xff);
	1422	m_ata->write_cs1(space, 6, 0x04, 0xff);
1423	1423	}
1424	1424	break;
1425	1425	}
r23786	r23787
1454	1454	switch(offset & 0x80)
1455	1455	{
1456	1456	case 0x00:
1457		r |= m_ide->read_cs0(space, reg, mem_mask >> 16) << 16;
	1457	r |= m_ata->read_cs0(space, reg, mem_mask >> 16) << 16;
1458	1458	break;
1459	1459	case 0x80:
1460		r |= m_ide->read_cs1(space, reg, mem_mask >> 16) << 16;
	1460	r |= m_ata->read_cs1(space, reg, mem_mask >> 16) << 16;
1461	1461	break;
1462	1462	}
1463	1463	}
r23786	r23787
1474	1474	switch(offset & 0x80)
1475	1475	{
1476	1476	case 0x00:
1477		m_ide->write_cs0(space, reg, data >> 16, mem_mask >> 16);
	1477	m_ata->write_cs0(space, reg, data >> 16, mem_mask >> 16);
1478	1478	break;
1479	1479	case 0x80:
1480		m_ide->write_cs1(space, reg, data >> 16, mem_mask >> 16);
	1480	m_ata->write_cs1(space, reg, data >> 16, mem_mask >> 16);
1481	1481	break;
1482	1482	}
1483	1483	}
r23786	r23787
2021	2021
2022	2022	void viper_state::machine_reset()
2023	2023	{
2024		m_ide->reset();
2025	2024	mpc8240_epic_reset();
2026	2025
2027		UINT8 *identify_device = m_ide->identify_device_buffer(0);
	2026	UINT8 *identify_device = m_ata->identify_device_buffer(0);
2028	2027
2029	2028	// Viper expects these settings or the BIOS fails
2030	2029	identify_device[51*2+0] = 0;           /* 51: PIO data transfer cycle timing mode */
r23786	r23787
2057	2056	MCFG_PCI_BUS_LEGACY_DEVICE(0, "mpc8240", mpc8240_pci_r, mpc8240_pci_w)
2058	2057	MCFG_PCI_BUS_LEGACY_DEVICE(12, "voodoo", voodoo3_pci_r, voodoo3_pci_w)
2059	2058
2060		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
	2059	MCFG_ATA_INTERFACE_ADD("ata", ata_devices, "hdd", NULL, true)
2061	2060
2062	2061	MCFG_3DFX_VOODOO_3_ADD("voodoo", STD_VOODOO_3_CLOCK, voodoo_intf)
2063	2062
r23786	r23787
2126	2125
2127	2126	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2128	2127
2129		DISK_REGION( "ide:0:hdd" )
	2128	DISK_REGION( "ata:0:hdd:image" )
2130	2129	DISK_IMAGE( "ppp2nd", 0, SHA1(b8b90483d515c83eac05ffa617af19612ea990b0))
2131	2130	ROM_END
2132	2131
r23786	r23787
2140	2139	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2141	2140	ROM_LOAD("a45jaa_nvram.u39", 0x00000, 0x2000, CRC(c24e29fc) SHA1(efb6ecaf25cbdf9d8dfcafa85e38a195fa5ff6c4))
2142	2141
2143		DISK_REGION( "ide:0:hdd" )
	2142	DISK_REGION( "ata:0:hdd:image" )
2144	2143	DISK_IMAGE( "a45a02", 0, SHA1(9af2481f53de705ae48fad08d8dd26553667c2d0) )
2145	2144	ROM_END
2146	2145
r23786	r23787
2153	2152	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2154	2153	ROM_LOAD("nvram.u39", 0x00000, 0x2000, NO_DUMP )
2155	2154
2156		DISK_REGION( "ide:0:hdd" )
	2155	DISK_REGION( "ata:0:hdd:image" )
2157	2156	DISK_IMAGE( "922d02", 0, SHA1(01f35e324c9e8567da0f51b3e68fff1562c32116) )
2158	2157	ROM_END
2159	2158
r23786	r23787
2166	2165	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2167	2166	ROM_LOAD("nvram.u39", 0x00000, 0x2000, NO_DUMP )
2168	2167
2169		DISK_REGION( "ide:0:hdd" )
	2168	DISK_REGION( "ata:0:hdd:image" )
2170	2169	DISK_IMAGE( "922b02", 0, SHA1(4d288b5dcfab3678af662783e7083a358eee99ce) )
2171	2170	ROM_END
2172	2171
r23786	r23787
2180	2179	ROM_LOAD("nvram.u39", 0x00000, 0x2000, CRC(d0604e84) SHA1(18d1183f1331af3e655a56692eb7ab877b4bc239)) //old dump, probably has non-default settings.
2181	2180	ROM_LOAD("941jab_nvram.u39", 0x00000, 0x2000, CRC(6c4a852f) SHA1(2753dda42cdd81af22dc6780678f1ddeb3c62013))
2182	2181
2183		DISK_REGION( "ide:0:hdd" )
	2182	DISK_REGION( "ata:0:hdd:image" )
2184	2183	DISK_IMAGE( "941b02", 0,  SHA1(943bc9b1ea7273a8382b94c8a75010dfe296df14) )
2185	2184	ROM_END
2186	2185
r23786	r23787
2190	2189	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2191	2190	ROM_LOAD("941eaa_nvram.u39", 0x00000, 0x2000, CRC(5ee7004d) SHA1(92e0ce01049308f459985d466fbfcfac82f34a47))
2192	2191
2193		DISK_REGION( "ide:0:hdd" )
	2192	DISK_REGION( "ata:0:hdd:image" )
2194	2193	DISK_IMAGE( "941a02", 0,  NO_DUMP )
2195	2194	ROM_END
2196	2195
r23786	r23787
2203	2202	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2204	2203	ROM_LOAD("b41ebc_nvram.u39", 0x00000, 0x2000, CRC(55d1681d) SHA1(26868cf0d14f23f06b81f2df0b4186924439bb43))
2205	2204
2206		DISK_REGION( "ide:0:hdd" )
	2205	DISK_REGION( "ata:0:hdd:image" )
2207	2206	DISK_IMAGE( "b41c02", 0, SHA1(fb6b0b43a6f818041d644bcd711f6a727348d3aa) )
2208	2207	ROM_END
2209	2208
r23786	r23787
2217	2216	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2218	2217	ROM_LOAD("b33uaa_nvram.u39", 0x00000, 0x1ff8, BAD_DUMP CRC(0f0ba988) SHA1(5618c03b21fc2ba14b2e159cee3aab7f53c2c34d)) //data looks plain bad (compared to the other games)
2219	2218
2220		DISK_REGION( "ide:0:hdd" )
	2219	DISK_REGION( "ata:0:hdd:image" )
2221	2220	DISK_IMAGE( "b33a02", 0, SHA1(819d8fac5d2411542c1b989105cffe38a5545fc2) )
2222	2221	ROM_END
2223	2222
r23786	r23787
2230	2229	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2231	2230	ROM_LOAD("a29aaa_nvram.u39", 0x000000, 0x2000, CRC(14b9fe68) SHA1(3c59e6df1bb46bc1835c13fd182b1bb092c08759)) //supposed to be aab version?
2232	2231
2233		DISK_REGION( "ide:0:hdd" )
	2232	DISK_REGION( "ata:0:hdd:image" )
2234	2233	DISK_IMAGE( "a29b02", 0, SHA1(f0c04310caf2cca804fde20805eb30a44c5a6796) ) //missing bootloader
2235	2234	ROM_END
2236	2235
r23786	r23787
2243	2242	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2244	2243	ROM_LOAD("a29jaa_nvram.u39", 0x000000, 0x2000, CRC(2f7cdf27) SHA1(0b69d8728be12909e235268268a312982f81d46a))
2245	2244
2246		DISK_REGION( "ide:0:hdd" )
	2245	DISK_REGION( "ata:0:hdd:image" )
2247	2246	DISK_IMAGE( "a29a02", 0, SHA1(00afad399737652b3e17257c70a19f62e37f3c97) )
2248	2247	ROM_END
2249	2248
r23786	r23787
2256	2255	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2257	2256	ROM_LOAD("a00uad_nvram.u39", 0x000000, 0x2000, CRC(cca056ca) SHA1(de1a00d84c1311d48bbe6d24f5b36e22ecf5e85a))
2258	2257
2259		DISK_REGION( "ide:0:hdd" )
	2258	DISK_REGION( "ata:0:hdd:image" )
2260	2259	DISK_IMAGE( "a00uad02", 0, SHA1(6acb8dc41920e7025b87034a3a62b185ef0109d9) )
2261	2260	ROM_END
2262	2261
r23786	r23787
2269	2268	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2270	2269	ROM_LOAD("a00uac_nvram.u39", 0x000000, 0x2000,  NO_DUMP )
2271	2270
2272		DISK_REGION( "ide:0:hdd" )
	2271	DISK_REGION( "ata:0:hdd:image" )
2273	2272	DISK_IMAGE( "a00uac02", 0, SHA1(b268789416dbf8886118a634b911f0ee254970de) )
2274	2273	ROM_END
2275	2274
r23786	r23787
2282	2281	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2283	2282	ROM_LOAD("a00kac_nvram.u39", 0x000000, 0x2000,  CRC(8ddc921c) SHA1(901538da237679fc74966a301278b36d1335671f) )
2284	2283
2285		DISK_REGION( "ide:0:hdd" )
	2284	DISK_REGION( "ata:0:hdd:image" )
2286	2285	DISK_IMAGE( "a00kac02", 0, SHA1(b268789416dbf8886118a634b911f0ee254970de) )
2287	2286	ROM_END
2288	2287
r23786	r23787
2295	2294	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2296	2295	ROM_LOAD("a00eaa_nvram.u39", 0x000000, 0x2000,  CRC(4f3497b6) SHA1(3045c54f98dff92cdf3a1fc0cd4c76ba82d632d7) )
2297	2296
2298		DISK_REGION( "ide:0:hdd" )
	2297	DISK_REGION( "ata:0:hdd:image" )
2299	2298	DISK_IMAGE( "a00eaa02", 0, SHA1(81565a2dce2e2b0a7927078a784354948af1f87c) )
2300	2299	ROM_END
2301	2300
r23786	r23787
2308	2307	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2309	2308	ROM_LOAD("a00jaa_nvram.u39", 0x000000, 0x2000, CRC(9ecf70dc) SHA1(4769a99b0cc28563e219860b8d480f32d1e21f60))
2310	2309
2311		DISK_REGION( "ide:0:hdd" )
	2310	DISK_REGION( "ata:0:hdd:image" )
2312	2311	DISK_IMAGE( "a00jac02", 0, SHA1(d962d3a8ea84c380767d0fe336296911c289c224) )
2313	2312	ROM_END
2314	2313
r23786	r23787
2321	2320	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2322	2321	ROM_LOAD("nvram.u39", 0x000000, 0x2000, NO_DUMP )
2323	2322
2324		DISK_REGION( "ide:0:hdd" )
	2323	DISK_REGION( "ata:0:hdd:image" )
2325	2324	DISK_IMAGE( "b11a02", 0, SHA1(57665664321b78c1913d01f0d2c0b8d3efd42e04) )
2326	2325	ROM_END
2327	2326
r23786	r23787
2334	2333	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2335	2334	ROM_LOAD("nvram.u39", 0x000000, 0x2000, NO_DUMP )
2336	2335
2337		DISK_REGION( "ide:0:hdd" )
	2336	DISK_REGION( "ata:0:hdd:image" )
2338	2337	DISK_IMAGE( "c00jab", 0, BAD_DUMP SHA1(3763aaded9b45388a664edd84a3f7f8ff4101be4) )
2339	2338	ROM_END
2340	2339
r23786	r23787
2347	2346	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2348	2347	ROM_LOAD("a13uaa_nvram.u39", 0x000000, 0x2000, CRC(7b0e1ac8) SHA1(1ea549964539e27f87370e9986bfa44eeed037cd))
2349	2348
2350		DISK_REGION( "ide:0:hdd" )
	2349	DISK_REGION( "ata:0:hdd:image" )
2351	2350	DISK_IMAGE( "a13c02", 0, SHA1(d740784fa51a3f43695ea95e23f92ef05f43284a) )
2352	2351	ROM_END
2353	2352
r23786	r23787
2362	2361	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2363	2362	ROM_LOAD("nvram.u39", 0x000000, 0x2000, CRC(2f325c55) SHA1(0bc44f40f981a815c8ce64eae95ae55db510c565))
2364	2363
2365		DISK_REGION( "ide:0:hdd" )
	2364	DISK_REGION( "ata:0:hdd:image" )
2366	2365	DISK_IMAGE( "a13b02", 0, SHA1(c25a61b76d365794c2da4a9e7de88a5519e944ec) )
2367	2366	ROM_END
2368	2367
r23786	r23787
2376	2375	ROM_LOAD("a41ebb_nvram.u39", 0x00000, 0x2000, CRC(22f59ac0) SHA1(e14ea2ba95b72edf0a3331ab82c192760bfdbce3))
2377	2376	//  a41eba_nvram == a41ebb_nvram
2378	2377
2379		DISK_REGION( "ide:0:hdd" )
	2378	DISK_REGION( "ata:0:hdd:image" )
2380	2379	DISK_IMAGE( "a41b02", 0, SHA1(0426f4bb9001cf457f44e2c22e3d7575b8049aa3) )
2381	2380	ROM_END
2382	2381
r23786	r23787
2389	2388	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2390	2389	ROM_LOAD("a41aaa_nvram.u39", 0x00000, 0x2000, CRC(d5de9b8e) SHA1(768bcd46a6ad20948f60f5e0ecd2f7b9c2901061))
2391	2390
2392		DISK_REGION( "ide:0:hdd" )
	2391	DISK_REGION( "ata:0:hdd:image" )
2393	2392	DISK_IMAGE( "a41a02", 0, SHA1(bbb71e23bddfa07dfa30b6565a35befd82b055b8) )
2394	2393	ROM_END
2395	2394
r23786	r23787
2403	2402	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2404	2403	ROM_LOAD("941eaa_nvram.u39", 0x00000, 0x2000, NO_DUMP )
2405	2404
2406		DISK_REGION( "ide:0:hdd" )
	2405	DISK_REGION( "ata:0:hdd:image" )
2407	2406	DISK_IMAGE( "a41c02", 0, SHA1(ab3020e8709768c0fd2467573e92b679a05944e5) )
2408	2407	ROM_END
2409	2408
r23786	r23787
2416	2415	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2417	2416	ROM_LOAD("a30eab_nvram.u39", 0x00000, 0x2000, CRC(c123342c) SHA1(55416767608fe0311a362854a16b214b04435a31))
2418	2417
2419		DISK_REGION( "ide:0:hdd" )
	2418	DISK_REGION( "ata:0:hdd:image" )
2420	2419	DISK_IMAGE( "a30b02", 0, SHA1(d2be83b7323c365ba445de7697c3fb8eb83d0212) )
2421	2420	ROM_END
2422	2421
r23786	r23787
2429	2428	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2430	2429	ROM_LOAD("a30jac_nvram.u39", 0x00000, 0x2000, NO_DUMP )
2431	2430
2432		DISK_REGION( "ide:0:hdd" )
	2431	DISK_REGION( "ata:0:hdd:image" )
2433	2432	DISK_IMAGE( "a30c02", 0, SHA1(533b5669b00884a800df9ba29651777a76559862) )
2434	2433	ROM_END
2435	2434
r23786	r23787
2443	2442	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2444	2443	ROM_LOAD("wcombat_nvram.u39", 0x00000, 0x2000, CRC(4f8b5858) SHA1(68066241c6f9db7f45e55b3c5da101987f4ce53c))
2445	2444
2446		DISK_REGION( "ide:0:hdd" )
	2445	DISK_REGION( "ata:0:hdd:image" )
2447	2446	DISK_IMAGE( "c22d02", 0, BAD_DUMP SHA1(85d2a8b5ec4cfd932190486cad991f0c180ca6b3) )
2448	2447	ROM_END
2449	2448
r23786	r23787
2453	2452	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2454	2453	ROM_LOAD("wcombatk_nvram.u39", 0x00000, 0x2000, CRC(ebd4d645) SHA1(2fa7e2c6b113214f3eb1900c8ceef4d5fcf0bb76))
2455	2454
2456		DISK_REGION( "ide:0:hdd" )
	2455	DISK_REGION( "ata:0:hdd:image" )
2457	2456	DISK_IMAGE( "c22c02", 0, BAD_DUMP SHA1(8bd1dfbf926ad5b28fa7dafd7e31c475325ec569) )
2458	2457	ROM_END
2459	2458
r23786	r23787
2466	2465	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2467	2466	ROM_LOAD("wcombatj_nvram.u39", 0x00000, 0x2000, CRC(bd8a6640) SHA1(2d409197ef3fb07d984d27fa943f29c7a711d715))
2468	2467
2469		DISK_REGION( "ide:0:hdd" )
	2468	DISK_REGION( "ata:0:hdd:image" )
2470	2469	DISK_IMAGE( "c22a02", 0, BAD_DUMP SHA1(b607fb2ddfd0bd552b7a736cea4ac1aa3ea021bd) )
2471	2470	ROM_END
2472	2471
r23786	r23787
2479	2478	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2480	2479	ROM_LOAD("b4xjab_nvram.u39", 0x00000, 0x2000, CRC(33708a93) SHA1(715968e3c9c15edf628fa6ac655dc0864e336c6c))
2481	2480
2482		DISK_REGION( "ide:0:hdd" )
	2481	DISK_REGION( "ata:0:hdd:image" )
2483	2482	DISK_IMAGE( "b4xb02", 0, SHA1(d8d54f3f16b762bf0187fe29b2f8696015c0a940) )
2484	2483	ROM_END
2485	2484
r23786	r23787
2541	2540	ROM_LOAD("nvram.u39", 0x00000, 0x2000, CRC(9fb551a5) SHA1(a33d185e186d404c3bf62277d7e34e5ad0000b09)) //likely non-default settings
2542	2541	ROM_LOAD("c09jad_nvram.u39", 0x00000, 0x2000, CRC(33e960b7) SHA1(a9a249e68c89b18d4685f1859fe35dc21df18e14))
2543	2542
2544		DISK_REGION( "ide:0:hdd" )
	2543	DISK_REGION( "ata:0:hdd:image" )
2545	2544	DISK_IMAGE( "c09d04", 0, SHA1(7395b7a33e953f65827aea44461e49f8388464fb) )
2546	2545	ROM_END
2547	2546
r23786	r23787
2555	2554	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2556	2555	ROM_LOAD("c09jac_nvram.u39", 0x00000, 0x2000, NO_DUMP )
2557	2556
2558		DISK_REGION( "ide:0:hdd" )
	2557	DISK_REGION( "ata:0:hdd:image" )
2559	2558	DISK_IMAGE( "c09c04", 0, SHA1(bf5f7447d74399d34edd4eb6dfcca7f6fc2154f2) )
2560	2559	ROM_END
2561	2560

trunk/src/mame/drivers/vp101.c

r23786	r23787
15	15
16	16	#include "emu.h"
17	17	#include "cpu/mips/mips3.h"
18		#include "machine/idectrl.h"
	18	#include "machine/ataintf.h"
19	19
20	20
21	21	class vp10x_state : public driver_device
r23786	r23787
103	103	ROM_REGION(0x80000, "pic", 0)       /* PIC18c422 program - read-protected, need dumped */
104	104	ROM_LOAD( "8722a-1206.bin", 0x000000, 0x80000, NO_DUMP )
105	105
106		DISK_REGION( "ide" )
	106	DISK_REGION( "ata:0:hdd:image" )
107	107	DISK_IMAGE_READONLY("jn010108", 0, SHA1(4f3e9c6349c9be59213df1236dba7d79e7cd704e) )
108	108	ROM_END
109	109
r23786	r23787
115	115	ROM_REGION(0x80000, "pic", 0)       /* PIC18c422 I/P program - read-protected, need dumped */
116	116	ROM_LOAD( "special_forces_et_u7_rev1.2.u7", 0x000000, 0x80000, NO_DUMP )
117	117
118		DISK_REGION( "ide" )
	118	DISK_REGION( "ata:0:hdd:image" )
119	119	DISK_IMAGE_READONLY("sf010101", 0, SHA1(59b5e3d8e1d5537204233598830be2066aad0556) )
120	120	ROM_END
121	121

trunk/src/mame/drivers/extrema.c

r23786	r23787
64	64	ROM_END
65	65
66	66	#define MISSING_DISK \
67		DISK_REGION( "ide" ) \
	67	DISK_REGION( "ata:0:hdd:image" ) \
68	68	DISK_IMAGE( "extrema_hdd", 0, NO_DUMP )
69	69
70	70	ROM_START( adults )

trunk/src/mame/drivers/fruitpc.c

r23786	r23787
70	70
71	71	static ADDRESS_MAP_START( fruitpc_io, AS_IO, 32, fruitpc_state )
72	72	AM_IMPORT_FROM(pcat32_io_common)
73		AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
	73	AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
74	74	AM_RANGE(0x0310, 0x0313) AM_READ8(fruit_inp_r, 0xffffffff)
75	75	AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
76	76	AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
77	77	AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
78		AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
	78	AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
79	79	ADDRESS_MAP_END
80	80
81	81	#define AT_KEYB_HELPER(bit, text, key1) \
r23786	r23787
157	157
158	158	MCFG_FRAGMENT_ADD( pcat_common )
159	159
160		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
161		MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
	160	MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	161	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
162	162
163	163	/* video hardware */
164	164	MCFG_FRAGMENT_ADD( pcvideo_vga )
r23786	r23787
175	175	ROM_REGION( 0x20000, "bios", 0 )
176	176	ROM_LOAD( "at-gs001.bin", 0x000000, 0x020000, CRC(7dec34d0) SHA1(81d194d67fef9f6531bd3cd1ee0baacb5c2558bf) )
177	177
178		DISK_REGION( "ide:0:hdd" )    // 8 MB Compact Flash card
	178	DISK_REGION( "ide:0:hdd:image" )    // 8 MB Compact Flash card
179	179	DISK_IMAGE( "fruit", 0,SHA1(df250ff06a97fa141a4144034f7035ac2947c53c) )
180	180	ROM_END
181	181

trunk/src/mame/drivers/kinst.c

r23786	r23787
131	131	#include "emu.h"
132	132	#include "cpu/mips/mips3.h"
133	133	#include "cpu/adsp2100/adsp2100.h"
134		#include "machine/idectrl.h"
	134	#include "machine/ataintf.h"
135	135	#include "machine/midwayic.h"
136	136	#include "audio/dcs.h"
137	137
r23786	r23787
151	151	m_control(*this, "control"),
152	152	m_rombase(*this, "rombase"),
153	153	m_maincpu(*this, "maincpu"),
154		m_ide(*this, "ide" )
	154	m_ata(*this, "ata" )
155	155	{
156	156	}
157	157
r23786	r23787
175	175	UINT32 screen_update_kinst(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
176	176	INTERRUPT_GEN_MEMBER(irq0_start);
177	177	required_device<cpu_device> m_maincpu;
178		required_device<ide_controller_device> m_ide;
	178	required_device<ata_interface_device> m_ata;
179	179
180	180	protected:
181	181	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
r23786	r23787
215	215
216	216	void kinst_state::machine_reset()
217	217	{
218		UINT8 *identify_device = m_ide->identify_device_buffer(0);
	218	UINT8 *identify_device = m_ata->identify_device_buffer(0);
219	219
220	220	if (strncmp(machine().system().name, "kinst2", 6) != 0)
221	221	{
r23786	r23787
325	325
326	326	READ32_MEMBER(kinst_state::kinst_ide_r)
327	327	{
328		return m_ide->read_cs0(space, offset / 2, mem_mask);
	328	return m_ata->read_cs0(space, offset / 2, mem_mask);
329	329	}
330	330
331	331
332	332	WRITE32_MEMBER(kinst_state::kinst_ide_w)
333	333	{
334		m_ide->write_cs0(space, offset / 2, data, mem_mask);
	334	m_ata->write_cs0(space, offset / 2, data, mem_mask);
335	335	}
336	336
337	337
338	338	READ32_MEMBER(kinst_state::kinst_ide_extra_r)
339	339	{
340		return m_ide->read_cs1(space, 6, 0xff);
	340	return m_ata->read_cs1(space, 6, 0xff);
341	341	}
342	342
343	343
344	344	WRITE32_MEMBER(kinst_state::kinst_ide_extra_w)
345	345	{
346		m_ide->write_cs1(space, 6, data, 0xff);
	346	m_ata->write_cs1(space, 6, data, 0xff);
347	347	}
348	348
349	349
r23786	r23787
689	689	MCFG_CPU_VBLANK_INT_DRIVER("screen", kinst_state,  irq0_start)
690	690
691	691
692		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
693		MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(kinst_state, ide_interrupt))
	692	MCFG_ATA_INTERFACE_ADD("ata", ata_devices, "hdd", NULL, true)
	693	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(kinst_state, ide_interrupt))
694	694
695	695	/* video hardware */
696	696	MCFG_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
r23786	r23787
731	731	ROM_LOAD16_BYTE( "u35-l1", 0xc00000, 0x80000, CRC(0aaef4fc) SHA1(48c4c954ac9db648f28ad64f9845e19ec432eec3) )
732	732	ROM_LOAD16_BYTE( "u36-l1", 0xe00000, 0x80000, CRC(0577bb60) SHA1(cc78070cc41701e9a91fde5cfbdc7e1e83354854) )
733	733
734		DISK_REGION( "ide:0:hdd" )
	734	DISK_REGION( "ata:0:hdd:image" )
735	735	DISK_IMAGE( "kinst", 0, SHA1(81d833236e994528d1482979261401b198d1ca53) )
736	736	ROM_END
737	737
r23786	r23787
750	750	ROM_LOAD16_BYTE( "u35-l1", 0xc00000, 0x80000, CRC(0aaef4fc) SHA1(48c4c954ac9db648f28ad64f9845e19ec432eec3) )
751	751	ROM_LOAD16_BYTE( "u36-l1", 0xe00000, 0x80000, CRC(0577bb60) SHA1(cc78070cc41701e9a91fde5cfbdc7e1e83354854) )
752	752
753		DISK_REGION( "ide:0:hdd" )
	753	DISK_REGION( "ata:0:hdd:image" )
754	754	DISK_IMAGE( "kinst", 0, SHA1(81d833236e994528d1482979261401b198d1ca53) )
755	755	ROM_END
756	756
r23786	r23787
769	769	ROM_LOAD16_BYTE( "u35-l1", 0xc00000, 0x80000, CRC(0aaef4fc) SHA1(48c4c954ac9db648f28ad64f9845e19ec432eec3) )
770	770	ROM_LOAD16_BYTE( "u36-l1", 0xe00000, 0x80000, CRC(0577bb60) SHA1(cc78070cc41701e9a91fde5cfbdc7e1e83354854) )
771	771
772		DISK_REGION( "ide:0:hdd" )
	772	DISK_REGION( "ata:0:hdd:image" )
773	773	DISK_IMAGE( "kinst", 0, SHA1(81d833236e994528d1482979261401b198d1ca53) )
774	774	ROM_END
775	775
r23786	r23787
788	788	ROM_LOAD16_BYTE( "u35-l1", 0xc00000, 0x80000, CRC(0aaef4fc) SHA1(48c4c954ac9db648f28ad64f9845e19ec432eec3) )
789	789	ROM_LOAD16_BYTE( "u36-l1", 0xe00000, 0x80000, CRC(0577bb60) SHA1(cc78070cc41701e9a91fde5cfbdc7e1e83354854) )
790	790
791		DISK_REGION( "ide:0:hdd" )
	791	DISK_REGION( "ata:0:hdd:image" )
792	792	DISK_IMAGE( "kinst", 0, SHA1(81d833236e994528d1482979261401b198d1ca53) )
793	793	ROM_END
794	794
r23786	r23787
807	807	ROM_LOAD16_BYTE( "ki2_l1.u35", 0xc00000, 0x80000, CRC(7245ce69) SHA1(24a3ff009c8a7f5a0bfcb198b8dcb5df365770d3) )
808	808	ROM_LOAD16_BYTE( "ki2_l1.u36", 0xe00000, 0x80000, CRC(8920acbb) SHA1(0fca72c40067034939b984b4bf32972a5a6c26af) )
809	809
810		DISK_REGION( "ide:0:hdd" )
	810	DISK_REGION( "ata:0:hdd:image" )
811	811	DISK_IMAGE( "kinst2", 0, SHA1(e7c9291b4648eae0012ea0cc230731ed4987d1d5) )
812	812	ROM_END
813	813
r23786	r23787
826	826	ROM_LOAD16_BYTE( "ki2_l1.u35", 0xc00000, 0x80000, CRC(7245ce69) SHA1(24a3ff009c8a7f5a0bfcb198b8dcb5df365770d3) )
827	827	ROM_LOAD16_BYTE( "ki2_l1.u36", 0xe00000, 0x80000, CRC(8920acbb) SHA1(0fca72c40067034939b984b4bf32972a5a6c26af) )
828	828
829		DISK_REGION( "ide:0:hdd" )
	829	DISK_REGION( "ata:0:hdd:image" )
830	830	DISK_IMAGE( "kinst2", 0, SHA1(e7c9291b4648eae0012ea0cc230731ed4987d1d5) )
831	831	ROM_END
832	832
r23786	r23787
845	845	ROM_LOAD16_BYTE( "ki2_l1.u35", 0xc00000, 0x80000, CRC(7245ce69) SHA1(24a3ff009c8a7f5a0bfcb198b8dcb5df365770d3) )
846	846	ROM_LOAD16_BYTE( "ki2_l1.u36", 0xe00000, 0x80000, CRC(8920acbb) SHA1(0fca72c40067034939b984b4bf32972a5a6c26af) )
847	847
848		DISK_REGION( "ide:0:hdd" )
	848	DISK_REGION( "ata:0:hdd:image" )
849	849	DISK_IMAGE( "kinst2", 0, SHA1(e7c9291b4648eae0012ea0cc230731ed4987d1d5) )
850	850	ROM_END
851	851
r23786	r23787
864	864	ROM_LOAD16_BYTE( "ki2_l1.u35", 0xc00000, 0x80000, CRC(7245ce69) SHA1(24a3ff009c8a7f5a0bfcb198b8dcb5df365770d3) )
865	865	ROM_LOAD16_BYTE( "ki2_l1.u36", 0xe00000, 0x80000, CRC(8920acbb) SHA1(0fca72c40067034939b984b4bf32972a5a6c26af) )
866	866
867		DISK_REGION( "ide:0:hdd" )
	867	DISK_REGION( "ata:0:hdd:image" )
868	868	DISK_IMAGE( "kinst2", 0, SHA1(e7c9291b4648eae0012ea0cc230731ed4987d1d5) )
869	869	ROM_END
870	870
r23786	r23787
883	883	ROM_LOAD16_BYTE( "ki2_l1.u35", 0xc00000, 0x80000, CRC(7245ce69) SHA1(24a3ff009c8a7f5a0bfcb198b8dcb5df365770d3) )
884	884	ROM_LOAD16_BYTE( "ki2_l1.u36", 0xe00000, 0x80000, CRC(8920acbb) SHA1(0fca72c40067034939b984b4bf32972a5a6c26af) )
885	885
886		DISK_REGION( "ide:0:hdd" )
	886	DISK_REGION( "ata:0:hdd:image" )
887	887	DISK_IMAGE( "kinst2", 0, SHA1(e7c9291b4648eae0012ea0cc230731ed4987d1d5) )
888	888	ROM_END
889	889
r23786	r23787
902	902	ROM_LOAD16_BYTE( "ki2_l1.u35", 0xc00000, 0x80000, CRC(7245ce69) SHA1(24a3ff009c8a7f5a0bfcb198b8dcb5df365770d3) )
903	903	ROM_LOAD16_BYTE( "ki2_l1.u36", 0xe00000, 0x80000, CRC(8920acbb) SHA1(0fca72c40067034939b984b4bf32972a5a6c26af) )
904	904
905		DISK_REGION( "ide:0:hdd" )
	905	DISK_REGION( "ata:0:hdd:image" )
906	906	DISK_IMAGE( "kinst2", 0, SHA1(e7c9291b4648eae0012ea0cc230731ed4987d1d5) )
907	907	ROM_END
908	908

trunk/src/mame/drivers/funkball.c

r23786	r23787
401	401	AM_IMPORT_FROM(pcat32_io_common)
402	402	AM_RANGE(0x00e8, 0x00ef) AM_NOP
403	403
404		AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
405		AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
	404	AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
	405	AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
406	406	AM_RANGE(0x03f8, 0x03ff) AM_READWRITE8(serial_r,serial_w,0xffffffff)
407	407
408	408	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
r23786	r23787
869	869	MCFG_PCI_BUS_LEGACY_DEVICE(7, "voodoo_0", voodoo_0_pci_r, voodoo_0_pci_w)
870	870	MCFG_PCI_BUS_LEGACY_DEVICE(18, NULL, cx5510_pci_r, cx5510_pci_w)
871	871
872		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
873		MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
	872	MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	873	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
874	874
875	875	/* video hardware */
876	876	MCFG_3DFX_VOODOO_1_ADD("voodoo_0", STD_VOODOO_1_CLOCK, voodoo_intf)

trunk/src/mame/drivers/gamecstl.c

r23786	r23787
345	345	AM_IMPORT_FROM(pcat32_io_common)
346	346	AM_RANGE(0x00e8, 0x00eb) AM_NOP
347	347	AM_RANGE(0x00ec, 0x00ef) AM_NOP
348		AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
	348	AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
349	349	AM_RANGE(0x0300, 0x03af) AM_NOP
350	350	AM_RANGE(0x03b0, 0x03df) AM_NOP
351	351	AM_RANGE(0x0278, 0x027b) AM_WRITE(pnp_config_w)
352		AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
	352	AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
353	353	AM_RANGE(0x0a78, 0x0a7b) AM_WRITE(pnp_data_w)
354	354	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
355	355	ADDRESS_MAP_END
r23786	r23787
435	435	MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
436	436	MCFG_PCI_BUS_LEGACY_DEVICE(7, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
437	437
438		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
439		MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
	438	MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	439	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
440	440
441	441	/* video hardware */
442	442	MCFG_SCREEN_ADD("screen", RASTER)
r23786	r23787
469	469	ROM_REGION(0x08100, "gfx1", 0)
470	470	ROM_LOAD("cga.chr",     0x00000, 0x01000, BAD_DUMP CRC(42009069) SHA1(ed08559ce2d7f97f68b9f540bddad5b6295294dd))
471	471
472		DISK_REGION( "ide:0:hdd" )
	472	DISK_REGION( "ide:0:hdd:image" )
473	473	DISK_IMAGE( "gamecstl", 0, SHA1(b431af3c42c48ba07972d77a3d24e60ee1e4359e) )
474	474	ROM_END
475	475
r23786	r23787
480	480	ROM_REGION(0x08100, "gfx1", 0)
481	481	ROM_LOAD("cga.chr",     0x00000, 0x01000, BAD_DUMP CRC(42009069) SHA1(ed08559ce2d7f97f68b9f540bddad5b6295294dd))
482	482
483		DISK_REGION( "ide:0:hdd" )
	483	DISK_REGION( "ide:0:hdd:image" )
484	484	DISK_IMAGE( "gamecst2", 0, SHA1(14e1b311cb474801c7bdda3164a0c220fb102159) )
485	485	ROM_END
486	486

trunk/src/mame/drivers/voyager.c

r23786	r23787
248	248	//AM_RANGE(0x00e8, 0x00eb) AM_NOP
249	249	AM_RANGE(0x00e8, 0x00ef) AM_NOP //AMI BIOS write to this ports as delays between I/O ports operations sending al value -> NEWIODELAY
250	250	AM_RANGE(0x0170, 0x0177) AM_NOP //To debug
251		AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
	251	AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
252	252	AM_RANGE(0x0200, 0x021f) AM_NOP //To debug
253	253	AM_RANGE(0x0260, 0x026f) AM_NOP //To debug
254	254	AM_RANGE(0x0278, 0x027b) AM_WRITENOP//AM_WRITE(pnp_config_w)
r23786	r23787
267	267	AM_RANGE(0x0378, 0x037f) AM_NOP //To debug
268	268	// AM_RANGE(0x0300, 0x03af) AM_NOP
269	269	// AM_RANGE(0x03b0, 0x03df) AM_NOP
270		AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
	270	AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
271	271	AM_RANGE(0x03f8, 0x03ff) AM_NOP // To debug Serial Port COM1:
272	272	AM_RANGE(0x0a78, 0x0a7b) AM_WRITENOP//AM_WRITE(pnp_data_w)
273	273	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
r23786	r23787
480	480
481	481	MCFG_FRAGMENT_ADD( pcat_common )
482	482
483		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
484		MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
	483	MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	484	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
485	485
486	486	MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
487	487	MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
r23786	r23787
511	511
512	512	ROM_REGION( 0x800, "nvram", ROMREGION_ERASE00 )
513	513
514		DISK_REGION( "ide:0:hdd" )
	514	DISK_REGION( "ide:0:hdd:image" )
515	515	DISK_IMAGE_READONLY( "voyager", 0, SHA1(8b94f2420f6abb40148e4ba6eed8819d8e85dbde))
516	516	ROM_END
517	517

trunk/src/mame/drivers/zn.c

r23786	r23787
19	19	#include "machine/7200fifo.h"
20	20	#include "machine/znsec.h"
21	21	#include "machine/zndip.h"
	22	#include "machine/ataintf.h"
22	23	#include "machine/idectrl.h"
23	24	#include "audio/taitosnd.h"
24	25	#include "sound/2610intf.h"
r23786	r23787
88	89	DECLARE_MACHINE_RESET(coh1000c);
89	90	DECLARE_MACHINE_RESET(coh1000ta);
90	91	DECLARE_MACHINE_RESET(coh1000tb);
91		DECLARE_MACHINE_RESET(coh1000w);
92	92	DECLARE_MACHINE_RESET(coh1002e);
93	93	DECLARE_MACHINE_RESET(bam2);
94		DECLARE_MACHINE_RESET(jdredd);
95	94	DECLARE_MACHINE_RESET(coh1001l);
96	95	DECLARE_MACHINE_RESET(coh1002v);
97	96	DECLARE_MACHINE_RESET(coh1002m);
r23786	r23787
1359	1358	AM_RANGE(0x1f000000, 0x1f1fffff) AM_ROM AM_REGION("roms", 0)
1360	1359	AM_RANGE(0x1f000000, 0x1f000003) AM_WRITENOP
1361	1360	AM_RANGE(0x1f7e8000, 0x1f7e8003) AM_NOP
	1361	// 8/16
1362	1362	AM_RANGE(0x1f7e4030, 0x1f7e403f) AM_DEVREADWRITE8("ide", ide_controller_device, read_via_config, write_via_config, 0xffffffff)
1363		AM_RANGE(0x1f7e41f0, 0x1f7e41f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
1364		AM_RANGE(0x1f7e43f0, 0x1f7e43f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
1365		AM_RANGE(0x1f7f41f0, 0x1f7f41f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
1366		AM_RANGE(0x1f7f43f0, 0x1f7f43f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
	1363	AM_RANGE(0x1f7e41f0, 0x1f7e41f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
	1364	AM_RANGE(0x1f7e43f0, 0x1f7e43f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
	1365	// 32
	1366	AM_RANGE(0x1f7f41f0, 0x1f7f41f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
	1367	AM_RANGE(0x1f7f43f0, 0x1f7f43f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
1367	1368
1368	1369	AM_IMPORT_FROM(zn_map)
1369	1370	ADDRESS_MAP_END
1370	1371
1371		MACHINE_RESET_MEMBER(zn_state,coh1000w)
1372		{
1373		m_ide->reset();
1374		}
1375
1376	1372	static MACHINE_CONFIG_DERIVED( coh1000w, zn1_2mb_vram )
1377	1373	MCFG_CPU_MODIFY("maincpu")
1378	1374	MCFG_CPU_PROGRAM_MAP(coh1000w_map)
r23786	r23787
1380	1376	MCFG_RAM_MODIFY("maincpu:ram")
1381	1377	MCFG_RAM_DEFAULT_SIZE("8M")
1382	1378
1383		MCFG_MACHINE_RESET_OVERRIDE(zn_state, coh1000w )
1384
1385		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
1386		MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("maincpu:irq", psxirq_device, intin10))
	1379	MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	1380	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("maincpu:irq", psxirq_device, intin10))
1387	1381	MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 5, psx_dma_read_delegate( FUNC( zn_state::atpsx_dma_read ), (zn_state *) owner ) )
1388	1382	MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 5, psx_dma_write_delegate( FUNC( zn_state::atpsx_dma_write ), (zn_state *) owner ) )
1389	1383	MACHINE_CONFIG_END
r23786	r23787
1956	1950	ADDRESS_MAP_END
1957	1951
1958	1952	static ADDRESS_MAP_START(jdredd_map, AS_PROGRAM, 32, zn_state)
1959		AM_RANGE(0x1fbfff80, 0x1fbfff8f) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
1960		AM_RANGE(0x1fbfff90, 0x1fbfff9f) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
	1953	AM_RANGE(0x1fbfff80, 0x1fbfff8f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs1, write_cs1, 0xffffffff)
	1954	AM_RANGE(0x1fbfff90, 0x1fbfff9f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs0, write_cs0, 0xffffffff)
1961	1955
1962	1956	AM_IMPORT_FROM(coh1000a_map)
1963	1957	ADDRESS_MAP_END
1964	1958
1965		MACHINE_RESET_MEMBER(zn_state,jdredd)
1966		{
1967		m_ide->reset();
1968		}
1969
1970	1959	static MACHINE_CONFIG_DERIVED( coh1000a, zn1_2mb_vram )
1971	1960	MCFG_CPU_MODIFY("maincpu")
1972	1961	MCFG_CPU_PROGRAM_MAP(coh1000a_map)
r23786	r23787
1986	1975	MCFG_DEVICE_MODIFY("gpu")
1987	1976	MCFG_PSXGPU_VBLANK_CALLBACK(vblank_state_delegate( FUNC( zn_state::jdredd_vblank ), (zn_state *) owner))
1988	1977
1989		MCFG_MACHINE_RESET_OVERRIDE(zn_state, jdredd)
1990
1991		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
1992		MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("maincpu:irq", psxirq_device, intin10))
	1978	MCFG_ATA_INTERFACE_ADD("ata", ata_devices, "hdd", NULL, true)
	1979	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("maincpu:irq", psxirq_device, intin10))
1993	1980	MACHINE_CONFIG_END
1994	1981
1995	1982	/*
r23786	r23787
4399	4386	ROM_LOAD( "mtr-bam-a09.u31", 0x2400000, 0x400000, CRC(e4bd7cec) SHA1(794d10b15a22aeed89082f4db2f3cb94aa7d807d) )
4400	4387	ROM_LOAD( "mtr-bam-a10.u32", 0x2800000, 0x400000, CRC(37fd1fa0) SHA1(afe846a817e499c405a5fd4ad83094270640faf3) )
4401	4388
4402		DISK_REGION( "ide:0:hdd" )
	4389	DISK_REGION( "ata:0:hdd:image" )
4403	4390	DISK_IMAGE("bam2", 0, SHA1(634d9a745a82c567fc4d7ce48e3570d88326c5f9) )
4404	4391	ROM_END
4405	4392
r23786	r23787
4423	4410	ROM_LOAD16_BYTE( "pr2_036.u17",  0x100001, 0x080000, CRC(3681516c) SHA1(714f73ea4ac190c36a6eb2308616a4aecabc4e69) )
4424	4411	ROM_LOAD16_BYTE( "pr2_036.u15",  0x100000, 0x080000, CRC(4b24bd54) SHA1(7f27cd524d10e5869aab6d4dc6a4217d049c475d) )
4425	4412
4426		DISK_REGION( "ide:0:hdd" )
	4413	DISK_REGION( "ide:0:hdd:image" )
4427	4414	DISK_IMAGE( "primrag2", 0, SHA1(bc615068ddf4fd967f770ee01c02f285c052c4c5) )
4428	4415	ROM_END
4429	4416
r23786	r23787
4475	4462	ROM_LOAD16_BYTE( "j-dread.u36",  0x000001, 0x020000, CRC(37addbf9) SHA1(a4061a1ba9e230f080f0bfea69bf77efe9264a92) )
4476	4463	ROM_LOAD16_BYTE( "j-dread.u35",  0x000000, 0x020000, CRC(c1e17191) SHA1(82901439b1a51b9aadb4df4b9d944f26697a1460) )
4477	4464
4478		DISK_REGION( "ide:0:hdd" )
	4465	DISK_REGION( "ata:0:hdd:image" )
4479	4466	DISK_IMAGE( "jdreddc", 0, SHA1(eee205f83e5f590f8baf36452c873d7063156bd0) )
4480	4467	ROM_END
4481	4468
r23786	r23787
4486	4473	ROM_LOAD16_BYTE( "j-dread.u36",  0x000001, 0x020000, CRC(37addbf9) SHA1(a4061a1ba9e230f080f0bfea69bf77efe9264a92) )
4487	4474	ROM_LOAD16_BYTE( "j-dread.u35",  0x000000, 0x020000, CRC(c1e17191) SHA1(82901439b1a51b9aadb4df4b9d944f26697a1460) )
4488	4475
4489		DISK_REGION( "ide:0:hdd" )
	4476	DISK_REGION( "ide:0:hdd:image" )
4490	4477	DISK_IMAGE( "jdreddb", 0, SHA1(20f696fa6e1fbf97793bac2a794631c5dd4fb39a) )
4491	4478	ROM_END
4492	4479

trunk/src/mame/drivers/queen.c

r23786	r23787
236	236	AM_IMPORT_FROM(pcat32_io_common)
237	237	AM_RANGE(0x00e8, 0x00ef) AM_NOP
238	238
239		AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
	239	AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
240	240	AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
241	241	AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
242	242	AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
243		AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
	243	AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
244	244
245	245	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
246	246	ADDRESS_MAP_END
r23786	r23787
273	273	MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
274	274	MCFG_PCI_BUS_LEGACY_DEVICE(7, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
275	275
276		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
277		MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
	276	MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	277	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
278	278
279	279	/* video hardware */
280	280	MCFG_FRAGMENT_ADD( pcvideo_vga )
r23786	r23787
291	291	//  ROM_LOAD16_BYTE( "trident_tgui9680_bios.bin", 0x0000, 0x4000, BAD_DUMP CRC(1eebde64) SHA1(67896a854d43a575037613b3506aea6dae5d6a19) )
292	292	//  ROM_CONTINUE(                                 0x0001, 0x4000 )
293	293
294		DISK_REGION( "ide:0:hdd" )
	294	DISK_REGION( "ide:0:hdd:image" )
295	295	DISK_IMAGE( "pqiidediskonmodule", 0,SHA1(a56efcc711b1c5a2e63160b3088001a8c4fb56c2) )
296	296	ROM_END
297	297

trunk/src/mame/drivers/chihiro.c

r23786	r23787
365	365	#include "machine/pic8259.h"
366	366	#include "machine/pit8253.h"
367	367	#include "machine/idectrl.h"
	368	#include "machine/idehd.h"
368	369	#include "machine/naomigd.h"
369	370	#include "video/polynew.h"
370	371	#include "bitmap.h"
r23786	r23787
2656	2657
2657	2658	// ======================> ide_baseboard_device
2658	2659
2659		class ide_baseboard_device : public ide_mass_storage_device
	2660	class ide_baseboard_device : public ata_mass_storage_device
2660	2661	{
2661	2662	public:
2662	2663	// construction/destruction
r23786	r23787
2666	2667	virtual int  write_sector(UINT32 lba, const void *buffer);
2667	2668	protected:
2668	2669	// device-level overrides
2669		virtual void device_start();
2670	2670	virtual void device_reset();
2671	2671	};
2672	2672
r23786	r23787
2682	2682	//-------------------------------------------------
2683	2683
2684	2684	ide_baseboard_device::ide_baseboard_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
2685		: ide_mass_storage_device(mconfig, IDE_BASEBOARD, "IDE Baseboard", tag, owner, clock, "ide_baseboard", __FILE__)
	2685	: ata_mass_storage_device(mconfig, IDE_BASEBOARD, "IDE Baseboard", tag, owner, clock, "ide_baseboard", __FILE__)
2686	2686	{
2687	2687	}
2688	2688
2689	2689	//-------------------------------------------------
2690		//  device_start - device-specific startup
2691		//-------------------------------------------------
2692
2693		void ide_baseboard_device::device_start()
2694		{
2695		}
2696
2697		//-------------------------------------------------
2698	2690	//  device_reset - device-specific reset
2699	2691	//-------------------------------------------------
2700	2692
2701	2693	void ide_baseboard_device::device_reset()
2702	2694	{
	2695	ata_mass_storage_device::device_reset();
	2696
2703	2697	m_num_cylinders=65535;
2704	2698	m_num_sectors=255;
2705	2699	m_num_heads=255;
r23786	r23787
2951	2945	AM_RANGE(0x0020, 0x0023) AM_DEVREADWRITE8("pic8259_1", pic8259_device, read, write, 0xffffffff)
2952	2946	AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("pit8254", pit8254_device, read, write, 0xffffffff)
2953	2947	AM_RANGE(0x00a0, 0x00a3) AM_DEVREADWRITE8("pic8259_2", pic8259_device, read, write, 0xffffffff)
2954		AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", bus_master_ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
	2948	AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", bus_master_ide_controller_device, read_cs0, write_cs0, 0xffffffff)
2955	2949	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
2956	2950	AM_RANGE(0x8000, 0x80ff) AM_READWRITE(dummy_r, dummy_w)
2957	2951	AM_RANGE(0xc000, 0xc0ff) AM_READWRITE(smbus_r, smbus_w)
r23786	r23787
3004	2998	MCFG_PIC8259_ADD( "pic8259_2", DEVWRITELINE("pic8259_1", pic8259_device, ir2_w), GND, NULL )
3005	2999	MCFG_PIT8254_ADD( "pit8254", chihiro_pit8254_config )
3006	3000	MCFG_BUS_MASTER_IDE_CONTROLLER_ADD( "ide", ide_baseboard, NULL, "bb", true)
3007		MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
	3001	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
3008	3002	MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE("maincpu", AS_PROGRAM)
3009	3003
3010	3004	/* video hardware */

trunk/src/mame/drivers/pyson.c

r23786	r23787
221	221	PYSON_BIOS
222	222
223	223	ROM_REGION(0x840000, "key", ROMREGION_ERASE00)
224		DISK_REGION( "ide:0:hdd" )
	224	DISK_REGION( "ide:0:hdd:image" )
225	225	ROM_END
226	226
227	227	ROM_START( wswe )
r23786	r23787
235	235	ROM_REGION(0x2000, "timekeeper", ROMREGION_ERASE00)
236	236	ROM_LOAD( "m48t58y.u48",       0x000000, 0x002000, CRC(d4181cb5) SHA1(c5560d1ac043bfe2527fac3fb1989fa8fc53cf8a) )
237	237
238		DISK_REGION( "ide:0:hdd" )
	238	DISK_REGION( "ide:0:hdd:image" )
239	239	DISK_IMAGE_READONLY( "c18jaa03", 0, SHA1(b47190aa38f1f3a499b817758e3f29fac54391bd) )
240	240	ROM_END
241	241
r23786	r23787
250	250	ROM_REGION(0x2000, "timekeeper", ROMREGION_ERASE00)
251	251	ROM_LOAD( "m48t58y.u48",       0x000000, 0x002000, CRC(76068de0) SHA1(5f75b88ad04871fb3799fe904658c87524bad94f) )
252	252
253		DISK_REGION( "ide:0:hdd" )
	253	DISK_REGION( "ide:0:hdd:image" )
254	254	DISK_IMAGE_READONLY( "c27jaa03", 0, SHA1(9b2aa900711d88cf5effb3ba6be18726ea006ac4) )
255	255	ROM_END
256	256

trunk/src/mame/drivers/taitotz.c

r23786	r23787
174	174	#include "emu.h"
175	175	#include "cpu/powerpc/ppc.h"
176	176	#include "cpu/tlcs900/tlcs900.h"
177		#include "machine/idectrl.h"
	177	#include "machine/ataintf.h"
178	178	#include "machine/nvram.h"
179	179	#include "video/polynew.h"
180	180
r23786	r23787
567	567	m_iocpu(*this, "iocpu"),
568	568	m_work_ram(*this, "work_ram"),
569	569	m_mbox_ram(*this, "mbox_ram"),
570		m_ide(*this, "ide")
	570	m_ata(*this, "ata")
571	571	{
572	572	}
573	573
r23786	r23787
575	575	required_device<cpu_device> m_iocpu;
576	576	required_shared_ptr<UINT64> m_work_ram;
577	577	required_shared_ptr<UINT8>  m_mbox_ram;
578		required_device<ide_controller_device> m_ide;
	578	required_device<ata_interface_device> m_ata;
579	579
580	580	DECLARE_READ64_MEMBER(ppc_common_r);
581	581	DECLARE_WRITE64_MEMBER(ppc_common_w);
r23786	r23787
2118	2118	{
2119	2119	if ((offset & 1) == 0)
2120	2120	{
2121		ide_cs0_latch_r = m_ide->read_cs0(space, reg, 0xffff);
	2121	ide_cs0_latch_r = m_ata->read_cs0(space, reg, 0xffff);
2122	2122	return (ide_cs0_latch_r & 0xff);
2123	2123	}
2124	2124	else
r23786	r23787
2131	2131	if (offset & 1)
2132	2132	fatalerror("tlcs_ide0_r: %02X, odd offset\n", offset);
2133	2133
2134		UINT8 d = m_ide->read_cs0(space, reg, 0xff);
	2134	UINT8 d = m_ata->read_cs0(space, reg, 0xff);
2135	2135	if (reg == 7)
2136	2136	d &= ~0x2;      // Type Zero doesn't like the index bit. It's defined as vendor-specific, so it probably shouldn't be up...
2137	2137	// The status check explicitly checks for 0x50 (drive ready, seek complete).
r23786	r23787
2154	2154	{
2155	2155	ide_cs0_latch_w &= 0x00ff;
2156	2156	ide_cs0_latch_w |= (UINT16)(data) << 8;
2157		m_ide->write_cs0(space, reg, ide_cs0_latch_w, 0xffff);
	2157	m_ata->write_cs0(space, reg, ide_cs0_latch_w, 0xffff);
2158	2158	}
2159	2159	}
2160	2160	else
2161	2161	{
2162	2162	if (offset & 1)
2163	2163	fatalerror("tlcs_ide0_w: %02X, %02X, odd offset\n", offset, data);
2164		m_ide->write_cs0(space, reg, data, 0xff);
	2164	m_ata->write_cs0(space, reg, data, 0xff);
2165	2165	}
2166	2166	}
2167	2167
r23786	r23787
2174	2174
2175	2175	if ((offset & 1) == 0)
2176	2176	{
2177		UINT8 d = m_ide->read_cs1(space, reg, 0xff);
	2177	UINT8 d = m_ata->read_cs1(space, reg, 0xff);
2178	2178	d &= ~0x2;      // Type Zero doesn't like the index bit. It's defined as vendor-specific, so it probably shouldn't be up...
2179	2179	// The status check explicitly checks for 0x50 (drive ready, seek complete).
2180	2180	return d;
r23786	r23787
2182	2182	else
2183	2183	{
2184	2184	//fatalerror("tlcs_ide1_r: %02X, odd offset\n", offset);
2185		UINT8 d = m_ide->read_cs1(space, reg, 0xff);
	2185	UINT8 d = m_ata->read_cs1(space, reg, 0xff);
2186	2186	d &= ~0x2;
2187	2187	return d;
2188	2188	}
r23786	r23787
2204	2204	{
2205	2205	ide_cs1_latch_w &= 0x00ff;
2206	2206	ide_cs1_latch_w |= (UINT16)(data) << 16;
2207		m_ide->write_cs1(space, reg, ide_cs1_latch_w, 0xffff);
	2207	m_ata->write_cs1(space, reg, ide_cs1_latch_w, 0xffff);
2208	2208	}
2209	2209	}
2210	2210
r23786	r23787
2530	2530	{
2531	2531	if (m_hdd_serial_number != NULL)
2532	2532	{
2533		UINT8 *identify_device = m_ide->identify_device_buffer(0);
	2533	UINT8 *identify_device = m_ata->identify_device_buffer(0);
2534	2534
2535	2535	for (int i=0; i < 20; i++)
2536	2536	{
r23786	r23787
2590	2590
2591	2591	MCFG_QUANTUM_TIME(attotime::from_hz(120))
2592	2592
2593		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
2594		MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(taitotz_state, ide_interrupt))
	2593	MCFG_ATA_INTERFACE_ADD("ata", ata_devices, "hdd", NULL, true)
	2594	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(taitotz_state, ide_interrupt))
2595	2595
2596	2596	MCFG_NVRAM_ADD_0FILL("nvram")
2597	2597
r23786	r23787
2724	2724	ROM_REGION( 0x40000, "io_cpu", ROMREGION_ERASE00 )
2725	2725	ROM_REGION( 0x10000, "sound_cpu", ROMREGION_ERASE00 ) /* Internal ROM :( */
2726	2726	ROM_REGION( 0x500, "plds", ROMREGION_ERASE00 )
2727		DISK_REGION( "ide:0:hdd" )
	2727	DISK_REGION( "ata:0:hdd:image" )
2728	2728	ROM_END
2729	2729
2730	2730	ROM_START( landhigh )
r23786	r23787
2743	2743	ROM_LOAD( "e82-02.ic45", 0x117, 0x2dd, CRC(f581cff5) SHA1(468e0e6a3828f2dcda35c6d523154510f9c99db7) )
2744	2744	ROM_LOAD( "e68-06.ic24", 0x3f4, 0x100, NO_DUMP )
2745	2745
2746		DISK_REGION( "ide:0:hdd" )
	2746	DISK_REGION( "ata:0:hdd:image" )
2747	2747	DISK_IMAGE( "landhigh", 0, SHA1(7cea4ea5c3899e6ac774a4eb12821f44541d9c9c) )
2748	2748	ROM_END
2749	2749
r23786	r23787
2758	2758	ROM_REGION( 0x10000, "sound_cpu", 0 ) /* Internal ROM :( */
2759	2759	ROM_LOAD( "e68-01.ic7", 0x000000, 0x010000, NO_DUMP )
2760	2760
2761		DISK_REGION( "ide:0:hdd" )
	2761	DISK_REGION( "ata:0:hdd:image" )
2762	2762	DISK_IMAGE( "batlgear", 0, SHA1(eab283839ad3e0a3e6be11f6482570db334eacca) )
2763	2763	ROM_END
2764	2764
r23786	r23787
2773	2773	ROM_REGION( 0x10000, "sound_cpu", 0 ) /* Internal ROM :( */
2774	2774	ROM_LOAD( "e68-01.ic7", 0x000000, 0x010000, NO_DUMP )
2775	2775
2776		DISK_REGION( "ide:0:hdd" )
	2776	DISK_REGION( "ata:0:hdd:image" )
2777	2777	DISK_IMAGE( "bg2_204j", 0, SHA1(7ac100fba39ae0b93980c0af2f0212a731106912) )
2778	2778	ROM_END
2779	2779
r23786	r23787
2788	2788	ROM_REGION( 0x10000, "sound_cpu", 0 ) /* Internal ROM :( */
2789	2789	ROM_LOAD( "e68-01.ic7", 0x000000, 0x010000, NO_DUMP )
2790	2790
2791		DISK_REGION( "ide:0:hdd" )
	2791	DISK_REGION( "ata:0:hdd:image" )
2792	2792	DISK_IMAGE( "bg2_201j", 0, SHA1(542d12682bd0f95143368578461c6a4fcc492fcc) )
2793	2793	ROM_END
2794	2794
r23786	r23787
2812	2812	ROM_REGION( 0x20000, "oki2", 0 )
2813	2813	ROM_LOAD( "e74-08.ic8", 0x000000, 0x020000, CRC(ca5baccc) SHA1(4594b7a6232b912d698fff053f7e3f51d8e1bfb6) ) // located on the I/O PCB
2814	2814
2815		DISK_REGION( "ide:0:hdd" )
	2815	DISK_REGION( "ata:0:hdd:image" )
2816	2816	DISK_IMAGE( "pwrshovl", 0, SHA1(360f63b39f645851c513b4644fb40601b9ba1412) )
2817	2817	ROM_END
2818	2818
r23786	r23787
2827	2827	ROM_REGION( 0x10000, "sound_cpu", 0 ) /* Internal ROM :( */
2828	2828	ROM_LOAD( "e68-01.ic7", 0x000000, 0x010000, NO_DUMP )
2829	2829
2830		DISK_REGION( "ide:0:hdd" )
	2830	DISK_REGION( "ata:0:hdd:image" )
2831	2831	DISK_IMAGE( "raizpin", 0, SHA1(883ebcda03026df31da1cdb95af521e100c171ed) )
2832	2832	ROM_END
2833	2833

trunk/src/mame/drivers/atlantis.c

r23786	r23787
142	142	MCFG_CPU_PROGRAM_MAP(main_map)
143	143
144	144
145		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
	145	MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
146	146
147	147	/* video hardware */
148	148	MCFG_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
r23786	r23787
173	173	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* 512k for R4310 code */
174	174	ROM_LOAD( "skins_game_u4_boot_1.00.u4", 0x000000, 0x080000, CRC(0fe87720) SHA1(4b24abbe662a2d7b61e6a3f079e28b73605ba19f) )
175	175
176		DISK_REGION( "ide:0:hdd" )
	176	DISK_REGION( "ide:0:hdd:image" )
177	177	DISK_IMAGE( "mwskins", 0, SHA1(5cb293a6fdb2478293f48ddfc93cdd018acb2bb5) )
178	178	ROM_END
179	179
r23786	r23787
181	181	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* 512k for R4310 code */
182	182	ROM_LOAD( "skins_game_u4_boot_1.00.u4", 0x000000, 0x080000, CRC(0fe87720) SHA1(4b24abbe662a2d7b61e6a3f079e28b73605ba19f) )
183	183
184		DISK_REGION( "ide:0:hdd" )
	184	DISK_REGION( "ide:0:hdd:image" )
185	185	DISK_IMAGE( "mwskinsa", 0, SHA1(72497917b31156eb11a46bbcc6f22a254dcec044) )
186	186	ROM_END
187	187
r23786	r23787
189	189	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* 512k for R4310 code */
190	190	ROM_LOAD( "skins_game_u4_boot_1.00.u4", 0x000000, 0x080000, CRC(0fe87720) SHA1(4b24abbe662a2d7b61e6a3f079e28b73605ba19f) )
191	191
192		DISK_REGION( "ide:0:hdd" )
	192	DISK_REGION( "ide:0:hdd:image" )
193	193	DISK_IMAGE( "mwskins104", 0, SHA1(6917f66718999c144c854795c5856bf5659b85fa) )
194	194	ROM_END
195	195

trunk/src/mame/drivers/cobra.c

r23786	r23787
314	314	#include "emu.h"
315	315	#include "cpu/powerpc/ppc.h"
316	316	#include "machine/pci.h"
317		#include "machine/idectrl.h"
	317	#include "machine/ataintf.h"
318	318	#include "machine/timekpr.h"
319	319	#include "machine/jvshost.h"
320	320	#include "machine/jvsdev.h"
r23786	r23787
609	609	m_gfxcpu(*this, "gfxcpu"),
610	610	m_gfx_pagetable(*this, "pagetable"),
611	611	m_k001604(*this, "k001604"),
612		m_ide(*this, "ide")
	612	m_ata(*this, "ata")
613	613	{
614	614	}
615	615
r23786	r23787
618	618	required_device<cpu_device> m_gfxcpu;
619	619	required_shared_ptr<UINT64> m_gfx_pagetable;
620	620	required_device<k001604_device> m_k001604;
621		required_device<ide_controller_device> m_ide;
	621	required_device<ata_interface_device> m_ata;
622	622
623	623	DECLARE_READ64_MEMBER(main_comram_r);
624	624	DECLARE_WRITE64_MEMBER(main_comram_w);
r23786	r23787
1819	1819	{
1820	1820	mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 );
1821	1821
1822		UINT32 data = m_ide->read_cs0(space, offset, mem_mask);
	1822	UINT32 data = m_ata->read_cs0(space, offset, mem_mask);
1823	1823	data = ( data << 8 ) | ( data >> 8 );
1824	1824
1825	1825	return data;
r23786	r23787
1830	1830	mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 );
1831	1831	data = ( data << 8 ) | ( data >> 8 );
1832	1832
1833		m_ide->write_cs0(space, offset, data, mem_mask);
	1833	m_ata->write_cs0(space, offset, data, mem_mask);
1834	1834	}
1835	1835
1836	1836	READ16_MEMBER(cobra_state::sub_ata1_r)
1837	1837	{
1838	1838	mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 );
1839	1839
1840		UINT32 data = m_ide->read_cs1(space, offset, mem_mask);
	1840	UINT32 data = m_ata->read_cs1(space, offset, mem_mask);
1841	1841
1842	1842	return ( data << 8 ) | ( data >> 8 );
1843	1843	}
r23786	r23787
1847	1847	mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 );
1848	1848	data = ( data << 8 ) | ( data >> 8 );
1849	1849
1850		m_ide->write_cs1(space, offset, data, mem_mask);
	1850	m_ata->write_cs1(space, offset, data, mem_mask);
1851	1851	}
1852	1852
1853	1853	READ32_MEMBER(cobra_state::sub_comram_r)
r23786	r23787
3163	3163	{
3164	3164	m_sub_interrupt = 0xff;
3165	3165
3166		UINT8 *identify_device = m_ide->identify_device_buffer(0);
	3166	UINT8 *identify_device = m_ata->identify_device_buffer(0);
3167	3167
3168	3168	// Cobra expects these settings or the BIOS fails
3169	3169	identify_device[51*2+0] = 0;           /* 51: PIO data transfer cycle timing mode */
r23786	r23787
3204	3204	MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
3205	3205	MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, mpc106_pci_r, mpc106_pci_w)
3206	3206
3207		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
3208		MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(cobra_state, ide_interrupt))
	3207	MCFG_ATA_INTERFACE_ADD("ata", ata_devices, "hdd", NULL, true)
	3208	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(cobra_state, ide_interrupt))
3209	3209
3210	3210	/* video hardware */
3211	3211
r23786	r23787
3487	3487
3488	3488	ROM_REGION(0x1000000, "rfsnd", ROMREGION_ERASE00)
3489	3489
3490		DISK_REGION( "ide:0:hdd" )
	3490	DISK_REGION( "ata:0:hdd:image" )
3491	3491	DISK_IMAGE_READONLY( "645c04", 0, SHA1(c0aabe69f6eb4e4cf748d606ae50674297af6a04) )
3492	3492	ROM_END
3493	3493
r23786	r23787
3506	3506
3507	3507	ROM_REGION(0x1000000, "rfsnd", ROMREGION_ERASE00)
3508	3508
3509		DISK_REGION( "ide:0:hdd" )
	3509	DISK_REGION( "ata:0:hdd:image" )
3510	3510	DISK_IMAGE_READONLY( "676a04", 0, SHA1(8e89d3e5099e871b99fccba13adaa3cf8a6b71f0) )
3511	3511	ROM_END
3512	3512

trunk/src/mame/drivers/jaguar.c

r23786	r23787
1090	1090	else if( offset >= 0x1f0/4 && offset < 0x1f8/4 )
1091	1091	{
1092	1092	if (ACCESSING_BITS_0_15)
1093		data |= m_ide->read_cs0_pc(space, (offset * 2) & 7, mem_mask);
	1093	data |= m_ide->read_cs0(space, (offset * 2) & 7, mem_mask);
1094	1094	if (ACCESSING_BITS_16_31)
1095		data |= m_ide->read_cs0_pc(space, ((offset * 2) & 7) + 1, mem_mask >> 16) << 16;
	1095	data |= m_ide->read_cs0(space, ((offset * 2) & 7) + 1, mem_mask >> 16) << 16;
1096	1096	}
1097	1097	else if( offset >= 0x3f0/4 && offset < 0x3f8/4 )
1098	1098	{
1099	1099	if (ACCESSING_BITS_0_15)
1100		data |= m_ide->read_cs1_pc(space, (offset * 2) & 7, mem_mask);
	1100	data |= m_ide->read_cs1(space, (offset * 2) & 7, mem_mask);
1101	1101	if (ACCESSING_BITS_16_31)
1102		data |= m_ide->read_cs1_pc(space, ((offset * 2) & 7) + 1, mem_mask >> 16) << 16;
	1102	data |= m_ide->read_cs1(space, ((offset * 2) & 7) + 1, mem_mask >> 16) << 16;
1103	1103	}
1104	1104
1105	1105	return data;
r23786	r23787
1115	1115	else if( offset >= 0x1f0/4 && offset < 0x1f8/4 )
1116	1116	{
1117	1117	if (ACCESSING_BITS_0_15)
1118		m_ide->write_cs0_pc(space, (offset * 2) & 7, data, mem_mask);
	1118	m_ide->write_cs0(space, (offset * 2) & 7, data, mem_mask);
1119	1119	if (ACCESSING_BITS_16_31)
1120		m_ide->write_cs0_pc(space, ((offset * 2) & 7) + 1, data >> 16, mem_mask >> 16);
	1120	m_ide->write_cs0(space, ((offset * 2) & 7) + 1, data >> 16, mem_mask >> 16);
1121	1121	}
1122	1122	else if( offset >= 0x3f0/4 && offset < 0x3f8/4 )
1123	1123	{
1124	1124	if (ACCESSING_BITS_0_15)
1125		m_ide->write_cs1_pc(space, (offset * 2) & 7, data, mem_mask);
	1125	m_ide->write_cs1(space, (offset * 2) & 7, data, mem_mask);
1126	1126	if (ACCESSING_BITS_16_31)
1127		m_ide->write_cs1_pc(space, ((offset * 2) & 7) + 1, data >> 16, mem_mask >> 16);
	1127	m_ide->write_cs1(space, ((offset * 2) & 7) + 1, data >> 16, mem_mask >> 16);
1128	1128	}
1129	1129	}
1130	1130
r23786	r23787
1601	1601
1602	1602	MCFG_NVRAM_ADD_1FILL("nvram")
1603	1603
1604		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
1605		MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(jaguar_state, external_int))
	1604	MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	1605	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(jaguar_state, external_int))
1606	1606
1607	1607	/* video hardware */
1608	1608	MCFG_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
r23786	r23787
1623	1623
1624	1624	static MACHINE_CONFIG_DERIVED( cojagr3k_rom, cojagr3k )
1625	1625	MCFG_DEVICE_REMOVE("ide:0")
1626		MCFG_IDE_SLOT_ADD("ide:0", ide_devices, NULL, true)
	1626	MCFG_ATA_SLOT_ADD("ide:0", ata_devices, NULL, true)
1627	1627	MACHINE_CONFIG_END
1628	1628
1629	1629	static MACHINE_CONFIG_DERIVED( cojag68k, cojagr3k )
r23786	r23787
1897	1897	ROM_REGION16_BE( 0x1000, "waverom", 0 )
1898	1898	ROM_LOAD16_WORD("jagwave.rom", 0x0000, 0x1000, CRC(7a25ee5b) SHA1(58117e11fd6478c521fbd3fdbe157f39567552f0) )
1899	1899
1900		DISK_REGION( "ide:0:hdd" )
	1900	DISK_REGION( "ide:0:hdd:image" )
1901	1901	DISK_IMAGE( "area51t", 0, SHA1(d2865cc7b1bb08a4393a72013a90e18d8a8f9860) )
1902	1902	ROM_END
1903	1903
r23786	r23787
1911	1911	ROM_REGION16_BE( 0x1000, "waverom", 0 )
1912	1912	ROM_LOAD16_WORD("jagwave.rom", 0x0000, 0x1000, CRC(7a25ee5b) SHA1(58117e11fd6478c521fbd3fdbe157f39567552f0) )
1913	1913
1914		DISK_REGION( "ide:0:hdd" )
	1914	DISK_REGION( "ide:0:hdd:image" )
1915	1915	DISK_IMAGE( "area51", 0, SHA1(3b303bc37e206a6d7339352c869f050d04186f11) )
1916	1916	ROM_END
1917	1917
r23786	r23787
1925	1925	ROM_REGION16_BE( 0x1000, "waverom", 0 )
1926	1926	ROM_LOAD16_WORD("jagwave.rom", 0x0000, 0x1000, CRC(7a25ee5b) SHA1(58117e11fd6478c521fbd3fdbe157f39567552f0) )
1927	1927
1928		DISK_REGION( "ide:0:hdd" )
	1928	DISK_REGION( "ide:0:hdd:image" )
1929	1929	DISK_IMAGE( "area51", 0, SHA1(3b303bc37e206a6d7339352c869f050d04186f11) )
1930	1930	ROM_END
1931	1931
r23786	r23787
1939	1939	ROM_REGION16_BE( 0x1000, "waverom", 0 )
1940	1940	ROM_LOAD16_WORD("jagwave.rom", 0x0000, 0x1000, CRC(7a25ee5b) SHA1(58117e11fd6478c521fbd3fdbe157f39567552f0) )
1941	1941
1942		DISK_REGION( "ide:0:hdd" )
	1942	DISK_REGION( "ide:0:hdd:image" )
1943	1943	DISK_IMAGE( "maxforce", 0, SHA1(d54e7a8f3866bb2a1d28ae637e7c92ffa4dbe558) )
1944	1944	ROM_END
1945	1945
r23786	r23787
1954	1954	ROM_REGION16_BE( 0x1000, "waverom", 0 )
1955	1955	ROM_LOAD16_WORD("jagwave.rom", 0x0000, 0x1000, CRC(7a25ee5b) SHA1(58117e11fd6478c521fbd3fdbe157f39567552f0) )
1956	1956
1957		DISK_REGION( "ide:0:hdd" )
	1957	DISK_REGION( "ide:0:hdd:image" )
1958	1958	DISK_IMAGE( "maxforce", 0, SHA1(d54e7a8f3866bb2a1d28ae637e7c92ffa4dbe558) )
1959	1959	ROM_END
1960	1960
r23786	r23787
1972	1972	ROM_REGION( 0x800, "user2", 0 ) /* 28C16 style eeprom, currently loaded but not used */
1973	1973	ROM_LOAD( "28c16.17z", 0x000, 0x800, CRC(1cdd9088) SHA1(4f01f02ff95f31ced87a3cdd7f171afd92551266) )
1974	1974
1975		DISK_REGION( "ide:0:hdd" )
	1975	DISK_REGION( "ide:0:hdd:image" )
1976	1976	DISK_IMAGE( "maxforce", 0, SHA1(d54e7a8f3866bb2a1d28ae637e7c92ffa4dbe558) )
1977	1977	ROM_END
1978	1978
r23786	r23787
1987	1987	ROM_REGION16_BE( 0x1000, "waverom", 0 )
1988	1988	ROM_LOAD16_WORD("jagwave.rom", 0x0000, 0x1000, CRC(7a25ee5b) SHA1(58117e11fd6478c521fbd3fdbe157f39567552f0) )
1989	1989
1990		DISK_REGION( "ide:0:hdd" )
	1990	DISK_REGION( "ide:0:hdd:image" )
1991	1991	DISK_IMAGE( "area51mx", 0, SHA1(5ff10f4e87094d4449eabf3de7549564ca568c7e) )
1992	1992	ROM_END
1993	1993
r23786	r23787
2002	2002	ROM_REGION16_BE( 0x1000, "waverom", 0 )
2003	2003	ROM_LOAD16_WORD("jagwave.rom", 0x0000, 0x1000, CRC(7a25ee5b) SHA1(58117e11fd6478c521fbd3fdbe157f39567552f0) )
2004	2004
2005		DISK_REGION( "ide:0:hdd" )
	2005	DISK_REGION( "ide:0:hdd:image" )
2006	2006	DISK_IMAGE( "area51mx", 0, SHA1(5ff10f4e87094d4449eabf3de7549564ca568c7e) )
2007	2007	ROM_END
2008	2008
r23786	r23787
2017	2017	ROM_REGION16_BE( 0x1000, "waverom", 0 )
2018	2018	ROM_LOAD16_WORD("jagwave.rom", 0x0000, 0x1000, CRC(7a25ee5b) SHA1(58117e11fd6478c521fbd3fdbe157f39567552f0) )
2019	2019
2020		DISK_REGION( "ide:0:hdd" )
	2020	DISK_REGION( "ide:0:hdd:image" )
2021	2021	DISK_IMAGE( "vcircle", 0, SHA1(bfa79c4cacdc9c2cd6362f62a23056b3e35a2034) )
2022	2022	ROM_END
2023	2023

trunk/src/mame/drivers/quakeat.c

r23786	r23787
92	92	static ADDRESS_MAP_START( quake_io, AS_IO, 32, quakeat_state )
93	93	AM_IMPORT_FROM(pcat32_io_common)
94	94	AM_RANGE(0x00e8, 0x00eb) AM_NOP
95		//  AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
	95	//  AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
96	96	AM_RANGE(0x0300, 0x03af) AM_NOP
97	97	AM_RANGE(0x03b0, 0x03df) AM_NOP
98	98	//  AM_RANGE(0x0278, 0x027b) AM_WRITE(pnp_config_w)
99		//  AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
	99	//  AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
100	100	//  AM_RANGE(0x0a78, 0x0a7b) AM_WRITE(pnp_data_w)
101	101	//  AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_device, read, write)
102	102	ADDRESS_MAP_END

trunk/src/mame/drivers/twinkle.c

r23786	r23787
235	235	#include "machine/am53cf96.h"
236	236	#include "machine/rtc65271.h"
237	237	#include "machine/i2cmem.h"
238		#include "machine/idectrl.h"
	238	#include "machine/ataintf.h"
239	239	#include "sound/spu.h"
240	240	#include "sound/cdda.h"
241	241	#include "sound/rf5c400.h"
r23786	r23787
713	713	// 250000 = write to initiate DMA?
714	714	// 260000 = ???
715	715	AM_RANGE(0x280000, 0x280fff) AM_READWRITE(shared_68k_r, shared_68k_w )
716		AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE("ide", ide_controller_device, read_cs0, write_cs0)
	716	AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE("ata", ata_interface_device, read_cs0, write_cs0)
717	717	// 34000E = ???
718	718	AM_RANGE(0x400000, 0x400fff) AM_DEVREADWRITE("rfsnd", rf5c400_device, rf5c400_r, rf5c400_w)
719	719	AM_RANGE(0x800000, 0xffffff) AM_READWRITE(twinkle_waveram_r, twinkle_waveram_w )    // 8 MB window wave RAM
r23786	r23787
839	839	MCFG_AM53CF96_ADD("scsi:am53cf96")
840	840	MCFG_AM53CF96_IRQ_HANDLER(DEVWRITELINE("^maincpu:irq", psxirq_device, intin10))
841	841
842		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
843		MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(twinkle_state, ide_interrupt))
	842	MCFG_ATA_INTERFACE_ADD("ata", ata_devices, "hdd", NULL, true)
	843	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(twinkle_state, ide_interrupt))
844	844
845	845	MCFG_RTC65271_ADD("rtc", twinkle_rtc)
846	846
r23786	r23787
939	939	DISK_REGION( "cdrom1" ) // video CD
940	940	DISK_IMAGE_READONLY("863jaa04", 0, BAD_DUMP SHA1(8f6a0d2e191153032c9388b5298d8ee531b22a41) )
941	941
942		DISK_REGION( "ide:0:hdd" )
	942	DISK_REGION( "ata:0:hdd:image" )
943	943	DISK_IMAGE_READONLY("c44jaa03", 0, SHA1(53e9bd25d1674a04aeec81c0224b4e4e44af802a) ) // was part of a 1st mix machine, but "c44" indicates 8th mix?
944	944	ROM_END
945	945
r23786	r23787
955	955	DISK_REGION( "cdrom1" ) // video CD
956	956	DISK_IMAGE_READONLY( "985jaa02", 0, NO_DUMP )
957	957
958		DISK_REGION( "ide:0:hdd" )
	958	DISK_REGION( "ata:0:hdd:image" )
959	959	DISK_IMAGE_READONLY( "985jaahd", 0, NO_DUMP )
960	960	ROM_END
961	961
r23786	r23787
971	971	DISK_REGION( "cdrom1" ) // video CD
972	972	DISK_IMAGE_READONLY( "992jaa02", 0, NO_DUMP )
973	973
974		DISK_REGION( "ide:0:hdd" )
	974	DISK_REGION( "ata:0:hdd:image" )
975	975	DISK_IMAGE_READONLY( "992jaahd", 0, NO_DUMP )
976	976	ROM_END
977	977
r23786	r23787
987	987	DISK_REGION( "cdrom1" ) // video CD
988	988	DISK_IMAGE_READONLY( "a03jaa02", 0, NO_DUMP )
989	989
990		DISK_REGION( "ide:0:hdd" )
	990	DISK_REGION( "ata:0:hdd:image" )
991	991	DISK_IMAGE_READONLY( "a03jaahd", 0, NO_DUMP )
992	992	ROM_END
993	993
r23786	r23787
1003	1003	DISK_REGION( "cdrom1" ) // DVD
1004	1004	DISK_IMAGE_READONLY( "b4ujaa02", 0, NO_DUMP )
1005	1005
1006		DISK_REGION( "ide:0:hdd" )
	1006	DISK_REGION( "ata:0:hdd:image" )
1007	1007	DISK_IMAGE_READONLY( "b4ujaahd", 0, NO_DUMP )
1008	1008	ROM_END
1009	1009
r23786	r23787
1019	1019	DISK_REGION( "cdrom1" ) // DVD
1020	1020	DISK_IMAGE_READONLY( "b44jaa02", 0, NO_DUMP )
1021	1021
1022		DISK_REGION( "ide:0:hdd" )
	1022	DISK_REGION( "ata:0:hdd:image" )
1023	1023	DISK_IMAGE_READONLY( "b44jaahd", 0, NO_DUMP )
1024	1024	ROM_END
1025	1025
r23786	r23787
1035	1035	DISK_REGION( "cdrom1" ) // DVD
1036	1036	DISK_IMAGE_READONLY( "c44jaa02", 0, NO_DUMP )
1037	1037
1038		DISK_REGION( "ide:0:hdd" )
	1038	DISK_REGION( "ata:0:hdd:image" )
1039	1039	DISK_IMAGE_READONLY( "c44jaahd", 0, NO_DUMP )
1040	1040	ROM_END
1041	1041
r23786	r23787
1051	1051	DISK_REGION( "cdrom1" ) // video CD
1052	1052	DISK_IMAGE_READONLY( "abmjaa02", 0, NO_DUMP )
1053	1053
1054		DISK_REGION( "ide:0:hdd" )
	1054	DISK_REGION( "ata:0:hdd:image" )
1055	1055	DISK_IMAGE_READONLY( "abmjaahd", 0, NO_DUMP )
1056	1056	ROM_END
1057	1057
r23786	r23787
1067	1067	DISK_REGION( "cdrom1" ) // video CD
1068	1068	DISK_IMAGE_READONLY( "abmjaa02", 0, NO_DUMP )
1069	1069
1070		DISK_REGION( "ide:0:hdd" )
	1070	DISK_REGION( "ata:0:hdd:image" )
1071	1071	DISK_IMAGE_READONLY( "abmjaahd", 0, NO_DUMP )
1072	1072	ROM_END
1073	1073
r23786	r23787
1083	1083	DISK_REGION( "cdrom1" ) // video CD
1084	1084	DISK_IMAGE_READONLY( "abmjaa02", 0, NO_DUMP )
1085	1085
1086		DISK_REGION( "ide:0:hdd" )
	1086	DISK_REGION( "ata:0:hdd:image" )
1087	1087	DISK_IMAGE_READONLY( "abmjaahd", 0, NO_DUMP )
1088	1088	ROM_END
1089	1089

trunk/src/mame/drivers/vegas.c

r23786	r23787
1462	1462
1463	1463	UINT32 data = 0;
1464	1464	if (ACCESSING_BITS_0_15)
1465		data |= ide->read_cs0_pc(space, offset * 2, mem_mask);
	1465	data |= ide->read_cs0(space, offset * 2, mem_mask);
1466	1466	if (ACCESSING_BITS_16_31)
1467		data |= ide->read_cs0_pc(space, (offset * 2) + 1, mem_mask >> 16) << 16;
	1467	data |= ide->read_cs0(space, (offset * 2) + 1, mem_mask >> 16) << 16;
1468	1468
1469	1469	return data;
1470	1470	}
r23786	r23787
1475	1475	bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1476	1476
1477	1477	if (ACCESSING_BITS_0_15)
1478		ide->write_cs0_pc(space, offset * 2, data, mem_mask);
	1478	ide->write_cs0(space, offset * 2, data, mem_mask);
1479	1479	if (ACCESSING_BITS_16_31)
1480		ide->write_cs0_pc(space, (offset * 2) + 1, data >> 16, mem_mask >> 16);
	1480	ide->write_cs0(space, (offset * 2) + 1, data >> 16, mem_mask >> 16);
1481	1481	}
1482	1482
1483	1483
r23786	r23787
1487	1487
1488	1488	UINT32 data = 0;
1489	1489	if (ACCESSING_BITS_0_15)
1490		data |= ide->read_cs1_pc(space, (4/2) + (offset * 2), mem_mask);
	1490	data |= ide->read_cs1(space, (4/2) + (offset * 2), mem_mask);
1491	1491	if (ACCESSING_BITS_16_31)
1492		data |= ide->read_cs1_pc(space, (4/2) + (offset * 2) + 1, mem_mask >> 16) << 16;
	1492	data |= ide->read_cs1(space, (4/2) + (offset * 2) + 1, mem_mask >> 16) << 16;
1493	1493
1494	1494	return data;
1495	1495	}
r23786	r23787
1500	1500	bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1501	1501
1502	1502	if (ACCESSING_BITS_0_15)
1503		ide->write_cs1_pc(space, 6/2 + offset * 2, data, mem_mask);
	1503	ide->write_cs1(space, 6/2 + offset * 2, data, mem_mask);
1504	1504	if (ACCESSING_BITS_16_31)
1505		ide->write_cs1_pc(space, 6/2 + (offset * 2) + 1, data >> 16, mem_mask >> 16);
	1505	ide->write_cs1(space, 6/2 + (offset * 2) + 1, data >> 16, mem_mask >> 16);
1506	1506	}
1507	1507
1508	1508
r23786	r23787
2279	2279
2280	2280	MCFG_M48T37_ADD("timekeeper")
2281	2281
2282		MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
2283		MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(vegas_state, ide_interrupt))
	2282	MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	2283	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(vegas_state, ide_interrupt))
2284	2284	MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE("maincpu", AS_PROGRAM)
2285	2285
2286	2286	MCFG_SMC91C94_ADD("ethernet", ethernet_intf)
r23786	r23787
2371	2371	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* EPROM 1.5 11/17/1998 */
2372	2372	ROM_LOAD( "legend15.bin", 0x000000, 0x80000, CRC(a8372d70) SHA1(d8cd4fd4d7007ee38bb58b5a818d0f83043d5a48) )
2373	2373
2374		DISK_REGION( "ide:0:hdd" )    /* Guts 1.5 1/14/1999 Game 1/14/1999 */
	2374	DISK_REGION( "ide:0:hdd:image" )    /* Guts 1.5 1/14/1999 Game 1/14/1999 */
2375	2375	DISK_IMAGE( "gauntleg", 0, SHA1(66eb70e2fba574a7abe54be8bd45310654b24b08) )
2376	2376
2377	2377	ROM_REGION16_LE( 0x10000, "dcs", 0 )    /* Vegas SIO boot ROM */
r23786	r23787
2383	2383	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* EPROM 1.3 9/25/1998 */
2384	2384	ROM_LOAD( "legend12.bin", 0x000000, 0x80000, CRC(34674c5f) SHA1(92ec1779f3ab32944cbd953b6e1889503a57794b) )
2385	2385
2386		DISK_REGION( "ide:0:hdd" )    /* Guts 1.4 10/22/1998 Main 10/23/1998 */
	2386	DISK_REGION( "ide:0:hdd:image" )    /* Guts 1.4 10/22/1998 Main 10/23/1998 */
2387	2387	DISK_IMAGE( "gauntl12", 0, SHA1(c8208e3ce3b02a271dc6b089efa98dd996b66ce0) )
2388	2388
2389	2389	ROM_REGION16_LE( 0x10000, "dcs", 0 )    /* Vegas SIO boot ROM */
r23786	r23787
2395	2395	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* EPROM 1.7 12/14/1999 */
2396	2396	ROM_LOAD( "gauntdl.bin", 0x000000, 0x80000, CRC(3d631518) SHA1(d7f5a3bc109a19c9c7a711d607ff87e11868b536) )
2397	2397
2398		DISK_REGION( "ide:0:hdd" )    /* Guts: 1.9 3/17/2000 Game 5/9/2000 */
	2398	DISK_REGION( "ide:0:hdd:image" )    /* Guts: 1.9 3/17/2000 Game 5/9/2000 */
2399	2399	DISK_IMAGE( "gauntdl", 0, SHA1(ba3af48171e727c2f7232c06dcf8411cbcf14de8) )
2400	2400
2401	2401	ROM_REGION16_LE( 0x10000, "dcs", 0 )    /* Vegas SIO boot ROM */
r23786	r23787
2407	2407	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* EPROM 1.7 12/14/1999 */
2408	2408	ROM_LOAD( "gauntdl.bin", 0x000000, 0x80000, CRC(3d631518) SHA1(d7f5a3bc109a19c9c7a711d607ff87e11868b536) )
2409	2409
2410		DISK_REGION( "ide:0:hdd" )    /* Guts: 1.9 3/17/2000 Game 3/19/2000 */
	2410	DISK_REGION( "ide:0:hdd:image" )    /* Guts: 1.9 3/17/2000 Game 3/19/2000 */
2411	2411	DISK_IMAGE( "gauntd24", 0, SHA1(3e055794d23d62680732e906cfaf9154765de698) )
2412	2412
2413	2413	ROM_REGION16_LE( 0x10000, "dcs", 0 )    /* Vegas SIO boot ROM */
r23786	r23787
2419	2419	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* EPROM 1.9 3/25/1999 */
2420	2420	ROM_LOAD( "warboot.v19", 0x000000, 0x80000, CRC(b0c095cd) SHA1(d3b8cccdca83f0ecb49aa7993864cfdaa4e5c6f0) )
2421	2421
2422		DISK_REGION( "ide:0:hdd" )    /* Guts 1.3 4/20/1999 Game 4/20/1999 */
	2422	DISK_REGION( "ide:0:hdd:image" )    /* Guts 1.3 4/20/1999 Game 4/20/1999 */
2423	2423	DISK_IMAGE( "warfa", 0, SHA1(87f8a8878cd6be716dbd6c68fb1bc7f564ede484) )
2424	2424
2425	2425	ROM_REGION16_LE( 0x10000, "dcs", 0 )    /* Vegas SIO boot ROM */
r23786	r23787
2431	2431	ROM_REGION32_LE( 0x80000, "user1", 0 )
2432	2432	ROM_LOAD( "tenthdeg.bio", 0x000000, 0x80000, CRC(1cd2191b) SHA1(a40c48f3d6a9e2760cec809a79a35abe762da9ce) )
2433	2433
2434		DISK_REGION( "ide:0:hdd" )    /* Guts 5/26/1998 Main 8/25/1998 */
	2434	DISK_REGION( "ide:0:hdd:image" )    /* Guts 5/26/1998 Main 8/25/1998 */
2435	2435	DISK_IMAGE( "tenthdeg", 0, SHA1(41a1a045a2d118cf6235be2cc40bf16dbb8be5d1) )
2436	2436
2437	2437	ROM_REGION16_LE( 0x10000, "dcs", 0 )    /* Vegas SIO boot ROM */
r23786	r23787
2443	2443	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* EPROM 2.6 4/22/1999 */
2444	2444	ROM_LOAD( "rbmain.bin", 0x000000, 0x80000, CRC(060e1aa8) SHA1(2a1027d209f87249fe143500e721dfde7fb5f3bc) )
2445	2445
2446		DISK_REGION( "ide:0:hdd" )    /* Guts 4/22/1999 Game 4/22/1999 */
	2446	DISK_REGION( "ide:0:hdd:image" )    /* Guts 4/22/1999 Game 4/22/1999 */
2447	2447	DISK_IMAGE( "roadburn", 0, SHA1(a62870cceafa6357d7d3505aca250c3f16087566) )
2448	2448	ROM_END
2449	2449
r23786	r23787
2452	2452	ROM_REGION32_LE( 0x80000, "user1", 0 )
2453	2453	ROM_LOAD( "nbau27.100", 0x000000, 0x80000, CRC(ff5d620d) SHA1(8f07567929f40a2269a42495dfa9dd5edef688fe) )
2454	2454
2455		DISK_REGION( "ide:0:hdd" )
	2455	DISK_REGION( "ide:0:hdd:image" )
2456	2456	DISK_IMAGE( "nbashowt", 0, SHA1(f7c56bc3dcbebc434de58034986179ae01127f87) )
2457	2457
2458	2458	ROM_REGION16_LE( 0x10000, "dcs", 0 )    /* Vegas SIO boot ROM */
r23786	r23787
2465	2465	ROM_LOAD( "u27nflnba.bin", 0x000000, 0x80000, CRC(6a9bd382) SHA1(18b942df6af86ea944c24166dbe88148334eaff9) )
2466	2466	//  ROM_LOAD( "bootnflnba.bin", 0x000000, 0x80000, CRC(3def7053) SHA1(8f07567929f40a2269a42495dfa9dd5edef688fe) )
2467	2467
2468		DISK_REGION( "ide:0:hdd" )
	2468	DISK_REGION( "ide:0:hdd:image" )
2469	2469	DISK_IMAGE( "nbanfl", 0, SHA1(f60c627f85f1bf58f2ea674063736a1e516e7e9e) )
2470	2470
2471	2471	ROM_REGION16_LE( 0x10000, "dcs", 0 )    /* Vegas SIO boot ROM */
r23786	r23787
2477	2477	ROM_REGION32_LE( 0x80000, "user1", 0 )
2478	2478	ROM_LOAD( "bootu27", 0x000000, 0x80000, CRC(c44550a2) SHA1(ad30f1c3382ff2f5902a4cbacbb1f0c4e37f42f9) )
2479	2479
2480		DISK_REGION( "ide:0:hdd" )
	2480	DISK_REGION( "ide:0:hdd:image" )
2481	2481	DISK_IMAGE( "cartfury", 0, SHA1(4c5bc2803297ea9a191bbd8b002d0e46b4ae1563) )
2482	2482
2483	2483	ROM_REGION16_LE( 0x10000, "dcs", 0 )    /* ADSP-2105 data */
r23786	r23787
2489	2489	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* EPROM 1.02 7/9/1999 */
2490	2490	ROM_LOAD( "sf2049.u27", 0x000000, 0x80000, CRC(174ba8fe) SHA1(baba83b811eca659f00514a008a86ef0ac9680ee) )
2491	2491
2492		DISK_REGION( "ide:0:hdd" )    /* Guts 1.03 9/3/1999 Game 9/8/1999 */
	2492	DISK_REGION( "ide:0:hdd:image" )    /* Guts 1.03 9/3/1999 Game 9/8/1999 */
2493	2493	DISK_IMAGE( "sf2049", 0, SHA1(9e0661b8566a6c78d18c59c11cd3a6628d025405) )
2494	2494	ROM_END
2495	2495
r23786	r23787
2498	2498	ROM_REGION32_LE( 0x80000, "user1", 0 )
2499	2499	ROM_LOAD( "sf2049se.u27", 0x000000, 0x80000, CRC(da4ecd9c) SHA1(2574ff3d608ebcc59a63cf6dea13ee7650ae8921) )
2500	2500
2501		DISK_REGION( "ide:0:hdd" )
	2501	DISK_REGION( "ide:0:hdd:image" )
2502	2502	DISK_IMAGE( "sf2049se", 0, SHA1(7b27a8ce2a953050ce267548bb7160b41f3e8054) )
2503	2503	ROM_END
2504	2504
r23786	r23787
2507	2507	ROM_REGION32_LE( 0x80000, "user1", 0 )
2508	2508	ROM_LOAD( "sf2049te.u27", 0x000000, 0x80000, CRC(cc7c8601) SHA1(3f37dbd1b32b3ac5caa300725468e8e426f0fb83) )
2509	2509
2510		DISK_REGION( "ide:0:hdd" )
	2510	DISK_REGION( "ide:0:hdd:image" )
2511	2511	DISK_IMAGE( "sf2049te", 0, SHA1(625aa36436587b7bec3e7db1d19793b760e2ea51) )
2512	2512	ROM_END
2513	2513

trunk/src/mame/drivers/qdrmfgp.c

r23786	r23787
23	23
24	24	#include "emu.h"
25	25	#include "cpu/m68000/m68000.h"
26		#include "machine/idectrl.h"
	26	#include "machine/ataintf.h"
27	27	#include "sound/k054539.h"
28	28	#include "video/konicdev.h"
29	29	#include "machine/k053252.h"
r23786	r23787
199	199	}
200	200	}
201	201
202		return m_ide->read_cs0(space, offset, mem_mask);
	202	return m_ata->read_cs0(space, offset, mem_mask);
203	203	}
204	204
205	205
r23786	r23787
291	291	AM_RANGE(0x880000, 0x881fff) AM_DEVREADWRITE_LEGACY("k056832", k056832_ram_word_r, k056832_ram_word_w)          /* vram */
292	292	AM_RANGE(0x882000, 0x883fff) AM_DEVREADWRITE_LEGACY("k056832", k056832_ram_word_r, k056832_ram_word_w)          /* vram (mirror) */
293	293	AM_RANGE(0x900000, 0x901fff) AM_READ(v_rom_r)                                               /* gfxrom through */
294		AM_RANGE(0xa00000, 0xa0000f) AM_DEVREADWRITE("ide", ide_controller_device, read_cs0, write_cs0) /* IDE control regs */
295		AM_RANGE(0xa40000, 0xa4000f) AM_DEVREADWRITE("ide", ide_controller_device, read_cs1, write_cs1) /* IDE status control reg */
	294	AM_RANGE(0xa00000, 0xa0000f) AM_DEVREADWRITE("ata", ata_interface_device, read_cs0, write_cs0) /* IDE control regs */
	295	AM_RANGE(0xa40000, 0xa4000f) AM_DEVREADWRITE("ata", ata_interface_device, read_cs1, write_cs1) /* IDE status control reg */
296	296	AM_RANGE(0xc00000, 0xcbffff) AM_READWRITE(sndram_r, sndram_w)                               /* sound ram */
297	297	ADDRESS_MAP_END
298	298
r23786	r23787
314	314	AM_RANGE(0x880000, 0x881fff) AM_READWRITE(gp2_vram_r, gp2_vram_w)                           /* vram */
315	315	AM_RANGE(0x89f000, 0x8a0fff) AM_READWRITE(gp2_vram_mirror_r, gp2_vram_mirror_w)             /* vram (mirror) */
316	316	AM_RANGE(0x900000, 0x901fff) AM_READ(v_rom_r)                                               /* gfxrom through */
317		AM_RANGE(0xa00000, 0xa0000f) AM_READ(gp2_ide_std_r) AM_DEVWRITE("ide", ide_controller_device, write_cs0) /* IDE control regs */
318		AM_RANGE(0xa40000, 0xa4000f) AM_DEVREADWRITE("ide", ide_controller_device, read_cs1, write_cs1) /* IDE status control reg */
	317	AM_RANGE(0xa00000, 0xa0000f) AM_READ(gp2_ide_std_r) AM_DEVWRITE("ata", ata_interface_device, write_cs0) /* IDE control regs */
	318	AM_RANGE(0xa40000, 0xa4000f) AM_DEVREADWRITE("ata", ata_interface_device, read_cs1, write_cs1) /* IDE status control reg */
319	319	AM_RANGE(0xc00000, 0xcbffff) AM_READWRITE(sndram_r,sndram_w)                                /* sound ram */
320	320	ADDRESS_MAP_END
321	321
r23786	r23787
596	596
597	597	/* reset the IDE controller */
598	598	m_gp2_irq_control = 0;
599		m_ide->reset();
600	599	}
601	600
602	601
r23786	r23787
615	614	MCFG_MACHINE_START_OVERRIDE(qdrmfgp_state,qdrmfgp)
616	615	MCFG_NVRAM_ADD_1FILL("nvram")
617	616
618		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
619		MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(qdrmfgp_state, ide_interrupt))
	617	MCFG_ATA_INTERFACE_ADD("ata", ata_devices, "hdd", NULL, true)
	618	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(qdrmfgp_state, ide_interrupt))
620	619
621	620	/* video hardware */
622	621	MCFG_SCREEN_ADD("screen", RASTER)
r23786	r23787
651	650	MCFG_MACHINE_START_OVERRIDE(qdrmfgp_state,qdrmfgp2)
652	651	MCFG_NVRAM_ADD_1FILL("nvram")
653	652
654		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
655		MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(qdrmfgp_state, gp2_ide_interrupt))
	653	MCFG_ATA_INTERFACE_ADD("ata", ata_devices, "hdd", NULL, true)
	654	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(qdrmfgp_state, gp2_ide_interrupt))
656	655
657	656	/* video hardware */
658	657	MCFG_SCREEN_ADD("screen", RASTER)
r23786	r23787
697	696	ROM_LOAD( "gq_460_a07.14h", 0x000000, 0x80000, CRC(67d8ea6b) SHA1(11af1b5a33de2a6e24823964d210bef193ecefe4) )
698	697	ROM_LOAD( "gq_460_a06.12h", 0x080000, 0x80000, CRC(97ed5a77) SHA1(68600fd8d914451284cf181fb4bd5872860fb9ad) )
699	698
700		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	699	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
701	700	DISK_IMAGE( "gq460a08", 0, SHA1(2f142f986fa3c79d5c4102e800980d1706c35f75) )
702	701	ROM_END
703	702
r23786	r23787
714	713	ROM_LOAD( "ge_557_a07.19h", 0x000000, 0x80000, CRC(7491e0c8) SHA1(6459ab5e7af052ef7a1c4ce01cd844c0f4319f2e) )
715	714	ROM_LOAD( "ge_557_a08.19k", 0x080000, 0x80000, CRC(3da2b20c) SHA1(fdc2cdc27f3299f541944a78ce36ed33a7926056) )
716	715
717		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	716	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
718	717	DISK_IMAGE( "ge557a09", 0, SHA1(1ef8093b542fe0bf8240a5fd64e5af3839b6a04c) )
719	718	ROM_END
720	719

trunk/src/mame/drivers/djmain.c

r23786	r23787
65	65
66	66	#include "emu.h"
67	67	#include "cpu/m68000/m68000.h"
68		#include "machine/idectrl.h"
	68	#include "machine/ataintf.h"
69	69	#include "sound/k054539.h"
70	70	#include "video/konicdev.h"
71	71	#include "includes/djmain.h"
r23786	r23787
416	416	AM_RANGE(0x803800, 0x803fff) AM_READ(obj_rom_r)                     // OBJECT ROM readthrough (for POST)
417	417	AM_RANGE(0xc00000, 0xc01fff) AM_DEVREADWRITE_LEGACY("k056832", k056832_ram_long_r, k056832_ram_long_w)  // VIDEO RAM (tilemap) (beatmania)
418	418	AM_RANGE(0xc02000, 0xc02047) AM_WRITE(unknownc02000_w)                  // ??
419		AM_RANGE(0xd00000, 0xd0000f) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff) // IDE control regs (hiphopmania)
420		AM_RANGE(0xd40000, 0xd4000f) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff) // IDE status control reg (hiphopmania)
	419	AM_RANGE(0xd00000, 0xd0000f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs0, write_cs0, 0xffffffff) // IDE control regs (hiphopmania)
	420	AM_RANGE(0xd40000, 0xd4000f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs1, write_cs1, 0xffffffff) // IDE status control reg (hiphopmania)
421	421	AM_RANGE(0xe00000, 0xe01fff) AM_DEVREADWRITE_LEGACY("k056832", k056832_ram_long_r, k056832_ram_long_w)  // VIDEO RAM (tilemap) (hiphopmania)
422		AM_RANGE(0xf00000, 0xf0000f) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff) // IDE control regs (beatmania)
423		AM_RANGE(0xf40000, 0xf4000f) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff) // IDE status control reg (beatmania)
	422	AM_RANGE(0xf00000, 0xf0000f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs0, write_cs0, 0xffffffff) // IDE control regs (beatmania)
	423	AM_RANGE(0xf40000, 0xf4000f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs1, write_cs1, 0xffffffff) // IDE status control reg (beatmania)
424	424	ADDRESS_MAP_END
425	425
426	426
r23786	r23787
1354	1354
1355	1355	void djmain_state::machine_start()
1356	1356	{
1357		if (m_ide_master_password != NULL)
1358		m_ide->ide_set_master_password(0, m_ide_master_password);
1359		if (m_ide_user_password != NULL)
1360		m_ide->ide_set_user_password(0, m_ide_user_password);
	1357	if (m_ata_master_password != NULL)
	1358	m_ata->set_master_password(0, m_ata_master_password);
	1359	if (m_ata_user_password != NULL)
	1360	m_ata->set_user_password(0, m_ata_user_password);
1361	1361
1362	1362	save_item(NAME(m_sndram_bank));
1363	1363	save_item(NAME(m_pending_vb_int));
r23786	r23787
1374	1374	m_sndram_bank = 0;
1375	1375	sndram_set_bank();
1376	1376
1377		/* reset the IDE controller */
1378		m_ide->reset();
1379
1380	1377	/* reset LEDs */
1381	1378	set_led_status(machine(), 0, 1);
1382	1379	set_led_status(machine(), 1, 1);
r23786	r23787
1410	1407	MCFG_CPU_VBLANK_INT_DRIVER("screen", djmain_state,  vb_interrupt)
1411	1408
1412	1409
1413		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
1414		MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(djmain_state, ide_interrupt))
	1410	MCFG_ATA_INTERFACE_ADD("ata", ata_devices, "hdd", NULL, true)
	1411	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(djmain_state, ide_interrupt))
1415	1412
1416	1413	/* video hardware */
1417	1414	MCFG_SCREEN_ADD("screen", RASTER)
r23786	r23787
1466	1463	ROM_LOAD16_BYTE( "753jaa09.25d", 0x100000, 0x80000, CRC(B50C3DBB) SHA1(6022ea249aad0793b2279699e68087b4bc9b4ef1) )
1467	1464	ROM_LOAD16_BYTE( "753jaa10.27d", 0x100001, 0x80000, CRC(391F4BFD) SHA1(791c9889ea3ce639bbfb87934a1cad9aa3c9ccde) )
1468	1465
1469		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1466	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1470	1467	DISK_IMAGE( "753jaa11", 0, SHA1(2e70cf31a853322f29f99b6f292c187a2cf33015) ) /* ver 1.00 JA */
1471	1468	// There is an alternate image
1472	1469	//DISK_IMAGE( "753jaa11", 0, MD5(260c9b72f4a03055e3abad61c6225324) SHA1(2cc3e149744516bf2353a2b47d33bc9d2072b6c4) ) /* ver 1.00 JA */
r23786	r23787
1491	1488	ROM_LOAD16_BYTE( "853jaa09.25d", 0x100000, 0x80000, CRC(8584E21E) SHA1(3d1ca6de00f9ac07bbe7cd1e67093cca7bf484bb) )
1492	1489	ROM_LOAD16_BYTE( "853jaa10.27d", 0x100001, 0x80000, CRC(9CB92D98) SHA1(6ace4492ba0b5a8f94a9e7b4f7126b31c6254637) )
1493	1490
1494		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1491	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1495	1492	DISK_IMAGE( "853jaa11", 0, SHA1(9683ff8462491252b6eb2e5b3aa6496884c01506) ) /* ver 1.10 JA */
1496	1493
1497	1494	ROM_REGION( 0x1000000, "shared", ROMREGION_ERASE00 )        /* K054539 RAM */
r23786	r23787
1514	1511	ROM_LOAD16_BYTE( "853jaa09.25d", 0x100000, 0x80000, CRC(8584E21E) SHA1(3d1ca6de00f9ac07bbe7cd1e67093cca7bf484bb) )
1515	1512	ROM_LOAD16_BYTE( "853jaa10.27d", 0x100001, 0x80000, CRC(9CB92D98) SHA1(6ace4492ba0b5a8f94a9e7b4f7126b31c6254637) )
1516	1513
1517		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1514	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1518	1515	DISK_IMAGE( "853jaa11", 0, SHA1(9683ff8462491252b6eb2e5b3aa6496884c01506) ) /* ver 1.10 JA */
1519	1516
1520	1517	ROM_REGION( 0x1000000, "shared", ROMREGION_ERASE00 )        /* K054539 RAM */
r23786	r23787
1537	1534	ROM_LOAD16_BYTE( "825jaa09.25d", 0x100000, 0x80000, CRC(D3E65669) SHA1(51abf452da60794fa47c05d11c08b203dde563ff) )
1538	1535	ROM_LOAD16_BYTE( "825jaa10.27d", 0x100001, 0x80000, CRC(44D184F3) SHA1(28f3ec33a29164a6531f53db071272ccf015f66d) )
1539	1536
1540		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1537	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1541	1538	DISK_IMAGE( "825jaa11", 0, SHA1(048919977232bbce046406a7212586cf39b77cf2) ) /* ver 1.00 JA */
1542	1539
1543	1540	ROM_REGION( 0x1000000, "shared", ROMREGION_ERASE00 )        /* K054539 RAM */
r23786	r23787
1560	1557	ROM_LOAD16_BYTE( "858jaa09.25d", 0x100000, 0x80000, CRC(0B4AD843) SHA1(c01e15053dd1975dc68db9f4e6da47062d8f9b54) )
1561	1558	ROM_LOAD16_BYTE( "858jaa10.27d", 0x100001, 0x80000, CRC(00B124EE) SHA1(435d28a327c2707833a8ddfe841104df65ffa3f8) )
1562	1559
1563		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1560	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1564	1561	DISK_IMAGE( "858jaa11", 0, SHA1(bc590472046336a1000f29901fe3fd7b29747e47) ) /* ver 1.00 JA */
1565	1562
1566	1563	ROM_REGION( 0x1000000, "shared", ROMREGION_ERASE00 )        /* K054539 RAM */
r23786	r23787
1583	1580	ROM_LOAD16_BYTE( "858uaa09.25d", 0x100000, 0x80000, CRC(99519886) SHA1(664f6bd953201a6e2fc123cb8b3facf72766107d) )
1584	1581	ROM_LOAD16_BYTE( "858uaa10.27d", 0x100001, 0x80000, CRC(20AA7145) SHA1(eeff87eb9a9864985d751f45e843ee6e73db8cfd) )
1585	1582
1586		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1583	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1587	1584	DISK_IMAGE( "858jaa11", 0, SHA1(bc590472046336a1000f29901fe3fd7b29747e47) ) /* ver 1.00 JA */
1588	1585
1589	1586	ROM_REGION( 0x1000000, "shared", ROMREGION_ERASE00 )        /* K054539 RAM */
r23786	r23787
1606	1603	ROM_LOAD16_BYTE( "847jab09.25d", 0x100000, 0x80000, CRC(2E4AC9FE) SHA1(bbd4c6e0c82fc0be88f851e901e5853b6bcf775f) )
1607	1604	ROM_LOAD16_BYTE( "847jab10.27d", 0x100001, 0x80000, CRC(C78516F5) SHA1(1adf5805c808dc55de14a9a9b20c3d2cf7bf414d) )
1608	1605
1609		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1606	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1610	1607	DISK_IMAGE( "847jaa11", 0, SHA1(8cad631531b5616d6a4b0a99d988f4b525932dc7) ) /* ver 1.00 JA */
1611	1608
1612	1609	ROM_REGION( 0x1000000, "shared", ROMREGION_ERASE00 )        /* K054539 RAM */
r23786	r23787
1629	1626	ROM_LOAD16_BYTE( "981jaa09.25d", 0x100000, 0x80000, CRC(D96D4E1C) SHA1(379aa4e82cd06490645f54dab1724c827108735d) )
1630	1627	ROM_LOAD16_BYTE( "981jaa10.27d", 0x100001, 0x80000, CRC(06BEE0E4) SHA1(6eea8614cb01e7079393b9976b6fd6a52c14e3c0) )
1631	1628
1632		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1629	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1633	1630	DISK_IMAGE( "981jaa11", 0, SHA1(dc7353fa436d96ae174a58d3a38ca9928a63727f) ) /* ver 1.00 JA */
1634	1631
1635	1632	ROM_REGION( 0x1000000, "shared", ROMREGION_ERASE00 )        /* K054539 RAM */
r23786	r23787
1652	1649	ROM_LOAD16_BYTE( "993jaa09.25d", 0x100000, 0x80000, CRC(E1A172DD) SHA1(42e850c055dc5bfccf6b6989f9f3a945fce13006) )
1653	1650	ROM_LOAD16_BYTE( "993jaa10.27d", 0x100001, 0x80000, CRC(9D113A2D) SHA1(eee94a5f7015c49aa630b8df0c8e9d137d238811) )
1654	1651
1655		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1652	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1656	1653	DISK_IMAGE( "993hdda01", 0, SHA1(f5d4df1dd27ce6ee2d0897852342691d55b63bfb) )
1657	1654	// this image has not been verified
1658	1655	//  DISK_IMAGE( "993jaa11", 0, MD5(e26eb62d7cf3357585f5066da6063143) )  /* ver 1.00 JA */
r23786	r23787
1677	1674	ROM_LOAD16_BYTE( "988jaa09.25d", 0x100000, 0x80000, CRC(8F3BAE7F) SHA1(c4dac14f6c7f75a2b19153e05bfe969e9eb4aca0) )
1678	1675	ROM_LOAD16_BYTE( "988jaa10.27d", 0x100001, 0x80000, CRC(248BF0EE) SHA1(d89205ed57e771401bfc2c24043d200ecbd0b7fc) )
1679	1676
1680		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1677	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1681	1678	DISK_IMAGE( "988jaa11", 0, SHA1(12a0988c631dd3331e54b8417a9659402afe168b) ) /* ver 1.00 JA */
1682	1679
1683	1680	ROM_REGION( 0x1000000, "shared", ROMREGION_ERASE00 )        /* K054539 RAM */
r23786	r23787
1700	1697	ROM_LOAD16_BYTE( "988uaa09.25d", 0x100000, 0x80000, CRC(C2AD6810) SHA1(706388c5acf6718297fd90e10f8a673463a0893b) )
1701	1698	ROM_LOAD16_BYTE( "988uaa10.27d", 0x100001, 0x80000, CRC(DAB0F3C9) SHA1(6fd899e753e32f60262c54ab8553c686c7ef28de) )
1702	1699
1703		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1700	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1704	1701	DISK_IMAGE( "988jaa11", 0, SHA1(12a0988c631dd3331e54b8417a9659402afe168b) ) /* ver 1.00 JA */
1705	1702
1706	1703	ROM_REGION( 0x1000000, "shared", ROMREGION_ERASE00 )        /* K054539 RAM */
r23786	r23787
1723	1720	ROM_LOAD16_BYTE( "995jaa09.25d", 0x100000, 0x80000, CRC(1510A9C2) SHA1(daf1ab26b7b6b0fe0123b3fbee68684157c2ce51) )
1724	1721	ROM_LOAD16_BYTE( "995jaa10.27d", 0x100001, 0x80000, CRC(F9E4E9F2) SHA1(fe91badf6b0baeea690d75399d8c66fabcf6d352) )
1725	1722
1726		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1723	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1727	1724	DISK_IMAGE( "995jaa11", 0, SHA1(8fec3c4d97f64f48b9867230a97cda4347496075) ) /* ver 1.00 JA */
1728	1725
1729	1726	ROM_REGION( 0x1000000, "shared", ROMREGION_ERASE00 )        /* K054539 RAM */
r23786	r23787
1746	1743	ROM_LOAD16_BYTE( "a05jaa09.25d", 0x100000, 0x80000, CRC(1504D62C) SHA1(3c31c6625bc089235a96fe21021239f2d0c0f6e1) )
1747	1744	ROM_LOAD16_BYTE( "a05jaa10.27d", 0x100001, 0x80000, CRC(99D75C36) SHA1(9599420863aa0a9492d3caeb03f8ac5fd4c3cdb2) )
1748	1745
1749		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1746	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1750	1747	DISK_IMAGE( "a05jaa11", 0, SHA1(7ebc41cc3e9a0a922b49201b34e29201522eb726) ) /* ver 1.00 JA */
1751	1748
1752	1749	ROM_REGION( 0x1000000, "shared", ROMREGION_ERASE00 )        /* K054539 RAM */
r23786	r23787
1769	1766	ROM_LOAD16_BYTE( "a21jaa09.25d", 0x100000, 0x80000, CRC(181E6F70) SHA1(82c7ca3068ace9a66b614ead4b90ea6fe4017d51) )
1770	1767	ROM_LOAD16_BYTE( "a21jaa10.27d", 0x100001, 0x80000, CRC(1AC33595) SHA1(3173bb8dc420487c4d427e779444a98aad37d51e) )
1771	1768
1772		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1769	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1773	1770	DISK_IMAGE( "a21jaa11", 0, SHA1(ed0a07212a360e75934fc22c56265842cf0829b6) ) /* ver 1.00 JA */
1774	1771
1775	1772	ROM_REGION( 0x1000000, "shared", ROMREGION_ERASE00 )        /* K054539 RAM */
r23786	r23787
1792	1789	ROM_LOAD16_BYTE( "b07jaa09.25d", 0x100000, 0x80000, CRC(2530CEDB) SHA1(94b38b4fe198b26a2ff4d99d2cb28a0f935fe940) )
1793	1790	ROM_LOAD16_BYTE( "b07jaa10.27d", 0x100001, 0x80000, CRC(6B75BA9C) SHA1(aee922adc3bc0296ae6e08e461b20a9e5e72a2df) )
1794	1791
1795		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1792	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1796	1793	DISK_IMAGE( "b07jaa11", 0, SHA1(e4925494f0a801abb4d3aa6524c379eb445d8dff) ) /* ver 1.00 JA */
1797	1794	// this image has not been verified
1798	1795	//DISK_IMAGE( "b07jab11", 0, MD5(0e9440787ca69567792095085e2a3619) )    /* ver 1.00 JA */
r23786	r23787
1817	1814	ROM_LOAD16_BYTE( "c01jaa09.25d", 0x100000, 0x80000, CRC(45CF93B1) SHA1(7c5082bcd1fe15761a0a965e25dda121904ff1bd) )
1818	1815	ROM_LOAD16_BYTE( "c01jaa10.27d", 0x100001, 0x80000, CRC(C9927749) SHA1(c2644877bda483e241381265e723ea8ab8357761) )
1819	1816
1820		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1817	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1821	1818	DISK_IMAGE( "c01jaa11", 0, SHA1(0a53c4412a72a886f5fb98c12c529d056d625244) ) /* ver 1.00 JA */
1822	1819	// this image has not been verified
1823	1820	//DISK_IMAGE( "c01jaa11", 0, MD5(8bb7e6b6bc63cac8a4f2997307c25748) )    /* ver 1.00 JA */
r23786	r23787
1842	1839	ROM_LOAD16_BYTE( "831jaa09.25d", 0x100000, 0x80000, CRC(AE7838D2) SHA1(4f8a6793065c6c1eb08161f65b1d6246987bf47e) )
1843	1840	ROM_LOAD16_BYTE( "831jaa10.27d", 0x100001, 0x80000, CRC(85173CB6) SHA1(bc4d86bf4654a9a0a58e624f77090854950f3993) )
1844	1841
1845		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1842	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1846	1843	DISK_IMAGE( "831jhdda01", 0, SHA1(ef62d5fcc1a36235fc932e6ecef71dc845d1d72d) )
1847	1844
1848	1845	ROM_REGION( 0x1000000, "shared", ROMREGION_ERASE00 )        /* K054539 RAM */
r23786	r23787
1867	1864	ROM_LOAD16_BYTE( "825jab09.25d", 0x100000, 0x80000, CRC(1407BA5D) SHA1(e7a0d190326589f4d94e83cb7c85dd4e91f4efad) )
1868	1865	ROM_LOAD16_BYTE( "825jab10.27d", 0x100001, 0x80000, CRC(2AFD0A10) SHA1(1b8b868ac5720bb1b376f4eb8952efb190257bda) )
1869	1866
1870		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1867	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1871	1868	DISK_IMAGE( "825jab11", 0, MD5(f4360da10a932ba90e93469df7426d1d) SHA1(1) )  /* ver 1.01 JA */
1872	1869
1873	1870	ROM_REGION( 0x1000000, "shared", ROMREGION_ERASE00 )        /* K054539 RAM */
r23786	r23787
1890	1887	ROM_LOAD16_BYTE( "803jaa09.25d", 0x100000, 0x80000, CRC(204D53EB) SHA1(349de147246b0ed08fb7e473d63e073b71fa30c9) )
1891	1888	ROM_LOAD16_BYTE( "803jaa10.27d", 0x100001, 0x80000, CRC(535A61A3) SHA1(b24c57601a7e3a349473af69114703133a46806d) )
1892	1889
1893		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1890	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1894	1891	DISK_IMAGE( "803jaa11", 0, MD5(54a8ac87857d81740621c622e27736d7) )  /* ver 1.00 JA */
1895	1892
1896	1893	ROM_REGION( 0x1000000, "shared", ROMREGION_ERASE00 )        /* K054539 RAM */
r23786	r23787
1913	1910	ROM_LOAD16_BYTE( "980jaa09.25d", 0x100000, 0x80000, CRC(1CB4D84E) SHA1(9669585c6a2825aeae6e47dd03458624b4c44721) )
1914	1911	ROM_LOAD16_BYTE( "980jaa10.27d", 0x100001, 0x80000, CRC(7776B87E) SHA1(662b7cd7cb4fb8f8bab240ef543bf9a593e23a03) )
1915	1912
1916		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1913	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1917	1914	DISK_IMAGE( "980jaa11", 0, MD5(6e5cc17a6bc75cac0256192cc700215c) )  /* ver 1.00 JA */
1918	1915
1919	1916	ROM_REGION( 0x1000000, "shared", ROMREGION_ERASE00 )        /* K054539 RAM */
r23786	r23787
1936	1933	ROM_LOAD16_BYTE( "970jba09.25d", 0x100000, 0x80000, CRC(5D2BDA52) SHA1(d03c135ac04437b54e4d267ae168fe7ebb9e5b65) )
1937	1934	ROM_LOAD16_BYTE( "970jba10.27d", 0x100001, 0x80000, CRC(EDC4A245) SHA1(30bbd7bf0299a064119c535abb9be69d725aa130) )
1938	1935
1939		DISK_REGION( "ide:0:hdd" )            /* IDE HARD DRIVE */
	1936	DISK_REGION( "ata:0:hdd:image" )            /* IDE HARD DRIVE */
1940	1937	DISK_IMAGE( "970jba11", 0, MD5(1616905838fdb2b521d53499c6c2a7a4) )  /* ver 1.00 JA */
1941	1938
1942	1939	ROM_REGION( 0x1000000, "shared", ROMREGION_ERASE00 )        /* K054539 RAM */
r23786	r23787
1951	1948
1952	1949	DRIVER_INIT_MEMBER(djmain_state,beatmania)
1953	1950	{
1954		m_ide_master_password = NULL;
1955		m_ide_user_password = NULL;
	1951	m_ata_master_password = NULL;
	1952	m_ata_user_password = NULL;
1956	1953	}
1957	1954
1958	1955	static const UINT8 beatmania_master_password[2 + 32] =
r23786	r23787
1977	1974
1978	1975	DRIVER_INIT_CALL(beatmania);
1979	1976
1980		m_ide_master_password = beatmania_master_password;
1981		m_ide_user_password = hmcompmx_user_password;
	1977	m_ata_master_password = beatmania_master_password;
	1978	m_ata_user_password = hmcompmx_user_password;
1982	1979	}
1983	1980
1984	1981	DRIVER_INIT_MEMBER(djmain_state,bm4thmix)
r23786	r23787
1994	1991
1995	1992	DRIVER_INIT_CALL(beatmania);
1996	1993
1997		m_ide_user_password = bm4thmix_user_password;
	1994	m_ata_user_password = bm4thmix_user_password;
1998	1995	}
1999	1996
2000	1997	DRIVER_INIT_MEMBER(djmain_state,bm5thmix)
r23786	r23787
2010	2007
2011	2008	DRIVER_INIT_CALL(beatmania);
2012	2009
2013		m_ide_master_password = beatmania_master_password;
2014		m_ide_user_password = bm5thmix_user_password;
	2010	m_ata_master_password = beatmania_master_password;
	2011	m_ata_user_password = bm5thmix_user_password;
2015	2012	}
2016	2013
2017	2014	DRIVER_INIT_MEMBER(djmain_state,bmclubmx)
r23786	r23787
2027	2024
2028	2025	DRIVER_INIT_CALL(beatmania);
2029	2026
2030		m_ide_master_password = beatmania_master_password;
2031		m_ide_user_password = bmclubmx_user_password;
	2027	m_ata_master_password = beatmania_master_password;
	2028	m_ata_user_password = bmclubmx_user_password;
2032	2029	}
2033	2030
2034	2031
r23786	r23787
2045	2042
2046	2043	DRIVER_INIT_CALL(beatmania);
2047	2044
2048		m_ide_master_password = beatmania_master_password;
2049		m_ide_user_password = bmcompm2_user_password;
	2045	m_ata_master_password = beatmania_master_password;
	2046	m_ata_user_password = bmcompm2_user_password;
2050	2047	}
2051	2048
2052	2049	DRIVER_INIT_MEMBER(djmain_state,hmcompm2)
r23786	r23787
2062	2059
2063	2060	DRIVER_INIT_CALL(beatmania);
2064	2061
2065		m_ide_master_password = beatmania_master_password;
2066		m_ide_user_password = hmcompm2_user_password;
	2062	m_ata_master_password = beatmania_master_password;
	2063	m_ata_user_password = hmcompm2_user_password;
2067	2064	}
2068	2065
2069	2066	DRIVER_INIT_MEMBER(djmain_state,bmdct)
r23786	r23787
2079	2076
2080	2077	DRIVER_INIT_CALL(beatmania);
2081	2078
2082		m_ide_master_password = beatmania_master_password;
2083		m_ide_user_password = bmdct_user_password;
	2079	m_ata_master_password = beatmania_master_password;
	2080	m_ata_user_password = bmdct_user_password;
2084	2081	}
2085	2082
2086	2083	DRIVER_INIT_MEMBER(djmain_state,bmcorerm)
r23786	r23787
2096	2093
2097	2094	DRIVER_INIT_CALL(beatmania);
2098	2095
2099		m_ide_master_password = beatmania_master_password;
2100		m_ide_user_password = bmcorerm_user_password;
	2096	m_ata_master_password = beatmania_master_password;
	2097	m_ata_user_password = bmcorerm_user_password;
2101	2098	}
2102	2099
2103	2100	DRIVER_INIT_MEMBER(djmain_state,bm6thmix)
r23786	r23787
2113	2110
2114	2111	DRIVER_INIT_CALL(beatmania);
2115	2112
2116		m_ide_master_password = beatmania_master_password;
2117		m_ide_user_password = bm6thmix_user_password;
	2113	m_ata_master_password = beatmania_master_password;
	2114	m_ata_user_password = bm6thmix_user_password;
2118	2115	}
2119	2116
2120	2117	DRIVER_INIT_MEMBER(djmain_state,bm7thmix)
r23786	r23787
2130	2127
2131	2128	DRIVER_INIT_CALL(beatmania);
2132	2129
2133		m_ide_master_password = beatmania_master_password;
2134		m_ide_user_password = bm7thmix_user_password;
	2130	m_ata_master_password = beatmania_master_password;
	2131	m_ata_user_password = bm7thmix_user_password;
2135	2132	}
2136	2133
2137	2134	DRIVER_INIT_MEMBER(djmain_state,bmfinal)
r23786	r23787
2147	2144
2148	2145	DRIVER_INIT_CALL(beatmania);
2149	2146
2150		m_ide_master_password = beatmania_master_password;
2151		m_ide_user_password = bmfinal_user_password;
	2147	m_ata_master_password = beatmania_master_password;
	2148	m_ata_user_password = bmfinal_user_password;
2152	2149	}
2153	2150
2154	2151

trunk/src/mame/drivers/iteagle.c

r23786	r23787
84	84
85	85	#include "emu.h"
86	86	#include "cpu/mips/mips3.h"
87		#include "machine/idectrl.h"
	87	#include "machine/ataintf.h"
88	88	#include "video/voodoo.h"
89	89
90	90	class iteagle_state : public driver_device
r23786	r23787
199	199	MCFG_CPU_CONFIG(r4310_config)
200	200	MCFG_CPU_PROGRAM_MAP(main_map)
201	201
202		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
203		MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(iteagle_state, ide_interrupt))
	202	MCFG_ATA_INTERFACE_ADD("ata", ata_devices, "hdd", NULL, true)
	203	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(iteagle_state, ide_interrupt))
204	204
205	205	/* video hardware */
206	206	MCFG_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
r23786	r23787
258	258	ROM_START( iteagle )
259	259	EAGLE_BIOS
260	260
261		DISK_REGION( "ide:0:hdd" )
	261	DISK_REGION( "ata:0:hdd:image" )
262	262	ROM_END
263	263
264	264	ROM_START( gtfore04 )
265	265	EAGLE_BIOS
266	266
267		DISK_REGION( "ide:0:hdd" )
	267	DISK_REGION( "ata:0:hdd:image" )
268	268	DISK_IMAGE( "gt2004", 0, SHA1(739a52d6ce13bb6ac7a543ee0e8086fb66be19b9) )
269	269	ROM_END
270	270
271	271	ROM_START( gtfore05 )
272	272	EAGLE_BIOS
273	273
274		DISK_REGION( "ide:0:hdd" )
	274	DISK_REGION( "ata:0:hdd:image" )
275	275	DISK_IMAGE( "gt2005", 0, SHA1(d8de569d8cf97b5aaada10ce896eb3c75f1b37f1) )
276	276	ROM_END
277	277

trunk/src/mame/drivers/maygayep.c

r23786	r23787
4264	4264	*/
4265	4265
4266	4266	#define EP_PHARO_HDD \
4267		DISK_REGION( "ide" ) \
	4267	DISK_REGION( "ata:0:hdd:image" ) \
4268	4268	DISK_IMAGE( "ep_pharo", 0, SHA1(daf56705178bb2b6f3547418a98c361478702aed) )
4269	4269
4270	4270

trunk/src/mame/drivers/seattle.c

r23786	r23787
1778	1778	/* note that blitz times out if we don't have this cycle stealing */
1779	1779	if (offset == 6/2)
1780	1780	m_maincpu->eat_cycles(100);
1781		return m_ide->read_cs1_pc(space, offset, mem_mask);
	1781	return m_ide->read_cs1(space, offset, mem_mask);
1782	1782	}
1783	1783
1784	1784	static ADDRESS_MAP_START( seattle_map, AS_PROGRAM, 32, seattle_state )
1785	1785	ADDRESS_MAP_UNMAP_HIGH
1786	1786	AM_RANGE(0x00000000, 0x007fffff) AM_RAM AM_SHARE("rambase") // wg3dh only has 4MB; sfrush, blitz99 8MB
1787	1787	AM_RANGE(0x08000000, 0x08ffffff) AM_DEVREAD_LEGACY("voodoo", voodoo_r) AM_WRITE(seattle_voodoo_w)
1788		AM_RANGE(0x0a0001f0, 0x0a0001f7) AM_DEVREADWRITE16("ide", bus_master_ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
1789		AM_RANGE(0x0a0003f0, 0x0a0003f7) AM_READ16(seattle_ide_r, 0xffffffff) AM_DEVWRITE16("ide", bus_master_ide_controller_device, write_cs1_pc, 0xffffffff)
	1788	AM_RANGE(0x0a0001f0, 0x0a0001f7) AM_DEVREADWRITE16("ide", bus_master_ide_controller_device, read_cs0, write_cs0, 0xffffffff)
	1789	AM_RANGE(0x0a0003f0, 0x0a0003f7) AM_READ16(seattle_ide_r, 0xffffffff) AM_DEVWRITE16("ide", bus_master_ide_controller_device, write_cs1, 0xffffffff)
1790	1790	AM_RANGE(0x0a00040c, 0x0a00040f) AM_NOP                     // IDE-related, but annoying
1791	1791	AM_RANGE(0x0a000f00, 0x0a000f07) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, ide_bus_master32_r, ide_bus_master32_w)
1792	1792	AM_RANGE(0x0c000000, 0x0c000fff) AM_READWRITE(galileo_r, galileo_w)
r23786	r23787
2535	2535
2536	2536	MCFG_NVRAM_ADD_1FILL("nvram")
2537	2537
2538		MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
2539		MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(seattle_state, ide_interrupt))
	2538	MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	2539	MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(seattle_state, ide_interrupt))
2540	2540	MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE("maincpu", AS_PROGRAM)
2541	2541
2542	2542	MCFG_3DFX_VOODOO_1_ADD("voodoo", STD_VOODOO_1_CLOCK, voodoo_intf)
r23786	r23787
2628	2628	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* Boot Code Version L1.2 (10/8/96) */
2629	2629	ROM_LOAD( "wg3dh_12.u32", 0x000000, 0x80000, CRC(15e4cea2) SHA1(72c0db7dc53ce645ba27a5311b5ce803ad39f131) )
2630	2630
2631		DISK_REGION( "ide:0:hdd" )    /* Hard Drive Version 1.3 (Guts 10/15/96, Main 10/15/96) */
	2631	DISK_REGION( "ide:0:hdd:image" )    /* Hard Drive Version 1.3 (Guts 10/15/96, Main 10/15/96) */
2632	2632	DISK_IMAGE( "wg3dh", 0, SHA1(4fc6f25d7f043d9bcf8743aa8df1d9be3cbc375b) )
2633	2633
2634	2634	ROM_REGION16_LE( 0x10000, "dcs", 0 )    /* ADSP-2115 data Version L1.1 */
r23786	r23787
2640	2640	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* Boot Code Version 1.0ce 7/2/97 */
2641	2641	ROM_LOAD( "mace10ce.u32", 0x000000, 0x80000, CRC(7a50b37e) SHA1(33788835f84a9443566c80bee9f20a1691490c6d) )
2642	2642
2643		DISK_REGION( "ide:0:hdd" )    /* Hard Drive Version 1.0B 6/10/97 (Guts 7/2/97, Main 7/2/97) */
	2643	DISK_REGION( "ide:0:hdd:image" )    /* Hard Drive Version 1.0B 6/10/97 (Guts 7/2/97, Main 7/2/97) */
2644	2644	DISK_IMAGE( "mace", 0, SHA1(96ec8d3ff5dd894e21aa81403bcdbeba44bb97ea) )
2645	2645
2646	2646	ROM_REGION16_LE( 0x10000, "dcs", 0 )    /* ADSP-2115 data Version L1.1, Labeled as Version 1.0 */
r23786	r23787
2652	2652	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* Boot Code Version ??? 5/7/97 */
2653	2653	ROM_LOAD( "maceboot.u32", 0x000000, 0x80000, CRC(effe3ebc) SHA1(7af3ca3580d6276ffa7ab8b4c57274e15ee6bcbb) )
2654	2654
2655		DISK_REGION( "ide:0:hdd" )    /* Hard Drive Version 1.0a (Guts 6/9/97, Main 5/12/97) */
	2655	DISK_REGION( "ide:0:hdd:image" )    /* Hard Drive Version 1.0a (Guts 6/9/97, Main 5/12/97) */
2656	2656	DISK_IMAGE( "macea", 0, BAD_DUMP SHA1(9bd4a60627915d71932cab24f89c48ea21f4c1cb) )
2657	2657
2658	2658	ROM_REGION16_LE( 0x10000, "dcs", 0 )    /* ADSP-2115 data Version L1.1 */
r23786	r23787
2673	2673	ROM_LOAD32_WORD( "sfrush.u53",  0x800000, 0x200000, CRC(71f8ddb0) SHA1(c24bef801f43bae68fda043c4356e8cf1298ca97) )
2674	2674	ROM_LOAD32_WORD( "sfrush.u49",  0x800002, 0x200000, CRC(dfb0a54c) SHA1(ed34f9485f7a7e5bb73bf5c6428b27548e12db12) )
2675	2675
2676		DISK_REGION( "ide:0:hdd" )    /* Hard Drive Version L1.06 */
	2676	DISK_REGION( "ide:0:hdd:image" )    /* Hard Drive Version L1.06 */
2677	2677	DISK_IMAGE( "sfrush", 0, SHA1(e2db0270a707fb2115207f988d5751081d6b4994) )
2678	2678	ROM_END
2679	2679
r23786	r23787
2691	2691	ROM_LOAD32_WORD( "audio.u53",  0x800000, 0x200000, CRC(51c89a14) SHA1(6bc62bcda224040a4596d795132874828011a038) )
2692	2692	ROM_LOAD32_WORD( "audio.u49",  0x800002, 0x200000, CRC(e6b684d3) SHA1(1f5bab7fae974cecc8756dd23e3c7aa2cf6e7dc7) )
2693	2693
2694		DISK_REGION( "ide:0:hdd" )    /* Hard Drive Version 1.2 */
	2694	DISK_REGION( "ide:0:hdd:image" )    /* Hard Drive Version 1.2 */
2695	2695	DISK_IMAGE( "sfrushrk", 0, SHA1(e763f26aca67ebc17fe8b8df4fba91d492cf7837) )
2696	2696	ROM_END
2697	2697
r23786	r23787
2700	2700	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* Boot Code Version 1.2 (2/18/98) */
2701	2701	ROM_LOAD( "caspd1_2.u32", 0x000000, 0x80000, CRC(0a235e4e) SHA1(b352f10fad786260b58bd344b5002b6ea7aaf76d) )
2702	2702
2703		DISK_REGION( "ide:0:hdd" )    /* Release version 2.1a (4/17/98) (Guts 1.25 4/17/98, Main 4/17/98) */
	2703	DISK_REGION( "ide:0:hdd:image" )    /* Release version 2.1a (4/17/98) (Guts 1.25 4/17/98, Main 4/17/98) */
2704	2704	DISK_IMAGE( "calspeed", 0, SHA1(08d411c591d4b8bbdd6437ea80d01c4cec8516f8) )
2705	2705
2706	2706	ROM_REGION16_LE( 0x10000, "dcs", 0 )    /* ADSP-2115 data Version 1.02 */
r23786	r23787
2712	2712	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* Boot Code Version 1.2 (2/18/98) */
2713	2713	ROM_LOAD( "caspd1_2.u32", 0x000000, 0x80000, CRC(0a235e4e) SHA1(b352f10fad786260b58bd344b5002b6ea7aaf76d) )
2714	2714
2715		DISK_REGION( "ide:0:hdd" )    /* Release version 1.0r7a (3/4/98) (Guts 3/3/98, Main 1/19/98) */
	2715	DISK_REGION( "ide:0:hdd:image" )    /* Release version 1.0r7a (3/4/98) (Guts 3/3/98, Main 1/19/98) */
2716	2716	DISK_IMAGE( "calspeda", 0, SHA1(6b1c3a7530195ef7309b06a651b01c8b3ece92c6) )
2717	2717
2718	2718	ROM_REGION16_LE( 0x10000, "dcs", 0 )    /* ADSP-2115 data Version 1.02 */
r23786	r23787
2724	2724	ROM_REGION32_LE( 0x80000, "user1", 0 )
2725	2725	ROM_LOAD( "vtrxboot.bin", 0x000000, 0x80000, CRC(ee487a6c) SHA1(fb9efda85047cf615f24f7276a9af9fd542f3354) )
2726	2726
2727		DISK_REGION( "ide:0:hdd" )
	2727	DISK_REGION( "ide:0:hdd:image" )
2728	2728	DISK_IMAGE( "vaportrx", 0, SHA1(fe53ca7643d2ed2745086abb7f2243c69678cab1) )
2729	2729
2730	2730	ROM_REGION16_LE( 0x10000, "dcs", 0 )    /* ADSP-2115 data Version 1.02 */
r23786	r23787
2736	2736	ROM_REGION32_LE( 0x80000, "user1", 0 )
2737	2737	ROM_LOAD( "vtrxboot.bin", 0x000000, 0x80000, CRC(ee487a6c) SHA1(fb9efda85047cf615f24f7276a9af9fd542f3354) )
2738	2738
2739		DISK_REGION( "ide:0:hdd" ) /* Guts: Apr 10 1998 11:03:14  Main: Apr 10 1998 11:27:44 */
	2739	DISK_REGION( "ide:0:hdd:image" ) /* Guts: Apr 10 1998 11:03:14  Main: Apr 10 1998 11:27:44 */
2740	2740	DISK_IMAGE( "vaportrp", 0, SHA1(6c86637c442ebd6994eee8c0ae0dce343c35dbe9) )
2741	2741
2742	2742	ROM_REGION16_LE( 0x10000, "dcs", 0 )    /* ADSP-2115 data Version 1.02 */
r23786	r23787
2751	2751	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Seattle System Boot ROM Version 0.1i Apr 14 1997  14:52:53 */
2752	2752	ROM_LOAD( "biofreak.u32", 0x000000, 0x80000, CRC(cefa00bb) SHA1(7e171610ede1e8a448fb8d175f9cb9e7d549de28) )
2753	2753
2754		DISK_REGION( "ide:0:hdd" ) /* Build Date 12/11/97 */
	2754	DISK_REGION( "ide:0:hdd:image" ) /* Build Date 12/11/97 */
2755	2755	DISK_IMAGE( "biofreak", 0, SHA1(711241642f92ded8eaf20c418ea748989183fe10) )
2756	2756	ROM_END
2757	2757
r23786	r23787
2763	2763	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* Boot Code Version 1.2 */
2764	2764	ROM_LOAD( "blitz1_2.u32", 0x000000, 0x80000, CRC(38dbecf5) SHA1(7dd5a5b3baf83a7f8f877ff4cd3f5e8b5201b36f) )
2765	2765
2766		DISK_REGION( "ide:0:hdd" )    /* Hard Drive Version 1.21 */
	2766	DISK_REGION( "ide:0:hdd:image" )    /* Hard Drive Version 1.21 */
2767	2767	DISK_IMAGE( "blitz", 0, SHA1(9131c7888e89b3c172780156ed3fe1fe46f78b0a) )
2768	2768	ROM_END
2769	2769
r23786	r23787
2775	2775	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* Boot Code Version 1.1 */
2776	2776	ROM_LOAD( "blitz1_1.u32", 0x000000, 0x80000, CRC(8163ce02) SHA1(89b432d8879052f6c5534ee49599f667f50a010f) )
2777	2777
2778		DISK_REGION( "ide:0:hdd" )    /* Hard Drive Version 1.21 */
	2778	DISK_REGION( "ide:0:hdd:image" )    /* Hard Drive Version 1.21 */
2779	2779	DISK_IMAGE( "blitz", 0, SHA1(9131c7888e89b3c172780156ed3fe1fe46f78b0a) )
2780	2780	ROM_END
2781	2781
r23786	r23787
2787	2787	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* Boot Code Version 1.0 */
2788	2788	ROM_LOAD( "bltz9910.u32", 0x000000, 0x80000, CRC(777119b2) SHA1(40d255181c2f3a787919c339e83593fd506779a5) )
2789	2789
2790		DISK_REGION( "ide:0:hdd" )    /* Hard Drive Version 1.30 */
	2790	DISK_REGION( "ide:0:hdd:image" )    /* Hard Drive Version 1.30 */
2791	2791	DISK_IMAGE( "blitz99", 0, SHA1(19877e26ffce81dd525031e9e2b4f83ff982e2d9) )
2792	2792	ROM_END
2793	2793
r23786	r23787
2799	2799	ROM_REGION32_LE( 0x80000, "user1", 0 )  /* Boot Code Version 1.4 */
2800	2800	ROM_LOAD( "bltz2k14.u32", 0x000000, 0x80000, CRC(ac4f0051) SHA1(b8125c17370db7bfd9b783230b4ef3d5b22a2025) )
2801	2801
2802		DISK_REGION( "ide:0:hdd" )    /* Hard Drive Version 1.5 */
	2802	DISK_REGION( "ide:0:hdd:image" )    /* Hard Drive Version 1.5 */
2803	2803	DISK_IMAGE( "blitz2k", 0, SHA1(e89b7fbd4b4a9854d47ae97493e0afffbd1f69e7) )
2804	2804	ROM_END
2805	2805
r23786	r23787
2811	2811	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Boot Rom Version 1.9 */
2812	2812	ROM_LOAD( "carnevil1_9.u32", 0x000000, 0x80000, CRC(82c07f2e) SHA1(fa51c58022ce251c53bad12fc6ffadb35adb8162) )
2813	2813
2814		DISK_REGION( "ide:0:hdd" )    /* Hard Drive v1.0.3  Diagnostics v3.4 / Feb 1 1999 16:00:07 */
	2814	DISK_REGION( "ide:0:hdd:image" )    /* Hard Drive v1.0.3  Diagnostics v3.4 / Feb 1 1999 16:00:07 */
2815	2815	DISK_IMAGE( "carnevil", 0, SHA1(5cffb0de63ad36eb01c5951bab04d3f8a9e23e16) )
2816	2816	ROM_END
2817	2817
r23786	r23787
2823	2823	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Boot Rom Version 1.9 */
2824	2824	ROM_LOAD( "carnevil1_9.u32", 0x000000, 0x80000, CRC(82c07f2e) SHA1(fa51c58022ce251c53bad12fc6ffadb35adb8162) )
2825	2825
2826		DISK_REGION( "ide:0:hdd" )    /* Hard Drive v1.0.1  Diagnostics v3.3 / Oct 20 1998 11:44:41 */
	2826	DISK_REGION( "ide:0:hdd:image" )    /* Hard Drive v1.0.1  Diagnostics v3.3 / Oct 20 1998 11:44:41 */
2827	2827	DISK_IMAGE( "carnevi1", 0, BAD_DUMP SHA1(94532727512280930a100fe473bf3a938fe2d44f) )
2828	2828	ROM_END
2829	2829
r23786	r23787
2835	2835	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Boot Rom Version 9. */
2836	2836	ROM_LOAD( "hyprdrve.u32", 0x000000, 0x80000, CRC(3e18cb80) SHA1(b18cc4253090ee1d65d72a7ec0c426ed08c4f238) )
2837	2837
2838		DISK_REGION( "ide:0:hdd" )    /* Version 1.40  Oct 23 1998  15:16:00 */
	2838	DISK_REGION( "ide:0:hdd:image" )    /* Version 1.40  Oct 23 1998  15:16:00 */
2839	2839	DISK_IMAGE( "hyprdriv", 0, SHA1(8cfa343797575b32f46cc24150024be48963a03e) )
2840	2840	ROM_END
2841	2841

trunk/src/mame/drivers/globalvr.c

r23786	r23787
90	90
91	91
92	92	ROM_START( hyperv2 )
93		DISK_REGION( "ide:0:hdd" )
	93	DISK_REGION( "ide:0:hdd:image" )
94	94	DISK_IMAGE_READONLY( "hyperv2_pqi_6-12-02", 0, SHA1(44473f2950c0e108acb0961579a46f4765e379f7) )
95	95	ROM_END
96	96
r23786	r23787
98	98	ROM_REGION( 0x168000, "bootdisk", 0 ) /* Win98/DOS bootdisk from folder made into .IMA with WinImage */
99	99	ROM_LOAD( "hyperv2_pqi_9-30-01.ima", 0x000000, 0x168000, CRC(964d8e00) SHA1(efefcfcca85328df8445a4ba482cd7d5b584ae05) )
100	100
101		DISK_REGION( "ide:0:hdd" )
	101	DISK_REGION( "ide:0:hdd:image" )
102	102	DISK_IMAGE_READONLY( "hyperv2_pqi_9-30-01", 0, SHA1(7a8c201a83a45609d0242a20441891f5204d7dd1) )
103	103	ROM_END
104	104
105	105	ROM_START( gvrxpsys )
106		DISK_REGION( "ide:0:hdd" )
	106	DISK_REGION( "ide:0:hdd:image" )
107	107	DISK_IMAGE_READONLY( "globalvr_xp_system", 0, SHA1(83a784fe038acbd651544b3fa3b17ceb11bbeeab) )
108	108	ROM_END
109	109
110	110	ROM_START( gvrxpsup )
111		DISK_REGION( "ide:0:hdd" )
	111	DISK_REGION( "ide:0:hdd:image" )
112	112	DISK_IMAGE_READONLY( "vr_xp_system_6-11-2002", 0, SHA1(c2b586a0106632bcaddc1df8077ee9c226537d2b) )
113	113	ROM_END
114	114
115	115	ROM_START( bhead2k )
116		DISK_REGION( "ide:0:hdd" )
	116	DISK_REGION( "ide:0:hdd:image" )
117	117	DISK_IMAGE_READONLY( "beachhead2000_5-27-2003", 0, SHA1(d4473a7fb9820f2e517a1e0609ec9e12f326fc06) )
118	118	ROM_END
119	119
120	120	ROM_START( bhead2ka )
121		DISK_REGION( "ide:0:hdd" )
	121	DISK_REGION( "ide:0:hdd:image" )
122	122	DISK_IMAGE_READONLY( "beachhead2000_9-16-2001", 0, SHA1(2151c0aff39a5279adb422e97f00c610d21c48e8) )
123	123	ROM_END
124	124
125	125	ROM_START( bhead2k2 )
126		DISK_REGION( "ide:0:hdd" )
	126	DISK_REGION( "ide:0:hdd:image" )
127	127	DISK_IMAGE_READONLY( "beachhead2002_5-27-2003", 0, SHA1(c58e62363387b76b4f03432b543498d4560d27a9) )
128	128	ROM_END
129	129
130	130	ROM_START( bhead2k3 )
131		DISK_REGION( "ide:0:hdd" )
	131	DISK_REGION( "ide:0:hdd:image" )
132	132	DISK_IMAGE_READONLY( "beachhead2003desertwar_5-27-2003", 0, SHA1(fed23a6496836050eb1d4f69b91da09adbd9d973) )
133	133	ROM_END
134	134
135	135	ROM_START( nfsug )
136		DISK_REGION( "ide:0:hdd" )
	136	DISK_REGION( "ide:0:hdd:image" )
137	137	DISK_IMAGE_READONLY( "nfsug1_1-disc1", 0, SHA1(25a9f0606ac3909bd7c4f3f3a59c6782e3c84712) )
138	138
139	139	DISK_REGION( "drive_1" )

trunk/src/mame/drivers/savquest.c

r23786	r23787
552	552
553	553	AM_RANGE(0x00e8, 0x00ef) AM_NOP
554	554
555		AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
	555	AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
556	556	AM_RANGE(0x0378, 0x037b) AM_READWRITE(parallel_port_r, parallel_port_w)
557	557	AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
558	558	AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
559	559	AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
560		AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
	560	AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
561	561
562	562	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
563	563
r23786	r23787
619	619	MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
620	620	MCFG_PCI_BUS_LEGACY_DEVICE(7, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
621	621
622		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
623		MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
	622	MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	623	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
624	624
625	625	/* video hardware */
626	626	MCFG_FRAGMENT_ADD( pcvideo_s3_vga )
r23786	r23787
636	636	ROM_LOAD( "s3_764.bin",   0x000000, 0x008000, BAD_DUMP CRC(4f10aac7) SHA1(c77b3f11cc15679121314823588887dd547cd715) )
637	637	ROM_IGNORE( 0x8000 )
638	638
639		DISK_REGION( "ide:0:hdd" )
	639	DISK_REGION( "ide:0:hdd:image" )
640	640	DISK_IMAGE( "savquest", 0, SHA1(b7c8901172b66706a7ab5f5c91e6912855153fa9) )
641	641	ROM_END
642	642

trunk/src/mame/drivers/photoply.c

r23786	r23787
48	48	static ADDRESS_MAP_START( photoply_io, AS_IO, 32, photoply_state )
49	49	AM_IMPORT_FROM(pcat32_io_common)
50	50	AM_RANGE(0x00e8, 0x00eb) AM_NOP
51		AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
	51	AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
52	52	AM_RANGE(0x0278, 0x027f) AM_RAM //parallel port 2
53	53	AM_RANGE(0x0378, 0x037f) AM_RAM //parallel port
54	54	//AM_RANGE(0x03bc, 0x03bf) AM_RAM //parallel port 3
55	55	AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
56	56	AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
57	57	AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
58		AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
	58	AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
59	59	ADDRESS_MAP_END
60	60
61	61	#define AT_KEYB_HELPER(bit, text, key1) \
r23786	r23787
123	123
124	124	MCFG_GFXDECODE( photoply )
125	125
126		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
127		MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
	126	MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	127	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
128	128
129	129	MCFG_FRAGMENT_ADD( pcvideo_vga )
130	130	MACHINE_CONFIG_END
r23786	r23787
143	143	ROM_REGION(0x8000, "video_bios", 0 )
144	144	ROM_LOAD("vga.bin", 0x000000, 0x8000, CRC(7a859659) SHA1(ff667218261969c48082ec12aa91088a01b0cb2a) )
145	145
146		DISK_REGION( "ide:0:hdd" )
	146	DISK_REGION( "ide:0:hdd:image" )
147	147	DISK_IMAGE( "pp201", 0, SHA1(23e1940d485d19401e7d0ad912ddad2cf2ea10b4) )
148	148	ROM_END
149	149

trunk/src/mame/drivers/midqslvr.c

r23786	r23787
372	372	AM_IMPORT_FROM(pcat32_io_common)
373	373	AM_RANGE(0x00e8, 0x00ef) AM_NOP
374	374
375		AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
	375	AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
376	376	AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
377	377	AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
378	378	AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
379		AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
	379	AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
380	380
381	381	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
382	382	ADDRESS_MAP_END
r23786	r23787
418	418	MCFG_PCI_BUS_LEGACY_DEVICE( 0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
419	419	MCFG_PCI_BUS_LEGACY_DEVICE(31, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
420	420
421		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
422		MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
	421	MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	422	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
423	423
424	424	/* video hardware */
425	425	MCFG_FRAGMENT_ADD( pcvideo_vga )
r23786	r23787
434	434	//  ROM_LOAD16_BYTE( "trident_tgui9680_bios.bin", 0x0000, 0x4000, BAD_DUMP CRC(1eebde64) SHA1(67896a854d43a575037613b3506aea6dae5d6a19) )
435	435	//  ROM_CONTINUE(                                 0x0001, 0x4000 )
436	436
437		DISK_REGION( "ide:0:hdd" )
	437	DISK_REGION( "ide:0:hdd:image" )
438	438	DISK_IMAGE( "offrthnd", 0, SHA1(d88f1c5b75361a1e310565a8a5a09c674a4a1a22) )
439	439	ROM_END
440	440
r23786	r23787
446	446	//  ROM_LOAD16_BYTE( "trident_tgui9680_bios.bin", 0x0000, 0x4000, BAD_DUMP CRC(1eebde64) SHA1(67896a854d43a575037613b3506aea6dae5d6a19) )
447	447	//  ROM_CONTINUE(                                 0x0001, 0x4000 )
448	448
449		DISK_REGION( "ide:0:hdd" )
	449	DISK_REGION( "ide:0:hdd:image" )
450	450	DISK_IMAGE( "hydro", 0,  SHA1(d481d178782943c066b41764628a419cd55f676d) )
451	451	ROM_END
452	452
r23786	r23787
458	458	//  ROM_LOAD16_BYTE( "trident_tgui9680_bios.bin", 0x0000, 0x4000, BAD_DUMP CRC(1eebde64) SHA1(67896a854d43a575037613b3506aea6dae5d6a19) )
459	459	//  ROM_CONTINUE(                                 0x0001, 0x4000 )
460	460
461		DISK_REGION( "ide:0:hdd" )
	461	DISK_REGION( "ide:0:hdd:image" )
462	462	DISK_IMAGE( "arctthnd", 0,  SHA1(f4373e57c3f453ac09c735b5d8d99ff811416a23) )
463	463	ROM_END
464	464
r23786	r23787
471	471	//  ROM_LOAD16_BYTE( "trident_tgui9680_bios.bin", 0x0000, 0x4000, BAD_DUMP CRC(1eebde64) SHA1(67896a854d43a575037613b3506aea6dae5d6a19) )
472	472	//  ROM_CONTINUE(                                 0x0001, 0x4000 )
473	473
474		DISK_REGION( "ide:0:hdd" )
	474	DISK_REGION( "ide:0:hdd:image" )
475	475	DISK_IMAGE( "uarctict", 0, SHA1(8557a1d7ae8dc41c879350cb1c228f4c27a0dd09) )
476	476	ROM_END
477	477

trunk/src/mame/drivers/calchase.c

r23786	r23787
409	409	//AM_RANGE(0x00e8, 0x00eb) AM_NOP
410	410	AM_RANGE(0x00e8, 0x00ef) AM_NOP //AMI BIOS write to this ports as delays between I/O ports operations sending al value -> NEWIODELAY
411	411	AM_RANGE(0x0170, 0x0177) AM_NOP //To debug
412		AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
	412	AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
413	413	AM_RANGE(0x0200, 0x021f) AM_NOP //To debug
414	414	AM_RANGE(0x0260, 0x026f) AM_NOP //To debug
415	415	AM_RANGE(0x0278, 0x027b) AM_WRITENOP//AM_WRITE(pnp_config_w)
r23786	r23787
428	428	AM_RANGE(0x0378, 0x037f) AM_NOP //To debug
429	429	// AM_RANGE(0x0300, 0x03af) AM_NOP
430	430	// AM_RANGE(0x03b0, 0x03df) AM_NOP
431		AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
	431	AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
432	432	AM_RANGE(0x03f8, 0x03ff) AM_NOP // To debug Serial Port COM1:
433	433	AM_RANGE(0x0a78, 0x0a7b) AM_WRITENOP//AM_WRITE(pnp_data_w)
434	434	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
r23786	r23787
644	644
645	645	MCFG_FRAGMENT_ADD( pcat_common )
646	646
647		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
648		MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
	647	MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
	648	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
649	649
650	650	MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
651	651	MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
r23786	r23787
696	696	ROM_REGION( 0x800, "nvram", 0 )
697	697	ROM_LOAD( "ds1220y_nv.bin", 0x000, 0x800, CRC(7912c070) SHA1(b4c55c7ca76bcd8dad1c4b50297233349ae02ed3) )
698	698
699		DISK_REGION( "ide:0:hdd" )
	699	DISK_REGION( "ide:0:hdd:image" )
700	700	DISK_IMAGE_READONLY( "calchase", 0,BAD_DUMP SHA1(6ae51a9b3f31cf4166322328a98c0235b0874eb3) )
701	701	ROM_END
702	702

trunk/src/mame/drivers/taitogn.c

r23786	r23787
795	795	ROM_START(raycris)
796	796	TAITOGNET_BIOS
797	797
798		DISK_REGION( "pccard:ataflash" )
	798	DISK_REGION( "pccard:ataflash:image" )
799	799	DISK_IMAGE( "raycris", 0, SHA1(015cb0e6c4421cc38809de28c4793b4491386aee))
800	800	ROM_END
801	801
r23786	r23787
803	803	ROM_START(gobyrc)
804	804	TAITOGNET_BIOS
805	805
806		DISK_REGION( "pccard:ataflash" )
	806	DISK_REGION( "pccard:ataflash:image" )
807	807	DISK_IMAGE( "gobyrc", 0, SHA1(0bee1f495fc8b033fd56aad9260ae94abb35eb58))
808	808	ROM_END
809	809
810	810	ROM_START(rcdego)
811	811	TAITOGNET_BIOS
812	812
813		DISK_REGION( "pccard:ataflash" )
	813	DISK_REGION( "pccard:ataflash:image" )
814	814	DISK_IMAGE( "rcdego", 0, SHA1(9e177f2a3954cfea0c8c5a288e116324d10f5dd1))
815	815	ROM_END
816	816
817	817	ROM_START(chaoshea)
818	818	TAITOGNET_BIOS
819	819
820		DISK_REGION( "pccard:ataflash" )
	820	DISK_REGION( "pccard:ataflash:image" )
821	821	DISK_IMAGE( "chaosheat", 0, SHA1(c13b7d7025eee05f1f696d108801c7bafb3f1356))
822	822	ROM_END
823	823
824	824	ROM_START(chaosheaj)
825	825	TAITOGNET_BIOS
826	826
827		DISK_REGION( "pccard:ataflash" )
	827	DISK_REGION( "pccard:ataflash:image" )
828	828	DISK_IMAGE( "chaosheatj", 0, SHA1(2f211ac08675ea8ec33c7659a13951db94eaa627))
829	829	ROM_END
830	830
r23786	r23787
832	832	ROM_START(flipmaze)
833	833	TAITOGNET_BIOS
834	834
835		DISK_REGION( "pccard:ataflash" )
	835	DISK_REGION( "pccard:ataflash:image" )
836	836	DISK_IMAGE( "flipmaze", 0, SHA1(423b6c06f4f2d9a608ce20b61a3ac11687d22c40) )
837	837	ROM_END
838	838
r23786	r23787
840	840	ROM_START(spuzbobl)
841	841	TAITOGNET_BIOS
842	842
843		DISK_REGION( "pccard:ataflash" )
	843	DISK_REGION( "pccard:ataflash:image" )
844	844	DISK_IMAGE( "spuzbobl", 0, SHA1(1b1c72fb7e5656021485fefaef8f2ba48e2b4ea8))
845	845	ROM_END
846	846
847	847	ROM_START(spuzboblj)
848	848	TAITOGNET_BIOS
849	849
850		DISK_REGION( "pccard:ataflash" )
	850	DISK_REGION( "pccard:ataflash:image" )
851	851	DISK_IMAGE( "spuzbobj", 0, SHA1(dac433cf88543d2499bf797d7406b82ae4338726))
852	852	ROM_END
853	853
854	854	ROM_START(soutenry)
855	855	TAITOGNET_BIOS
856	856
857		DISK_REGION( "pccard:ataflash" )
	857	DISK_REGION( "pccard:ataflash:image" )
858	858	DISK_IMAGE( "soutenry", 0, SHA1(9204d0be833d29f37b8cd3fbdf09da69b622254b))
859	859	ROM_END
860	860
861	861	ROM_START(shanghss)
862	862	TAITOGNET_BIOS
863	863
864		DISK_REGION( "pccard:ataflash" )
	864	DISK_REGION( "pccard:ataflash:image" )
865	865	DISK_IMAGE( "shanghss", 0, SHA1(7964f71ec5c81d2120d83b63a82f97fbad5a8e6d))
866	866	ROM_END
867	867
868	868	ROM_START(sianniv)
869	869	TAITOGNET_BIOS
870	870
871		DISK_REGION( "pccard:ataflash" )
	871	DISK_REGION( "pccard:ataflash:image" )
872	872	DISK_IMAGE( "sianniv", 0, SHA1(1e08b813190a9e1baf29bc16884172d6c8da7ae3))
873	873	ROM_END
874	874
875	875	ROM_START(kollon)
876	876	TAITOGNET_BIOS
877	877
878		DISK_REGION( "pccard:ataflash" )
	878	DISK_REGION( "pccard:ataflash:image" )
879	879	DISK_IMAGE( "kollon", 0, SHA1(d8ea5b5b0ee99004b16ef89883e23de6c7ddd7ce))
880	880	ROM_END
881	881
r23786	r23787
883	883	TAITOGNET_BIOS
884	884	ROM_DEFAULT_BIOS( "v2" )
885	885
886		DISK_REGION( "pccard:ataflash" )
	886	DISK_REGION( "pccard:ataflash:image" )
887	887	DISK_IMAGE( "kollonc", 0, SHA1(ce62181659701cfb8f7c564870ab902be4d8e060)) /* Original Taito Compact Flash version */
888	888	ROM_END
889	889
890	890	ROM_START(shikigam)
891	891	TAITOGNET_BIOS
892	892
893		DISK_REGION( "pccard:ataflash" )
	893	DISK_REGION( "pccard:ataflash:image" )
894	894	DISK_IMAGE( "shikigam", 0, SHA1(fa49a0bc47f5cb7c30d7e49e2c3696b21bafb840))
895	895	ROM_END
896	896
r23786	r23787
900	900	ROM_START(otenamih)
901	901	TAITOGNET_BIOS
902	902
903		DISK_REGION( "pccard:ataflash" )
	903	DISK_REGION( "pccard:ataflash:image" )
904	904	DISK_IMAGE( "otenamih", 0, SHA1(b3babe3a1876c43745616ee1e7d87276ce7dad0b) )
905	905	ROM_END
906	906
r23786	r23787
908	908	ROM_START(psyvaria)
909	909	TAITOGNET_BIOS
910	910
911		DISK_REGION( "pccard:ataflash" )
	911	DISK_REGION( "pccard:ataflash:image" )
912	912	DISK_IMAGE( "psyvaria", 0,  SHA1(b981a42a10069322b77f7a268beae1d409b4156d))
913	913	ROM_END
914	914
915	915	ROM_START(psyvarrv)
916	916	TAITOGNET_BIOS
917	917
918		DISK_REGION( "pccard:ataflash" )
	918	DISK_REGION( "pccard:ataflash:image" )
919	919	DISK_IMAGE( "psyvarrv", 0, SHA1(277c4f52502bcd7acc1889840962ec80d56465f3))
920	920	ROM_END
921	921
922	922	ROM_START(zooo)
923	923	TAITOGNET_BIOS
924	924
925		DISK_REGION( "pccard:ataflash" )
	925	DISK_REGION( "pccard:ataflash:image" )
926	926	DISK_IMAGE( "zooo", 0, SHA1(e275b3141b2bc49142990e6b497a5394a314a30b))
927	927	ROM_END
928	928
929	929	ROM_START(zokuoten)
930	930	TAITOGNET_BIOS
931	931
932		DISK_REGION( "pccard:ataflash" )
	932	DISK_REGION( "pccard:ataflash:image" )
933	933	DISK_IMAGE( "zokuoten", 0, SHA1(5ce13db00518f96af64935176c71ec68d2a51938))
934	934	ROM_END
935	935
r23786	r23787
937	937	TAITOGNET_BIOS
938	938	ROM_DEFAULT_BIOS( "v2" )
939	939
940		DISK_REGION( "pccard:ataflash" )
	940	DISK_REGION( "pccard:ataflash:image" )
941	941	DISK_IMAGE( "otenamhf", 0, SHA1(5b15c33bf401e5546d78e905f538513d6ffcf562)) /* Original Taito Compact Flash version */
942	942	ROM_END
943	943
r23786	r23787
949	949	ROM_START(nightrai)
950	950	TAITOGNET_BIOS
951	951
952		DISK_REGION( "pccard:ataflash" )
	952	DISK_REGION( "pccard:ataflash:image" )
953	953	DISK_IMAGE( "nightrai", 0, SHA1(74d0458f851cbcf10453c5cc4c47bb4388244cdf))
954	954	ROM_END
955	955
956	956	ROM_START(otenki)
957	957	TAITOGNET_BIOS
958	958
959		DISK_REGION( "pccard:ataflash" )
	959	DISK_REGION( "pccard:ataflash:image" )
960	960	DISK_IMAGE( "otenki", 0, SHA1(7e745ca4c4570215f452fd09cdd56a42c39caeba))
961	961	ROM_END
962	962
r23786	r23787
965	965	ROM_START(usagi)
966	966	TAITOGNET_BIOS
967	967
968		DISK_REGION( "pccard:ataflash" )
	968	DISK_REGION( "pccard:ataflash:image" )
969	969	DISK_IMAGE( "usagi", 0, SHA1(edf9dd271957f6cb06feed238ae21100514bef8e))
970	970	ROM_END
971	971
972	972	ROM_START(mahjngoh)
973	973	TAITOGNET_BIOS
974	974
975		DISK_REGION( "pccard:ataflash" )
	975	DISK_REGION( "pccard:ataflash:image" )
976	976	DISK_IMAGE( "mahjngoh", 0, SHA1(3ef1110d15582d7c0187438d7ad61765dd121cff))
977	977	ROM_END
978	978
979	979	ROM_START(shangtou)
980	980	TAITOGNET_BIOS
981	981
982		DISK_REGION( "pccard:ataflash" )
	982	DISK_REGION( "pccard:ataflash:image" )
983	983	DISK_IMAGE( "shanghaito", 0, SHA1(9901db5a9aae77e3af4157aa2c601eaab5b7ca85) )
984	984	ROM_END
985	985
r23786	r23787
989	989	ROM_START(xiistag)
990	990	TAITOGNET_BIOS
991	991
992		DISK_REGION( "pccard:ataflash" )
	992	DISK_REGION( "pccard:ataflash:image" )
993	993	DISK_IMAGE( "xiistag", 0, SHA1(586e37c8d926293b2bd928e5f0d693910cfb05a2))
994	994	ROM_END
995	995

trunk/src/mame/includes/qdrmfgp.h

r23786	r23787
1		#include "machine/idectrl.h"
	1	#include "machine/ataintf.h"
2	2	#include "sound/k054539.h"
3	3
4	4	class qdrmfgp_state : public driver_device
r23786	r23787
11	11	m_workram(*this, "workram"),
12	12	m_k056832(*this, "k056832"),
13	13	m_k054539(*this, "k054539"),
14		m_ide(*this, "ide")
	14	m_ata(*this, "ata")
15	15	{
16	16	}
17	17
r23786	r23787
21	21	required_shared_ptr<UINT16> m_workram;
22	22	required_device<k056832_device> m_k056832;
23	23	required_device<k054539_device> m_k054539;
24		required_device<ide_controller_device> m_ide;
	24	required_device<ata_interface_device> m_ata;
25	25	UINT16 m_control;
26	26	INT32 m_gp2_irq_control;
27	27	INT32 m_pal;

trunk/src/mame/includes/djmain.h

r23786	r23787
1		#include "machine/idectrl.h"
	1	#include "machine/ataintf.h"
2	2
3	3	class djmain_state : public driver_device
4	4	{
r23786	r23787
9	9	m_maincpu(*this, "maincpu"),
10	10	m_k056832(*this, "k056832"),
11	11	m_k055555(*this, "k055555"),
12		m_ide(*this, "ide")
	12	m_ata(*this, "ata")
13	13	{
14	14	}
15	15
r23786	r23787
21	21	UINT8 m_pending_vb_int;
22	22	UINT16 m_v_ctrl;
23	23	UINT32 m_obj_regs[0xa0/4];
24		const UINT8 *m_ide_user_password;
25		const UINT8 *m_ide_master_password;
	24	const UINT8 *m_ata_user_password;
	25	const UINT8 *m_ata_master_password;
26	26	required_shared_ptr<UINT32> m_obj_ram;
27	27	DECLARE_WRITE32_MEMBER(paletteram32_w);
28	28	DECLARE_WRITE32_MEMBER(sndram_bank_w);
r23786	r23787
65	65	required_device<cpu_device> m_maincpu;
66	66	required_device<k056832_device> m_k056832;
67	67	required_device<k055555_device> m_k055555;
68		required_device<ide_controller_device> m_ide;
	68	required_device<ata_interface_device> m_ata;
69	69	};
70	70
71	71	/*----------- defined in video/djmain.c -----------*/

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