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r23756 Monday 17th June, 2013 at 20:08:06 UTC by Wilbert Pol
i4004.c: Modernized cpu core (nw)
[src/emu/cpu/i4004]i4004.c i4004.h
[src/mame/drivers]flicker.c
[src/mess/drivers]4004clk.c busicom.c
[src/mess/includes]busicom.h

trunk/src/mame/drivers/flicker.c
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3737protected:
3838
3939   // devices
40   required_device<cpu_device> m_maincpu;
40   required_device<i4004_cpu_device> m_maincpu;
4141
4242private:
4343   UINT8 m_out_data;
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141141   if (BIT(ioport("COIN")->read(), 0) )
142142      test_port |= coin_port;
143143
144   i4004_set_test(m_maincpu, BIT(test_port, offset));
144   m_maincpu->set_test(BIT(test_port, offset));
145145}
146146
147147WRITE8_MEMBER( flicker_state::port10_w )
trunk/src/emu/cpu/i4004/i4004.h
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2222    TYPE DEFINITIONS
2323***************************************************************************/
2424
25/***************************************************************************
26    FUNCTION PROTOTYPES
27***************************************************************************/
25class i4004_cpu_device :  public cpu_device
26{
27public:
28   // construction/destruction
29   i4004_cpu_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock);
2830
29DECLARE_LEGACY_CPU_DEVICE(I4004, i4004);
31   void set_test(UINT8 val);
3032
31CPU_DISASSEMBLE( i4004 );
33protected:
34   // device-level overrides
35   virtual void device_start();
36   virtual void device_reset();
3237
33void i4004_set_test(device_t *device, UINT8 val);
38   // device_execute_interface overrides
39   virtual UINT32 execute_min_cycles() const { return 8; }
40   virtual UINT32 execute_max_cycles() const { return 16; }
41   virtual void execute_run();
42
43   // device_memory_interface overrides
44   virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const
45   {
46      switch (spacenum)
47      {
48         case AS_PROGRAM: return &m_program_config;
49         case AS_IO:      return &m_io_config;
50         case AS_DATA:    return &m_data_config;
51         default:         return NULL;
52      }
53   }
54
55   // device_state_interface overrides
56   virtual void state_import(const device_state_entry &entry);
57   virtual void state_export(const device_state_entry &entry);
58   virtual void state_string_export(const device_state_entry &entry, astring &string);
59
60   // device_disasm_interface overrides
61   virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
62   virtual UINT32 disasm_max_opcode_bytes() const { return 2; }
63   virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
64
65   UINT8 ROP();
66   UINT8 READ_ROM();
67   void WPM();
68   UINT8 ARG();
69   UINT8 RM();
70   UINT8 RMS(UINT32 a);
71   void WM(UINT8 v);
72   void WMP(UINT8 v);
73   void WMS(UINT32 a, UINT8 v);
74   UINT8 RIO();
75   void WIO(UINT8 v);
76   UINT8 GET_REG(UINT8 num);
77   void SET_REG(UINT8 num, UINT8 val);
78   void PUSH_STACK();
79   void POP_STACK();
80   void execute_one(int opcode);
81
82   address_space_config m_program_config;
83   address_space_config m_io_config;
84   address_space_config m_data_config;
85
86   UINT8   m_A; // Accumulator
87   UINT8   m_R[8];
88   PAIR    m_ADDR[4]; // Address registers
89   PAIR    m_RAM;
90   UINT8   m_C; // Carry flag
91   UINT8   m_TEST; // Test PIN status
92   PAIR    m_PC; // It is in fact one of ADDR regs
93   UINT8   m_flags; // used for I/O only
94
95   address_space *m_program;
96   direct_read_data *m_direct;
97   address_space *m_data;
98   address_space *m_io;
99   int                 m_icount;
100   int                 m_pc_pos; // PC possition in ADDR
101   int                 m_addr_mask;
102};
103
104
105extern const device_type I4004;
106
107
34108#endif
trunk/src/emu/cpu/i4004/i4004.c
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1111#include "debugger.h"
1212#include "i4004.h"
1313
14#define VERBOSE 0
1514
16#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
17
1815static const UINT8 kbp_table[] = { 0x00,0x01,0x02,0x0f,0x03,0x0f,0x0f,0x0f,0x04,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f };
1916
20/***************************************************************************
21    TYPE DEFINITIONS
22***************************************************************************/
2317
24struct i4004_state
25{
26   UINT8   A; // Accumulator
27   UINT8   R[8];
28   PAIR    ADDR[4]; // Address registers
29   PAIR    RAM;
30   UINT8   C; // Carry flag
31   UINT8   TEST; // Test PIN status
32   PAIR    PC; // It is in fact one of ADDR regs
33   UINT8   flags; // used for I/O only
34
35   legacy_cpu_device *device;
36   address_space *program;
37   direct_read_data *direct;
38   address_space *data;
39   address_space *io;
40   int                 icount;
41   int                 pc_pos; // PC possition in ADDR
42   int                 addr_mask;
43};
44
4518/***************************************************************************
4619    MACROS
4720***************************************************************************/
48#define GET_PC                  (cpustate->ADDR[cpustate->pc_pos])
21#define GET_PC                  (m_ADDR[m_pc_pos])
4922
50/***************************************************************************
51    INLINE FUNCTIONS
52***************************************************************************/
5323
54INLINE i4004_state *get_safe_token(device_t *device)
24const device_type I4004 = &device_creator<i4004_cpu_device>;
25
26
27i4004_cpu_device::i4004_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
28   : cpu_device(mconfig, I4004, "Intel I4004", tag, owner, clock)
29   , m_program_config("program", ENDIANNESS_LITTLE, 8, 12, 0)
30   , m_io_config("io", ENDIANNESS_LITTLE, 8, 6, 0)
31   , m_data_config("data", ENDIANNESS_LITTLE, 8, 12, 0)
5532{
56   assert(device != NULL);
57   assert(device->type() == I4004);
58   return (i4004_state *)downcast<legacy_cpu_device *>(device)->token();
33   m_is_octal = true;
5934}
6035
61INLINE UINT8 ROP(i4004_state *cpustate)
36
37UINT8 i4004_cpu_device::ROP()
6238{
63   UINT8 retVal = cpustate->direct->read_decrypted_byte(GET_PC.w.l);
39   UINT8 retVal = m_direct->read_decrypted_byte(GET_PC.w.l);
6440   GET_PC.w.l = (GET_PC.w.l + 1) & 0x0fff;
65   cpustate->PC = GET_PC;
41   m_PC = GET_PC;
6642   return retVal;
6743}
6844
69INLINE UINT8 READ_ROM(i4004_state *cpustate)
45UINT8 i4004_cpu_device::READ_ROM()
7046{
71   return cpustate->direct->read_decrypted_byte((GET_PC.w.l & 0x0f00) | cpustate->R[0]);
47   return m_direct->read_decrypted_byte((GET_PC.w.l & 0x0f00) | m_R[0]);
7248}
7349
74INLINE void WPM(i4004_state *cpustate)
50void i4004_cpu_device::WPM()
7551{
76   UINT8 t =  (cpustate->program->read_byte(cpustate->RAM.d) << 4) | cpustate->A;
77   cpustate->program->write_byte((GET_PC.w.l & 0x0f00) | cpustate->RAM.d, t);
52   UINT8 t =  (m_program->read_byte(m_RAM.d) << 4) | m_A;
53   m_program->write_byte((GET_PC.w.l & 0x0f00) | m_RAM.d, t);
7854}
7955
8056
81INLINE UINT8 ARG(i4004_state *cpustate)
57UINT8 i4004_cpu_device::ARG()
8258{
83   UINT8 retVal = cpustate->direct->read_raw_byte(GET_PC.w.l);
59   UINT8 retVal = m_direct->read_raw_byte(GET_PC.w.l);
8460   GET_PC.w.l = (GET_PC.w.l + 1) & 0x0fff;
85   cpustate->PC = GET_PC;
61   m_PC = GET_PC;
8662   return retVal;
8763}
8864
89INLINE UINT8 RM(i4004_state *cpustate)
65UINT8 i4004_cpu_device::RM()
9066{
91   return cpustate->data->read_byte(cpustate->RAM.d) & 0x0f;
67   return m_data->read_byte(m_RAM.d) & 0x0f;
9268}
9369
94INLINE UINT8 RMS(i4004_state *cpustate, UINT32 a)
70UINT8 i4004_cpu_device::RMS(UINT32 a)
9571{
96   return cpustate->data->read_byte((cpustate->RAM.d & 0xff0) + a) >> 4;
72   return m_data->read_byte((m_RAM.d & 0xff0) + a) >> 4;
9773}
9874
99INLINE void WM(i4004_state *cpustate, UINT8 v)
75void i4004_cpu_device::WM(UINT8 v)
10076{
101   UINT8 t =  cpustate->data->read_byte(cpustate->RAM.d);
102   cpustate->data->write_byte(cpustate->RAM.d, (t & 0xf0) | v);
77   UINT8 t =  m_data->read_byte(m_RAM.d);
78   m_data->write_byte(m_RAM.d, (t & 0xf0) | v);
10379}
10480
10581
106INLINE void WMP(i4004_state *cpustate, UINT8 v)
82void i4004_cpu_device::WMP(UINT8 v)
10783{
108   cpustate->io->write_byte((cpustate->RAM.d >> 6) | 0x10, v & 0x0f);
84   m_io->write_byte((m_RAM.d >> 6) | 0x10, v & 0x0f);
10985}
11086
111INLINE void WMS(i4004_state *cpustate, UINT32 a, UINT8 v)
87void i4004_cpu_device::WMS(UINT32 a, UINT8 v)
11288{
113   UINT8 t =  cpustate->data->read_byte((cpustate->RAM.d & 0xff0) + a);
114   cpustate->data->write_byte((cpustate->RAM.d & 0xff0) + a, (t & 0x0f) | (v<<4));
89   UINT8 t =  m_data->read_byte((m_RAM.d & 0xff0) + a);
90   m_data->write_byte((m_RAM.d & 0xff0) + a, (t & 0x0f) | (v<<4));
11591}
11692
117INLINE UINT8 RIO(i4004_state *cpustate)
93UINT8 i4004_cpu_device::RIO()
11894{
119   return cpustate->io->read_byte(cpustate->RAM.b.l >> 4) & 0x0f;
95   return m_io->read_byte(m_RAM.b.l >> 4) & 0x0f;
12096}
12197
122INLINE void WIO(i4004_state *cpustate, UINT8 v)
98void i4004_cpu_device::WIO(UINT8 v)
12399{
124   cpustate->io->write_byte(cpustate->RAM.b.l >> 4, v & 0x0f);
100   m_io->write_byte(m_RAM.b.l >> 4, v & 0x0f);
125101}
126102
127INLINE UINT8 GET_REG(i4004_state *cpustate, UINT8 num)
103UINT8 i4004_cpu_device::GET_REG(UINT8 num)
128104{
129   UINT8 r = cpustate->R[num>>1];
105   UINT8 r = m_R[num>>1];
130106   if (num & 1) {
131107      return r & 0x0f;
132108   } else {
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134110   }
135111}
136112
137INLINE void SET_REG(i4004_state *cpustate, UINT8 num, UINT8 val)
113void i4004_cpu_device::SET_REG(UINT8 num, UINT8 val)
138114{
139115   if (num & 1) {
140      cpustate->R[num>>1] = (cpustate->R[num>>1] & 0xf0) + (val & 0x0f);
116      m_R[num>>1] = (m_R[num>>1] & 0xf0) + (val & 0x0f);
141117   } else {
142      cpustate->R[num>>1] = (cpustate->R[num>>1] & 0x0f) + ((val & 0x0f) << 4);
118      m_R[num>>1] = (m_R[num>>1] & 0x0f) + ((val & 0x0f) << 4);
143119   }
144120}
145121
146INLINE void PUSH_STACK(i4004_state *cpustate)
122void i4004_cpu_device::PUSH_STACK()
147123{
148   cpustate->pc_pos = (cpustate->pc_pos + 1) & cpustate->addr_mask;
124   m_pc_pos = (m_pc_pos + 1) & m_addr_mask;
149125}
150126
151INLINE void POP_STACK(i4004_state *cpustate)
127void i4004_cpu_device::POP_STACK()
152128{
153   cpustate->ADDR[cpustate->pc_pos].d = 0;
154   cpustate->pc_pos = (cpustate->pc_pos - 1) & cpustate->addr_mask;
129   m_ADDR[m_pc_pos].d = 0;
130   m_pc_pos = (m_pc_pos - 1) & m_addr_mask;
155131}
156132
157void i4004_set_test(device_t *device, UINT8 val)
133void i4004_cpu_device::set_test(UINT8 val)
158134{
159   i4004_state *cpustate = get_safe_token(device);
160   cpustate->TEST = val;
135   m_TEST = val;
161136}
162137
163static void execute_one(i4004_state *cpustate, int opcode)
138void i4004_cpu_device::execute_one(int opcode)
164139{
165   cpustate->icount -= 8;
140   m_icount -= 8;
166141   switch (opcode)
167142   {
168143      case 0x00:  /* NOP  */
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173148      case 0x18: case 0x19: case 0x1a: case 0x1b:
174149      case 0x1c: case 0x1d: case 0x1e: case 0x1f: /* JCN */
175150         {
176            UINT8 arg =  ARG(cpustate);
151            UINT8 arg =  ARG();
177152
178153            UINT8 C1 = BIT(opcode,3);
179154            UINT8 C2 = BIT(opcode,2);
180155            UINT8 C3 = BIT(opcode,1);
181156            UINT8 C4 = BIT(opcode,0);
182            UINT8 JUMP = (((cpustate->A == 0) ? 1 : 0) & C2) | ((cpustate->C) & C3) | ((cpustate->TEST ^ 1) & C4);
183            cpustate->icount -= 8;
157            UINT8 JUMP = (((m_A == 0) ? 1 : 0) & C2) | ((m_C) & C3) | ((m_TEST ^ 1) & C4);
158            m_icount -= 8;
184159
185160            if(((C1 ^ 1) &  JUMP) | (C1 & (JUMP ^ 1))) {
186161               GET_PC.w.l = (GET_PC.w.l & 0x0f00) | arg;
187               cpustate->PC = GET_PC;
162               m_PC = GET_PC;
188163            }
189164         }
190165         break;
191166      case 0x20: case 0x22: case 0x24: case 0x26:
192167      case 0x28: case 0x2a: case 0x2c: case 0x2e: /* FIM */
193         cpustate->icount -= 8;
194         cpustate->R[(opcode & 0x0f)>>1] = ROP(cpustate);
168         m_icount -= 8;
169         m_R[(opcode & 0x0f)>>1] = ROP();
195170         break;
196171      case 0x21: case 0x23: case 0x25: case 0x27:
197172      case 0x29: case 0x2b: case 0x2d: case 0x2f: /* SRC */
198         cpustate->RAM.b.l = cpustate->R[(opcode & 0x0f)>>1];
173         m_RAM.b.l = m_R[(opcode & 0x0f)>>1];
199174         break;
200175      case 0x30: case 0x32: case 0x34: case 0x36:
201176      case 0x38: case 0x3a: case 0x3c: case 0x3e: /* FIN */
202         cpustate->icount -= 8;
203         cpustate->R[(opcode & 0x0f)>>1] = READ_ROM(cpustate);
177         m_icount -= 8;
178         m_R[(opcode & 0x0f)>>1] = READ_ROM();
204179         break;
205180      case 0x31: case 0x33: case 0x35: case 0x37:
206181      case 0x39: case 0x3b: case 0x3d: case 0x3f: /* JIN */
207         GET_PC.w.l = (GET_PC.w.l & 0x0f00) | cpustate->R[(opcode & 0x0f)>>1];
208         cpustate->PC = GET_PC;
182         GET_PC.w.l = (GET_PC.w.l & 0x0f00) | m_R[(opcode & 0x0f)>>1];
183         m_PC = GET_PC;
209184         break;
210185      case 0x40: case 0x41: case 0x42: case 0x43:
211186      case 0x44: case 0x45: case 0x46: case 0x47:
212187      case 0x48: case 0x49: case 0x4a: case 0x4b:
213188      case 0x4c: case 0x4d: case 0x4e: case 0x4f: /* JUN */
214         cpustate->icount -= 8;
215         GET_PC.w.l = ((opcode & 0x0f) << 8) | ARG(cpustate);
216         cpustate->PC = GET_PC;
189         m_icount -= 8;
190         GET_PC.w.l = ((opcode & 0x0f) << 8) | ARG();
191         m_PC = GET_PC;
217192         break;
218193      case 0x50: case 0x51: case 0x52: case 0x53:
219194      case 0x54: case 0x55: case 0x56: case 0x57:
220195      case 0x58: case 0x59: case 0x5a: case 0x5b:
221196      case 0x5c: case 0x5d: case 0x5e: case 0x5f: /* JMS */
222197         {
223            UINT16 newPC = ((opcode & 0x0f) << 8) | ARG(cpustate);
224            cpustate->icount -= 8;
225            PUSH_STACK(cpustate);
198            UINT16 newPC = ((opcode & 0x0f) << 8) | ARG();
199            m_icount -= 8;
200            PUSH_STACK();
226201            GET_PC.w.l = newPC;
227            cpustate->PC = GET_PC;
202            m_PC = GET_PC;
228203         }
229204         break;
230205      case 0x60: case 0x61: case 0x62: case 0x63:
231206      case 0x64: case 0x65: case 0x66: case 0x67:
232207      case 0x68: case 0x69: case 0x6a: case 0x6b:
233208      case 0x6c: case 0x6d: case 0x6e: case 0x6f: /* INC */
234         SET_REG(cpustate, opcode & 0x0f, GET_REG(cpustate, opcode & 0x0f) + 1);
209         SET_REG(opcode & 0x0f, GET_REG(opcode & 0x0f) + 1);
235210         break;
236211      case 0x70: case 0x71: case 0x72: case 0x73:
237212      case 0x74: case 0x75: case 0x76: case 0x77:
238213      case 0x78: case 0x79: case 0x7a: case 0x7b:
239214      case 0x7c: case 0x7d: case 0x7e: case 0x7f: /* ISZ */
240215         {
241            UINT8 val = (GET_REG(cpustate, opcode & 0x0f) + 1) & 0xf;
242            UINT16 addr = ARG(cpustate);
243            cpustate->icount -= 8;
244            SET_REG(cpustate, opcode & 0x0f, val);
216            UINT8 val = (GET_REG(opcode & 0x0f) + 1) & 0xf;
217            UINT16 addr = ARG();
218            m_icount -= 8;
219            SET_REG(opcode & 0x0f, val);
245220            if (val!=0) {
246221               GET_PC.w.l = (GET_PC.w.l & 0x0f00) | addr;
247222            }
248            cpustate->PC = GET_PC;
223            m_PC = GET_PC;
249224         }
250225         break;
251226      case 0x80: case 0x81: case 0x82: case 0x83:
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253228      case 0x88: case 0x89: case 0x8a: case 0x8b:
254229      case 0x8c: case 0x8d: case 0x8e: case 0x8f: /* ADD */
255230         {
256            UINT8 acc = cpustate->A + GET_REG(cpustate, opcode & 0x0f) + cpustate->C;
257            cpustate->A = acc & 0x0f;
258            cpustate->C = (acc >> 4) & 1;
231            UINT8 acc = m_A + GET_REG(opcode & 0x0f) + m_C;
232            m_A = acc & 0x0f;
233            m_C = (acc >> 4) & 1;
259234         }
260235         break;
261236      case 0x90: case 0x91: case 0x92: case 0x93:
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263238      case 0x98: case 0x99: case 0x9a: case 0x9b:
264239      case 0x9c: case 0x9d: case 0x9e: case 0x9f: /* SUB */
265240         {
266            UINT8 acc = cpustate->A + (GET_REG(cpustate, opcode & 0x0f) ^ 0x0f) + (cpustate->C ^ 1);
267            cpustate->A = acc & 0x0f;
268            cpustate->C = (acc >> 4) & 1;
241            UINT8 acc = m_A + (GET_REG(opcode & 0x0f) ^ 0x0f) + (m_C ^ 1);
242            m_A = acc & 0x0f;
243            m_C = (acc >> 4) & 1;
269244         }
270245         break;
271246      case 0xa0: case 0xa1: case 0xa2: case 0xa3:
272247      case 0xa4: case 0xa5: case 0xa6: case 0xa7:
273248      case 0xa8: case 0xa9: case 0xaa: case 0xab:
274249      case 0xac: case 0xad: case 0xae: case 0xaf: /* LD */
275         cpustate->A = GET_REG(cpustate, opcode & 0x0f);
250         m_A = GET_REG(opcode & 0x0f);
276251         break;
277252      case 0xb0: case 0xb1: case 0xb2: case 0xb3:
278253      case 0xb4: case 0xb5: case 0xb6: case 0xb7:
279254      case 0xb8: case 0xb9: case 0xba: case 0xbb:
280255      case 0xbc: case 0xbd: case 0xbe: case 0xbf: /* XCH */
281256         {
282            UINT8 temp = cpustate->A;
283            cpustate->A = GET_REG(cpustate, opcode & 0x0f);
284            SET_REG(cpustate, opcode & 0x0f, temp);
257            UINT8 temp = m_A;
258            m_A = GET_REG(opcode & 0x0f);
259            SET_REG(opcode & 0x0f, temp);
285260         }
286261         break;
287262      case 0xc0: case 0xc1: case 0xc2: case 0xc3:
288263      case 0xc4: case 0xc5: case 0xc6: case 0xc7:
289264      case 0xc8: case 0xc9: case 0xca: case 0xcb:
290265      case 0xcc: case 0xcd: case 0xce: case 0xcf: /*  BBL */
291         POP_STACK(cpustate);
292         cpustate->A = opcode & 0x0f;
293         cpustate->PC = GET_PC;
266         POP_STACK();
267         m_A = opcode & 0x0f;
268         m_PC = GET_PC;
294269         break;
295270      case 0xd0: case 0xd1: case 0xd2: case 0xd3:
296271      case 0xd4: case 0xd5: case 0xd6: case 0xd7:
297272      case 0xd8: case 0xd9: case 0xda: case 0xdb:
298273      case 0xdc: case 0xdd: case 0xde: case 0xdf: /* LDM */
299         cpustate->A = opcode & 0x0f;
274         m_A = opcode & 0x0f;
300275         break;
301276      case 0xe0: /* WRM */
302         WM(cpustate,cpustate->A);
277         WM(m_A);
303278         break;
304279      case 0xe1: /* WMP */
305         WMP(cpustate,cpustate->A);
280         WMP(m_A);
306281         break;
307282      case 0xe2: /* WRR */
308         WIO(cpustate,cpustate->A);
283         WIO(m_A);
309284         break;
310285      case 0xe3: /* WPM */
311         WPM(cpustate);
286         WPM();
312287         break;
313288      case 0xe4: /* WR0 */
314         WMS(cpustate,0,cpustate->A);
289         WMS(0,m_A);
315290         break;
316291      case 0xe5: /* WR1 */
317         WMS(cpustate,1,cpustate->A);
292         WMS(1,m_A);
318293         break;
319294      case 0xe6: /* WR2 */
320         WMS(cpustate,2,cpustate->A);
295         WMS(2,m_A);
321296         break;
322297      case 0xe7: /* WR3 */
323         WMS(cpustate,3,cpustate->A);
298         WMS(3,m_A);
324299         break;
325300      case 0xe8: /* SBM */
326         cpustate->A = cpustate->A + (RM(cpustate) ^ 0x0f) + (cpustate->C ^ 1);
327         cpustate->C = cpustate->A >> 4;
328         cpustate->A &= 0x0f;
301         m_A = m_A + (RM() ^ 0x0f) + (m_C ^ 1);
302         m_C = m_A >> 4;
303         m_A &= 0x0f;
329304         break;
330305      case 0xe9: /* RDM */
331         cpustate->A = RM(cpustate);
306         m_A = RM();
332307         break;
333308      case 0xea: /* RDR */
334         cpustate->A = RIO(cpustate);
309         m_A = RIO();
335310         break;
336311      case 0xeb: /* ADM */
337         cpustate->A += RM(cpustate) + cpustate->C;
338         cpustate->C = cpustate->A >> 4;
339         cpustate->A &= 0x0f;
312         m_A += RM() + m_C;
313         m_C = m_A >> 4;
314         m_A &= 0x0f;
340315         break;
341316      case 0xec: /* RD0 */
342         cpustate->A = RMS(cpustate,0);
317         m_A = RMS(0);
343318         break;
344319      case 0xed: /* RD1 */
345         cpustate->A = RMS(cpustate,1);
320         m_A = RMS(1);
346321         break;
347322      case 0xee: /* RD2 */
348         cpustate->A = RMS(cpustate,2);
323         m_A = RMS(2);
349324         break;
350325      case 0xef: /* RD3 */
351         cpustate->A = RMS(cpustate,3);
326         m_A = RMS(3);
352327         break;
353328
354329      case 0xf0: /* CLB */
355         cpustate->A = 0;
356         cpustate->C = 0;
330         m_A = 0;
331         m_C = 0;
357332         break;
358333      case 0xf1: /* CLC */
359         cpustate->C = 0;
334         m_C = 0;
360335         break;
361336      case 0xf2: /* IAC */
362         cpustate->A += 1;
363         cpustate->C = cpustate->A >> 4;
364         cpustate->A &= 0x0f;
337         m_A += 1;
338         m_C = m_A >> 4;
339         m_A &= 0x0f;
365340         break;
366341      case 0xf3: /* CMC */
367         cpustate->C ^= 1;
342         m_C ^= 1;
368343         break;
369344      case 0xf4: /* CMA */
370         cpustate->A ^= 0x0f;
345         m_A ^= 0x0f;
371346         break;
372347      case 0xf5: /* RAL */
373         cpustate->A = (cpustate->A << 1) | cpustate->C;
374         cpustate->C = cpustate->A >> 4;
375         cpustate->A &= 0x0f;
348         m_A = (m_A << 1) | m_C;
349         m_C = m_A >> 4;
350         m_A &= 0x0f;
376351         break;
377352      case 0xf6: /* RAR */
378353         {
379            UINT8 c = cpustate->A & 1;
380            cpustate->A = (cpustate->A >> 1) | (cpustate->C  << 3);
381            cpustate->C = c;
354            UINT8 c = m_A & 1;
355            m_A = (m_A >> 1) | (m_C  << 3);
356            m_C = c;
382357         }
383358         break;
384359      case 0xf7: /* TCC */
385         cpustate->A = cpustate->C;
386         cpustate->C = 0;
360         m_A = m_C;
361         m_C = 0;
387362         break;
388363      case 0xf8: /* DAC */
389         cpustate->A = cpustate->A + 0x0f;
390         cpustate->C = cpustate->A >> 4;
391         cpustate->A &= 0x0f;
364         m_A = m_A + 0x0f;
365         m_C = m_A >> 4;
366         m_A &= 0x0f;
392367         break;
393368      case 0xf9: /* TCS */
394         cpustate->A = cpustate->C ? 10 : 9;
395         cpustate->C = 0;
369         m_A = m_C ? 10 : 9;
370         m_C = 0;
396371         break;
397372      case 0xfa: /* STC */
398         cpustate->C = 1;
373         m_C = 1;
399374         break;
400375      case 0xfb: /* DAA */
401         if (cpustate->C || (cpustate->A > 9)) {
402            cpustate->A += 6;
376         if (m_C || (m_A > 9)) {
377            m_A += 6;
403378         }
404         if (cpustate->A > 0x0f) {
379         if (m_A > 0x0f) {
405380            // it is unaffected if it is in range
406            cpustate->C = 1;
381            m_C = 1;
407382         }
408         cpustate->A &= 0x0f;
383         m_A &= 0x0f;
409384         break;
410385      case 0xfc: /* KBP */
411         cpustate->A = kbp_table[cpustate->A];
386         m_A = kbp_table[m_A];
412387         break;
413388      case 0xfd: /* DCL */
414         cpustate->RAM.b.h = cpustate->A;
389         m_RAM.b.h = m_A;
415390         break;
416391   }
417392}
r23755r23756
421396    COMMON EXECUTION
422397***************************************************************************/
423398
424static CPU_EXECUTE( i4004 )
399void i4004_cpu_device::execute_run()
425400{
426   i4004_state *cpustate = get_safe_token(device);
427
428401   do
429402   {
430      debugger_instruction_hook(device, GET_PC.d);
431      execute_one(cpustate, ROP(cpustate));
403      debugger_instruction_hook(this, GET_PC.d);
404      execute_one(ROP());
432405
433   } while (cpustate->icount > 0);
406   } while (m_icount > 0);
434407}
435408
436409/***************************************************************************
437410    CORE INITIALIZATION
438411***************************************************************************/
439412
440static CPU_INIT( i4004 )
413void i4004_cpu_device::device_start()
441414{
442   i4004_state *cpustate = get_safe_token(device);
443
444415   /* set up the state table */
445416   {
446      device_state_interface *state;
447      device->interface(state);
448      state->state_add(I4004_PC,    "PC",    cpustate->PC.w.l).mask(0x0fff);
449      state->state_add(STATE_GENPC, "GENPC", cpustate->PC.w.l).mask(0x0fff).noshow();
450      state->state_add(STATE_GENFLAGS, "GENFLAGS", cpustate->flags).mask(0x0f).callimport().callexport().noshow().formatstr("%4s");
451      state->state_add(I4004_A,     "A",     cpustate->A).mask(0x0f);
417      state_add(I4004_PC,    "PC",    m_PC.w.l).mask(0x0fff);
418      state_add(STATE_GENPC, "GENPC", m_PC.w.l).mask(0x0fff).noshow();
419      state_add(STATE_GENFLAGS, "GENFLAGS", m_flags).mask(0x0f).callimport().callexport().noshow().formatstr("%4s");
420      state_add(I4004_A,     "A",     m_A).mask(0x0f);
452421
453422      astring tempstr;
454423      for (int regnum = 0; regnum < 8; regnum++)
455         state->state_add(I4004_R01 + regnum, tempstr.format("R%X%X", regnum*2, regnum*2+1), cpustate->R[regnum]);
424      {
425         state_add(I4004_R01 + regnum, tempstr.format("R%X%X", regnum*2, regnum*2+1), m_R[regnum]);
426      }
456427
457428      for (int addrnum = 0; addrnum < 4; addrnum++)
458         state->state_add(I4004_ADDR1 + addrnum, tempstr.format("ADDR%d", addrnum + 1), cpustate->ADDR[addrnum].w.l).mask(0xfff);
429      {
430         state_add(I4004_ADDR1 + addrnum, tempstr.format("ADDR%d", addrnum + 1), m_ADDR[addrnum].w.l).mask(0xfff);
431      }
459432
460      state->state_add(I4004_RAM,   "RAM",   cpustate->RAM.w.l).mask(0x0fff);
433      state_add(I4004_RAM,   "RAM",   m_RAM.w.l).mask(0x0fff);
461434   }
462435
463   cpustate->device = device;
436   m_program = &space(AS_PROGRAM);
437   m_direct = &m_program->direct();
438   m_data = &space(AS_DATA);
439   m_io = &space(AS_IO);
464440
465   cpustate->program = &device->space(AS_PROGRAM);
466   cpustate->direct = &cpustate->program->direct();
467   cpustate->data = &device->space(AS_DATA);
468   cpustate->io = &device->space(AS_IO);
441   save_item(NAME(m_PC));
442   save_item(NAME(m_A));
443   save_item(NAME(m_C));
444   save_item(NAME(m_TEST));
445   save_item(NAME(m_pc_pos));
446   save_item(NAME(m_ADDR[0]));
447   save_item(NAME(m_ADDR[1]));
448   save_item(NAME(m_ADDR[2]));
449   save_item(NAME(m_ADDR[3]));
450   save_item(NAME(m_R[0]));
451   save_item(NAME(m_R[1]));
452   save_item(NAME(m_R[2]));
453   save_item(NAME(m_R[3]));
454   save_item(NAME(m_R[4]));
455   save_item(NAME(m_R[5]));
456   save_item(NAME(m_R[6]));
457   save_item(NAME(m_R[7]));
458   save_item(NAME(m_RAM));
469459
470   device->save_item(NAME(cpustate->PC));
471   device->save_item(NAME(cpustate->A));
472   device->save_item(NAME(cpustate->C));
473   device->save_item(NAME(cpustate->TEST));
474   device->save_item(NAME(cpustate->pc_pos));
475   device->save_item(NAME(cpustate->ADDR[0]));
476   device->save_item(NAME(cpustate->ADDR[1]));
477   device->save_item(NAME(cpustate->ADDR[2]));
478   device->save_item(NAME(cpustate->ADDR[3]));
479   device->save_item(NAME(cpustate->R[0]));
480   device->save_item(NAME(cpustate->R[1]));
481   device->save_item(NAME(cpustate->R[2]));
482   device->save_item(NAME(cpustate->R[3]));
483   device->save_item(NAME(cpustate->R[4]));
484   device->save_item(NAME(cpustate->R[5]));
485   device->save_item(NAME(cpustate->R[6]));
486   device->save_item(NAME(cpustate->R[7]));
487   device->save_item(NAME(cpustate->RAM));
460   m_icountptr = &m_icount;
488461}
489462
490463
491
492464/***************************************************************************
493465    COMMON RESET
494466***************************************************************************/
495467
496static CPU_RESET( i4004 )
468void i4004_cpu_device::device_reset()
497469{
498   i4004_state *cpustate = get_safe_token(device);
470   m_addr_mask = 3;
471   m_C = 0;
472   m_pc_pos = 0;
473   m_A = 0;
474   memset(m_R,0,8);
475   memset(m_ADDR,0,sizeof(m_ADDR));
476   m_RAM.d = 0;
477   m_PC = GET_PC;
499478
500   cpustate->addr_mask = 3;
501   cpustate->C = 0;
502   cpustate->pc_pos = 0;
503   cpustate->A = 0;
504   memset(cpustate->R,0,8);
505   memset(cpustate->ADDR,0,sizeof(cpustate->ADDR));
506   cpustate->RAM.d = 0;
507   cpustate->PC = GET_PC;
508
509479}
510480
511481
r23755r23756
514484    COMMON STATE IMPORT/EXPORT
515485***************************************************************************/
516486
517static CPU_IMPORT_STATE( i4004 )
487void i4004_cpu_device::state_import(const device_state_entry &entry)
518488{
519   i4004_state *cpustate = get_safe_token(device);
520
521489   switch (entry.index())
522490   {
523491      case STATE_GENFLAGS:
524         cpustate->C = (cpustate->flags >> 1) & 1;
525         cpustate->TEST = (cpustate->flags >> 0) & 1;
492         m_C = (m_flags >> 1) & 1;
493         m_TEST = (m_flags >> 0) & 1;
526494         break;
527495   }
528496}
529497
530static CPU_EXPORT_STATE( i4004 )
498void i4004_cpu_device::state_export(const device_state_entry &entry)
531499{
532   i4004_state *cpustate = get_safe_token(device);
533
534500   switch (entry.index())
535501   {
536502      case STATE_GENFLAGS:
537         cpustate->flags = ((cpustate->A == 0) ? 0x04 : 0x00) |
538                        (cpustate->C ? 0x02 : 0x00) |
539                        (cpustate->TEST ? 0x01 : 0x00);
503         m_flags = ((m_A == 0) ? 0x04 : 0x00) |
504                    (m_C ? 0x02 : 0x00) |
505                    (m_TEST ? 0x01 : 0x00);
540506         break;
541507   }
542508}
543509
544static CPU_EXPORT_STRING( i4004 )
510void i4004_cpu_device::state_string_export(const device_state_entry &entry, astring &string)
545511{
546   i4004_state *cpustate = get_safe_token(device);
547
548512   switch (entry.index())
549513   {
550514      case STATE_GENFLAGS:
551515         string.printf(".%c%c%c",
552            (cpustate->A==0) ? 'Z':'.',
553            cpustate->C      ? 'C':'.',
554            cpustate->TEST   ? 'T':'.');
516            (m_A==0) ? 'Z':'.',
517            m_C      ? 'C':'.',
518            m_TEST   ? 'T':'.');
555519         break;
556520   }
557521}
558522
559/***************************************************************************
560    COMMON SET INFO
561***************************************************************************/
562static CPU_SET_INFO( i4004 )
523offs_t i4004_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
563524{
525   extern CPU_DISASSEMBLE( i4004 );
526   return CPU_DISASSEMBLE_NAME(i4004)(this, buffer, pc, oprom, opram, options);
564527}
565528
566/***************************************************************************
567    4004 GET INFO
568***************************************************************************/
569
570CPU_GET_INFO( i4004 )
571{
572   i4004_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
573   switch (state)
574   {
575      /* --- the following bits of info are returned as 64-bit signed integers --- */
576      case CPUINFO_INT_CONTEXT_SIZE:                  info->i = sizeof(i4004_state);          break;
577      case CPUINFO_INT_INPUT_LINES:                   info->i = 0;                            break;
578      case CPUINFO_INT_DEFAULT_IRQ_VECTOR:            info->i = 0;                            break;
579      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;            break;
580      case CPUINFO_INT_CLOCK_MULTIPLIER:              info->i = 1;                            break;
581      case CPUINFO_INT_CLOCK_DIVIDER:                 info->i = 1;                            break;
582      case CPUINFO_INT_MIN_INSTRUCTION_BYTES:         info->i = 1;                            break;
583      case CPUINFO_INT_MAX_INSTRUCTION_BYTES:         info->i = 2;                            break;
584      case CPUINFO_INT_MIN_CYCLES:                    info->i = 8;                            break;
585      case CPUINFO_INT_MAX_CYCLES:                    info->i = 16;                           break;
586
587      case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:            info->i = 8;                            break;
588      case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM:        info->i = 12;                           break;
589      case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM:        info->i = 0;                            break;
590
591      case CPUINFO_INT_DATABUS_WIDTH + AS_DATA:           info->i = 8;                            break;
592      case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA:           info->i = 12;                           break;
593      case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA:           info->i = 0;                            break;
594
595      case CPUINFO_INT_DATABUS_WIDTH + AS_IO:             info->i = 8;                            break; // Only lower 4 bits used
596      case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:             info->i = 6;                            break; // 4 I/O for each ROM chip and 4 OUT for each RAM
597      case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO:             info->i = 0;                            break; // There could be 4 chips in 16 banks for RAM
598
599      /* --- the following bits of info are returned as pointers to functions --- */
600      case CPUINFO_FCT_SET_INFO:      info->setinfo = CPU_SET_INFO_NAME(i4004);               break;
601      case CPUINFO_FCT_INIT:          info->init = CPU_INIT_NAME(i4004);                      break;
602      case CPUINFO_FCT_RESET:         info->reset = CPU_RESET_NAME(i4004);                    break;
603      case CPUINFO_FCT_EXECUTE:       info->execute = CPU_EXECUTE_NAME(i4004);                break;
604      case CPUINFO_FCT_DISASSEMBLE:   info->disassemble = CPU_DISASSEMBLE_NAME(i4004);        break;
605      case CPUINFO_FCT_IMPORT_STATE:  info->import_state = CPU_IMPORT_STATE_NAME(i4004);      break;
606      case CPUINFO_FCT_EXPORT_STATE:  info->export_state = CPU_EXPORT_STATE_NAME(i4004);      break;
607      case CPUINFO_FCT_EXPORT_STRING: info->export_string = CPU_EXPORT_STRING_NAME(i4004);    break;
608
609      /* --- the following bits of info are returned as pointers --- */
610      case CPUINFO_PTR_INSTRUCTION_COUNTER:           info->icount = &cpustate->icount;       break;
611
612      /* --- the following bits of info are returned as NULL-terminated strings --- */
613      case CPUINFO_STR_NAME:                      strcpy(info->s, "4004");                break;
614      case CPUINFO_STR_FAMILY:                    strcpy(info->s, "Intel 4004");          break;
615      case CPUINFO_STR_VERSION:                   strcpy(info->s, "1.0");                 break;
616      case CPUINFO_STR_SOURCE_FILE:               strcpy(info->s, __FILE__);              break;
617      case CPUINFO_STR_CREDITS:                   strcpy(info->s, "Copyright Miodrag Milanovic"); break;
618
619      case CPUINFO_IS_OCTAL:                      info->i = true;                         break;
620   }
621}
622
623DEFINE_LEGACY_CPU_DEVICE(I4004, i4004);
529//      case CPUINFO_IS_OCTAL:                      info->i = true;                         break;
trunk/src/mess/drivers/4004clk.c
r23755r23756
2020      m_dac(*this, "dac")
2121      { }
2222
23   required_device<cpu_device> m_maincpu;
23   required_device<i4004_cpu_device> m_maincpu;
2424   required_device<dac_device> m_dac;
2525   DECLARE_READ8_MEMBER( data_r );
2626   DECLARE_WRITE8_MEMBER( nixie_w );
r23755r23756
130130
131131TIMER_DEVICE_CALLBACK_MEMBER(nixieclock_state::timer_callback)
132132{
133   i4004_set_test(m_maincpu,m_timer);
133   m_maincpu->set_test(m_timer);
134134   m_timer^=1;
135135}
136136
trunk/src/mess/drivers/busicom.c
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182182   m_timer ^=1;
183183   if (m_timer==1) m_drum_index++;
184184   if (m_drum_index==13) m_drum_index=0;
185   i4004_set_test(m_maincpu,m_timer);
185   m_maincpu->set_test(m_timer);
186186
187187}
188188
trunk/src/mess/includes/busicom.h
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77#ifndef BUSICOM_H_
88#define BUSICOM_H_
99
10#include "cpu/i4004/i4004.h"
1011
1112class busicom_state : public driver_device
1213{
r23755r23756
3334   virtual void palette_init();
3435   UINT32 screen_update_busicom(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
3536   TIMER_DEVICE_CALLBACK_MEMBER(timer_callback);
36   required_device<cpu_device> m_maincpu;
37   required_device<i4004_cpu_device> m_maincpu;
3738   UINT8 get_bit_selected(UINT32 val,int num);
3839};
3940

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