trunk/src/mame/drivers/naomi.c
r23729 | r23730 | |
1534 | 1534 | AM_RANGE(0x005f7000, 0x005f70ff) AM_MIRROR(0x02000000) AM_DEVICE16( "rom_board", naomi_board, submap, U64(0x0000ffff0000ffff) ) |
1535 | 1535 | AM_RANGE(0x005f7400, 0x005f74ff) AM_MIRROR(0x02000000) AM_DEVICE32( "rom_board", naomi_g1_device, amap, U64(0xffffffffffffffff) ) |
1536 | 1536 | AM_RANGE(0x005f7800, 0x005f78ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w ) |
1537 | | AM_RANGE(0x005f7c00, 0x005f7cff) AM_MIRROR(0x02000000) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, U64(0xffffffffffffffff)) |
| 1537 | AM_RANGE(0x005f7c00, 0x005f7cff) AM_MIRROR(0x02000000) AM_DEVICE32("powervr2", powervr2_device, pd_dma_map, U64(0xffffffffffffffff)) |
1538 | 1538 | AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff)) |
1539 | 1539 | AM_RANGE(0x00600000, 0x006007ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_modem_r, dc_modem_w ) |
1540 | 1540 | AM_RANGE(0x00700000, 0x00707fff) AM_MIRROR(0x02000000) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w ) |
r23729 | r23730 | |
1586 | 1586 | AM_RANGE(0x005f7000, 0x005f70ff) AM_MIRROR(0x02000000) AM_DEVICE16( "rom_board", naomi_board, submap, U64(0x0000ffff0000ffff) ) |
1587 | 1587 | AM_RANGE(0x005f7400, 0x005f74ff) AM_MIRROR(0x02000000) AM_DEVICE32( "rom_board", naomi_g1_device, amap, U64(0xffffffffffffffff) ) |
1588 | 1588 | AM_RANGE(0x005f7800, 0x005f78ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w ) |
1589 | | AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, U64(0xffffffffffffffff)) |
| 1589 | AM_RANGE(0x005f7c00, 0x005f7cff) AM_MIRROR(0x02000000) AM_DEVICE32("powervr2", powervr2_device, pd_dma_map, U64(0xffffffffffffffff)) |
1590 | 1590 | AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff)) |
1591 | 1591 | AM_RANGE(0x00600000, 0x006007ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_modem_r, dc_modem_w ) |
1592 | 1592 | AM_RANGE(0x00700000, 0x00707fff) AM_MIRROR(0x02000000) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w ) |
r23729 | r23730 | |
1739 | 1739 | AM_RANGE(0x005f7000, 0x005f70ff) AM_MIRROR(0x02000000) AM_DEVICE16( "rom_board", aw_rom_board, submap, U64(0x0000ffff0000ffff) ) |
1740 | 1740 | AM_RANGE(0x005f7400, 0x005f74ff) AM_MIRROR(0x02000000) AM_DEVICE32( "rom_board", naomi_g1_device, amap, U64(0xffffffffffffffff) ) |
1741 | 1741 | AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w ) |
1742 | | AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, U64(0xffffffffffffffff)) |
| 1742 | AM_RANGE(0x005f7c00, 0x005f7cff) AM_MIRROR(0x02000000) AM_DEVICE32("powervr2", powervr2_device, pd_dma_map, U64(0xffffffffffffffff)) |
1743 | 1743 | AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff)) |
1744 | 1744 | AM_RANGE(0x00600000, 0x006007ff) AM_READWRITE(aw_modem_r, aw_modem_w ) |
1745 | 1745 | AM_RANGE(0x00700000, 0x00707fff) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w ) |
trunk/src/mame/video/powervr2.c
r23729 | r23730 | |
86 | 86 | AM_RANGE(0x1000, 0x1fff) AM_READWRITE(palette_r, palette_w) |
87 | 87 | ADDRESS_MAP_END |
88 | 88 | |
| 89 | DEVICE_ADDRESS_MAP_START(pd_dma_map, 32, powervr2_device) |
| 90 | AM_RANGE(0x00, 0x03) AM_READWRITE(sb_pdstap_r, sb_pdstap_w) |
| 91 | AM_RANGE(0x04, 0x07) AM_READWRITE(sb_pdstar_r, sb_pdstar_w) |
| 92 | AM_RANGE(0x08, 0x0b) AM_READWRITE(sb_pdlen_r, sb_pdlen_w) |
| 93 | AM_RANGE(0x0c, 0x0f) AM_READWRITE(sb_pddir_r, sb_pddir_w) |
| 94 | AM_RANGE(0x10, 0x13) AM_READWRITE(sb_pdtsel_r, sb_pdtsel_w) |
| 95 | AM_RANGE(0x14, 0x17) AM_READWRITE(sb_pden_r, sb_pden_w) |
| 96 | AM_RANGE(0x18, 0x1b) AM_READWRITE(sb_pdst_r, sb_pdst_w) |
| 97 | AM_RANGE(0x80, 0x83) AM_READWRITE(sb_pdapro_r, sb_pdapro_w) |
| 98 | ADDRESS_MAP_END |
| 99 | |
89 | 100 | const int powervr2_device::pvr_parconfseq[] = {1,2,3,2,3,4,5,6,5,6,7,8,9,10,11,12,13,14,13,14,15,16,17,16,17,0,0,0,0,0,18,19,20,19,20,21,22,23,22,23}; |
90 | 101 | const int powervr2_device::pvr_wordsvertex[24] = {8,8,8,8,8,16,16,8,8,8, 8, 8,8,8,8,8,16,16, 8,16,16,8,16,16}; |
91 | 102 | const int powervr2_device::pvr_wordspolygon[24] = {8,8,8,8,8, 8, 8,8,8,8,16,16,8,8,8,8, 8, 8,16,16,16,8, 8, 8}; |
r23729 | r23730 | |
1456 | 1467 | machine().primary_screen->configure(spg_hbstart, spg_vbstart, visarea, machine().primary_screen->frame_period().attoseconds ); |
1457 | 1468 | } |
1458 | 1469 | |
| 1470 | |
| 1471 | READ32_MEMBER( powervr2_device::sb_pdstap_r ) |
| 1472 | { |
| 1473 | return sb_pdstap; |
| 1474 | } |
| 1475 | |
| 1476 | WRITE32_MEMBER( powervr2_device::sb_pdstap_w ) |
| 1477 | { |
| 1478 | COMBINE_DATA(&sb_pdstap); |
| 1479 | m_pvr_dma.pvr_addr = sb_pdstap; |
| 1480 | } |
| 1481 | |
| 1482 | READ32_MEMBER( powervr2_device::sb_pdstar_r ) |
| 1483 | { |
| 1484 | return sb_pdstar; |
| 1485 | } |
| 1486 | |
| 1487 | WRITE32_MEMBER( powervr2_device::sb_pdstar_w ) |
| 1488 | { |
| 1489 | COMBINE_DATA(&sb_pdstar); |
| 1490 | m_pvr_dma.sys_addr = sb_pdstar; |
| 1491 | } |
| 1492 | |
| 1493 | READ32_MEMBER( powervr2_device::sb_pdlen_r ) |
| 1494 | { |
| 1495 | return sb_pdlen; |
| 1496 | } |
| 1497 | |
| 1498 | WRITE32_MEMBER( powervr2_device::sb_pdlen_w ) |
| 1499 | { |
| 1500 | COMBINE_DATA(&sb_pdlen); |
| 1501 | m_pvr_dma.size = sb_pdlen; |
| 1502 | } |
| 1503 | |
| 1504 | READ32_MEMBER( powervr2_device::sb_pddir_r ) |
| 1505 | { |
| 1506 | return sb_pddir; |
| 1507 | } |
| 1508 | |
| 1509 | WRITE32_MEMBER( powervr2_device::sb_pddir_w ) |
| 1510 | { |
| 1511 | COMBINE_DATA(&sb_pddir); |
| 1512 | m_pvr_dma.dir = sb_pddir; |
| 1513 | } |
| 1514 | |
| 1515 | READ32_MEMBER( powervr2_device::sb_pdtsel_r ) |
| 1516 | { |
| 1517 | return sb_pdtsel; |
| 1518 | } |
| 1519 | |
| 1520 | WRITE32_MEMBER( powervr2_device::sb_pdtsel_w ) |
| 1521 | { |
| 1522 | COMBINE_DATA(&sb_pdtsel); |
| 1523 | m_pvr_dma.sel = sb_pdtsel & 1; |
| 1524 | } |
| 1525 | |
| 1526 | READ32_MEMBER( powervr2_device::sb_pden_r ) |
| 1527 | { |
| 1528 | return sb_pden; |
| 1529 | } |
| 1530 | |
| 1531 | WRITE32_MEMBER( powervr2_device::sb_pden_w ) |
| 1532 | { |
| 1533 | COMBINE_DATA(&sb_pden); |
| 1534 | m_pvr_dma.flag = sb_pden & 1; |
| 1535 | } |
| 1536 | |
| 1537 | READ32_MEMBER( powervr2_device::sb_pdst_r ) |
| 1538 | { |
| 1539 | return sb_pdst; |
| 1540 | } |
| 1541 | |
| 1542 | WRITE32_MEMBER( powervr2_device::sb_pdst_w ) |
| 1543 | { |
| 1544 | COMBINE_DATA(&sb_pdst); |
| 1545 | |
| 1546 | UINT32 old = m_pvr_dma.start & 1; |
| 1547 | m_pvr_dma.start = sb_pdst & 1; |
| 1548 | |
| 1549 | if(((old & 1) == 0) && m_pvr_dma.flag && m_pvr_dma.start && ((m_pvr_dma.sel & 1) == 0)) // 0 -> 1 |
| 1550 | pvr_dma_execute(space); |
| 1551 | } |
| 1552 | |
| 1553 | READ32_MEMBER( powervr2_device::sb_pdapro_r ) |
| 1554 | { |
| 1555 | return sb_pdapro; |
| 1556 | } |
| 1557 | |
| 1558 | WRITE32_MEMBER( powervr2_device::sb_pdapro_w ) |
| 1559 | { |
| 1560 | COMBINE_DATA(&sb_pdapro); |
| 1561 | } |
| 1562 | |
| 1563 | |
1459 | 1564 | TIMER_CALLBACK_MEMBER(powervr2_device::transfer_opaque_list_irq) |
1460 | 1565 | { |
1461 | 1566 | irq_cb(EOXFER_OPLST_IRQ); |
r23729 | r23730 | |
1804 | 1909 | // SB_LMMODE0 |
1805 | 1910 | WRITE64_MEMBER(powervr2_device::ta_texture_directpath0_w ) |
1806 | 1911 | { |
1807 | | int mode = pvrctrl_regs[SB_LMMODE0]&1; |
| 1912 | // That's not in the pvr control address space, it's in g2's |
| 1913 | // int mode = pvrctrl_regs[SB_LMMODE0]&1; |
| 1914 | int mode = 0; |
1808 | 1915 | if (mode&1) |
1809 | 1916 | { |
1810 | 1917 | printf("ta_texture_directpath0_w 32-bit access!\n"); |
r23729 | r23730 | |
1819 | 1926 | // SB_LMMODE1 |
1820 | 1927 | WRITE64_MEMBER(powervr2_device::ta_texture_directpath1_w ) |
1821 | 1928 | { |
1822 | | int mode = pvrctrl_regs[SB_LMMODE1]&1; |
| 1929 | // That's not in the pvr control address space, it's in g2's |
| 1930 | // int mode = pvrctrl_regs[SB_LMMODE1]&1; |
| 1931 | int mode = 0; |
1823 | 1932 | if (mode&1) |
1824 | 1933 | { |
1825 | 1934 | printf("ta_texture_directpath1_w 32-bit access!\n"); |
r23729 | r23730 | |
2830 | 2939 | |
2831 | 2940 | TIMER_CALLBACK_MEMBER(powervr2_device::pvr_dma_irq) |
2832 | 2941 | { |
2833 | | m_pvr_dma.start = pvrctrl_regs[SB_PDST] = 0; |
| 2942 | m_pvr_dma.start = sb_pdst = 0; |
2834 | 2943 | irq_cb(DMA_PVR_IRQ); |
2835 | 2944 | } |
2836 | 2945 | |
2837 | | READ32_MEMBER(powervr2_device::pvr_ctrl_r) |
2838 | | { |
2839 | | #if DEBUG_PVRCTRL |
2840 | | mame_printf_verbose("PVRCTRL: [%08x] read %x @ %x, mask %x (PC=%x)\n", 0x5f7c00+reg*4, pvrctrl_regs[offset], offset, mem_mask, space.device().safe_pc()); |
2841 | | #endif |
2842 | | |
2843 | | return (UINT64)pvrctrl_regs[offset]; |
2844 | | } |
2845 | | |
2846 | | WRITE32_MEMBER(powervr2_device::pvr_ctrl_w) |
2847 | | { |
2848 | | UINT8 old; |
2849 | | |
2850 | | switch (offset) |
2851 | | { |
2852 | | case SB_PDSTAP: m_pvr_dma.pvr_addr = data; break; |
2853 | | case SB_PDSTAR: m_pvr_dma.sys_addr = data; break; |
2854 | | case SB_PDLEN: m_pvr_dma.size = data; break; |
2855 | | case SB_PDDIR: m_pvr_dma.dir = data & 1; break; |
2856 | | case SB_PDTSEL: |
2857 | | m_pvr_dma.sel = data & 1; |
2858 | | //if(m_pvr_dma.sel & 1) |
2859 | | // printf("Warning: Unsupported irq mode trigger PVR-DMA\n"); |
2860 | | break; |
2861 | | case SB_PDEN: m_pvr_dma.flag = data & 1; break; |
2862 | | case SB_PDST: |
2863 | | old = m_pvr_dma.start & 1; |
2864 | | m_pvr_dma.start = data & 1; |
2865 | | |
2866 | | if(((old & 1) == 0) && m_pvr_dma.flag && m_pvr_dma.start && ((m_pvr_dma.sel & 1) == 0)) // 0 -> 1 |
2867 | | pvr_dma_execute(space); |
2868 | | break; |
2869 | | } |
2870 | | |
2871 | | #if DEBUG_PVRCTRL |
2872 | | mame_printf_verbose("PVRCTRL: [%08x=%x] write %x to %x (reg %x), mask %x\n", 0x5f7c00+reg*4, data, offset, mem_mask); |
2873 | | #endif |
2874 | | |
2875 | | pvrctrl_regs[offset] = data; |
2876 | | } |
2877 | | |
2878 | 2946 | void powervr2_device::pvr_dma_execute(address_space &space) |
2879 | 2947 | { |
2880 | 2948 | UINT32 src,dst,size; |
r23729 | r23730 | |
2923 | 2991 | { |
2924 | 2992 | irq_cb.resolve_safe(); |
2925 | 2993 | |
2926 | | memset(pvrctrl_regs, 0, sizeof(pvrctrl_regs)); |
2927 | 2994 | memset(grab, 0, sizeof(grab)); |
2928 | 2995 | pvr_build_parameterconfig(); |
2929 | 2996 | |
r23729 | r23730 | |
2980 | 3047 | memset(fog_table, 0, sizeof(fog_table)); |
2981 | 3048 | memset(palette, 0, sizeof(palette)); |
2982 | 3049 | |
| 3050 | sb_pdstap = 0; |
| 3051 | sb_pdstar = 0; |
| 3052 | sb_pdlen = 0; |
| 3053 | sb_pddir = 0; |
| 3054 | sb_pdtsel = 0; |
| 3055 | sb_pden = 0; |
| 3056 | sb_pdst = 0; |
| 3057 | sb_pdapro = 0; |
| 3058 | |
2983 | 3059 | save_item(NAME(softreset)); |
2984 | 3060 | save_item(NAME(param_base)); |
2985 | 3061 | save_item(NAME(region_base)); |
r23729 | r23730 | |
3021 | 3097 | save_pointer(NAME(fog_table), 0x80); |
3022 | 3098 | save_pointer(NAME(palette), 0x400); |
3023 | 3099 | |
| 3100 | save_item(NAME(sb_pdstap)); |
| 3101 | save_item(NAME(sb_pdstar)); |
| 3102 | save_item(NAME(sb_pdlen)); |
| 3103 | save_item(NAME(sb_pddir)); |
| 3104 | save_item(NAME(sb_pdtsel)); |
| 3105 | save_item(NAME(sb_pden)); |
| 3106 | save_item(NAME(sb_pdst)); |
| 3107 | save_item(NAME(sb_pdapro)); |
| 3108 | |
3024 | 3109 | save_item(NAME(m_pvr_dma.pvr_addr)); |
3025 | 3110 | save_item(NAME(m_pvr_dma.sys_addr)); |
3026 | 3111 | save_item(NAME(m_pvr_dma.size)); |
r23729 | r23730 | |
3028 | 3113 | save_item(NAME(m_pvr_dma.dir)); |
3029 | 3114 | save_item(NAME(m_pvr_dma.flag)); |
3030 | 3115 | save_item(NAME(m_pvr_dma.start)); |
3031 | | save_pointer(NAME(pvrctrl_regs),0x100/4); |
3032 | 3116 | save_item(NAME(debug_dip_status)); |
3033 | 3117 | save_pointer(NAME(tafifo_buff),32); |
3034 | 3118 | save_item(NAME(scanline)); |
trunk/src/mame/video/powervr2.h
r23729 | r23730 | |
26 | 26 | }; |
27 | 27 | |
28 | 28 | DECLARE_ADDRESS_MAP(ta_map, 32); |
| 29 | DECLARE_ADDRESS_MAP(pd_dma_map, 32); |
29 | 30 | |
30 | 31 | struct { |
31 | 32 | UINT32 pvr_addr; |
r23729 | r23730 | |
114 | 115 | UINT64 *pvr2_framebuffer_ram; |
115 | 116 | UINT64 *elan_ram; |
116 | 117 | |
117 | | |
118 | | UINT32 pvrctrl_regs[0x100/4]; |
119 | 118 | UINT32 debug_dip_status; |
120 | 119 | emu_timer *vbout_timer; |
121 | 120 | emu_timer *vbin_timer; |
r23729 | r23730 | |
220 | 219 | DECLARE_READ32_MEMBER( palette_r ); |
221 | 220 | DECLARE_WRITE32_MEMBER( palette_w ); |
222 | 221 | |
| 222 | DECLARE_READ32_MEMBER( sb_pdstap_r ); |
| 223 | DECLARE_WRITE32_MEMBER( sb_pdstap_w ); |
| 224 | DECLARE_READ32_MEMBER( sb_pdstar_r ); |
| 225 | DECLARE_WRITE32_MEMBER( sb_pdstar_w ); |
| 226 | DECLARE_READ32_MEMBER( sb_pdlen_r ); |
| 227 | DECLARE_WRITE32_MEMBER( sb_pdlen_w ); |
| 228 | DECLARE_READ32_MEMBER( sb_pddir_r ); |
| 229 | DECLARE_WRITE32_MEMBER( sb_pddir_w ); |
| 230 | DECLARE_READ32_MEMBER( sb_pdtsel_r ); |
| 231 | DECLARE_WRITE32_MEMBER( sb_pdtsel_w ); |
| 232 | DECLARE_READ32_MEMBER( sb_pden_r ); |
| 233 | DECLARE_WRITE32_MEMBER( sb_pden_w ); |
| 234 | DECLARE_READ32_MEMBER( sb_pdst_r ); |
| 235 | DECLARE_WRITE32_MEMBER( sb_pdst_w ); |
| 236 | DECLARE_READ32_MEMBER( sb_pdapro_r ); |
| 237 | DECLARE_WRITE32_MEMBER( sb_pdapro_w ); |
223 | 238 | |
224 | | DECLARE_READ32_MEMBER( pvr_ctrl_r ); |
225 | | DECLARE_WRITE32_MEMBER( pvr_ctrl_w ); |
226 | 239 | DECLARE_READ32_MEMBER( pvr_ta_r ); |
227 | 240 | DECLARE_WRITE32_MEMBER( pvr_ta_w ); |
228 | 241 | DECLARE_READ32_MEMBER( pvr2_ta_r ); |
r23729 | r23730 | |
280 | 293 | UINT32 fog_table[0x80]; |
281 | 294 | UINT32 palette[0x400]; |
282 | 295 | |
| 296 | // PD DMA registers |
| 297 | UINT32 sb_pdstap, sb_pdstar, sb_pdlen, sb_pddir, sb_pdtsel, sb_pden, sb_pdst, sb_pdapro; |
| 298 | |
283 | 299 | static UINT32 (*const blend_functions[64])(UINT32 s, UINT32 d); |
284 | 300 | |
285 | 301 | static inline INT32 clamp(INT32 in, INT32 min, INT32 max); |