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r23711 Friday 14th June, 2013 at 17:10:05 UTC by O. Galibert
powervr2: Explode the core/ta registers [O. Galibert]
[src/mame/drivers]naomi.c
[src/mame/includes]dc.h
[src/mame/video]powervr2.c powervr2.h
[src/mess/drivers]dccons.c

trunk/src/mame/drivers/naomi.c
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15351535   AM_RANGE(0x005f7400, 0x005f74ff) AM_MIRROR(0x02000000) AM_DEVICE32( "rom_board", naomi_g1_device, amap, U64(0xffffffffffffffff) )
15361536   AM_RANGE(0x005f7800, 0x005f78ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
15371537   AM_RANGE(0x005f7c00, 0x005f7cff) AM_MIRROR(0x02000000) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, U64(0xffffffffffffffff))
1538   AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w, U64(0xffffffffffffffff))
1538   AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff))
15391539   AM_RANGE(0x00600000, 0x006007ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_modem_r, dc_modem_w )
15401540   AM_RANGE(0x00700000, 0x00707fff) AM_MIRROR(0x02000000) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
15411541   AM_RANGE(0x00710000, 0x0071000f) AM_MIRROR(0x02000000) AM_READWRITE(dc_rtc_r, dc_rtc_w )
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15871587   AM_RANGE(0x005f7400, 0x005f74ff) AM_MIRROR(0x02000000) AM_DEVICE32( "rom_board", naomi_g1_device, amap, U64(0xffffffffffffffff) )
15881588   AM_RANGE(0x005f7800, 0x005f78ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
15891589   AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, U64(0xffffffffffffffff))
1590   AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w, U64(0xffffffffffffffff))
1590   AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff))
15911591   AM_RANGE(0x00600000, 0x006007ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_modem_r, dc_modem_w )
15921592   AM_RANGE(0x00700000, 0x00707fff) AM_MIRROR(0x02000000) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
15931593   AM_RANGE(0x00710000, 0x0071000f) AM_MIRROR(0x02000000) AM_READWRITE(dc_rtc_r, dc_rtc_w )
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15991599
16001600//  AM_RANGE(0x025f6800, 0x025f69ff) AM_READWRITE_LEGACY(dc_sysctrl_r, dc_sysctrl_w ) // second PVR DMA!
16011601//  AM_RANGE(0x025f7c00, 0x025f7cff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, U64(0xffffffffffffffff))
1602   AM_RANGE(0x025f8000, 0x025f9fff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr2_ta_r, pvr2_ta_w, U64(0xffffffffffffffff))
1602   AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff))
16031603
16041604   /* Area 1 */
16051605   AM_RANGE(0x04000000, 0x04ffffff) AM_RAM AM_SHARE("dc_texture_ram")      // texture memory 64 bit access
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16091609
16101610   /* Area 2*/
16111611   AM_RANGE(0x085f6800, 0x085f69ff) AM_WRITE(dc_sysctrl_w ) // writes to BOTH PVRs
1612   AM_RANGE(0x085f8000, 0x085f9fff) AM_DEVWRITE32("powervr2", powervr2_device, pvrs_ta_w, U64(0xffffffffffffffff) ) // writes to BOTH PVRs
1612   AM_RANGE(0x085f8000, 0x805f9fff) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff))
16131613   AM_RANGE(0x08800000, 0x088000ff) AM_DEVREADWRITE32("powervr2", powervr2_device, elan_regs_r, elan_regs_w, U64(0xffffffffffffffff)) // T&L chip registers
16141614//  AM_RANGE(0x09000000, 0x09??????) T&L command processing
16151615   AM_RANGE(0x0a000000, 0x0bffffff) AM_RAM AM_SHARE("elan_ram") // T&L chip RAM
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17401740   AM_RANGE(0x005f7400, 0x005f74ff) AM_MIRROR(0x02000000) AM_DEVICE32( "rom_board", naomi_g1_device, amap, U64(0xffffffffffffffff) )
17411741   AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
17421742   AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, U64(0xffffffffffffffff))
1743   AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w, U64(0xffffffffffffffff))
1743   AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff))
17441744   AM_RANGE(0x00600000, 0x006007ff) AM_READWRITE(aw_modem_r, aw_modem_w )
17451745   AM_RANGE(0x00700000, 0x00707fff) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
17461746   AM_RANGE(0x00710000, 0x0071000f) AM_READWRITE(dc_rtc_r, dc_rtc_w )
trunk/src/mame/video/powervr2.c
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11/*
2    dc.c - Dreamcast video emulation
3
2  Dreamcast video emulation
43*/
54
65#include "emu.h"
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1312
1413const device_type POWERVR2 = &device_creator<powervr2_device>;
1514
15DEVICE_ADDRESS_MAP_START(ta_map, 32, powervr2_device)
16   AM_RANGE(0x0000, 0x0003) AM_READ(     id_r)
17   AM_RANGE(0x0004, 0x0007) AM_READ(     revision_r)
18   AM_RANGE(0x0008, 0x000b) AM_READWRITE(softreset_r,        softreset_w)
19   AM_RANGE(0x0014, 0x0017) AM_WRITE(    startrender_w)
20// 18 = test select
21   AM_RANGE(0x0020, 0x0023) AM_READWRITE(param_base_r,       param_base_w)
22   AM_RANGE(0x002c, 0x002f) AM_READWRITE(region_base_r,      region_base_w)
23// 30 = span sort cfg
24   AM_RANGE(0x0040, 0x0043) AM_READWRITE(vo_border_col_r,    vo_border_col_w)
25   AM_RANGE(0x0044, 0x0047) AM_READWRITE(fb_r_ctrl_r,        fb_r_ctrl_w)
26   AM_RANGE(0x0048, 0x004b) AM_READWRITE(fb_w_ctrl_r,        fb_w_ctrl_w)
27   AM_RANGE(0x004c, 0x004f) AM_READWRITE(fb_w_linestride_r,  fb_w_linestride_w)
28   AM_RANGE(0x0050, 0x0053) AM_READWRITE(fb_r_sof1_r,        fb_r_sof1_w)
29   AM_RANGE(0x0054, 0x0057) AM_READWRITE(fb_r_sof2_r,        fb_r_sof2_w)
30   AM_RANGE(0x005c, 0x005f) AM_READWRITE(fb_r_size_r,        fb_r_size_w)
31   AM_RANGE(0x0060, 0x0063) AM_READWRITE(fb_w_sof1_r,        fb_w_sof1_w)
32   AM_RANGE(0x0064, 0x0067) AM_READWRITE(fb_w_sof2_r,        fb_w_sof2_w)
33   AM_RANGE(0x0068, 0x006b) AM_READWRITE(fb_x_clip_r,        fb_x_clip_w)
34   AM_RANGE(0x006c, 0x006f) AM_READWRITE(fb_y_clip_r,        fb_y_clip_w)
35// 74 = fpu_shad_scale
36// 78 = fpu_cull_val
37   AM_RANGE(0x007c, 0x007f) AM_READWRITE(fpu_param_cfg_r,    fpu_param_cfg_w)
38// 80 = half_offset
39// 84 = fpu_perp_val
40// 88 = isp_backgnd_d
41   AM_RANGE(0x008c, 0x008f) AM_READWRITE(isp_backgnd_t_r,    isp_backgnd_t_w)
42// 98 = isp_feed_cfg
43// a0 = sdram_refresh
44// a4 = sdram_arb_cfg
45// a8 = sdram_cfg
46// b0 = fog_col_ram
47// b4 = fog_col_vert
48// b8 = fog_density
49// bc = fog_clamp_max
50// c0 = fog_clamp_min
51// c4 = spg_trigger_pos
52   AM_RANGE(0x00c8, 0x00cb) AM_READWRITE(spg_hblank_int_r,   spg_hblank_int_w)
53   AM_RANGE(0x00cc, 0x00cf) AM_READWRITE(spg_vblank_int_r,   spg_vblank_int_w)
54// d0 = spg_control
55   AM_RANGE(0x00d4, 0x00d7) AM_READWRITE(spg_hblank_r,       spg_hblank_w)
56   AM_RANGE(0x00d8, 0x00db) AM_READWRITE(spg_load_r,         spg_load_w)
57   AM_RANGE(0x00dc, 0x00df) AM_READWRITE(spg_vblank_r,       spg_vblank_w)
58   AM_RANGE(0x00e0, 0x00e3) AM_READWRITE(spg_width_r,        spg_width_w)
59   AM_RANGE(0x00e4, 0x00e7) AM_READWRITE(text_control_r,     text_control_w)
60   AM_RANGE(0x00e8, 0x00eb) AM_READWRITE(vo_control_r,       vo_control_w)
61   AM_RANGE(0x00ec, 0x00ef) AM_READWRITE(vo_startx_r,        vo_startx_w)
62   AM_RANGE(0x00f0, 0x00f3) AM_READWRITE(vo_starty_r,        vo_starty_w)
63// f4 = scaler_ctl
64   AM_RANGE(0x0108, 0x010b) AM_READWRITE(pal_ram_ctrl_r,     pal_ram_ctrl_w)
65   AM_RANGE(0x010c, 0x010f) AM_READ(     spg_status_r)
66// 110 = fb_burstctrl
67// 118 = y_coeff
68// 11c = pt_alpha_ref
69
70   AM_RANGE(0x0124, 0x0127) AM_READWRITE(ta_ol_base_r,       ta_ol_base_w)
71   AM_RANGE(0x0128, 0x012b) AM_READWRITE(ta_isp_base_r,      ta_isp_base_w)
72   AM_RANGE(0x012c, 0x012f) AM_READWRITE(ta_ol_limit_r,      ta_ol_limit_w)
73   AM_RANGE(0x0130, 0x0133) AM_READWRITE(ta_isp_limit_r,     ta_isp_limit_w)
74   AM_RANGE(0x0134, 0x0137) AM_READ(     ta_next_opb_r)
75   AM_RANGE(0x0138, 0x013b) AM_READ(     ta_itp_current_r)
76// 13c = ta_glob_tile_clip
77   AM_RANGE(0x0140, 0x0143) AM_READWRITE(ta_alloc_ctrl_r,    ta_alloc_ctrl_w)
78   AM_RANGE(0x0144, 0x0147) AM_READWRITE(ta_list_init_r,     ta_list_init_w)
79   AM_RANGE(0x0148, 0x014b) AM_READWRITE(ta_yuv_tex_base_r,  ta_yuv_tex_base_w)
80   AM_RANGE(0x014c, 0x014f) AM_READWRITE(ta_yuv_tex_ctrl_r,  ta_yuv_tex_ctrl_w)
81   AM_RANGE(0x0150, 0x0153) AM_READWRITE(ta_yuv_tex_cnt_r,   ta_yuv_tex_cnt_w)
82   AM_RANGE(0x0160, 0x0163) AM_WRITE(    ta_list_cont_w)
83   AM_RANGE(0x0164, 0x0167) AM_READWRITE(ta_next_opb_init_r, ta_next_opb_init_w)
84
85   AM_RANGE(0x0200, 0x03ff) AM_READWRITE(fog_table_r,        fog_table_w)
86   AM_RANGE(0x1000, 0x1fff) AM_READWRITE(palette_r,          palette_w)
87ADDRESS_MAP_END
88
1689const int powervr2_device::pvr_parconfseq[] = {1,2,3,2,3,4,5,6,5,6,7,8,9,10,11,12,13,14,13,14,15,16,17,16,17,0,0,0,0,0,18,19,20,19,20,21,22,23,22,23};
1790const int powervr2_device::pvr_wordsvertex[24]  = {8,8,8,8,8,16,16,8,8,8, 8, 8,8,8,8,8,16,16, 8,16,16,8,16,16};
1891const int powervr2_device::pvr_wordspolygon[24] = {8,8,8,8,8, 8, 8,8,8,8,16,16,8,8,8,8, 8, 8,16,16,16,8, 8, 8};
1992
2093#define DEBUG_FIFO_POLY (0)
21#define DEBUG_PVRTA (0)
22#define DEBUG_PVRTA_REGS (0)
94#define DEBUG_PVRTA 0
2395#define DEBUG_PVRDLIST  (0)
2496#define DEBUG_PALRAM (1)
2597#define DEBUG_PVRCTRL   (0)
2698
27/* PVR TA macro defines */
28/*
29SPG_HBLANK_INT
30---- --xx xxxx xxxx ---- ---- ---- ---- hblank_in_interrupt
31---- ---- ---- ---- --xx ---- ---- ---- hblank_int_mode
32---- ---- ---- ---- ---- --xx xxxx xxxx line_comp_val
33*/
34#define spg_hblank_in_irq   ((pvrta_regs[SPG_HBLANK_INT] & 0x03ff0000) >> 16)
35#define spg_hblank_in_irq_new   ((pvrta_regs[SPG_HBLANK_INT] & 0x03ff0000) >> 16)
36#define spg_hblank_int_mode ((pvrta_regs[SPG_HBLANK_INT] & 0x00003000) >> 12)
37#define spg_line_comp_val   ((pvrta_regs[SPG_HBLANK_INT] & 0x000003ff) >> 0)
38
39/*
40SPG_VBLANK_INT
41---- --xx xxxx xxxx ---- ---- ---- ---- vblank_out_interrupt_line_number
42---- ---- ---- ---- ---- --xx xxxx xxxx vblank_in_interrupt_line_number
43*/
44#define spg_vblank_out_irq_line_num ((pvrta_regs[SPG_VBLANK_INT] & 0x03ff0000) >> 16)
45#define spg_vblank_in_irq_line_num  ((pvrta_regs[SPG_VBLANK_INT] & 0x000003ff) >> 0)
46#define spg_vblank_out_irq_line_num_new ((pvrta_regs[SPG_VBLANK_INT] & 0x03ff0000) >> 16)
47#define spg_vblank_in_irq_line_num_new  ((pvrta_regs[SPG_VBLANK_INT] & 0x000003ff) >> 0)
48
49
50/*
51VO_BORDER_COL
52---- ---x ---- ---- ---- ---- ---- ---- Chroma ;suchie3 sets 0xff there, maybe it's 8 bits too?
53---- ---- xxxx xxxx ---- ---- ---- ---- Red
54---- ---- ---- ---- xxxx xxxx ---- ---- Green
55---- ---- ---- ---- ---- ---- xxxx xxxx Blue
56*/
57#define vo_border_K ((pvrta_regs[VO_BORDER_COL] & 0x01000000) >> 24)
58#define vo_border_R ((pvrta_regs[VO_BORDER_COL] & 0x00ff0000) >> 16)
59#define vo_border_G ((pvrta_regs[VO_BORDER_COL] & 0x0000ff00) >> 8)
60#define vo_border_B ((pvrta_regs[VO_BORDER_COL] & 0x000000ff) >> 0)
61
62/*
63SPG_HBLANK
64---- ---- --xx xxxx xxxx ---- ---- ---- hbend
65---- ---- ---- ---- ---- --xx xxxx xxxx hbstart
66*/
67#define spg_hbend    ((pvrta_regs[SPG_HBLANK] & 0x03ff0000) >> 16)
68#define spg_hbstart  ((pvrta_regs[SPG_HBLANK] & 0x000003ff) >> 0)
69
70
71/*
72SPG_LOAD
73---- ---- --xx xxxx xxxx ---- ---- ---- vcount
74---- ---- ---- ---- ---- --xx xxxx xxxx hcount
75*/
76#define spg_vcount   ((pvrta_regs[SPG_LOAD] & 0x03ff0000) >> 16)
77#define spg_hcount   ((pvrta_regs[SPG_LOAD] & 0x000003ff) >> 0)
78
79/*
80SPG_VBLANK
81---- ---- --xx xxxx xxxx ---- ---- ---- vbend
82---- ---- ---- ---- ---- --xx xxxx xxxx vbstart
83*/
84#define spg_vbend    ((pvrta_regs[SPG_VBLANK] & 0x03ff0000) >> 16)
85#define spg_vbstart  ((pvrta_regs[SPG_VBLANK] & 0x000003ff) >> 0)
86
87
88/*
89VO_CONTROL
90---- ---- --xx xxxx ---- ---- ---- ---- pclk_delay
91---- ---- ---- ---- ---- ---x ---- ---- pixel_double ;used in test mode
92---- ---- ---- ---- ---- ---- xxxx ---- field_mode
93---- ---- ---- ---- ---- ---- ---- x--- blank_video
94---- ---- ---- ---- ---- ---- ---- -x-- blank_pol
95---- ---- ---- ---- ---- ---- ---- --x- vsync_pol
96---- ---- ---- ---- ---- ---- ---- ---x hsync_pol
97*/
98#define spg_pclk_delay   ((pvrta_regs[VO_CONTROL] & 0x003f0000) >> 16)
99#define spg_pixel_double ((pvrta_regs[VO_CONTROL] & 0x00000100) >> 8)
100#define spg_field_mode   ((pvrta_regs[VO_CONTROL] & 0x000000f0) >> 4)
101#define spg_blank_video  ((pvrta_regs[VO_CONTROL] & 0x00000008) >> 3)
102#define spg_blank_pol    ((pvrta_regs[VO_CONTROL] & 0x00000004) >> 2)
103#define spg_vsync_pol    ((pvrta_regs[VO_CONTROL] & 0x00000002) >> 1)
104#define spg_hsync_pol    ((pvrta_regs[VO_CONTROL] & 0x00000001) >> 0)
105
106/*
107VO_STARTX
108---- ---- ---- ---- ---- ---x xxxx xxxx horzontal start position
109*/
110#define vo_horz_start_pos ((pvrta_regs[VO_STARTX] & 0x000003ff) >> 0)
111
112/*
113VO_STARTY
114---- ---x xxxx xxxx ---- ---- ---- ---- vertical start position on field 2
115---- ---- ---- ---- ---- ---x xxxx xxxx vertical start position on field 1
116*/
117
118#define vo_vert_start_pos_f2 ((pvrta_regs[VO_STARTY] & 0x03ff0000) >> 16)
119#define vo_vert_start_pos_f1 ((pvrta_regs[VO_STARTY] & 0x000003ff) >> 0)
120
121/*
122SPG_STATUS
123---- ---- ---- ---- --x- ---- ---- ---- vsync
124---- ---- ---- ---- ---x ---- ---- ---- hsync
125---- ---- ---- ---- ---- x--- ---- ---- blank
126---- ---- ---- ---- ---- -x-- ---- ---- field number
127---- ---- ---- ---- ---- --xx xxxx xxxx scanline
128*/
129
130
13199// Perform a standard bilinear filter across four pixels
132100inline INT32 powervr2_device::clamp(INT32 in, INT32 min, INT32 max)
133101{
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441409   int off = dilated1[t->cd][xt] + dilated0[t->cd][yt];
442410   int addrp = t->address + (off >> 1);
443411   int c = ((reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(addrp)] >> ((off & 1) << 2)) & 0xf;
444   return cv_1555(pvrta_regs[t->palbase + c]);
412   return cv_1555(palette[t->palbase + c]);
445413}
446414
447415UINT32 powervr2_device::tex_r_p4_1555_vq(texinfo *t, float x, float y)
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451419   int idx = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(t->address + dilated1[t->cd][xt >> 1] + dilated0[t->cd][yt >> 1])];
452420   int addrp = t->vqbase + 8*idx + dilated1[t->cd][xt & 1] + dilated0[t->cd][yt & 3];
453421   int c = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(addrp)] & 0xf;
454   return cv_1555(pvrta_regs[t->palbase + c]);
422   return cv_1555(palette[t->palbase + c]);
455423}
456424
457425UINT32 powervr2_device::tex_r_p4_565_tw(texinfo *t, float x, float y)
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461429   int off = dilated1[t->cd][xt] + dilated0[t->cd][yt];
462430   int addrp = t->address + (off >> 1);
463431   int c = ((reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(addrp)] >> ((off & 1) << 2)) & 0xf;
464   return cv_565(pvrta_regs[t->palbase + c]);
432   return cv_565(palette[t->palbase + c]);
465433}
466434
467435UINT32 powervr2_device::tex_r_p4_565_vq(texinfo *t, float x, float y)
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471439   int idx = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(t->address + dilated1[t->cd][xt >> 1] + dilated0[t->cd][yt >> 1])];
472440   int addrp = t->vqbase + 8*idx + dilated1[t->cd][xt & 1] + dilated0[t->cd][yt & 3];
473441   int c = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(addrp)] & 0xf;
474   return cv_565(pvrta_regs[t->palbase + c]);
442   return cv_565(palette[t->palbase + c]);
475443}
476444
477445UINT32 powervr2_device::tex_r_p4_4444_tw(texinfo *t, float x, float y)
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481449   int off = dilated1[t->cd][xt] + dilated0[t->cd][yt];
482450   int addrp = t->address + (off >> 1);
483451   int c = ((reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(addrp)] >> ((off & 1) << 2)) & 0xf;
484   return cv_4444(pvrta_regs[t->palbase + c]);
452   return cv_4444(palette[t->palbase + c]);
485453}
486454
487455UINT32 powervr2_device::tex_r_p4_4444_vq(texinfo *t, float x, float y)
r23710r23711
491459   int idx = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(t->address + dilated1[t->cd][xt >> 1] + dilated0[t->cd][yt >> 1])];
492460   int addrp = t->vqbase + 8*idx + dilated1[t->cd][xt & 1] + dilated0[t->cd][yt & 3];
493461   int c = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(addrp)] & 0xf;
494   return cv_4444(pvrta_regs[t->palbase + c]);
462   return cv_4444(palette[t->palbase + c]);
495463}
496464
497465UINT32 powervr2_device::tex_r_p4_8888_tw(texinfo *t, float x, float y)
r23710r23711
501469   int off = dilated1[t->cd][xt] + dilated0[t->cd][yt];
502470   int addrp = t->address + (off >> 1);
503471   int c = ((reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(addrp)] >> ((off & 1) << 2)) & 0xf;
504   return pvrta_regs[t->palbase + c];
472   return palette[t->palbase + c];
505473}
506474
507475UINT32 powervr2_device::tex_r_p4_8888_vq(texinfo *t, float x, float y)
r23710r23711
511479   int idx = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(t->address + dilated1[t->cd][xt >> 1] + dilated0[t->cd][yt >> 1])];
512480   int addrp = t->vqbase + 8*idx + dilated1[t->cd][xt & 1] + dilated0[t->cd][yt & 3];
513481   int c = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(addrp)] & 0xf;
514   return pvrta_regs[t->palbase + c];
482   return palette[t->palbase + c];
515483}
516484
517485UINT32 powervr2_device::tex_r_p8_1555_tw(texinfo *t, float x, float y)
r23710r23711
520488   int yt = ((int)y) & (t->sizey-1);
521489   int addrp = t->address + dilated1[t->cd][xt] + dilated0[t->cd][yt];
522490   int c = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(addrp)];
523   return cv_1555(pvrta_regs[t->palbase + c]);
491   return cv_1555(palette[t->palbase + c]);
524492}
525493
526494UINT32 powervr2_device::tex_r_p8_1555_vq(texinfo *t, float x, float y)
r23710r23711
530498   int idx = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(t->address + dilated1[t->cd][xt >> 1] + dilated0[t->cd][yt >> 1])];
531499   int addrp = t->vqbase + 8*idx + dilated1[t->cd][xt & 1] + dilated0[t->cd][yt & 3];
532500   int c = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(addrp)];
533   return cv_1555(pvrta_regs[t->palbase + c]);
501   return cv_1555(palette[t->palbase + c]);
534502}
535503
536504UINT32 powervr2_device::tex_r_p8_565_tw(texinfo *t, float x, float y)
r23710r23711
539507   int yt = ((int)y) & (t->sizey-1);
540508   int addrp = t->address + dilated1[t->cd][xt] + dilated0[t->cd][yt];
541509   int c = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(addrp)];
542   return cv_565(pvrta_regs[t->palbase + c]);
510   return cv_565(palette[t->palbase + c]);
543511}
544512
545513UINT32 powervr2_device::tex_r_p8_565_vq(texinfo *t, float x, float y)
r23710r23711
549517   int idx = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(t->address + dilated1[t->cd][xt >> 1] + dilated0[t->cd][yt >> 1])];
550518   int addrp = t->vqbase + 8*idx + dilated1[t->cd][xt & 1] + dilated0[t->cd][yt & 3];
551519   int c = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(addrp)];
552   return cv_565(pvrta_regs[t->palbase + c]);
520   return cv_565(palette[t->palbase + c]);
553521}
554522
555523UINT32 powervr2_device::tex_r_p8_4444_tw(texinfo *t, float x, float y)
r23710r23711
558526   int yt = ((int)y) & (t->sizey-1);
559527   int addrp = t->address + dilated1[t->cd][xt] + dilated0[t->cd][yt];
560528   int c = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(addrp)];
561   return cv_4444(pvrta_regs[t->palbase + c]);
529   return cv_4444(palette[t->palbase + c]);
562530}
563531
564532UINT32 powervr2_device::tex_r_p8_4444_vq(texinfo *t, float x, float y)
r23710r23711
568536   int idx = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(t->address + dilated1[t->cd][xt >> 1] + dilated0[t->cd][yt >> 1])];
569537   int addrp = t->vqbase + 8*idx + dilated1[t->cd][xt & 1] + dilated0[t->cd][yt & 3];
570538   int c = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(addrp)];
571   return cv_4444(pvrta_regs[t->palbase + c]);
539   return cv_4444(palette[t->palbase + c]);
572540}
573541
574542UINT32 powervr2_device::tex_r_p8_8888_tw(texinfo *t, float x, float y)
r23710r23711
577545   int yt = ((int)y) & (t->sizey-1);
578546   int addrp = t->address + dilated1[t->cd][xt] + dilated0[t->cd][yt];
579547   int c = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(addrp)];
580   return pvrta_regs[t->palbase + c];
548   return palette[t->palbase + c];
581549}
582550
583551UINT32 powervr2_device::tex_r_p8_8888_vq(texinfo *t, float x, float y)
r23710r23711
587555   int idx = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(t->address + dilated1[t->cd][xt >> 1] + dilated0[t->cd][yt >> 1])];
588556   int addrp = t->vqbase + 8*idx + dilated1[t->cd][xt & 1] + dilated0[t->cd][yt & 3];
589557   int c = (reinterpret_cast<UINT8 *>(dc_texture_ram))[BYTE_XOR_LE(addrp)];
590   return pvrta_regs[t->palbase + c];
558   return palette[t->palbase + c];
591559}
592560
593561
r23710r23711
640608
641609
642610   /* Stride select is used only in the non-twiddled case */
643   t->stride = (t->mode & 1) && strideselect ? (pvrta_regs[TEXT_CONTROL] & 0x1f) << 5 : t->sizex;
611   t->stride = (t->mode & 1) && strideselect ? (text_control & 0x1f) << 5 : t->sizex;
644612
645613   t->blend_mode  = blend_mode;
646614   t->filter_mode = filtermode;
r23710r23711
653621   t->vqbase = t->address;
654622   t->blend = use_alpha ? blend_functions[t->blend_mode] : bl10;
655623
656   //  fprintf(stderr, "tex %d %d %d %d\n", t->pf, t->mode, pvrta_regs[PAL_RAM_CTRL], t->mipmapped);
624   //  fprintf(stderr, "tex %d %d %d %d\n", t->pf, t->mode, pal_ram_ctrl, t->mipmapped);
657625
658626   switch(t->pf) {
659627   case 0: // 1555
r23710r23711
707675      break;
708676
709677   case 5: // 4bpp palette
710      t->palbase = 0x400 | ((t->palette & 0x3f) << 4);
678      t->palbase = (t->palette & 0x3f) << 4;
711679      switch(t->mode) {
712680      case 0: case 1:
713681         miptype = 0;
714682
715         switch(pvrta_regs[PAL_RAM_CTRL]) {
683         switch(pal_ram_ctrl) {
716684         case 0: t->r = &powervr2_device::tex_r_p4_1555_tw; break;
717685         case 1: t->r = &powervr2_device::tex_r_p4_565_tw;  break;
718686         case 2: t->r = &powervr2_device::tex_r_p4_4444_tw; break;
r23710r23711
721689         break;
722690      case 2: case 3:
723691         miptype = 3; // ?
724         switch(pvrta_regs[PAL_RAM_CTRL]) {
692         switch(pal_ram_ctrl) {
725693         case 0: t->r = &powervr2_device::tex_r_p4_1555_vq; t->address += 0x800; break;
726694         case 1: t->r = &powervr2_device::tex_r_p4_565_vq;  t->address += 0x800; break;
727695         case 2: t->r = &powervr2_device::tex_r_p4_4444_vq; t->address += 0x800; break;
r23710r23711
736704      break;
737705
738706   case 6: // 8bpp palette
739      t->palbase = 0x400 | ((t->palette & 0x30) << 4);
707      t->palbase = (t->palette & 0x30) << 4;
740708      switch(t->mode) {
741709      case 0: case 1:
742710         miptype = 1;
743711
744         switch(pvrta_regs[PAL_RAM_CTRL]) {
712         switch(pal_ram_ctrl) {
745713         case 0: t->r = &powervr2_device::tex_r_p8_1555_tw; break;
746714         case 1: t->r = &powervr2_device::tex_r_p8_565_tw; break;
747715         case 2: t->r = &powervr2_device::tex_r_p8_4444_tw; break;
r23710r23711
750718         break;
751719      case 2: case 3:
752720         miptype = 3; // ?
753         switch(pvrta_regs[PAL_RAM_CTRL]) {
721         switch(pal_ram_ctrl) {
754722         case 0: t->r = &powervr2_device::tex_r_p8_1555_vq; t->address += 0x800; break;
755723         case 1: t->r = &powervr2_device::tex_r_p8_565_vq;  t->address += 0x800; break;
756724         case 2: t->r = &powervr2_device::tex_r_p8_4444_vq; t->address += 0x800; break;
r23710r23711
860828
861829}
862830
863READ32_MEMBER( powervr2_device::pvr_ta_r )
831READ32_MEMBER( powervr2_device::id_r )
864832{
865   switch (offset)
866   {
867   case SPG_STATUS:
868      {
869         UINT8 fieldnum,vsync,hsync,blank;
833   return 0x17fd11db;
834}
870835
871         fieldnum = (space.machine().primary_screen->frame_number() & 1) ? 1 : 0;
836READ32_MEMBER( powervr2_device::revision_r )
837{
838   return 0x00000011;
839}
872840
873         vsync = space.machine().primary_screen->vblank() ? 1 : 0;
874         if(spg_vsync_pol) { vsync^=1; }
841READ32_MEMBER( powervr2_device::softreset_r )
842{
843   return softreset;
844}
875845
876         hsync = space.machine().primary_screen->hblank() ? 1 : 0;
877         if(spg_hsync_pol) { hsync^=1; }
846WRITE32_MEMBER( powervr2_device::softreset_w )
847{
848   COMBINE_DATA(&softreset);
849   if (softreset & 1) {
850#if DEBUG_PVRTA
851      logerror("%s: TA soft reset\n", tag());
852#endif
853      listtype_used=0;
854   }
855   if (softreset & 2) {
856#if DEBUG_PVRTA
857      logerror("%s: Core Pipeline soft reset\n", tag());
858#endif
859      if (start_render_received == 1) {
860         for (int a=0;a < NUM_BUFFERS;a++)
861            if (grab[a].busy == 1)
862               grab[a].busy = 0;
863         start_render_received = 0;
864      }
865   }
866   if (softreset & 4) {
867#if DEBUG_PVRTA
868      logerror("%s: sdram I/F soft reset\n", tag());
869#endif
870   }
871}
878872
879         /* FIXME: following is just a wild guess */
880         blank = (space.machine().primary_screen->vblank() | space.machine().primary_screen->hblank()) ? 0 : 1;
881         if(spg_blank_pol) { blank^=1; }
873WRITE32_MEMBER( powervr2_device::startrender_w )
874{
875   g_profiler.start(PROFILER_USER1);
876#if DEBUG_PVRTA
877   logerror("%s: Start render, region=%08x, params=%08x\n", tag(), region_base, param_base);
878#endif
882879
883         pvrta_regs[offset] = (vsync << 13) | (hsync << 12) | (blank << 11) | (fieldnum << 10) | (space.machine().primary_screen->vpos() & 0x3ff);
880   // select buffer to draw using param_base
881   for (int a=0;a < NUM_BUFFERS;a++) {
882      if ((grab[a].ispbase == param_base) && (grab[a].valid == 1) && (grab[a].busy == 0)) {
883         grab[a].busy = 1;
884         renderselect = a;
885         start_render_received=1;
886
887
888         grab[a].fbwsof1 = fb_w_sof1;
889         grab[a].fbwsof2 = fb_w_sof2;
890
891         rectangle clip(0, 1023, 0, 1023);
892
893         // we've got a request to draw, so, draw to the accumulation buffer!
894         // this should really be done for each tile!
895         render_to_accumulation_buffer(*fake_accumulationbuffer_bitmap,clip);
896
897         endofrender_timer_isp->adjust(attotime::from_usec(4000) ); // hack, make sure render takes some amount of time
898
899         /* copy the tiles to the framebuffer (really the rendering should be in this loop too) */
900         int sizera = fpu_param_cfg & 0x200000 ? 6 : 5;
901         int offsetra=region_base;
902
903         //printf("base is %08x\n", offsetra);
904
905         // sanity
906         int sanitycount = 0;
907         for (;;) {
908            UINT32 st[6];
909
910            st[0]=space.read_dword((0x05000000+offsetra));
911            st[1]=space.read_dword((0x05000004+offsetra)); // Opaque List Pointer
912            st[2]=space.read_dword((0x05000008+offsetra)); // Opaque Modifier Volume List Pointer
913            st[3]=space.read_dword((0x0500000c+offsetra)); // Translucent List Pointer
914            st[4]=space.read_dword((0x05000010+offsetra)); // Translucent Modifier Volume List Pointer
915
916            if (sizera == 6) {
917               st[5] = space.read_dword((0x05000014+offsetra)); // Punch Through List Pointer
918               offsetra+=0x18;
919            } else   {
920               st[5] = 0;
921               offsetra+=0x14;
922            }
923
924            {
925               int x = ((st[0]&0x000000fc)>>2)*32;
926               int y = ((st[0]&0x00003f00)>>8)*32;
927               //printf("tiledata %08x %d %d - %08x %08x %08x %08x %08x\n",st[0],x,y,st[1],st[2],st[3],st[4],st[5]);
928
929               // should render to the accumulation buffer here using pointers we filled in when processing the data
930               // sent to the TA.  HOWEVER, we don't process the TA data and create the real format object lists, so
931               // instead just use these co-ordinates to copy data from our fake full-screnen accumnulation buffer into
932               // the framebuffer
933
934               pvr_accumulationbuffer_to_framebuffer(space, x,y);
935            }
936
937            if (st[0] & 0x80000000)
938               break;
939
940            // prevent infinite loop if asked to process invalid data
941            if(sanitycount>2000)
942               break;
943         }
884944         break;
885945      }
886   case SPG_TRIGGER_POS:
887      printf("Warning: read at h/v counter ext latches\n");
888      break;
889   case TA_LIST_INIT:
890      return 0; //bit 31 always return 0, a probable left-over in Crazy Taxi reads this and discards the read (?)
891946   }
947}
892948
893   #if DEBUG_PVRTA_REGS
894   if (reg != 0x43)
895      mame_printf_verbose("PVRTA: [%08x] read %x @ %x (reg %x), mask %" I64FMT "x (PC=%x)\n", 0x5f8000+reg*4, pvrta_regs[reg], offset, reg, mem_mask, space.device().safe_pc());
896   #endif
897   return (UINT64)pvrta_regs[offset];
949
950READ32_MEMBER( powervr2_device::param_base_r )
951{
952   return param_base;
898953}
899954
900WRITE32_MEMBER( powervr2_device::pvr_ta_w )
955WRITE32_MEMBER( powervr2_device::param_base_w )
901956{
902   UINT32 sizera,offsetra;
903   int a;
904   int sanitycount;
957   COMBINE_DATA(&param_base);
958}
905959
906   // Dreamcast BIOS attempts to set PVRID to zero and then dies
907   // if it succeeds.  Don't allow.
908   if ((offset != PVRID) && (offset != REVISION))
909   {
910      pvrta_regs[offset] = data; // 5f8000+reg*4=dat
911   }
960READ32_MEMBER( powervr2_device::region_base_r )
961{
962   return region_base;
963}
912964
913   switch (offset)
914   {
915   case SOFTRESET:
916      if (data & 1)
917      {
918         #if DEBUG_PVRTA
919         mame_printf_verbose("pvr_ta_w:  TA soft reset\n");
920         #endif
921         listtype_used=0;
922      }
923      if (data & 2)
924      {
925         #if DEBUG_PVRTA
926         mame_printf_verbose("pvr_ta_w:  Core Pipeline soft reset\n");
927         #endif
928         if (start_render_received == 1)
929         {
930            for (a=0;a < NUM_BUFFERS;a++)
931               if (grab[a].busy == 1)
932                  grab[a].busy = 0;
933            start_render_received = 0;
934         }
935      }
936      if (data & 4)
937      {
938         #if DEBUG_PVRTA
939         mame_printf_verbose("pvr_ta_w:  sdram I/F soft reset\n");
940         #endif
941      }
942      break;
943   case STARTRENDER:
944      g_profiler.start(PROFILER_USER1);
945      #if DEBUG_PVRTA
946      mame_printf_verbose("Start Render Received:\n");
947      mame_printf_verbose("  Region Array at %08x\n",pvrta_regs[REGION_BASE]);
948      mame_printf_verbose("  ISP/TSP Parameters at %08x\n",pvrta_regs[PARAM_BASE]);
965WRITE32_MEMBER( powervr2_device::region_base_w )
966{
967   COMBINE_DATA(&region_base);
968}
949969
950      #endif
951      // select buffer to draw using PARAM_BASE
952      for (a=0;a < NUM_BUFFERS;a++)
953      {
954         if ((grab[a].ispbase == pvrta_regs[PARAM_BASE]) && (grab[a].valid == 1) && (grab[a].busy == 0))
955         {
956            grab[a].busy = 1;
957            renderselect = a;
958            start_render_received=1;
970READ32_MEMBER( powervr2_device::vo_border_col_r )
971{
972   return vo_border_col;
973}
959974
975WRITE32_MEMBER( powervr2_device::vo_border_col_w )
976{
977   COMBINE_DATA(&vo_border_col);
978}
960979
961            grab[a].fbwsof1=pvrta_regs[FB_W_SOF1];
962            grab[a].fbwsof2=pvrta_regs[FB_W_SOF2];
980READ32_MEMBER( powervr2_device::fb_r_ctrl_r )
981{
982   return fb_r_ctrl;
983}
963984
964            rectangle clip(0, 1023, 0, 1023);
985WRITE32_MEMBER( powervr2_device::fb_r_ctrl_w )
986{
987   COMBINE_DATA(&fb_r_ctrl);
988}
965989
966            // we've got a request to draw, so, draw to the accumulation buffer!
967            // this should really be done for each tile!
968            render_to_accumulation_buffer(*fake_accumulationbuffer_bitmap,clip);
990READ32_MEMBER( powervr2_device::fb_w_ctrl_r )
991{
992   return fb_w_ctrl;
993}
969994
970            endofrender_timer_isp->adjust(attotime::from_usec(4000) ); // hack, make sure render takes some amount of time
995WRITE32_MEMBER( powervr2_device::fb_w_ctrl_w )
996{
997   COMBINE_DATA(&fb_w_ctrl);
998}
971999
972            /* copy the tiles to the framebuffer (really the rendering should be in this loop too) */
973            if (pvrta_regs[FPU_PARAM_CFG] & 0x200000)
974               sizera=6;
975            else
976               sizera=5;
977            offsetra=pvrta_regs[REGION_BASE];
1000READ32_MEMBER( powervr2_device::fb_w_linestride_r )
1001{
1002   return fb_w_linestride;
1003}
9781004
979            //printf("base is %08x\n", offsetra);
1005WRITE32_MEMBER( powervr2_device::fb_w_linestride_w )
1006{
1007   COMBINE_DATA(&fb_w_linestride);
1008}
9801009
981            // sanity
982            sanitycount = 0;
983            for (;;)
984            {
985               UINT32 st[6];
1010READ32_MEMBER( powervr2_device::fb_r_sof1_r )
1011{
1012   return fb_r_sof1;
1013}
9861014
987               st[0]=space.read_dword((0x05000000+offsetra));
988               st[1]=space.read_dword((0x05000004+offsetra)); // Opaque List Pointer
989               st[2]=space.read_dword((0x05000008+offsetra)); // Opaque Modifier Volume List Pointer
990               st[3]=space.read_dword((0x0500000c+offsetra)); // Translucent List Pointer
991               st[4]=space.read_dword((0x05000010+offsetra)); // Translucent Modifier Volume List Pointer
1015WRITE32_MEMBER( powervr2_device::fb_r_sof1_w )
1016{
1017   COMBINE_DATA(&fb_r_sof1);
1018}
9921019
993               if (sizera == 6)
994               {
995                  st[5] = space.read_dword((0x05000014+offsetra)); // Punch Through List Pointer
996                  offsetra+=0x18;
997               }
998               else
999               {
1000                  st[5] = 0;
1001                  offsetra+=0x14;
1002               }
1020READ32_MEMBER( powervr2_device::fb_r_sof2_r )
1021{
1022   return fb_r_sof2;
1023}
10031024
1004               {
1005                  int x = ((st[0]&0x000000fc)>>2)*32;
1006                  int y = ((st[0]&0x00003f00)>>8)*32;
1007                  //printf("tiledata %08x %d %d - %08x %08x %08x %08x %08x\n",st[0],x,y,st[1],st[2],st[3],st[4],st[5]);
1025WRITE32_MEMBER( powervr2_device::fb_r_sof2_w )
1026{
1027   COMBINE_DATA(&fb_r_sof2);
1028}
10081029
1009                  // should render to the accumulation buffer here using pointers we filled in when processing the data
1010                  // sent to the TA.  HOWEVER, we don't process the TA data and create the real format object lists, so
1011                  // instead just use these co-ordinates to copy data from our fake full-screnen accumnulation buffer into
1012                  // the framebuffer
1030READ32_MEMBER( powervr2_device::fb_r_size_r )
1031{
1032   return fb_r_size;
1033}
10131034
1014                  pvr_accumulationbuffer_to_framebuffer(space, x,y);
1015               }
1035WRITE32_MEMBER( powervr2_device::fb_r_size_w )
1036{
1037   COMBINE_DATA(&fb_r_size);
1038}
10161039
1017               if (st[0] & 0x80000000)
1018                  break;
1040READ32_MEMBER( powervr2_device::fb_w_sof1_r )
1041{
1042   return fb_w_sof1;
1043}
10191044
1020               // prevent infinite loop if asked to process invalid data
1021               if(sanitycount>2000)
1022                  break;
1023            }
1045WRITE32_MEMBER( powervr2_device::fb_w_sof1_w )
1046{
1047   COMBINE_DATA(&fb_w_sof1);
1048}
10241049
1050READ32_MEMBER( powervr2_device::fb_w_sof2_r )
1051{
1052   return fb_w_sof2;
1053}
10251054
1055WRITE32_MEMBER( powervr2_device::fb_w_sof2_w )
1056{
1057   COMBINE_DATA(&fb_w_sof2);
1058}
10261059
1060READ32_MEMBER( powervr2_device::fb_x_clip_r )
1061{
1062   return fb_x_clip;
1063}
10271064
1065WRITE32_MEMBER( powervr2_device::fb_x_clip_w )
1066{
1067   COMBINE_DATA(&fb_x_clip);
1068}
1069
1070READ32_MEMBER( powervr2_device::fb_y_clip_r )
1071{
1072   return fb_y_clip;
1073}
1074
1075WRITE32_MEMBER( powervr2_device::fb_y_clip_w )
1076{
1077   COMBINE_DATA(&fb_y_clip);
1078}
1079
1080READ32_MEMBER( powervr2_device::fpu_param_cfg_r )
1081{
1082   return fpu_param_cfg;
1083}
1084
1085WRITE32_MEMBER( powervr2_device::fpu_param_cfg_w )
1086{
1087   COMBINE_DATA(&fpu_param_cfg);
1088}
1089
1090READ32_MEMBER( powervr2_device::isp_backgnd_t_r )
1091{
1092   return isp_backgnd_t;
1093}
1094
1095WRITE32_MEMBER( powervr2_device::isp_backgnd_t_w )
1096{
1097   COMBINE_DATA(&isp_backgnd_t);
1098}
1099
1100READ32_MEMBER( powervr2_device::spg_hblank_int_r )
1101{
1102   return spg_hblank_int;
1103}
1104
1105WRITE32_MEMBER( powervr2_device::spg_hblank_int_w )
1106{
1107   COMBINE_DATA(&spg_hblank_int);
1108   /* TODO: timer adjust */
1109}
1110
1111READ32_MEMBER( powervr2_device::spg_vblank_int_r )
1112{
1113   return spg_vblank_int;
1114}
1115
1116WRITE32_MEMBER( powervr2_device::spg_vblank_int_w )
1117{
1118   COMBINE_DATA(&spg_vblank_int);
1119
1120   /* clear pending irqs and modify them with the updated ones */
1121   vbin_timer->adjust(attotime::never);
1122   vbout_timer->adjust(attotime::never);
1123
1124   vbin_timer->adjust(space.machine().primary_screen->time_until_pos(spg_vblank_int & 0x3ff));
1125   vbout_timer->adjust(space.machine().primary_screen->time_until_pos((spg_vblank_int >> 16) & 0x3ff));
1126}
1127
1128READ32_MEMBER( powervr2_device::spg_hblank_r )
1129{
1130   return spg_hblank;
1131}
1132
1133WRITE32_MEMBER( powervr2_device::spg_hblank_w )
1134{
1135   COMBINE_DATA(&spg_hblank);
1136   update_screen_format();
1137}
1138
1139READ32_MEMBER( powervr2_device::spg_load_r )
1140{
1141   return spg_load;
1142}
1143
1144WRITE32_MEMBER( powervr2_device::spg_load_w )
1145{
1146   COMBINE_DATA(&spg_load);
1147   update_screen_format();
1148}
1149
1150READ32_MEMBER( powervr2_device::spg_vblank_r )
1151{
1152   return spg_vblank;
1153}
1154
1155WRITE32_MEMBER( powervr2_device::spg_vblank_w )
1156{
1157   COMBINE_DATA(&spg_vblank);
1158   update_screen_format();
1159}
1160
1161READ32_MEMBER( powervr2_device::spg_width_r )
1162{
1163   return spg_width;
1164}
1165
1166WRITE32_MEMBER( powervr2_device::spg_width_w )
1167{
1168   COMBINE_DATA(&spg_width);
1169   update_screen_format();
1170}
1171
1172READ32_MEMBER( powervr2_device::text_control_r )
1173{
1174   return text_control;
1175}
1176
1177WRITE32_MEMBER( powervr2_device::text_control_w )
1178{
1179   COMBINE_DATA(&text_control);
1180}
1181
1182READ32_MEMBER( powervr2_device::vo_control_r )
1183{
1184   return vo_control;
1185}
1186
1187WRITE32_MEMBER( powervr2_device::vo_control_w )
1188{
1189   COMBINE_DATA(&vo_control);
1190}
1191
1192READ32_MEMBER( powervr2_device::vo_startx_r )
1193{
1194   return vo_startx;
1195}
1196
1197WRITE32_MEMBER( powervr2_device::vo_startx_w )
1198{
1199   COMBINE_DATA(&vo_startx);
1200   update_screen_format();
1201}
1202
1203READ32_MEMBER( powervr2_device::vo_starty_r )
1204{
1205   return vo_starty;
1206}
1207
1208WRITE32_MEMBER( powervr2_device::vo_starty_w )
1209{
1210   COMBINE_DATA(&vo_starty);
1211   update_screen_format();
1212}
1213
1214READ32_MEMBER( powervr2_device::pal_ram_ctrl_r )
1215{
1216   return pal_ram_ctrl;
1217}
1218
1219WRITE32_MEMBER( powervr2_device::pal_ram_ctrl_w )
1220{
1221   COMBINE_DATA(&pal_ram_ctrl);
1222}
1223
1224READ32_MEMBER( powervr2_device::spg_status_r )
1225{
1226   UINT32 fieldnum = (machine().primary_screen->frame_number() & 1) ? 1 : 0;
1227
1228   UINT32 vsync = machine().primary_screen->vblank() ? 1 : 0;
1229   if(vo_control & 2) { vsync^=1; }
1230
1231   UINT32 hsync = machine().primary_screen->hblank() ? 1 : 0;
1232   if(vo_control & 1) { hsync^=1; }
1233
1234   /* FIXME: following is just a wild guess */
1235   UINT32 blank = (machine().primary_screen->vblank() | space.machine().primary_screen->hblank()) ? 0 : 1;
1236   if(vo_control & 4) { blank^=1; }
1237
1238   return (vsync << 13) | (hsync << 12) | (blank << 11) | (fieldnum << 10) | (machine().primary_screen->vpos() & 0x3ff);
1239}
1240
1241
1242READ32_MEMBER( powervr2_device::ta_ol_base_r )
1243{
1244   return ta_ol_base;
1245}
1246
1247WRITE32_MEMBER( powervr2_device::ta_ol_base_w )
1248{
1249   COMBINE_DATA(&ta_ol_base);
1250}
1251
1252READ32_MEMBER( powervr2_device::ta_isp_base_r )
1253{
1254   return ta_isp_base;
1255}
1256
1257WRITE32_MEMBER( powervr2_device::ta_isp_base_w )
1258{
1259   COMBINE_DATA(&ta_isp_base);
1260}
1261
1262READ32_MEMBER( powervr2_device::ta_ol_limit_r )
1263{
1264   return ta_ol_limit;
1265}
1266
1267WRITE32_MEMBER( powervr2_device::ta_ol_limit_w )
1268{
1269   COMBINE_DATA(&ta_ol_limit);
1270}
1271
1272READ32_MEMBER( powervr2_device::ta_isp_limit_r )
1273{
1274   return ta_isp_limit;
1275}
1276
1277WRITE32_MEMBER( powervr2_device::ta_isp_limit_w )
1278{
1279   COMBINE_DATA(&ta_isp_limit);
1280}
1281
1282READ32_MEMBER( powervr2_device::ta_next_opb_r )
1283{
1284   return ta_next_opb;
1285}
1286
1287READ32_MEMBER( powervr2_device::ta_itp_current_r )
1288{
1289   return ta_itp_current;
1290}
1291
1292READ32_MEMBER( powervr2_device::ta_alloc_ctrl_r )
1293{
1294   return ta_alloc_ctrl;
1295}
1296
1297WRITE32_MEMBER( powervr2_device::ta_alloc_ctrl_w )
1298{
1299   COMBINE_DATA(&ta_alloc_ctrl);
1300}
1301
1302READ32_MEMBER( powervr2_device::ta_list_init_r )
1303{
1304   return 0; //bit 31 always return 0, a probable left-over in Crazy Taxi reads this and discards the read (?)
1305}
1306
1307WRITE32_MEMBER( powervr2_device::ta_list_init_w )
1308{
1309   if(data & 0x80000000) {
1310      tafifo_pos=0;
1311      tafifo_mask=7;
1312      tafifo_vertexwords=8;
1313      tafifo_listtype= -1;
1314#if DEBUG_PVRTA
1315      logerror("%s: list init ol=(%08x, %08x) isp=(%08x, %08x), alloc=%08x obp=%08x\n",
1316             tag(), ta_ol_base, ta_ol_limit, ta_isp_base, ta_isp_limit, ta_alloc_ctrl, ta_next_opb_init);
1317#endif
1318      ta_next_opb = ta_next_opb_init;
1319      ta_itp_current = ta_isp_base;
1320      alloc_ctrl_OPB_Mode = ta_alloc_ctrl & 0x100000; // 0 up 1 down
1321      alloc_ctrl_PT_OPB = (4 << ((ta_alloc_ctrl >> 16) & 3)) & 0x38; // number of 32 bit words (0,8,16,32)
1322      alloc_ctrl_TM_OPB = (4 << ((ta_alloc_ctrl >> 12) & 3)) & 0x38;
1323      alloc_ctrl_T_OPB = (4 << ((ta_alloc_ctrl >> 8) & 3)) & 0x38;
1324      alloc_ctrl_OM_OPB = (4 << ((ta_alloc_ctrl >> 4) & 3)) & 0x38;
1325      alloc_ctrl_O_OPB = (4 << ((ta_alloc_ctrl >> 0) & 3)) & 0x38;
1326      listtype_used |= (1+4);
1327      // use ta_isp_base and select buffer for grab data
1328      grabsel = -1;
1329      // try to find already used buffer but not busy
1330      for (int a=0;a < NUM_BUFFERS;a++)
1331         if ((grab[a].ispbase == ta_isp_base) && (grab[a].busy == 0) && (grab[a].valid == 1)) {
1332            grabsel=a;
10281333            break;
10291334         }
1030      }
1031      if (a != NUM_BUFFERS)
1032         break;
1033      assert_always(0, "TA grabber error A!\n");
1034      break;
1035   case TA_LIST_INIT:
1036      if(data & 0x80000000)
1037      {
1038         tafifo_pos=0;
1039         tafifo_mask=7;
1040         tafifo_vertexwords=8;
1041         tafifo_listtype= -1;
1042   #if DEBUG_PVRTA
1043         mame_printf_verbose("TA_OL_BASE       %08x TA_OL_LIMIT  %08x\n", pvrta_regs[TA_OL_BASE], pvrta_regs[TA_OL_LIMIT]);
1044         mame_printf_verbose("TA_ISP_BASE      %08x TA_ISP_LIMIT %08x\n", pvrta_regs[TA_ISP_BASE], pvrta_regs[TA_ISP_LIMIT]);
1045         mame_printf_verbose("TA_ALLOC_CTRL    %08x\n", pvrta_regs[TA_ALLOC_CTRL]);
1046         mame_printf_verbose("TA_NEXT_OPB_INIT %08x\n", pvrta_regs[TA_NEXT_OPB_INIT]);
1047   #endif
1048         pvrta_regs[TA_NEXT_OPB] = pvrta_regs[TA_NEXT_OPB_INIT];
1049         pvrta_regs[TA_ITP_CURRENT] = pvrta_regs[TA_ISP_BASE];
1050         alloc_ctrl_OPB_Mode = pvrta_regs[TA_ALLOC_CTRL] & 0x100000; // 0 up 1 down
1051         alloc_ctrl_PT_OPB = (4 << ((pvrta_regs[TA_ALLOC_CTRL] >> 16) & 3)) & 0x38; // number of 32 bit words (0,8,16,32)
1052         alloc_ctrl_TM_OPB = (4 << ((pvrta_regs[TA_ALLOC_CTRL] >> 12) & 3)) & 0x38;
1053         alloc_ctrl_T_OPB = (4 << ((pvrta_regs[TA_ALLOC_CTRL] >> 8) & 3)) & 0x38;
1054         alloc_ctrl_OM_OPB = (4 << ((pvrta_regs[TA_ALLOC_CTRL] >> 4) & 3)) & 0x38;
1055         alloc_ctrl_O_OPB = (4 << ((pvrta_regs[TA_ALLOC_CTRL] >> 0) & 3)) & 0x38;
1056         listtype_used |= (1+4);
1057         // use TA_ISP_BASE and select buffer for grab data
1058         grabsel = -1;
1059         // try to find already used buffer but not busy
1060         for (a=0;a < NUM_BUFFERS;a++)
1061         {
1062            if ((grab[a].ispbase == pvrta_regs[TA_ISP_BASE]) && (grab[a].busy == 0) && (grab[a].valid == 1))
1063            {
1335
1336      // try a buffer not used yet
1337      if (grabsel < 0)
1338         for (int a=0;a < NUM_BUFFERS;a++)
1339            if (grab[a].valid == 0) {
10641340               grabsel=a;
10651341               break;
10661342            }
1067         }
1068         // try a buffer not used yet
1069         if (grabsel < 0)
1070         {
1071            for (a=0;a < NUM_BUFFERS;a++)
1072            {
1073               if (grab[a].valid == 0)
1074               {
1075                  grabsel=a;
1076                  break;
1077               }
1343
1344      // find a non busy buffer starting from the last one used
1345      if (grabsel < 0)
1346         for (int a=0;a < 3;a++)
1347            if (grab[(grabsellast+1+a) & 3].busy == 0) {
1348               grabsel=a;
1349               break;
10781350            }
1079         }
1080         // find a non busy buffer starting from the last one used
1081         if (grabsel < 0)
1082         {
1083            for (a=0;a < 3;a++)
1084            {
1085               if (grab[(grabsellast+1+a) & 3].busy == 0)
1086               {
1087                  grabsel=a;
1088                  break;
1089               }
1090            }
1091         }
1092         if (grabsel < 0)
1093            assert_always(0, "TA grabber error B!\n");
1094         grabsellast=grabsel;
1095         grab[grabsel].ispbase=pvrta_regs[TA_ISP_BASE];
1096         grab[grabsel].busy=0;
1097         grab[grabsel].valid=1;
1098         grab[grabsel].verts_size=0;
1099         grab[grabsel].strips_size=0;
11001351
1101         g_profiler.stop();
1102      }
1103      break;
1104//#define TA_YUV_TEX_BASE       ((0x005f8148-0x005f8000)/4)
1105   case TA_YUV_TEX_BASE:
1106      printf("TA_YUV_TEX_BASE initialized to %08x\n", data);
1352      if (grabsel < 0)
1353         assert_always(0, "TA grabber error B!\n");
1354      grabsellast=grabsel;
1355      grab[grabsel].ispbase=ta_isp_base;
1356      grab[grabsel].busy=0;
1357      grab[grabsel].valid=1;
1358      grab[grabsel].verts_size=0;
1359      grab[grabsel].strips_size=0;
1360     
1361      g_profiler.stop();
1362   }
1363}
11071364
1108      // hack, this interrupt is generated after transfering a set amount of data
1109      //irq_cb(EOXFER_YUV_IRQ);
11101365
1111      break;
1112   case TA_YUV_TEX_CTRL:
1113      printf("TA_YUV_TEX_CTRL initialized to %08x\n", data);
1114      break;
1366READ32_MEMBER( powervr2_device::ta_yuv_tex_base_r )
1367{
1368   return ta_yuv_tex_base;
1369}
11151370
1116   case SPG_VBLANK_INT:
1117      /* clear pending irqs and modify them with the updated ones */
1118      vbin_timer->adjust(attotime::never);
1119      vbout_timer->adjust(attotime::never);
1371WRITE32_MEMBER( powervr2_device::ta_yuv_tex_base_w )
1372{
1373   COMBINE_DATA(&ta_yuv_tex_base);
1374   logerror("%s: ta_yuv_tex_base = %08x\n", tag(), ta_yuv_tex_base);
11201375
1121      vbin_timer->adjust(space.machine().primary_screen->time_until_pos(spg_vblank_in_irq_line_num));
1122      vbout_timer->adjust(space.machine().primary_screen->time_until_pos(spg_vblank_out_irq_line_num));
1123      break;
1124   /* TODO: timer adjust for SPG_HBLANK_INT too */
1125   case TA_LIST_CONT:
1126   #if DEBUG_PVRTA
1127      mame_printf_verbose("List continuation processing\n");
1128   #endif
1129      if(data & 0x80000000)
1130      {
1131         tafifo_listtype= -1; // no list being received
1132         listtype_used |= (1+4);
1133      }
1134      break;
1135   case SPG_VBLANK:
1136   case SPG_HBLANK:
1137   case SPG_LOAD:
1138   case VO_STARTX:
1139   case VO_STARTY:
1140      {
1141         rectangle visarea = space.machine().primary_screen->visible_area();
1142         /* FIXME: right visible area calculations aren't known yet*/
1143         visarea.min_x = 0;
1144         visarea.max_x = ((spg_hbstart - spg_hbend - vo_horz_start_pos) <= 0x180 ? 320 : 640) - 1;
1145         visarea.min_y = 0;
1146         visarea.max_y = ((spg_vbstart - spg_vbend - vo_vert_start_pos_f1) <= 0x100 ? 240 : 480) - 1;
1376   // hack, this interrupt is generated after transfering a set amount of data
1377   //irq_cb(EOXFER_YUV_IRQ);
1378}
11471379
1380READ32_MEMBER( powervr2_device::ta_yuv_tex_ctrl_r )
1381{
1382   return ta_yuv_tex_ctrl;
1383}
11481384
1149         space.machine().primary_screen->configure(spg_hbstart, spg_vbstart, visarea, space.machine().primary_screen->frame_period().attoseconds );
1150      }
1151      break;
1385WRITE32_MEMBER( powervr2_device::ta_yuv_tex_ctrl_w )
1386{
1387   COMBINE_DATA(&ta_yuv_tex_ctrl);
1388   logerror("%s: ta_yuv_tex_ctrl = %08x\n", tag(), ta_yuv_tex_ctrl);
1389}
1390
1391READ32_MEMBER( powervr2_device::ta_yuv_tex_cnt_r )
1392{
1393   return ta_yuv_tex_cnt;
1394}
1395
1396WRITE32_MEMBER( powervr2_device::ta_yuv_tex_cnt_w )
1397{
1398   COMBINE_DATA(&ta_yuv_tex_cnt);
1399}
1400
1401WRITE32_MEMBER( powervr2_device::ta_list_cont_w )
1402{
1403   if(data & 0x80000000) {
1404      tafifo_listtype= -1; // no list being received
1405      listtype_used |= (1+4);
11521406   }
1407}
11531408
1154   #if DEBUG_PVRTA_REGS
1155   if ((offset != 0x14) && (offset != 0x15))
1156      mame_printf_verbose("PVRTA: [%08x=%x] write %x to %x %x, mask %x\n", 0x5f8000+reg*4, data, offset, (reg*4)+0x8000, mem_mask);
1157   #endif
1409READ32_MEMBER( powervr2_device::ta_next_opb_init_r )
1410{
1411   return ta_next_opb_init;
11581412}
11591413
1414WRITE32_MEMBER( powervr2_device::ta_next_opb_init_w )
1415{
1416   COMBINE_DATA(&ta_next_opb_init);
1417}
1418
1419
1420READ32_MEMBER( powervr2_device::fog_table_r )
1421{
1422   return fog_table[offset];
1423}
1424
1425WRITE32_MEMBER( powervr2_device::fog_table_w )
1426{
1427   COMBINE_DATA(fog_table+offset);
1428}
1429
1430READ32_MEMBER( powervr2_device::palette_r )
1431{
1432   return palette[offset];
1433}
1434
1435WRITE32_MEMBER( powervr2_device::palette_w )
1436{
1437   COMBINE_DATA(palette+offset);
1438}
1439
1440void powervr2_device::update_screen_format()
1441{
1442   INT32 spg_hbstart = spg_hblank & 0x3ff;
1443   INT32 spg_hbend = (spg_hblank >> 16) & 0x3ff;
1444   INT32 spg_vbstart = spg_vblank & 0x3ff;
1445   INT32 spg_vbend = (spg_vblank >> 16) & 0x3ff;
1446   INT32 vo_horz_start_pos = vo_startx & 0x3ff;
1447   INT32 vo_vert_start_pos_f1 = vo_starty & 0x3ff;
1448
1449   rectangle visarea = machine().primary_screen->visible_area();
1450   /* FIXME: right visible area calculations aren't known yet*/
1451   visarea.min_x = 0;
1452   visarea.max_x = ((spg_hbstart - spg_hbend - vo_horz_start_pos) <= 0x180 ? 320 : 640) - 1;
1453   visarea.min_y = 0;
1454   visarea.max_y = ((spg_vbstart - spg_vbend - vo_vert_start_pos_f1) <= 0x100 ? 240 : 480) - 1;
1455
1456   machine().primary_screen->configure(spg_hbstart, spg_vbstart, visarea, machine().primary_screen->frame_period().attoseconds );
1457}
1458
11601459TIMER_CALLBACK_MEMBER(powervr2_device::transfer_opaque_list_irq)
11611460{
11621461   irq_cb(EOXFER_OPLST_IRQ);
r23710r23711
18382137{
18392138   dc_state *state = machine().driver_data<dc_state>();
18402139   address_space &space = state->m_maincpu->space(AS_PROGRAM);
1841   int cs,rs,ns;
1842   UINT32 c;
18432140#if 0
18442141   int stride;
18452142   UINT16 *bmpaddr16;
r23710r23711
18522149
18532150   //printf("drawtest!\n");
18542151
1855   rs=renderselect;
1856   c=pvrta_regs[ISP_BACKGND_T];
1857   c=space.read_dword(0x05000000+((c&0xfffff8)>>1)+(3+3)*4);
2152   int rs=renderselect;
2153   UINT32 c=space.read_dword(0x05000000+((isp_backgnd_t & 0xfffff8)>>1)+(3+3)*4);
18582154   bitmap.fill(c, cliprect);
18592155
18602156
1861   ns=grab[rs].strips_size;
2157   int ns=grab[rs].strips_size;
18622158   if(ns)
18632159      memset(wbuffer, 0x00, sizeof(wbuffer));
18642160
1865   for (cs=0;cs < ns;cs++)
2161   for (int cs=0;cs < ns;cs++)
18662162   {
18672163      strip *ts = &grab[rs].strips[cs];
18682164      int sv = ts->svert;
r23710r23711
19142210   // the standard format for the framebuffer appears to be 565
19152211   // yes, this means colour data is lost in the conversion
19162212
1917   UINT32 wc = pvrta_regs[FB_W_CTRL];
1918   UINT32 stride = pvrta_regs[FB_W_LINESTRIDE];
1919   UINT32 writeoffs = pvrta_regs[FB_W_SOF1];
2213   UINT8 packmode = fb_w_ctrl & 0x7;
19202214
1921   UINT32* src;
1922
1923
1924   UINT8 packmode = wc & 0x7;
1925
19262215   switch (packmode)
19272216   {
19282217      // used by ringout
r23710r23711
19312220         int xcnt,ycnt;
19322221         for (ycnt=0;ycnt<32;ycnt++)
19332222         {
1934            UINT32 realwriteoffs = 0x05000000 + writeoffs + (y+ycnt) * (stride<<3) + (x*2);
1935            src = &fake_accumulationbuffer_bitmap->pix32(y+ycnt, x);
2223            UINT32 realwriteoffs = 0x05000000 + fb_w_sof1 + (y+ycnt) * (fb_w_linestride<<3) + (x*2);
2224            UINT32 *src = &fake_accumulationbuffer_bitmap->pix32(y+ycnt, x);
19362225
19372226
19382227            for (xcnt=0;xcnt<32;xcnt++)
r23710r23711
19552244         int xcnt,ycnt;
19562245         for (ycnt=0;ycnt<32;ycnt++)
19572246         {
1958            UINT32 realwriteoffs = 0x05000000 + writeoffs + (y+ycnt) * (stride<<3) + (x*2);
1959            src = &fake_accumulationbuffer_bitmap->pix32(y+ycnt, x);
2247            UINT32 realwriteoffs = 0x05000000 + fb_w_sof1 + (y+ycnt) * (fb_w_linestride<<3) + (x*2);
2248            UINT32 *src = &fake_accumulationbuffer_bitmap->pix32(y+ycnt, x);
19602249
19612250
19622251            for (xcnt=0;xcnt<32;xcnt++)
r23710r23711
19822271         int xcnt,ycnt;
19832272         for (ycnt=0;ycnt<32;ycnt++)
19842273         {
1985            UINT32 realwriteoffs = 0x05000000 + writeoffs + (y+ycnt) * (stride<<3) + (x*2);
1986            src = &fake_accumulationbuffer_bitmap->pix32(y+ycnt, x);
2274            UINT32 realwriteoffs = 0x05000000 + fb_w_sof1 + (y+ycnt) * (fb_w_linestride<<3) + (x*2);
2275            UINT32 *src = &fake_accumulationbuffer_bitmap->pix32(y+ycnt, x);
19872276
19882277
19892278            for (xcnt=0;xcnt<32;xcnt++)
r23710r23711
20072296         int xcnt,ycnt;
20082297         for (ycnt=0;ycnt<32;ycnt++)
20092298         {
2010            UINT32 realwriteoffs = 0x05000000 + writeoffs + (y+ycnt) * (stride<<3) + (x*2);
2011            src = &fake_accumulationbuffer_bitmap->pix32(y+ycnt, x);
2299            UINT32 realwriteoffs = 0x05000000 + fb_w_sof1 + (y+ycnt) * (fb_w_linestride<<3) + (x*2);
2300            UINT32 *src = &fake_accumulationbuffer_bitmap->pix32(y+ycnt, x);
20122301
20132302
20142303            for (xcnt=0;xcnt<32;xcnt++)
r23710r23711
20342323         int xcnt,ycnt;
20352324         for (ycnt=0;ycnt<32;ycnt++)
20362325         {
2037            UINT32 realwriteoffs = 0x05000000 + writeoffs + (y+ycnt) * (stride<<3) + (x*2);
2038            src = &fake_accumulationbuffer_bitmap->pix32(y+ycnt, x);
2326            UINT32 realwriteoffs = 0x05000000 + fb_w_sof1 + (y+ycnt) * (fb_w_linestride<<3) + (x*2);
2327            UINT32 *src = &fake_accumulationbuffer_bitmap->pix32(y+ycnt, x);
20392328
20402329
20412330            for (xcnt=0;xcnt<32;xcnt++)
r23710r23711
20682357   UINT32 c;
20692358   UINT32 r,g,b;
20702359
2071   UINT32 wc = pvrta_regs[FB_R_CTRL];
2072   UINT8 unpackmode = (wc & 0x0000000c) >>2;  // aka fb_depth
2073   UINT8 enable = (wc & 0x00000001);
2360   UINT8 unpackmode = (fb_r_ctrl & 0x0000000c) >>2;  // aka fb_depth
2361   UINT8 enable = (fb_r_ctrl & 0x00000001);
20742362
20752363   // ??
20762364   if (!enable) return;
20772365
20782366   // only for rgb565 framebuffer
2079   xi=((pvrta_regs[FB_R_SIZE] & 0x3ff)+1) << 1;
2080   dy=((pvrta_regs[FB_R_SIZE] >> 10) & 0x3ff)+1;
2367   xi=((fb_r_size & 0x3ff)+1) << 1;
2368   dy=((fb_r_size >> 10) & 0x3ff)+1;
20812369
20822370   dy++;
20832371   dy*=2; // probably depends on interlace mode, fields etc...
r23710r23711
20882376         // should upsample back to 8-bit output using fb_concat
20892377         for (y=0;y <= dy;y++)
20902378         {
2091            addrp=pvrta_regs[FB_R_SOF1]+y*xi*2;
2092            if(spg_pixel_double)
2379            addrp = fb_r_sof1+y*xi*2;
2380            if(vo_control & 0x100)
20932381            {
20942382               for (x=0;x < xi;x++)
20952383               {
r23710r23711
21322420         // should upsample back to 8-bit output using fb_concat
21332421         for (y=0;y <= dy;y++)
21342422         {
2135            addrp=pvrta_regs[FB_R_SOF1]+y*xi*2;
2136            if(spg_pixel_double)
2423            addrp = fb_r_sof1+y*xi*2;
2424            if(vo_control & 0x100)
21372425            {
21382426               for (x=0;x < xi;x++)
21392427               {
r23710r23711
21772465      case 0x02: ; // 888 RGB 24-bit - suchie3 - HACKED, see pvr_accumulationbuffer_to_framebuffer!
21782466         for (y=0;y <= dy;y++)
21792467         {
2180            addrp=pvrta_regs[FB_R_SOF1]+y*xi*2;
2181            if(spg_pixel_double)
2468            addrp = fb_r_sof1+y*xi*2;
2469            if(vo_control & 0x100)
21822470            {
21832471               for (x=0;x < xi;x++)
21842472               {
r23710r23711
22212509      case 0x03:        // 0888 ARGB 32-bit - HACKED, see pvr_accumulationbuffer_to_framebuffer!
22222510         for (y=0;y <= dy;y++)
22232511         {
2224            addrp=pvrta_regs[FB_R_SOF1]+y*xi*2;
2225            if(spg_pixel_double)
2512            addrp = fb_r_sof1+y*xi*2;
2513            if(vo_control & 0x100)
22262514            {
22272515               for (x=0;x < xi;x++)
22282516               {
r23710r23711
22722560   UINT32 r,g,b;
22732561   int i;
22742562
2275   //popmessage("%02x",pvrta_regs[PAL_RAM_CTRL]);
2563   //popmessage("%02x",pal_ram_ctrl);
22762564
22772565   for(i=0;i<0x400;i++)
22782566   {
2279      pal = pvrta_regs[((0x005F9000-0x005F8000)/4)+i];
2280      switch(pvrta_regs[PAL_RAM_CTRL])
2567      pal = palette[i];
2568      switch(pal_ram_ctrl)
22812569      {
22822570         case 0: //argb1555 <- guilty gear uses this mode
22832571         {
r23710r23711
23572645{
23582646   irq_cb(VBL_IN_IRQ);
23592647
2360   vbin_timer->adjust(machine().primary_screen->time_until_pos(spg_vblank_in_irq_line_num));
2648   vbin_timer->adjust(machine().primary_screen->time_until_pos(spg_vblank_int & 0x3ff));
23612649}
23622650
23632651TIMER_CALLBACK_MEMBER(powervr2_device::vbout)
23642652{
23652653   irq_cb(VBL_OUT_IRQ);
23662654
2367   vbout_timer->adjust(machine().primary_screen->time_until_pos(spg_vblank_out_irq_line_num));
2655   vbout_timer->adjust(machine().primary_screen->time_until_pos((spg_vblank_int >> 16) & 0x3ff));
23682656}
23692657
23702658TIMER_CALLBACK_MEMBER(powervr2_device::hbin)
23712659{
2372   if(spg_hblank_int_mode & 1)
2660   if(spg_hblank_int & 0x1000)
23732661   {
23742662      if(scanline == next_y)
23752663      {
23762664         irq_cb(HBL_IN_IRQ);
2377         next_y+=spg_line_comp_val;
2665         next_y += spg_hblank_int & 0x3ff;
23782666      }
23792667   }
2380   else if((scanline == spg_line_comp_val) || (spg_hblank_int_mode & 2))
2668   else if((scanline == (spg_hblank_int & 0x3ff)) || (spg_hblank_int & 0x2000))
23812669   {
23822670      irq_cb(HBL_IN_IRQ);
23832671   }
r23710r23711
23862674
23872675   scanline++;
23882676
2389   if(scanline >= spg_vblank_in_irq_line_num)
2677   if(scanline >= (spg_vblank_int & 0x3ff))
23902678   {
23912679      scanline = 0;
2392      next_y = spg_line_comp_val;
2680      next_y = spg_hblank_int & 0x3ff;
23932681   }
23942682
2395   hbin_timer->adjust(machine().primary_screen->time_until_pos(scanline, spg_hblank_in_irq-1));
2683   hbin_timer->adjust(machine().primary_screen->time_until_pos(scanline, ((spg_hblank_int >> 16) & 0x3ff)-1));
23962684}
23972685
23982686
r23710r23711
24552743   }
24562744#endif
24572745
2458   bitmap.fill(MAKE_ARGB(0xff,vo_border_R,vo_border_G,vo_border_B), cliprect); //FIXME: Chroma bit?
2746   bitmap.fill(MAKE_ARGB(0xff,
2747                    (vo_border_col >> 16) & 0xff,
2748                    (vo_border_col >> 8 ) & 0xff,
2749                    (vo_border_col      ) & 0xff), cliprect); //FIXME: Chroma bit?
24592750
2460   if(!spg_blank_video)
2751   if(!(vo_control & 8))
24612752      pvr_drawframebuffer(bitmap, cliprect);
24622753
24632754   // update this here so we only do string lookup once per frame
r23710r23711
25322823
25332824WRITE32_MEMBER( powervr2_device::pvrs_ta_w )
25342825{
2535   pvr_ta_w(space,offset,data,mem_mask);
2536   pvr2_ta_w(space,offset,data,mem_mask);
2826   //   pvr_ta_w(space,offset,data,mem_mask);
2827   //   pvr2_ta_w(space,offset,data,mem_mask);
25372828   //printf("PVR2 %08x %08x\n",reg,dat);
25382829}
25392830
r23710r23711
26332924   irq_cb.resolve_safe();
26342925
26352926   memset(pvrctrl_regs, 0, sizeof(pvrctrl_regs));
2636   memset(pvrta_regs, 0, sizeof(pvrta_regs));
26372927   memset(grab, 0, sizeof(grab));
26382928   pvr_build_parameterconfig();
26392929
r23710r23711
26492939
26502940   fake_accumulationbuffer_bitmap = auto_bitmap_rgb32_alloc(machine(),1024,1024);
26512941
2942   softreset = 0;
2943   param_base = 0;
2944   region_base = 0;
2945   vo_border_col = 0;
2946   fb_r_ctrl = 0;
2947   fb_w_ctrl = 0;
2948   fb_w_linestride = 0;
2949   fb_r_sof1 = 0;
2950   fb_r_sof2 = 0;
2951   fb_r_size = 0;
2952   fb_w_sof1 = 0;
2953   fb_w_sof2 = 0;
2954   fb_x_clip = 0;
2955   fb_y_clip = 0;
2956   fpu_param_cfg = 0;
2957   isp_backgnd_t = 0;
2958   spg_hblank_int = 0;
2959   spg_vblank_int = 0;
2960   spg_hblank = 0;
2961   spg_load = 0;
2962   spg_vblank = 0;
2963   spg_width = 0;
2964   vo_control = 0;
2965   vo_startx = 0;
2966   vo_starty = 0;
2967   text_control = 0;
2968   pal_ram_ctrl = 0;
2969   ta_ol_base = 0;
2970   ta_ol_limit = 0;
2971   ta_isp_base = 0;
2972   ta_isp_limit = 0;
2973   ta_next_opb = 0;
2974   ta_itp_current = 0;
2975   ta_alloc_ctrl = 0;
2976   ta_next_opb_init = 0;
2977   ta_yuv_tex_base = 0;
2978   ta_yuv_tex_ctrl = 0;
2979   ta_yuv_tex_cnt = 0;
2980   memset(fog_table, 0, sizeof(fog_table));
2981   memset(palette, 0, sizeof(palette));
2982
2983   save_item(NAME(softreset));
2984   save_item(NAME(param_base));
2985   save_item(NAME(region_base));
2986   save_item(NAME(vo_border_col));
2987   save_item(NAME(fb_r_ctrl));
2988   save_item(NAME(fb_w_ctrl));
2989   save_item(NAME(fb_w_linestride));
2990   save_item(NAME(fb_r_sof1));
2991   save_item(NAME(fb_r_sof2));
2992   save_item(NAME(fb_r_size));
2993   save_item(NAME(fb_w_sof1));
2994   save_item(NAME(fb_w_sof2));
2995   save_item(NAME(fb_x_clip));
2996   save_item(NAME(fb_y_clip));
2997   save_item(NAME(fpu_param_cfg));
2998   save_item(NAME(isp_backgnd_t));
2999   save_item(NAME(spg_hblank_int));
3000   save_item(NAME(spg_vblank_int));
3001   save_item(NAME(spg_hblank));
3002   save_item(NAME(spg_load));
3003   save_item(NAME(spg_vblank));
3004   save_item(NAME(spg_width));
3005   save_item(NAME(vo_control));
3006   save_item(NAME(vo_startx));
3007   save_item(NAME(vo_starty));
3008   save_item(NAME(text_control));
3009   save_item(NAME(pal_ram_ctrl));
3010   save_item(NAME(ta_ol_base));
3011   save_item(NAME(ta_ol_limit));
3012   save_item(NAME(ta_isp_base));
3013   save_item(NAME(ta_isp_limit));
3014   save_item(NAME(ta_next_opb));
3015   save_item(NAME(ta_itp_current));
3016   save_item(NAME(ta_alloc_ctrl));
3017   save_item(NAME(ta_next_opb_init));
3018   save_item(NAME(ta_yuv_tex_base));
3019   save_item(NAME(ta_yuv_tex_ctrl));
3020   save_item(NAME(ta_yuv_tex_cnt));
3021   save_pointer(NAME(fog_table), 0x80);
3022   save_pointer(NAME(palette), 0x400);
3023
26523024   save_item(NAME(m_pvr_dma.pvr_addr));
26533025   save_item(NAME(m_pvr_dma.sys_addr));
26543026   save_item(NAME(m_pvr_dma.size));
r23710r23711
26563028   save_item(NAME(m_pvr_dma.dir));
26573029   save_item(NAME(m_pvr_dma.flag));
26583030   save_item(NAME(m_pvr_dma.start));
2659   save_pointer(NAME(pvrta_regs),0x2000/4);
26603031   save_pointer(NAME(pvrctrl_regs),0x100/4);
26613032   save_item(NAME(debug_dip_status));
26623033   save_pointer(NAME(tafifo_buff),32);
r23710r23711
26663037
26673038void powervr2_device::device_reset()
26683039{
2669   pvrta_regs[VO_CONTROL]=     0x00000108;
2670   pvrta_regs[SOFTRESET]=      0x00000007;
2671   pvrta_regs[VO_STARTX]=      0x0000009d;
2672   pvrta_regs[VO_STARTY]=      0x00150015;
2673   pvrta_regs[SPG_HBLANK]=     0x007e0345;
2674   pvrta_regs[SPG_LOAD]=       0x01060359;
2675   pvrta_regs[SPG_VBLANK]=     0x01500104;
2676   pvrta_regs[SPG_HBLANK_INT]= 0x031d0000;
2677   pvrta_regs[SPG_VBLANK_INT]= 0x01500104;
3040   softreset =                 0x00000007;
3041   vo_control =                0x00000108;
3042   vo_startx =                 0x0000009d;
3043   vo_starty =                 0x00150015;
3044   spg_hblank =                0x007e0345;
3045   spg_load =                  0x01060359;
3046   spg_vblank =                0x01500104;
3047   spg_hblank_int =            0x031d0000;
3048   spg_vblank_int =            0x01500104;
26783049
2679   // if the next 2 registers do not have the correct values, the naomi bios will hang
2680   pvrta_regs[PVRID]=0x17fd11db;
2681   pvrta_regs[REVISION]=0x11;
2682
26833050   tafifo_pos=0;
26843051   tafifo_mask=7;
26853052   tafifo_vertexwords=8;
r23710r23711
26883055   renderselect= -1;
26893056   grabsel=0;
26903057
2691   vbout_timer->adjust(machine().primary_screen->time_until_pos(spg_vblank_out_irq_line_num_new));
2692   vbin_timer->adjust(machine().primary_screen->time_until_pos(spg_vblank_in_irq_line_num_new));
2693   hbin_timer->adjust(machine().primary_screen->time_until_pos(0, spg_hblank_in_irq_new-1));
3058   vbout_timer->adjust(machine().primary_screen->time_until_pos((spg_vblank_int >> 16) & 0x3ff));
3059   vbin_timer->adjust(machine().primary_screen->time_until_pos(spg_vblank_int & 0x3ff));
3060   hbin_timer->adjust(machine().primary_screen->time_until_pos(0, ((spg_hblank_int >> 16) & 0x3ff)-1));
26943061
26953062   scanline = 0;
26963063   next_y = 0;
trunk/src/mame/video/powervr2.h
r23710r23711
2525      DMA_PVR_IRQ
2626   };
2727
28   DECLARE_ADDRESS_MAP(ta_map, 32);
29
2830   struct {
2931      UINT32 pvr_addr;
3032      UINT32 sys_addr;
r23710r23711
112114   UINT64 *pvr2_framebuffer_ram;
113115   UINT64 *elan_ram;
114116
115   UINT32 pvrta_regs[0x2000/4];
117
116118   UINT32 pvrctrl_regs[0x100/4];
117119   UINT32 debug_dip_status;
118120   emu_timer *vbout_timer;
r23710r23711
128130   powervr2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
129131   template<class _cb> void set_irq_cb(_cb cb) { irq_cb.set_callback(cb); }
130132
131   DECLARE_READ32_MEMBER( pvr_ctrl_r );
133   DECLARE_READ32_MEMBER(  id_r );
134   DECLARE_READ32_MEMBER(  revision_r );
135   DECLARE_READ32_MEMBER(  softreset_r );
136   DECLARE_WRITE32_MEMBER( softreset_w );
137   DECLARE_WRITE32_MEMBER( startrender_w );
138   DECLARE_READ32_MEMBER(  param_base_r );
139   DECLARE_WRITE32_MEMBER( param_base_w );
140   DECLARE_READ32_MEMBER(  region_base_r );
141   DECLARE_WRITE32_MEMBER( region_base_w );
142   DECLARE_READ32_MEMBER(  vo_border_col_r );
143   DECLARE_WRITE32_MEMBER( vo_border_col_w );
144   DECLARE_READ32_MEMBER(  fb_r_ctrl_r );
145   DECLARE_WRITE32_MEMBER( fb_r_ctrl_w );
146   DECLARE_READ32_MEMBER(  fb_w_ctrl_r );
147   DECLARE_WRITE32_MEMBER( fb_w_ctrl_w );
148   DECLARE_READ32_MEMBER(  fb_w_linestride_r );
149   DECLARE_WRITE32_MEMBER( fb_w_linestride_w );
150   DECLARE_READ32_MEMBER(  fb_r_sof1_r );
151   DECLARE_WRITE32_MEMBER( fb_r_sof1_w );
152   DECLARE_READ32_MEMBER(  fb_r_sof2_r );
153   DECLARE_WRITE32_MEMBER( fb_r_sof2_w );
154   DECLARE_READ32_MEMBER(  fb_r_size_r );
155   DECLARE_WRITE32_MEMBER( fb_r_size_w );
156   DECLARE_READ32_MEMBER(  fb_w_sof1_r );
157   DECLARE_WRITE32_MEMBER( fb_w_sof1_w );
158   DECLARE_READ32_MEMBER(  fb_w_sof2_r );
159   DECLARE_WRITE32_MEMBER( fb_w_sof2_w );
160   DECLARE_READ32_MEMBER(  fb_x_clip_r );
161   DECLARE_WRITE32_MEMBER( fb_x_clip_w );
162   DECLARE_READ32_MEMBER(  fb_y_clip_r );
163   DECLARE_WRITE32_MEMBER( fb_y_clip_w );
164   DECLARE_READ32_MEMBER(  fpu_param_cfg_r );
165   DECLARE_WRITE32_MEMBER( fpu_param_cfg_w );
166   DECLARE_READ32_MEMBER(  isp_backgnd_t_r );
167   DECLARE_WRITE32_MEMBER( isp_backgnd_t_w );
168   DECLARE_READ32_MEMBER(  spg_hblank_int_r );
169   DECLARE_WRITE32_MEMBER( spg_hblank_int_w );
170   DECLARE_READ32_MEMBER(  spg_vblank_int_r );
171   DECLARE_WRITE32_MEMBER( spg_vblank_int_w );
172   DECLARE_READ32_MEMBER(  spg_hblank_r );
173   DECLARE_WRITE32_MEMBER( spg_hblank_w );
174   DECLARE_READ32_MEMBER(  spg_load_r );
175   DECLARE_WRITE32_MEMBER( spg_load_w );
176   DECLARE_READ32_MEMBER(  spg_vblank_r );
177   DECLARE_WRITE32_MEMBER( spg_vblank_w );
178   DECLARE_READ32_MEMBER(  spg_width_r );
179   DECLARE_WRITE32_MEMBER( spg_width_w );
180   DECLARE_READ32_MEMBER(  text_control_r );
181   DECLARE_WRITE32_MEMBER( text_control_w );
182   DECLARE_READ32_MEMBER(  vo_control_r );
183   DECLARE_WRITE32_MEMBER( vo_control_w );
184   DECLARE_READ32_MEMBER(  vo_startx_r );
185   DECLARE_WRITE32_MEMBER( vo_startx_w );
186   DECLARE_READ32_MEMBER(  vo_starty_r );
187   DECLARE_WRITE32_MEMBER( vo_starty_w );
188   DECLARE_READ32_MEMBER(  pal_ram_ctrl_r );
189   DECLARE_WRITE32_MEMBER( pal_ram_ctrl_w );
190   DECLARE_READ32_MEMBER(  spg_status_r );
191
192   DECLARE_READ32_MEMBER(  ta_ol_base_r );
193   DECLARE_WRITE32_MEMBER( ta_ol_base_w );
194   DECLARE_READ32_MEMBER(  ta_isp_base_r );
195   DECLARE_WRITE32_MEMBER( ta_isp_base_w );
196   DECLARE_READ32_MEMBER(  ta_ol_limit_r );
197   DECLARE_WRITE32_MEMBER( ta_ol_limit_w );
198   DECLARE_READ32_MEMBER(  ta_isp_limit_r );
199   DECLARE_WRITE32_MEMBER( ta_isp_limit_w );
200   DECLARE_READ32_MEMBER(  ta_next_opb_r );
201   DECLARE_READ32_MEMBER(  ta_itp_current_r );
202   DECLARE_READ32_MEMBER(  ta_alloc_ctrl_r );
203   DECLARE_WRITE32_MEMBER( ta_alloc_ctrl_w );
204   DECLARE_READ32_MEMBER(  ta_list_init_r );
205   DECLARE_WRITE32_MEMBER( ta_list_init_w );
206   DECLARE_READ32_MEMBER(  ta_yuv_tex_base_r );
207   DECLARE_WRITE32_MEMBER( ta_yuv_tex_base_w );
208   DECLARE_READ32_MEMBER(  ta_yuv_tex_ctrl_r );
209   DECLARE_WRITE32_MEMBER( ta_yuv_tex_ctrl_w );
210   DECLARE_READ32_MEMBER(  ta_yuv_tex_cnt_r );
211   DECLARE_WRITE32_MEMBER( ta_yuv_tex_cnt_w );
212   DECLARE_READ32_MEMBER(  ta_list_cont_r );
213   DECLARE_WRITE32_MEMBER( ta_list_cont_w );
214   DECLARE_READ32_MEMBER(  ta_next_opb_init_r );
215   DECLARE_WRITE32_MEMBER( ta_next_opb_init_w );
216
217
218   DECLARE_READ32_MEMBER(  fog_table_r );
219   DECLARE_WRITE32_MEMBER( fog_table_w );
220   DECLARE_READ32_MEMBER(  palette_r );
221   DECLARE_WRITE32_MEMBER( palette_w );
222
223
224   DECLARE_READ32_MEMBER(  pvr_ctrl_r );
132225   DECLARE_WRITE32_MEMBER( pvr_ctrl_w );
133   DECLARE_READ32_MEMBER( pvr_ta_r );
226   DECLARE_READ32_MEMBER( pvr_ta_r );
134227   DECLARE_WRITE32_MEMBER( pvr_ta_w );
135   DECLARE_READ32_MEMBER( pvr2_ta_r );
228   DECLARE_READ32_MEMBER( pvr2_ta_r );
136229   DECLARE_WRITE32_MEMBER( pvr2_ta_w );
137   DECLARE_READ32_MEMBER( pvrs_ta_r );
230   DECLARE_READ32_MEMBER( pvrs_ta_r );
138231   DECLARE_WRITE32_MEMBER( pvrs_ta_w );
139   DECLARE_READ32_MEMBER( elan_regs_r );
232   DECLARE_READ32_MEMBER( elan_regs_r );
140233   DECLARE_WRITE32_MEMBER( elan_regs_w );
141234   DECLARE_WRITE64_MEMBER( ta_fifo_poly_w );
142235   DECLARE_WRITE64_MEMBER( ta_fifo_yuv_w );
r23710r23711
166259private:
167260   devcb2_write8 irq_cb;
168261
262   // Core registers
263   UINT32 softreset;
264   UINT32 param_base, region_base;
265   UINT32 vo_border_col;
266   UINT32 fb_r_ctrl, fb_w_ctrl, fb_w_linestride, fb_r_sof1, fb_r_sof2, fb_r_size, fb_w_sof1, fb_w_sof2, fb_x_clip, fb_y_clip;
267   UINT32 fpu_param_cfg;
268   UINT32 isp_backgnd_t;
269   UINT32 spg_hblank_int, spg_vblank_int, spg_hblank, spg_load, spg_vblank, spg_width;
270   UINT32 vo_control, vo_startx, vo_starty;
271   UINT32 text_control;
272   UINT32 pal_ram_ctrl;
273
274   // TA registers
275   UINT32 ta_ol_base, ta_ol_limit, ta_isp_base, ta_isp_limit;
276   UINT32 ta_next_opb, ta_itp_current, ta_alloc_ctrl, ta_next_opb_init;
277   UINT32 ta_yuv_tex_base, ta_yuv_tex_ctrl, ta_yuv_tex_cnt;
278
279   // Other registers
280   UINT32 fog_table[0x80];
281   UINT32 palette[0x400];
282
169283   static UINT32 (*const blend_functions[64])(UINT32 s, UINT32 d);
170284
171285   static inline INT32 clamp(INT32 in, INT32 min, INT32 max);
r23710r23711
298412   void pvr_build_parameterconfig();
299413   void process_ta_fifo();
300414   void debug_paletteram();
415   void update_screen_format();
301416};
302417
303418extern const device_type POWERVR2;
trunk/src/mame/includes/dc.h
r23710r23711
246246#define RTC3        ((0x00710008-0x00710000)/4)
247247
248248
249/*--------------- CORE registers --------------*/
250#define PVRID               ((0x005f8000-0x005f8000)/4)
251#define REVISION            ((0x005f8004-0x005f8000)/4)
252#define SOFTRESET           ((0x005f8008-0x005f8000)/4)
253#define STARTRENDER         ((0x005f8014-0x005f8000)/4)
254#define TEST_SELECT         ((0x005f8018-0x005f8000)/4)
255#define PARAM_BASE          ((0x005f8020-0x005f8000)/4)
256#define REGION_BASE         ((0x005f802c-0x005f8000)/4)
257#define SPAN_SORT_CFG       ((0x005f8030-0x005f8000)/4)
258#define VO_BORDER_COL       ((0x005f8040-0x005f8000)/4)
259#define FB_R_CTRL           ((0x005f8044-0x005f8000)/4)
260#define FB_W_CTRL           ((0x005f8048-0x005f8000)/4)
261#define FB_W_LINESTRIDE     ((0x005f804c-0x005f8000)/4)
262#define FB_R_SOF1           ((0x005f8050-0x005f8000)/4)
263#define FB_R_SOF2           ((0x005f8054-0x005f8000)/4)
264#define FB_R_SIZE           ((0x005f805c-0x005f8000)/4)
265#define FB_W_SOF1           ((0x005f8060-0x005f8000)/4)
266#define FB_W_SOF2           ((0x005f8064-0x005f8000)/4)
267#define FB_X_CLIP           ((0x005f8068-0x005f8000)/4)
268#define FB_Y_CLIP           ((0x005f806c-0x005f8000)/4)
269#define FPU_SHAD_SCALE      ((0x005f8074-0x005f8000)/4)
270#define FPU_CULL_VAL        ((0x005f8078-0x005f8000)/4)
271#define FPU_PARAM_CFG       ((0x005f807c-0x005f8000)/4)
272#define HALF_OFFSET         ((0x005f8080-0x005f8000)/4)
273#define FPU_PERP_VAL        ((0x005f8084-0x005f8000)/4)
274#define ISP_BACKGND_D       ((0x005f8088-0x005f8000)/4)
275#define ISP_BACKGND_T       ((0x005f808c-0x005f8000)/4)
276#define ISP_FEED_CFG        ((0x005f8098-0x005f8000)/4)
277#define SDRAM_REFRESH       ((0x005f80a0-0x005f8000)/4)
278#define SDRAM_ARB_CFG       ((0x005f80a4-0x005f8000)/4)
279#define SDRAM_CFG           ((0x005f80a8-0x005f8000)/4)
280#define FOG_COL_RAM         ((0x005f80b0-0x005f8000)/4)
281#define FOG_COL_VERT        ((0x005f80b4-0x005f8000)/4)
282#define FOG_DENSITY         ((0x005f80b8-0x005f8000)/4)
283#define FOG_CLAMP_MAX       ((0x005f80bc-0x005f8000)/4)
284#define FOG_CLAMP_MIN       ((0x005f80c0-0x005f8000)/4)
285#define SPG_TRIGGER_POS     ((0x005f80c4-0x005f8000)/4)
286#define SPG_HBLANK_INT      ((0x005f80c8-0x005f8000)/4)
287#define SPG_VBLANK_INT      ((0x005f80cc-0x005f8000)/4)
288#define SPG_CONTROL         ((0x005f80d0-0x005f8000)/4)
289#define SPG_HBLANK          ((0x005f80d4-0x005f8000)/4)
290#define SPG_LOAD            ((0x005f80d8-0x005f8000)/4)
291#define SPG_VBLANK          ((0x005f80dc-0x005f8000)/4)
292#define SPG_WIDTH           ((0x005f80e0-0x005f8000)/4)
293#define TEXT_CONTROL        ((0x005f80e4-0x005f8000)/4)
294#define VO_CONTROL          ((0x005f80e8-0x005f8000)/4)
295#define VO_STARTX           ((0x005f80ec-0x005f8000)/4)
296#define VO_STARTY           ((0x005f80f0-0x005f8000)/4)
297#define SCALER_CTL          ((0x005f80f4-0x005f8000)/4)
298#define PAL_RAM_CTRL        ((0x005f8108-0x005f8000)/4)
299#define ISP_BACKGND_T       ((0x005f808c-0x005f8000)/4)
300#define SPG_STATUS          ((0x005f810c-0x005f8000)/4)
301#define FB_BURSTCTRL        ((0x005f8110-0x005f8000)/4)
302#define Y_COEFF             ((0x005f8118-0x005f8000)/4)
303#define PT_ALPHA_REF        ((0x005f811c-0x005f8000)/4)
304/* 0x005f8200 - 0x005f83ff fog_table */
305/* 0x005f9000 - 0x005f9fff palette_ram */
306
307/*--------- Tile Accelerator registers ---------*/
308#define TA_OL_BASE          ((0x005f8124-0x005f8000)/4)
309#define TA_ISP_BASE         ((0x005f8128-0x005f8000)/4)
310#define TA_OL_LIMIT         ((0x005f812c-0x005f8000)/4)
311#define TA_ISP_LIMIT        ((0x005f8130-0x005f8000)/4)
312#define TA_NEXT_OPB         ((0x005f8134-0x005f8000)/4)
313#define TA_ITP_CURRENT      ((0x005f8138-0x005f8000)/4)
314#define TA_GLOB_TILE_CLIP   ((0x005f813c-0x005f8000)/4)
315#define TA_ALLOC_CTRL       ((0x005f8140-0x005f8000)/4)
316#define TA_LIST_INIT        ((0x005f8144-0x005f8000)/4)
317#define TA_YUV_TEX_BASE     ((0x005f8148-0x005f8000)/4)
318#define TA_YUV_TEX_CTRL     ((0x005f814c-0x005f8000)/4)
319#define TA_YUV_TEX_CNT      ((0x005f8150-0x005f8000)/4)
320#define TA_LIST_CONT        ((0x005f8160-0x005f8000)/4)
321#define TA_NEXT_OPB_INIT    ((0x005f8164-0x005f8000)/4)
322/* 0x005f8600 - 0x005f8f5c TA_OL_POINTERS (read only) */
323
324249/* ------------- normal interrupts ------------- */
325250#define IST_EOR_VIDEO    0x00000001
326251#define IST_EOR_ISP      0x00000002
trunk/src/mess/drivers/dccons.c
r23710r23711
119119   AM_RANGE(0x005f7400, 0x005f74ff) AM_READWRITE(dc_mess_g1_ctrl_r, dc_mess_g1_ctrl_w )
120120   AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
121121   AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, U64(0xffffffffffffffff))
122   AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w, U64(0xffffffffffffffff))
122   AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff))
123123   AM_RANGE(0x00600000, 0x006007ff) AM_READWRITE(dc_modem_r, dc_modem_w )
124124   AM_RANGE(0x00700000, 0x00707fff) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
125125   AM_RANGE(0x00710000, 0x0071000f) AM_READWRITE(dc_rtc_r, dc_rtc_w )

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