trunk/src/mess/machine/cs4031.c
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| 82 | 82 | /* 1f */ "RESERVED" |
| 83 | 83 | }; |
| 84 | 84 | |
| 85 | const float cs4031_device::m_dma_clock_divider[] = |
| 86 | { |
| 87 | 10, 8, 6, 0, 0, 0, 0, 0, 5, 4, 3, 2.5, 2, 1.5, 0, 0 |
| 88 | }; |
| 89 | |
| 85 | 90 | //------------------------------------------------- |
| 86 | 91 | // machine_config_additions - device-specific |
| 87 | 92 | // machine configurations |
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| 159 | 164 | }; |
| 160 | 165 | |
| 161 | 166 | static MACHINE_CONFIG_FRAGMENT( cs4031 ) |
| 162 | | MCFG_I8237_ADD("dma1", XTAL_14_31818MHz/3 /* todo: set to 0, instead set via config register */, dma1_config) |
| 163 | | MCFG_I8237_ADD("dma2", XTAL_14_31818MHz/3 /* todo: set to 0, instead set via config register */, dma2_config) |
| 167 | MCFG_I8237_ADD("dma1", 0, dma1_config) |
| 168 | MCFG_I8237_ADD("dma2", 0, dma2_config) |
| 164 | 169 | MCFG_PIC8259_ADD("intc1", WRITELINE(cs4031_device, intc1_int_w), VCC, READ8(cs4031_device, intc1_slave_ack_r)) |
| 165 | 170 | MCFG_PIC8259_ADD("intc2", DEVWRITELINE("intc1", pic8259_device, ir2_w), GND, NULL) |
| 166 | 171 | MCFG_PIT8254_ADD("ctc", cs4031_pit_config) |
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| 330 | 335 | update_read_regions(); |
| 331 | 336 | update_write_regions(); |
| 332 | 337 | |
| 338 | // initialize dma controller clocks |
| 339 | update_dma_clock(); |
| 333 | 340 | } |
| 334 | 341 | |
| 335 | 342 | //------------------------------------------------- |
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| 430 | 437 | } |
| 431 | 438 | } |
| 432 | 439 | |
| 440 | void cs4031_device::update_dma_clock() |
| 441 | { |
| 442 | if (m_dma_clock_divider[m_registers[DMA_CLOCK] & 0x0f] != 0) |
| 443 | { |
| 444 | UINT32 dma_clock = clock() / m_dma_clock_divider[m_registers[DMA_CLOCK] & 0x0f]; |
| 433 | 445 | |
| 446 | if (!BIT(m_registers[DMA_WAIT_STATE], 0)) |
| 447 | dma_clock /= 2; |
| 448 | |
| 449 | logerror("cs4031_device::update_dma_clock: dma clock is now %u\n", dma_clock); |
| 450 | |
| 451 | m_dma1->set_unscaled_clock(dma_clock); |
| 452 | m_dma2->set_unscaled_clock(dma_clock); |
| 453 | } |
| 454 | } |
| 455 | |
| 456 | |
| 434 | 457 | //************************************************************************** |
| 435 | 458 | // INTERRUPTS |
| 436 | 459 | //************************************************************************** |
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| 539 | 562 | // execute command |
| 540 | 563 | switch (m_address) |
| 541 | 564 | { |
| 542 | | case 0x01: break; |
| 565 | case DMA_WAIT_STATE: |
| 566 | update_dma_clock(); |
| 567 | break; |
| 568 | |
| 543 | 569 | case 0x05: break; |
| 544 | 570 | case 0x06: break; |
| 545 | 571 | case 0x07: break; |
| 546 | 572 | case 0x08: break; |
| 547 | 573 | case 0x09: break; |
| 548 | | case 0x0a: break; |
| 574 | |
| 575 | case DMA_CLOCK: |
| 576 | update_dma_clock(); |
| 577 | break; |
| 578 | |
| 549 | 579 | case 0x10: break; |
| 550 | 580 | case 0x11: break; |
| 551 | 581 | case 0x12: break; |
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| 556 | 586 | case 0x17: break; |
| 557 | 587 | case 0x18: break; |
| 558 | 588 | |
| 559 | | case 0x19: |
| 589 | case SHADOW_READ: |
| 560 | 590 | update_read_regions(); |
| 561 | 591 | break; |
| 562 | 592 | |
| 563 | | case 0x1a: |
| 593 | case SHADOW_WRITE: |
| 564 | 594 | update_write_regions(); |
| 565 | 595 | break; |
| 566 | 596 | |
| 567 | | case 0x1b: |
| 597 | case ROMCS: |
| 568 | 598 | update_read_regions(); |
| 569 | 599 | update_write_regions(); |
| 570 | 600 | break; |
| 571 | 601 | |
| 572 | | case 0x1c: break; |
| 602 | case SOFT_RESET_AND_GATEA20: |
| 603 | break; |
| 573 | 604 | } |
| 574 | 605 | } |
| 575 | 606 | |