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r23691 Friday 14th June, 2013 at 02:40:41 UTC by R. Belmont
es5510: Preliminary hookup to es5505/5506.  Samples are passed through unchanged for now.  [Christian Brunschen]

[src/emu/cpu/es5510]	es5510.c es5510.h
[src/emu/sound]	es5506.c es5506.h
[src/mame/audio]	taito_en.c
[src/mame/drivers]	itech32.c macrossp.c ssv.c
[src/mess/drivers]	esq5505.c esqkt.c esqmr.c

trunk/src/mess/drivers/esqkt.c

r23690	r23691
410	410	"waverom2", /* Bank 1 */
411	411	"waverom3", /* Bank 0 */
412	412	"waverom4", /* Bank 1 */
	413	1,          /* channels */
413	414	DEVCB_DRIVER_LINE_MEMBER(esqkt_state,esq5506_otto_irq), /* irq */
414	415	DEVCB_DEVICE_HANDLER(DEVICE_SELF, esq5506_read_adc)
415	416	};
r23690	r23691
420	421	"waverom2", /* Bank 1 */
421	422	"waverom3", /* Bank 0 */
422	423	"waverom4", /* Bank 1 */
	424	1,          /* channels */
423	425	DEVCB_NULL,
424	426	DEVCB_NULL
425	427	};

trunk/src/mess/drivers/esqmr.c

r23690	r23691
65	65	"waverom2", /* Bank 1 */
66	66	"waverom3", /* Bank 0 */
67	67	"waverom4", /* Bank 1 */
	68	1,          /* channels */
68	69	DEVCB_LINE(esq5506_otto_irq), /* irq */
69	70	DEVCB_DEVICE_HANDLER(DEVICE_SELF, esq5506_read_adc)
70	71	};
r23690	r23691
75	76	"waverom2", /* Bank 1 */
76	77	"waverom3", /* Bank 0 */
77	78	"waverom4", /* Bank 1 */
	79	1,          /* channels */
78	80	DEVCB_NULL,
79	81	DEVCB_NULL
80	82	};

trunk/src/mess/drivers/esq5505.c

r23690	r23691
125	125	static int shift = 32;
126	126	#endif
127	127
	128	void print_to_stderr(const char *format, ...)
	129	{
	130	va_list arg;
	131	va_start(arg, format);
	132	vfprintf(stderr, format, arg);
	133	va_end(arg);
	134	}
	135
	136	#define PUMP_DETECT_SILENCE 1
	137	#define PUMP_TRACK_SAMPLES 0
	138	#define PUMP_FAKE_ESP_PROCESSING 1
	139	class esq_5505_5510_pump : public device_t,
	140	public device_sound_interface
	141	{
	142	public:
	143	esq_5505_5510_pump(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	144
	145	void set_otis(es5505_device *otis) { m_otis = otis; }
	146	void set_esp(es5510_device *esp) { m_esp = esp; }
	147	void set_esp_halted(bool esp_halted) {
	148	m_esp_halted = esp_halted;
	149	logerror("ESP-halted -> %d\n", m_esp_halted);
	150	if (!esp_halted) {
	151	m_esp->list_program(print_to_stderr);
	152	}
	153	}
	154	bool get_esp_halted() {
	155	return m_esp_halted;
	156	}
	157
	158	protected:
	159	// device-level overrides
	160	virtual void device_start();
	161	virtual void device_stop();
	162	virtual void device_reset();
	163
	164	// sound stream update overrides
	165	virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples);
	166
	167	// timer callback overridea
	168	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	169
	170	private:
	171	// internal state:
	172	// sound stream
	173	sound_stream *m_stream;
	174
	175	// per-sample timer
	176	emu_timer *m_timer;
	177
	178	// OTIS sound generator
	179	es5505_device *m_otis;
	180
	181	// ESP signal processor
	182	es5510_device *m_esp;
	183
	184	// Is the ESP halted by the CPU?
	185	bool m_esp_halted;
	186
	187	#if !PUMP_FAKE_ESP_PROCESSING
	188	osd_ticks_t ticks_spent_processing;
	189	int samples_processed;
	190	#endif
	191
	192	#if PUMP_DETECT_SILENCE
	193	int silent_for;
	194	bool was_silence;
	195	#endif
	196
	197	#if PUMP_TRACK_SAMPLES
	198	int last_samples;
	199	osd_ticks_t last_ticks;
	200	osd_ticks_t next_report_ticks;
	201	#endif
	202	};
	203
	204	const device_type ESQ_5505_5510_PUMP = &device_creator<esq_5505_5510_pump>;
	205
	206	esq_5505_5510_pump::esq_5505_5510_pump(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	207	: device_t(mconfig, ESQ_5505_5510_PUMP, "ESQ_5505_5510_PUMP", tag, owner, clock),
	208	device_sound_interface(mconfig, *this),
	209	m_esp_halted(true)
	210	{
	211	}
	212
	213	void esq_5505_5510_pump::device_start()
	214	{
	215	INT64 nsec_per_sample = 100 * 16 * 21;
	216	attotime sample_time(0, 1000000000 * nsec_per_sample);
	217	attotime initial_delay(0, 0);
	218	logerror("Clock = %d\n", clock());
	219	m_stream = machine().sound().stream_alloc(*this, 8, 2, clock(), this);
	220	m_timer = timer_alloc(0);
	221	m_timer->adjust(initial_delay, 0, sample_time);
	222	m_timer->enable(true);
	223
	224	#if PUMP_DETECT_SILENCE
	225	silent_for = 500;
	226	was_silence = 1;
	227	#endif
	228	#if !PUMP_FAKE_ESP_PROCESSING
	229	ticks_spent_processing = 0;
	230	samples_processed = 0;
	231	#endif
	232	#if PUMP_TRACK_SAMPLES
	233	last_samples = 0;
	234	last_ticks = osd_ticks();
	235	next_report_ticks = last_ticks + osd_ticks_per_second();
	236	#endif
	237	}
	238
	239	void esq_5505_5510_pump::device_stop()
	240	{
	241	m_timer->enable(false);
	242	}
	243
	244	void esq_5505_5510_pump::device_reset()
	245	{
	246	}
	247
	248	void esq_5505_5510_pump::sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples)
	249	{
	250	if (samples != 1) {
	251	logerror("Pump: request for %d samples\n", samples);
	252	}
	253
	254	stream_sample_t *left = outputs[0], *right = outputs[1];
	255	for (int i = 0; i < samples; i++)
	256	{
	257	// anything for the 'aux' output?
	258	INT32 l = inputs[0][i] >> 4;
	259	INT32 r = inputs[1][i] >> 4;
	260
	261	// push the samples into the ESP
	262	m_esp->ser_w(0, inputs[2][i] >> 4);
	263	m_esp->ser_w(1, inputs[3][i] >> 4);
	264	m_esp->ser_w(2, inputs[4][i] >> 4);
	265	m_esp->ser_w(3, inputs[5][i] >> 4);
	266	m_esp->ser_w(4, inputs[6][i] >> 4);
	267	m_esp->ser_w(5, inputs[7][i] >> 4);
	268
	269	m_esp->ser_w(6, 0);
	270	m_esp->ser_w(7, 0);
	271
	272	#if PUMP_FAKE_ESP_PROCESSING
	273	m_esp->ser_w(6, m_esp->ser_r(0) + m_esp->ser_r(2) + m_esp->ser_r(4));
	274	m_esp->ser_w(7, m_esp->ser_r(1) + m_esp->ser_r(3) + m_esp->ser_r(5));
	275	#else
	276	if (!m_esp_halted) {
	277	logerror("passing one sample through ESP\n");
	278	osd_ticks_t a = osd_ticks();
	279	m_esp->run_once();
	280	osd_ticks_t b = osd_ticks();
	281	ticks_spent_processing += (b - a);
	282	samples_processed++;
	283	}
	284	#endif
	285
	286	// read the processed result from the ESP and add to the saved AUX data
	287	l += m_esp->ser_r(6);
	288	r += m_esp->ser_r(7);
	289
	290	// write the combined data to the output
	291	*left++  = l;
	292	*right++ = r;
	293	}
	294
	295	#if PUMP_DETECT_SILENCE
	296	for (int i = 0; i < samples; i++) {
	297	if (outputs[0][i] == 0 && outputs[1][i] == 0) {
	298	silent_for++;
	299	} else {
	300	silent_for = 0;
	301	}
	302	}
	303	bool silence = silent_for >= 500;
	304	if (was_silence != silence) {
	305	if (!silence) {
	306	fprintf(stderr, ".-*\n");
	307	} else {
	308	fprintf(stderr, "*-.\n");
	309	}
	310	was_silence = silence;
	311	}
	312	#endif
	313
	314	#if PUMP_TRACK_SAMPLES
	315	last_samples += samples;
	316	osd_ticks_t now = osd_ticks();
	317	if (now >= next_report_ticks)
	318	{
	319	osd_ticks_t elapsed = now - last_ticks;
	320	osd_ticks_t tps = osd_ticks_per_second();
	321	fprintf(stderr, "Pump: %d samples in %" I64FMT "d ticks for %f Hz\n", last_samples, elapsed, last_samples * (double)tps / (double)elapsed);
	322	last_ticks = now;
	323	while (next_report_ticks <= now) {
	324	next_report_ticks += tps;
	325	}
	326	last_samples = 0;
	327
	328	#if !PUMP_FAKE_ESP_PROCESSING
	329	fprintf(stderr, "  ESP spent %" I64FMT "d ticks on %d samples, %f ticks per sample\n", ticks_spent_processing, samples_processed, (double)ticks_spent_processing / (double)samples_processed);
	330	ticks_spent_processing = 0;
	331	samples_processed = 0;
	332	#endif
	333	}
	334	#endif
	335	}
	336
	337	void esq_5505_5510_pump::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) {
	338	// ecery time there's a new sample period, update the stream!
	339	m_stream->update();
	340	}
	341
	342
128	343	class esq5505_state : public driver_device
129	344	{
130	345	public:
r23690	r23691
132	347	: driver_device(mconfig, type, tag),
133	348	m_maincpu(*this, "maincpu"),
134	349	m_duart(*this, "duart"),
	350	m_otis(*this, "otis"),
135	351	m_esp(*this, "esp"),
	352	m_pump(*this, "pump"),
136	353	m_fdc(*this, "wd1772"),
137	354	m_panel(*this, "panel"),
138	355	m_dmac(*this, "mc68450"),
r23690	r23691
141	358
142	359	required_device<m68000_device> m_maincpu;
143	360	required_device<duartn68681_device> m_duart;
	361	required_device<es5505_device> m_otis;
144	362	required_device<es5510_device> m_esp;
	363	required_device<esq_5505_5510_pump> m_pump;
145	364	optional_device<wd1772_t> m_fdc;
146	365	required_device<esqpanel_device> m_panel;
147	366	optional_device<hd63450_device> m_dmac;
148	367	required_device<serial_port_device> m_mdout;
149	368
	369	virtual void machine_start();
150	370	virtual void machine_reset();
151	371
152	372	DECLARE_READ16_MEMBER(es5510_dsp_r);
r23690	r23691
200	420	int vector = 0;
201	421	switch(irqline) {
202	422	case 1:
203		otis_irq_state = 0;
204		vector = M68K_INT_ACK_AUTOVECTOR;
205		break;
	423	otis_irq_state = 0;
	424	vector = M68K_INT_ACK_AUTOVECTOR;
	425	break;
206	426	case 2:
207		dmac_irq_state = 0;
208		vector = dmac_irq_vector;
209		break;
	427	dmac_irq_state = 0;
	428	vector = dmac_irq_vector;
	429	break;
210	430	case 3:
211		duart_irq_state = 0;
212		vector = duart_irq_vector;
213		break;
	431	duart_irq_state = 0;
	432	vector = duart_irq_vector;
	433	break;
214	434	default:
215		printf("\nUnexpected IRQ ACK Callback: IRQ %d\n", irqline);
216		return 0;
	435	printf("\nUnexpected IRQ ACK Callback: IRQ %d\n", irqline);
	436	return 0;
217	437	}
218	438	update_irq_to_maincpu();
219	439	return vector;
220	440	}
221	441
	442	void esq5505_state::machine_start()
	443	{
	444	driver_device::machine_start();
	445	// tell the pump about the OTIS & ESP chips
	446	m_pump->set_otis(m_otis);
	447	m_pump->set_esp(m_esp);
	448	}
	449
222	450	void esq5505_state::machine_reset()
223	451	{
224	452	m_rom = (UINT16 *)(void *)memregion("osrom")->base();
r23690	r23691
229	457	void esq5505_state::update_irq_to_maincpu() {
230	458	//printf("\nupdating IRQ state: have OTIS=%d, DMAC=%d, DUART=%d\n", otis_irq_state, dmac_irq_state, duart_irq_state);
231	459	if (duart_irq_state) {
232		m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
233		m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
234		m_maincpu->set_input_line_and_vector(M68K_IRQ_3, ASSERT_LINE, duart_irq_vector);
	460	m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
	461	m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
	462	m_maincpu->set_input_line_and_vector(M68K_IRQ_3, ASSERT_LINE, duart_irq_vector);
235	463	} else if (dmac_irq_state) {
236		m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
237		m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
238		m_maincpu->set_input_line_and_vector(M68K_IRQ_2, ASSERT_LINE, dmac_irq_vector);
	464	m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
	465	m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
	466	m_maincpu->set_input_line_and_vector(M68K_IRQ_2, ASSERT_LINE, dmac_irq_vector);
239	467	} else if (otis_irq_state) {
240		m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
241		m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
242		m_maincpu->set_input_line(M68K_IRQ_1, ASSERT_LINE);
	468	m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
	469	m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
	470	m_maincpu->set_input_line(M68K_IRQ_1, ASSERT_LINE);
243	471	} else {
244		m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
245		m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
246		m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
	472	m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
	473	m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
	474	m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
247	475	}
248	476	}
249	477
r23690	r23691
291	519
292	520	static ADDRESS_MAP_START( vfx_map, AS_PROGRAM, 16, esq5505_state )
293	521	AM_RANGE(0x000000, 0x007fff) AM_READWRITE(lower_r, lower_w)
294		AM_RANGE(0x200000, 0x20001f) AM_DEVREADWRITE_LEGACY("ensoniq", es5505_r, es5505_w)
	522	AM_RANGE(0x200000, 0x20001f) AM_DEVREADWRITE_LEGACY("otis", es5505_r, es5505_w)
295	523	AM_RANGE(0x280000, 0x28001f) AM_DEVREADWRITE8("duart", duartn68681_device, read, write, 0x00ff)
296	524	AM_RANGE(0x260000, 0x2601ff) AM_DEVREADWRITE8("esp", es5510_device, host_r, host_w, 0x00ff)
297	525	AM_RANGE(0xc00000, 0xc1ffff) AM_ROM AM_REGION("osrom", 0)
r23690	r23691
300	528
301	529	static ADDRESS_MAP_START( vfxsd_map, AS_PROGRAM, 16, esq5505_state )
302	530	AM_RANGE(0x000000, 0x00ffff) AM_READWRITE(lower_r, lower_w)
303		AM_RANGE(0x200000, 0x20001f) AM_DEVREADWRITE_LEGACY("ensoniq", es5505_r, es5505_w)
	531	AM_RANGE(0x200000, 0x20001f) AM_DEVREADWRITE_LEGACY("otis", es5505_r, es5505_w)
304	532	AM_RANGE(0x280000, 0x28001f) AM_DEVREADWRITE8("duart", duartn68681_device, read, write, 0x00ff)
305	533	AM_RANGE(0x260000, 0x2601ff) AM_DEVREADWRITE8("esp", es5510_device, host_r, host_w, 0x00ff)
306	534	AM_RANGE(0x2c0000, 0x2c0007) AM_DEVREADWRITE8("wd1772", wd1772_t, read, write, 0x00ff)
r23690	r23691
311	539
312	540	static ADDRESS_MAP_START( eps_map, AS_PROGRAM, 16, esq5505_state )
313	541	AM_RANGE(0x000000, 0x007fff) AM_READWRITE(lower_r, lower_w)
314		AM_RANGE(0x200000, 0x20001f) AM_DEVREADWRITE_LEGACY("ensoniq", es5505_r, es5505_w)
	542	AM_RANGE(0x200000, 0x20001f) AM_DEVREADWRITE_LEGACY("otis", es5505_r, es5505_w)
315	543	AM_RANGE(0x240000, 0x2400ff) AM_DEVREADWRITE_LEGACY("mc68450", hd63450_r, hd63450_w)
316	544	AM_RANGE(0x280000, 0x28001f) AM_DEVREADWRITE8("duart", duartn68681_device, read, write, 0x00ff)
317	545	AM_RANGE(0x2c0000, 0x2c0007) AM_DEVREADWRITE8("wd1772", wd1772_t, read, write, 0x00ff)
r23690	r23691
322	550
323	551	static ADDRESS_MAP_START( sq1_map, AS_PROGRAM, 16, esq5505_state )
324	552	AM_RANGE(0x000000, 0x03ffff) AM_READWRITE(lower_r, lower_w)
325		AM_RANGE(0x200000, 0x20001f) AM_DEVREADWRITE_LEGACY("ensoniq", es5505_r, es5505_w)
	553	AM_RANGE(0x200000, 0x20001f) AM_DEVREADWRITE_LEGACY("otis", es5505_r, es5505_w)
326	554	AM_RANGE(0x260000, 0x2601ff) AM_DEVREADWRITE8("esp", es5510_device, host_r, host_w, 0x0ff)
327	555	AM_RANGE(0x280000, 0x28001f) AM_DEVREADWRITE8("duart", duartn68681_device, read, write, 0x00ff)
328	556	AM_RANGE(0x2c0000, 0x2c0007) AM_DEVREADWRITE8("wd1772", wd1772_t, read, write, 0x00ff)
r23690	r23691
448	676	*/
449	677
450	678	if (data & 0x40) {
451		if (!m_esp->input_state(es5510_device::ES5510_HALT)) {
452		logerror("ESQ5505: Asserting ESPHALT\n");
453		m_esp->set_input_line(es5510_device::ES5510_HALT, ASSERT_LINE);
	679	if (!m_pump->get_esp_halted()) {
	680	logerror("ESQ5505: Asserting ESPHALT\n");
	681	m_pump->set_esp_halted(true);
454	682	}
455	683	} else {
456		if (m_esp->input_state(es5510_device::ES5510_HALT)) {
457		logerror("ESQ5505: Clearing ESPHALT\n");
458		m_esp->set_input_line(es5510_device::ES5510_HALT, CLEAR_LINE);
	684	if (m_pump->get_esp_halted()) {
	685	logerror("ESQ5505: Clearing ESPHALT\n");
	686	m_pump->set_esp_halted(false);
459	687	}
460	688	}
461	689
r23690	r23691
611	839	{
612	840	"waverom",  /* Bank 0 */
613	841	"waverom2", /* Bank 1 */
	842	4,          /* channels */
614	843	DEVCB_DRIVER_LINE_MEMBER(esq5505_state,esq5505_otis_irq), /* irq */
615	844	DEVCB_DEVICE_HANDLER(DEVICE_SELF, esq5505_read_adc)
616	845	};
r23690	r23691
643	872	MCFG_CPU_PROGRAM_MAP(vfx_map)
644	873
645	874	MCFG_CPU_ADD("esp", ES5510, XTAL_10MHz)
	875	MCFG_DEVICE_DISABLE()
646	876
647	877	MCFG_ESQPANEL2x40_ADD("panel", esqpanel_config)
648	878
r23690	r23691
652	882	MCFG_SERIAL_PORT_ADD("mdout", midiout_intf, midiout_slot, "midiout")
653	883
654	884	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
655		MCFG_SOUND_ADD("ensoniq", ES5505, XTAL_10MHz)
656		MCFG_SOUND_CONFIG(es5505_config)
	885
	886	MCFG_SOUND_ADD("pump", ESQ_5505_5510_PUMP, XTAL_10MHz / (16 * 21))
657	887	MCFG_SOUND_ROUTE(0, "lspeaker", 2.0)
658	888	MCFG_SOUND_ROUTE(1, "rspeaker", 2.0)
	889
	890	MCFG_SOUND_ADD("otis", ES5505, XTAL_10MHz)
	891	MCFG_SOUND_CONFIG(es5505_config)
	892	MCFG_SOUND_ROUTE_EX(0, "pump", 1.0, 0)
	893	MCFG_SOUND_ROUTE_EX(1, "pump", 1.0, 1)
	894	MCFG_SOUND_ROUTE_EX(2, "pump", 1.0, 2)
	895	MCFG_SOUND_ROUTE_EX(3, "pump", 1.0, 3)
	896	MCFG_SOUND_ROUTE_EX(4, "pump", 1.0, 4)
	897	MCFG_SOUND_ROUTE_EX(5, "pump", 1.0, 5)
	898	MCFG_SOUND_ROUTE_EX(6, "pump", 1.0, 6)
	899	MCFG_SOUND_ROUTE_EX(7, "pump", 1.0, 7)
659	900	MACHINE_CONFIG_END
660	901
661	902	static MACHINE_CONFIG_DERIVED(eps, vfx)
r23690	r23691
685	926	MCFG_CPU_PROGRAM_MAP(vfxsd_map)
686	927
687	928	MCFG_CPU_ADD("esp", ES5510, XTAL_10MHz)
	929	MCFG_DEVICE_DISABLE()
688	930
689	931	MCFG_ESQPANEL2x40_ADD("panel", esqpanel_config)
690	932
r23690	r23691
694	936	MCFG_SERIAL_PORT_ADD("mdout", midiout_intf, midiout_slot, "midiout")
695	937
696	938	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
697		MCFG_SOUND_ADD("ensoniq", ES5505, XTAL_30_4761MHz / 2)
698		MCFG_SOUND_CONFIG(es5505_config)
	939
	940	MCFG_SOUND_ADD("pump", ESQ_5505_5510_PUMP, XTAL_30_4761MHz / (2 * 16 * 32))
699	941	MCFG_SOUND_ROUTE(0, "lspeaker", 2.0)
700	942	MCFG_SOUND_ROUTE(1, "rspeaker", 2.0)
701	943
	944	MCFG_SOUND_ADD("otis", ES5505, XTAL_30_4761MHz / 2)
	945	MCFG_SOUND_CONFIG(es5505_config)
	946	MCFG_SOUND_ROUTE_EX(0, "pump", 1.0, 0)
	947	MCFG_SOUND_ROUTE_EX(1, "pump", 1.0, 1)
	948	MCFG_SOUND_ROUTE_EX(2, "pump", 1.0, 2)
	949	MCFG_SOUND_ROUTE_EX(3, "pump", 1.0, 3)
	950	MCFG_SOUND_ROUTE_EX(4, "pump", 1.0, 4)
	951	MCFG_SOUND_ROUTE_EX(5, "pump", 1.0, 5)
	952	MCFG_SOUND_ROUTE_EX(6, "pump", 1.0, 6)
	953	MCFG_SOUND_ROUTE_EX(7, "pump", 1.0, 7)
	954
702	955	MCFG_WD1772x_ADD("wd1772", 8000000)
703	956	MCFG_FLOPPY_DRIVE_ADD("wd1772:0", ensoniq_floppies, "35dd", esq5505_state::floppy_formats)
704	957	MACHINE_CONFIG_END

trunk/src/mame/drivers/macrossp.c

r23690	r23691
587	587	"ensoniq.1",
588	588	"ensoniq.2",
589	589	"ensoniq.3",
	590	1,             /* channels */
590	591	DEVCB_DRIVER_LINE_MEMBER(macrossp_state,irqhandler)
591	592	};
592	593

trunk/src/mame/drivers/itech32.c

r23690	r23691
1666	1666	"ensoniq.0",
1667	1667	"ensoniq.1",
1668	1668	"ensoniq.2",
1669		"ensoniq.3"
	1669	"ensoniq.3",
	1670	1               /* channels */
1670	1671	};
1671	1672
1672	1673

trunk/src/mame/drivers/ssv.c

r23690	r23691
2491	2491	"ensoniq.0",
2492	2492	"ensoniq.1",
2493	2493	"ensoniq.2",
2494		"ensoniq.3"
	2494	"ensoniq.3",
	2495	1              /* channels */
2495	2496	};
2496	2497
2497	2498	/***************************************************************************

trunk/src/mame/audio/taito_en.c

r23690	r23691
315	315	{
316	316	"ensoniq.0",    /* Bank 0: Unused by F3 games? */
317	317	"ensoniq.0",    /* Bank 1: All games seem to use this */
	318	1,              /* channels */
318	319	DEVCB_NULL            /* IRQ */
319	320	};
320	321

trunk/src/emu/sound/es5506.c

r23690	r23691
193	193	UINT16 *    volume_lookup;
194	194	device_t *device;
195	195
	196	int         channels;            /* the number of output stereo channels: 1..4 for 5505, 1..6 for 5506 */
	197
196	198	#if MAKE_WAVS
197	199	void *      wavraw;                 /* raw waveform */
198	200	#endif
r23690	r23691
783	785
784	786	***********************************************************************************************/
785	787
786		static void generate_samples(es5506_state *chip, INT32 *left, INT32 *right, int samples)
	788	static void generate_samples(es5506_state *chip, INT32 **outputs, int offset, int samples)
787	789	{
788	790	int v;
789	791
r23690	r23691
791	793	if (!samples)
792	794	return;
793	795
794		/* clear out the accumulator */
795		memset(left, 0, samples * sizeof(left[0]));
796		memset(right, 0, samples * sizeof(right[0]));
	796	/* clear out the accumulators */
	797	for (int i = 0; i < chip->channels << 1; i++)
	798	{
	799	memset(outputs[i] + offset, 0, sizeof(INT32) * samples);
	800	}
797	801
798	802	/* loop over voices */
799	803	for (v = 0; v <= chip->active_voices; v++)
r23690	r23691
805	809	if (voice->start == voice->end)
806	810	voice->control |= CONTROL_STOP0;
807	811
	812	int voice_channel = (voice->control & CONTROL_CAMASK) >> 10;
	813	int channel = voice_channel % chip->channels;
	814	int l = channel << 1;
	815	int r = l + 1;
	816	INT32 *left = outputs[l] + offset;
	817	INT32 *right = outputs[r] + offset;
	818
808	819	/* generate from the appropriate source */
809	820	if (!base)
810	821	{
r23690	r23691
845	856
846	857	***********************************************************************************************/
847	858
848		static STREAM_UPDATE( es5506_update )
	859	STREAM_UPDATE( es5506_update )
849	860	{
850	861	es5506_state *chip = (es5506_state *)param;
851		INT32 *lsrc = NULL, *rsrc = NULL;
852		stream_sample_t *ldest = outputs[0];
853		stream_sample_t *rdest = outputs[1];
854	862
855	863	#if MAKE_WAVS
856	864	/* start the logging once we have a sample rate */
r23690	r23691
862	870	#endif
863	871
864	872	/* loop until all samples are output */
	873	int offset = 0;
865	874	while (samples)
866	875	{
867	876	int length = (samples > MAX_SAMPLE_CHUNK) ? MAX_SAMPLE_CHUNK : samples;
868		int samp;
869	877
870		/* determine left/right source data */
871		lsrc = chip->scratch;
872		rsrc = chip->scratch + length;
873		generate_samples(chip, lsrc, rsrc, length);
	878	generate_samples(chip, outputs, offset, length);
874	879
875		/* copy the data */
876		for (samp = 0; samp < length; samp++)
877		{
878		*ldest++ = lsrc[samp] >> 4;
879		*rdest++ = rsrc[samp] >> 4;
880		}
881
882	880	#if MAKE_WAVS
883	881	/* log the raw data */
884		if (chip->wavraw)
	882	if (chip->wavraw) {
	883	/* determine left/right source data */
	884	INT32 *lsrc = chip->scratch, *rsrc = chip->scratch + length;
	885	int channel;
	886	memset(lsrc, 0, sizeof(INT32) * length * 2);
	887	/* loop over the output channels */
	888	for (channel = 0; channel < chip->channels; channel++) {
	889	INT32 *l = outputs[(channel << 1)] + offset;
	890	INT32 *r = outputs[(channel << 1) + 1] + offset;
	891	/* add the current channel's samples to the WAV data */
	892	for (samp = 0; samp < length; samp++) {
	893	lsrc[samp] += l[samp];
	894	rsrc[samp] += r[samp];
	895	}
	896	}
885	897	wav_add_data_32lr(chip->wavraw, lsrc, rsrc, length, 4);
	898	}
886	899	#endif
887	900
888	901	/* account for these samples */
	902	offset += length;
889	903	samples -= length;
890	904	}
891	905	}
r23690	r23691
903	917	es5506_state *chip = get_safe_token(device);
904	918	int j;
905	919	UINT32 accum_mask;
	920	int channels = 1;  /* 1 channel by default, for backward compatibility */
906	921
	922	/* only override the number of channels if the value is in the valid range 1 .. 6 */
	923	if (1 <= intf->channels && intf->channels <= 6)
	924	channels = intf->channels;
	925
907	926	/* debugging */
908	927	if (LOG_COMMANDS && !eslog)
909	928	eslog = fopen("es.log", "w");
910	929
911	930	/* create the stream */
912		chip->stream = device->machine().sound().stream_alloc(*device, 0, 2, device->clock() / (16*32), chip, es5506_update);
	931	chip->stream = device->machine().sound().stream_alloc(*device, 0, 2 * channels, device->clock() / (16*32), chip, es5506_update);
913	932
914	933	/* initialize the regions */
915	934	chip->region_base[0] = intf->region0 ? (UINT16 *)device->machine().root_device().memregion(intf->region0)->base() : NULL;
r23690	r23691
923	942	chip->irq_callback.resolve(intf->irq_callback,*device);
924	943	chip->port_read.resolve(intf->read_port,*device);
925	944	chip->irqv = 0x80;
	945	chip->channels = channels;
926	946
927	947	/* compute the tables */
928	948	compute_tables(chip);
r23690	r23691
1556	1576	{
1557	1577	const es5505_interface *intf = (const es5505_interface *)device->static_config();
1558	1578	es5506_interface es5506intf;
	1579	int channels = 1;  /* 1 channel by default, for backward compatibility */
1559	1580
	1581	/* only override the number of channels if the value is in the valid range 1 .. 4 */
	1582	if (1 <= intf->channels && intf->channels <= 4)
	1583	channels = intf->channels;
	1584
1560	1585	memset(&es5506intf, 0, sizeof(es5506intf));
1561	1586
1562	1587	es5506intf.region0 = intf->region0;
1563	1588	es5506intf.region1 = intf->region1;
	1589	es5506intf.channels = channels;
1564	1590	es5506intf.irq_callback = intf->irq_callback;
1565	1591	es5506intf.read_port = intf->read_port;
1566	1592
r23690	r23691
2194	2220	fatalerror("sound_stream_update called; not applicable to legacy sound devices\n");
2195	2221	}
2196	2222
2197
2198	2223	const device_type ES5505 = &device_creator<es5505_device>;
2199	2224
2200	2225	es5505_device::es5505_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)

trunk/src/emu/sound/es5506.h

r23690	r23691
16	16	{
17	17	const char * region0;                       /* memory region where the sample ROM lives */
18	18	const char * region1;                       /* memory region where the sample ROM lives */
	19	int channels;                               /* number of output channels: 1 .. 4 */
19	20	devcb_write_line irq_callback;  /* irq callback */
20	21	devcb_read16 read_port;          /* input port read */
21	22	};
r23690	r23691
58	59	const char * region1;                       /* memory region where the sample ROM lives */
59	60	const char * region2;                       /* memory region where the sample ROM lives */
60	61	const char * region3;                       /* memory region where the sample ROM lives */
	62	int channels;                               /* number of output channels: 1 .. 6 */
61	63	devcb_write_line irq_callback;  /* irq callback */
62	64	devcb_read16 read_port;          /* input port read */
63	65	};
r23690	r23691
79	81
80	82	extern const device_type ES5505;
81	83
	84	extern STREAM_UPDATE( es5506_update );
82	85
83	86	#endif /* __ES5506_H__ */

trunk/src/emu/cpu/es5510/es5510.c

r23690	r23691
11	11	#include "es5510.h"
12	12	#include "cpu/m68000/m68000.h"
13	13
	14	#define VERBOSE 0
	15
	16	#if VERBOSE
	17	#define LOG(x) do { logerror x; } while(0)
	18	#else
	19	#define LOG(x)
	20	#endif
	21
14	22	const device_type ES5510 = &device_creator<es5510_device>;
15	23
16	24	#define FLAG_N (1 << 7)
r23690	r23691
63	71
64	72	inline static INT32 saturate(INT32 value, UINT8 &flags) {
65	73	if (isFlagSet(flags, FLAG_V)) {
66		return isFlagSet(flags, FLAG_N) ? 0x00800000 : 0x007fffff;
	74	return isFlagSet(flags, FLAG_N) ? 0x00800000 : 0x007fffff;
67	75	} else {
68		return value;
	76	return value;
69	77	}
70	78	}
71	79
r23690	r23691
84	92
85	93
86	94	es5510_device::es5510_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
87		: cpu_device(mconfig, ES5510, "ES5510", tag, owner, clock)
	95	: cpu_device(mconfig, ES5510, "ES5510", tag, owner, clock)
88	96	{
89	97	// Initialize ESP to mostly zeroed, configured for 64k samples of delay line memory, running (not halted)
	98	halt_asserted = false;
90	99	icount = 0;
91	100	pc = 0;
92	101	state = STATE_HALTED;
r23690	r23691
218	227	static inline char * DESCRIBE_SRC_DST(char *s, UINT8 reg, op_src_dst_t src_dst) {
219	228	switch (src_dst) {
220	229	case es5510_device::SRC_DST_REG:
221		return DESCRIBE_REG(s, reg);
	230	return DESCRIBE_REG(s, reg);
222	231	case es5510_device::SRC_DST_DELAY:
223		return stpcpy_int(s, "Delay");
	232	return stpcpy_int(s, "Delay");
224	233	case es5510_device::SRC_DST_BOTH:
225		s = DESCRIBE_REG(s, reg);
226		return stpcpy_int(s, ",Delay");
	234	s = DESCRIBE_REG(s, reg);
	235	return stpcpy_int(s, ",Delay");
227	236	}
228	237	// should never happen!
229	238	return s;
r23690	r23691
249	258
250	259	switch (op.operands) {
251	260	case 0:
252		return stpcpy_int(s, op.opcode);
	261	return stpcpy_int(s, op.opcode);
253	262
254	263	case 1:
255		s += sprintf(s, "%s %s >", op.opcode, REGNAME(bReg));
256		return DESCRIBE_SRC_DST(s, aReg, opSelect.alu_dst);
	264	s += sprintf(s, "%s %s >", op.opcode, REGNAME(bReg));
	265	return DESCRIBE_SRC_DST(s, aReg, opSelect.alu_dst);
257	266
258	267	case 2:
259		s += sprintf(s, "%s %s,", op.opcode, REGNAME(bReg));
260		s = DESCRIBE_SRC_DST(s, aReg, opSelect.alu_src);
261		s += sprintf(s, " >");
262		return DESCRIBE_SRC_DST(s, aReg, opSelect.alu_dst);
	268	s += sprintf(s, "%s %s,", op.opcode, REGNAME(bReg));
	269	s = DESCRIBE_SRC_DST(s, aReg, opSelect.alu_src);
	270	s += sprintf(s, " >");
	271	return DESCRIBE_SRC_DST(s, aReg, opSelect.alu_dst);
263	272	}
264	273	return s;
265	274	}
r23690	r23691
268	277	{
269	278	if (mac)
270	279	{
271		s += sprintf(s, "MAC + ");
	280	s += sprintf(s, "MAC + ");
272	281	}
273	282	s = DESCRIBE_REG(s, dReg);
274	283	s += sprintf(s, " * ");
r23690	r23691
297	306	s += sprintf(s, "; ");
298	307	s = DESCRIBE_RAM(s, ramControl, gpr);
299	308	if (skip) {
300		s += sprintf(s, "; skippable");
	309	s += sprintf(s, "; skippable");
301	310	}
302	311
303	312	return s;
r23690	r23691
311	320	// VFX hack
312	321	if (mame_stricmp(space.machine().system().name, "vfx") == 0)
313	322	{
314		if (space.device().safe_pc() == 0xc091f0)
315		{
316		return space.device().state().state_int(M68K_D2);
	323	if (space.device().safe_pc() == 0xc091f0)
	324	{
	325	return space.device().state().state_int(M68K_D2);
	326	}
317	327	}
318		}
319	328
320	329	switch(offset)
321	330	{
322		case 0x00: logerror("ES5510: Read GPR latch[2]: %02x\n", (gpr_latch >> 16) & 0xff); return (gpr_latch >> 16) & 0xff;
323		case 0x01: logerror("ES5510: Read GPR latch[1]: %02x\n", (gpr_latch >>  8) & 0xff); return (gpr_latch >>  8) & 0xff;
324		case 0x02: logerror("ES5510: Read GPR latch[0]: %02x\n", (gpr_latch >>  0) & 0xff); return (gpr_latch >>  0) & 0xff;
	331	case 0x00: LOG(("ES5510: Host Read GPR latch[2]: %02x\n", (gpr_latch >> 16) & 0xff)); return (gpr_latch >> 16) & 0xff;
	332	case 0x01: LOG(("ES5510: Host Read GPR latch[1]: %02x\n", (gpr_latch >>  8) & 0xff)); return (gpr_latch >>  8) & 0xff;
	333	case 0x02: LOG(("ES5510: Host Read GPR latch[0]: %02x\n", (gpr_latch >>  0) & 0xff)); return (gpr_latch >>  0) & 0xff;
325	334
326		case 0x03: logerror("ES5510: Read INSTR latch[5]: %02x\n", (UINT8)((instr_latch >> 40) & 0xff)); return (instr_latch >> 40) & 0xff;
327		case 0x04: logerror("ES5510: Read INSTR latch[4]: %02x\n", (UINT8)((instr_latch >> 32) & 0xff)); return (instr_latch >> 32) & 0xff;
328		case 0x05: logerror("ES5510: Read INSTR latch[3]: %02x\n", (UINT8)((instr_latch >> 24) & 0xff)); return (instr_latch >> 24) & 0xff;
329		case 0x06: logerror("ES5510: Read INSTR latch[2]: %02x\n", (UINT8)((instr_latch >> 16) & 0xff)); return (instr_latch >> 16) & 0xff;
330		case 0x07: logerror("ES5510: Read INSTR latch[1]: %02x\n", (UINT8)((instr_latch >>  8) & 0xff)); return (instr_latch >>  8) & 0xff;
331		case 0x08: logerror("ES5510: Read INSTR latch[0]: %02x\n", (UINT8)((instr_latch >>  0) & 0xff)); return (instr_latch >>  0) & 0xff;
	335	case 0x03: LOG(("ES5510: Host Read INSTR latch[5]: %02x\n", (UINT8)((instr_latch >> 40) & 0xff))); return (instr_latch >> 40) & 0xff;
	336	case 0x04: LOG(("ES5510: Host Read INSTR latch[4]: %02x\n", (UINT8)((instr_latch >> 32) & 0xff))); return (instr_latch >> 32) & 0xff;
	337	case 0x05: LOG(("ES5510: Host Read INSTR latch[3]: %02x\n", (UINT8)((instr_latch >> 24) & 0xff))); return (instr_latch >> 24) & 0xff;
	338	case 0x06: LOG(("ES5510: Host Read INSTR latch[2]: %02x\n", (UINT8)((instr_latch >> 16) & 0xff))); return (instr_latch >> 16) & 0xff;
	339	case 0x07: LOG(("ES5510: Host Read INSTR latch[1]: %02x\n", (UINT8)((instr_latch >>  8) & 0xff))); return (instr_latch >>  8) & 0xff;
	340	case 0x08: LOG(("ES5510: Host Read INSTR latch[0]: %02x\n", (UINT8)((instr_latch >>  0) & 0xff))); return (instr_latch >>  0) & 0xff;
332	341
333		case 0x09: logerror("ES5510: Read DIL latch[2]: %02x\n", (dil_latch >> 16) & 0xff); return (dil_latch >> 16) & 0xff;
334		case 0x0a: logerror("ES5510: Read DIL latch[1]: %02x\n", (dil_latch >>  8) & 0xff); return (dil_latch >>  8) & 0xff;
335		case 0x0b: logerror("ES5510: Read DIL latch[0]: %02x\n", (dil_latch >>  0) & 0xff); return (dil_latch >>  0) & 0xff; //TODO: docs says that this always returns 0
	342	case 0x09: LOG(("ES5510: Host Read DIL latch[2]: %02x\n", (dil_latch >> 16) & 0xff)); return (dil_latch >> 16) & 0xff;
	343	case 0x0a: LOG(("ES5510: Host Read DIL latch[1]: %02x\n", (dil_latch >>  8) & 0xff)); return (dil_latch >>  8) & 0xff;
	344	case 0x0b: LOG(("ES5510: Host Read DIL latch[0]: %02x\n", (dil_latch >>  0) & 0xff)); return (dil_latch >>  0) & 0xff; //TODO: docs says that this always returns 0
336	345
337		case 0x0c: logerror("ES5510: Read DOL latch[2]: %02x\n", (dol_latch >> 16) & 0xff); return (dol_latch >> 16) & 0xff;
338		case 0x0d: logerror("ES5510: Read DOL latch[1]: %02x\n", (dol_latch >>  8) & 0xff); return (dol_latch >>  8) & 0xff;
339		case 0x0e: logerror("ES5510: Read DOL latch[0]: %02x\n", (dol_latch >>  0) & 0xff); return (dol_latch >>  0) & 0xff; //TODO: docs says that this always returns 0
	346	case 0x0c: LOG(("ES5510: Host Read DOL latch[2]: %02x\n", (dol_latch >> 16) & 0xff)); return (dol_latch >> 16) & 0xff;
	347	case 0x0d: LOG(("ES5510: Host Read DOL latch[1]: %02x\n", (dol_latch >>  8) & 0xff)); return (dol_latch >>  8) & 0xff;
	348	case 0x0e: LOG(("ES5510: Host Read DOL latch[0]: %02x\n", (dol_latch >>  0) & 0xff)); return (dol_latch >>  0) & 0xff; //TODO: docs says that this always returns 0
340	349
341		case 0x0f: logerror("ES5510: Read DADR latch[2]: %02x\n", (dadr_latch >> 16) & 0xff); return (dadr_latch >> 16) & 0xff;
342		case 0x10: logerror("ES5510: Read DADR latch[1]: %02x\n", (dadr_latch >>  8) & 0xff); return (dadr_latch >>  8) & 0xff;
343		case 0x11: logerror("ES5510: Read DADR latch[0]: %02x\n", (dadr_latch >>  0) & 0xff); return (dadr_latch >>  0) & 0xff;
	350	case 0x0f: LOG(("ES5510: Host Read DADR latch[2]: %02x\n", (dadr_latch >> 16) & 0xff)); return (dadr_latch >> 16) & 0xff;
	351	case 0x10: LOG(("ES5510: Host Read DADR latch[1]: %02x\n", (dadr_latch >>  8) & 0xff)); return (dadr_latch >>  8) & 0xff;
	352	case 0x11: LOG(("ES5510: Host Read DADR latch[0]: %02x\n", (dadr_latch >>  0) & 0xff)); return (dadr_latch >>  0) & 0xff;
344	353
345		case 0x12: logerror("ES5510: Reading Host Control\n"); return 0; // Host Control
	354	case 0x12: LOG(("ES5510: Host Reading Host Control\n")); return 0; // Host Control
346	355
347	356	case 0x16: return 0x27; // Program Counter, for test purposes only
348	357	}
r23690	r23691
353	362
354	363	WRITE8_MEMBER(es5510_device::host_w)
355	364	{
	365	#if VERBOSE
356	366	static char buf[1024];
	367	#endif
357	368	switch (offset) {
358	369	case 0x00:
359		gpr_latch = (gpr_latch&0x00ffff) | ((data&0xff)<<16);
360		logerror("ES5510: Write GPR latch[2] = %02x -> %06x (%d)\n", data, gpr_latch, SX(gpr_latch));
361		break;
	370	gpr_latch = (gpr_latch&0x00ffff) | ((data&0xff)<<16);
	371	LOG(("ES5510: Host Write GPR latch[2] = %02x -> %06x (%d)\n", data, gpr_latch, SX(gpr_latch)));
	372	break;
362	373	case 0x01:
363		gpr_latch = (gpr_latch&0xff00ff) | ((data&0xff)<< 8);
364		logerror("ES5510: Write GPR latch[1] = %02x -> %06x (%d)\n", data, gpr_latch, SX(gpr_latch));
365		break;
	374	gpr_latch = (gpr_latch&0xff00ff) | ((data&0xff)<< 8);
	375	LOG(("ES5510: Host Write GPR latch[1] = %02x -> %06x (%d)\n", data, gpr_latch, SX(gpr_latch)));
	376	break;
366	377	case 0x02:
367		gpr_latch = (gpr_latch&0xffff00) | ((data&0xff)<< 0);
368		logerror("ES5510: Write GPR latch[0] = %02x -> %06x (%d)\n", data, gpr_latch, SX(gpr_latch));
369		break;
	378	gpr_latch = (gpr_latch&0xffff00) | ((data&0xff)<< 0);
	379	LOG(("ES5510: Host Write GPR latch[0] = %02x -> %06x (%d)\n", data, gpr_latch, SX(gpr_latch)));
	380	break;
370	381
371		/* 0x03 to 0x08 INSTR Register */
372		case 0x03: instr_latch = ((instr_latch&U64(0x00ffffffffff)) | ((INT64)data&0xff)<<40); logerror("ES5510: Write INSTR latch[5] = %02x -> %012" I64FMT "x\n", data, instr_latch); break;
373		case 0x04: instr_latch = ((instr_latch&U64(0xff00ffffffff)) | ((INT64)data&0xff)<<32); logerror("ES5510: Write INSTR latch[4] = %02x -> %012" I64FMT "x\n", data, instr_latch); break;
374		case 0x05: instr_latch = ((instr_latch&U64(0xffff00ffffff)) | ((INT64)data&0xff)<<24); logerror("ES5510: Write INSTR latch[3] = %02x -> %012" I64FMT "x\n", data, instr_latch); break;
375		case 0x06: instr_latch = ((instr_latch&U64(0xffffff00ffff)) | ((INT64)data&0xff)<<16); logerror("ES5510: Write INSTR latch[2] = %02x -> %012" I64FMT "x\n", data, instr_latch); break;
376		case 0x07: instr_latch = ((instr_latch&U64(0xffffffff00ff)) | ((INT64)data&0xff)<< 8); logerror("ES5510: Write INSTR latch[1] = %02x -> %012" I64FMT "x\n", data, instr_latch); break;
377		case 0x08: instr_latch = ((instr_latch&U64(0xffffffffff00)) | ((INT64)data&0xff)<< 0); logerror("ES5510: Write INSTR latch[0] = %02x -> %012" I64FMT "x\n", data, instr_latch); break;
	382	/* 0x03 to 0x08 INSTR Register */
	383	case 0x03: instr_latch = ((instr_latch&U64(0x00ffffffffff)) | ((INT64)data&0xff)<<40); LOG(("ES5510: Host Write INSTR latch[5] = %02x -> %012" I64FMT "x\n", data, instr_latch)); break;
	384	case 0x04: instr_latch = ((instr_latch&U64(0xff00ffffffff)) | ((INT64)data&0xff)<<32); LOG(("ES5510: Host Write INSTR latch[4] = %02x -> %012" I64FMT "x\n", data, instr_latch)); break;
	385	case 0x05: instr_latch = ((instr_latch&U64(0xffff00ffffff)) | ((INT64)data&0xff)<<24); LOG(("ES5510: Host Write INSTR latch[3] = %02x -> %012" I64FMT "x\n", data, instr_latch)); break;
	386	case 0x06: instr_latch = ((instr_latch&U64(0xffffff00ffff)) | ((INT64)data&0xff)<<16); LOG(("ES5510: Host Write INSTR latch[2] = %02x -> %012" I64FMT "x\n", data, instr_latch)); break;
	387	case 0x07: instr_latch = ((instr_latch&U64(0xffffffff00ff)) | ((INT64)data&0xff)<< 8); LOG(("ES5510: Host Write INSTR latch[1] = %02x -> %012" I64FMT "x\n", data, instr_latch)); break;
	388	case 0x08: instr_latch = ((instr_latch&U64(0xffffffffff00)) | ((INT64)data&0xff)<< 0); LOG(("ES5510: Host Write INSTR latch[0] = %02x -> %012" I64FMT "x\n", data, instr_latch)); break;
378	389
379		/* 0x09 to 0x0b DIL Register (r/o) */
	390	/* 0x09 to 0x0b DIL Register (r/o) */
380	391
381		case 0x0c: dol_latch = (dol_latch&0x00ffff) | ((data&0xff)<<16); logerror("ES5510: Write DOL latch[2] = %02x -> %06x (%d)\n", data, dol_latch, SX(dol_latch)); break;
382		case 0x0d: dol_latch = (dol_latch&0xff00ff) | ((data&0xff)<< 8); logerror("ES5510: Write DOL latch[1] = %02x -> %06x (%d)\n", data, dol_latch, SX(dol_latch)); break;
383		case 0x0e: dol_latch = (dol_latch&0xffff00) | ((data&0xff)<< 0); logerror("ES5510: Write DOL latch[0] = %02x -> %06x (%d)\n", data, dol_latch, SX(dol_latch)); break; //TODO: docs says that this always returns 0xff
	392	case 0x0c: dol_latch = (dol_latch&0x00ffff) | ((data&0xff)<<16); LOG(("ES5510: Host Write DOL latch[2] = %02x -> %06x (%d)\n", data, dol_latch, SX(dol_latch))); break;
	393	case 0x0d: dol_latch = (dol_latch&0xff00ff) | ((data&0xff)<< 8); LOG(("ES5510: Host Write DOL latch[1] = %02x -> %06x (%d)\n", data, dol_latch, SX(dol_latch))); break;
	394	case 0x0e: dol_latch = (dol_latch&0xffff00) | ((data&0xff)<< 0); LOG(("ES5510: Host Write DOL latch[0] = %02x -> %06x (%d)\n", data, dol_latch, SX(dol_latch))); break; //TODO: docs says that this always returns 0xff
384	395
385	396	case 0x0f:
386		dadr_latch = (dadr_latch&0x00ffff) | ((data&0xff)<<16);
387		if (ram_sel)
388		{
389		dil_latch = dram[dadr_latch];
390		}
391		else
392		{
393		dram[dadr_latch] = dol_latch;
394		}
395		break;
	397	dadr_latch = (dadr_latch&0x00ffff) | ((data&0xff)<<16);
	398	if (ram_sel)
	399	{
	400	dil_latch = dram[dadr_latch];
	401	}
	402	else
	403	{
	404	dram[dadr_latch] = dol_latch;
	405	}
	406	break;
396	407
397	408	case 0x10: dadr_latch = (dadr_latch&0xff00ff) | ((data&0xff)<< 8); break;
398	409	case 0x11: dadr_latch = (dadr_latch&0xffff00) | ((data&0xff)<< 0); break;
399	410
400		/* 0x12 Host Control */
	411	/* 0x12 Host Control */
401	412
402	413	case 0x14: ram_sel = data & 0x80; /* bit 6 is i/o select, everything else is undefined */break;
403	414
404		/* 0x16 Program Counter (test purpose, r/o?) */
405		/* 0x17 Internal Refresh counter (test purpose) */
406		/* 0x18 Host Serial Control */
	415	/* 0x16 Program Counter (test purpose, r/o?) */
	416	/* 0x17 Internal Refresh counter (test purpose) */
	417	/* 0x18 Host Serial Control */
407	418	case 0x18:
408		logerror("ES5510: Write Host Serial control %02x: %s, %s, ser3 %s, ser2 %s, ser1 %s, ser0 %s\n", data,
	419	LOG(("ES5510: Host Write Host Serial control %02x: %s, %s, ser3 %s, ser2 %s, ser1 %s, ser0 %s\n", data,
409	420	data&0x80 ? "Master" : "Slave",
410	421	data&0x40 ? "Sony" : "I2S",
411	422	data & 0x20 ? "Out" : "In",
412	423	data & 0x10 ? "Out" : "In",
413	424	data & 0x08 ? "Out" : "In",
414		data & 0x04 ? "Out" : "In");
415		break;
	425	data & 0x04 ? "Out" : "In"));
	426	break;
416	427
417		/* 0x1f Halt enable (w) / Frame Counter (r) */
	428	/* 0x1f Halt enable (w) / Frame Counter (r) */
418	429	case 0x1F:
419		logerror("ES5510: Write Halt Enable %02x; HALT line is %d\n", data, input_state(ES5510_HALT));
420		if (input_state(ES5510_HALT)) {
421		logerror("ES5510: Write to Halt Enable while HALT line is asserted: Halting!\n");
422		state = STATE_HALTED;
423		}
424		break;
	430	LOG(("ES5510: Host Write Halt Enable %02x; HALT line is %d\n", data, halt_asserted));
	431	if (halt_asserted) {
	432	LOG(("ES5510: Host Write to Halt Enable while HALT line is asserted: Halting!\n"));
	433	state = STATE_HALTED;
	434	}
	435	break;
425	436
426	437	case 0x80: /* Read select - GPR + INSTR */
427		logerror("ES5510: Read INSTR+GPR %02x (%s): %012" I64FMT "x %06x (%d)\n", data, REGNAME(data & 0xff), instr[data] & U64(0xffffffffffff), gpr[data] & 0xffffff, gpr[data]);
	438	LOG(("ES5510: Host Read INSTR+GPR %02x (%s): %012" I64FMT "x %06x (%d)\n", data, REGNAME(data & 0xff), instr[data] & U64(0xffffffffffff), gpr[data] & 0xffffff, gpr[data]));
428	439
429		/* Check if an INSTR address is selected */
430		if (data < 0xa0) {
431		instr_latch = instr[data];
432		}
433		if (data < 0xc0) {
434		gpr_latch = gpr[data] & 0xffffff;
435		} else if (data >= 0xea) {
436		gpr_latch = read_reg(data);
437		}
438		break;
	440	/* Check if an INSTR address is selected */
	441	if (data < 0xa0) {
	442	instr_latch = instr[data];
	443	}
	444	if (data < 0xc0) {
	445	gpr_latch = gpr[data] & 0xffffff;
	446	} else if (data >= 0xea) {
	447	gpr_latch = read_reg(data);
	448	}
	449	break;
439	450
440	451	case 0xa0: /* Write select - GPR */
441		logerror("ES5510: Write GPR %02x (%s): %06x (%d)\n",data, REGNAME(data&0xff), gpr_latch, SX(gpr_latch));
442		write_reg(data, gpr_latch);
443		break;
	452	LOG(("ES5510: Host Write GPR %02x (%s): %06x (%d)\n", data, REGNAME(data&0xff), gpr_latch, SX(gpr_latch)));
	453	write_reg(data, gpr_latch);
	454	break;
444	455
445	456	case 0xc0: /* Write select - INSTR */
446		DESCRIBE_INSTR(buf, instr_latch, gpr[data]);
447		logerror("ES5510: Write INSTR %02x %012" I64FMT "x: %s\n",data, instr_latch&U64(0xffffffffffff), buf);
448		if (data < 0xa0) {
449		instr[data] = instr_latch&U64(0xffffffffffff);
450		}
451		break;
	457	#if VERBOSE
	458	DESCRIBE_INSTR(buf, instr_latch, gpr[data]);
	459	LOG(("ES5510: Host Write INSTR %02x %012" I64FMT "x: %s\n", data, instr_latch&U64(0xffffffffffff), buf));
	460	#endif
	461	if (data < 0xa0) {
	462	instr[data] = instr_latch&U64(0xffffffffffff);
	463	}
	464	break;
452	465
453	466	case 0xe0: /* Write select - GPR + INSTR */
454		DESCRIBE_INSTR(buf, instr_latch, gpr_latch);
455		logerror("ES5510:  Write INSTR+GPR %02x (%s): %012" I64FMT "x %06x (%d): %s\n",data, REGNAME(data&0xff), instr_latch, gpr_latch, SX(gpr_latch), buf);
456		if (data < 0xa0) {
457		instr[data] = instr_latch;
	467	#if VERBOSE
	468	DESCRIBE_INSTR(buf, instr_latch, gpr_latch);
	469	LOG(("ES5510: Host Write INSTR+GPR %02x (%s): %012" I64FMT "x %06x (%d): %s\n", data, REGNAME(data&0xff), instr_latch, gpr_latch, SX(gpr_latch), buf));
	470	#endif
	471	if (data < 0xa0) {
	472	instr[data] = instr_latch;
	473	}
	474	write_reg(data, gpr_latch);
	475	break;
458	476	}
459		write_reg(data, gpr_latch);
460		break;
	477	}
	478
	479	INT16 es5510_device::ser_r(int offset)
	480	{
	481	switch(offset)
	482	{
	483	case 0: return ser0l;
	484	case 1: return ser0r;
	485	case 2: return ser1l;
	486	case 3: return ser1r;
	487	case 4: return ser2l;
	488	case 5: return ser2r;
	489	case 6: return ser3l;
	490	case 7: return ser3r;
461	491	}
	492	return 0;
462	493	}
463	494
	495	void es5510_device::ser_w(int offset, INT16 data)
	496	{
	497	switch(offset)
	498	{
	499	case 0: ser0l = data; break;
	500	case 1: ser0r = data; break;
	501	case 2: ser1l = data; break;
	502	case 3: ser1r = data; break;
	503	case 4: ser2l = data; break;
	504	case 5: ser2r = data; break;
	505	case 6: ser3l = data; break;
	506	case 7: ser3r = data; break;
	507	}
	508	}
	509
464	510	void es5510_device::device_start() {
465	511	m_icountptr = &icount;
466	512	state_add(STATE_GENPC,"GENPC", pc).noshow();
r23690	r23691
505	551	return 1;
506	552	}
507	553
508		void es5510_device::execute_run() {
509		while (icount > 0) {
510		if (state == STATE_HALTED) {
511		// Currently halted, sample the HALT line
512		if (input_state(ES5510_HALT)) {
513		// remain halted
514		host_control |= 0x04; // Signal Host Access OK
515		} else {
516		logerror("ES5501: Starting!\n");
517		state = STATE_RUNNING;
	554	void es5510_device::execute_set_input(int linenum, int state) {
	555	if (linenum == ES5510_HALT) {
	556	halt_asserted = (state == ASSERT_LINE);
	557	}
	558	}
518	559
	560	void es5510_device::list_program(void(p)(const char *, ...)) {
	561	LOG(("ES5501: Starting!\n"));
	562
519	563	UINT8 addr;
520	564	char buf[1024];
521	565	for (addr = 0; addr < 0xa0; addr++) {
522	566	DESCRIBE_INSTR(buf, instr[addr], gpr[addr]);
523		logerror("%02x: %012" I64FMT "x %06x  %s\n", addr, instr[addr], gpr[addr]&0xffffff, buf);
	567	p("%02x: %012" I64FMT "x %06x  %s\n", addr, instr[addr], gpr[addr]&0xffffff, buf);
524	568	}
525	569	for (; addr < 0xc0; addr++) {
526		logerror("%02x: %06x (%d)\n", addr, gpr[addr]&0xffffff, gpr[addr]);
	570	p("%02x: %06x (%d)\n", addr, gpr[addr]&0xffffff, gpr[addr]);
527	571	}
528		}
529		} else {
530		// currently running, execute one instruction.
	572	}
531	573
532		ram_pp = ram_p;
533		ram_p = ram;
	574	void es5510_device::execute_run() {
	575	while (icount > 0) {
	576	if (state == STATE_HALTED) {
	577	// Currently halted, sample the HALT line
	578	if (halt_asserted) {
	579	// remain halted
	580	host_control |= 0x04; // Signal Host Access OK
	581	} else {
	582	// start from the beginning at PC 0
	583	state = STATE_RUNNING;
	584	host_control &= ~0x04; // Signal Host Access not OK
	585	pc = 0;
	586	}
	587	} else {
	588	// currently running, execute one instruction.
534	589
535		// *** T0, clock high
536		// --- nothing to do!
	590	#if VERBOSE
	591	char buf[1024];
	592	DESCRIBE_INSTR(buf, instr[pc], gpr[pc]);
	593	LOG(("%02x: %012" I64FMT "x %06x  %s\n", pc, instr[pc], gpr[pc]&0xffffff, buf));
	594	#endif
537	595
538		// *** T0, clock low
539		// --- Read instruction N
540		UINT64 instr = this->instr[pc];
	596	ram_pp = ram_p;
	597	ram_p = ram;
541	598
542		// --- RAM cycle N-2 (if a Read cycle): data read from bus is stored in DIL
543		if (ram_pp.cycle != RAM_CYCLE_WRITE) {
544		if (ram_pp.io) { // read from I/O and store into DIL
545		dil = 0; // read_io(ram_pp.address);;
546		} else { // read from DRAM and store into DIL
547		dil = dram[ram_pp.address];
548		}
549		}
	599	// *** T0, clock high
	600	// --- nothing to do!
550	601
551		// --- start of RAM cycle N
552		ram_control_t ramControl = RAM_CONTROL[((instr >> 3) & 0x07)];
553		ram.cycle = ramControl.cycle;
554		ram.io = ramControl.access == RAM_CONTROL_IO;
	602	// *** T0, clock low
	603	// --- Read instruction N
	604	UINT64 instr = this->instr[pc];
555	605
556		// --- RAM cycle N: read offset N
557		INT32 offset = gpr[pc];
558		switch(ramControl.access) {
559		case RAM_CONTROL_DELAY:
560		ram.address = (((dbase + offset) % (dlength + 1)) & memmask) >> memshift;
561		break;
562		case RAM_CONTROL_TABLE_A:
563		ram.address = ((abase + offset) & memmask) >> memshift;
564		break;
565		case RAM_CONTROL_TABLE_B:
566		ram.address = ((bbase + offset) & memmask) >> memshift;
567		break;
568		case RAM_CONTROL_IO:
569		ram.address = offset & 0x00fffff0; // mask off the low 4 bits
570		break;
571		}
	606	// --- RAM cycle N-2 (if a Read cycle): data read from bus is stored in DIL
	607	if (ram_pp.cycle != RAM_CYCLE_WRITE) {
	608	if (ram_pp.io) { // read from I/O and store into DIL
	609	dil = 0; // read_io(ram_pp.address);;
	610	} else { // read from DRAM and store into DIL
	611	dil = dram[ram_pp.address];
	612	}
	613	}
572	614
573		// *** T1, clock high
574		// --- Decode instruction N;
575		//     we will do this both here and in stages as the different parts of the instruction complete & recommence.
	615	// --- start of RAM cycle N
	616	ram_control_t ramControl = RAM_CONTROL[((instr >> 3) & 0x07)];
	617	ram.cycle = ramControl.cycle;
	618	ram.io = ramControl.access == RAM_CONTROL_IO;
576	619
577		UINT8 operandSelect = (UINT8)((instr >> 8) & 0x0f);
578		const op_select_t &opSelect = OPERAND_SELECT[operandSelect];
579		bool skip = false;
580		bool skippable = ((instr >> 7) & 0x01) != 0; // aka the 'SKIP' bit in the instruction word
581		if (skippable) {
582		bool skipConditionSatisfied = (ccr & cmr & FLAG_MASK) != 0;
583		if (isFlagSet(cmr, FLAG_NOT)) {
584		skipConditionSatisfied = !skipConditionSatisfied;
585		}
586		skip = skipConditionSatisfied;
587		}
	620	// --- RAM cycle N: read offset N
	621	INT32 offset = gpr[pc];
	622	switch(ramControl.access) {
	623	case RAM_CONTROL_DELAY:
	624	ram.address = (((dbase + offset) % (dlength + 1)) & memmask) >> memshift;
	625	break;
	626	case RAM_CONTROL_TABLE_A:
	627	ram.address = ((abase + offset) & memmask) >> memshift;
	628	break;
	629	case RAM_CONTROL_TABLE_B:
	630	ram.address = ((bbase + offset) & memmask) >> memshift;
	631	break;
	632	case RAM_CONTROL_IO:
	633	ram.address = offset & 0x00fffff0; // mask off the low 4 bits
	634	break;
	635	}
588	636
589		// --- Write Multiplier result N-1
590		if (mulacc.write_result) {
591		mulacc.product = (mulacc.cValue * mulacc.dValue) << mulshift;
592		mulacc.result = (mulacc.accumulate ? machl : 0) + mulacc.product;
593		INT32 tmp = (mulacc.result & U64(0x0000ffffff000000)) >> 24;
594		if (mulacc.dst & SRC_DST_REG) {
595		machl = mulacc.result;
596		write_reg(mulacc.cReg, tmp);
597		}
598		if (mulacc.dst & SRC_DST_DELAY) {
599		write_to_dol(tmp);
600		}
601		}
	637	// *** T1, clock high
	638	// --- Decode instruction N;
	639	//     we will do this both here and in stages as the different parts of the instruction complete & recommence.
602	640
603		// *** T1, clock low
604		// --- Start of multiplier cycle N
605		mulacc.cReg = (UINT8)((instr >> 32) & 0xff);
606		mulacc.dReg = (UINT8)((instr >> 40) & 0xff);
607		mulacc.src = opSelect.mac_src;
608		mulacc.dst = opSelect.mac_dst;
609		mulacc.accumulate = ((instr >> 6) & 0x01) != 0;
610		mulacc.write_result = skip;
	641	UINT8 operandSelect = (UINT8)((instr >> 8) & 0x0f);
	642	const op_select_t &opSelect = OPERAND_SELECT[operandSelect];
	643	bool skip = false;
	644	bool skippable = ((instr >> 7) & 0x01) != 0; // aka the 'SKIP' bit in the instruction word
	645	if (skippable) {
	646	bool skipConditionSatisfied = (ccr & cmr & FLAG_MASK) != 0;
	647	if (isFlagSet(cmr, FLAG_NOT)) {
	648	skipConditionSatisfied = !skipConditionSatisfied;
	649	}
	650	skip = skipConditionSatisfied;
	651	}
611	652
612		// --- Read Multiplier Operands N
613		if (mulacc.src == SRC_DST_REG) {
614		mulacc.cValue = read_reg(mulacc.cReg);
615		} else { // must be SRC_DST_DELAY
616		mulacc.cValue = dil;
617		}
618		mulacc.dValue = read_reg(mulacc.dReg);
	653	// --- Write Multiplier result N-1
	654	if (mulacc.write_result) {
	655	mulacc.product = (mulacc.cValue * mulacc.dValue) << mulshift;
	656	mulacc.result = (mulacc.accumulate ? machl : 0) + mulacc.product;
	657	INT32 tmp = (mulacc.result & U64(0x0000ffffff000000)) >> 24;
	658	if (mulacc.dst & SRC_DST_REG) {
	659	machl = mulacc.result;
	660	write_reg(mulacc.cReg, tmp);
	661	}
	662	if (mulacc.dst & SRC_DST_DELAY) {
	663	write_to_dol(tmp);
	664	}
	665	}
619	666
620		// *** T2, clock high
621		// --- Write ALU Result N-1
622		if (alu.write_result) {
623		UINT8 flags = ccr;
624		alu.result = alu_operation(alu.op, alu.aValue, alu.bValue, flags);
625		if (alu.dst & SRC_DST_REG) {
626		write_reg(alu.aReg, alu.result);
627		}
628		if (alu.dst & SRC_DST_DELAY) {
629		write_to_dol(alu.result);
630		}
631		if (alu.update_ccr) {
632		ccr = flags;
633		}
634		}
	667	// *** T1, clock low
	668	// --- Start of multiplier cycle N
	669	mulacc.cReg = (UINT8)((instr >> 32) & 0xff);
	670	mulacc.dReg = (UINT8)((instr >> 40) & 0xff);
	671	mulacc.src = opSelect.mac_src;
	672	mulacc.dst = opSelect.mac_dst;
	673	mulacc.accumulate = ((instr >> 6) & 0x01) != 0;
	674	mulacc.write_result = !skip;
635	675
636		// *** T2, clock low
637		// --- Start of ALU cycle N
638		alu.aReg = (instr >> 16) & 0xff;
639		alu.bReg = (instr >> 24) & 0xff;
640		alu.op = (instr >> 12) & 0x0f;
641		alu.src = opSelect.alu_src;
642		alu.dst = opSelect.alu_dst;
643		alu.write_result = skip;
644		alu.update_ccr = !skippable || (alu.op == OP_CMP);
	676	// --- Read Multiplier Operands N
	677	if (mulacc.src == SRC_DST_REG) {
	678	mulacc.cValue = read_reg(mulacc.cReg);
	679	} else { // must be SRC_DST_DELAY
	680	mulacc.cValue = dil;
	681	}
	682	mulacc.dValue = read_reg(mulacc.dReg);
645	683
646		// --- Read ALU Operands N
647		alu_op_t aluOp = ALU_OPS[alu.op];
648		if (aluOp.operands == 2) {
649		if (alu.src == SRC_DST_REG) {
650		alu.aValue = read_reg(alu.aReg);
651		} else { // must be SRC_DST_DELAY
652		alu.aValue = dil;
653		}
654		}
655		if (aluOp.operands >= 1) {
656		alu.bValue = read_reg(alu.bReg);
657		}
	684	// *** T2, clock high
	685	// --- Write ALU Result N-1
	686	if (alu.write_result) {
	687	UINT8 flags = ccr;
	688	alu.result = alu_operation(alu.op, alu.aValue, alu.bValue, flags);
	689	if (alu.dst & SRC_DST_REG) {
	690	write_reg(alu.aReg, alu.result);
	691	}
	692	if (alu.dst & SRC_DST_DELAY) {
	693	write_to_dol(alu.result);
	694	}
	695	if (alu.update_ccr) {
	696	ccr = flags;
	697	}
	698	}
658	699
659		// --- RAM cycle N-1
660		if (ram_p.cycle != RAM_CYCLE_READ) {
661		if (ram_p.cycle == RAM_CYCLE_WRITE) {
662		// If this is a write cycle, write the frontmost DOL value to RAM or I/O
663		if (ram_p.io) {
664		// write_io(ram_p.io, dol[0]);
665		} else {
666		dram[ram_p.address] = dol[0];
	700	// *** T2, clock low
	701	// --- Start of ALU cycle N
	702	alu.aReg = (instr >> 16) & 0xff;
	703	alu.bReg = (instr >> 24) & 0xff;
	704	alu.op = (instr >> 12) & 0x0f;
	705	alu.src = opSelect.alu_src;
	706	alu.dst = opSelect.alu_dst;
	707	alu.write_result = !skip;
	708	alu.update_ccr = !skippable || (alu.op == OP_CMP);
	709
	710	if (alu.op == 0xF) {
	711	alu_operation_end();
	712	} else {
	713	// --- Read ALU Operands N
	714	alu_op_t aluOp = ALU_OPS[alu.op];
	715	if (aluOp.operands == 2) {
	716	if (alu.src == SRC_DST_REG) {
	717	alu.aValue = read_reg(alu.aReg);
	718	} else { // must be SRC_DST_DELAY
	719	alu.aValue = dil;
	720	}
	721	}
	722	if (aluOp.operands >= 1) {
	723	alu.bValue = read_reg(alu.bReg);
	724	}
	725	}
	726
	727	// --- RAM cycle N-1
	728	if (ram_p.cycle != RAM_CYCLE_READ) {
	729	if (ram_p.cycle == RAM_CYCLE_WRITE) {
	730	// If this is a write cycle, write the frontmost DOL value to RAM or I/O
	731	if (ram_p.io) {
	732	// write_io(ram_p.io, dol[0]);
	733	} else {
	734	dram[ram_p.address] = dol[0];
	735	}
	736	}
	737	// If this is a Write or Dump cycle, eject the frontmost DL value.
	738	dol[0] = dol[1];
	739	if (dol_count > 0) {
	740	--dol_count;
	741	}
	742	}
	743
	744	++pc;
667	745	}
	746	--icount;
668	747	}
669		// If this is a Write or Dump cycle, eject the frontmost DL value.
670		dol[0] = dol[1];
671		if (dol_count > 0) {
672		--dol_count;
673		}
674		}
675
676		++pc;
677		}
678		--icount;
679		}
680	748	}
681	749
682	750	UINT32 es5510_device::disasm_min_opcode_bytes() const
r23690	r23691
697	765	INT32 es5510_device::read_reg(UINT8 reg)
698	766	{
699	767	if (reg < 0xc0) {
700		return gpr[reg];
	768	return gpr[reg];
701	769	} else {
702		switch(reg)
703		{
704		case 234: return ser0r;
705		case 235: return ser0l;
706		case 236: return ser1r;
707		case 237: return ser1l;
708		case 238: return ser2r;
709		case 239: return ser2l;
710		case 240: return ser3r;
711		case 241: return ser3l;
712		case 242: return (machl >>  0) & 0x00ffffff;
713		case 243: return (machl >> 24) & 0x00ffffff;
714		case 244: return dil; // DIL when reading
715		case 245: return dlength;
716		case 246: return abase;
717		case 247: return bbase;
718		case 248: return dbase;
719		case 249: return sigreg;
720		case 250: return ccr;
721		case 251: return cmr;
722		case 252: return 0x00ffffff;
723		case 253: return 0x00800000;
724		case 254: return 0x007fffff;
725		case 255: return 0x00000000;
726		default:
727		// unknown SPR
728		return 0;
	770	switch(reg)
	771	{
	772	case 234: return ser0r;
	773	case 235: return ser0l;
	774	case 236: return ser1r;
	775	case 237: return ser1l;
	776	case 238: return ser2r;
	777	case 239: return ser2l;
	778	case 240: return ser3r;
	779	case 241: return ser3l;
	780	case 242: return (machl >>  0) & 0x00ffffff;
	781	case 243: return (machl >> 24) & 0x00ffffff;
	782	case 244: return dil; // DIL when reading
	783	case 245: return dlength;
	784	case 246: return abase;
	785	case 247: return bbase;
	786	case 248: return dbase;
	787	case 249: return sigreg;
	788	case 250: return ccr;
	789	case 251: return cmr;
	790	case 252: return 0x00ffffff;
	791	case 253: return 0x00800000;
	792	case 254: return 0x007fffff;
	793	case 255: return 0x00000000;
	794	default:
	795	// unknown SPR
	796	return 0;
	797	}
729	798	}
	799	}
	800
	801	void es5510_device::run_once()
	802	{
	803	// turn HALT off
	804	set_HALT(false);
	805
	806	// run for one instruction
	807	icount = 1;
	808	execute_run();
	809
	810	// turn HALT on again
	811	set_HALT(true);
	812
	813	// run ESP to the end of its program, a few instructions at a time
	814	while (state != STATE_HALTED) {
	815	icount = 1;
	816	execute_run();
730	817	}
731	818	}
732	819
733	820	INT8 countLowOnes(INT32 x) {
734	821	INT8 n = 0;
735	822	while ((x & 1) == 1) {
736		++n;
737		x >>= 1;
	823	++n;
	824	x >>= 1;
738	825	}
739	826	return n;
740	827	}
r23690	r23691
743	830	{
744	831	value &= 0x00ffffff;
745	832	if (reg < 0xc0) {
746		gpr[reg] = value;
	833	gpr[reg] = value;
747	834	} else {
748		switch(reg)
749		{
750		case 234: ser0r = value;
751		break;
752		case 235: ser0l = value;
753		break;
754		case 236: ser1r = value;
755		break;
756		case 237: ser1l = value;
757		break;
758		case 238: ser2r = value;
759		break;
760		case 239: ser2l = value;
761		break;
762		case 240: ser3r = value;
763		break;
764		case 241: ser3l = value;
765		break;
766		case 242: machl = (machl & ~((INT64)0x00ffffff <<  0)) | (value <<  0);
767		break;
768		case 243: machl = (machl & ~((INT64)0x00ffffff << 24)) | (value << 24);
769		break;
770		case 244:
771		memshift = countLowOnes(value);
772		memsiz = 0x00ffffff >> (24 - memshift);
773		memmask = 0x00ffffff & ~memsiz;
774		memincrement = 1 << memshift;
775		break;
776		case 245: dlength = value;
777		break;
778		case 246: abase = value;
779		break;
780		case 247: bbase = value;
781		break;
782		case 248: dbase = value;
783		break;
784		case 249: sigreg = (value != 0);
785		break;
786		case 250: ccr = (value >> 16) & FLAG_MASK;
787		break;
788		case 251: cmr = (value >> 16) & (FLAG_MASK | FLAG_NOT);
789		break;
790		case 252: // no-op
791		break;
792		case 253: // no-op
793		break;
794		case 254: // no-op
795		break;
796		case 255: // no-op
797		break;
798		default: // unknown register
799		break;
	835	switch(reg)
	836	{
	837	case 234: ser0r = value;
	838	break;
	839	case 235: ser0l = value;
	840	break;
	841	case 236: ser1r = value;
	842	break;
	843	case 237: ser1l = value;
	844	break;
	845	case 238: ser2r = value;
	846	break;
	847	case 239: ser2l = value;
	848	break;
	849	case 240: ser3r = value;
	850	break;
	851	case 241: ser3l = value;
	852	break;
	853	case 242: machl = (machl & ~((INT64)0x00ffffff <<  0)) | (value <<  0);
	854	break;
	855	case 243: machl = (machl & ~((INT64)0x00ffffff << 24)) | (value << 24);
	856	break;
	857	case 244:
	858	memshift = countLowOnes(value);
	859	memsiz = 0x00ffffff >> (24 - memshift);
	860	memmask = 0x00ffffff & ~memsiz;
	861	memincrement = 1 << memshift;
	862	break;
	863	case 245: dlength = value;
	864	break;
	865	case 246: abase = value;
	866	break;
	867	case 247: bbase = value;
	868	break;
	869	case 248: dbase = value;
	870	break;
	871	case 249: sigreg = (value != 0);
	872	break;
	873	case 250: ccr = (value >> 16) & FLAG_MASK;
	874	break;
	875	case 251: cmr = (value >> 16) & (FLAG_MASK | FLAG_NOT);
	876	break;
	877	case 252: // no-op
	878	break;
	879	case 253: // no-op
	880	break;
	881	case 254: // no-op
	882	break;
	883	case 255: // no-op
	884	break;
	885	default: // unknown register
	886	break;
	887	}
800	888	}
801		}
802	889	}
803	890
804	891	void es5510_device::write_to_dol(INT32 value) {
805	892	if (dol_count >= 2) {
806		dol[0] = dol[1];
807		dol[1] = value;
	893	dol[0] = dol[1];
	894	dol[1] = value;
808	895	} else {
809		dol[dol_count++] = value;
	896	dol[dol_count++] = value;
810	897	}
811	898	}
812	899
	900	void es5510_device::alu_operation_end() {
	901	// Handle the END instruction separately
	902	LOG(("ES5510: END\n"));
	903	// sample the HALT line
	904	if (halt_asserted) {
	905	// halt
	906	state = STATE_HALTED;
	907	host_control |= 0x04; // Signal Host Access OK
	908	}
	909	// update the delay line base pointer
	910	dbase -= memincrement;
	911	if (dbase < 0) {
	912	dbase = dlength;
	913	}
	914	}
	915
813	916	INT32 es5510_device::alu_operation(UINT8 op, INT32 a, INT32 b, UINT8 &flags) {
814	917	switch(op) {
815	918	case 0x0: // ADD
816		return saturate(add(a, b, flags), flags);
	919	return saturate(add(a, b, flags), flags);
817	920
818	921	case 0x1: // SUB
819		return saturate(add(a, negate(b), flags), flags);
	922	return saturate(add(a, negate(b), flags), flags);
820	923
821	924	case 0x2: // ADDU
822		return add(a, b, flags);
	925	return add(a, b, flags);
823	926
824	927	case 0x3: // SUBU
825		return add(a, negate(b), flags);
	928	return add(a, negate(b), flags);
826	929
827	930	case 0x4: // CMP
828		add(a, negate(b), flags);
829		return a;
	931	add(a, negate(b), flags);
	932	return a;
830	933
831	934	case 0x5: // AND
832		a &= b;
833		setFlagTo(flags, FLAG_N, (a & 0x0080000000) != 0);
834		setFlagTo(flags, FLAG_Z, a == 0);
835		return a;
	935	a &= b;
	936	setFlagTo(flags, FLAG_N, (a & 0x0080000000) != 0);
	937	setFlagTo(flags, FLAG_Z, a == 0);
	938	return a;
836	939
837	940	case 0x6: // OR
838		a |= b;
839		setFlagTo(flags, FLAG_N, (a & 0x0080000000) != 0);
840		setFlagTo(flags, FLAG_Z, a == 0);
841		return a;
	941	a |= b;
	942	setFlagTo(flags, FLAG_N, (a & 0x0080000000) != 0);
	943	setFlagTo(flags, FLAG_Z, a == 0);
	944	return a;
842	945
843	946	case 0x7: // XOR
844		a ^= b;
845		setFlagTo(flags, FLAG_N, (a & 0x0080000000) != 0);
846		setFlagTo(flags, FLAG_Z, a == 0);
847		return a;
	947	a ^= b;
	948	setFlagTo(flags, FLAG_N, (a & 0x0080000000) != 0);
	949	setFlagTo(flags, FLAG_Z, a == 0);
	950	return a;
848	951
849	952	case 0x8: // ABS
850	953	{
851		clearFlag(flags, FLAG_N);
852		bool isNegative = (a & 0x00800000) != 0;
853		setFlagTo(flags, FLAG_C, isNegative);
854		if (isNegative) {
855		a = (a ^ 0x00ffffff) + 1;
	954	clearFlag(flags, FLAG_N);
	955	bool isNegative = (a & 0x00800000) != 0;
	956	setFlagTo(flags, FLAG_C, isNegative);
	957	if (isNegative) {
	958	a = (a ^ 0x00ffffff) + 1;
	959	}
	960	return a;
856	961	}
857		return a;
858		}
859	962
860	963	case 0x9: // MOV
861		return b;
	964	return b;
862	965
863	966	case 0xA: // ASL2
864		return asl(b, 2, flags);
	967	return asl(b, 2, flags);
865	968
866	969	case 0xB: // ASL8
867		return asl(b, 8, flags);
	970	return asl(b, 8, flags);
868	971
869	972	case 0xC: // LS15
870		return (b << 15) & 0x007fffff;
	973	return (b << 15) & 0x007fffff;
871	974
872	975	case 0xD: // DIFF
873		return add(0x007fffff, negate(b), flags);
	976	return add(0x007fffff, negate(b), flags);
874	977
875	978	case 0xE: // ASR
876		return (b >> 1) | (b & 0x00800000);
	979	return (b >> 1) | (b & 0x00800000);
877	980
878		case 0xF: // END
879		// sample the HALT line
880		if (input_state(ES5510_HALT)) {
881		// halt
882		state = STATE_HALTED;
883		host_control |= 0x04; // Signal Host Access OK
884		}
885		// update the delay line base pointer
886		dbase -= memincrement;
887		if (dbase < 0) {
888		dbase = dlength;
889		}
890
	981	case 0xF: // END - handled separately in alu_operation_end()
891	982	default:
892		return 0;
	983	return 0;
893	984	}
894	985	}

trunk/src/emu/cpu/es5510/es5510.h

r23690	r23691
13	13	#include "emu.h"
14	14
15	15	class es5510_device : public cpu_device {
16		public:
	16	public:
17	17	es5510_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
18	18
19	19	DECLARE_READ8_MEMBER(host_r);
20	20	DECLARE_WRITE8_MEMBER(host_w);
21	21
22		DECLARE_READ16_MEMBER(ser_r);
23		DECLARE_WRITE16_MEMBER(ser_w);
	22	INT16 ser_r(int offset);
	23	void ser_w(int offset, INT16 data);
24	24
25	25	enum line_t {
26		ES5510_HALT = 0
	26	ES5510_HALT = 0
27	27	};
28	28
29	29	enum state_t {
30		STATE_RUNNING = 0,
31		STATE_HALTED = 1
	30	STATE_RUNNING = 0,
	31	STATE_HALTED = 1
32	32	};
33	33
34	34	struct alu_op_t {
35		int operands;
36		const char * const opcode;
	35	int operands;
	36	const char * const opcode;
37	37	};
38	38
39	39	enum op_src_dst_t {
40		SRC_DST_REG =   1 << 0,
41		SRC_DST_DELAY = 1 << 1,
42		SRC_DST_BOTH =  (1 << 0) | (1 << 1)
	40	SRC_DST_REG =   1 << 0,
	41	SRC_DST_DELAY = 1 << 1,
	42	SRC_DST_BOTH =  (1 << 0) | (1 << 1)
43	43	};
44	44
45	45	struct op_select_t {
46		const op_src_dst_t alu_src;
47		const op_src_dst_t alu_dst;
48		const op_src_dst_t mac_src;
49		const op_src_dst_t mac_dst;
	46	const op_src_dst_t alu_src;
	47	const op_src_dst_t alu_dst;
	48	const op_src_dst_t mac_src;
	49	const op_src_dst_t mac_dst;
50	50	};
51	51
52	52	enum ram_control_access_t {
53		RAM_CONTROL_DELAY = 0,
54		RAM_CONTROL_TABLE_A,
55		RAM_CONTROL_TABLE_B,
56		RAM_CONTROL_IO
	53	RAM_CONTROL_DELAY = 0,
	54	RAM_CONTROL_TABLE_A,
	55	RAM_CONTROL_TABLE_B,
	56	RAM_CONTROL_IO
57	57	};
58	58
59	59	enum ram_cycle_t {
60		RAM_CYCLE_READ = 0,
61		RAM_CYCLE_WRITE = 1,
62		RAM_CYCLE_DUMP_FIFO = 2
	60	RAM_CYCLE_READ = 0,
	61	RAM_CYCLE_WRITE = 1,
	62	RAM_CYCLE_DUMP_FIFO = 2
63	63	};
64	64
65	65	struct ram_control_t {
66		ram_cycle_t cycle;
67		ram_control_access_t access;
68		const char * const description;
	66	ram_cycle_t cycle;
	67	ram_control_access_t access;
	68	const char * const description;
69	69	};
70	70
71	71	static const alu_op_t ALU_OPS[16];
r23690	r23691
73	73	static const ram_control_t RAM_CONTROL[8];
74	74
75	75	struct alu_t {
76		UINT8 aReg;
77		UINT8 bReg;
78		op_src_dst_t src;
79		op_src_dst_t dst;
80		UINT8 op;
81		INT32 aValue;
82		INT32 bValue;
83		INT32 result;
84		bool update_ccr;
85		bool write_result;
	76	UINT8 aReg;
	77	UINT8 bReg;
	78	op_src_dst_t src;
	79	op_src_dst_t dst;
	80	UINT8 op;
	81	INT32 aValue;
	82	INT32 bValue;
	83	INT32 result;
	84	bool update_ccr;
	85	bool write_result;
86	86	};
87	87
88	88	struct mulacc_t {
89		UINT8 cReg;
90		UINT8 dReg;
91		op_src_dst_t src;
92		op_src_dst_t dst;
93		bool accumulate;
94		INT64 cValue;
95		INT64 dValue;
96		INT64 product;
97		INT64 result;
98		bool write_result;
	89	UINT8 cReg;
	90	UINT8 dReg;
	91	op_src_dst_t src;
	92	op_src_dst_t dst;
	93	bool accumulate;
	94	INT64 cValue;
	95	INT64 dValue;
	96	INT64 product;
	97	INT64 result;
	98	bool write_result;
99	99	};
100	100
101	101	struct ram_t {
102		INT32 address;     // up to 20 bits, left-justified within the right 24 bits of the 32-bit word
103		bool io;           // I/O space, rather than delay line memory
104		ram_cycle_t cycle; // cycle type
	102	INT32 address;     // up to 20 bits, left-justified within the right 24 bits of the 32-bit word
	103	bool io;           // I/O space, rather than delay line memory
	104	ram_cycle_t cycle; // cycle type
105	105	};
106	106
107		protected:
	107	// direct access to the 'HALT' pin - not just through the
	108	void set_HALT(bool halt) { halt_asserted = halt; }
	109	bool get_HALT() { return halt_asserted; }
	110
	111	void run_once();
	112	void list_program(void(p)(const char *, ...));
	113
	114	protected:
108	115	virtual void device_start();
109	116	virtual void device_reset();
110	117	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
r23690	r23691
117	124	virtual UINT32 disasm_min_opcode_bytes() const;
118	125	virtual UINT32 disasm_max_opcode_bytes() const;
119	126	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	127	virtual void execute_set_input(int linenum, int state);
120	128
121	129	INT32 read_reg(UINT8 reg);
122	130	void write_reg(UINT8 reg, INT32 value);
123	131	void write_to_dol(INT32 value);
124	132
125	133	INT32 alu_operation(UINT8 op, INT32 aValue, INT32 bValue, UINT8 &flags);
	134	void alu_operation_end();
126	135
127		private:
	136	private:
128	137	int icount;
	138	bool halt_asserted;
129	139	UINT8 pc;
130	140	state_t state;
131	141	INT32 gpr[0xc0];     // 24 bits, right justified and sign extended

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