trunk/src/mess/machine/cs4031.h
| r23688 | r23689 | |
| 106 | 106 | DECLARE_READ8_MEMBER( dma1_ior1_r ) { return m_read_ior(1); } |
| 107 | 107 | DECLARE_READ8_MEMBER( dma1_ior2_r ) { return m_read_ior(2); } |
| 108 | 108 | DECLARE_READ8_MEMBER( dma1_ior3_r ) { return m_read_ior(3); } |
| 109 | | DECLARE_READ8_MEMBER( dma2_ior1_r ) { UINT16 result = m_read_ior(5); m_dma_high_byte = result & 0xff00; return result & 0xff; } |
| 110 | | DECLARE_READ8_MEMBER( dma2_ior2_r ) { UINT16 result = m_read_ior(6); m_dma_high_byte = result & 0xff00; return result & 0xff; } |
| 111 | | DECLARE_READ8_MEMBER( dma2_ior3_r ) { UINT16 result = m_read_ior(7); m_dma_high_byte = result & 0xff00; return result & 0xff; } |
| 109 | DECLARE_READ8_MEMBER( dma2_ior1_r ) { UINT16 result = m_read_ior(5); m_dma_high_byte = result >> 8; return result; } |
| 110 | DECLARE_READ8_MEMBER( dma2_ior2_r ) { UINT16 result = m_read_ior(6); m_dma_high_byte = result >> 8; return result; } |
| 111 | DECLARE_READ8_MEMBER( dma2_ior3_r ) { UINT16 result = m_read_ior(7); m_dma_high_byte = result >> 8; return result; } |
| 112 | 112 | DECLARE_WRITE8_MEMBER( dma1_iow0_w ) { m_write_iow(0, data, 0xffff); } |
| 113 | 113 | DECLARE_WRITE8_MEMBER( dma1_iow1_w ) { m_write_iow(1, data, 0xffff); } |
| 114 | 114 | DECLARE_WRITE8_MEMBER( dma1_iow2_w ) { m_write_iow(2, data, 0xffff); } |
| 115 | 115 | DECLARE_WRITE8_MEMBER( dma1_iow3_w ) { m_write_iow(3, data, 0xffff); } |
| 116 | | DECLARE_WRITE8_MEMBER( dma2_iow1_w ) { m_write_iow(5, m_dma_high_byte | data, 0xffff); } |
| 117 | | DECLARE_WRITE8_MEMBER( dma2_iow2_w ) { m_write_iow(6, m_dma_high_byte | data, 0xffff); } |
| 118 | | DECLARE_WRITE8_MEMBER( dma2_iow3_w ) { m_write_iow(7, m_dma_high_byte | data, 0xffff); } |
| 116 | DECLARE_WRITE8_MEMBER( dma2_iow1_w ) { m_write_iow(5, (m_dma_high_byte << 8) | data, 0xffff); } |
| 117 | DECLARE_WRITE8_MEMBER( dma2_iow2_w ) { m_write_iow(6, (m_dma_high_byte << 8) | data, 0xffff); } |
| 118 | DECLARE_WRITE8_MEMBER( dma2_iow3_w ) { m_write_iow(7, (m_dma_high_byte << 8) | data, 0xffff); } |
| 119 | 119 | DECLARE_WRITE_LINE_MEMBER( dma1_dack0_w ) { set_dma_channel(0, state); } |
| 120 | 120 | DECLARE_WRITE_LINE_MEMBER( dma1_dack1_w ) { set_dma_channel(1, state); } |
| 121 | 121 | DECLARE_WRITE_LINE_MEMBER( dma1_dack2_w ) { set_dma_channel(2, state); } |