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199869 Revisions

r23686 Thursday 13th June, 2013 at 20:42:30 UTC by Wilbert Pol
hcd62121.c: Modernized cpu core. (nw)

[src/emu/cpu/hcd62121]

hcd62121.c hcd62121.h hcd62121_ops.h

trunk/src/emu/cpu/hcd62121/hcd62121.c
r23685	r23686
15	15	#include "hcd62121.h"
16	16
17	17
18		struct hcd62121_state
19		{
20		UINT32 prev_pc;
21		UINT16 sp;
22		UINT16 ip;
23		UINT8 dsize;
24		UINT8 cseg;
25		UINT8 dseg;
26		UINT8 sseg;
27		UINT8 f;
28		UINT16 lar;
29		UINT8 reg[0x80];
30		UINT8 temp1[0x10];
31		UINT8 temp2[0x10];
32		device_irq_acknowledge_callback irq_callback;
33		legacy_cpu_device *device;
34		address_space *program;
35		address_space *io;
36		int icount;
37		};
38
39
40	18	/* From the battery check routine at 20:e874 it looks like
41	19	bit 3 of the flag register should be the Zero flag. */
42	20	#define _FLAG_Z 0x08
r23685	r23686
46	24	#define _FLAG_ZH 0x10
47	25
48	26
49		#define mem_readbyte(cs,A) ((UINT8)(cs)->program->read_byte(A))
50		#define mem_writebyte(cs,A,V) ((cs)->program->write_byte(A,V))
51		#define io_readbyte(cs,A) ((UINT8)(cs)->io->read_byte(A))
52		#define io_writebyte(cs,A,V) ((cs)->io->write_byte(A,V))
	27	const device_type HCD62121 = &device_creator<hcd62121_cpu_device>;
53	28
54	29
55		INLINE UINT8 read_op(hcd62121_state *cpustate)
	30	hcd62121_cpu_device::hcd62121_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	31	: cpu_device(mconfig, HCD62121, "Hitachi HCD62121", tag, owner, clock)
	32	, m_program_config("program", ENDIANNESS_BIG, 8, 24, 0)
	33	, m_io_config("io", ENDIANNESS_BIG, 8, 8, 0)
56	34	{
57		UINT8 d = mem_readbyte(cpustate, ( cpustate->cseg << 16 ) \| cpustate->ip );
58		cpustate->ip++;
	35	}
	36
	37
	38	UINT8 hcd62121_cpu_device::read_op()
	39	{
	40	UINT8 d = m_program->read_byte( ( m_cseg << 16 ) \| m_ip );
	41	m_ip++;
59	42	return d;
60	43	}
61	44
62	45
63		~~INLINE~~ UINT8 ~~datasize(~~ hcd62121_state *cpustate, UINT8 op )
	46	UINT8 hcd62121_cpu_device::datasize( UINT8 op )
64	47	{
65	48	switch( op & 0x03 )
66	49	{
r23685	r23686
69	52	case 1:
70	53	return 2;
71	54	case 2:
72		return ( ~~cpustate->~~dsize >> 4 ) + 1;
	55	return ( m_dsize >> 4 ) + 1;
73	56	case 3:
74		return ( ~~cpustate->~~dsize & 0x0f ) + 1;
	57	return ( m_dsize & 0x0f ) + 1;
75	58	}
76	59	return 1;
77	60	}
78	61
79	62
80		~~INLINE~~ void ~~read_reg(~~ hcd62121_state *cpustate, int size, UINT8 op1 )
	63	void hcd62121_cpu_device::read_reg( int size, UINT8 op1 )
81	64	{
82	65	int i;
83	66
84	67	if ( op1 & 0x80 )
85	68	{
86	69	for ( i = 0; i < size; i++ )
87		~~cpus~~tate~~->te~~mp1[i] = ~~cpustate->~~reg[ ( op1 - i ) & 0x7f ];
	70	m_temp1[i] = m_reg[ ( op1 - i ) & 0x7f ];
88	71	}
89	72	else
90	73	{
91	74	for ( i = 0; i < size; i++ )
92		~~cpus~~tate~~->te~~mp1[i] = ~~cpustate->~~reg[ ( op1 + i ) & 0x7f ];
	75	m_temp1[i] = m_reg[ ( op1 + i ) & 0x7f ];
93	76	}
94	77	}
95	78
96	79
97		~~INLINE~~ void ~~write_reg(~~ hcd62121_state *cpustate, int size, UINT8 op1 )
	80	void hcd62121_cpu_device::write_reg( int size, UINT8 op1 )
98	81	{
99	82	int i;
100	83
101	84	if ( op1 & 0x80 )
102	85	{
103	86	for ( i = 0; i < size; i++ )
104		~~cpustate->~~reg[ ( op1 - i ) & 0x7f ] = ~~cpustate->~~temp1[i];
	87	m_reg[ ( op1 - i ) & 0x7f ] = m_temp1[i];
105	88	}
106	89	else
107	90	{
108	91	for ( i = 0; i < size; i++ )
109		~~cpustate->~~reg[ ( op1 + i ) & 0x7f ] = ~~cpustate->~~temp1[i];
	92	m_reg[ ( op1 + i ) & 0x7f ] = m_temp1[i];
110	93	}
111	94	}
112	95
113	96
114		~~INLINE~~ void ~~read_regreg(~~ hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2, bool op_is_logical )
	97	void hcd62121_cpu_device::read_regreg( int size, UINT8 op1, UINT8 op2, bool op_is_logical )
115	98	{
116	99	int i;
117	100
118	101	for ( i = 0; i < size; i++ )
119		~~cpus~~tate~~->te~~mp1[i] = ~~cpustate->~~reg[ (op1 + i) & 0x7f];
	102	m_temp1[i] = m_reg[ (op1 + i) & 0x7f];
120	103
121	104	if ( op1 & 0x80 )
122	105	{
123	106	/* Second operand is an immediate value */
124		~~cpustate->~~temp2[0] = op2;
	107	m_temp2[0] = op2;
125	108	for ( i = 1; i < size; i++ )
126		~~cpustate->~~temp2[i] = op_is_logical ? op2 : 0;
	109	m_temp2[i] = op_is_logical ? op2 : 0;
127	110	}
128	111	else
129	112	{
130	113	/* Second operand is a register */
131	114	for ( i = 0; i < size; i++ )
132		~~cpus~~tate~~->te~~mp2[i] = ~~cpustate->~~reg[ (op2 + i) & 0x7f ];
	115	m_temp2[i] = m_reg[ (op2 + i) & 0x7f ];
133	116	}
134	117
135	118	if ( ! ( op1 & 0x80 ) && ! ( op2 & 0x80 ) )
r23685	r23686
137	120	/* We need to swap parameters */
138	121	for ( i = 0; i < size; i++ )
139	122	{
140		UINT8 v = cpustate->temp1[i];
141		cpustate->temp1[i] = cpustate->temp2[i];
142		cpustate->temp2[i] = v;
	123	UINT8 v = m_temp1[i];
	124	m_temp1[i] = m_temp2[i];
	125	m_temp2[i] = v;
143	126	}
144	127	}
145	128	}
146	129
147	130
148		~~INLINE~~ void ~~write_regreg(~~ hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2 )
	131	void hcd62121_cpu_device::write_regreg( int size, UINT8 op1, UINT8 op2 )
149	132	{
150	133	int i;
151	134
r23685	r23686
153	136	{
154	137	/* store in reg1 */
155	138	for ( i = 0; i < size; i++ )
156		~~cpustate->~~reg[ (op1 + i) & 0x7f] = ~~cpustate->~~temp1[i];
	139	m_reg[ (op1 + i) & 0x7f] = m_temp1[i];
157	140	}
158	141	else
159	142	{
160	143	/* store in reg2 */
161	144	for ( i = 0; i < size; i++ )
162		~~cpustate->~~reg[ (op2 + i) & 0x7f] = ~~cpustate->~~temp1[i];
	145	m_reg[ (op2 + i) & 0x7f] = m_temp1[i];
163	146	}
164	147	}
165	148
166	149
167		~~INLINE~~ void ~~read_iregreg(~~ hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2 )
	150	void hcd62121_cpu_device::read_iregreg( int size, UINT8 op1, UINT8 op2 )
168	151	{
169	152	int i;
170	153	UINT16 ad;
171	154
172		ad = ~~cpustate->~~reg[ ( 0x40 \| op1 ) & 0x7f ] \| ( ~~cpustate->~~reg[ ( 0x40 \| ( op1 + 1 ) ) & 0x7f ] << 8 );
	155	ad = m_reg[ ( 0x40 \| op1 ) & 0x7f ] \| ( m_reg[ ( 0x40 \| ( op1 + 1 ) ) & 0x7f ] << 8 );
173	156
174	157	for ( i = 0; i < size; i++ )
175	158	{
176		~~cpus~~tate~~->te~~mp1[i] = mem_readbyte( ~~cpustate,~~ ( ~~cpustate->~~dseg << 16 ) \| ad );
	159	m_temp1[i] = m_program->read_byte( ( m_dseg << 16 ) \| ad );
177	160	ad += ( op1 & 0x40 ) ? -1 : 1;
178	161	}
179		~~cpustate->~~lar = ad;
	162	m_lar = ad;
180	163
181	164	if ( op1 & 0x80 )
182	165	{
183		~~cpustate->~~temp2[0] = op2;
	166	m_temp2[0] = op2;
184	167	for ( i = 1; i < size; i++ )
185		~~cpustate->~~temp2[i] = 0;
	168	m_temp2[i] = 0;
186	169	}
187	170	else
188	171	{
189	172	for ( i = 0; i < size; i++ )
190		~~cpus~~tate~~->te~~mp2[i] = ~~cpustate->~~reg[ (op2 + i) & 0x7f ];
	173	m_temp2[i] = m_reg[ (op2 + i) & 0x7f ];
191	174	}
192	175
193	176	if ( ! ( op1 & 0x80 ) && ! ( op2 & 0x80 ) )
r23685	r23686
195	178	/* We need to swap parameters */
196	179	for ( i = 0; i < size; i++ )
197	180	{
198		UINT8 v = cpustate->temp1[i];
199		cpustate->temp1[i] = cpustate->temp2[i];
200		cpustate->temp2[i] = v;
	181	UINT8 v = m_temp1[i];
	182	m_temp1[i] = m_temp2[i];
	183	m_temp2[i] = v;
201	184	}
202	185	}
203	186	}
204	187
205	188
206		~~INLINE~~ void ~~write_iregreg(~~ hcd62121_state *cpustate, int size, UINT8 op1, UINT8 op2 )
	189	void hcd62121_cpu_device::write_iregreg( int size, UINT8 op1, UINT8 op2 )
207	190	{
208	191	int i;
209	192
210	193	if ( ( op1 & 0x80 ) \|\| ( op2 & 0x80 ) )
211	194	{
212	195	/* store in (reg1) */
213		UINT16 ad = ~~cpustate->~~reg[ ( 0x40 \| op1 ) & 0x7f ] \| ( ~~cpustate->~~reg[ ( 0x40 \| ( op1 + 1 ) ) & 0x7f ] << 8 );
	196	UINT16 ad = m_reg[ ( 0x40 \| op1 ) & 0x7f ] \| ( m_reg[ ( 0x40 \| ( op1 + 1 ) ) & 0x7f ] << 8 );
214	197
215	198	for ( i = 0; i < size; i++ )
216	199	{
217		mem_writebyte( ~~cpustate,~~ ( ~~cpustate->~~dseg << 16 ) \| ad, ~~cpustate->~~temp1[i] );
	200	m_program->write_byte( ( m_dseg << 16 ) \| ad, m_temp1[i] );
218	201	ad += ( op1 & 0x40 ) ? -1 : 1;
219	202	}
220		~~cpustate->~~lar = ad;
	203	m_lar = ad;
221	204	}
222	205	else
223	206	{
224	207	/* store in reg2 */
225	208	for ( i = 0; i < size; i++ )
226		~~cpustate->~~reg[ (op2 + i) & 0x7f] = ~~cpustate->~~temp1[i];
	209	m_reg[ (op2 + i) & 0x7f] = m_temp1[i];
227	210	}
228	211	}
229	212
230	213
231		~~INLINE~~ void write_iregreg2( ~~hcd62121_state *cpustate,~~ int size, UINT8 op1, UINT8 op2 )
	214	void hcd62121_cpu_device::write_iregreg2( int size, UINT8 op1, UINT8 op2 )
232	215	{
233	216	int i;
234	217
r23685	r23686
236	219	{
237	220	/* store in reg2 */
238	221	for ( i = 0; i < size; i++ )
239		~~cpustate->~~reg[ (op2 + i) & 0x7f] = ~~cpustate->~~temp2[i];
	222	m_reg[ (op2 + i) & 0x7f] = m_temp2[i];
240	223	}
241	224	else
242	225	{
243	226	/* store in (reg1) */
244		UINT16 ad = ~~cpustate->~~reg[ ( 0x40 \| op1 ) & 0x7f ] \| ( ~~cpustate->~~reg[ ( 0x40 \| ( op1 + 1 ) ) & 0x7f ] << 8 );
	227	UINT16 ad = m_reg[ ( 0x40 \| op1 ) & 0x7f ] \| ( m_reg[ ( 0x40 \| ( op1 + 1 ) ) & 0x7f ] << 8 );
245	228
246	229	for ( i = 0; i < size; i++ )
247	230	{
248		mem_writebyte( ~~cpustate,~~ ( ~~cpustate->~~dseg << 16 ) \| ad, ~~cpustate->~~temp2[i] );
	231	m_program->write_byte( ( m_dseg << 16 ) \| ad, m_temp2[i] );
249	232	ad += ( op1 & 0x40 ) ? -1 : 1;
250	233	}
251		~~cpustate->~~lar = ad;
	234	m_lar = ad;
252	235	}
253	236	}
254	237
255	238
256		~~INLINE~~ int chec~~k_con~~d~~( hcd~~62121_state *cpu~~stat~~e, UINT8 op )
	239	int hcd62121_cpu_device::check_cond( UINT8 op )
257	240	{
258	241	switch ( op & 0x07 )
259	242	{
260	243	case 0x00: /* ZH set */
261		if ( ~~cpustate->~~f & _FLAG_ZH )
	244	if ( m_f & _FLAG_ZH )
262	245	return 1;
263	246	break;
264	247
265	248	case 0x01: /* ZL set */
266		if ( ~~cpustate->~~f & _FLAG_ZL )
	249	if ( m_f & _FLAG_ZL )
267	250	return 1;
268	251	break;
269	252
270	253	case 0x02: /* C set */
271		if ( ~~cpustate->~~f & _FLAG_C )
	254	if ( m_f & _FLAG_C )
272	255	return 1;
273	256	break;
274	257
275	258	case 0x03: /* Z set */
276		if ( ~~cpustate->~~f & _FLAG_Z )
	259	if ( m_f & _FLAG_Z )
277	260	return 1;
278	261	break;
279	262
280	263	case 0x04: /* Z or C set */
281		if ( ~~cpustate->~~f & ( _FLAG_Z \| _FLAG_C ) )
	264	if ( m_f & ( _FLAG_Z \| _FLAG_C ) )
282	265	return 1;
283	266	break;
284	267
285	268	case 0x05: /* CL set */
286		if ( ~~cpustate->~~f & _FLAG_CL )
	269	if ( m_f & _FLAG_CL )
287	270	return 1;
288	271	break;
289	272
290	273	case 0x06: /* C clear */
291		if ( ! ( ~~cpustate->~~f & _FLAG_C ) )
	274	if ( ! ( m_f & _FLAG_C ) )
292	275	return 1;
293	276	break;
294	277
295	278	case 0x07: /* Z clear */
296		if ( ! ( ~~cpustate->~~f & _FLAG_Z ) )
	279	if ( ! ( m_f & _FLAG_Z ) )
297	280	return 1;
298	281	break;
299	282	}
r23685	r23686
302	285	}
303	286
304	287
305		~~INLINE~~ hcd62121_~~state get~~_~~safe_token(~~device_t device)
	288	void hcd62121_cpu_device::device_start()
306	289	{
307		assert(device != NULL);
308		assert(device->type() == HCD62121);
309		return (hcd62121_state )downcast<legacy_cpu_device >(device)->token();
	290	// m_irq_callback = irqcallback;
	291	m_program = &space(AS_PROGRAM);
	292	m_io = &space(AS_IO);
	293
	294	save_item( NAME(m_prev_pc) );
	295	save_item( NAME(m_sp) );
	296	save_item( NAME(m_ip) );
	297	save_item( NAME(m_dsize) );
	298	save_item( NAME(m_cseg) );
	299	save_item( NAME(m_dseg) );
	300	save_item( NAME(m_sseg) );
	301	save_item( NAME(m_f) );
	302	save_item( NAME(m_lar) );
	303	save_item( NAME(m_reg) );
	304	save_item( NAME(m_temp1) );
	305	save_item( NAME(m_temp2) );
	306
	307	// Register state for debugger
	308	state_add( STATE_GENPC, "curpc", m_ip ).callimport().callexport().formatstr("%8s");
	309	state_add( STATE_GENFLAGS, "GENFLAGS", m_f ).callimport().callexport().formatstr("%12s").noshow();
	310
	311	state_add( HCD62121_IP, "IP", m_ip ).callimport().callexport().formatstr("%04X");
	312	state_add( HCD62121_SP, "SP", m_sp ).callimport().callexport().formatstr("%04X");
	313	state_add( HCD62121_LAR, "LAR", m_lar ).callimport().callexport().formatstr("%04X");
	314	state_add( HCD62121_CS, "CS", m_cseg ).callimport().callexport().formatstr("%02X");
	315	state_add( HCD62121_DS, "DS", m_dseg ).callimport().callexport().formatstr("%02X");
	316	state_add( HCD62121_SS, "SS", m_sseg ).callimport().callexport().formatstr("%02X");
	317	state_add( HCD62121_DSIZE, "DSIZE", m_dsize ).callimport().callexport().formatstr("%02X");
	318	state_add( HCD62121_F, "F", m_f ).callimport().callexport().formatstr("%02X");
	319
	320	state_add( HCD62121_R00, "R00", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	321	state_add( HCD62121_R04, "R04", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	322	state_add( HCD62121_R08, "R08", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	323	state_add( HCD62121_R0C, "R0C", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	324	state_add( HCD62121_R10, "R10", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	325	state_add( HCD62121_R14, "R14", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	326	state_add( HCD62121_R18, "R18", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	327	state_add( HCD62121_R1C, "R1C", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	328	state_add( HCD62121_R20, "R20", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	329	state_add( HCD62121_R24, "R24", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	330	state_add( HCD62121_R28, "R28", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	331	state_add( HCD62121_R2C, "R2C", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	332	state_add( HCD62121_R30, "R30", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	333	state_add( HCD62121_R34, "R34", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	334	state_add( HCD62121_R38, "R38", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	335	state_add( HCD62121_R3C, "R3C", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	336	state_add( HCD62121_R40, "R40", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	337	state_add( HCD62121_R44, "R44", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	338	state_add( HCD62121_R48, "R48", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	339	state_add( HCD62121_R4C, "R4C", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	340	state_add( HCD62121_R50, "R50", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	341	state_add( HCD62121_R54, "R54", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	342	state_add( HCD62121_R58, "R58", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	343	state_add( HCD62121_R5C, "R5C", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	344	state_add( HCD62121_R60, "R60", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	345	state_add( HCD62121_R64, "R64", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	346	state_add( HCD62121_R68, "R68", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	347	state_add( HCD62121_R6C, "R6C", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	348	state_add( HCD62121_R70, "R70", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	349	state_add( HCD62121_R74, "R74", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	350	state_add( HCD62121_R78, "R78", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	351	state_add( HCD62121_R7C, "R7C", m_reg[0x00] ).callimport().callexport().formatstr("%8s");
	352
	353	m_icountptr = &m_icount;
310	354	}
311	355
312	356
313		~~stat~~ic ~~CPU_INIT(~~ hcd62121 )
	357	void hcd62121_cpu_device::state_string_export(const device_state_entry &entry, astring &string)
314	358	{
315		hcd62121_state *cpustate = get_safe_token(device);
	359	switch (entry.index())
	360	{
	361	case STATE_GENPC:
	362	string.printf("%06X", ( m_cseg << 16 ) \| m_ip);
	363	break;
316	364
317		cpustate->irq_callback = irqcallback;
318		cpustate->device = device;
319		cpustate->program = &device->space(AS_PROGRAM);
320		cpustate->io = &device->space(AS_IO);
	365	case STATE_GENFLAGS:
	366	string.printf("%s-%s-%s-%c-%c",
	367	m_f & _FLAG_ZH ? "ZH":"__",
	368	m_f & _FLAG_CL ? "CL":"__",
	369	m_f & _FLAG_ZL ? "ZL":"__",
	370	m_f & _FLAG_C ? 'C':'_',
	371	m_f & _FLAG_Z ? 'Z':'_'
	372	);
	373
	374	break;
	375
	376	case HCD62121_R00:
	377	string.printf("%02X%02X%02X%02X", m_reg[0x00], m_reg[0x01], m_reg[0x02], m_reg[0x03]);
	378	break;
	379	case HCD62121_R04:
	380	string.printf("%02X%02X%02X%02X", m_reg[0x04], m_reg[0x05], m_reg[0x06], m_reg[0x07]);
	381	break;
	382	case HCD62121_R08:
	383	string.printf("%02X%02X%02X%02X", m_reg[0x08], m_reg[0x09], m_reg[0x0A], m_reg[0x0B]);
	384	break;
	385	case HCD62121_R0C:
	386	string.printf("%02X%02X%02X%02X", m_reg[0x0C], m_reg[0x0D], m_reg[0x0E], m_reg[0x0F]);
	387	break;
	388	case HCD62121_R10:
	389	string.printf("%02X%02X%02X%02X", m_reg[0x10], m_reg[0x11], m_reg[0x12], m_reg[0x13]);
	390	break;
	391	case HCD62121_R14:
	392	string.printf("%02X%02X%02X%02X", m_reg[0x14], m_reg[0x15], m_reg[0x16], m_reg[0x17]);
	393	break;
	394	case HCD62121_R18:
	395	string.printf("%02X%02X%02X%02X", m_reg[0x18], m_reg[0x19], m_reg[0x1A], m_reg[0x1B]);
	396	break;
	397	case HCD62121_R1C:
	398	string.printf("%02X%02X%02X%02X", m_reg[0x1C], m_reg[0x1D], m_reg[0x1E], m_reg[0x1F]);
	399	break;
	400	case HCD62121_R20:
	401	string.printf("%02X%02X%02X%02X", m_reg[0x20], m_reg[0x21], m_reg[0x22], m_reg[0x23]);
	402	break;
	403	case HCD62121_R24:
	404	string.printf("%02X%02X%02X%02X", m_reg[0x24], m_reg[0x25], m_reg[0x26], m_reg[0x27]);
	405	break;
	406	case HCD62121_R28:
	407	string.printf("%02X%02X%02X%02X", m_reg[0x28], m_reg[0x29], m_reg[0x2A], m_reg[0x2B]);
	408	break;
	409	case HCD62121_R2C:
	410	string.printf("%02X%02X%02X%02X", m_reg[0x2C], m_reg[0x2D], m_reg[0x2E], m_reg[0x2F]);
	411	break;
	412	case HCD62121_R30:
	413	string.printf("%02X%02X%02X%02X", m_reg[0x30], m_reg[0x31], m_reg[0x32], m_reg[0x33]);
	414	break;
	415	case HCD62121_R34:
	416	string.printf("%02X%02X%02X%02X", m_reg[0x34], m_reg[0x35], m_reg[0x36], m_reg[0x37]);
	417	break;
	418	case HCD62121_R38:
	419	string.printf("%02X%02X%02X%02X", m_reg[0x38], m_reg[0x39], m_reg[0x3A], m_reg[0x3B]);
	420	break;
	421	case HCD62121_R3C:
	422	string.printf("%02X%02X%02X%02X", m_reg[0x3C], m_reg[0x3D], m_reg[0x3E], m_reg[0x3F]);
	423	break;
	424	case HCD62121_R40:
	425	string.printf("%02X%02X%02X%02X", m_reg[0x40], m_reg[0x41], m_reg[0x42], m_reg[0x43]);
	426	break;
	427	case HCD62121_R44:
	428	string.printf("%02X%02X%02X%02X", m_reg[0x44], m_reg[0x45], m_reg[0x46], m_reg[0x47]);
	429	break;
	430	case HCD62121_R48:
	431	string.printf("%02X%02X%02X%02X", m_reg[0x48], m_reg[0x49], m_reg[0x4A], m_reg[0x4B]);
	432	break;
	433	case HCD62121_R4C:
	434	string.printf("%02X%02X%02X%02X", m_reg[0x4C], m_reg[0x4D], m_reg[0x4E], m_reg[0x4F]);
	435	break;
	436	case HCD62121_R50:
	437	string.printf("%02X%02X%02X%02X", m_reg[0x50], m_reg[0x51], m_reg[0x52], m_reg[0x53]);
	438	break;
	439	case HCD62121_R54:
	440	string.printf("%02X%02X%02X%02X", m_reg[0x54], m_reg[0x55], m_reg[0x56], m_reg[0x57]);
	441	break;
	442	case HCD62121_R58:
	443	string.printf("%02X%02X%02X%02X", m_reg[0x58], m_reg[0x59], m_reg[0x5A], m_reg[0x5B]);
	444	break;
	445	case HCD62121_R5C:
	446	string.printf("%02X%02X%02X%02X", m_reg[0x5C], m_reg[0x5D], m_reg[0x5E], m_reg[0x5F]);
	447	break;
	448	case HCD62121_R60:
	449	string.printf("%02X%02X%02X%02X", m_reg[0x60], m_reg[0x61], m_reg[0x62], m_reg[0x63]);
	450	break;
	451	case HCD62121_R64:
	452	string.printf("%02X%02X%02X%02X", m_reg[0x64], m_reg[0x65], m_reg[0x66], m_reg[0x67]);
	453	break;
	454	case HCD62121_R68:
	455	string.printf("%02X%02X%02X%02X", m_reg[0x68], m_reg[0x69], m_reg[0x6A], m_reg[0x6B]);
	456	break;
	457	case HCD62121_R6C:
	458	string.printf("%02X%02X%02X%02X", m_reg[0x6C], m_reg[0x6D], m_reg[0x6E], m_reg[0x6F]);
	459	break;
	460	case HCD62121_R70:
	461	string.printf("%02X%02X%02X%02X", m_reg[0x70], m_reg[0x71], m_reg[0x72], m_reg[0x73]);
	462	break;
	463	case HCD62121_R74:
	464	string.printf("%02X%02X%02X%02X", m_reg[0x74], m_reg[0x75], m_reg[0x76], m_reg[0x77]);
	465	break;
	466	case HCD62121_R78:
	467	string.printf("%02X%02X%02X%02X", m_reg[0x78], m_reg[0x79], m_reg[0x7A], m_reg[0x7B]);
	468	break;
	469	case HCD62121_R7C:
	470	string.printf("%02X%02X%02X%02X", m_reg[0x7C], m_reg[0x7D], m_reg[0x7E], m_reg[0x7F]);
	471	break;
	472	}
321	473	}
322	474
323	475
324		~~stat~~ic ~~CPU_RESET(~~ hcd62121 )
	476	void hcd62121_cpu_device::device_reset()
325	477	{
326		hcd62121_state *cpustate = get_safe_token(device);
	478	m_sp = 0x0000;
	479	m_ip = 0x0000;
	480	m_cseg = 0;
	481	m_dseg = 0;
	482	m_sseg = 0;
	483	m_lar = 0;
	484	m_f = 0;
	485	m_dsize = 0;
327	486
328		cpustate->sp = 0x0000;
329		cpustate->ip = 0x0000;
330		cpustate->cseg = 0;
331		cpustate->dseg = 0;
332		cpustate->sseg = 0;
333		cpustate->lar = 0;
334		cpustate->f = 0;
335		cpustate->dsize = 0;
336
337	487	for( int i = 0; i < 0x80; i++ )
338	488	{
339		~~cpustate->~~reg[i] = 0;
	489	m_reg[i] = 0;
340	490	}
341	491	}
342	492
343	493
344		~~stat~~ic ~~CPU_EXECUTE(~~ hcd62121 )
	494	void hcd62121_cpu_device::execute_run()
345	495	{
346		hcd62121_state *cpustate = get_safe_token(device);
347
348	496	do
349	497	{
350		UINT32 pc = ( cpus~~tat~~e~~->cse~~g << 16 ) \| ~~cpustate->~~ip;
	498	UINT32 pc = ( m_cseg << 16 ) \| m_ip;
351	499	UINT8 op;
352	500
353		debugger_instruction_hook(device, pc);
354		cpustate->prev_pc = pc;
	501	debugger_instruction_hook(this, pc);
	502	m_prev_pc = pc;
355	503
356		op = read_op( ~~cpustate~~ );
	504	op = read_op();
357	505
358		~~cpustate->~~icount -= 4;
	506	m_icount -= 4;
359	507
360	508	switch ( op )
361	509	{
362	510	#include "hcd62121_ops.h"
363	511	};
364	512
365		} while (~~cpustate->~~icount > 0);
	513	} while (m_icount > 0);
366	514	}
367	515
368	516
369		static ~~CPU~~_~~SET_~~IN~~FO(~~ hcd62~~121~~ )
	517	offs_t hcd62121_cpu_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options)
370	518	{
371		hcd62121_state *cpustate = get_safe_token(device);
372
373		switch (state)
374		{
375		/* --- the following bits of info are set as 64-bit signed integers --- */
376		case CPUINFO_INT_INPUT_STATE + 0:
377		case CPUINFO_INT_INPUT_STATE + 1:
378		break;
379
380		case CPUINFO_INT_SP: cpustate->sp = info->i; break;
381		case CPUINFO_INT_PC: cpustate->ip = info->i; break;
382
383		case CPUINFO_INT_REGISTER + HCD62121_IP: cpustate->ip = info->i; break;
384		case CPUINFO_INT_REGISTER + HCD62121_SP: cpustate->sp = info->i; break;
385		case CPUINFO_INT_REGISTER + HCD62121_LAR: cpustate->lar = info->i; break;
386		case CPUINFO_INT_REGISTER + HCD62121_CS: cpustate->cseg = info->i; break;
387		case CPUINFO_INT_REGISTER + HCD62121_DS: cpustate->dseg = info->i; break;
388		case CPUINFO_INT_REGISTER + HCD62121_SS: cpustate->sseg = info->i; break;
389		case CPUINFO_INT_REGISTER + HCD62121_DSIZE: cpustate->dsize = info->i; break;
390		// case CPUINFO_INT_REGISTER + HCD62121_R00: break;
391		// case CPUINFO_INT_REGISTER + HCD62121_R02: break;
392		}
	519	extern CPU_DISASSEMBLE( hcd62121 );
	520	return CPU_DISASSEMBLE_NAME(hcd62121)(this, buffer, pc, oprom, opram, options);
393	521	}
394	522
395
396		CPU_GET_INFO( hcd62121 )
397		{
398		hcd62121_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
399
400		switch (state)
401		{
402		/* --- the following bits of info are returned as 64-bit signed integers --- */
403		case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(hcd62121_state); break;
404		case CPUINFO_INT_INPUT_LINES: info->i = 2; break;
405		case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0xff; break;
406		case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
407		case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
408		case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
409		case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break;
410		case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 18; break;
411		case CPUINFO_INT_MIN_CYCLES: info->i = 4; /* right? */ break;
412		case CPUINFO_INT_MAX_CYCLES: info->i = 48; /* right? */ break;
413
414		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break;
415		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break;
416		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
417		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
418		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
419		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
420		case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 8; break;
421		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 8; break;
422		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
423
424		case CPUINFO_INT_SP: info->i = cpustate->sp; break;
425		case CPUINFO_INT_PC: info->i = ( cpustate->cseg << 16 ) \| cpustate->ip; break;
426		case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->prev_pc; break;
427
428		case CPUINFO_INT_INPUT_STATE + 0:
429		case CPUINFO_INT_INPUT_STATE + 1:
430		/* TODO */ break;
431
432		case CPUINFO_INT_REGISTER + HCD62121_IP: info->i = cpustate->ip; break;
433		case CPUINFO_INT_REGISTER + HCD62121_SP: info->i = cpustate->sp; break;
434		case CPUINFO_INT_REGISTER + HCD62121_LAR: info->i = cpustate->lar; break;
435		case CPUINFO_INT_REGISTER + HCD62121_CS: info->i = cpustate->cseg; break;
436		case CPUINFO_INT_REGISTER + HCD62121_DS: info->i = cpustate->dseg; break;
437		case CPUINFO_INT_REGISTER + HCD62121_SS: info->i = cpustate->sseg; break;
438		case CPUINFO_INT_REGISTER + HCD62121_DSIZE: info->i = cpustate->dsize; break;
439		case CPUINFO_INT_REGISTER + HCD62121_R00: info->i = ( cpustate->reg[0x00] << 24 ) \| ( cpustate->reg[0x01] << 16 ) \| ( cpustate->reg[0x02] << 8 ) \| cpustate->reg[0x03]; break;
440		// case CPUINFO_INT_REGISTER + HCD62121_R02: info->i = cpustate->; break;
441
442		/* --- the following bits of info are returned as pointers to data or functions --- */
443		case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(hcd62121); break;
444		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(hcd62121); break;
445		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(hcd62121); break;
446		case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(hcd62121); break;
447		case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(hcd62121); break;
448		case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
449
450		/* --- the following bits of info are returned as NULL-terminated strings --- */
451		case CPUINFO_STR_NAME: strcpy(info->s, "HCD62121"); break;
452		case CPUINFO_STR_FAMILY: strcpy(info->s, "Hitachi HCD62121"); break;
453		case CPUINFO_STR_VERSION: strcpy(info->s, "0.1"); break;
454		case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
455		case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright The MESS Team."); break;
456
457		case CPUINFO_STR_FLAGS:
458		sprintf(info->s, "%s-%s-%s-%c-%c",
459		cpustate->f & _FLAG_ZH ? "ZH":"__",
460		cpustate->f & _FLAG_CL ? "CL":"__",
461		cpustate->f & _FLAG_ZL ? "ZL":"__",
462		cpustate->f & _FLAG_C ? 'C':'_',
463		cpustate->f & _FLAG_Z ? 'Z':'_'
464		);
465		break;
466
467		case CPUINFO_STR_REGISTER + HCD62121_IP: sprintf(info->s, "IP:%04X", cpustate->ip); break;
468		case CPUINFO_STR_REGISTER + HCD62121_SP: sprintf(info->s, "SP:%04X", cpustate->sp); break;
469		case CPUINFO_STR_REGISTER + HCD62121_LAR: sprintf(info->s, "LAR:%04X", cpustate->lar); break;
470		case CPUINFO_STR_REGISTER + HCD62121_CS: sprintf(info->s, "CS:%02X", cpustate->cseg); break;
471		case CPUINFO_STR_REGISTER + HCD62121_DS: sprintf(info->s, "DS:%02X", cpustate->dseg); break;
472		case CPUINFO_STR_REGISTER + HCD62121_SS: sprintf(info->s, "SS:%02X", cpustate->sseg); break;
473		case CPUINFO_STR_REGISTER + HCD62121_DSIZE: sprintf(info->s, "DSIZE:%02X", cpustate->dsize); break;
474		case CPUINFO_STR_REGISTER + HCD62121_R00: sprintf(info->s, "R00:%02X%02X%02X%02X", cpustate->reg[0x00], cpustate->reg[0x01], cpustate->reg[0x02], cpustate->reg[0x03]); break;
475		case CPUINFO_STR_REGISTER + HCD62121_R04: sprintf(info->s, "R04:%02X%02X%02X%02X", cpustate->reg[0x04], cpustate->reg[0x05], cpustate->reg[0x06], cpustate->reg[0x07]); break;
476		case CPUINFO_STR_REGISTER + HCD62121_R08: sprintf(info->s, "R08:%02X%02X%02X%02X", cpustate->reg[0x08], cpustate->reg[0x09], cpustate->reg[0x0a], cpustate->reg[0x0b]); break;
477		case CPUINFO_STR_REGISTER + HCD62121_R0C: sprintf(info->s, "R0C:%02X%02X%02X%02X", cpustate->reg[0x0c], cpustate->reg[0x0d], cpustate->reg[0x0e], cpustate->reg[0x0f]); break;
478		case CPUINFO_STR_REGISTER + HCD62121_R10: sprintf(info->s, "R10:%02X%02X%02X%02X", cpustate->reg[0x10], cpustate->reg[0x11], cpustate->reg[0x12], cpustate->reg[0x13]); break;
479		case CPUINFO_STR_REGISTER + HCD62121_R14: sprintf(info->s, "R14:%02X%02X%02X%02X", cpustate->reg[0x14], cpustate->reg[0x15], cpustate->reg[0x16], cpustate->reg[0x17]); break;
480		case CPUINFO_STR_REGISTER + HCD62121_R18: sprintf(info->s, "R18:%02X%02X%02X%02X", cpustate->reg[0x18], cpustate->reg[0x19], cpustate->reg[0x1a], cpustate->reg[0x1b]); break;
481		case CPUINFO_STR_REGISTER + HCD62121_R1C: sprintf(info->s, "R1C:%02X%02X%02X%02X", cpustate->reg[0x1c], cpustate->reg[0x1d], cpustate->reg[0x1e], cpustate->reg[0x1f]); break;
482		case CPUINFO_STR_REGISTER + HCD62121_R20: sprintf(info->s, "R20:%02X%02X%02X%02X", cpustate->reg[0x20], cpustate->reg[0x21], cpustate->reg[0x22], cpustate->reg[0x23]); break;
483		case CPUINFO_STR_REGISTER + HCD62121_R24: sprintf(info->s, "R24:%02X%02X%02X%02X", cpustate->reg[0x24], cpustate->reg[0x25], cpustate->reg[0x26], cpustate->reg[0x27]); break;
484		case CPUINFO_STR_REGISTER + HCD62121_R28: sprintf(info->s, "R28:%02X%02X%02X%02X", cpustate->reg[0x28], cpustate->reg[0x29], cpustate->reg[0x2a], cpustate->reg[0x2b]); break;
485		case CPUINFO_STR_REGISTER + HCD62121_R2C: sprintf(info->s, "R2C:%02X%02X%02X%02X", cpustate->reg[0x2c], cpustate->reg[0x2d], cpustate->reg[0x2e], cpustate->reg[0x2f]); break;
486		case CPUINFO_STR_REGISTER + HCD62121_R30: sprintf(info->s, "R30:%02X%02X%02X%02X", cpustate->reg[0x30], cpustate->reg[0x31], cpustate->reg[0x32], cpustate->reg[0x33]); break;
487		case CPUINFO_STR_REGISTER + HCD62121_R34: sprintf(info->s, "R34:%02X%02X%02X%02X", cpustate->reg[0x34], cpustate->reg[0x35], cpustate->reg[0x36], cpustate->reg[0x37]); break;
488		case CPUINFO_STR_REGISTER + HCD62121_R38: sprintf(info->s, "R38:%02X%02X%02X%02X", cpustate->reg[0x38], cpustate->reg[0x39], cpustate->reg[0x3a], cpustate->reg[0x3b]); break;
489		case CPUINFO_STR_REGISTER + HCD62121_R3C: sprintf(info->s, "R3C:%02X%02X%02X%02X", cpustate->reg[0x3c], cpustate->reg[0x3d], cpustate->reg[0x3e], cpustate->reg[0x3f]); break;
490		case CPUINFO_STR_REGISTER + HCD62121_R40: sprintf(info->s, "R40:%02X%02X%02X%02X", cpustate->reg[0x40], cpustate->reg[0x41], cpustate->reg[0x42], cpustate->reg[0x43]); break;
491		case CPUINFO_STR_REGISTER + HCD62121_R44: sprintf(info->s, "R44:%02X%02X%02X%02X", cpustate->reg[0x44], cpustate->reg[0x45], cpustate->reg[0x46], cpustate->reg[0x47]); break;
492		case CPUINFO_STR_REGISTER + HCD62121_R48: sprintf(info->s, "R48:%02X%02X%02X%02X", cpustate->reg[0x48], cpustate->reg[0x49], cpustate->reg[0x4a], cpustate->reg[0x4b]); break;
493		case CPUINFO_STR_REGISTER + HCD62121_R4C: sprintf(info->s, "R4C:%02X%02X%02X%02X", cpustate->reg[0x4c], cpustate->reg[0x4d], cpustate->reg[0x4e], cpustate->reg[0x4f]); break;
494		case CPUINFO_STR_REGISTER + HCD62121_R50: sprintf(info->s, "R50:%02X%02X%02X%02X", cpustate->reg[0x50], cpustate->reg[0x51], cpustate->reg[0x52], cpustate->reg[0x53]); break;
495		case CPUINFO_STR_REGISTER + HCD62121_R54: sprintf(info->s, "R54:%02X%02X%02X%02X", cpustate->reg[0x54], cpustate->reg[0x55], cpustate->reg[0x56], cpustate->reg[0x57]); break;
496		case CPUINFO_STR_REGISTER + HCD62121_R58: sprintf(info->s, "R58:%02X%02X%02X%02X", cpustate->reg[0x58], cpustate->reg[0x59], cpustate->reg[0x5a], cpustate->reg[0x5b]); break;
497		case CPUINFO_STR_REGISTER + HCD62121_R5C: sprintf(info->s, "R5C:%02X%02X%02X%02X", cpustate->reg[0x5c], cpustate->reg[0x5d], cpustate->reg[0x5e], cpustate->reg[0x5f]); break;
498		case CPUINFO_STR_REGISTER + HCD62121_R60: sprintf(info->s, "R60:%02X%02X%02X%02X", cpustate->reg[0x60], cpustate->reg[0x61], cpustate->reg[0x62], cpustate->reg[0x63]); break;
499		case CPUINFO_STR_REGISTER + HCD62121_R64: sprintf(info->s, "R64:%02X%02X%02X%02X", cpustate->reg[0x64], cpustate->reg[0x65], cpustate->reg[0x66], cpustate->reg[0x67]); break;
500		case CPUINFO_STR_REGISTER + HCD62121_R68: sprintf(info->s, "R68:%02X%02X%02X%02X", cpustate->reg[0x68], cpustate->reg[0x69], cpustate->reg[0x6a], cpustate->reg[0x6b]); break;
501		case CPUINFO_STR_REGISTER + HCD62121_R6C: sprintf(info->s, "R6C:%02X%02X%02X%02X", cpustate->reg[0x6c], cpustate->reg[0x6d], cpustate->reg[0x6e], cpustate->reg[0x6f]); break;
502		case CPUINFO_STR_REGISTER + HCD62121_R70: sprintf(info->s, "R70:%02X%02X%02X%02X", cpustate->reg[0x70], cpustate->reg[0x71], cpustate->reg[0x72], cpustate->reg[0x73]); break;
503		case CPUINFO_STR_REGISTER + HCD62121_R74: sprintf(info->s, "R74:%02X%02X%02X%02X", cpustate->reg[0x74], cpustate->reg[0x75], cpustate->reg[0x76], cpustate->reg[0x77]); break;
504		case CPUINFO_STR_REGISTER + HCD62121_R78: sprintf(info->s, "R78:%02X%02X%02X%02X", cpustate->reg[0x78], cpustate->reg[0x79], cpustate->reg[0x7a], cpustate->reg[0x7b]); break;
505		case CPUINFO_STR_REGISTER + HCD62121_R7C: sprintf(info->s, "R7C:%02X%02X%02X%02X", cpustate->reg[0x7c], cpustate->reg[0x7d], cpustate->reg[0x7e], cpustate->reg[0x7f]); break;
506		}
507		}
508
509		DEFINE_LEGACY_CPU_DEVICE(HCD62121, hcd62121);

trunk/src/emu/cpu/hcd62121/hcd62121.h
r23685	r23686
31	31	};
32	32
33	33
34		DECLARE_LEGACY_CPU_DEVICE(HCD62121, hcd62121);
	34	class hcd62121_cpu_device : public cpu_device
	35	{
	36	public:
	37	// construction/destruction
	38	hcd62121_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
35	39
	40	protected:
	41	// device-level overrides
	42	virtual void device_start();
	43	virtual void device_reset();
36	44
37		extern CPU_DISASSEMBLE( hcd62121 );
	45	// device_execute_interface overrides
	46	virtual UINT32 execute_min_cycles() const { return 4; }
	47	virtual UINT32 execute_max_cycles() const { return 48; }
	48	virtual UINT32 execute_input_lines() const { return 2; }
	49	virtual void execute_run();
38	50
	51	// device_memory_interface overrides
	52	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); }
	53
	54	// device_state_interface overrides
	55	void state_string_export(const device_state_entry &entry, astring &string);
	56
	57	// device_disasm_interface overrides
	58	virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
	59	virtual UINT32 disasm_max_opcode_bytes() const { return 18; }
	60	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	61
	62	UINT8 read_op();
	63	UINT8 datasize( UINT8 op );
	64	void read_reg( int size, UINT8 op1 );
	65	void write_reg( int size, UINT8 op1 );
	66	void read_regreg( int size, UINT8 op1, UINT8 op2, bool op_is_logical );
	67	void write_regreg( int size, UINT8 op1, UINT8 op2 );
	68	void read_iregreg( int size, UINT8 op1, UINT8 op2 );
	69	void write_iregreg( int size, UINT8 op1, UINT8 op2 );
	70	void write_iregreg2( int size, UINT8 op1, UINT8 op2 );
	71	int check_cond( UINT8 op );
	72
	73	address_space_config m_program_config;
	74	address_space_config m_io_config;
	75
	76	UINT32 m_prev_pc;
	77	UINT16 m_sp;
	78	UINT16 m_ip;
	79	UINT8 m_dsize;
	80	UINT8 m_cseg;
	81	UINT8 m_dseg;
	82	UINT8 m_sseg;
	83	UINT8 m_f;
	84	UINT16 m_lar;
	85	UINT8 m_reg[0x80];
	86	UINT8 m_temp1[0x10];
	87	UINT8 m_temp2[0x10];
	88
	89	address_space *m_program;
	90	address_space *m_io;
	91	int m_icount;
	92	};
	93
	94
	95	extern const device_type HCD62121;
	96
	97
39	98	#endif /* __HCD62121_H__ */

trunk/src/emu/cpu/hcd62121/hcd62121_ops.h
r23685	r23686
6	6	\
7	7	for ( i = 0; i < size; i++ ) \
8	8	{ \
9		if ( ( ~~cpus~~tate~~->te~~mp1[i] & ~~cpus~~tate~~->te~~mp2[i] ) != ~~cpustate->~~temp2[i] ) \
	9	if ( ( m_temp1[i] & m_temp2[i] ) != m_temp2[i] ) \
10	10	mskres = 0; \
11	11	} \
12	12	\
13	13	if ( mskres ) \
14		~~cpustate->~~f &= ~_FLAG_Z; \
	14	m_f &= ~_FLAG_Z; \
15	15	else \
16		~~cpustate->~~f \|= _FLAG_Z; \
	16	m_f \|= _FLAG_Z; \
17	17	}
18	18
19	19	#define HCD62121_IMSK \
r23685	r23686
24	24	\
25	25	for ( i = 0; i < size; i++ ) \
26	26	{ \
27		if ( ( ~~cpus~~tate~~->te~~mp1[i] & ~~~cpus~~tate~~->te~~mp2[i] ) != ~~~cpustate->~~temp2[i] ) \
	27	if ( ( m_temp1[i] & ~m_temp2[i] ) != ~m_temp2[i] ) \
28	28	mskres = 0; \
29		if ( ~~cpus~~tate~~->te~~mp1[i] \| ~~cpustate->~~temp2[i] ) \
	29	if ( m_temp1[i] \| m_temp2[i] ) \
30	30	set_zero = 1; \
31	31	} \
32	32	\
33	33	if ( set_zero ) \
34		~~cpustate->~~f \|= _FLAG_Z; \
	34	m_f \|= _FLAG_Z; \
35	35	else \
36		~~cpustate->~~f &= ~_FLAG_Z; \
	36	m_f &= ~_FLAG_Z; \
37	37	\
38	38	if ( mskres ) \
39		~~cpustate->~~f &= ~_FLAG_C; \
	39	m_f &= ~_FLAG_C; \
40	40	else \
41		~~cpustate->~~f \|= _FLAG_C; \
	41	m_f \|= _FLAG_C; \
42	42	}
43	43
44	44
r23685	r23686
49	49	\
50	50	for ( i = 0; i < size; i++ ) \
51	51	{ \
52		cpustate->temp1[i] = cpustate->temp1[i] & cpustate->temp2[i]; \
53		if ( cpustate->temp1[i] ) \
	52	m_temp1[i] = m_temp1[i] & m_temp2[i]; \
	53	if ( m_temp1[i] ) \
54	54	is_zero = 0; \
55	55	} \
56	56	\
57	57	if ( is_zero ) \
58		~~cpustate->~~f \|= _FLAG_Z; \
	58	m_f \|= _FLAG_Z; \
59	59	else \
60		~~cpustate->~~f &= ~_FLAG_Z; \
	60	m_f &= ~_FLAG_Z; \
61	61	\
62		if ( cpustate->temp1[0] & 0x0f ) \
63		cpustate->f &= ~_FLAG_ZL; \
	62	if ( m_temp1[0] & 0x0f ) \
	63	m_f &= ~_FLAG_ZL; \
64	64	else \
65		~~cpustate->~~f \|= _FLAG_ZL; \
	65	m_f \|= _FLAG_ZL; \
66	66	\
67		if ( cpustate->temp1[0] & 0xf0 ) \
68		cpustate->f &= ~_FLAG_ZH; \
	67	if ( m_temp1[0] & 0xf0 ) \
	68	m_f &= ~_FLAG_ZH; \
69	69	else \
70		~~cpustate->~~f \|= _FLAG_ZH; \
	70	m_f \|= _FLAG_ZH; \
71	71	}
72	72
73	73	#define HCD62121_OR \
r23685	r23686
77	77	\
78	78	for ( i = 0; i < size; i++ ) \
79	79	{ \
80		cpustate->temp1[i] = cpustate->temp1[i] \| cpustate->temp2[i]; \
81		if ( cpustate->temp1[i] ) \
	80	m_temp1[i] = m_temp1[i] \| m_temp2[i]; \
	81	if ( m_temp1[i] ) \
82	82	is_zero = 0; \
83	83	} \
84	84	\
85	85	if ( is_zero ) \
86		~~cpustate->~~f \|= _FLAG_Z; \
	86	m_f \|= _FLAG_Z; \
87	87	else \
88		~~cpustate->~~f &= ~_FLAG_Z; \
	88	m_f &= ~_FLAG_Z; \
89	89	\
90		if ( cpustate->temp1[0] & 0x0f ) \
91		cpustate->f &= ~_FLAG_ZL; \
	90	if ( m_temp1[0] & 0x0f ) \
	91	m_f &= ~_FLAG_ZL; \
92	92	else \
93		~~cpustate->~~f \|= _FLAG_ZL; \
	93	m_f \|= _FLAG_ZL; \
94	94	\
95		if ( cpustate->temp1[0] & 0xf0 ) \
96		cpustate->f &= ~_FLAG_ZH; \
	95	if ( m_temp1[0] & 0xf0 ) \
	96	m_f &= ~_FLAG_ZH; \
97	97	else \
98		~~cpustate->~~f \|= _FLAG_ZH; \
	98	m_f \|= _FLAG_ZH; \
99	99	}
100	100
101	101	#define HCD62121_XOR \
r23685	r23686
105	105	\
106	106	for ( i = 0; i < size; i++ ) \
107	107	{ \
108		cpustate->temp1[i] = cpustate->temp1[i] ^ cpustate->temp2[i]; \
109		if ( cpustate->temp1[i] ) \
	108	m_temp1[i] = m_temp1[i] ^ m_temp2[i]; \
	109	if ( m_temp1[i] ) \
110	110	is_zero = 0; \
111	111	} \
112	112	\
113	113	if ( is_zero ) \
114		~~cpustate->~~f \|= _FLAG_Z; \
	114	m_f \|= _FLAG_Z; \
115	115	else \
116		~~cpustate->~~f &= ~_FLAG_Z; \
	116	m_f &= ~_FLAG_Z; \
117	117	\
118		if ( cpustate->temp1[0] & 0x0f ) \
119		cpustate->f &= ~_FLAG_ZL; \
	118	if ( m_temp1[0] & 0x0f ) \
	119	m_f &= ~_FLAG_ZL; \
120	120	else \
121		~~cpustate->~~f \|= _FLAG_ZL; \
	121	m_f \|= _FLAG_ZL; \
122	122	\
123		if ( cpustate->temp1[0] & 0xf0 ) \
124		cpustate->f &= ~_FLAG_ZH; \
	123	if ( m_temp1[0] & 0xf0 ) \
	124	m_f &= ~_FLAG_ZH; \
125	125	else \
126		~~cpustate->~~f \|= _FLAG_ZH; \
	126	m_f \|= _FLAG_ZH; \
127	127	}
128	128
129	129	#define HCD62121_ADD \
r23685	r23686
131	131	int i; \
132	132	UINT8 is_zero = 1, carry = 0; \
133	133	\
134		if ( ( cpustate->temp1[0] & 0x0f ) + ( cpustate->temp2[0] & 0x0f ) > 15 ) \
135		cpustate->f \|= _FLAG_CL; \
	134	if ( ( m_temp1[0] & 0x0f ) + ( m_temp2[0] & 0x0f ) > 15 ) \
	135	m_f \|= _FLAG_CL; \
136	136	else \
137		~~cpustate->~~f &= ~_FLAG_CL; \
	137	m_f &= ~_FLAG_CL; \
138	138	\
139	139	for ( i = 0; i < size; i++ ) \
140	140	{ \
141		UINT16 res = ~~cpus~~tate~~->te~~mp1[i] + ~~cpustate->~~temp2[i] + carry; \
	141	UINT16 res = m_temp1[i] + m_temp2[i] + carry; \
142	142	\
143		cpustate->temp1[i] = res & 0xff; \
144		if ( cpustate->temp1[i] ) \
	143	m_temp1[i] = res & 0xff; \
	144	if ( m_temp1[i] ) \
145	145	is_zero = 0; \
146	146	\
147	147	carry = ( res & 0xff00 ) ? 1 : 0; \
148	148	} \
149	149	\
150	150	if ( is_zero ) \
151		~~cpustate->~~f \|= _FLAG_Z; \
	151	m_f \|= _FLAG_Z; \
152	152	else \
153		~~cpustate->~~f &= ~_FLAG_Z; \
	153	m_f &= ~_FLAG_Z; \
154	154	\
155	155	if ( carry ) \
156		~~cpustate->~~f \|= _FLAG_C; \
	156	m_f \|= _FLAG_C; \
157	157	else \
158		~~cpustate->~~f &= ~_FLAG_C; \
	158	m_f &= ~_FLAG_C; \
159	159	\
160		if ( cpustate->temp1[0] & 0x0f ) \
161		cpustate->f &= ~_FLAG_ZL; \
	160	if ( m_temp1[0] & 0x0f ) \
	161	m_f &= ~_FLAG_ZL; \
162	162	else \
163		~~cpustate->~~f \|= _FLAG_ZL; \
	163	m_f \|= _FLAG_ZL; \
164	164	\
165		if ( cpustate->temp1[0] & 0xf0 ) \
166		cpustate->f &= ~_FLAG_ZH; \
	165	if ( m_temp1[0] & 0xf0 ) \
	166	m_f &= ~_FLAG_ZH; \
167	167	else \
168		~~cpustate->~~f \|= _FLAG_ZH; \
	168	m_f \|= _FLAG_ZH; \
169	169	}
170	170
171	171	/* BCD ADD */
r23685	r23686
174	174	int i; \
175	175	UINT8 is_zero = 1, carry = 0; \
176	176	\
177		if ( ( cpustate->temp1[0] & 0x0f ) + ( cpustate->temp2[0] & 0x0f ) > 9 ) \
178		cpustate->f \|= _FLAG_CL; \
	177	if ( ( m_temp1[0] & 0x0f ) + ( m_temp2[0] & 0x0f ) > 9 ) \
	178	m_f \|= _FLAG_CL; \
179	179	else \
180		~~cpustate->~~f &= ~_FLAG_CL; \
	180	m_f &= ~_FLAG_CL; \
181	181	\
182	182	for ( i = 0; i < size; i++ ) \
183	183	{ \
184		UINT16 res = ( ~~cpus~~tate~~->te~~mp1[i] & 0x0f ) + ( ~~cpustate->~~temp2[i] & 0x0f ) + carry; \
	184	UINT16 res = ( m_temp1[i] & 0x0f ) + ( m_temp2[i] & 0x0f ) + carry; \
185	185	\
186	186	carry = 0; \
187	187	if ( res > 9 ) \
188	188	{ \
189	189	res += 6; \
190	190	} \
191		res += ( ~~cpus~~tate~~->te~~mp1[i] & 0xf0 ) + ( ~~cpustate->~~temp2[i] & 0xf0 ); \
	191	res += ( m_temp1[i] & 0xf0 ) + ( m_temp2[i] & 0xf0 ); \
192	192	if ( res > 0x9f ) \
193	193	{ \
194	194	res += 0x60; \
195	195	} \
196		cpustate->temp1[i] = res & 0xff; \
197		if ( cpustate->temp1[i] ) \
	196	m_temp1[i] = res & 0xff; \
	197	if ( m_temp1[i] ) \
198	198	is_zero = 0; \
199	199	\
200	200	carry = ( res & 0xff00 ) ? 1 : 0; \
201	201	} \
202	202	\
203	203	if ( is_zero ) \
204		~~cpustate->~~f \|= _FLAG_Z; \
	204	m_f \|= _FLAG_Z; \
205	205	else \
206		~~cpustate->~~f &= ~_FLAG_Z; \
	206	m_f &= ~_FLAG_Z; \
207	207	\
208	208	if ( carry ) \
209		~~cpustate->~~f \|= _FLAG_C; \
	209	m_f \|= _FLAG_C; \
210	210	else \
211		~~cpustate->~~f &= ~_FLAG_C; \
	211	m_f &= ~_FLAG_C; \
212	212	\
213		if ( cpustate->temp1[0] & 0x0f ) \
214		cpustate->f &= ~_FLAG_ZL; \
	213	if ( m_temp1[0] & 0x0f ) \
	214	m_f &= ~_FLAG_ZL; \
215	215	else \
216		~~cpustate->~~f \|= _FLAG_ZL; \
	216	m_f \|= _FLAG_ZL; \
217	217	\
218		if ( cpustate->temp1[0] & 0xf0 ) \
219		cpustate->f &= ~_FLAG_ZH; \
	218	if ( m_temp1[0] & 0xf0 ) \
	219	m_f &= ~_FLAG_ZH; \
220	220	else \
221		~~cpustate->~~f \|= _FLAG_ZH; \
	221	m_f \|= _FLAG_ZH; \
222	222	}
223	223
224	224	#define HCD62121_SUB \
r23685	r23686
226	226	int i; \
227	227	UINT8 is_zero = 1, carry = 0; \
228	228	\
229		if ( ( cpustate->temp1[0] & 0x0f ) < ( cpustate->temp2[0] & 0x0f ) ) \
230		cpustate->f \|= _FLAG_CL; \
	229	if ( ( m_temp1[0] & 0x0f ) < ( m_temp2[0] & 0x0f ) ) \
	230	m_f \|= _FLAG_CL; \
231	231	else \
232		~~cpustate->~~f &= ~_FLAG_CL; \
	232	m_f &= ~_FLAG_CL; \
233	233	\
234	234	for ( i = 0; i < size; i++ ) \
235	235	{ \
236		UINT16 res = ~~cpus~~tate~~->te~~mp1[i] - ~~cpustate->~~temp2[i] - carry; \
	236	UINT16 res = m_temp1[i] - m_temp2[i] - carry; \
237	237	\
238		cpustate->temp1[i] = res & 0xff; \
239		if ( cpustate->temp1[i] ) \
	238	m_temp1[i] = res & 0xff; \
	239	if ( m_temp1[i] ) \
240	240	is_zero = 0; \
241	241	\
242	242	carry = ( res & 0xff00 ) ? 1 : 0; \
243	243	} \
244	244	\
245	245	if ( is_zero ) \
246		~~cpustate->~~f \|= _FLAG_Z; \
	246	m_f \|= _FLAG_Z; \
247	247	else \
248		~~cpustate->~~f &= ~_FLAG_Z; \
	248	m_f &= ~_FLAG_Z; \
249	249	\
250	250	if ( carry ) \
251		~~cpustate->~~f \|= _FLAG_C; \
	251	m_f \|= _FLAG_C; \
252	252	else \
253		~~cpustate->~~f &= ~_FLAG_C; \
	253	m_f &= ~_FLAG_C; \
254	254	\
255		if ( cpustate->temp1[0] & 0x0f ) \
256		cpustate->f &= ~_FLAG_ZL; \
	255	if ( m_temp1[0] & 0x0f ) \
	256	m_f &= ~_FLAG_ZL; \
257	257	else \
258		~~cpustate->~~f \|= _FLAG_ZL; \
	258	m_f \|= _FLAG_ZL; \
259	259	\
260		if ( cpustate->temp1[0] & 0xf0 ) \
261		cpustate->f &= ~_FLAG_ZH; \
	260	if ( m_temp1[0] & 0xf0 ) \
	261	m_f &= ~_FLAG_ZH; \
262	262	else \
263		~~cpustate->~~f \|= _FLAG_ZH; \
	263	m_f \|= _FLAG_ZH; \
264	264	}
265	265
266	266	#define HCD62121_PUSHW(source) \
267	267	{ \
268	268	UINT16 address = source; \
269		mem_writebyte( cpustate, ( cpustate->sseg << 16 ) \| cpustate->sp, ( address ) & 0xff ); \
270		cpustate->sp--; \
271		mem_writebyte( cpustate, ( cpustate->sseg << 16 ) \| cpustate->sp, ( address ) >> 8 ); \
272		cpustate->sp--; \
	269	m_program->write_byte( ( m_sseg << 16 ) \| m_sp, ( address ) & 0xff ); \
	270	m_sp--; \
	271	m_program->write_byte( ( m_sseg << 16 ) \| m_sp, ( address ) >> 8 ); \
	272	m_sp--; \
273	273	}
274	274
275	275	#define HCD62121_POPW(dest) \
276	276	{ \
277	277	UINT16 res; \
278		cpustate->sp++; \
279		res = mem_readbyte( cpustate, ( cpustate->sseg << 16 ) \| cpustate->sp ) << 8; \
280		cpustate->sp++; \
281		res \|= mem_readbyte( cpustate, ( cpustate->sseg << 16 ) \| cpustate->sp ); \
	278	m_sp++; \
	279	res = m_program->read_byte( ( m_sseg << 16 ) \| m_sp ) << 8; \
	280	m_sp++; \
	281	res \|= m_program->read_byte( ( m_sseg << 16 ) \| m_sp ); \
282	282	dest = res; \
283	283	}
284	284
r23685	r23686
287	287	case 0x06: /* mskq r1,r2 */
288	288	case 0x07: /* mskt r1,r2 */
289	289	{
290		int size = datasize( cpustate, op );
291		UINT8 reg1 = read_op( cpustate );
292		UINT8 reg2 = read_op( cpustate );
	290	int size = datasize( op );
	291	UINT8 reg1 = read_op();
	292	UINT8 reg2 = read_op();
293	293
294		read_regreg( ~~cpustate,~~ size, reg1, reg2, false );
	294	read_regreg( size, reg1, reg2, false );
295	295
296	296	HCD62121_MSK;
297	297	}
r23685	r23686
304	304	/* Shift is a nibble shift! */
305	305	{
306	306	int i;
307		int size = datasize( cpustate, op );
308		UINT8 reg1 = read_op( cpustate );
	307	int size = datasize( op );
	308	UINT8 reg1 = read_op();
309	309	UINT8 d1 = 0, d2 = 0;
310	310
311		read_reg( ~~cpustate,~~ size, reg1 );
	311	read_reg( size, reg1 );
312	312
313	313	for ( i = 0; i < size; i++ )
314	314	{
315	315	if ( reg1 & 0x80 )
316	316	{
317		d1 = ( cpustate->temp1[i] & 0x0f ) << 4;
318		cpustate->temp1[i] = ( cpustate->temp1[i] >> 4 ) \| d2;
	317	d1 = ( m_temp1[i] & 0x0f ) << 4;
	318	m_temp1[i] = ( m_temp1[i] >> 4 ) \| d2;
319	319	}
320	320	else
321	321	{
322		d1 = ( cpustate->temp1[i] & 0xf0 ) >> 4;
323		cpustate->temp1[i] = ( cpustate->temp1[i] << 4 ) \| d2;
	322	d1 = ( m_temp1[i] & 0xf0 ) >> 4;
	323	m_temp1[i] = ( m_temp1[i] << 4 ) \| d2;
324	324	}
325	325	d2 = d1;
326	326	}
327	327
328		write_reg( ~~cpustate,~~ size, reg1 );
	328	write_reg( size, reg1 );
329	329	}
330	330	break;
331	331
r23685	r23686
334	334	case 0x0E: /* testq r1,r2 */
335	335	case 0x0F: /* testt r1,r2 */
336	336	{
337		int size = datasize( cpustate, op );
338		UINT8 reg1 = read_op( cpustate );
339		UINT8 reg2 = read_op( cpustate );
	337	int size = datasize( op );
	338	UINT8 reg1 = read_op();
	339	UINT8 reg2 = read_op();
340	340
341		read_regreg( ~~cpustate,~~ size, reg1, reg2, false );
	341	read_regreg( size, reg1, reg2, false );
342	342
343	343	HCD62121_AND;
344	344	}
r23685	r23686
349	349	case 0x12: /* xorq r1,r2 */
350	350	case 0x13: /* xort r1,r2 */
351	351	{
352		int size = datasize( cpustate, op );
353		UINT8 reg1 = read_op( cpustate );
354		UINT8 reg2 = read_op( cpustate );
	352	int size = datasize( op );
	353	UINT8 reg1 = read_op();
	354	UINT8 reg2 = read_op();
355	355
356		read_regreg( ~~cpustate,~~ size, reg1, reg2, false );
	356	read_regreg( size, reg1, reg2, false );
357	357
358	358	HCD62121_XOR;
359	359
360		write_regreg( ~~cpustate,~~ size, reg1, reg2 );
	360	write_regreg( size, reg1, reg2 );
361	361	}
362	362	break;
363	363
r23685	r23686
366	366	case 0x16: /* cmpq r1,r2 */
367	367	case 0x17: /* cmpt r1,r2 */
368	368	{
369		int size = datasize( cpustate, op );
370		UINT8 reg1 = read_op( cpustate );
371		UINT8 reg2 = read_op( cpustate );
	369	int size = datasize( op );
	370	UINT8 reg1 = read_op();
	371	UINT8 reg2 = read_op();
372	372
373		read_regreg( ~~cpustate,~~ size, reg1, reg2, false );
	373	read_regreg( size, reg1, reg2, false );
374	374
375	375	HCD62121_SUB;
376	376	}
r23685	r23686
382	382	case 0x1B: /* movt r1,r2 */
383	383	{
384	384	int i;
385		int size = datasize( cpustate, op );
386		UINT8 reg1 = read_op( cpustate );
387		UINT8 reg2 = read_op( cpustate );
	385	int size = datasize( op );
	386	UINT8 reg1 = read_op();
	387	UINT8 reg2 = read_op();
388	388
389		read_regreg( ~~cpustate,~~ size, reg1, reg2, false );
	389	read_regreg( size, reg1, reg2, false );
390	390
391	391	for ( i = 0; i < size; i++ )
392		~~cpus~~tate~~->te~~mp1[i] = ~~cpustate->~~temp2[i];
	392	m_temp1[i] = m_temp2[i];
393	393
394		write_regreg( ~~cpustate,~~ size, reg1, reg2 );
	394	write_regreg( size, reg1, reg2 );
395	395	}
396	396	break;
397	397
r23685	r23686
400	400	case 0x1E: /* imskq r1,r2 */
401	401	case 0x1F: /* imskt r1,r2 */
402	402	{
403		int size = datasize( cpustate, op );
404		UINT8 reg1 = read_op( cpustate );
405		UINT8 reg2 = read_op( cpustate );
	403	int size = datasize( op );
	404	UINT8 reg1 = read_op();
	405	UINT8 reg2 = read_op();
406	406
407		read_regreg( ~~cpustate,~~ size, reg1, reg2, false );
	407	read_regreg( size, reg1, reg2, false );
408	408
409	409	HCD62121_IMSK;
410	410	}
r23685	r23686
417	417	/* Shift is a single shift! */
418	418	{
419	419	int i;
420		int size = datasize( cpustate, op );
421		UINT8 reg1 = read_op( cpustate );
	420	int size = datasize( op );
	421	UINT8 reg1 = read_op();
422	422	UINT8 d1 = 0, d2 = 0;
423	423
424		read_reg( ~~cpustate,~~ size, reg1 );
	424	read_reg( size, reg1 );
425	425
426	426	for ( i = 0; i < size; i++ )
427	427	{
428		d1 = ( cpustate->temp1[i] & 0x01 ) << 7;
429		cpustate->temp1[i] = ( cpustate->temp1[i] >> 1 ) \| d2;
	428	d1 = ( m_temp1[i] & 0x01 ) << 7;
	429	m_temp1[i] = ( m_temp1[i] >> 1 ) \| d2;
430	430	d2 = d1;
431	431	}
432	432
433		write_reg( ~~cpustate,~~ size, reg1 );
	433	write_reg( size, reg1 );
434	434	}
435	435	break;
436	436
r23685	r23686
439	439	case 0x26: /* orq r1,r2 */
440	440	case 0x27: /* ort r1,r2 */
441	441	{
442		int size = datasize( cpustate, op );
443		UINT8 reg1 = read_op( cpustate );
444		UINT8 reg2 = read_op( cpustate );
	442	int size = datasize( op );
	443	UINT8 reg1 = read_op();
	444	UINT8 reg2 = read_op();
445	445
446		read_regreg( ~~cpustate,~~ size, reg1, reg2, false );
	446	read_regreg( size, reg1, reg2, false );
447	447
448	448	HCD62121_OR;
449	449
450		write_regreg( ~~cpustate,~~ size, reg1, reg2 );
	450	write_regreg( size, reg1, reg2 );
451	451	}
452	452	break;
453	453
r23685	r23686
458	458	/* Shift is a single shift! */
459	459	{
460	460	int i;
461		int size = datasize( cpustate, op );
462		UINT8 reg1 = read_op( cpustate );
	461	int size = datasize( op );
	462	UINT8 reg1 = read_op();
463	463	UINT8 d1 = 0, d2 = 0;
464	464
465		read_reg( ~~cpustate,~~ size, reg1 );
	465	read_reg( size, reg1 );
466	466
467	467	for ( i = 0; i < size; i++ )
468	468	{
469		d1 = ( cpustate->temp1[i] & 0x80 ) >> 7;
470		cpustate->temp1[i] = ( cpustate->temp1[i] << 1 ) \| d2;
	469	d1 = ( m_temp1[i] & 0x80 ) >> 7;
	470	m_temp1[i] = ( m_temp1[i] << 1 ) \| d2;
471	471	d2 = d1;
472	472	}
473	473
474		write_reg( ~~cpustate,~~ size, reg1 );
	474	write_reg( size, reg1 );
475	475	}
476	476	break;
477	477
r23685	r23686
480	480	case 0x2E: /* andq r1,r2 */
481	481	case 0x2F: /* andt r1,r2 */
482	482	{
483		int size = datasize( cpustate, op );
484		UINT8 reg1 = read_op( cpustate );
485		UINT8 reg2 = read_op( cpustate );
	483	int size = datasize( op );
	484	UINT8 reg1 = read_op();
	485	UINT8 reg2 = read_op();
486	486
487		read_regreg( ~~cpustate,~~ size, reg1, reg2, true );
	487	read_regreg( size, reg1, reg2, true );
488	488
489	489	HCD62121_AND;
490	490
491		write_regreg( ~~cpustate,~~ size, reg1, reg2 );
	491	write_regreg( size, reg1, reg2 );
492	492	}
493	493	break;
494	494
r23685	r23686
497	497	case 0x36: /* subq r1,r2 */
498	498	case 0x37: /* subt r1,r2 */
499	499	{
500		int size = datasize( cpustate, op );
501		UINT8 reg1 = read_op( cpustate );
502		UINT8 reg2 = read_op( cpustate );
	500	int size = datasize( op );
	501	UINT8 reg1 = read_op();
	502	UINT8 reg2 = read_op();
503	503
504		read_regreg( ~~cpustate,~~ size, reg1, reg2, false );
	504	read_regreg( size, reg1, reg2, false );
505	505
506	506	HCD62121_SUB;
507	507
508		write_regreg( ~~cpustate,~~ size, reg1, reg2 );
	508	write_regreg( size, reg1, reg2 );
509	509	}
510	510	break;
511	511
r23685	r23686
514	514	case 0x3A: /* adbq r1,r2 */
515	515	case 0x3B: /* adbt r1,r2 */
516	516	{
517		int size = datasize( cpustate, op );
518		UINT8 reg1 = read_op( cpustate );
519		UINT8 reg2 = read_op( cpustate );
	517	int size = datasize( op );
	518	UINT8 reg1 = read_op();
	519	UINT8 reg2 = read_op();
520	520
521		read_regreg( ~~cpustate,~~ size, reg1, reg2, false );
	521	read_regreg( size, reg1, reg2, false );
522	522
523	523	HCD62121_ADDB;
524	524
525		write_regreg( ~~cpustate,~~ size, reg1, reg2 );
	525	write_regreg( size, reg1, reg2 );
526	526	}
527	527	break;
528	528
r23685	r23686
531	531	case 0x3E: /* addq r1,r2 */
532	532	case 0x3F: /* addt r1,r2 */
533	533	{
534		int size = datasize( cpustate, op );
535		UINT8 reg1 = read_op( cpustate );
536		UINT8 reg2 = read_op( cpustate );
	534	int size = datasize( op );
	535	UINT8 reg1 = read_op();
	536	UINT8 reg2 = read_op();
537	537
538		read_regreg( ~~cpustate,~~ size, reg1, reg2, false );
	538	read_regreg( size, reg1, reg2, false );
539	539
540	540	HCD62121_ADD;
541	541
542		write_regreg( ~~cpustate,~~ size, reg1, reg2 );
	542	write_regreg( size, reg1, reg2 );
543	543	}
544	544	break;
545	545
r23685	r23686
548	548	case 0x4E: /* testq ir1,r2 */
549	549	case 0x4F: /* testt ir1,r2 */
550	550	{
551		int size = datasize( cpustate, op );
552		UINT8 reg1 = read_op( cpustate );
553		UINT8 reg2 = read_op( cpustate );
	551	int size = datasize( op );
	552	UINT8 reg1 = read_op();
	553	UINT8 reg2 = read_op();
554	554
555		read_iregreg( ~~cpustate,~~ size, reg1, reg2 );
	555	read_iregreg( size, reg1, reg2 );
556	556
557	557	HCD62121_AND;
558	558	}
r23685	r23686
563	563	case 0x56: /* cmpq ir1,r2 */
564	564	case 0x57: /* cmpt ir1,r2 */
565	565	{
566		int size = datasize( cpustate, op );
567		UINT8 reg1 = read_op( cpustate );
568		UINT8 reg2 = read_op( cpustate );
	566	int size = datasize( op );
	567	UINT8 reg1 = read_op();
	568	UINT8 reg2 = read_op();
569	569
570		read_iregreg( ~~cpustate,~~ size, reg1, reg2 );
	570	read_iregreg( size, reg1, reg2 );
571	571
572	572	HCD62121_SUB;
573	573	}
r23685	r23686
579	579	case 0x5B: /* movt ir1,r2 */
580	580	{
581	581	int i;
582		int size = datasize( cpustate, op );
583		UINT8 reg1 = read_op( cpustate );
584		UINT8 reg2 = read_op( cpustate );
	582	int size = datasize( op );
	583	UINT8 reg1 = read_op();
	584	UINT8 reg2 = read_op();
585	585
586		read_iregreg( ~~cpustate,~~ size, reg1, reg2 );
	586	read_iregreg( size, reg1, reg2 );
587	587
588	588	for ( i = 0; i < size; i++ )
589		~~cpus~~tate~~->te~~mp1[i] = ~~cpustate->~~temp2[i];
	589	m_temp1[i] = m_temp2[i];
590	590
591		write_iregreg( ~~cpustate,~~ size, reg1, reg2 );
	591	write_iregreg( size, reg1, reg2 );
592	592	}
593	593	break;
594	594
r23685	r23686
597	597	case 0x66: /* orb ir1,r2 */
598	598	case 0x67: /* orb ir1,r2 */
599	599	{
600		int size = datasize( cpustate, op );
601		UINT8 reg1 = read_op( cpustate );
602		UINT8 reg2 = read_op( cpustate );
	600	int size = datasize( op );
	601	UINT8 reg1 = read_op();
	602	UINT8 reg2 = read_op();
603	603
604		read_iregreg( ~~cpustate,~~ size, reg1, reg2 );
	604	read_iregreg( size, reg1, reg2 );
605	605
606	606	HCD62121_OR;
607	607
608		write_iregreg( ~~cpustate,~~ size, reg1, reg2 );
	608	write_iregreg( size, reg1, reg2 );
609	609	}
610	610	break;
611	611
r23685	r23686
614	614	case 0x6E: /* andq ir1,r2 */
615	615	case 0x6F: /* andt ir1,r2 */
616	616	{
617		int size = datasize( cpustate, op );
618		UINT8 reg1 = read_op( cpustate );
619		UINT8 reg2 = read_op( cpustate );
	617	int size = datasize( op );
	618	UINT8 reg1 = read_op();
	619	UINT8 reg2 = read_op();
620	620
621		read_iregreg( ~~cpustate,~~ size, reg1, reg2 );
	621	read_iregreg( size, reg1, reg2 );
622	622
623	623	HCD62121_AND;
624	624
625		write_iregreg( ~~cpustate,~~ size, reg1, reg2 );
	625	write_iregreg( size, reg1, reg2 );
626	626	}
627	627	break;
628	628
r23685	r23686
631	631	case 0x7E: /* addq ir1,r2 */
632	632	case 0x7F: /* addt ir1,r2 */
633	633	{
634		int size = datasize( cpustate, op );
635		UINT8 reg1 = read_op( cpustate );
636		UINT8 reg2 = read_op( cpustate );
	634	int size = datasize( op );
	635	UINT8 reg1 = read_op();
	636	UINT8 reg2 = read_op();
637	637
638		read_iregreg( ~~cpustate,~~ size, reg1, reg2 );
	638	read_iregreg( size, reg1, reg2 );
639	639
640	640	HCD62121_ADD;
641	641
642		write_iregreg( ~~cpustate,~~ size, reg1, reg2 );
	642	write_iregreg( size, reg1, reg2 );
643	643	}
644	644	break;
645	645
646	646	case 0x88: /* jump _a16 */
647		~~cpustate->~~ip = ( read_op( ~~cpustate~~ ) << 8 ) \| read_op( ~~cpustate~~ );
	647	m_ip = ( read_op() << 8 ) \| read_op();
648	648	break;
649	649
650	650	case 0x89: /* jumpf cs:a16 */
651	651	{
652		UINT8 cs = read_op( cpustate );
653		UINT8 a1 = read_op( cpustate );
654		UINT8 a2 = read_op( cpustate );
	652	UINT8 cs = read_op();
	653	UINT8 a1 = read_op();
	654	UINT8 a2 = read_op();
655	655
656		cpustate->cseg = cs;
657		cpustate->ip = ( a1 << 8 ) \| a2;
	656	m_cseg = cs;
	657	m_ip = ( a1 << 8 ) \| a2;
658	658	}
659	659	break;
660	660
661	661	case 0x8A: /* call a16 */
662	662	{
663		UINT8 a1 = read_op( cpustate );
664		UINT8 a2 = read_op( cpustate );
	663	UINT8 a1 = read_op();
	664	UINT8 a2 = read_op();
665	665
666		HCD62121_PUSHW( ~~cpustate->~~ip );
	666	HCD62121_PUSHW( m_ip );
667	667
668		~~cpustate->~~ip = ( a1 << 8 ) \| a2;
	668	m_ip = ( a1 << 8 ) \| a2;
669	669	}
670	670	break;
671	671
672	672	case 0x8C: /* unk_8C */
673	673	case 0x8D: /* unk_8D */
674	674	case 0x8E: /* unk_8E */
675		logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpus~~tat~~e~~->cse~~g, ~~cpustate->~~ip-1, op );
	675	logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op );
676	676	break;
677	677
678	678	case 0x90: /* retzh */
r23685	r23686
683	683	case 0x95: /* retcl */
684	684	case 0x96: /* retnc */
685	685	case 0x97: /* retnz */
686		if ( check_cond( cpustate, op ) )
687		HCD62121_POPW( cpustate->ip );
	686	if ( check_cond( op ) )
	687	HCD62121_POPW( m_ip );
688	688	break;
689	689
690	690	case 0x98: /* jump (r1) */
691	691	{
692		UINT8 reg1 = read_op( cpustate );
693		UINT16 ad = cpustate->reg[ ( reg1 \| 0x40 ) & 0x7f ] << 8;
	692	UINT8 reg1 = read_op();
	693	UINT16 ad = m_reg[ ( reg1 \| 0x40 ) & 0x7f ] << 8;
694	694
695	695	if ( reg1 & 0x40 )
696		ad \|= ~~cpustate->~~reg[ ( ( reg1 - 1 ) \| 0x40 ) & 0x7f ];
	696	ad \|= m_reg[ ( ( reg1 - 1 ) \| 0x40 ) & 0x7f ];
697	697	else
698		ad \|= ~~cpustate->~~reg[ ( ( reg1 + 1 ) \| 0x40 ) & 0x7f ];
	698	ad \|= m_reg[ ( ( reg1 + 1 ) \| 0x40 ) & 0x7f ];
699	699
700		~~cpustate->~~ip = ad;
	700	m_ip = ad;
701	701	}
702	702	break;
703	703
704	704	case 0x9F: /* ret */
705		HCD62121_POPW( ~~cpustate->~~ip );
	705	HCD62121_POPW( m_ip );
706	706	break;
707	707
708	708	case 0xA0: /* jmpzh a16 */
r23685	r23686
714	714	case 0xA6: /* jmpnc a16 */
715	715	case 0xA7: /* jmpnz a16 */
716	716	{
717		UINT8 a1 = read_op( cpustate );
718		UINT8 a2 = read_op( cpustate );
	717	UINT8 a1 = read_op();
	718	UINT8 a2 = read_op();
719	719
720		if ( check_cond( cpustate, op ) )
721		cpustate->ip = ( a1 << 8 ) \| a2;
	720	if ( check_cond( op ) )
	721	m_ip = ( a1 << 8 ) \| a2;
722	722	}
723	723	break;
724	724
r23685	r23686
731	731	case 0xAE: /* callnc a16 */
732	732	case 0xAF: /* callnz a16 */
733	733	{
734		UINT8 a1 = read_op( cpustate );
735		UINT8 a2 = read_op( cpustate );
	734	UINT8 a1 = read_op();
	735	UINT8 a2 = read_op();
736	736
737		if ( check_cond( ~~cpustate,~~ op ) )
	737	if ( check_cond( op ) )
738	738	{
739		HCD62121_PUSHW( ~~cpustate->~~ip );
	739	HCD62121_PUSHW( m_ip );
740	740
741		~~cpustate->~~ip = ( a1 << 8 ) \| a2;
	741	m_ip = ( a1 << 8 ) \| a2;
742	742	}
743	743	}
744	744	break;
745	745
746	746	case 0xB1: /* unk_B1 reg/i8 */
747	747	case 0xB3: /* unk_B3 reg/i8 */
748		logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op );
749		read_op( cpustate );
	748	logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op );
	749	read_op();
750	750	break;
751	751
752	752	case 0xB4: /* out koh,reg */
753		io_writebyte( ~~cpustate,~~ HCD62121_KOH, ~~cpustate->~~reg[ read_op( ~~cpustate~~ ) & 0x7f ] );
	753	m_io->write_byte( HCD62121_KOH, m_reg[ read_op() & 0x7f ] );
754	754	break;
755	755
756	756	case 0xB5: /* out koh,i8 */
757		io_writebyte( ~~cpustate,~~ HCD62121_KOH, read_op( ~~cpustate~~ ) );
	757	m_io->write_byte( HCD62121_KOH, read_op() );
758	758	break;
759	759
760	760	case 0xB6: /* out kol,reg */
761		io_writebyte( ~~cpustate,~~ HCD62121_KOL, ~~cpustate->~~reg[ read_op( ~~cpustate~~ ) & 0x7f ] );
	761	m_io->write_byte( HCD62121_KOL, m_reg[ read_op() & 0x7f ] );
762	762	break;
763	763
764	764	case 0xB7: /* out kol,i8 */
765		io_writebyte( ~~cpustate,~~ HCD62121_KOL, read_op( ~~cpustate~~ ) );
	765	m_io->write_byte( HCD62121_KOL, read_op() );
766	766	break;
767	767
768	768	case 0xB9: /* unk_B9 reg/i8 */
769		logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op );
770		read_op( cpustate );
	769	logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op );
	770	read_op();
771	771	break;
772	772
773	773	case 0xBB: /* jmpcl? a16 */
774		logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpus~~tat~~e~~->cse~~g, ~~cpustate->~~ip-1, op );
	774	logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op );
775	775	{
776		UINT8 a1 = read_op( cpustate );
777		UINT8 a2 = read_op( cpustate );
	776	UINT8 a1 = read_op();
	777	UINT8 a2 = read_op();
778	778
779		if ( cpustate->f & _FLAG_CL )
780		cpustate->ip = ( a1 << 8 ) \| a2;
	779	if ( m_f & _FLAG_CL )
	780	m_ip = ( a1 << 8 ) \| a2;
781	781	}
782	782	break;
783	783
784	784	case 0xBF: /* jmpncl? a16 */
785		logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpus~~tat~~e~~->cse~~g, ~~cpustate->~~ip-1, op );
	785	logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op );
786	786	{
787		UINT8 a1 = read_op( cpustate );
788		UINT8 a2 = read_op( cpustate );
	787	UINT8 a1 = read_op();
	788	UINT8 a2 = read_op();
789	789
790		if ( ! ( cpustate->f & _FLAG_CL ) )
791		cpustate->ip = ( a1 << 8 ) \| a2;
	790	if ( ! ( m_f & _FLAG_CL ) )
	791	m_ip = ( a1 << 8 ) \| a2;
792	792	}
793	793	break;
794	794
r23685	r23686
798	798	case 0xC3: /* movw reg,i80 */
799	799	{
800	800	int i;
801		int size = datasize( cpustate, op );
802		UINT8 reg = read_op( cpustate );
	801	int size = datasize( op );
	802	UINT8 reg = read_op();
803	803
804	804	for( i = 0; i < size; i++ )
805	805	{
806		~~cpustate->~~reg[(reg + i) & 0x7f] = read_op( ~~cpustate~~ );
	806	m_reg[(reg + i) & 0x7f] = read_op();
807	807	}
808	808	}
809	809	break;
r23685	r23686
814	814	case 0xC7: /* movt (lar),r1 / r1,(lar) */
815	815	{
816	816	int i;
817		int size = datasize( cpustate, op );
818		UINT8 reg1 = read_op( cpustate );
819		UINT8 reg2 = read_op( cpustate );
	817	int size = datasize( op );
	818	UINT8 reg1 = read_op();
	819	UINT8 reg2 = read_op();
820	820	int pre_inc = 0;
821	821	int post_inc = 1;
822	822
r23685	r23686
845	845	/* (lar) <- r1 */
846	846	for ( i = 0; i < size; i++ )
847	847	{
848		cpustate->lar += pre_inc;
849		mem_writebyte( cpustate, ( cpustate->dseg << 16 ) \| cpustate->lar, cpustate->reg[ ( reg2 + i ) & 0x7f ] );
850		cpustate->lar += post_inc;
	848	m_lar += pre_inc;
	849	m_program->write_byte( ( m_dseg << 16 ) \| m_lar, m_reg[ ( reg2 + i ) & 0x7f ] );
	850	m_lar += post_inc;
851	851	}
852	852	}
853	853	else
r23685	r23686
855	855	/* r1 <- (lar) */
856	856	for ( i = 0; i < size; i++ )
857	857	{
858		cpustate->lar += pre_inc;
859		cpustate->reg[ ( reg2 + i ) & 0x7f ] = mem_readbyte( cpustate, ( cpustate->dseg << 16 ) \| cpustate->lar );
860		cpustate->lar += post_inc;
	858	m_lar += pre_inc;
	859	m_reg[ ( reg2 + i ) & 0x7f ] = m_program->read_byte( ( m_dseg << 16 ) \| m_lar );
	860	m_lar += post_inc;
861	861	}
862	862	}
863	863	}
r23685	r23686
869	869	case 0xCF: /* swapt ir1,r2? */
870	870	{
871	871	int i;
872		int size = datasize( cpustate, op );
873		UINT8 reg1 = read_op( cpustate );
874		UINT8 reg2 = read_op( cpustate );
	872	int size = datasize( op );
	873	UINT8 reg1 = read_op();
	874	UINT8 reg2 = read_op();
875	875
876		read_iregreg( ~~cpustate,~~ size, reg1, reg2 );
	876	read_iregreg( size, reg1, reg2 );
877	877
878	878	for ( i = 0; i < size; i++ )
879	879	{
880		UINT8 d = cpustate->temp1[i];
881		cpustate->temp1[i] = cpustate->temp2[i];
882		cpustate->temp2[i] = d;
	880	UINT8 d = m_temp1[i];
	881	m_temp1[i] = m_temp2[i];
	882	m_temp2[i] = d;
883	883	}
884	884
885		write_iregreg( cpustate, size, reg1, reg2 );
886		write_iregreg2( cpustate, size, reg1, reg2 );
	885	write_iregreg( size, reg1, reg2 );
	886	write_iregreg2( size, reg1, reg2 );
887	887	}
888	888	break;
889	889
890	890	case 0xD0: /* movb cs,reg */
891		cpus~~tat~~e~~->cse~~g = ~~cpustate->~~reg[ read_op( ~~cpustate~~ ) & 0x7f ];
	891	m_cseg = m_reg[ read_op() & 0x7f ];
892	892	break;
893	893
894	894	case 0xD1: /* movb cs,i8 */
895		cpus~~tat~~e~~->cse~~g = read_op( ~~cpustate~~ );
	895	m_cseg = read_op();
896	896	break;
897	897
898	898	case 0xD2: /* movb dsize,reg */
899		~~cpustate->~~dsize = ~~cpustate->~~reg[ read_op( ~~cpustate~~ ) & 0x7f ];
	899	m_dsize = m_reg[ read_op() & 0x7f ];
900	900	break;
901	901
902	902	case 0xD3: /* movb dsize,i8 */
903		~~cpustate->~~dsize = read_op( ~~cpustate~~ );
	903	m_dsize = read_op();
904	904	break;
905	905
906	906	case 0xD4: /* movb ss,reg */
907		~~cpu~~s~~tate->~~sseg = ~~cpustate->~~reg[ read_op( ~~cpustate~~ ) & 0x7f ];
	907	m_sseg = m_reg[ read_op() & 0x7f ];
908	908	break;
909	909
910	910	case 0xD5: /* movb ss,i8 */
911		~~cpu~~s~~tate->~~sseg = read_op( ~~cpustate~~ );
	911	m_sseg = read_op();
912	912	break;
913	913
914	914	case 0xD6: /* movw sp,reg */
915	915	{
916		UINT8 reg1 = read_op( ~~cpustate~~ );
	916	UINT8 reg1 = read_op();
917	917
918		~~cpu~~s~~tate->s~~p = ~~cpustate->~~reg[ reg1 & 0x7f ] \| ( ~~cpustate->~~reg[ ( reg1 + 1 ) & 0x7f ] << 8 );
	918	m_sp = m_reg[ reg1 & 0x7f ] \| ( m_reg[ ( reg1 + 1 ) & 0x7f ] << 8 );
919	919	}
920	920	break;
921	921
922	922	case 0xD7: /* movw sp,i16 */
923		cpustate->sp = read_op( cpustate) << 8;
924		cpustate->sp \|= read_op( cpustate );
	923	m_sp = read_op() << 8;
	924	m_sp \|= read_op();
925	925	break;
926	926
927	927	case 0xD8: /* movb f,reg */
928		~~cpustate->~~f = ~~cpustate->~~reg[ read_op( ~~cpustate~~ ) & 0x7f ];
	928	m_f = m_reg[ read_op() & 0x7f ];
929	929	break;
930	930
931	931	case 0xD9: /* movb f,i8 */
932		~~cpustate->~~f = read_op( ~~cpustate~~ );
	932	m_f = read_op();
933	933	break;
934	934
935	935	case 0xDC: /* movb ds,reg */
936		~~cpustate->~~dseg = ~~cpustate->~~reg[ read_op( ~~cpustate~~ ) & 0x7f ];
	936	m_dseg = m_reg[ read_op() & 0x7f ];
937	937	break;
938	938
939	939	case 0xDD: /* movb ds,i8 */
940		~~cpustate->~~dseg = read_op( ~~cpustate~~ );
	940	m_dseg = read_op();
941	941	break;
942	942
943	943	case 0xDE: /* movw lar,reg */
944	944	{
945		UINT8 reg1 = read_op( ~~cpustate~~ );
	945	UINT8 reg1 = read_op();
946	946
947		~~cpustate->~~lar = ~~cpustate->~~reg[ reg1 & 0x7f ] \| ( ~~cpustate->~~reg[ ( reg1 + 1 ) & 0x7f ] << 8 );
	947	m_lar = m_reg[ reg1 & 0x7f ] \| ( m_reg[ ( reg1 + 1 ) & 0x7f ] << 8 );
948	948	}
949	949	break;
950	950
951	951	case 0xE0: /* in0 reg */
952	952	{
953		UINT8 reg1 = read_op( ~~cpustate~~ );
	953	UINT8 reg1 = read_op();
954	954
955		~~cpustate->~~reg[ reg1 & 0x7f ] = io_readbyte( ~~cpustate,~~ HCD62121_IN0 );
	955	m_reg[ reg1 & 0x7f ] = m_io->read_byte( HCD62121_IN0 );
956	956	}
957	957	break;
958	958
959	959	case 0xE1: /* unk_E1 reg/i8 (in?) */
960		logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op );
961		read_op( cpustate );
	960	logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op );
	961	read_op();
962	962	break;
963	963
964	964	case 0xE2: /* in kb, reg */
965		~~cpustate->~~reg[ read_op( ~~cpustate~~ ) & 0x7f ] = io_readbyte( ~~cpustate,~~ HCD62121_KI );
	965	m_reg[ read_op() & 0x7f ] = m_io->read_byte( HCD62121_KI );
966	966	break;
967	967
968	968	case 0xE3: /* unk_e3 reg/i8 (in?) */
r23685	r23686
970	970	case 0xE5: /* unk_e5 reg/i8 (in?) */
971	971	case 0xE6: /* unk_e6 reg/i8 (in?) */
972	972	case 0xE7: /* unk_e7 reg/i8 (in?) */
973		logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op );
974		read_op( cpustate );
	973	logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op );
	974	read_op();
975	975	break;
976	976
977	977	case 0xE8: /* movw r1,lar */
978	978	{
979		UINT8 reg1 = read_op( ~~cpustate~~ );
	979	UINT8 reg1 = read_op();
980	980
981		cpustate->reg[ reg1 & 0x7f ] = cpustate->lar & 0xff;
982		cpustate->reg[ ( reg1 + 1 ) & 0x7f ] = cpustate->lar >> 8;
	981	m_reg[ reg1 & 0x7f ] = m_lar & 0xff;
	982	m_reg[ ( reg1 + 1 ) & 0x7f ] = m_lar >> 8;
983	983	}
984	984	break;
985	985
986	986	case 0xEB: /* movw reg,ss */
987	987	{
988		UINT8 reg1 = read_op( ~~cpustate~~ );
	988	UINT8 reg1 = read_op();
989	989
990		cpustate->reg[ reg1 & 0x7f ] = cpustate->sp & 0xff;
991		cpustate->reg[ ( reg1 + 1 ) & 0x7f ] = cpustate->sp >> 8;
	990	m_reg[ reg1 & 0x7f ] = m_sp & 0xff;
	991	m_reg[ ( reg1 + 1 ) & 0x7f ] = m_sp >> 8;
992	992	}
993	993	break;
994	994
995	995	case 0xEF: /* movb reg,ss */
996		~~cpustate->~~reg[ read_op( ~~cpustate~~ ) & 0x7f ] = ~~cpustate->~~sseg;
	996	m_reg[ read_op() & 0x7f ] = m_sseg;
997	997	break;
998	998
999	999	case 0xF0: /* unk_F0 reg/i8 (out?) */
r23685	r23686
1004	1004	case 0xF5: /* unk_F5 reg/i8 (out?) */
1005	1005	case 0xF6: /* unk_F6 reg/i8 (out?) */
1006	1006	case 0xF7: /* unk_F7 reg/i8 (out?) */
1007		logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpustate->cseg, cpustate->ip-1, op );
1008		read_op( cpustate );
	1007	logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op );
	1008	read_op();
1009	1009	break;
1010	1010
1011	1011	case 0xFC: /* unk_FC */
1012	1012	case 0xFD: /* unk_FD */
1013	1013	case 0xFE: /* unk_FE */
1014		logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpus~~tat~~e~~->cse~~g, ~~cpustate->~~ip-1, op );
	1014	logerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op );
1015	1015	break;
1016	1016
1017	1017	case 0xFF: /* nop */
1018	1018	break;
1019	1019
1020	1020	default:
1021		/logerror/fatalerror( "%02x:%04x: unimplemented instruction %02x encountered\n", cpus~~tat~~e~~->cse~~g, ~~cpustate->~~ip-1, op );
	1021	/logerror/fatalerror( "%02x:%04x: unimplemented instruction %02x encountered\n", m_cseg, m_ip-1, op );
1022	1022	break;

199869 Revisions