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r23678 Thursday 13th June, 2013 at 18:03:32 UTC by smf
Split hard drive emulation from the ide controller. [smf]

[src/emu/machine]

idectrl.c idectrl.h idehd.c idehd.h

trunk/src/emu/machine/idectrl.c

r23677	r23678
26	26	CONSTANTS
27	27	***************************************************************************/
28	28
29		#define MINIMUM_COMMAND_TIME                (attotime::from_usec(10))
30
31		#define TIME_PER_SECTOR                     (attotime::from_usec(100))
32		#define TIME_PER_ROTATION                   (attotime::from_hz(5400/60))
33		#define TIME_SECURITY_ERROR                 (attotime::from_msec(1000))
34
35		#define TIME_SEEK_MULTISECTOR               (attotime::from_msec(13))
36		#define TIME_NO_SEEK_MULTISECTOR            (attotime::from_nsec(16300))
37
38		#define IDE_BANK0_DATA                      0
39		#define IDE_BANK0_ERROR                     1
40		#define IDE_BANK0_SECTOR_COUNT              2
41		#define IDE_BANK0_SECTOR_NUMBER             3
42		#define IDE_BANK0_CYLINDER_LSB              4
43		#define IDE_BANK0_CYLINDER_MSB              5
44		#define IDE_BANK0_HEAD_NUMBER               6
45		#define IDE_BANK0_STATUS_COMMAND            7
46
47		#define IDE_BANK1_STATUS_CONTROL            6
48
49	29	#define IDE_BANK2_CONFIG_UNK                4
50	30	#define IDE_BANK2_CONFIG_REGISTER           8
51	31	#define IDE_BANK2_CONFIG_DATA               0xc
52	32
53		#define IDE_COMMAND_READ_SECTORS            0x20
54		#define IDE_COMMAND_READ_SECTORS_NORETRY    0x21
55		#define IDE_COMMAND_WRITE_SECTORS           0x30
56		#define IDE_COMMAND_WRITE_SECTORS_NORETRY   0x31
57		#define IDE_COMMAND_DIAGNOSTIC              0x90
58		#define IDE_COMMAND_SET_CONFIG              0x91
59		#define IDE_COMMAND_READ_MULTIPLE           0xc4
60		#define IDE_COMMAND_WRITE_MULTIPLE          0xc5
61		#define IDE_COMMAND_SET_BLOCK_COUNT         0xc6
62		#define IDE_COMMAND_READ_DMA                0xc8
63		#define IDE_COMMAND_WRITE_DMA               0xca
64		#define IDE_COMMAND_GET_INFO                0xec
65		#define IDE_COMMAND_SET_FEATURES            0xef
66		#define IDE_COMMAND_SECURITY_UNLOCK         0xf2
67		#define IDE_COMMAND_UNKNOWN_F9              0xf9
68		#define IDE_COMMAND_VERIFY_SECTORS          0x40
69		#define IDE_COMMAND_VERIFY_SECTORS_NORETRY  0x41
70		#define IDE_COMMAND_ATAPI_IDENTIFY          0xa1
71		#define IDE_COMMAND_RECALIBRATE             0x10
72		#define IDE_COMMAND_SEEK                    0x70
73		#define IDE_COMMAND_IDLE_IMMEDIATE          0xe1
74		#define IDE_COMMAND_IDLE                    0xe3
75		#define IDE_COMMAND_TAITO_GNET_UNLOCK_1     0xfe
76		#define IDE_COMMAND_TAITO_GNET_UNLOCK_2     0xfc
77		#define IDE_COMMAND_TAITO_GNET_UNLOCK_3     0x0f
78	33
79
80	34	void ide_controller_device::set_irq(int state)
81	35	{
82		ide_device_interface *dev = slot[cur_drive]->dev();
83
84		if (dev == NULL)
85		return;
86
87	36	if (state == ASSERT_LINE)
88	37	LOG(("IDE interrupt assert\n"));
89	38	else
r23677	r23678
91	40
92	41	/* signal an interrupt */
93	42	m_irq_handler(state);
94
95		if (dev != NULL)
96		dev->interrupt_pending = state;
97	43	}
98	44
99	45	void ide_controller_device::set_dmarq(int state)
100	46	{
	47	m_dmarq_handler(state);
101	48	}
102	49
103		enum
	50	WRITE_LINE_MEMBER( ide_controller_device::irq0_write_line )
104	51	{
105		TID_NULL,
106		TID_DELAYED_INTERRUPT,
107		TID_DELAYED_INTERRUPT_BUFFER_READY,
108		TID_RESET_CALLBACK,
109		TID_SECURITY_ERROR_DONE,
110		TID_READ_SECTOR_DONE_CALLBACK,
111		TID_WRITE_SECTOR_DONE_CALLBACK
112		};
	52	m_irq[0] = state;
113	53
114		void ide_controller_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
	54	set_irq(m_irq[0] == ASSERT_LINE || m_irq[1] == ASSERT_LINE);
	55	}
	56
	57	WRITE_LINE_MEMBER( ide_controller_device::irq1_write_line )
115	58	{
116		ide_device_interface *dev = slot[cur_drive]->dev();
	59	m_irq[1] = state;
117	60
118		switch(id)
119		{
120		case TID_DELAYED_INTERRUPT:
121		dev->status &= ~IDE_STATUS_BUSY;
122		set_irq(ASSERT_LINE);
123		break;
	61	set_irq(m_irq[0] == ASSERT_LINE || m_irq[1] == ASSERT_LINE);
	62	}
124	63
125		case TID_DELAYED_INTERRUPT_BUFFER_READY:
126		dev->status &= ~IDE_STATUS_BUSY;
127		dev->status |= IDE_STATUS_BUFFER_READY;
128		set_irq(ASSERT_LINE);
129		break;
	64	WRITE_LINE_MEMBER( ide_controller_device::dmarq0_write_line )
	65	{
	66	m_dmarq[0] = state;
130	67
131		case TID_SECURITY_ERROR_DONE:
132		/* clear error state */
133		dev->status &= ~IDE_STATUS_ERROR;
134		dev->status |= IDE_STATUS_DRIVE_READY;
135		break;
136
137		case TID_READ_SECTOR_DONE_CALLBACK:
138		read_sector_done();
139		break;
140
141		case TID_WRITE_SECTOR_DONE_CALLBACK:
142		write_sector_done();
143		break;
144		}
	68	set_dmarq(m_dmarq[0] == ASSERT_LINE || m_dmarq[1] == ASSERT_LINE);
145	69	}
146	70
147
148		void ide_controller_device::signal_delayed_interrupt(attotime time, int buffer_ready)
	71	WRITE_LINE_MEMBER( ide_controller_device::dmarq1_write_line )
149	72	{
150		ide_device_interface *dev = slot[cur_drive]->dev();
	73	m_dmarq[1] = state;
151	74
152		/* clear buffer ready and set the busy flag */
153		dev->status &= ~IDE_STATUS_BUFFER_READY;
154		dev->status |= IDE_STATUS_BUSY;
155
156		/* set a timer */
157		if (buffer_ready)
158		timer_set(time, TID_DELAYED_INTERRUPT_BUFFER_READY);
159		else
160		timer_set(time, TID_DELAYED_INTERRUPT);
	75	set_dmarq(m_dmarq[0] == ASSERT_LINE || m_dmarq[1] == ASSERT_LINE);
161	76	}
162	77
163	78
164
165	79	/***************************************************************************
166	80	INITIALIZATION AND RESET
167	81	***************************************************************************/
168	82
169	83	UINT8 *ide_controller_device::ide_get_features(int _drive)
170	84	{
171		return slot[_drive]->dev()->get_features();
	85	return m_slot[_drive]->dev()->get_features();
172	86	}
173	87
174	88	void ide_controller_device::ide_set_gnet_readlock(int _drive, const UINT8 onoff)
175	89	{
176		slot[_drive]->dev()->gnetreadlock = onoff;
	90	m_slot[_drive]->dev()->m_gnetreadlock = onoff;
177	91	}
178	92
179	93	void ide_controller_device::ide_set_master_password(int _drive, const UINT8 *password)
180	94	{
181		slot[_drive]->dev()->master_password = password;
182		slot[_drive]->dev()->master_password_enable = (password != NULL);
	95	m_slot[_drive]->dev()->m_master_password = password;
	96	m_slot[_drive]->dev()->m_master_password_enable = (password != NULL);
183	97	}
184	98
185	99
186	100	void ide_controller_device::ide_set_user_password(int _drive, const UINT8 *password)
187	101	{
188		slot[_drive]->dev()->user_password = password;
189		slot[_drive]->dev()->user_password_enable = (password != NULL);
	102	m_slot[_drive]->dev()->m_user_password = password;
	103	m_slot[_drive]->dev()->m_user_password_enable = (password != NULL);
190	104	}
191	105
192
193
194	106	/*************************************
195	107	*
196		*  Advance to the next sector
	108	*  IDE controller read
197	109	*
198	110	*************************************/
199	111
200		void ide_controller_device::next_sector()
	112	UINT16 ide_controller_device::read_dma()
201	113	{
202		/* LBA direct? */
203		ide_device_interface *dev = slot[cur_drive]->dev();
204		if (dev->cur_head_reg & 0x40)
205		{
206		dev->cur_sector++;
207		if (dev->cur_sector == 0)
208		{
209		dev->cur_cylinder++;
210		if (dev->cur_cylinder == 0)
211		dev->cur_head++;
212		}
213		}
	114	UINT16 result = 0xffff;
	115	for (int i = 0; i < 2; i++)
	116	if (m_slot[i]->dev() != NULL)
	117	result &= m_slot[i]->dev()->read_dma();
214	118
215		/* standard CHS */
216		else
217		{
218		/* sectors are 1-based */
219		dev->cur_sector++;
220		if (dev->cur_sector > dev->get_sectors())
221		{
222		/* heads are 0 based */
223		dev->cur_sector = 1;
224		dev->cur_head++;
225		if (dev->cur_head >= dev->get_heads())
226		{
227		dev->cur_head = 0;
228		dev->cur_cylinder++;
229		}
230		}
231		}
232
233		dev->cur_lba = dev->lba_address();
	119	//  printf( "read_dma %04x\n", result );
	120	return result;
234	121	}
235	122
236
237
238		/*************************************
239		*
240		*  security error handling
241		*
242		*************************************/
243
244		void ide_controller_device::security_error()
	123	READ16_MEMBER( ide_controller_device::read_cs0 )
245	124	{
246		ide_device_interface *dev = slot[cur_drive]->dev();
	125	UINT16 result = mem_mask;
	126	for (int i = 0; i < 2; i++)
	127	if (m_slot[i]->dev() != NULL)
	128	result &= m_slot[i]->dev()->read_cs0(space, offset, mem_mask);
247	129
248		/* set error state */
249		dev->status |= IDE_STATUS_ERROR;
250		dev->status &= ~IDE_STATUS_DRIVE_READY;
	130	//  printf( "read cs0 %04x %04x %04x\n", offset, result, mem_mask );
251	131
252		/* just set a timer and mark ourselves error */
253		timer_set(TIME_SECURITY_ERROR, TID_SECURITY_ERROR_DONE);
	132	return result;
254	133	}
255	134
256
257
258		/*************************************
259		*
260		*  Sector reading
261		*
262		*************************************/
263
264		void ide_controller_device::read_buffer_empty()
	135	READ16_MEMBER( ide_controller_device::read_cs1 )
265	136	{
266		ide_device_interface *dev = slot[cur_drive]->dev();
	137	UINT16 result = mem_mask;
	138	for (int i = 0; i < 2; i++)
	139	if (m_slot[i]->dev() != NULL)
	140	result &= m_slot[i]->dev()->read_cs1(space, offset, mem_mask);
267	141
268		/* reset the totals */
269		dev->buffer_offset = 0;
	142	//  printf( "read cs1 %04x %04x %04x\n", offset, result, mem_mask );
270	143
271		/* clear the buffer ready and busy flag */
272		dev->status &= ~IDE_STATUS_BUFFER_READY;
273		dev->status &= ~IDE_STATUS_BUSY;
274		dev->error = IDE_ERROR_DEFAULT;
275		set_dmarq(0);
276
277		if (dev->master_password_enable || dev->user_password_enable)
278		{
279		security_error();
280
281		dev->sector_count = 0;
282
283		return;
284		}
285
286		/* if there is more data to read, keep going */
287		if (dev->sector_count > 0)
288		dev->sector_count--;
289		if (dev->sector_count > 0)
290		read_next_sector();
	144	return result;
291	145	}
292	146
293
294		void ide_controller_device::read_sector_done()
295		{
296		ide_device_interface *dev = slot[cur_drive]->dev();
297		int lba = dev->lba_address(), count = 0;
298
299		/* GNET readlock check */
300		if (dev->gnetreadlock) {
301		dev->status &= ~IDE_STATUS_ERROR;
302		dev->status &= ~IDE_STATUS_BUSY;
303		return;
304		}
305
306		/* now do the read */
307		count = dev->read_sector(lba, dev->buffer);
308
309		/* by default, mark the buffer ready and the seek complete */
310		if (!dev->verify_only)
311		dev->status |= IDE_STATUS_BUFFER_READY;
312		dev->status |= IDE_STATUS_SEEK_COMPLETE;
313
314		/* and clear the busy and error flags */
315		dev->status &= ~IDE_STATUS_ERROR;
316		dev->status &= ~IDE_STATUS_BUSY;
317
318		/* if we succeeded, advance to the next sector and set the nice bits */
319		if (count == 1)
320		{
321		/* advance the pointers, unless this is the last sector */
322		/* Gauntlet: Dark Legacy checks to make sure we stop on the last sector */
323		if (dev->sector_count != 1)
324		next_sector();
325
326		/* clear the error value */
327		dev->error = IDE_ERROR_NONE;
328
329		/* signal an interrupt */
330		if (!dev->verify_only)
331		dev->sectors_until_int--;
332		if (dev->sectors_until_int == 0 || dev->sector_count == 1)
333		{
334		dev->sectors_until_int = ((dev->command == IDE_COMMAND_READ_MULTIPLE) ? dev->block_count : 1);
335		set_irq(ASSERT_LINE);
336		}
337
338		/* handle DMA */
339		if (dev->dma_active)
340		set_dmarq(1);
341
342		/* if we're just verifying we can read the next sector */
343		if (dev->verify_only)
344		read_buffer_empty();
345		}
346
347		/* if we got an error, we need to report it */
348		else
349		{
350		/* set the error flag and the error */
351		dev->status |= IDE_STATUS_ERROR;
352		dev->error = IDE_ERROR_BAD_SECTOR;
353
354		/* signal an interrupt */
355		set_irq(ASSERT_LINE);
356		}
357		}
358
359
360		void ide_controller_device::read_first_sector()
361		{
362		ide_device_interface *dev = slot[cur_drive]->dev();
363		/* mark ourselves busy */
364		dev->status |= IDE_STATUS_BUSY;
365
366		/* just set a timer */
367		if (dev->command == IDE_COMMAND_READ_MULTIPLE)
368		{
369		int new_lba = dev->lba_address();
370		attotime seek_time;
371
372		if (new_lba == dev->cur_lba || new_lba == dev->cur_lba + 1)
373		seek_time = TIME_NO_SEEK_MULTISECTOR;
374		else
375		seek_time = TIME_SEEK_MULTISECTOR;
376
377		dev->cur_lba = new_lba;
378		timer_set(seek_time, TID_READ_SECTOR_DONE_CALLBACK);
379		}
380		else
381		timer_set(TIME_PER_SECTOR, TID_READ_SECTOR_DONE_CALLBACK);
382		}
383
384
385		void ide_controller_device::read_next_sector()
386		{
387		ide_device_interface *dev = slot[cur_drive]->dev();
388
389		/* mark ourselves busy */
390		dev->status |= IDE_STATUS_BUSY;
391
392		if (dev->command == IDE_COMMAND_READ_MULTIPLE)
393		{
394		if (dev->sectors_until_int != 1)
395		/* make ready now */
396		read_sector_done();
397		else
398		/* just set a timer */
399		timer_set(attotime::from_usec(1), TID_READ_SECTOR_DONE_CALLBACK);
400		}
401		else
402		/* just set a timer */
403		timer_set(TIME_PER_SECTOR, TID_READ_SECTOR_DONE_CALLBACK);
404		}
405
406
407
408		/*************************************
409		*
410		*  Sector writing
411		*
412		*************************************/
413
414		void ide_controller_device::continue_write()
415		{
416		ide_device_interface *dev = slot[cur_drive]->dev();
417
418		/* reset the totals */
419		dev->buffer_offset = 0;
420
421		/* clear the buffer ready flag */
422		dev->status &= ~IDE_STATUS_BUFFER_READY;
423		dev->status |= IDE_STATUS_BUSY;
424
425		if (dev->command == IDE_COMMAND_WRITE_MULTIPLE)
426		{
427		if (dev->sectors_until_int != 1)
428		{
429		/* ready to write now */
430		write_sector_done();
431		}
432		else
433		{
434		/* set a timer to do the write */
435		timer_set(TIME_PER_SECTOR, TID_WRITE_SECTOR_DONE_CALLBACK);
436		}
437		}
438		else
439		{
440		/* set a timer to do the write */
441		timer_set(TIME_PER_SECTOR, TID_WRITE_SECTOR_DONE_CALLBACK);
442		}
443		}
444
445
446		void ide_controller_device::write_buffer_full()
447		{
448		ide_device_interface *dev = slot[cur_drive]->dev();
449
450		set_dmarq(0);
451		if (dev->command == IDE_COMMAND_SECURITY_UNLOCK)
452		{
453		if (dev->user_password_enable && memcmp(dev->buffer, dev->user_password, 2 + 32) == 0)
454		{
455		LOGPRINT(("IDE Unlocked user password\n"));
456		dev->user_password_enable = 0;
457		}
458		if (dev->master_password_enable && memcmp(dev->buffer, dev->master_password, 2 + 32) == 0)
459		{
460		LOGPRINT(("IDE Unlocked master password\n"));
461		dev->master_password_enable = 0;
462		}
463		if (PRINTF_IDE_PASSWORD)
464		{
465		int i;
466
467		for (i = 0; i < 34; i += 2)
468		{
469		if (i % 8 == 2)
470		mame_printf_debug("\n");
471
472		mame_printf_debug("0x%02x, 0x%02x, ", dev->buffer[i], dev->buffer[i + 1]);
473		//mame_printf_debug("0x%02x%02x, ", dev->buffer[i], dev->buffer[i + 1]);
474		}
475		mame_printf_debug("\n");
476		}
477
478		/* clear the busy and error flags */
479		dev->status &= ~IDE_STATUS_ERROR;
480		dev->status &= ~IDE_STATUS_BUSY;
481		dev->status &= ~IDE_STATUS_BUFFER_READY;
482
483		if (dev->master_password_enable || dev->user_password_enable)
484		security_error();
485		else
486		dev->status |= IDE_STATUS_DRIVE_READY;
487		}
488		else if (dev->command == IDE_COMMAND_TAITO_GNET_UNLOCK_2)
489		{
490		UINT8 key[5] = { 0 };
491		int i, bad = 0;
492		dev->read_key(key);
493
494		for (i=0; !bad && i<512; i++)
495		bad = ((i < 2 || i >= 7) && dev->buffer[i]) || ((i >= 2 && i < 7) && dev->buffer[i] != key[i-2]);
496
497		dev->status &= ~IDE_STATUS_BUSY;
498		dev->status &= ~IDE_STATUS_BUFFER_READY;
499		if (bad)
500		dev->status |= IDE_STATUS_ERROR;
501		else {
502		dev->status &= ~IDE_STATUS_ERROR;
503		dev->gnetreadlock= 0;
504		}
505		}
506		else
507		{
508		continue_write();
509		}
510		}
511
512
513		void ide_controller_device::write_sector_done()
514		{
515		ide_device_interface *dev = slot[cur_drive]->dev();
516		int lba = dev->lba_address(), count = 0;
517
518		/* now do the write */
519		count = dev->write_sector(lba, dev->buffer);
520
521		/* by default, mark the buffer ready and the seek complete */
522		dev->status |= IDE_STATUS_BUFFER_READY;
523		dev->status |= IDE_STATUS_SEEK_COMPLETE;
524
525		/* and clear the busy adn error flags */
526		dev->status &= ~IDE_STATUS_ERROR;
527		dev->status &= ~IDE_STATUS_BUSY;
528
529		/* if we succeeded, advance to the next sector and set the nice bits */
530		if (count == 1)
531		{
532		/* advance the pointers, unless this is the last sector */
533		/* Gauntlet: Dark Legacy checks to make sure we stop on the last sector */
534		if (dev->sector_count != 1)
535		next_sector();
536
537		/* clear the error value */
538		dev->error = IDE_ERROR_NONE;
539
540		/* signal an interrupt */
541		if (--dev->sectors_until_int == 0 || dev->sector_count == 1)
542		{
543		dev->sectors_until_int = ((dev->command == IDE_COMMAND_WRITE_MULTIPLE) ? dev->block_count : 1);
544		set_irq(ASSERT_LINE);
545		}
546
547		/* signal an interrupt if there's more data needed */
548		if (dev->sector_count > 0)
549		dev->sector_count--;
550		if (dev->sector_count == 0)
551		dev->status &= ~IDE_STATUS_BUFFER_READY;
552
553		/* keep going for DMA */
554		if (dev->dma_active && dev->sector_count != 0)
555		{
556		set_dmarq(1);
557		}
558		}
559
560		/* if we got an error, we need to report it */
561		else
562		{
563		/* set the error flag and the error */
564		dev->status |= IDE_STATUS_ERROR;
565		dev->error = IDE_ERROR_BAD_SECTOR;
566
567		/* signal an interrupt */
568		set_irq(ASSERT_LINE);
569		}
570		}
571
572
573
574		/*************************************
575		*
576		*  Handle IDE commands
577		*
578		*************************************/
579
580		void ide_controller_device::handle_command(UINT8 _command)
581		{
582		UINT8 key[5];
583		ide_device_interface *dev = slot[cur_drive]->dev();
584
585		/* implicitly clear interrupts & dmarq here */
586		set_irq(CLEAR_LINE);
587		set_dmarq(0);
588		dev->command = _command;
589		switch (dev->command)
590		{
591		case IDE_COMMAND_READ_SECTORS:
592		case IDE_COMMAND_READ_SECTORS_NORETRY:
593		LOGPRINT(("IDE Read multiple: C=%d H=%d S=%d LBA=%d count=%d\n",
594		dev->cur_cylinder, dev->cur_head, dev->cur_sector, dev->lba_address(), dev->sector_count));
595
596		/* reset the buffer */
597		dev->buffer_offset = 0;
598		dev->sectors_until_int = 1;
599		dev->dma_active = 0;
600		dev->verify_only = 0;
601
602		/* start the read going */
603		read_first_sector();
604		break;
605
606		case IDE_COMMAND_READ_MULTIPLE:
607		LOGPRINT(("IDE Read multiple block: C=%d H=%d S=%d LBA=%d count=%d\n",
608		dev->cur_cylinder, dev->cur_head, dev->cur_sector, dev->lba_address(), dev->sector_count));
609
610		/* reset the buffer */
611		dev->buffer_offset = 0;
612		dev->sectors_until_int = 1;
613		dev->dma_active = 0;
614		dev->verify_only = 0;
615
616		/* start the read going */
617		read_first_sector();
618		break;
619
620		case IDE_COMMAND_VERIFY_SECTORS:
621		case IDE_COMMAND_VERIFY_SECTORS_NORETRY:
622		LOGPRINT(("IDE Read verify multiple with/without retries: C=%d H=%d S=%d LBA=%d count=%d\n",
623		dev->cur_cylinder, dev->cur_head, dev->cur_sector, dev->lba_address(), dev->sector_count));
624
625		/* reset the buffer */
626		dev->buffer_offset = 0;
627		dev->sectors_until_int = 1;
628		dev->dma_active = 0;
629		dev->verify_only = 1;
630
631		/* start the read going */
632		read_first_sector();
633		break;
634
635		case IDE_COMMAND_READ_DMA:
636		LOGPRINT(("IDE Read multiple DMA: C=%d H=%d S=%d LBA=%d count=%d\n",
637		dev->cur_cylinder, dev->cur_head, dev->cur_sector, dev->lba_address(), dev->sector_count));
638
639		/* reset the buffer */
640		dev->buffer_offset = 0;
641		dev->sectors_until_int = dev->sector_count;
642		dev->dma_active = 1;
643		dev->verify_only = 0;
644
645		/* start the read going */
646		read_first_sector();
647		break;
648
649		case IDE_COMMAND_WRITE_SECTORS:
650		case IDE_COMMAND_WRITE_SECTORS_NORETRY:
651		LOGPRINT(("IDE Write multiple: C=%d H=%d S=%d LBA=%d count=%d\n",
652		dev->cur_cylinder, dev->cur_head, dev->cur_sector, dev->lba_address(), dev->sector_count));
653
654		/* reset the buffer */
655		dev->buffer_offset = 0;
656		dev->sectors_until_int = 1;
657		dev->dma_active = 0;
658
659		/* mark the buffer ready */
660		dev->status |= IDE_STATUS_BUFFER_READY;
661		break;
662
663		case IDE_COMMAND_WRITE_MULTIPLE:
664		LOGPRINT(("IDE Write multiple block: C=%d H=%d S=%d LBA=%d count=%d\n",
665		dev->cur_cylinder, dev->cur_head, dev->cur_sector, dev->lba_address(), dev->sector_count));
666
667		/* reset the buffer */
668		dev->buffer_offset = 0;
669		dev->sectors_until_int = 1;
670		dev->dma_active = 0;
671
672		/* mark the buffer ready */
673		dev->status |= IDE_STATUS_BUFFER_READY;
674		break;
675
676		case IDE_COMMAND_WRITE_DMA:
677		LOGPRINT(("IDE Write multiple DMA: C=%d H=%d S=%d LBA=%d count=%d\n",
678		dev->cur_cylinder, dev->cur_head, dev->cur_sector, dev->lba_address(), dev->sector_count));
679
680		/* reset the buffer */
681		dev->buffer_offset = 0;
682		dev->sectors_until_int = dev->sector_count;
683		dev->dma_active = 1;
684
685		/* start the read going */
686		set_dmarq(1);
687		break;
688
689		case IDE_COMMAND_SECURITY_UNLOCK:
690		LOGPRINT(("IDE Security Unlock\n"));
691
692		/* reset the buffer */
693		dev->buffer_offset = 0;
694		dev->sectors_until_int = 0;
695		dev->dma_active = 0;
696
697		/* mark the buffer ready */
698		dev->status |= IDE_STATUS_BUFFER_READY;
699		set_irq(ASSERT_LINE);
700		break;
701
702		case IDE_COMMAND_GET_INFO:
703		LOGPRINT(("IDE Read features\n"));
704
705		/* reset the buffer */
706		dev->buffer_offset = 0;
707		dev->sector_count = 1;
708
709		/* build the features page */
710		memcpy(dev->buffer, slot[cur_drive]->dev()->get_features(), sizeof(dev->buffer));
711
712		/* indicate everything is ready */
713		dev->status |= IDE_STATUS_BUFFER_READY;
714		dev->status |= IDE_STATUS_SEEK_COMPLETE;
715		dev->status |= IDE_STATUS_DRIVE_READY;
716
717		/* and clear the busy adn error flags */
718		dev->status &= ~IDE_STATUS_ERROR;
719		dev->status &= ~IDE_STATUS_BUSY;
720
721		/* clear the error too */
722		dev->error = IDE_ERROR_NONE;
723
724		/* signal an interrupt */
725		signal_delayed_interrupt(MINIMUM_COMMAND_TIME, 1);
726		break;
727
728		case IDE_COMMAND_DIAGNOSTIC:
729		dev->error = IDE_ERROR_DEFAULT;
730
731		/* signal an interrupt */
732		signal_delayed_interrupt(MINIMUM_COMMAND_TIME, 0);
733		break;
734
735		case IDE_COMMAND_RECALIBRATE:
736		/* clear the error too */
737		dev->error = IDE_ERROR_NONE;
738		/* signal an interrupt */
739		signal_delayed_interrupt(MINIMUM_COMMAND_TIME, 0);
740		break;
741
742		case IDE_COMMAND_IDLE:
743		/* clear the error too */
744		dev->error = IDE_ERROR_NONE;
745
746		/* for timeout disabled value is 0 */
747		dev->sector_count = 0;
748		/* signal an interrupt */
749		set_irq(ASSERT_LINE);
750		break;
751
752		case IDE_COMMAND_SET_CONFIG:
753		LOGPRINT(("IDE Set configuration (%d heads, %d sectors)\n", dev->cur_head + 1, dev->sector_count));
754		dev->status &= ~IDE_STATUS_ERROR;
755		dev->error = IDE_ERROR_NONE;
756		dev->set_geometry(dev->sector_count,dev->cur_head + 1);
757
758		/* signal an interrupt */
759		signal_delayed_interrupt(MINIMUM_COMMAND_TIME, 0);
760		break;
761
762		case IDE_COMMAND_UNKNOWN_F9:
763		/* only used by Killer Instinct AFAICT */
764		LOGPRINT(("IDE unknown command (F9)\n"));
765
766		/* signal an interrupt */
767		set_irq(ASSERT_LINE);
768		break;
769
770		case IDE_COMMAND_SET_FEATURES:
771		LOGPRINT(("IDE Set features (%02X %02X %02X %02X %02X)\n", dev->precomp_offset, dev->sector_count & 0xff, dev->cur_sector, dev->cur_cylinder & 0xff, dev->cur_cylinder >> 8));
772
773		/* signal an interrupt */
774		signal_delayed_interrupt(MINIMUM_COMMAND_TIME, 0);
775		break;
776
777		case IDE_COMMAND_SET_BLOCK_COUNT:
778		LOGPRINT(("IDE Set block count (%02X)\n", dev->sector_count));
779
780		dev->block_count = dev->sector_count;
781		// judge dredd wants 'drive ready' on this command
782		dev->status |= IDE_STATUS_DRIVE_READY;
783
784		/* signal an interrupt */
785		set_irq(ASSERT_LINE);
786		break;
787
788		case IDE_COMMAND_TAITO_GNET_UNLOCK_1:
789		LOGPRINT(("IDE GNET Unlock 1\n"));
790
791		dev->sector_count = 1;
792		dev->status |= IDE_STATUS_DRIVE_READY;
793		dev->status &= ~IDE_STATUS_ERROR;
794		set_irq(ASSERT_LINE);
795		break;
796
797		case IDE_COMMAND_TAITO_GNET_UNLOCK_2:
798		LOGPRINT(("IDE GNET Unlock 2\n"));
799
800		/* reset the buffer */
801		dev->buffer_offset = 0;
802		dev->sectors_until_int = 0;
803		dev->dma_active = 0;
804
805		/* mark the buffer ready */
806		dev->status |= IDE_STATUS_BUFFER_READY;
807		set_irq(ASSERT_LINE);
808		break;
809
810		case IDE_COMMAND_TAITO_GNET_UNLOCK_3:
811		LOGPRINT(("IDE GNET Unlock 3\n"));
812
813		/* key check */
814		dev->read_key(key);
815		if ((dev->precomp_offset == key[0]) && (dev->sector_count == key[1]) && (dev->cur_sector == key[2]) && (dev->cur_cylinder == (((UINT16)key[4]<<8)|key[3])))
816		{
817		dev->gnetreadlock= 0;
818		}
819
820		/* update flags */
821		dev->status |= IDE_STATUS_DRIVE_READY;
822		dev->status &= ~IDE_STATUS_ERROR;
823		set_irq(ASSERT_LINE);
824		break;
825
826		case IDE_COMMAND_SEEK:
827		/*
828		cur_cylinder, cur_sector and cur_head
829		are all already set in this case so no need
830		so that implements actual seek
831		*/
832		/* clear the error too */
833		dev->error = IDE_ERROR_NONE;
834
835		/* for timeout disabled value is 0 */
836		dev->sector_count = 0;
837		/* signal an interrupt */
838		set_irq(ASSERT_LINE);
839		break;
840
841
842		default:
843		LOGPRINT(("IDE unknown command (%02X)\n", dev->command));
844		dev->status |= IDE_STATUS_ERROR;
845		dev->error = IDE_ERROR_UNKNOWN_COMMAND;
846		set_irq(ASSERT_LINE);
847		//debugger_break(device->machine());
848		break;
849		}
850		}
851
852
853
854		/*************************************
855		*
856		*  IDE controller read
857		*
858		*************************************/
859
860	147	READ8_MEMBER( ide_controller_device::read_via_config )
861	148	{
862	149	UINT16 result = 0;
r23677	r23678
868	155	{
869	156	/* unknown config register */
870	157	case IDE_BANK2_CONFIG_UNK:
871		result = config_unknown;
	158	result = m_config_unknown;
872	159	break;
873	160
874	161	/* active config register */
875	162	case IDE_BANK2_CONFIG_REGISTER:
876		result = config_register_num;
	163	result = m_config_register_num;
877	164	break;
878	165
879	166	/* data from active config register */
880	167	case IDE_BANK2_CONFIG_DATA:
881		if (config_register_num < IDE_CONFIG_REGISTERS)
882		result = config_register[config_register_num];
	168	if (m_config_register_num < IDE_CONFIG_REGISTERS)
	169	result = m_config_register[m_config_register_num];
883	170	break;
884	171
885	172	default:
r23677	r23678
904	191	}
905	192	}
906	193
907		UINT16 ide_controller_device::read_dma()
908		{
909		ide_device_interface *dev = slot[cur_drive]->dev();
910
911		if (dev == NULL)
912		{
913		if (slot[cur_drive^1]->dev() == NULL)
914		return 0xff;
915		return 0;
916		}
917
918		UINT16 result = dev->buffer[dev->buffer_offset++];
919		result |= dev->buffer[dev->buffer_offset++] << 8;
920
921		if (dev->buffer_offset >= IDE_DISK_SECTOR_SIZE)
922		{
923		LOG(("%s:IDE completed DMA read\n", machine().describe_context()));
924		read_buffer_empty();
925		}
926
927		return result;
928		}
929
930		READ16_MEMBER( ide_controller_device::read_cs0 )
931		{
932		UINT16 result = 0;
933		ide_device_interface *dev = slot[cur_drive]->dev();
934
935		/* logit */
936		//  if (offset != IDE_BANK0_DATA && offset != IDE_BANK0_STATUS_COMMAND)
937		LOG(("%s:IDE cs0 read at %X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask));
938
939		if (dev == NULL)
940		{
941		if (slot[cur_drive^1]->dev() == NULL)
942		return 0xff;
943		return 0;
944		}
945
946		if (dev->is_ready()) {
947		dev->status |= IDE_STATUS_DRIVE_READY;
948		} else {
949		dev->status &= ~IDE_STATUS_DRIVE_READY;
950		}
951
952		switch (offset)
953		{
954		/* read data if there's data to be read */
955		case IDE_BANK0_DATA:
956		if (dev->status & IDE_STATUS_BUFFER_READY)
957		{
958		/* fetch the correct amount of data */
959		result = dev->buffer[dev->buffer_offset++];
960		if (mem_mask == 0xffff)
961		result |= dev->buffer[dev->buffer_offset++] << 8;
962
963		/* if we're at the end of the buffer, handle it */
964		if (dev->buffer_offset >= IDE_DISK_SECTOR_SIZE)
965		{
966		LOG(("%s:IDE completed PIO read\n", machine().describe_context()));
967		read_buffer_empty();
968		}
969		}
970		break;
971
972		/* return the current error */
973		case IDE_BANK0_ERROR:
974		result = dev->error;
975		break;
976
977		/* return the current sector count */
978		case IDE_BANK0_SECTOR_COUNT:
979		result = dev->sector_count;
980		break;
981
982		/* return the current sector */
983		case IDE_BANK0_SECTOR_NUMBER:
984		result = dev->cur_sector;
985		break;
986
987		/* return the current cylinder LSB */
988		case IDE_BANK0_CYLINDER_LSB:
989		result = dev->cur_cylinder & 0xff;
990		break;
991
992		/* return the current cylinder MSB */
993		case IDE_BANK0_CYLINDER_MSB:
994		result = dev->cur_cylinder >> 8;
995		break;
996
997		/* return the current head */
998		case IDE_BANK0_HEAD_NUMBER:
999		result = dev->cur_head_reg;
1000		break;
1001
1002		/* return the current status and clear any pending interrupts */
1003		case IDE_BANK0_STATUS_COMMAND:
1004		result = dev->status;
1005		if (dev->last_status_timer->elapsed() > TIME_PER_ROTATION)
1006		{
1007		result |= IDE_STATUS_HIT_INDEX;
1008		dev->last_status_timer->adjust(attotime::never);
1009		}
1010		if (dev->interrupt_pending == ASSERT_LINE)
1011		set_irq(CLEAR_LINE);
1012		break;
1013
1014		/* log anything else */
1015		default:
1016		logerror("%s:unknown IDE cs0 read at %03X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask);
1017		break;
1018		}
1019
1020		//  printf( "read cs0 %04x %04x %04x\n", offset, result, mem_mask );
1021
1022		/* return the result */
1023		return result;
1024		}
1025
1026
1027	194	READ16_MEMBER( ide_controller_device::read_cs1_pc )
1028	195	{
1029	196	if (mem_mask == 0xff00)
r23677	r23678
1036	203	}
1037	204	}
1038	205
1039		READ16_MEMBER( ide_controller_device::read_cs1 )
1040		{
1041		UINT16 result = 0;
1042		ide_device_interface *dev = slot[cur_drive]->dev();
1043	206
1044		if (dev == NULL)
1045		{
1046		if (slot[cur_drive^1]->dev() == NULL)
1047		return 0xff;
1048		return 0;
1049		}
	207	/*************************************
	208	*
	209	*  IDE controller write
	210	*
	211	*************************************/
1050	212
1051		if (dev->is_ready()) {
1052		dev->status |= IDE_STATUS_DRIVE_READY;
1053		} else {
1054		dev->status &= ~IDE_STATUS_DRIVE_READY;
1055		}
	213	void ide_controller_device::write_dma( UINT16 data )
	214	{
	215	//  printf( "write_dma %04x\n", data );
1056	216
1057		/* logit */
1058		//  if (offset != IDE_BANK1_STATUS_CONTROL)
1059		LOG(("%s:IDE cs1 read at %X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask));
1060		/* return the current status but don't clear interrupts */
	217	for (int i = 0; i < 2; i++)
	218	if (m_slot[i]->dev() != NULL)
	219	m_slot[i]->dev()->write_dma(data);
	220	}
1061	221
1062		switch (offset)
1063		{
1064		case IDE_BANK1_STATUS_CONTROL:
1065		result = dev->status;
1066		if (dev->last_status_timer->elapsed() > TIME_PER_ROTATION)
1067		{
1068		result |= IDE_STATUS_HIT_INDEX;
1069		dev->last_status_timer->adjust(attotime::never);
1070		}
1071		break;
	222	WRITE16_MEMBER( ide_controller_device::write_cs0 )
	223	{
	224	//  printf( "write cs0 %04x %04x %04x\n", offset, data, mem_mask );
1072	225
1073		/* log anything else */
1074		default:
1075		logerror("%s:unknown IDE cs1 read at %03X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask);
1076		break;
1077		}
	226	for (int i = 0; i < 2; i++)
	227	if (m_slot[i]->dev() != NULL)
	228	m_slot[i]->dev()->write_cs0(space, offset, data, mem_mask);
	229	}
1078	230
1079		//  printf( "read cs1 %04x %04x %04x\n", offset, result, mem_mask );
	231	WRITE16_MEMBER( ide_controller_device::write_cs1 )
	232	{
	233	//  printf( "write cs1 %04x %04x %04x\n", offset, data, mem_mask );
1080	234
1081		/* return the result */
1082		return result;
	235	for (int i = 0; i < 2; i++)
	236	if (m_slot[i]->dev() != NULL)
	237	m_slot[i]->dev()->write_cs1(space, offset, data, mem_mask);
1083	238	}
1084	239
1085
1086		/*************************************
1087		*
1088		*  IDE controller write
1089		*
1090		*************************************/
1091
1092	240	WRITE8_MEMBER( ide_controller_device::write_via_config )
1093	241	{
1094	242	//  printf( "write via config %04x %04x %04x\n", offset, data, mem_mask );
r23677	r23678
1100	248	{
1101	249	/* unknown config register */
1102	250	case IDE_BANK2_CONFIG_UNK:
1103		config_unknown = data;
	251	m_config_unknown = data;
1104	252	break;
1105	253
1106	254	/* active config register */
1107	255	case IDE_BANK2_CONFIG_REGISTER:
1108		config_register_num = data;
	256	m_config_register_num = data;
1109	257	break;
1110	258
1111	259	/* data from active config register */
1112	260	case IDE_BANK2_CONFIG_DATA:
1113		if (config_register_num < IDE_CONFIG_REGISTERS)
1114		config_register[config_register_num] = data;
	261	if (m_config_register_num < IDE_CONFIG_REGISTERS)
	262	m_config_register[m_config_register_num] = data;
1115	263	break;
1116	264	}
1117	265	}
r23677	r23678
1129	277	}
1130	278	}
1131	279
1132		void ide_controller_device::write_dma( UINT16 data )
1133		{
1134		ide_device_interface *dev = slot[cur_drive]->dev();
1135
1136		if (dev == NULL)
1137		return;
1138
1139		dev->buffer[dev->buffer_offset++] = data;
1140		dev->buffer[dev->buffer_offset++] = data >> 8;
1141
1142		/* if we're at the end of the buffer, handle it */
1143		if (dev->buffer_offset >= IDE_DISK_SECTOR_SIZE)
1144		{
1145		LOG(("%s:IDE completed DMA write\n", machine().describe_context()));
1146		write_buffer_full();
1147		}
1148		}
1149
1150		WRITE16_MEMBER( ide_controller_device::write_cs0 )
1151		{
1152		//  printf( "write cs0 %04x %04x %04x\n", offset, data, mem_mask );
1153
1154		switch (offset)
1155		{
1156		case IDE_BANK0_HEAD_NUMBER:
1157		cur_drive = (data & 0x10) >> 4;
1158		break;
1159		}
1160
1161		ide_device_interface *dev = slot[cur_drive]->dev();
1162
1163		if (dev == NULL)
1164		return;
1165
1166		/* logit */
1167		if (offset != IDE_BANK0_DATA)
1168		LOG(("%s:IDE cs0 write to %X = %08X, mem_mask=%d\n", machine().describe_context(), offset, data, mem_mask));
1169		//  fprintf(stderr, "ide write %03x %02x mem_mask=%d\n", offset, data, size);
1170		switch (offset)
1171		{
1172		/* write data */
1173		case IDE_BANK0_DATA:
1174		if (dev->status & IDE_STATUS_BUFFER_READY)
1175		{
1176		/* store the correct amount of data */
1177		dev->buffer[dev->buffer_offset++] = data;
1178		if (mem_mask == 0xffff)
1179		dev->buffer[dev->buffer_offset++] = data >> 8;
1180
1181		/* if we're at the end of the buffer, handle it */
1182		if (dev->buffer_offset >= IDE_DISK_SECTOR_SIZE)
1183		{
1184		LOG(("%s:IDE completed PIO write\n", machine().describe_context()));
1185		write_buffer_full();
1186		}
1187		}
1188		break;
1189
1190		/* precompensation offset?? */
1191		case IDE_BANK0_ERROR:
1192		dev->precomp_offset = data;
1193		break;
1194
1195		/* sector count */
1196		case IDE_BANK0_SECTOR_COUNT:
1197		dev->sector_count = data ? data : 256;
1198		break;
1199
1200		/* current sector */
1201		case IDE_BANK0_SECTOR_NUMBER:
1202		dev->cur_sector = data;
1203		break;
1204
1205		/* current cylinder LSB */
1206		case IDE_BANK0_CYLINDER_LSB:
1207		dev->cur_cylinder = (dev->cur_cylinder & 0xff00) | (data & 0xff);
1208		break;
1209
1210		/* current cylinder MSB */
1211		case IDE_BANK0_CYLINDER_MSB:
1212		dev->cur_cylinder = (dev->cur_cylinder & 0x00ff) | ((data & 0xff) << 8);
1213		break;
1214
1215		/* current head */
1216		case IDE_BANK0_HEAD_NUMBER:
1217		dev->cur_head = data & 0x0f;
1218		dev->cur_head_reg = data;
1219		// LBA mode = data & 0x40
1220		break;
1221
1222		/* command */
1223		case IDE_BANK0_STATUS_COMMAND:
1224		handle_command(data);
1225		break;
1226		}
1227		}
1228
1229	280	WRITE16_MEMBER( ide_controller_device::write_cs1_pc )
1230	281	{
1231	282	if (mem_mask == 0xff00)
r23677	r23678
1238	289	}
1239	290	}
1240	291
1241		WRITE16_MEMBER( ide_controller_device::write_cs1 )
1242		{
1243		ide_device_interface *dev = slot[cur_drive]->dev();
1244
1245		if (dev == NULL)
1246		return;
1247
1248		//  printf( "write cs1 %04x %04x %04x\n", offset, data, mem_mask );
1249
1250		/* logit */
1251		LOG(("%s:IDE cs1 write to %X = %08X, mem_mask=%d\n", machine().describe_context(), offset, data, mem_mask));
1252
1253		switch (offset)
1254		{
1255		/* adapter control */
1256		case IDE_BANK1_STATUS_CONTROL:
1257		dev->adapter_control = data;
1258
1259		/* handle controller reset */
1260		//if (data == 0x04)
1261		if (data & 0x04)
1262		{
1263		dev->status |= IDE_STATUS_BUSY;
1264		dev->status &= ~IDE_STATUS_DRIVE_READY;
1265		dev->reset_timer->adjust(attotime::from_msec(5));
1266		}
1267		break;
1268		}
1269		}
1270
1271
1272	292	SLOT_INTERFACE_START(ide_devices)
1273	293	SLOT_INTERFACE("hdd", IDE_HARDDISK)
1274	294	SLOT_INTERFACE_END
1275	295
1276	296	ide_controller_device::ide_controller_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) :
1277	297	device_t(mconfig, type, name, tag, owner, clock),
1278		config_unknown(0),
1279		config_register_num(0),
1280		cur_drive(0),
1281		m_irq_handler(*this)
	298	m_config_unknown(0),
	299	m_config_register_num(0),
	300	m_irq_handler(*this),
	301	m_dmarq_handler(*this)
1282	302	{
1283	303	}
1284	304
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1287	307
1288	308	ide_controller_device::ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
1289	309	device_t(mconfig, IDE_CONTROLLER, "IDE Controller", tag, owner, clock),
1290		config_unknown(0),
1291		config_register_num(0),
1292		cur_drive(0),
1293		m_irq_handler(*this)
	310	m_config_unknown(0),
	311	m_config_register_num(0),
	312	m_irq_handler(*this),
	313	m_dmarq_handler(*this)
1294	314	{
1295	315	}
1296	316
r23677	r23678
1301	321	void ide_controller_device::device_start()
1302	322	{
1303	323	m_irq_handler.resolve_safe();
	324	m_dmarq_handler.resolve_safe();
1304	325
1305	326	/* set MAME harddisk handle */
1306		slot[0] = subdevice<ide_slot_device>("0");
1307		slot[1] = subdevice<ide_slot_device>("1");
	327	m_slot[0] = subdevice<ide_slot_device>("0");
	328	m_slot[1] = subdevice<ide_slot_device>("1");
1308	329
	330	for (int i = 0; i < 2; i++)
	331	{
	332	m_irq[i] = 0;
	333	m_dmarq[i] = 0;
	334
	335	ide_device_interface *dev = m_slot[i]->dev();
	336	if (dev != NULL)
	337	{
	338	if (i == 0)
	339	{
	340	dev->m_irq_handler.set_callback(DEVCB2_DEVWRITELINE("^", ide_controller_device, irq0_write_line));
	341	dev->m_dmarq_handler.set_callback(DEVCB2_DEVWRITELINE("^", ide_controller_device, dmarq0_write_line));
	342	}
	343	else
	344	{
	345	dev->m_irq_handler.set_callback(DEVCB2_DEVWRITELINE("^", ide_controller_device, irq1_write_line));
	346	dev->m_dmarq_handler.set_callback(DEVCB2_DEVWRITELINE("^", ide_controller_device, dmarq1_write_line));
	347	}
	348
	349	dev->m_csel = i;
	350	dev->m_dasp = m_slot[1]->dev() != NULL;
	351	}
	352	}
	353
1309	354	/* register ide states */
1310		save_item(NAME(config_unknown));
1311		save_item(NAME(config_register));
1312		save_item(NAME(config_register_num));
	355	save_item(NAME(m_config_unknown));
	356	save_item(NAME(m_config_register));
	357	save_item(NAME(m_config_register_num));
1313	358	}
1314	359
1315	360	//-------------------------------------------------
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1319	364	void ide_controller_device::device_reset()
1320	365	{
1321	366	LOG(("IDE controller reset performed\n"));
1322		/* reset the drive state */
1323		cur_drive = 0;
1324		set_irq(CLEAR_LINE);
1325		set_dmarq(0);
1326	367	}
1327	368
1328	369
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1425	466
1426	467	void bus_master_ide_controller_device::set_dmarq(int state)
1427	468	{
	469	ide_controller_device::set_dmarq(state);
	470
1428	471	if (m_dmarq != state)
1429	472	{
1430	473	m_dmarq = state;

trunk/src/emu/machine/idectrl.h

r23677	r23678
49	49	#define MCFG_IDE_CONTROLLER_IRQ_HANDLER(_devcb) \
50	50	devcb = &ide_controller_device::set_irq_handler(*device, DEVCB2_##_devcb);
51	51
	52	#define MCFG_IDE_CONTROLLER_DMARQ_HANDLER(_devcb) \
	53	devcb = &ide_controller_device::set_dmarq_handler(*device, DEVCB2_##_devcb);
	54
52	55	SLOT_INTERFACE_EXTERN(ide_devices);
53	56	SLOT_INTERFACE_EXTERN(ide_devices);
54	57
r23677	r23678
82	85
83	86	// static configuration helpers
84	87	template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<ide_controller_device &>(device).m_irq_handler.set_callback(object); }
	88	template<class _Object> static devcb2_base &set_dmarq_handler(device_t &device, _Object object) { return downcast<ide_controller_device &>(device).m_dmarq_handler.set_callback(object); }
85	89
86	90	UINT8 *ide_get_features(int drive);
87	91	void ide_set_gnet_readlock(int drive, const UINT8 onoff);
88	92	void ide_set_master_password(int drive, const UINT8 *password);
89	93	void ide_set_user_password(int drive, const UINT8 *password);
90	94
91		DECLARE_READ8_MEMBER(read_via_config);
92		DECLARE_WRITE8_MEMBER(write_via_config);
93	95	UINT16 read_dma();
94	96	DECLARE_READ16_MEMBER(read_cs0);
95	97	DECLARE_READ16_MEMBER(read_cs1);
r23677	r23678
97	99	DECLARE_WRITE16_MEMBER(write_cs0);
98	100	DECLARE_WRITE16_MEMBER(write_cs1);
99	101
	102	DECLARE_READ8_MEMBER(read_via_config);
	103	DECLARE_WRITE8_MEMBER(write_via_config);
100	104	DECLARE_READ16_MEMBER(read_cs0_pc);
101	105	DECLARE_READ16_MEMBER(read_cs1_pc);
102	106	DECLARE_WRITE16_MEMBER(write_cs0_pc);
103	107	DECLARE_WRITE16_MEMBER(write_cs1_pc);
104	108
105		virtual void set_irq(int state);
106		virtual void set_dmarq(int state);
107		void read_sector_done();
108		void write_sector_done();
109
110	109	protected:
111	110	// device-level overrides
112	111	virtual void device_start();
113	112	virtual void device_reset();
114		virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
115	113
116		void read_next_sector();
117		void continue_write();
	114	virtual void set_irq(int state);
	115	virtual void set_dmarq(int state);
118	116
119	117	private:
120		void signal_delayed_interrupt(attotime time, int buffer_ready);
121		void next_sector();
122		void security_error();
123		void continue_read();
124		void read_first_sector();
125		void handle_command(UINT8 _command);
126		void read_buffer_empty();
127		void write_buffer_full();
	118	DECLARE_WRITE_LINE_MEMBER(irq0_write_line);
	119	DECLARE_WRITE_LINE_MEMBER(dmarq0_write_line);
128	120
129		UINT8           config_unknown;
130		UINT8           config_register[IDE_CONFIG_REGISTERS];
131		UINT8           config_register_num;
	121	DECLARE_WRITE_LINE_MEMBER(irq1_write_line);
	122	DECLARE_WRITE_LINE_MEMBER(dmarq1_write_line);
132	123
133		UINT8           cur_drive;
134		ide_slot_device *slot[2];
	124	UINT8           m_config_unknown;
	125	UINT8           m_config_register[IDE_CONFIG_REGISTERS];
	126	UINT8           m_config_register_num;
135	127
	128	ide_slot_device *m_slot[2];
	129	int m_irq[2];
	130	int m_dmarq[2];
	131
136	132	devcb2_write_line m_irq_handler;
	133	devcb2_write_line m_dmarq_handler;
137	134	};
138	135
139	136	extern const device_type IDE_CONTROLLER;
r23677	r23678
157	154	DECLARE_READ32_MEMBER( ide_bus_master32_r );
158	155	DECLARE_WRITE32_MEMBER( ide_bus_master32_w );
159	156
160		virtual void set_irq(int state);
161		virtual void set_dmarq(int state);
162
163	157	protected:
164	158	virtual void device_start();
165	159
	160	virtual void set_irq(int state);
	161	virtual void set_dmarq(int state);
	162
166	163	private:
167	164	void execute_dma();
168	165

trunk/src/emu/machine/idehd.c

r23677	r23678
1	1	#include "idehd.h"
2	2
	3	/***************************************************************************
	4	DEBUGGING
	5	***************************************************************************/
	6
	7	#define VERBOSE                     0
3	8	#define PRINTF_IDE_COMMANDS         0
	9	#define PRINTF_IDE_PASSWORD         0
4	10
	11	#define LOG(x)  do { if (VERBOSE) logerror x; } while (0)
	12
	13	#define LOGPRINT(x) do { if (VERBOSE) logerror x; if (PRINTF_IDE_COMMANDS) mame_printf_debug x; } while (0)
	14
	15	#define MINIMUM_COMMAND_TIME                (attotime::from_usec(10))
	16
	17	#define TIME_PER_SECTOR                     (attotime::from_usec(100))
	18	#define TIME_PER_ROTATION                   (attotime::from_hz(5400/60))
	19	#define TIME_SECURITY_ERROR                 (attotime::from_msec(1000))
	20
	21	#define TIME_SEEK_MULTISECTOR               (attotime::from_msec(13))
	22	#define TIME_NO_SEEK_MULTISECTOR            (attotime::from_nsec(16300))
	23
	24	#define IDE_BANK0_DATA                      0
	25	#define IDE_BANK0_ERROR                     1
	26	#define IDE_BANK0_SECTOR_COUNT              2
	27	#define IDE_BANK0_SECTOR_NUMBER             3
	28	#define IDE_BANK0_CYLINDER_LSB              4
	29	#define IDE_BANK0_CYLINDER_MSB              5
	30	#define IDE_BANK0_HEAD_NUMBER               6
	31	#define IDE_BANK0_STATUS_COMMAND            7
	32
	33	#define IDE_BANK1_STATUS_CONTROL            6
	34
	35	#define IDE_COMMAND_READ_SECTORS            0x20
	36	#define IDE_COMMAND_READ_SECTORS_NORETRY    0x21
	37	#define IDE_COMMAND_WRITE_SECTORS           0x30
	38	#define IDE_COMMAND_WRITE_SECTORS_NORETRY   0x31
	39	#define IDE_COMMAND_DIAGNOSTIC              0x90
	40	#define IDE_COMMAND_SET_CONFIG              0x91
	41	#define IDE_COMMAND_READ_MULTIPLE           0xc4
	42	#define IDE_COMMAND_WRITE_MULTIPLE          0xc5
	43	#define IDE_COMMAND_SET_BLOCK_COUNT         0xc6
	44	#define IDE_COMMAND_READ_DMA                0xc8
	45	#define IDE_COMMAND_WRITE_DMA               0xca
	46	#define IDE_COMMAND_GET_INFO                0xec
	47	#define IDE_COMMAND_SET_FEATURES            0xef
	48	#define IDE_COMMAND_SECURITY_UNLOCK         0xf2
	49	#define IDE_COMMAND_UNKNOWN_F9              0xf9
	50	#define IDE_COMMAND_VERIFY_SECTORS          0x40
	51	#define IDE_COMMAND_VERIFY_SECTORS_NORETRY  0x41
	52	#define IDE_COMMAND_ATAPI_IDENTIFY          0xa1
	53	#define IDE_COMMAND_RECALIBRATE             0x10
	54	#define IDE_COMMAND_SEEK                    0x70
	55	#define IDE_COMMAND_IDLE_IMMEDIATE          0xe1
	56	#define IDE_COMMAND_IDLE                    0xe3
	57	#define IDE_COMMAND_TAITO_GNET_UNLOCK_1     0xfe
	58	#define IDE_COMMAND_TAITO_GNET_UNLOCK_2     0xfc
	59	#define IDE_COMMAND_TAITO_GNET_UNLOCK_3     0x0f
	60
5	61	enum
6	62	{
7	63	TID_NULL,
r23677	r23678
23	79
24	80	ide_device_interface::ide_device_interface(const machine_config &mconfig, device_t &device)
25	81	: device_slot_card_interface(mconfig, device),
26		master_password(NULL),
27		user_password(NULL)
	82	m_master_password(NULL),
	83	m_user_password(NULL),
	84	m_irq_handler(*this),
	85	m_dmarq_handler(*this)
28	86	{
29	87	}
30	88
	89	void ide_device_interface::set_irq(int state)
	90	{
	91	if (state == ASSERT_LINE)
	92	LOG(("IDE interrupt assert\n"));
	93	else
	94	LOG(("IDE interrupt clear\n"));
31	95
	96	/* signal an interrupt */
	97	m_irq_handler(state);
	98	}
32	99
	100	void ide_device_interface::set_dmarq(int state)
	101	{
	102	m_dmarq_handler(state);
	103	}
	104
	105	ide_mass_storage_device::ide_mass_storage_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock,const char *shortname, const char *source)
	106	: device_t(mconfig, type, name, tag, owner, clock, shortname, source),
	107	ide_device_interface(mconfig, *this)
	108	{
	109	}
	110
33	111	/*************************************
34	112	*
35	113	*  Compute the LBA address
36	114	*
37	115	*************************************/
38	116
39		UINT32 ide_device_interface::lba_address()
	117	UINT32 ide_mass_storage_device::lba_address()
40	118	{
41	119	/* LBA direct? */
42		if (cur_head_reg & 0x40)
43		return cur_sector + cur_cylinder * 256 + cur_head * 16777216;
	120	if (m_cur_head_reg & 0x40)
	121	return m_cur_sector + m_cur_cylinder * 256 + m_cur_head * 16777216;
44	122
45	123	/* standard CHS */
46	124	else
47		return (cur_cylinder * get_heads() + cur_head) * get_sectors() + cur_sector - 1;
	125	return (m_cur_cylinder * get_heads() + m_cur_head) * get_sectors() + m_cur_sector - 1;
48	126	}
49	127
50	128
r23677	r23678
223	301	m_features[255*2+1] = 0x00;
224	302	}
225	303
226		//**************************************************************************
227		//  IDE HARD DISK DEVICE
228		//**************************************************************************
229
230		// device type definition
231		const device_type IDE_HARDDISK = &device_creator<ide_hdd_device>;
232
233	304	//-------------------------------------------------
234		//  ide_hdd_device - constructor
	305	//  device_start - device-specific startup
235	306	//-------------------------------------------------
236	307
237		ide_hdd_device::ide_hdd_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
238		: device_t(mconfig, IDE_HARDDISK, "IDE Hard Disk", tag, owner, clock, "hdd", __FILE__),
239		ide_device_interface( mconfig, *this )
	308	void ide_mass_storage_device::device_start()
240	309	{
	310	m_irq_handler.resolve_safe();
	311	m_dmarq_handler.resolve_safe();
	312
	313	save_item(NAME(m_features));
	314
	315	save_item(NAME(m_cur_cylinder));
	316	save_item(NAME(m_cur_sector));
	317	save_item(NAME(m_cur_head));
	318	save_item(NAME(m_cur_head_reg));
	319
	320	save_item(NAME(m_cur_lba));
	321
	322	save_item(NAME(m_buffer));
	323	save_item(NAME(m_buffer_offset));
	324
	325	save_item(NAME(m_status));
	326	save_item(NAME(m_command));
	327	save_item(NAME(m_error));
	328
	329	save_item(NAME(m_adapter_control));
	330	save_item(NAME(m_precomp_offset));
	331	save_item(NAME(m_sector_count));
	332
	333	save_item(NAME(m_interrupt_pending));
	334	save_item(NAME(m_sectors_until_int));
	335
	336	save_item(NAME(m_master_password_enable));
	337	save_item(NAME(m_user_password_enable));
	338
	339	save_item(NAME(m_gnetreadlock));
	340	save_item(NAME(m_block_count));
	341
	342	save_item(NAME(m_dma_active));
	343	save_item(NAME(m_verify_only));
	344
	345	/* create a timer for timing status */
	346	m_last_status_timer = timer_alloc(TID_NULL);
	347	m_reset_timer = timer_alloc(TID_RESET_CALLBACK);
241	348	}
242	349
243		ide_hdd_device::ide_hdd_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) :
244		device_t(mconfig, type, name, tag, owner, clock, shortname, source),
245		ide_device_interface(mconfig, *this)
	350	void ide_mass_storage_device::device_reset()
246	351	{
	352	m_buffer_offset = 0;
	353	m_gnetreadlock = 0;
	354	m_master_password_enable = (m_master_password != NULL);
	355	m_user_password_enable = (m_user_password != NULL);
	356	m_error = IDE_ERROR_DEFAULT;
	357	m_status = IDE_STATUS_DRIVE_READY | IDE_STATUS_SEEK_COMPLETE;
	358	m_cur_drive = 0;
	359
	360	/* reset the drive state */
	361	set_irq(CLEAR_LINE);
	362	set_dmarq(CLEAR_LINE);
247	363	}
248	364
249		//-------------------------------------------------
250		//  device_start - device-specific startup
251		//-------------------------------------------------
	365	void ide_mass_storage_device::set_irq(int state)
	366	{
	367	ide_device_interface::set_irq(state);
252	368
253		void ide_hdd_device::device_start()
	369	m_interrupt_pending = state;
	370	}
	371
	372	void ide_mass_storage_device::signal_delayed_interrupt(attotime time, int buffer_ready)
254	373	{
255		//  save_item(NAME(features));
	374	/* clear buffer ready and set the busy flag */
	375	m_status &= ~IDE_STATUS_BUFFER_READY;
	376	m_status |= IDE_STATUS_BUSY;
256	377
257		save_item(NAME(cur_cylinder));
258		save_item(NAME(cur_sector));
259		save_item(NAME(cur_head));
260		save_item(NAME(cur_head_reg));
	378	/* set a timer */
	379	if (buffer_ready)
	380	timer_set(time, TID_DELAYED_INTERRUPT_BUFFER_READY);
	381	else
	382	timer_set(time, TID_DELAYED_INTERRUPT);
	383	}
261	384
262		save_item(NAME(cur_lba));
	385	/*************************************
	386	*
	387	*  Advance to the next sector
	388	*
	389	*************************************/
263	390
264		save_item(NAME(buffer));
265		save_item(NAME(buffer_offset));
	391	void ide_mass_storage_device::next_sector()
	392	{
	393	/* LBA direct? */
	394	if (m_cur_head_reg & 0x40)
	395	{
	396	m_cur_sector++;
	397	if (m_cur_sector == 0)
	398	{
	399	m_cur_cylinder++;
	400	if (m_cur_cylinder == 0)
	401	m_cur_head++;
	402	}
	403	}
266	404
267		save_item(NAME(status));
268		save_item(NAME(command));
269		save_item(NAME(error));
	405	/* standard CHS */
	406	else
	407	{
	408	/* sectors are 1-based */
	409	m_cur_sector++;
	410	if (m_cur_sector > get_sectors())
	411	{
	412	/* heads are 0 based */
	413	m_cur_sector = 1;
	414	m_cur_head++;
	415	if (m_cur_head >= get_heads())
	416	{
	417	m_cur_head = 0;
	418	m_cur_cylinder++;
	419	}
	420	}
	421	}
270	422
271		save_item(NAME(adapter_control));
272		save_item(NAME(precomp_offset));
273		save_item(NAME(sector_count));
	423	m_cur_lba = lba_address();
	424	}
274	425
275		save_item(NAME(interrupt_pending));
276		save_item(NAME(sectors_until_int));
277	426
278		save_item(NAME(master_password_enable));
279		save_item(NAME(user_password_enable));
280	427
281		save_item(NAME(gnetreadlock));
282		save_item(NAME(block_count));
	428	/*************************************
	429	*
	430	*  security error handling
	431	*
	432	*************************************/
283	433
284		save_item(NAME(dma_active));
285		save_item(NAME(verify_only));
	434	void ide_mass_storage_device::security_error()
	435	{
	436	/* set error state */
	437	m_status |= IDE_STATUS_ERROR;
	438	m_status &= ~IDE_STATUS_DRIVE_READY;
286	439
287		/* create a timer for timing status */
288		last_status_timer = timer_alloc(TID_NULL);
289		reset_timer = timer_alloc(TID_RESET_CALLBACK);
	440	/* just set a timer and mark ourselves error */
	441	timer_set(TIME_SECURITY_ERROR, TID_SECURITY_ERROR_DONE);
290	442	}
291	443
	444
	445
	446	/*************************************
	447	*
	448	*  Sector reading
	449	*
	450	*************************************/
	451
	452	void ide_mass_storage_device::read_buffer_empty()
	453	{
	454	/* reset the totals */
	455	m_buffer_offset = 0;
	456
	457	/* clear the buffer ready and busy flag */
	458	m_status &= ~IDE_STATUS_BUFFER_READY;
	459	m_status &= ~IDE_STATUS_BUSY;
	460	m_error = IDE_ERROR_DEFAULT;
	461	set_dmarq(CLEAR_LINE);
	462
	463	if (m_master_password_enable || m_user_password_enable)
	464	{
	465	security_error();
	466
	467	m_sector_count = 0;
	468
	469	return;
	470	}
	471
	472	/* if there is more data to read, keep going */
	473	if (m_sector_count > 0)
	474	m_sector_count--;
	475	if (m_sector_count > 0)
	476	read_next_sector();
	477	}
	478
	479
	480	void ide_mass_storage_device::read_sector_done()
	481	{
	482	int lba = lba_address(), count = 0;
	483
	484	/* GNET readlock check */
	485	if (m_gnetreadlock) {
	486	m_status &= ~IDE_STATUS_ERROR;
	487	m_status &= ~IDE_STATUS_BUSY;
	488	return;
	489	}
	490
	491	/* now do the read */
	492	count = read_sector(lba, m_buffer);
	493
	494	/* by default, mark the buffer ready and the seek complete */
	495	if (!m_verify_only)
	496	m_status |= IDE_STATUS_BUFFER_READY;
	497	m_status |= IDE_STATUS_SEEK_COMPLETE;
	498
	499	/* and clear the busy and error flags */
	500	m_status &= ~IDE_STATUS_ERROR;
	501	m_status &= ~IDE_STATUS_BUSY;
	502
	503	/* if we succeeded, advance to the next sector and set the nice bits */
	504	if (count == 1)
	505	{
	506	/* advance the pointers, unless this is the last sector */
	507	/* Gauntlet: Dark Legacy checks to make sure we stop on the last sector */
	508	if (m_sector_count != 1)
	509	next_sector();
	510
	511	/* clear the error value */
	512	m_error = IDE_ERROR_NONE;
	513
	514	/* signal an interrupt */
	515	if (!m_verify_only)
	516	m_sectors_until_int--;
	517	if (m_sectors_until_int == 0 || m_sector_count == 1)
	518	{
	519	m_sectors_until_int = ((m_command == IDE_COMMAND_READ_MULTIPLE) ? m_block_count : 1);
	520	set_irq(ASSERT_LINE);
	521	}
	522
	523	/* handle DMA */
	524	if (m_dma_active)
	525	set_dmarq(ASSERT_LINE);
	526
	527	/* if we're just verifying we can read the next sector */
	528	if (m_verify_only)
	529	read_buffer_empty();
	530	}
	531
	532	/* if we got an error, we need to report it */
	533	else
	534	{
	535	/* set the error flag and the error */
	536	m_status |= IDE_STATUS_ERROR;
	537	m_error = IDE_ERROR_BAD_SECTOR;
	538
	539	/* signal an interrupt */
	540	set_irq(ASSERT_LINE);
	541	}
	542	}
	543
	544
	545	void ide_mass_storage_device::read_first_sector()
	546	{
	547	/* mark ourselves busy */
	548	m_status |= IDE_STATUS_BUSY;
	549
	550	/* just set a timer */
	551	if (m_command == IDE_COMMAND_READ_MULTIPLE)
	552	{
	553	int new_lba = lba_address();
	554	attotime seek_time;
	555
	556	if (new_lba == m_cur_lba || new_lba == m_cur_lba + 1)
	557	seek_time = TIME_NO_SEEK_MULTISECTOR;
	558	else
	559	seek_time = TIME_SEEK_MULTISECTOR;
	560
	561	m_cur_lba = new_lba;
	562	timer_set(seek_time, TID_READ_SECTOR_DONE_CALLBACK);
	563	}
	564	else
	565	timer_set(TIME_PER_SECTOR, TID_READ_SECTOR_DONE_CALLBACK);
	566	}
	567
	568
	569	void ide_mass_storage_device::read_next_sector()
	570	{
	571	/* mark ourselves busy */
	572	m_status |= IDE_STATUS_BUSY;
	573
	574	if (m_command == IDE_COMMAND_READ_MULTIPLE)
	575	{
	576	if (m_sectors_until_int != 1)
	577	/* make ready now */
	578	read_sector_done();
	579	else
	580	/* just set a timer */
	581	timer_set(attotime::from_usec(1), TID_READ_SECTOR_DONE_CALLBACK);
	582	}
	583	else
	584	/* just set a timer */
	585	timer_set(TIME_PER_SECTOR, TID_READ_SECTOR_DONE_CALLBACK);
	586	}
	587
	588
	589
	590	/*************************************
	591	*
	592	*  Sector writing
	593	*
	594	*************************************/
	595
	596	void ide_mass_storage_device::continue_write()
	597	{
	598	/* reset the totals */
	599	m_buffer_offset = 0;
	600
	601	/* clear the buffer ready flag */
	602	m_status &= ~IDE_STATUS_BUFFER_READY;
	603	m_status |= IDE_STATUS_BUSY;
	604
	605	if (m_command == IDE_COMMAND_WRITE_MULTIPLE)
	606	{
	607	if (m_sectors_until_int != 1)
	608	{
	609	/* ready to write now */
	610	write_sector_done();
	611	}
	612	else
	613	{
	614	/* set a timer to do the write */
	615	timer_set(TIME_PER_SECTOR, TID_WRITE_SECTOR_DONE_CALLBACK);
	616	}
	617	}
	618	else
	619	{
	620	/* set a timer to do the write */
	621	timer_set(TIME_PER_SECTOR, TID_WRITE_SECTOR_DONE_CALLBACK);
	622	}
	623	}
	624
	625
	626	void ide_mass_storage_device::write_buffer_full()
	627	{
	628	set_dmarq(CLEAR_LINE);
	629	if (m_command == IDE_COMMAND_SECURITY_UNLOCK)
	630	{
	631	if (m_user_password_enable && memcmp(m_buffer, m_user_password, 2 + 32) == 0)
	632	{
	633	LOGPRINT(("IDE Unlocked user password\n"));
	634	m_user_password_enable = 0;
	635	}
	636	if (m_master_password_enable && memcmp(m_buffer, m_master_password, 2 + 32) == 0)
	637	{
	638	LOGPRINT(("IDE Unlocked master password\n"));
	639	m_master_password_enable = 0;
	640	}
	641	if (PRINTF_IDE_PASSWORD)
	642	{
	643	int i;
	644
	645	for (i = 0; i < 34; i += 2)
	646	{
	647	if (i % 8 == 2)
	648	mame_printf_debug("\n");
	649
	650	mame_printf_debug("0x%02x, 0x%02x, ", m_buffer[i], m_buffer[i + 1]);
	651	//mame_printf_debug("0x%02x%02x, ", m_buffer[i], m_buffer[i + 1]);
	652	}
	653	mame_printf_debug("\n");
	654	}
	655
	656	/* clear the busy and error flags */
	657	m_status &= ~IDE_STATUS_ERROR;
	658	m_status &= ~IDE_STATUS_BUSY;
	659	m_status &= ~IDE_STATUS_BUFFER_READY;
	660
	661	if (m_master_password_enable || m_user_password_enable)
	662	security_error();
	663	else
	664	m_status |= IDE_STATUS_DRIVE_READY;
	665	}
	666	else if (m_command == IDE_COMMAND_TAITO_GNET_UNLOCK_2)
	667	{
	668	UINT8 key[5] = { 0 };
	669	int i, bad = 0;
	670	read_key(key);
	671
	672	for (i=0; !bad && i<512; i++)
	673	bad = ((i < 2 || i >= 7) && m_buffer[i]) || ((i >= 2 && i < 7) && m_buffer[i] != key[i-2]);
	674
	675	m_status &= ~IDE_STATUS_BUSY;
	676	m_status &= ~IDE_STATUS_BUFFER_READY;
	677	if (bad)
	678	m_status |= IDE_STATUS_ERROR;
	679	else {
	680	m_status &= ~IDE_STATUS_ERROR;
	681	m_gnetreadlock= 0;
	682	}
	683	}
	684	else
	685	{
	686	continue_write();
	687	}
	688	}
	689
	690
	691	void ide_mass_storage_device::write_sector_done()
	692	{
	693	int lba = lba_address(), count = 0;
	694
	695	/* now do the write */
	696	count = write_sector(lba, m_buffer);
	697
	698	/* by default, mark the buffer ready and the seek complete */
	699	m_status |= IDE_STATUS_BUFFER_READY;
	700	m_status |= IDE_STATUS_SEEK_COMPLETE;
	701
	702	/* and clear the busy adn error flags */
	703	m_status &= ~IDE_STATUS_ERROR;
	704	m_status &= ~IDE_STATUS_BUSY;
	705
	706	/* if we succeeded, advance to the next sector and set the nice bits */
	707	if (count == 1)
	708	{
	709	/* advance the pointers, unless this is the last sector */
	710	/* Gauntlet: Dark Legacy checks to make sure we stop on the last sector */
	711	if (m_sector_count != 1)
	712	next_sector();
	713
	714	/* clear the error value */
	715	m_error = IDE_ERROR_NONE;
	716
	717	/* signal an interrupt */
	718	if (--m_sectors_until_int == 0 || m_sector_count == 1)
	719	{
	720	m_sectors_until_int = ((m_command == IDE_COMMAND_WRITE_MULTIPLE) ? m_block_count : 1);
	721	set_irq(ASSERT_LINE);
	722	}
	723
	724	/* signal an interrupt if there's more data needed */
	725	if (m_sector_count > 0)
	726	m_sector_count--;
	727	if (m_sector_count == 0)
	728	m_status &= ~IDE_STATUS_BUFFER_READY;
	729
	730	/* keep going for DMA */
	731	if (m_dma_active && m_sector_count != 0)
	732	{
	733	set_dmarq(ASSERT_LINE);
	734	}
	735	}
	736
	737	/* if we got an error, we need to report it */
	738	else
	739	{
	740	/* set the error flag and the error */
	741	m_status |= IDE_STATUS_ERROR;
	742	m_error = IDE_ERROR_BAD_SECTOR;
	743
	744	/* signal an interrupt */
	745	set_irq(ASSERT_LINE);
	746	}
	747	}
	748
	749
	750
	751	/*************************************
	752	*
	753	*  Handle IDE commands
	754	*
	755	*************************************/
	756
	757	void ide_mass_storage_device::handle_command(UINT8 _command)
	758	{
	759	UINT8 key[5];
	760
	761	/* implicitly clear interrupts & dmarq here */
	762	set_irq(CLEAR_LINE);
	763	set_dmarq(CLEAR_LINE);
	764	m_command = _command;
	765	switch (m_command)
	766	{
	767	case IDE_COMMAND_READ_SECTORS:
	768	case IDE_COMMAND_READ_SECTORS_NORETRY:
	769	LOGPRINT(("IDE Read multiple: C=%d H=%d S=%d LBA=%d count=%d\n",
	770	m_cur_cylinder, m_cur_head, m_cur_sector, lba_address(), m_sector_count));
	771
	772	/* reset the buffer */
	773	m_buffer_offset = 0;
	774	m_sectors_until_int = 1;
	775	m_dma_active = 0;
	776	m_verify_only = 0;
	777
	778	/* start the read going */
	779	read_first_sector();
	780	break;
	781
	782	case IDE_COMMAND_READ_MULTIPLE:
	783	LOGPRINT(("IDE Read multiple block: C=%d H=%d S=%d LBA=%d count=%d\n",
	784	m_cur_cylinder, m_cur_head, m_cur_sector, lba_address(), m_sector_count));
	785
	786	/* reset the buffer */
	787	m_buffer_offset = 0;
	788	m_sectors_until_int = 1;
	789	m_dma_active = 0;
	790	m_verify_only = 0;
	791
	792	/* start the read going */
	793	read_first_sector();
	794	break;
	795
	796	case IDE_COMMAND_VERIFY_SECTORS:
	797	case IDE_COMMAND_VERIFY_SECTORS_NORETRY:
	798	LOGPRINT(("IDE Read verify multiple with/without retries: C=%d H=%d S=%d LBA=%d count=%d\n",
	799	m_cur_cylinder, m_cur_head, m_cur_sector, lba_address(), m_sector_count));
	800
	801	/* reset the buffer */
	802	m_buffer_offset = 0;
	803	m_sectors_until_int = 1;
	804	m_dma_active = 0;
	805	m_verify_only = 1;
	806
	807	/* start the read going */
	808	read_first_sector();
	809	break;
	810
	811	case IDE_COMMAND_READ_DMA:
	812	LOGPRINT(("IDE Read multiple DMA: C=%d H=%d S=%d LBA=%d count=%d\n",
	813	m_cur_cylinder, m_cur_head, m_cur_sector, lba_address(), m_sector_count));
	814
	815	/* reset the buffer */
	816	m_buffer_offset = 0;
	817	m_sectors_until_int = m_sector_count;
	818	m_dma_active = 1;
	819	m_verify_only = 0;
	820
	821	/* start the read going */
	822	read_first_sector();
	823	break;
	824
	825	case IDE_COMMAND_WRITE_SECTORS:
	826	case IDE_COMMAND_WRITE_SECTORS_NORETRY:
	827	LOGPRINT(("IDE Write multiple: C=%d H=%d S=%d LBA=%d count=%d\n",
	828	m_cur_cylinder, m_cur_head, m_cur_sector, lba_address(), m_sector_count));
	829
	830	/* reset the buffer */
	831	m_buffer_offset = 0;
	832	m_sectors_until_int = 1;
	833	m_dma_active = 0;
	834
	835	/* mark the buffer ready */
	836	m_status |= IDE_STATUS_BUFFER_READY;
	837	break;
	838
	839	case IDE_COMMAND_WRITE_MULTIPLE:
	840	LOGPRINT(("IDE Write multiple block: C=%d H=%d S=%d LBA=%d count=%d\n",
	841	m_cur_cylinder, m_cur_head, m_cur_sector, lba_address(), m_sector_count));
	842
	843	/* reset the buffer */
	844	m_buffer_offset = 0;
	845	m_sectors_until_int = 1;
	846	m_dma_active = 0;
	847
	848	/* mark the buffer ready */
	849	m_status |= IDE_STATUS_BUFFER_READY;
	850	break;
	851
	852	case IDE_COMMAND_WRITE_DMA:
	853	LOGPRINT(("IDE Write multiple DMA: C=%d H=%d S=%d LBA=%d count=%d\n",
	854	m_cur_cylinder, m_cur_head, m_cur_sector, lba_address(), m_sector_count));
	855
	856	/* reset the buffer */
	857	m_buffer_offset = 0;
	858	m_sectors_until_int = m_sector_count;
	859	m_dma_active = 1;
	860
	861	/* start the read going */
	862	set_dmarq(ASSERT_LINE);
	863	break;
	864
	865	case IDE_COMMAND_SECURITY_UNLOCK:
	866	LOGPRINT(("IDE Security Unlock\n"));
	867
	868	/* reset the buffer */
	869	m_buffer_offset = 0;
	870	m_sectors_until_int = 0;
	871	m_dma_active = 0;
	872
	873	/* mark the buffer ready */
	874	m_status |= IDE_STATUS_BUFFER_READY;
	875	set_irq(ASSERT_LINE);
	876	break;
	877
	878	case IDE_COMMAND_GET_INFO:
	879	LOGPRINT(("IDE Read features\n"));
	880
	881	/* reset the buffer */
	882	m_buffer_offset = 0;
	883	m_sector_count = 1;
	884
	885	/* build the features page */
	886	memcpy(m_buffer, m_features, sizeof(m_buffer));
	887
	888	/* indicate everything is ready */
	889	m_status |= IDE_STATUS_BUFFER_READY;
	890	m_status |= IDE_STATUS_SEEK_COMPLETE;
	891	m_status |= IDE_STATUS_DRIVE_READY;
	892
	893	/* and clear the busy adn error flags */
	894	m_status &= ~IDE_STATUS_ERROR;
	895	m_status &= ~IDE_STATUS_BUSY;
	896
	897	/* clear the error too */
	898	m_error = IDE_ERROR_NONE;
	899
	900	/* signal an interrupt */
	901	signal_delayed_interrupt(MINIMUM_COMMAND_TIME, 1);
	902	break;
	903
	904	case IDE_COMMAND_DIAGNOSTIC:
	905	m_error = IDE_ERROR_DEFAULT;
	906
	907	/* signal an interrupt */
	908	signal_delayed_interrupt(MINIMUM_COMMAND_TIME, 0);
	909	break;
	910
	911	case IDE_COMMAND_RECALIBRATE:
	912	/* clear the error too */
	913	m_error = IDE_ERROR_NONE;
	914	/* signal an interrupt */
	915	signal_delayed_interrupt(MINIMUM_COMMAND_TIME, 0);
	916	break;
	917
	918	case IDE_COMMAND_IDLE:
	919	/* clear the error too */
	920	m_error = IDE_ERROR_NONE;
	921
	922	/* for timeout disabled value is 0 */
	923	m_sector_count = 0;
	924	/* signal an interrupt */
	925	set_irq(ASSERT_LINE);
	926	break;
	927
	928	case IDE_COMMAND_SET_CONFIG:
	929	LOGPRINT(("IDE Set configuration (%d heads, %d sectors)\n", m_cur_head + 1, m_sector_count));
	930	m_status &= ~IDE_STATUS_ERROR;
	931	m_error = IDE_ERROR_NONE;
	932	set_geometry(m_sector_count,m_cur_head + 1);
	933
	934	/* signal an interrupt */
	935	signal_delayed_interrupt(MINIMUM_COMMAND_TIME, 0);
	936	break;
	937
	938	case IDE_COMMAND_UNKNOWN_F9:
	939	/* only used by Killer Instinct AFAICT */
	940	LOGPRINT(("IDE unknown command (F9)\n"));
	941
	942	/* signal an interrupt */
	943	set_irq(ASSERT_LINE);
	944	break;
	945
	946	case IDE_COMMAND_SET_FEATURES:
	947	LOGPRINT(("IDE Set features (%02X %02X %02X %02X %02X)\n", m_precomp_offset, m_sector_count & 0xff, m_cur_sector, m_cur_cylinder & 0xff, m_cur_cylinder >> 8));
	948
	949	/* signal an interrupt */
	950	signal_delayed_interrupt(MINIMUM_COMMAND_TIME, 0);
	951	break;
	952
	953	case IDE_COMMAND_SET_BLOCK_COUNT:
	954	LOGPRINT(("IDE Set block count (%02X)\n", m_sector_count));
	955
	956	m_block_count = m_sector_count;
	957	// judge dredd wants 'drive ready' on this command
	958	m_status |= IDE_STATUS_DRIVE_READY;
	959
	960	/* signal an interrupt */
	961	set_irq(ASSERT_LINE);
	962	break;
	963
	964	case IDE_COMMAND_TAITO_GNET_UNLOCK_1:
	965	LOGPRINT(("IDE GNET Unlock 1\n"));
	966
	967	m_sector_count = 1;
	968	m_status |= IDE_STATUS_DRIVE_READY;
	969	m_status &= ~IDE_STATUS_ERROR;
	970	set_irq(ASSERT_LINE);
	971	break;
	972
	973	case IDE_COMMAND_TAITO_GNET_UNLOCK_2:
	974	LOGPRINT(("IDE GNET Unlock 2\n"));
	975
	976	/* reset the buffer */
	977	m_buffer_offset = 0;
	978	m_sectors_until_int = 0;
	979	m_dma_active = 0;
	980
	981	/* mark the buffer ready */
	982	m_status |= IDE_STATUS_BUFFER_READY;
	983	set_irq(ASSERT_LINE);
	984	break;
	985
	986	case IDE_COMMAND_TAITO_GNET_UNLOCK_3:
	987	LOGPRINT(("IDE GNET Unlock 3\n"));
	988
	989	/* key check */
	990	read_key(key);
	991	if ((m_precomp_offset == key[0]) && (m_sector_count == key[1]) && (m_cur_sector == key[2]) && (m_cur_cylinder == (((UINT16)key[4]<<8)|key[3])))
	992	{
	993	m_gnetreadlock= 0;
	994	}
	995
	996	/* update flags */
	997	m_status |= IDE_STATUS_DRIVE_READY;
	998	m_status &= ~IDE_STATUS_ERROR;
	999	set_irq(ASSERT_LINE);
	1000	break;
	1001
	1002	case IDE_COMMAND_SEEK:
	1003	/*
	1004	cur_cylinder, cur_sector and cur_head
	1005	are all already set in this case so no need
	1006	so that implements actual seek
	1007	*/
	1008	/* clear the error too */
	1009	m_error = IDE_ERROR_NONE;
	1010
	1011	/* for timeout disabled value is 0 */
	1012	m_sector_count = 0;
	1013	/* signal an interrupt */
	1014	set_irq(ASSERT_LINE);
	1015	break;
	1016
	1017
	1018	default:
	1019	LOGPRINT(("IDE unknown command (%02X)\n", m_command));
	1020	m_status |= IDE_STATUS_ERROR;
	1021	m_error = IDE_ERROR_UNKNOWN_COMMAND;
	1022	set_irq(ASSERT_LINE);
	1023	//debugger_break(device->machine());
	1024	break;
	1025	}
	1026	}
	1027
	1028	UINT16 ide_mass_storage_device::read_dma()
	1029	{
	1030	if (m_cur_drive != m_csel)
	1031	{
	1032	if (m_csel == 0 && m_dasp == 0)
	1033	return 0;
	1034
	1035	return 0xffff;
	1036	}
	1037
	1038	UINT16 result = m_buffer[m_buffer_offset++];
	1039	result |= m_buffer[m_buffer_offset++] << 8;
	1040
	1041	if (m_buffer_offset >= IDE_DISK_SECTOR_SIZE)
	1042	{
	1043	LOG(("%s:IDE completed DMA read\n", machine().describe_context()));
	1044	read_buffer_empty();
	1045	}
	1046
	1047	return result;
	1048	}
	1049
	1050	READ16_MEMBER( ide_mass_storage_device::read_cs0 )
	1051	{
	1052	UINT16 result = 0;
	1053
	1054	/* logit */
	1055	//  if (offset != IDE_BANK0_DATA && offset != IDE_BANK0_STATUS_COMMAND)
	1056	LOG(("%s:IDE cs0 read at %X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask));
	1057
	1058	if (m_cur_drive != m_csel)
	1059	{
	1060	if (m_csel == 0 && m_dasp == 0)
	1061	return 0;
	1062
	1063	return 0xffff;
	1064	}
	1065
	1066	if (is_ready()) {
	1067	m_status |= IDE_STATUS_DRIVE_READY;
	1068	} else {
	1069	m_status &= ~IDE_STATUS_DRIVE_READY;
	1070	}
	1071
	1072	switch (offset)
	1073	{
	1074	/* read data if there's data to be read */
	1075	case IDE_BANK0_DATA:
	1076	if (m_status & IDE_STATUS_BUFFER_READY)
	1077	{
	1078	/* fetch the correct amount of data */
	1079	result = m_buffer[m_buffer_offset++];
	1080	if (mem_mask == 0xffff)
	1081	result |= m_buffer[m_buffer_offset++] << 8;
	1082
	1083	/* if we're at the end of the buffer, handle it */
	1084	if (m_buffer_offset >= IDE_DISK_SECTOR_SIZE)
	1085	{
	1086	LOG(("%s:IDE completed PIO read\n", machine().describe_context()));
	1087	read_buffer_empty();
	1088	}
	1089	}
	1090	break;
	1091
	1092	/* return the current error */
	1093	case IDE_BANK0_ERROR:
	1094	result = m_error;
	1095	break;
	1096
	1097	/* return the current sector count */
	1098	case IDE_BANK0_SECTOR_COUNT:
	1099	result = m_sector_count;
	1100	break;
	1101
	1102	/* return the current sector */
	1103	case IDE_BANK0_SECTOR_NUMBER:
	1104	result = m_cur_sector;
	1105	break;
	1106
	1107	/* return the current cylinder LSB */
	1108	case IDE_BANK0_CYLINDER_LSB:
	1109	result = m_cur_cylinder & 0xff;
	1110	break;
	1111
	1112	/* return the current cylinder MSB */
	1113	case IDE_BANK0_CYLINDER_MSB:
	1114	result = m_cur_cylinder >> 8;
	1115	break;
	1116
	1117	/* return the current head */
	1118	case IDE_BANK0_HEAD_NUMBER:
	1119	result = m_cur_head_reg;
	1120	break;
	1121
	1122	/* return the current status and clear any pending interrupts */
	1123	case IDE_BANK0_STATUS_COMMAND:
	1124	result = m_status;
	1125	if (m_last_status_timer->elapsed() > TIME_PER_ROTATION)
	1126	{
	1127	result |= IDE_STATUS_HIT_INDEX;
	1128	m_last_status_timer->adjust(attotime::never);
	1129	}
	1130	if (m_interrupt_pending == ASSERT_LINE)
	1131	set_irq(CLEAR_LINE);
	1132	break;
	1133
	1134	/* log anything else */
	1135	default:
	1136	logerror("%s:unknown IDE cs0 read at %03X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask);
	1137	break;
	1138	}
	1139
	1140	/* return the result */
	1141	return result;
	1142	}
	1143
	1144	READ16_MEMBER( ide_mass_storage_device::read_cs1 )
	1145	{
	1146	if (m_cur_drive != m_csel)
	1147	{
	1148	if (m_csel == 0 && m_dasp == 0)
	1149	return 0;
	1150
	1151	return 0xffff;
	1152	}
	1153
	1154	if (is_ready()) {
	1155	m_status |= IDE_STATUS_DRIVE_READY;
	1156	} else {
	1157	m_status &= ~IDE_STATUS_DRIVE_READY;
	1158	}
	1159
	1160	/* logit */
	1161	//  if (offset != IDE_BANK1_STATUS_CONTROL)
	1162	LOG(("%s:IDE cs1 read at %X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask));
	1163	/* return the current status but don't clear interrupts */
	1164
	1165	UINT16 result = 0;
	1166
	1167	switch (offset)
	1168	{
	1169	case IDE_BANK1_STATUS_CONTROL:
	1170	result = m_status;
	1171	if (m_last_status_timer->elapsed() > TIME_PER_ROTATION)
	1172	{
	1173	result |= IDE_STATUS_HIT_INDEX;
	1174	m_last_status_timer->adjust(attotime::never);
	1175	}
	1176	break;
	1177
	1178	/* log anything else */
	1179	default:
	1180	logerror("%s:unknown IDE cs1 read at %03X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask);
	1181	break;
	1182	}
	1183
	1184	/* return the result */
	1185	return result;
	1186	}
	1187
	1188	void ide_mass_storage_device::write_dma( UINT16 data )
	1189	{
	1190	if (m_cur_drive != m_csel)
	1191	return;
	1192
	1193	m_buffer[m_buffer_offset++] = data;
	1194	m_buffer[m_buffer_offset++] = data >> 8;
	1195
	1196	/* if we're at the end of the buffer, handle it */
	1197	if (m_buffer_offset >= IDE_DISK_SECTOR_SIZE)
	1198	{
	1199	LOG(("%s:IDE completed DMA write\n", machine().describe_context()));
	1200	write_buffer_full();
	1201	}
	1202	}
	1203
	1204	WRITE16_MEMBER( ide_mass_storage_device::write_cs0 )
	1205	{
	1206	switch (offset)
	1207	{
	1208	case IDE_BANK0_HEAD_NUMBER:
	1209	m_cur_drive = (data & 0x10) >> 4;
	1210	break;
	1211	}
	1212
	1213	if (m_cur_drive != m_csel)
	1214	return;
	1215
	1216	/* logit */
	1217	if (offset != IDE_BANK0_DATA)
	1218	LOG(("%s:IDE cs0 write to %X = %08X, mem_mask=%d\n", machine().describe_context(), offset, data, mem_mask));
	1219	//  fprintf(stderr, "ide write %03x %02x mem_mask=%d\n", offset, data, size);
	1220	switch (offset)
	1221	{
	1222	/* write data */
	1223	case IDE_BANK0_DATA:
	1224	if (m_status & IDE_STATUS_BUFFER_READY)
	1225	{
	1226	/* store the correct amount of data */
	1227	m_buffer[m_buffer_offset++] = data;
	1228	if (mem_mask == 0xffff)
	1229	m_buffer[m_buffer_offset++] = data >> 8;
	1230
	1231	/* if we're at the end of the buffer, handle it */
	1232	if (m_buffer_offset >= IDE_DISK_SECTOR_SIZE)
	1233	{
	1234	LOG(("%s:IDE completed PIO write\n", machine().describe_context()));
	1235	write_buffer_full();
	1236	}
	1237	}
	1238	break;
	1239
	1240	/* precompensation offset?? */
	1241	case IDE_BANK0_ERROR:
	1242	m_precomp_offset = data;
	1243	break;
	1244
	1245	/* sector count */
	1246	case IDE_BANK0_SECTOR_COUNT:
	1247	m_sector_count = data ? data : 256;
	1248	break;
	1249
	1250	/* current sector */
	1251	case IDE_BANK0_SECTOR_NUMBER:
	1252	m_cur_sector = data;
	1253	break;
	1254
	1255	/* current cylinder LSB */
	1256	case IDE_BANK0_CYLINDER_LSB:
	1257	m_cur_cylinder = (m_cur_cylinder & 0xff00) | (data & 0xff);
	1258	break;
	1259
	1260	/* current cylinder MSB */
	1261	case IDE_BANK0_CYLINDER_MSB:
	1262	m_cur_cylinder = (m_cur_cylinder & 0x00ff) | ((data & 0xff) << 8);
	1263	break;
	1264
	1265	/* current head */
	1266	case IDE_BANK0_HEAD_NUMBER:
	1267	m_cur_head = data & 0x0f;
	1268	m_cur_head_reg = data;
	1269	// LBA mode = data & 0x40
	1270	break;
	1271
	1272	/* command */
	1273	case IDE_BANK0_STATUS_COMMAND:
	1274	handle_command(data);
	1275	break;
	1276	}
	1277	}
	1278
	1279	WRITE16_MEMBER( ide_mass_storage_device::write_cs1 )
	1280	{
	1281	if (m_cur_drive != m_csel)
	1282	return;
	1283
	1284	/* logit */
	1285	LOG(("%s:IDE cs1 write to %X = %08X, mem_mask=%d\n", machine().describe_context(), offset, data, mem_mask));
	1286
	1287	switch (offset)
	1288	{
	1289	/* adapter control */
	1290	case IDE_BANK1_STATUS_CONTROL:
	1291	m_adapter_control = data;
	1292
	1293	/* handle controller reset */
	1294	//if (data == 0x04)
	1295	if (data & 0x04)
	1296	{
	1297	m_status |= IDE_STATUS_BUSY;
	1298	m_status &= ~IDE_STATUS_DRIVE_READY;
	1299	m_reset_timer->adjust(attotime::from_msec(5));
	1300	}
	1301	break;
	1302	}
	1303	}
	1304
	1305	//**************************************************************************
	1306	//  IDE HARD DISK DEVICE
	1307	//**************************************************************************
	1308
	1309	// device type definition
	1310	const device_type IDE_HARDDISK = &device_creator<ide_hdd_device>;
	1311
292	1312	//-------------------------------------------------
	1313	//  ide_hdd_device - constructor
	1314	//-------------------------------------------------
	1315
	1316	ide_hdd_device::ide_hdd_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	1317	: ide_mass_storage_device(mconfig, IDE_HARDDISK, "IDE Hard Disk", tag, owner, clock, "hdd", __FILE__)
	1318	{
	1319	}
	1320
	1321	ide_hdd_device::ide_hdd_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) :
	1322	ide_mass_storage_device(mconfig, type, name, tag, owner, clock, shortname, source)
	1323	{
	1324	}
	1325
	1326	//-------------------------------------------------
293	1327	//  device_reset - device-specific reset
294	1328	//-------------------------------------------------
295	1329
296	1330	void ide_hdd_device::device_reset()
297	1331	{
	1332	ide_mass_storage_device::device_reset();
	1333
298	1334	m_handle = subdevice<harddisk_image_device>("harddisk")->get_chd_file();
299	1335
300	1336	if (m_handle)
r23677	r23678
323	1359	if (m_handle->read_metadata (HARD_DISK_IDENT_METADATA_TAG, 0, m_features, IDE_DISK_SECTOR_SIZE, metalength) != CHDERR_NONE)
324	1360	ide_build_features();
325	1361	}
326
327		buffer_offset = 0;
328		gnetreadlock = 0;
329		master_password_enable = (master_password != NULL);
330		user_password_enable = (user_password != NULL);
331		error = IDE_ERROR_DEFAULT;
332		status = IDE_STATUS_DRIVE_READY | IDE_STATUS_SEEK_COMPLETE;
333	1362	}
334	1363
335		void ide_hdd_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
	1364	void ide_mass_storage_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
336	1365	{
337	1366	switch(id)
338	1367	{
	1368	case TID_DELAYED_INTERRUPT:
	1369	m_status &= ~IDE_STATUS_BUSY;
	1370	set_irq(ASSERT_LINE);
	1371	break;
	1372
	1373	case TID_DELAYED_INTERRUPT_BUFFER_READY:
	1374	m_status &= ~IDE_STATUS_BUSY;
	1375	m_status |= IDE_STATUS_BUFFER_READY;
	1376	set_irq(ASSERT_LINE);
	1377	break;
	1378
339	1379	case TID_RESET_CALLBACK:
340	1380	reset();
341	1381	break;
	1382
	1383	case TID_SECURITY_ERROR_DONE:
	1384	/* clear error state */
	1385	m_status &= ~IDE_STATUS_ERROR;
	1386	m_status |= IDE_STATUS_DRIVE_READY;
	1387	break;
	1388
	1389	case TID_READ_SECTOR_DONE_CALLBACK:
	1390	read_sector_done();
	1391	break;
	1392
	1393	case TID_WRITE_SECTOR_DONE_CALLBACK:
	1394	write_sector_done();
	1395	break;
342	1396	}
343	1397	}
344	1398

trunk/src/emu/machine/idehd.h

r23677	r23678
23	23	{
24	24	public:
25	25	ide_device_interface(const machine_config &mconfig, device_t &device);
26		public:
27		virtual int  read_sector(UINT32 lba, void *buffer) = 0;
28		virtual int  write_sector(UINT32 lba, const void *buffer) = 0;
29	26
	27	virtual void set_irq(int state);
	28	virtual void set_dmarq(int state);
	29
	30	virtual UINT16 read_dma() = 0;
	31	virtual DECLARE_READ16_MEMBER(read_cs0) = 0;
	32	virtual DECLARE_READ16_MEMBER(read_cs1) = 0;
	33	virtual void write_dma(UINT16 data) = 0;
	34	virtual DECLARE_WRITE16_MEMBER(write_cs0) = 0;
	35	virtual DECLARE_WRITE16_MEMBER(write_cs1) = 0;
	36
30	37	UINT8 *get_features() { return m_features;}
31	38
32	39	UINT16 get_cylinders() { return m_num_cylinders; }
33	40	UINT16 get_sectors() { return m_num_sectors; }
34	41	UINT16 get_heads() { return m_num_heads; }
35		void set_geometry(UINT8 sectors, UINT8 heads) { m_num_sectors= sectors; m_num_heads=heads; }
36		UINT32 lba_address();
37	42	virtual bool is_ready() { return true; }
38	43	virtual void read_key(UINT8 key[]) { }
39		UINT16          cur_cylinder;
40		UINT8           cur_sector;
41		UINT8           cur_head;
42		UINT8           cur_head_reg;
43		UINT32          cur_lba;
44	44
45		UINT8           status;
46		UINT8           error;
47		UINT8           command;
	45	UINT8           m_master_password_enable;
	46	UINT8           m_user_password_enable;
	47	const UINT8 *   m_master_password;
	48	const UINT8 *   m_user_password;
48	49
49		UINT8           buffer[IDE_DISK_SECTOR_SIZE];
50		UINT16          buffer_offset;
	50	UINT8           m_gnetreadlock;
51	51
52		UINT8           adapter_control;
53		UINT8           precomp_offset;
54		UINT16          sector_count;
55		UINT16          block_count;
	52	int m_csel;
	53	int m_dasp;
56	54
57		UINT8           interrupt_pending;
58		UINT16          sectors_until_int;
	55	devcb2_write_line m_irq_handler;
	56	devcb2_write_line m_dmarq_handler;
59	57
60		UINT8           dma_active;
61		UINT8           verify_only;
62
63		UINT8           master_password_enable;
64		UINT8           user_password_enable;
65		const UINT8 *   master_password;
66		const UINT8 *   user_password;
67
68		UINT8           gnetreadlock;
69
70		emu_timer *     last_status_timer;
71		emu_timer *     reset_timer;
72
73	58	protected:
74	59	UINT8           m_features[IDE_DISK_SECTOR_SIZE];
75	60	UINT16          m_num_cylinders;
r23677	r23678
77	62	UINT8           m_num_heads;
78	63	};
79	64
	65	class ide_mass_storage_device : public device_t,
	66	public ide_device_interface
	67	{
	68	public:
	69	ide_mass_storage_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock,const char *shortname = "", const char *source = __FILE__);
	70
	71	virtual int  read_sector(UINT32 lba, void *buffer) = 0;
	72	virtual int  write_sector(UINT32 lba, const void *buffer) = 0;
	73
	74	virtual void set_irq(int state);
	75	virtual UINT16 read_dma();
	76	virtual DECLARE_READ16_MEMBER(read_cs0);
	77	virtual DECLARE_READ16_MEMBER(read_cs1);
	78	virtual void write_dma(UINT16 data);
	79	virtual DECLARE_WRITE16_MEMBER(write_cs0);
	80	virtual DECLARE_WRITE16_MEMBER(write_cs1);
	81
	82	protected:
	83	virtual void device_start();
	84	virtual void device_reset();
	85	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	86
	87	private:
	88	UINT32 lba_address();
	89	void set_geometry(UINT8 sectors, UINT8 heads) { m_num_sectors= sectors; m_num_heads=heads; }
	90	void read_sector_done();
	91	void write_sector_done();
	92	void read_next_sector();
	93	void continue_write();
	94	void signal_delayed_interrupt(attotime time, int buffer_ready);
	95	void next_sector();
	96	void security_error();
	97	void continue_read();
	98	void read_first_sector();
	99	void handle_command(UINT8 _command);
	100	void read_buffer_empty();
	101	void write_buffer_full();
	102
	103	int             m_cur_drive;
	104	UINT16          m_cur_cylinder;
	105	UINT8           m_cur_sector;
	106	UINT8           m_cur_head;
	107	UINT8           m_cur_head_reg;
	108	UINT32          m_cur_lba;
	109
	110	UINT8           m_status;
	111	UINT8           m_error;
	112	UINT8           m_command;
	113
	114	UINT8           m_buffer[IDE_DISK_SECTOR_SIZE];
	115	UINT16          m_buffer_offset;
	116
	117	UINT8           m_adapter_control;
	118	UINT8           m_precomp_offset;
	119	UINT16          m_sector_count;
	120	UINT16          m_block_count;
	121
	122	UINT8           m_interrupt_pending;
	123	UINT16          m_sectors_until_int;
	124
	125	UINT8           m_dma_active;
	126	UINT8           m_verify_only;
	127
	128	emu_timer *     m_last_status_timer;
	129	emu_timer *     m_reset_timer;
	130	};
	131
80	132	// ======================> ide_hdd_device
81	133
82		class ide_hdd_device : public device_t,
83		public ide_device_interface
	134	class ide_hdd_device : public ide_mass_storage_device
84	135	{
85	136	public:
86	137	// construction/destruction
r23677	r23678
92	143	virtual void read_key(UINT8 key[]);
93	144	protected:
94	145	// device-level overrides
95		virtual void device_start();
96	146	virtual void device_reset();
97		virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
98	147
99	148	// optional information overrides
100	149	virtual machine_config_constructor device_mconfig_additions() const;
r23677	r23678
105	154	chd_file       *m_handle;
106	155	hard_disk_file *m_disk;
107	156	};
	157
108	158	// device type definition
109	159	extern const device_type IDE_HARDDISK;

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