trunk/src/mame/drivers/pinball2k.c
| r23662 | r23663 | |
|---|
| 386 | 386 | UINT8 r = 0; |
| 387 | 387 | |
| 388 | 388 | // 0x22, 0x23, Cyrix configuration registers |
| 389 | | if (offset == 0x02) |
| 389 | if (offset == 0x00) |
| 390 | 390 | { |
| 391 | 391 | } |
| 392 | | else if (offset == 0x03) |
| 392 | else if (offset == 0x01) |
| 393 | 393 | { |
| 394 | 394 | r = m_mediagx_config_regs[m_mediagx_config_reg_sel]; |
| 395 | 395 | } |
| 396 | | else |
| 397 | | { |
| 398 | | r = m_pic8259_1->read(space, offset); |
| 399 | | } |
| 400 | 396 | return r; |
| 401 | 397 | } |
| 402 | 398 | |
| 403 | 399 | WRITE8_MEMBER(pinball2k_state::io20_w) |
| 404 | 400 | { |
| 405 | 401 | // 0x22, 0x23, Cyrix configuration registers |
| 406 | | if (offset == 0x02) |
| 402 | if (offset == 0x00) |
| 407 | 403 | { |
| 408 | 404 | m_mediagx_config_reg_sel = data; |
| 409 | 405 | } |
| 410 | | else if (offset == 0x03) |
| 406 | else if (offset == 0x01) |
| 411 | 407 | { |
| 412 | 408 | m_mediagx_config_regs[m_mediagx_config_reg_sel] = data; |
| 413 | 409 | } |
| 414 | | else |
| 415 | | { |
| 416 | | m_pic8259_1->write(space, offset, data); |
| 417 | | } |
| 418 | 410 | } |
| 419 | 411 | |
| 420 | 412 | READ32_MEMBER(pinball2k_state::parallel_port_r) |
| r23662 | r23663 | |
|---|
| 465 | 457 | ADDRESS_MAP_END |
| 466 | 458 | |
| 467 | 459 | static ADDRESS_MAP_START(mediagx_io, AS_IO, 32, pinball2k_state ) |
| 460 | AM_RANGE(0x0020, 0x0023) AM_READWRITE8(io20_r, io20_w, 0xffff0000) |
| 468 | 461 | AM_IMPORT_FROM(pcat32_io_common) |
| 469 | | AM_RANGE(0x0020, 0x003f) AM_READWRITE8(io20_r, io20_w, 0xffffffff) |
| 470 | 462 | AM_RANGE(0x00e8, 0x00eb) AM_NOP // I/O delay port |
| 471 | 463 | AM_RANGE(0x0378, 0x037b) AM_READWRITE(parallel_port_r, parallel_port_w) |
| 472 | 464 | AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write) |
trunk/src/mame/drivers/funkball.c
| r23662 | r23663 | |
|---|
| 247 | 247 | UINT8 r = 0; |
| 248 | 248 | |
| 249 | 249 | // 0x22, 0x23, Cyrix configuration registers |
| 250 | | if (offset == 0x02) |
| 250 | if (offset == 0x00) |
| 251 | 251 | { |
| 252 | 252 | } |
| 253 | | else if (offset == 0x03) |
| 253 | else if (offset == 0x01) |
| 254 | 254 | { |
| 255 | 255 | r = funkball_config_reg_r(); |
| 256 | 256 | } |
| 257 | | else |
| 258 | | { |
| 259 | | r = m_pic8259_1->read(space, offset); |
| 260 | | } |
| 261 | 257 | return r; |
| 262 | 258 | } |
| 263 | 259 | |
| 264 | 260 | WRITE8_MEMBER(funkball_state::io20_w) |
| 265 | 261 | { |
| 266 | 262 | // 0x22, 0x23, Cyrix configuration registers |
| 267 | | if (offset == 0x02) |
| 263 | if (offset == 0x00) |
| 268 | 264 | { |
| 269 | 265 | m_funkball_config_reg_sel = data; |
| 270 | 266 | } |
| 271 | | else if (offset == 0x03) |
| 267 | else if (offset == 0x01) |
| 272 | 268 | { |
| 273 | 269 | funkball_config_reg_w(data); |
| 274 | 270 | } |
| 275 | | else |
| 276 | | { |
| 277 | | m_pic8259_1->write(space, offset, data); |
| 278 | | } |
| 279 | 271 | } |
| 280 | 272 | |
| 281 | 273 | WRITE8_MEMBER( funkball_state::flash_w ) |
| r23662 | r23663 | |
|---|
| 405 | 397 | ADDRESS_MAP_END |
| 406 | 398 | |
| 407 | 399 | static ADDRESS_MAP_START(funkball_io, AS_IO, 32, funkball_state) |
| 400 | AM_RANGE(0x0020, 0x0023) AM_READWRITE8(io20_r, io20_w, 0xffff0000) |
| 408 | 401 | AM_IMPORT_FROM(pcat32_io_common) |
| 409 | | AM_RANGE(0x0020, 0x003f) AM_READWRITE8(io20_r, io20_w, 0xffffffff) |
| 410 | 402 | AM_RANGE(0x00e8, 0x00ef) AM_NOP |
| 411 | 403 | |
| 412 | 404 | // AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) |
trunk/src/mame/drivers/mediagx.c
| r23662 | r23663 | |
|---|
| 482 | 482 | UINT8 r = 0; |
| 483 | 483 | |
| 484 | 484 | // 0x22, 0x23, Cyrix configuration registers |
| 485 | | if (offset == 0x02) |
| 485 | if (offset == 0x00) |
| 486 | 486 | { |
| 487 | 487 | } |
| 488 | | else if (offset == 0x03) |
| 488 | else if (offset == 0x01) |
| 489 | 489 | { |
| 490 | 490 | r = m_mediagx_config_regs[m_mediagx_config_reg_sel]; |
| 491 | 491 | } |
| 492 | | else |
| 493 | | { |
| 494 | | r = m_pic8259_1->read(space, offset); |
| 495 | | } |
| 496 | 492 | return r; |
| 497 | 493 | } |
| 498 | 494 | |
| 499 | 495 | WRITE8_MEMBER(mediagx_state::io20_w) |
| 500 | 496 | { |
| 501 | 497 | // 0x22, 0x23, Cyrix configuration registers |
| 502 | | if (offset == 0x02) |
| 498 | if (offset == 0x00) |
| 503 | 499 | { |
| 504 | 500 | m_mediagx_config_reg_sel = data; |
| 505 | 501 | } |
| 506 | | else if (offset == 0x03) |
| 502 | else if (offset == 0x01) |
| 507 | 503 | { |
| 508 | 504 | m_mediagx_config_regs[m_mediagx_config_reg_sel] = data; |
| 509 | 505 | } |
| 510 | | else |
| 511 | | { |
| 512 | | m_pic8259_1->write(space, offset, data); |
| 513 | | } |
| 514 | 506 | } |
| 515 | 507 | |
| 516 | 508 | READ32_MEMBER(mediagx_state::parallel_port_r) |
| r23662 | r23663 | |
|---|
| 755 | 747 | ADDRESS_MAP_END |
| 756 | 748 | |
| 757 | 749 | static ADDRESS_MAP_START(mediagx_io, AS_IO, 32, mediagx_state ) |
| 750 | AM_RANGE(0x0020, 0x0023) AM_READWRITE8(io20_r, io20_w, 0xffff0000) |
| 758 | 751 | AM_IMPORT_FROM(pcat32_io_common) |
| 759 | | AM_RANGE(0x0020, 0x003f) AM_READWRITE8(io20_r, io20_w, 0xffffffff) |
| 760 | 752 | AM_RANGE(0x00e8, 0x00eb) AM_NOP // I/O delay port |
| 761 | 753 | AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) |
| 762 | 754 | AM_RANGE(0x0378, 0x037b) AM_READWRITE(parallel_port_r, parallel_port_w) |