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r23568 Sunday 9th June, 2013 at 15:44:43 UTC by smf
created a new device for the bus master ide controller, but the implementation is still in the ide controller. (nw)

[src/emu/machine]	idectrl.c idectrl.h
[src/mame/drivers]	chihiro.c seattle.c vegas.c

trunk/src/mame/drivers/chihiro.c

r23567	r23568
410	410	struct chihiro_devices {
411	411	pic8259_device    *pic8259_1;
412	412	pic8259_device    *pic8259_2;
413		ide_controller_device *ide;
	413	bus_master_ide_controller_device *ide;
414	414	} chihiro_devs;
415	415
416	416	nv2a_renderer *nvidia_nv2a;
r23567	r23568
2945	2945	AM_RANGE(0x0020, 0x0023) AM_DEVREADWRITE8("pic8259_1", pic8259_device, read, write, 0xffffffff)
2946	2946	AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("pit8254", pit8254_device, read, write, 0xffffffff)
2947	2947	AM_RANGE(0x00a0, 0x00a3) AM_DEVREADWRITE8("pic8259_2", pic8259_device, read, write, 0xffffffff)
2948		AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
	2948	AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", bus_master_ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
2949	2949	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
2950	2950	AM_RANGE(0x8000, 0x80ff) AM_READWRITE(dummy_r, dummy_w)
2951	2951	AM_RANGE(0xc000, 0xc0ff) AM_READWRITE(smbus_r, smbus_w)
2952		AM_RANGE(0xff60, 0xff67) AM_DEVREADWRITE("ide", ide_controller_device, ide_bus_master32_r, ide_bus_master32_w)
	2952	AM_RANGE(0xff60, 0xff67) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, ide_bus_master32_r, ide_bus_master32_w)
2953	2953	ADDRESS_MAP_END
2954	2954
2955	2955	static INPUT_PORTS_START( chihiro )
r23567	r23568
2967	2967	m_maincpu->set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(chihiro_state::irq_callback),this));
2968	2968	chihiro_devs.pic8259_1 = machine().device<pic8259_device>( "pic8259_1" );
2969	2969	chihiro_devs.pic8259_2 = machine().device<pic8259_device>( "pic8259_2" );
2970		chihiro_devs.ide = machine().device<ide_controller_device>( "ide" );
	2970	chihiro_devs.ide = machine().device<bus_master_ide_controller_device>( "ide" );
2971	2971	if (machine().debug_flags & DEBUG_FLAG_ENABLED)
2972	2972	debug_console_register_command(machine(),"chihiro",CMDFLAG_NONE,0,1,4,chihiro_debug_commands);
2973	2973	}
r23567	r23568
2997	2997	MCFG_PIC8259_ADD( "pic8259_1", WRITELINE(chihiro_state, chihiro_pic8259_1_set_int_line), VCC, READ8(chihiro_state,get_slave_ack) )
2998	2998	MCFG_PIC8259_ADD( "pic8259_2", DEVWRITELINE("pic8259_1", pic8259_device, ir2_w), GND, NULL )
2999	2999	MCFG_PIT8254_ADD( "pit8254", chihiro_pit8254_config )
3000		MCFG_IDE_CONTROLLER_ADD( "ide", ide_baseboard, NULL, "bb", true)
	3000	MCFG_BUS_MASTER_IDE_CONTROLLER_ADD( "ide", ide_baseboard, NULL, "bb", true)
3001	3001	MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
3002		MCFG_IDE_CONTROLLER_BUS_MASTER("maincpu", AS_PROGRAM)
	3002	MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE("maincpu", AS_PROGRAM)
3003	3003
3004	3004	/* video hardware */
3005	3005	MCFG_SCREEN_ADD("screen", RASTER)

trunk/src/mame/drivers/seattle.c

r23567	r23568
518	518	void update_widget_irq();
519	519	void init_common(int ioasic, int serialnum, int yearoffs, int config);
520	520	required_device<cpu_device> m_maincpu;
521		required_device<ide_controller_device> m_ide;
	521	required_device<bus_master_ide_controller_device> m_ide;
522	522	};
523	523
524	524	/*************************************
r23567	r23568
1785	1785	ADDRESS_MAP_UNMAP_HIGH
1786	1786	AM_RANGE(0x00000000, 0x007fffff) AM_RAM AM_SHARE("rambase") // wg3dh only has 4MB; sfrush, blitz99 8MB
1787	1787	AM_RANGE(0x08000000, 0x08ffffff) AM_DEVREAD_LEGACY("voodoo", voodoo_r) AM_WRITE(seattle_voodoo_w)
1788		AM_RANGE(0x0a0001f0, 0x0a0001f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
1789		AM_RANGE(0x0a0003f0, 0x0a0003f7) AM_READ16(seattle_ide_r, 0xffffffff) AM_DEVWRITE16("ide", ide_controller_device, write_cs1_pc, 0xffffffff)
	1788	AM_RANGE(0x0a0001f0, 0x0a0001f7) AM_DEVREADWRITE16("ide", bus_master_ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
	1789	AM_RANGE(0x0a0003f0, 0x0a0003f7) AM_READ16(seattle_ide_r, 0xffffffff) AM_DEVWRITE16("ide", bus_master_ide_controller_device, write_cs1_pc, 0xffffffff)
1790	1790	AM_RANGE(0x0a00040c, 0x0a00040f) AM_NOP                     // IDE-related, but annoying
1791		AM_RANGE(0x0a000f00, 0x0a000f07) AM_DEVREADWRITE("ide", ide_controller_device, ide_bus_master32_r, ide_bus_master32_w)
	1791	AM_RANGE(0x0a000f00, 0x0a000f07) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, ide_bus_master32_r, ide_bus_master32_w)
1792	1792	AM_RANGE(0x0c000000, 0x0c000fff) AM_READWRITE(galileo_r, galileo_w)
1793	1793	AM_RANGE(0x13000000, 0x13000003) AM_WRITE(asic_fifo_w)
1794	1794	AM_RANGE(0x16000000, 0x1600003f) AM_READWRITE_LEGACY(midway_ioasic_r, midway_ioasic_w)
r23567	r23568
2535	2535
2536	2536	MCFG_NVRAM_ADD_1FILL("nvram")
2537	2537
2538		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
	2538	MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
2539	2539	MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(seattle_state, ide_interrupt))
2540		MCFG_IDE_CONTROLLER_BUS_MASTER("maincpu", AS_PROGRAM)
	2540	MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE("maincpu", AS_PROGRAM)
2541	2541
2542	2542	MCFG_3DFX_VOODOO_1_ADD("voodoo", STD_VOODOO_1_CLOCK, voodoo_intf)
2543	2543

trunk/src/mame/drivers/vegas.c

r23567	r23568
1458	1458
1459	1459	static READ32_DEVICE_HANDLER( ide_main_r )
1460	1460	{
1461		ide_controller_device *ide = (ide_controller_device *) device;
	1461	bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1462	1462
1463	1463	UINT32 data = 0;
1464	1464	if (ACCESSING_BITS_0_15)
r23567	r23568
1472	1472
1473	1473	static WRITE32_DEVICE_HANDLER( ide_main_w )
1474	1474	{
1475		ide_controller_device *ide = (ide_controller_device *) device;
	1475	bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1476	1476
1477	1477	if (ACCESSING_BITS_0_15)
1478	1478	ide->write_cs0_pc(space, offset * 2, data, mem_mask);
r23567	r23568
1483	1483
1484	1484	static READ32_DEVICE_HANDLER( ide_alt_r )
1485	1485	{
1486		ide_controller_device *ide = (ide_controller_device *) device;
	1486	bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1487	1487
1488	1488	UINT32 data = 0;
1489	1489	if (ACCESSING_BITS_0_15)
r23567	r23568
1497	1497
1498	1498	static WRITE32_DEVICE_HANDLER( ide_alt_w )
1499	1499	{
1500		ide_controller_device *ide = (ide_controller_device *) device;
	1500	bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1501	1501
1502	1502	if (ACCESSING_BITS_0_15)
1503	1503	ide->write_cs1_pc(space, 6/2 + offset * 2, data, mem_mask);
r23567	r23568
1508	1508
1509	1509	static READ32_DEVICE_HANDLER( ide_bus_master32_r )
1510	1510	{
1511		ide_controller_device *ide = (ide_controller_device *) device;
	1511	bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1512	1512	return ide->ide_bus_master32_r(space, offset, mem_mask);
1513	1513	}
1514	1514
1515	1515
1516	1516	static WRITE32_DEVICE_HANDLER( ide_bus_master32_w )
1517	1517	{
1518		ide_controller_device *ide = (ide_controller_device *) device;
	1518	bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
1519	1519	ide->ide_bus_master32_w(space, offset, data, mem_mask);
1520	1520	}
1521	1521
r23567	r23568
2279	2279
2280	2280	MCFG_M48T37_ADD("timekeeper")
2281	2281
2282		MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
	2282	MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
2283	2283	MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(vegas_state, ide_interrupt))
2284		MCFG_IDE_CONTROLLER_BUS_MASTER("maincpu", AS_PROGRAM)
	2284	MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE("maincpu", AS_PROGRAM)
2285	2285
2286	2286	MCFG_SMC91C94_ADD("ethernet", ethernet_intf)
2287	2287

trunk/src/emu/machine/idectrl.c

r23567	r23568
190	190
191	191	/*************************************
192	192	*
193		*  Convert offset/mem_mask to offset
194		*  and size
195		*
196		*************************************/
197
198		INLINE int convert_to_offset_and_size32(offs_t *offset, UINT32 mem_mask)
199		{
200		int size = 4;
201
202		/* determine which real offset */
203		if (!ACCESSING_BITS_0_7)
204		{
205		(*offset)++, size = 3;
206		if (!ACCESSING_BITS_8_15)
207		{
208		(*offset)++, size = 2;
209		if (!ACCESSING_BITS_16_23)
210		(*offset)++, size = 1;
211		}
212		}
213
214		/* determine the real size */
215		if (ACCESSING_BITS_24_31)
216		return size;
217		size--;
218		if (ACCESSING_BITS_16_23)
219		return size;
220		size--;
221		if (ACCESSING_BITS_8_15)
222		return size;
223		size--;
224		return size;
225		}
226
227
228
229		/*************************************
230		*
231	193	*  Advance to the next sector
232	194	*
233	195	*************************************/
r23567	r23568
1387	1349	*
1388	1350	*************************************/
1389	1351
1390		UINT32 ide_controller_device::ide_bus_master_read(offs_t offset, int size)
	1352	READ32_MEMBER( bus_master_ide_controller_device::ide_bus_master32_r )
1391	1353	{
1392		LOG(("%s:ide_bus_master_read(%d, %d)\n", machine().describe_context(), offset, size));
	1354	LOG(("%s:ide_bus_master32_r(%d, %08x)\n", machine().describe_context(), offset, mem_mask));
1393	1355
1394		/* command register */
1395		if (offset == 0)
	1356	switch( offset )
	1357	{
	1358	case 0:
	1359	/* command register/status register */
1396	1360	return bus_master_command | (bus_master_status << 16);
1397	1361
1398		/* status register */
1399		if (offset == 2)
1400		return bus_master_status;
1401
1402		/* descriptor table register */
1403		if (offset == 4)
	1362	case 1:
	1363	/* descriptor table register */
1404	1364	return bus_master_descriptor;
	1365	}
1405	1366
1406	1367	return 0xffffffff;
1407	1368	}
r23567	r23568
1414	1375	*
1415	1376	*************************************/
1416	1377
1417		void ide_controller_device::ide_bus_master_write(offs_t offset, int size, UINT32 data)
	1378	WRITE32_MEMBER( bus_master_ide_controller_device::ide_bus_master32_w )
1418	1379	{
1419		LOG(("%s:ide_bus_master_write(%d, %d, %08X)\n", machine().describe_context(), offset, size, data));
	1380	LOG(("%s:ide_bus_master32_w(%d, %08x, %08X)\n", machine().describe_context(), offset, mem_mask, data));
1420	1381
1421		/* command register */
1422		if (offset == 0)
	1382	switch( offset )
1423	1383	{
1424		UINT8 old = bus_master_command;
1425		UINT8 val = data & 0xff;
1426
1427		/* save the read/write bit and the start/stop bit */
1428		bus_master_command = (old & 0xf6) | (val & 0x09);
1429		bus_master_status = (bus_master_status & ~IDE_BUSMASTER_STATUS_ACTIVE) | (val & 0x01);
1430
1431		/* handle starting a transfer */
1432		if (!(old & 1) && (val & 1))
	1384	case 0:
	1385	if( ACCESSING_BITS_0_7 )
1433	1386	{
1434		/* reset all the DMA data */
1435		dma_bytes_left = 0;
1436		dma_last_buffer = 0;
1437		dma_descriptor = bus_master_descriptor;
	1387	/* command register */
	1388	UINT8 old = bus_master_command;
	1389	UINT8 val = data & 0xff;
1438	1390
1439		/* if we're going live, start the pending read/write */
1440		if (dma_active)
	1391	/* save the read/write bit and the start/stop bit */
	1392	bus_master_command = (old & 0xf6) | (val & 0x09);
	1393	bus_master_status = (bus_master_status & ~IDE_BUSMASTER_STATUS_ACTIVE) | (val & 0x01);
	1394
	1395	/* handle starting a transfer */
	1396	if (!(old & 1) && (val & 1))
1441	1397	{
1442		if (bus_master_command & 8)
1443		read_next_sector();
1444		else
	1398	/* reset all the DMA data */
	1399	dma_bytes_left = 0;
	1400	dma_last_buffer = 0;
	1401	dma_descriptor = bus_master_descriptor;
	1402
	1403	/* if we're going live, start the pending read/write */
	1404	if (dma_active)
1445	1405	{
1446		read_buffer_from_dma();
1447		continue_write();
	1406	if (bus_master_command & 8)
	1407	read_next_sector();
	1408	else
	1409	{
	1410	read_buffer_from_dma();
	1411	continue_write();
	1412	}
1448	1413	}
1449	1414	}
1450	1415	}
1451		}
1452	1416
1453		/* status register */
1454		if (offset <= 2 && offset + size > 2)
1455		{
1456		UINT8 old = bus_master_status;
1457		UINT8 val = data >> (8 * (2 - offset));
	1417	if( ACCESSING_BITS_16_23 )
	1418	{
	1419	/* status register */
	1420	UINT8 old = bus_master_status;
	1421	UINT8 val = (data >> 16) & 0xff;
1458	1422
1459		/* save the DMA capable bits */
1460		bus_master_status = (old & 0x9f) | (val & 0x60);
	1423	/* save the DMA capable bits */
	1424	bus_master_status = (old & 0x9f) | (val & 0x60);
1461	1425
1462		/* clear interrupt and error bits */
1463		if (val & IDE_BUSMASTER_STATUS_IRQ)
1464		bus_master_status &= ~IDE_BUSMASTER_STATUS_IRQ;
1465		if (val & IDE_BUSMASTER_STATUS_ERROR)
1466		bus_master_status &= ~IDE_BUSMASTER_STATUS_ERROR;
1467		}
	1426	/* clear interrupt and error bits */
	1427	if (val & IDE_BUSMASTER_STATUS_IRQ)
	1428	bus_master_status &= ~IDE_BUSMASTER_STATUS_IRQ;
	1429	if (val & IDE_BUSMASTER_STATUS_ERROR)
	1430	bus_master_status &= ~IDE_BUSMASTER_STATUS_ERROR;
	1431	}
	1432	break;
1468	1433
1469		/* descriptor table register */
1470		if (offset == 4)
	1434	case 1:
	1435	/* descriptor table register */
1471	1436	bus_master_descriptor = data & 0xfffffffc;
	1437	break;
	1438	}
1472	1439	}
1473	1440
1474		READ32_MEMBER( ide_controller_device::ide_bus_master32_r )
1475		{
1476		int size;
1477	1441
1478		offset *= 4;
1479		size = convert_to_offset_and_size32(&offset, mem_mask);
1480
1481		return ide_bus_master_read(offset, size) << ((offset & 3) * 8);
1482		}
1483
1484
1485		WRITE32_MEMBER( ide_controller_device::ide_bus_master32_w )
1486		{
1487		int size;
1488
1489		offset *= 4;
1490		size = convert_to_offset_and_size32(&offset, mem_mask);
1491
1492		ide_bus_master_write(offset, size, data >> ((offset & 3) * 8));
1493		}
1494
1495
1496	1442	SLOT_INTERFACE_START(ide_devices)
1497	1443	SLOT_INTERFACE("hdd", IDE_HARDDISK)
1498	1444	SLOT_INTERFACE_END
1499	1445
1500		const device_type IDE_CONTROLLER = &device_creator<ide_controller_device>;
1501
1502		ide_controller_device::ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
1503		device_t(mconfig, IDE_CONTROLLER, "IDE Controller", tag, owner, clock),
	1446	ide_controller_device::ide_controller_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) :
	1447	device_t(mconfig, type, name, tag, owner, clock),
1504	1448	status(0),
	1449	bmcpu(NULL),
	1450	bmspace(0),
	1451	dma_space(NULL),
	1452	dma_active(0),
	1453	dma_address_xor(0),
	1454	dma_last_buffer(0),
	1455	dma_address(0),
	1456	dma_descriptor(0),
	1457	dma_bytes_left(0),
	1458	bus_master_command(0),
	1459	bus_master_status(0),
	1460	bus_master_descriptor(0),
1505	1461	adapter_control(0),
1506	1462	error(0),
1507	1463	command(0),
r23567	r23568
1512	1468	block_count(0),
1513	1469	sectors_until_int(0),
1514	1470	verify_only(0),
1515		dma_active(0),
	1471	config_unknown(0),
	1472	config_register_num(0),
	1473	master_password_enable(0),
	1474	user_password_enable(0),
	1475	master_password(NULL),
	1476	user_password(NULL),
	1477	gnetreadlock(0),
	1478	cur_drive(0),
	1479	m_irq_handler(*this)
	1480	{
	1481	}
	1482
	1483
	1484	const device_type IDE_CONTROLLER = &device_creator<ide_controller_device>;
	1485
	1486	ide_controller_device::ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	1487	device_t(mconfig, IDE_CONTROLLER, "IDE Controller", tag, owner, clock),
	1488	bmcpu(NULL),
	1489	bmspace(0),
1516	1490	dma_space(NULL),
	1491	dma_active(0),
1517	1492	dma_address_xor(0),
1518	1493	dma_last_buffer(0),
1519	1494	dma_address(0),
r23567	r23568
1522	1497	bus_master_command(0),
1523	1498	bus_master_status(0),
1524	1499	bus_master_descriptor(0),
	1500	adapter_control(0),
	1501	error(0),
	1502	command(0),
	1503	interrupt_pending(0),
	1504	precomp_offset(0),
	1505	buffer_offset(0),
	1506	sector_count(0),
	1507	block_count(0),
	1508	sectors_until_int(0),
	1509	verify_only(0),
1525	1510	config_unknown(0),
1526	1511	config_register_num(0),
1527	1512	master_password_enable(0),
r23567	r23568
1530	1515	user_password(NULL),
1531	1516	gnetreadlock(0),
1532	1517	cur_drive(0),
1533		m_irq_handler(*this),
1534		bmcpu(NULL),
1535		bmspace(0)
	1518	m_irq_handler(*this)
1536	1519	{
1537	1520	}
1538	1521
	1522	const device_type BUS_MASTER_IDE_CONTROLLER = &device_creator<bus_master_ide_controller_device>;
	1523
	1524	bus_master_ide_controller_device::bus_master_ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	1525	ide_controller_device(mconfig, BUS_MASTER_IDE_CONTROLLER, "Bus Master IDE Controller", tag, owner, clock)
	1526	{
	1527	}
	1528
1539	1529	//-------------------------------------------------
1540	1530	//  device_start - device-specific startup
1541	1531	//-------------------------------------------------

trunk/src/emu/machine/idectrl.h

r23567	r23568
49	49	#define MCFG_IDE_CONTROLLER_IRQ_HANDLER(_devcb) \
50	50	devcb = &ide_controller_device::set_irq_handler(*device, DEVCB2_##_devcb);
51	51
52		#define MCFG_IDE_CONTROLLER_BUS_MASTER(bmcpu, bmspace) \
53		ide_controller_device::set_bus_master(*device, bmcpu, bmspace);
54
55	52	SLOT_INTERFACE_EXTERN(ide_devices);
56	53	SLOT_INTERFACE_EXTERN(ide_devices);
57	54
r23567	r23568
80	77	{
81	78	public:
82	79	ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	80	ide_controller_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
83	81
84	82	// static configuration helpers
85	83	template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<ide_controller_device &>(device).m_irq_handler.set_callback(object); }
86		static void set_bus_master(device_t &device, const char *bmcpu, UINT32 bmspace) {ide_controller_device &ide = downcast<ide_controller_device &>(device); ide.bmcpu = bmcpu; ide.bmspace = bmspace; }
87	84
88	85	UINT8 *ide_get_features(int drive);
89	86	void ide_set_gnet_readlock(const UINT8 onoff);
r23567	r23568
102	99	DECLARE_WRITE16_MEMBER(write_cs0_pc);
103	100	DECLARE_WRITE16_MEMBER(write_cs1_pc);
104	101
105		DECLARE_READ32_MEMBER( ide_bus_master32_r );
106		DECLARE_WRITE32_MEMBER( ide_bus_master32_w );
107
108		UINT32 ide_bus_master_read(offs_t offset, int size);
109		void ide_bus_master_write(offs_t offset, int size, UINT32 data);
110	102	void signal_interrupt();
111	103	void clear_interrupt();
112	104	void read_sector_done();
r23567	r23568
119	111	virtual void device_start();
120	112	virtual void device_reset();
121	113
	114	const char *bmcpu;
	115	UINT32 bmspace;
	116	address_space * dma_space;
	117	UINT8           dma_active;
	118	UINT8           dma_address_xor;
	119	UINT8           dma_last_buffer;
	120	offs_t          dma_address;
	121	offs_t          dma_descriptor;
	122	UINT32          dma_bytes_left;
	123	UINT8           bus_master_command;
	124	UINT8           bus_master_status;
	125	UINT32          bus_master_descriptor;
	126
	127	void read_next_sector();
	128	void read_buffer_from_dma();
	129	void continue_write();
	130
122	131	private:
123	132	void signal_delayed_interrupt(attotime time, int buffer_ready);
124	133	void next_sector();
r23567	r23568
126	135	void continue_read();
127	136	void write_buffer_to_dma();
128	137	void read_first_sector();
129		void read_next_sector();
130		void read_buffer_from_dma();
131	138	void handle_command(UINT8 _command);
132		void continue_write();
133	139
134	140	UINT8           adapter_control;
135	141	UINT8           error;
r23567	r23568
145	151	UINT16          sectors_until_int;
146	152	UINT8           verify_only;
147	153
148		UINT8           dma_active;
149		address_space *dma_space;
150		UINT8           dma_address_xor;
151		UINT8           dma_last_buffer;
152		offs_t          dma_address;
153		offs_t          dma_descriptor;
154		UINT32          dma_bytes_left;
155
156		UINT8           bus_master_command;
157		UINT8           bus_master_status;
158		UINT32          bus_master_descriptor;
159
160	154	UINT8           config_unknown;
161	155	UINT8           config_register[IDE_CONFIG_REGISTERS];
162	156	UINT8           config_register_num;
r23567	r23568
175	169	ide_slot_device *slot[2];
176	170
177	171	devcb2_write_line m_irq_handler;
178		const char *bmcpu;
179		UINT32 bmspace;
180	172	};
181	173
182	174	extern const device_type IDE_CONTROLLER;
183	175
	176
	177	#define MCFG_BUS_MASTER_IDE_CONTROLLER_ADD(_tag, _slotintf, _master, _slave, _fixed) \
	178	MCFG_IDE_SLOT_ADD("drive_0", _slotintf, _master, _fixed) \
	179	MCFG_IDE_SLOT_ADD("drive_1", _slotintf, _slave, _fixed) \
	180	MCFG_DEVICE_ADD(_tag, BUS_MASTER_IDE_CONTROLLER, 0)
	181
	182	#define MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(bmcpu, bmspace) \
	183	bus_master_ide_controller_device::set_bus_master_space(*device, bmcpu, bmspace);
	184
	185	class bus_master_ide_controller_device : public ide_controller_device
	186	{
	187	public:
	188	bus_master_ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	189	static void set_bus_master_space(device_t &device, const char *bmcpu, UINT32 bmspace) {bus_master_ide_controller_device &ide = downcast<bus_master_ide_controller_device &>(device); ide.bmcpu = bmcpu; ide.bmspace = bmspace; }
	190
	191	DECLARE_READ32_MEMBER( ide_bus_master32_r );
	192	DECLARE_WRITE32_MEMBER( ide_bus_master32_w );
	193	};
	194
	195	extern const device_type BUS_MASTER_IDE_CONTROLLER;
	196
184	197	#endif  /* __IDECTRL_H__ */

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