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r23566 Sunday 9th June, 2013 at 13:22:00 UTC by Michael Zapf
(MESS) ti99: Make debugger happier. Also, removed some unneeded
variables. (nw)
[src/mess/machine/ti99]datamux.c datamux.h grom.c videowrp.c videowrp.h

trunk/src/mess/machine/ti99/videowrp.h
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2323   virtual void    reset_vdp(int state) =0;
2424
2525protected:
26   address_space   *m_space;
2726   tms9928a_device *m_tms9928a;
2827
2928   /* Constructor */
trunk/src/mess/machine/ti99/datamux.c
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8484    DEVICE ACCESSOR FUNCTIONS
8585***************************************************************************/
8686
87void ti99_datamux_device::read_all(address_space& space, UINT16 addr, UINT8 *target)
88{
89   attached_device *dev = m_devices.first();
90
91   // Reading the odd address first (addr+1)
92   while (dev != NULL)
93   {
94      if (dev->m_config->write_select != 0xffff) // write-only
95      {
96         if ((addr & dev->m_config->address_mask)==dev->m_config->select)
97         {
98            // Cast to the bus8z_device (see ti99defs.h)
99            bus8z_device *devz = static_cast<bus8z_device *>(dev->m_device);
100            devz->readz(space, addr, target);
101         }
102         // hope we don't have two devices answering...
103         // consider something like a logical OR and maybe some artificial smoke
104      }
105      dev = dev->m_next;
106   }
107}
108
109void ti99_datamux_device::write_all(address_space& space, UINT16 addr, UINT8 value)
110{
111   attached_device *dev = m_devices.first();
112   while (dev != NULL)
113   {
114      if ((addr & dev->m_config->address_mask)==(dev->m_config->select | dev->m_config->write_select))
115      {
116         bus8z_device *devz = static_cast<bus8z_device *>(dev->m_device);
117         devz->write(space, addr, value);
118      }
119      dev = dev->m_next;
120   }
121}
122
87123/*
88124    Read access. We are using two loops because the delay between both
89125    accesses must not occur within the loop. So we have one access on the bus,
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97133   UINT8 hbyte = 0;
98134   UINT16 addr = (offset << 1);
99135
100   assert (mem_mask == 0xffff);
101
102136   // Looks ugly, but this is close to the real thing. If the 16bit
103137   // memory expansion is installed in the console, and the access hits its
104138   // space, just respond to the memory access and don't bother the
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113147      if (base != 0)
114148      {
115149         UINT16 reply = m_ram16b[offset-base];
116         return reply;
150         return reply & mem_mask;
117151      }
118152   }
119153
120   attached_device *dev = m_devices.first();
154   // Read the odd address into the latch
155   read_all(space, addr+1, &m_latch);
121156
122   // Reading the odd address first (addr+1)
123   while (dev != NULL)
124   {
125      if (((addr+1) & dev->m_config->address_mask)==dev->m_config->select)
126      {
127         // Cast to the bus8z_device (see ti99defs.h)
128         bus8z_device *devz = static_cast<bus8z_device *>(dev->m_device);
129         devz->readz(*m_space, addr+1, &m_latch);
130      }
131      // hope we don't have two devices answering...
132      // consider something like a logical OR and maybe some artificial smoke
133      dev = dev->m_next;
134   }
135
136   dev = m_devices.first();
137
138157   // Reading the even address now (addr)
139   while (dev != NULL)
140   {
141      if (dev->m_config->write_select != 0xffff) // write-only
142      {
143         if ((addr & dev->m_config->address_mask)==dev->m_config->select)
144         {
145            bus8z_device *devz = static_cast<bus8z_device *>(dev->m_device);
146            devz->readz(*m_space, addr, &hbyte);
147         }
148      }
149      dev = dev->m_next;
150   }
158   read_all(space, addr, &hbyte);
151159
152160   // Insert four wait states and let CPU enter wait state
153161   // The counter in the real console is implemented by a shift register
154162   // that is triggered on a memory access
163
164   // We cannot split the wait states between the read accesses before we
165   // have a split-phase read access in the core
155166   m_waitcount = 6;
156167   m_ready(CLEAR_LINE);
157168
158169   // use the latch and the currently read byte and put it on the 16bit bus
159   return (hbyte<<8) | m_latch;
170   return ((hbyte<<8) | m_latch) & mem_mask;
160171}
161172
162173/*
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173184
174185//  printf("write addr=%04x, value=%04x\n", addr, data);
175186
176   assert (mem_mask == 0xffff);
177
178187   // Handle the internal 32K expansion
179188   if (m_use32k)
180189   {
181      if (addr>=0x2000 && addr<0x4000)
190      UINT16 base = 0;
191      if ((addr & 0xe000)==0x2000) base = 0x1000;
192      if (((addr & 0xe000)==0xa000) || ((addr & 0xc000)==0xc000)) base = 0x4000;
193
194      if (base != 0)
182195      {
183         m_ram16b[offset-0x1000] = data; // index 0000 - 0fff
196         m_ram16b[offset-base] = data;
184197         return;
185198      }
186      if (addr>=0xa000)
187      {
188         m_ram16b[offset-0x4000] = data; // index 1000 - 4fff
189         return;
190      }
191199   }
192200
193   attached_device *dev = m_devices.first();
194   while (dev != NULL)
195   {
196      if (((addr+1) & dev->m_config->address_mask)==(dev->m_config->select | dev->m_config->write_select))
197      {
198         bus8z_device *devz = static_cast<bus8z_device *>(dev->m_device);
199         devz->write(*m_space, addr+1, data & 0xff);
200      }
201      dev = dev->m_next;
202   }
201   // write odd byte
202   write_all(space, addr+1, data & 0xff);
203   // write even byte
204   write_all(space, addr, (data>>8) & 0xff);
203205
204   dev = m_devices.first();
205
206   while (dev != NULL)
207   {
208      if ((addr & dev->m_config->address_mask)==(dev->m_config->select | dev->m_config->write_select))
209      {
210         // write the byte from the upper 8 lines
211         bus8z_device *devz = static_cast<bus8z_device *>(dev->m_device);
212         devz->write(*m_space, addr, (data>>8) & 0xff);
213      }
214      dev = dev->m_next;
215   }
216
217206   // Insert four wait states and let CPU enter wait state
218207   m_waitcount = 6;
219208   m_ready(CLEAR_LINE);
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254243   m_ready.resolve(conf->ready, *this);
255244
256245   m_cpu = machine().device("maincpu");
257   m_space = &m_cpu->memory().space(AS_PROGRAM);
246   // m_space = &m_cpu->memory().space(AS_PROGRAM);
258247
259248   m_devices.reset(); // clear the list
260249   m_use32k = (ioport("RAM")->read()==1);
trunk/src/mess/machine/ti99/grom.c
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103103*/
104104READ8Z_MEMBER( ti99_grom_device::readz )
105105{
106   // Prevent debugger access
107   if (space.debugger_access()) return;
108
106109   if (offset & 2)
107110   {
108111      // GROMs generally answer the address read request
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163166*/
164167WRITE8_MEMBER( ti99_grom_device::write )
165168{
169   // Prevent debugger access
170   if (space.debugger_access()) return;
171
166172   if (offset & 2)
167173   {
168174      /* write GROM address */
trunk/src/mess/machine/ti99/datamux.h
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8181   virtual ioport_constructor device_input_ports() const;
8282
8383private:
84   // Common read routine
85   void read_all(address_space& space, UINT16 addr, UINT8 *target);
86
87   // Common write routine
88   void write_all(address_space& space, UINT16 addr, UINT8 value);
89
8490   // Ready line to the CPU
8591   devcb_resolved_write_line m_ready;
8692
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101107
102108   /* Reference to the CPU; avoid lookups. */
103109   device_t *m_cpu;
104
105   /* Reference to the address space, maybe unnecessary. */
106   address_space   *m_space;
107110};
108111
109112/******************************************************************************/
trunk/src/mess/machine/ti99/videowrp.c
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4848{
4949   if (offset & 2)
5050   {       /* read VDP status */
51      *value = m_tms9928a->register_read(*(this->m_space), 0);
51      *value = m_tms9928a->register_read(space, 0);
5252   }
5353   else
5454   {       /* read VDP RAM */
55      *value = m_tms9928a->vram_read(*(this->m_space), 0);
55      *value = m_tms9928a->vram_read(space, 0);
5656   }
5757}
5858
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6060{
6161   if (offset & 2)
6262   {   /* write VDP address */
63      m_tms9928a->register_write(*(this->m_space), 0, data);
63      m_tms9928a->register_write(space, 0, data);
6464   }
6565   else
6666   {   /* write VDP data */
67      m_tms9928a->vram_write(*(this->m_space), 0, data);
67      m_tms9928a->vram_write(space, 0, data);
6868   }
6969}
7070

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