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r23541 Saturday 8th June, 2013 at 15:42:11 UTC by smf
First pass at tidying up ide interface. It no longer tries to force everything to act as a PC. A copy of the VIA VT83C461 datasheet would be useful to remove some of the hacks added to make the games using it work again. [smf]
[src/emu/machine]ataflash.c idectrl.c idectrl.h rf5c296.c
[src/mame/drivers]calchase.c chihiro.c cobra.c djmain.c fruitpc.c funkball.c gamecstl.c jaguar.c kinst.c mediagx.c midqslvr.c midvunit.c photoply.c qdrmfgp.c quakeat.c queen.c savquest.c seattle.c taitotz.c twinkle.c vegas.c viper.c voyager.c zn.c
[src/mame/includes]djmain.h jaguar.h qdrmfgp.h
[src/mame/machine]midwayic.c midwayic.h
[src/mess/drivers]bebox.c
[src/mess/includes]bebox.h
[src/mess/machine]a2cffa.c a2vulcan.c a2zipdrive.c adam_ide.c bebox.c c64_ide64.c isa_ide.c isa_ide.h isa_ide8.c kc_d004.c
[src/mess/machine/ti99]tn_ide.c

trunk/src/mame/drivers/funkball.c
r23540r23541
125125   DECLARE_READ32_MEMBER(biu_ctrl_r);
126126   DECLARE_WRITE32_MEMBER(biu_ctrl_w);
127127   DECLARE_WRITE8_MEMBER(bios_ram_w);
128   DECLARE_READ32_MEMBER(ide_r);
129   DECLARE_WRITE32_MEMBER(ide_w);
130128   DECLARE_READ32_MEMBER(fdc_r);
131129   DECLARE_WRITE32_MEMBER(fdc_w);
132130   DECLARE_READ8_MEMBER(io20_r);
r23540r23541
212210   COMBINE_DATA(state->m_cx5510_regs + (reg/4));
213211}
214212
215#if 0
216READ32_MEMBER(funkball_state::ide_r)
217{
218   return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
219}
220
221WRITE32_MEMBER(funkball_state::ide_w)
222{
223   m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
224}
225
226READ32_MEMBER(funkball_state::fdc_r)
227{
228   return m-ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
229}
230
231WRITE32_MEMBER(funkball_state::fdc_w)
232{
233   //mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
234   m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
235}
236#endif
237
238213READ8_MEMBER( funkball_state::fdc_r )
239214{
240215   //printf("%02x\n",offset);
r23540r23541
434409   AM_RANGE(0x0020, 0x003f) AM_READWRITE8(io20_r, io20_w, 0xffffffff)
435410   AM_RANGE(0x00e8, 0x00ef) AM_NOP
436411
437//  AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w)
438//  AM_RANGE(0x03f0, 0x03ff) AM_READWRITE(fdc_r, fdc_w)
412//  AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
413//  AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
439414   AM_RANGE(0x03f0, 0x03ff) AM_READWRITE8(fdc_r,fdc_w,0xffffffff)
440415
441416   AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
trunk/src/mame/drivers/seattle.c
r23540r23541
482482   DECLARE_WRITE32_MEMBER(ethernet_w);
483483   DECLARE_READ32_MEMBER(widget_r);
484484   DECLARE_WRITE32_MEMBER(widget_w);
485   DECLARE_READ32_MEMBER(seattle_ide_r);
485   DECLARE_READ16_MEMBER(seattle_ide_r);
486486   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
487487   DECLARE_WRITE_LINE_MEMBER(vblank_assert);
488488   DECLARE_WRITE_LINE_MEMBER(voodoo_stall);
r23540r23541
17731773
17741774*/
17751775
1776READ32_MEMBER(seattle_state::seattle_ide_r)
1776READ16_MEMBER(seattle_state::seattle_ide_r)
17771777{
17781778   /* note that blitz times out if we don't have this cycle stealing */
1779   if (offset == 0x3f6/4)
1779   if (offset == 6/2)
17801780      m_maincpu->eat_cycles(100);
1781   return m_ide->ide_controller32_r(space, offset, mem_mask);
1781   return m_ide->read_cs1_pc(space, offset, mem_mask);
17821782}
17831783
17841784static ADDRESS_MAP_START( seattle_map, AS_PROGRAM, 32, seattle_state )
17851785   ADDRESS_MAP_UNMAP_HIGH
17861786   AM_RANGE(0x00000000, 0x007fffff) AM_RAM AM_SHARE("rambase") // wg3dh only has 4MB; sfrush, blitz99 8MB
17871787   AM_RANGE(0x08000000, 0x08ffffff) AM_DEVREAD_LEGACY("voodoo", voodoo_r) AM_WRITE(seattle_voodoo_w)
1788   AM_RANGE(0x0a000000, 0x0a0003ff) AM_READ(seattle_ide_r) AM_DEVWRITE("ide", ide_controller_device, ide_controller32_w)
1788   AM_RANGE(0x0a0001f0, 0x0a0001f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
1789   AM_RANGE(0x0a0003f0, 0x0a0003f7) AM_READ16(seattle_ide_r, 0xffffffff) AM_DEVWRITE16("ide", ide_controller_device, write_cs1_pc, 0xffffffff)
17891790   AM_RANGE(0x0a00040c, 0x0a00040f) AM_NOP                     // IDE-related, but annoying
17901791   AM_RANGE(0x0a000f00, 0x0a000f07) AM_DEVREADWRITE("ide", ide_controller_device, ide_bus_master32_r, ide_bus_master32_w)
17911792   AM_RANGE(0x0c000000, 0x0c000fff) AM_READWRITE(galileo_r, galileo_w)
trunk/src/mame/drivers/gamecstl.c
r23540r23541
7575public:
7676   gamecstl_state(const machine_config &mconfig, device_type type, const char *tag)
7777      : pcat_base_state(mconfig, type, tag),
78      m_ide(*this, "ide"),
7978      m_cga_ram(*this, "cga_ram") { }
8079
81   required_device<ide_controller_device> m_ide;
8280   required_shared_ptr<UINT32> m_cga_ram;
8381   UINT32 *m_bios_ram;
8482   UINT8 m_mxtc_config_reg[256];
r23540r23541
8785   DECLARE_WRITE32_MEMBER(pnp_config_w);
8886   DECLARE_WRITE32_MEMBER(pnp_data_w);
8987   DECLARE_WRITE32_MEMBER(bios_ram_w);
90   DECLARE_READ32_MEMBER(ide_r);
91   DECLARE_WRITE32_MEMBER(ide_w);
92   DECLARE_READ32_MEMBER(fdc_r);
93   DECLARE_WRITE32_MEMBER(fdc_w);
9488   DECLARE_DRIVER_INIT(gamecstl);
9589   virtual void machine_start();
9690   virtual void machine_reset();
r23540r23541
326320
327321
328322
329READ32_MEMBER(gamecstl_state::ide_r)
330{
331   return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
332}
333
334WRITE32_MEMBER(gamecstl_state::ide_w)
335{
336   m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
337}
338
339READ32_MEMBER(gamecstl_state::fdc_r)
340{
341   return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
342}
343
344WRITE32_MEMBER(gamecstl_state::fdc_w)
345{
346   //mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
347   m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
348}
349
350
351
352323WRITE32_MEMBER(gamecstl_state::bios_ram_w)
353324{
354325   if (m_mxtc_config_reg[0x59] & 0x20)     // write to RAM if this region is write-enabled
r23540r23541
374345   AM_IMPORT_FROM(pcat32_io_common)
375346   AM_RANGE(0x00e8, 0x00eb) AM_NOP
376347   AM_RANGE(0x00ec, 0x00ef) AM_NOP
377   AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w)
348   AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
378349   AM_RANGE(0x0300, 0x03af) AM_NOP
379350   AM_RANGE(0x03b0, 0x03df) AM_NOP
380351   AM_RANGE(0x0278, 0x027b) AM_WRITE(pnp_config_w)
381   AM_RANGE(0x03f0, 0x03ff) AM_READWRITE(fdc_r, fdc_w)
352   AM_RANGE(0x03f0, 0x03ff) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
382353   AM_RANGE(0x0a78, 0x0a7b) AM_WRITE(pnp_data_w)
383354   AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
384355ADDRESS_MAP_END
trunk/src/mame/drivers/jaguar.c
r23540r23541
10771077   AM_RANGE(0xf1d000, 0xf1dfff) AM_READWRITE(wave_rom_r16, wave_rom_w16 )
10781078ADDRESS_MAP_END
10791079
1080/// hack for 32 big endian bus talking to 16 bit little endian ide
1081READ32_MEMBER(jaguar_state::vt83c461_r)
1082{
1083   UINT32 data = 0;
10801084
1085   if(offset >= 0x30/4 && offset < 0x40/4)
1086   {
1087      if (ACCESSING_BITS_0_7)
1088         data = m_ide->read_via_config(space, (offset * 4) & 0xf, mem_mask);
1089   }
1090   else if( offset >= 0x1f0/4 && offset < 0x1f8/4 )
1091   {
1092      if (ACCESSING_BITS_0_15)
1093         data |= m_ide->read_cs0_pc(space, (offset * 2) & 7, mem_mask);
1094      if (ACCESSING_BITS_16_31)
1095         data |= m_ide->read_cs0_pc(space, ((offset * 2) & 7) + 1, mem_mask >> 16) << 16;
1096   }
1097   else if( offset >= 0x3f0/4 && offset < 0x3f8/4 )
1098   {
1099      if (ACCESSING_BITS_0_15)
1100         data |= m_ide->read_cs1_pc(space, (offset * 2) & 7, mem_mask);
1101      if (ACCESSING_BITS_16_31)
1102         data |= m_ide->read_cs1_pc(space, ((offset * 2) & 7) + 1, mem_mask >> 16) << 16;
1103   }
10811104
1105   return data;
1106}
1107
1108WRITE32_MEMBER(jaguar_state::vt83c461_w)
1109{
1110   if(offset >= 0x30/4 && offset < 0x40/4)
1111   {
1112      if (ACCESSING_BITS_0_7)
1113         m_ide->write_via_config(space, (offset * 4) & 0xf, data, mem_mask);
1114   }
1115   else if( offset >= 0x1f0/4 && offset < 0x1f8/4 )
1116   {
1117      if (ACCESSING_BITS_0_15)
1118         m_ide->write_cs0_pc(space, (offset * 2) & 7, data, mem_mask);
1119      if (ACCESSING_BITS_16_31)
1120         m_ide->write_cs0_pc(space, ((offset * 2) & 7) + 1, data >> 16, mem_mask >> 16);
1121   }
1122   else if( offset >= 0x3f0/4 && offset < 0x3f8/4 )
1123   {
1124      if (ACCESSING_BITS_0_15)
1125         m_ide->write_cs1_pc(space, (offset * 2) & 7, data, mem_mask);
1126      if (ACCESSING_BITS_16_31)
1127         m_ide->write_cs1_pc(space, ((offset * 2) & 7) + 1, data >> 16, mem_mask >> 16);
1128   }
1129}
1130
1131
1132
10821133/*************************************
10831134 *
10841135 *  Main CPU memory handlers
r23540r23541
10891140   AM_RANGE(0x04000000, 0x047fffff) AM_RAM AM_SHARE("sharedram")
10901141   AM_RANGE(0x04800000, 0x04bfffff) AM_ROMBANK("maingfxbank")
10911142   AM_RANGE(0x04c00000, 0x04dfffff) AM_ROMBANK("mainsndbank")
1092   AM_RANGE(0x04e00000, 0x04e003ff) AM_DEVREADWRITE("ide", ide_controller_device, ide_controller32_r, ide_controller32_w)
1143   AM_RANGE(0x04e00000, 0x04e003ff) AM_READWRITE(vt83c461_r, vt83c461_w)
10931144   AM_RANGE(0x04f00000, 0x04f003ff) AM_READWRITE16(tom_regs_r, tom_regs_w, 0xffffffff)
10941145   AM_RANGE(0x04f00400, 0x04f007ff) AM_RAM AM_SHARE("gpuclut")
10951146   AM_RANGE(0x04f02100, 0x04f021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w)
r23540r23541
11231174   AM_RANGE(0xa40000, 0xa40003) AM_WRITE(eeprom_enable_w)
11241175   AM_RANGE(0xb70000, 0xb70003) AM_READWRITE(misc_control_r, misc_control_w)
11251176   AM_RANGE(0xc00000, 0xdfffff) AM_ROMBANK("mainsndbank")
1126   AM_RANGE(0xe00000, 0xe003ff) AM_DEVREADWRITE("ide",  ide_controller_device, ide_controller32_r, ide_controller32_w)
1177   AM_RANGE(0xe00000, 0xe003ff) AM_READWRITE(vt83c461_r, vt83c461_w)
11271178   AM_RANGE(0xf00000, 0xf003ff) AM_READWRITE16(tom_regs_r, tom_regs_w, 0xffffffff)
11281179   AM_RANGE(0xf00400, 0xf007ff) AM_RAM AM_SHARE("gpuclut")
11291180   AM_RANGE(0xf02100, 0xf021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w)
r23540r23541
11511202   AM_RANGE(0x000000, 0x7fffff) AM_RAM AM_SHARE("sharedram")
11521203   AM_RANGE(0x800000, 0xbfffff) AM_ROMBANK("gpugfxbank")
11531204   AM_RANGE(0xc00000, 0xdfffff) AM_ROMBANK("dspsndbank")
1154   AM_RANGE(0xe00000, 0xe003ff) AM_DEVREADWRITE("ide", ide_controller_device, ide_controller32_r, ide_controller32_w)
1205   AM_RANGE(0xe00000, 0xe003ff) AM_READWRITE(vt83c461_r, vt83c461_w)
11551206   AM_RANGE(0xf00000, 0xf003ff) AM_READWRITE16(tom_regs_r, tom_regs_w, 0xffffffff)
11561207   AM_RANGE(0xf00400, 0xf007ff) AM_RAM AM_SHARE("gpuclut")
11571208   AM_RANGE(0xf02100, 0xf021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w)
trunk/src/mame/drivers/viper.c
r23540r23541
12661266      {
12671267         case 0x8:   // Duplicate Even RD Data
12681268         {
1269            r |= m_ide->ide_bus_r(0, 0) << 16;
1269            r |= m_ide->read_cs0(space, 0, mem_mask >> 16) << 16;
12701270            break;
12711271         }
12721272
r23540r23541
12871287      {
12881288         case 0x8:   // Duplicate Even RD Data
12891289         {
1290            m_ide->ide_bus_w(0, 0, (data >> 16) & 0xffff);
1290            m_ide->write_cs0(space, 0, data >> 16, mem_mask >> 16);
12911291            break;
12921292         }
12931293
r23540r23541
13181318            case 0x6:   // Select Card/Head
13191319            case 0x7:   // Status
13201320            {
1321               r |= m_ide->ide_bus_r(0, offset & 7) << 16;
1321               r |= m_ide->read_cs0(space, offset & 7, mem_mask >> 16) << 16;
13221322               break;
13231323            }
13241324
r23540r23541
13271327
13281328            case 0xd:   // Duplicate Error
13291329            {
1330               r |= m_ide->ide_bus_r(0, 1) << 16;
1330               r |= m_ide->read_cs0(space, 1, mem_mask >> 16) << 16;
13311331               break;
13321332            }
13331333            case 0xe:   // Alt Status
13341334            case 0xf:   // Drive Address
13351335            {
1336               r |= m_ide->ide_bus_r(1, offset & 7) << 16;
1336               r |= m_ide->read_cs1(space, offset & 7, mem_mask >> 16) << 16;
13371337               break;
13381338            }
13391339
r23540r23541
13831383            case 0x6:   // Select Card/Head
13841384            case 0x7:   // Command
13851385            {
1386               m_ide->ide_bus_w(0, offset & 7, (data >> 16) & 0xffff);
1386               m_ide->write_cs0(space, offset & 7, data >> 16, mem_mask >> 16);
13871387               break;
13881388            }
13891389
r23540r23541
13921392
13931393            case 0xd:   // Duplicate Features
13941394            {
1395               m_ide->ide_bus_w(0, 1, (data >> 16) & 0xffff);
1395               m_ide->write_cs0(space, 1, data >> 16, mem_mask >> 16);
13961396               break;
13971397            }
13981398            case 0xe:   // Device Ctl
13991399            case 0xf:   // Reserved
14001400            {
1401               m_ide->ide_bus_w(1, offset & 7, (data >> 16) & 0xffff);
1401               m_ide->write_cs1(space, offset & 7, data >> 16, mem_mask >> 16);
14021402               break;
14031403            }
14041404
r23540r23541
14241424                  // cylinder low register is set to 0x00
14251425                  // cylinder high register is set to 0x00
14261426
1427                  m_ide->ide_bus_w(1, 6, 0x04);
1427                  m_ide->write_cs1(space, 6, 0x04, 0xff);
14281428
1429                  m_ide->ide_bus_w(0, 2, 0x01);
1430                  m_ide->ide_bus_w(0, 3, 0x01);
1431                  m_ide->ide_bus_w(0, 4, 0x00);
1432                  m_ide->ide_bus_w(0, 5, 0x00);
1429                  m_ide->write_cs0(space, 2, 0x01, 0xff);
1430                  m_ide->write_cs0(space, 3, 0x01, 0xff);
1431                  m_ide->write_cs0(space, 4, 0x00, 0xff);
1432                  m_ide->write_cs0(space, 5, 0x00, 0xff);
14331433               }
14341434               break;
14351435            }
r23540r23541
14611461   {
14621462      int reg = (offset >> 4) & 0x7;
14631463
1464      r |= m_ide->ide_bus_r((offset & 0x80) ? 1 : 0, reg) << 16;
1464      switch(offset & 0x80)
1465      {
1466      case 0x00:
1467         r |= m_ide->read_cs0(space, reg, mem_mask >> 16) << 16;
1468         break;
1469      case 0x80:
1470         r |= m_ide->read_cs1(space, reg, mem_mask >> 16) << 16;
1471         break;
1472      }
14651473   }
14661474
14671475   return r;
r23540r23541
14731481   {
14741482      int reg = (offset >> 4) & 0x7;
14751483
1476      m_ide->ide_bus_w((offset & 0x80) ? 1 : 0, reg, (UINT16)(data >> 16));
1484      switch(offset & 0x80)
1485      {
1486      case 0x00:
1487         m_ide->write_cs0(space, reg, data >> 16, mem_mask >> 16);
1488         break;
1489      case 0x80:
1490         m_ide->write_cs1(space, reg, data >> 16, mem_mask >> 16);
1491         break;
1492      }
14771493   }
14781494}
14791495
trunk/src/mame/drivers/mediagx.c
r23540r23541
149149   DECLARE_WRITE32_MEMBER(parallel_port_w);
150150   DECLARE_READ32_MEMBER(ad1847_r);
151151   DECLARE_WRITE32_MEMBER(ad1847_w);
152   DECLARE_READ32_MEMBER(ide_r);
153   DECLARE_WRITE32_MEMBER(ide_w);
154   DECLARE_READ32_MEMBER(fdc_r);
155   DECLARE_WRITE32_MEMBER(fdc_w);
156152   DECLARE_READ8_MEMBER(io20_r);
157153   DECLARE_WRITE8_MEMBER(io20_w);
158154   DECLARE_DRIVER_INIT(a51site4);
r23540r23541
414410}
415411
416412
417READ32_MEMBER(mediagx_state::ide_r)
418{
419   return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
420}
421
422WRITE32_MEMBER(mediagx_state::ide_w)
423{
424   m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
425}
426
427READ32_MEMBER(mediagx_state::fdc_r)
428{
429   return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
430}
431
432WRITE32_MEMBER(mediagx_state::fdc_w)
433{
434   m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
435}
436
437
438
439413READ32_MEMBER(mediagx_state::memory_ctrl_r)
440414{
441415   return m_memory_ctrl_reg[offset];
r23540r23541
784758   AM_IMPORT_FROM(pcat32_io_common)
785759   AM_RANGE(0x0020, 0x003f) AM_READWRITE8(io20_r, io20_w, 0xffffffff)
786760   AM_RANGE(0x00e8, 0x00eb) AM_NOP     // I/O delay port
787   AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w)
761   AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
788762   AM_RANGE(0x0378, 0x037b) AM_READWRITE(parallel_port_r, parallel_port_w)
789   AM_RANGE(0x03f0, 0x03ff) AM_READWRITE(fdc_r, fdc_w)
763   AM_RANGE(0x03f0, 0x03ff) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
790764   AM_RANGE(0x0400, 0x04ff) AM_READWRITE(ad1847_r, ad1847_w)
791765   AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
792766ADDRESS_MAP_END
trunk/src/mame/drivers/kinst.c
r23540r23541
325325
326326READ32_MEMBER(kinst_state::kinst_ide_r)
327327{
328   return midway_ide_asic_r(m_ide, space, offset / 2, mem_mask);
328   return m_ide->read_cs0(space, offset / 2, mem_mask);
329329}
330330
331331
332332WRITE32_MEMBER(kinst_state::kinst_ide_w)
333333{
334   midway_ide_asic_w(m_ide, space, offset / 2, data, mem_mask);
334   m_ide->write_cs0(space, offset / 2, data, mem_mask);
335335}
336336
337337
338338READ32_MEMBER(kinst_state::kinst_ide_extra_r)
339339{
340   return m_ide->ide_controller32_r(space, 0x3f6/4, 0x00ff0000) >> 16;
340   return m_ide->read_cs1(space, 6, 0xff);
341341}
342342
343343
344344WRITE32_MEMBER(kinst_state::kinst_ide_extra_w)
345345{
346   m_ide->ide_controller32_w(space, 0x3f6/4, data << 16, 0x00ff0000);
346   m_ide->write_cs1(space, 6, data, 0xff);
347347}
348348
349349
trunk/src/mame/drivers/djmain.c
r23540r23541
271271
272272//---------
273273
274READ32_MEMBER(djmain_state::ide_std_r)
275{
276   if (ACCESSING_BITS_0_7)
277      return m_ide->ide_controller16_r(space, 0x1f0/2 + offset, 0xff00) >> 8;
278   else
279      return m_ide->ide_controller16_r(space, 0x1f0/2 + offset, 0xffff) << 16;
280}
281
282WRITE32_MEMBER(djmain_state::ide_std_w)
283{
284   if (ACCESSING_BITS_0_7)
285      m_ide->ide_controller16_w(space, 0x1f0/2 + offset, data << 8, 0xff00);
286   else
287      m_ide->ide_controller16_w(space, 0x1f0/2 + offset, data >> 16, 0xffff);
288}
289
290
291READ32_MEMBER(djmain_state::ide_alt_r)
292{
293   if (offset == 0)
294      return m_ide->ide_controller16_r(space, 0x3f6/2, 0x00ff) << 24;
295
296   return 0;
297}
298
299WRITE32_MEMBER(djmain_state::ide_alt_w)
300{
301   if (offset == 0 && ACCESSING_BITS_16_23)
302      m_ide->ide_controller16_w(space, 0x3f6/2, data >> 24, 0x00ff);
303}
304
305
306//---------
307
308274// light/coin blocker control
309275
310276/*
r23540r23541
450416   AM_RANGE(0x803800, 0x803fff) AM_READ(obj_rom_r)                     // OBJECT ROM readthrough (for POST)
451417   AM_RANGE(0xc00000, 0xc01fff) AM_DEVREADWRITE_LEGACY("k056832", k056832_ram_long_r, k056832_ram_long_w)  // VIDEO RAM (tilemap) (beatmania)
452418   AM_RANGE(0xc02000, 0xc02047) AM_WRITE(unknownc02000_w)                  // ??
453   AM_RANGE(0xd00000, 0xd0000f) AM_READWRITE(ide_std_r, ide_std_w)             // IDE control regs (hiphopmania)
454   AM_RANGE(0xd4000c, 0xd4000f) AM_READWRITE(ide_alt_r, ide_alt_w)             // IDE status control reg (hiphopmania)
419   AM_RANGE(0xd00000, 0xd0000f) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff) // IDE control regs (hiphopmania)
420   AM_RANGE(0xd40000, 0xd4000f) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff) // IDE status control reg (hiphopmania)
455421   AM_RANGE(0xe00000, 0xe01fff) AM_DEVREADWRITE_LEGACY("k056832", k056832_ram_long_r, k056832_ram_long_w)  // VIDEO RAM (tilemap) (hiphopmania)
456   AM_RANGE(0xf00000, 0xf0000f) AM_READWRITE(ide_std_r, ide_std_w)             // IDE control regs (beatmania)
457   AM_RANGE(0xf4000c, 0xf4000f) AM_READWRITE(ide_alt_r, ide_alt_w)             // IDE status control reg (beatmania)
422   AM_RANGE(0xf00000, 0xf0000f) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff) // IDE control regs (beatmania)
423   AM_RANGE(0xf40000, 0xf4000f) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff) // IDE status control reg (beatmania)
458424ADDRESS_MAP_END
459425
460426
trunk/src/mame/drivers/fruitpc.c
r23540r23541
2525public:
2626   fruitpc_state(const machine_config &mconfig, device_type type, const char *tag)
2727      : pcat_base_state(mconfig, type, tag),
28         m_ide(*this, "ide"),
2928         m_inp1(*this, "INP1"),
3029         m_inp2(*this, "INP2"),
3130         m_inp3(*this, "INP3"),
3231         m_inp4(*this, "INP4")
3332         { }
3433
35   required_device<ide_controller_device> m_ide;
36
3734   required_ioport m_inp1;
3835   required_ioport m_inp2;
3936   required_ioport m_inp3;
r23540r23541
4340   DECLARE_READ8_MEMBER(fruit_inp_r);
4441   virtual void machine_start();
4542   virtual void machine_reset();
46   DECLARE_READ32_MEMBER(ide_r);
47   DECLARE_WRITE32_MEMBER(ide_w);
48   DECLARE_READ32_MEMBER(fdc_r);
49   DECLARE_WRITE32_MEMBER(fdc_w);
5043};
5144
5245READ8_MEMBER(fruitpc_state::fruit_inp_r)
r23540r23541
6558   return 0;
6659}
6760
68READ32_MEMBER(fruitpc_state::ide_r)
69{
70   return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
71}
72
73WRITE32_MEMBER(fruitpc_state::ide_w)
74{
75   m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
76}
77
78READ32_MEMBER(fruitpc_state::fdc_r)
79{
80   return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
81}
82
83WRITE32_MEMBER(fruitpc_state::fdc_w)
84{
85   //mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
86   m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
87}
88
8961static ADDRESS_MAP_START( fruitpc_map, AS_PROGRAM, 32, fruitpc_state )
9062   AM_RANGE(0x00000000, 0x0009ffff) AM_RAM
9163   AM_RANGE(0x000a0000, 0x000bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffffffff) // VGA VRAM
r23540r23541
9870
9971static ADDRESS_MAP_START( fruitpc_io, AS_IO, 32, fruitpc_state )
10072   AM_IMPORT_FROM(pcat32_io_common)
101   AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w)
73   AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
10274   AM_RANGE(0x0310, 0x0313) AM_READ8(fruit_inp_r, 0xffffffff)
10375   AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
10476   AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
10577   AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
106   AM_RANGE(0x03f0, 0x03f7) AM_READWRITE(fdc_r, fdc_w)
78   AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
10779ADDRESS_MAP_END
10880
10981#define AT_KEYB_HELPER(bit, text, key1) \
trunk/src/mame/drivers/queen.c
r23540r23541
3737{
3838public:
3939   queen_state(const machine_config &mconfig, device_type type, const char *tag)
40      : pcat_base_state(mconfig, type, tag),
41         m_ide(*this, "ide")
42         { }
40      : pcat_base_state(mconfig, type, tag)
41   {
42   }
4343
4444   UINT32 *m_bios_ram;
4545   UINT32 *m_bios_ext_ram;
4646   UINT8 m_mxtc_config_reg[256];
4747   UINT8 m_piix4_config_reg[4][256];
4848
49   // devices
50   required_device<ide_controller_device> m_ide;
51
5249   DECLARE_WRITE32_MEMBER( bios_ext_ram_w );
5350
5451   DECLARE_WRITE32_MEMBER( bios_ram_w );
55   DECLARE_READ32_MEMBER(ide_r);
56   DECLARE_WRITE32_MEMBER(ide_w);
57   DECLARE_READ32_MEMBER(fdc_r);
58   DECLARE_WRITE32_MEMBER(fdc_w);
5952   virtual void machine_start();
6053   virtual void machine_reset();
6154   void intel82439tx_init();
r23540r23541
230223   }
231224}
232225
233READ32_MEMBER(queen_state::ide_r)
234{
235   return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
236}
237
238WRITE32_MEMBER(queen_state::ide_w)
239{
240   m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
241}
242
243READ32_MEMBER(queen_state::fdc_r)
244{
245   return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
246}
247
248WRITE32_MEMBER(queen_state::fdc_w)
249{
250   //mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
251   m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
252}
253
254226static ADDRESS_MAP_START( queen_map, AS_PROGRAM, 32, queen_state )
255227   AM_RANGE(0x00000000, 0x0009ffff) AM_RAM
256228   AM_RANGE(0x000a0000, 0x000bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffffffff)
r23540r23541
264236   AM_IMPORT_FROM(pcat32_io_common)
265237   AM_RANGE(0x00e8, 0x00ef) AM_NOP
266238
267   AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w)
239   AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
268240   AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
269241   AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
270242   AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
271   AM_RANGE(0x03f0, 0x03f7) AM_READWRITE(fdc_r, fdc_w)
243   AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
272244
273245   AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
274246ADDRESS_MAP_END
trunk/src/mame/drivers/voyager.c
r23540r23541
2424{
2525public:
2626   voyager_state(const machine_config &mconfig, device_type type, const char *tag)
27      : pcat_base_state(mconfig, type, tag),
28         m_ide(*this, "ide")
29         { }
27      : pcat_base_state(mconfig, type, tag)
28   {
29   }
3030
3131   UINT32 *m_bios_ram;
3232   UINT8 m_mxtc_config_reg[256];
3333   UINT8 m_piix4_config_reg[4][256];
3434
35   required_device<ide_controller_device> m_ide;
36
3735   UINT32 m_idle_skip_ram;
3836   DECLARE_WRITE32_MEMBER(bios_ram_w);
39   DECLARE_READ32_MEMBER(ide_r);
40   DECLARE_WRITE32_MEMBER(ide_w);
41   DECLARE_READ32_MEMBER(fdc_r);
42   DECLARE_WRITE32_MEMBER(fdc_w);
4337   DECLARE_DRIVER_INIT(voyager);
4438   virtual void machine_start();
4539   virtual void machine_reset();
r23540r23541
4741};
4842
4943
50READ32_MEMBER(voyager_state::ide_r)
51{
52   return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
53}
54
55WRITE32_MEMBER(voyager_state::ide_w)
56{
57   m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
58}
59
60READ32_MEMBER(voyager_state::fdc_r)
61{
62   return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
63}
64
65WRITE32_MEMBER(voyager_state::fdc_w)
66{
67   //mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
68   m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
69}
70
71
7244// Intel 82439TX System Controller (MXTC)
7345
7446static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg)
r23540r23541
276248   //AM_RANGE(0x00e8, 0x00eb) AM_NOP
277249   AM_RANGE(0x00e8, 0x00ef) AM_NOP //AMI BIOS write to this ports as delays between I/O ports operations sending al value -> NEWIODELAY
278250   AM_RANGE(0x0170, 0x0177) AM_NOP //To debug
279   AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w)
251   AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
280252   AM_RANGE(0x0200, 0x021f) AM_NOP //To debug
281253   AM_RANGE(0x0260, 0x026f) AM_NOP //To debug
282254   AM_RANGE(0x0278, 0x027b) AM_WRITENOP//AM_WRITE(pnp_config_w)
r23540r23541
295267   AM_RANGE(0x0378, 0x037f) AM_NOP //To debug
296268   // AM_RANGE(0x0300, 0x03af) AM_NOP
297269   // AM_RANGE(0x03b0, 0x03df) AM_NOP
298   AM_RANGE(0x03f0, 0x03f7) AM_READWRITE(fdc_r, fdc_w)
270   AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
299271   AM_RANGE(0x03f8, 0x03ff) AM_NOP // To debug Serial Port COM1:
300272   AM_RANGE(0x0a78, 0x0a7b) AM_WRITENOP//AM_WRITE(pnp_data_w)
301273   AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
trunk/src/mame/drivers/chihiro.c
r23540r23541
394394   DECLARE_WRITE32_MEMBER( geforce_w );
395395   DECLARE_READ32_MEMBER( usbctrl_r );
396396   DECLARE_WRITE32_MEMBER( usbctrl_w );
397   DECLARE_READ32_MEMBER( ide_r );
398   DECLARE_WRITE32_MEMBER( ide_w );
399397   DECLARE_READ32_MEMBER( smbus_r );
400398   DECLARE_WRITE32_MEMBER( smbus_w );
401399   DECLARE_READ32_MEMBER( dummy_r );
r23540r23541
26482646{
26492647}
26502648
2651/*
2652 * IDE
2653 */
2654
2655INLINE int convert_to_offset_and_size32(offs_t *offset, UINT32 mem_mask)
2656{
2657   int size = 4;
2658
2659   /* determine which real offset */
2660   if (!ACCESSING_BITS_0_7)
2661   {
2662      (*offset)++, size = 3;
2663      if (!ACCESSING_BITS_8_15)
2664      {
2665         (*offset)++, size = 2;
2666         if (!ACCESSING_BITS_16_23)
2667            (*offset)++, size = 1;
2668      }
2669   }
2670
2671   /* determine the real size */
2672   if (ACCESSING_BITS_24_31)
2673      return size;
2674   size--;
2675   if (ACCESSING_BITS_16_23)
2676      return size;
2677   size--;
2678   if (ACCESSING_BITS_8_15)
2679      return size;
2680   size--;
2681   return size;
2682}
2683
2684READ32_MEMBER( chihiro_state::ide_r )
2685{
2686   int size;
2687
2688   offset *= 4;
2689   size = convert_to_offset_and_size32(&offset, mem_mask);
2690   return chihiro_devs.ide->ide_controller_r(offset+0x01f0, size) << ((offset & 3) * 8);
2691}
2692
2693WRITE32_MEMBER( chihiro_state::ide_w )
2694{
2695   int size;
2696
2697   offset *= 4;
2698   size = convert_to_offset_and_size32(&offset, mem_mask);
2699   data = data >> ((offset & 3) * 8);
2700   chihiro_devs.ide->ide_controller_w(offset+0x01f0, size, data);
2701}
2702
27032649// ======================> ide_baseboard_device
27042650
27052651class ide_baseboard_device : public ide_hdd_device
r23540r23541
29992945   AM_RANGE(0x0020, 0x0023) AM_DEVREADWRITE8("pic8259_1", pic8259_device, read, write, 0xffffffff)
30002946   AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("pit8254", pit8254_device, read, write, 0xffffffff)
30012947   AM_RANGE(0x00a0, 0x00a3) AM_DEVREADWRITE8("pic8259_2", pic8259_device, read, write, 0xffffffff)
3002   AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w)
2948   AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
30032949   AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
30042950   AM_RANGE(0x8000, 0x80ff) AM_READWRITE(dummy_r, dummy_w)
30052951   AM_RANGE(0xc000, 0xc0ff) AM_READWRITE(smbus_r, smbus_w)
trunk/src/mame/drivers/savquest.c
r23540r23541
4040{
4141public:
4242   savquest_state(const machine_config &mconfig, device_type type, const char *tag)
43      : pcat_base_state(mconfig, type, tag),
44         m_ide(*this, "ide")
45   { }
43      : pcat_base_state(mconfig, type, tag)
44   {
45   }
4646
4747   UINT32 *m_bios_f0000_ram;
4848   UINT32 *m_bios_e0000_ram;
r23540r23541
6767   UINT8 m_mxtc_config_reg[256];
6868   UINT8 m_piix4_config_reg[8][256];
6969
70   // devices
71   required_device<ide_controller_device> m_ide;
72
7370   DECLARE_WRITE32_MEMBER( bios_f0000_ram_w );
7471   DECLARE_WRITE32_MEMBER( bios_e0000_ram_w );
7572   DECLARE_WRITE32_MEMBER( bios_e4000_ram_w );
r23540r23541
8582   // driver_device overrides
8683//  virtual void video_start();
8784public:
88   DECLARE_READ32_MEMBER(ide_r);
89   DECLARE_WRITE32_MEMBER(ide_w);
90   DECLARE_READ32_MEMBER(fdc_r);
91   DECLARE_WRITE32_MEMBER(fdc_w);
9285   virtual void machine_start();
9386   virtual void machine_reset();
9487   void intel82439tx_init();
r23540r23541
535528   }
536529}
537530
538READ32_MEMBER(savquest_state::ide_r)
539{
540   return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
541}
542
543WRITE32_MEMBER(savquest_state::ide_w)
544{
545   m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
546}
547
548READ32_MEMBER(savquest_state::fdc_r)
549{
550   return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
551}
552
553WRITE32_MEMBER(savquest_state::fdc_w)
554{
555   //mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
556   m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
557}
558
559531static ADDRESS_MAP_START(savquest_map, AS_PROGRAM, 32, savquest_state)
560532   AM_RANGE(0x00000000, 0x0009ffff) AM_RAM
561533   AM_RANGE(0x000a0000, 0x000bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffffffff)
r23540r23541
575547
576548   AM_RANGE(0x00e8, 0x00ef) AM_NOP
577549
578   AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w)
550   AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
579551   AM_RANGE(0x0378, 0x037b) AM_READWRITE(parallel_port_r, parallel_port_w)
580552   AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
581553   AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
582554   AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
583   AM_RANGE(0x03f0, 0x03f7) AM_READWRITE(fdc_r, fdc_w)
555   AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
584556
585557   AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
586558
trunk/src/mame/drivers/photoply.c
r23540r23541
2121{
2222public:
2323   photoply_state(const machine_config &mconfig, device_type type, const char *tag)
24      : pcat_base_state(mconfig, type, tag),
25      m_ide(*this, "ide") { }
24      : pcat_base_state(mconfig, type, tag)
25   {
26   }
2627
2728   UINT8 m_vga_address;
2829
29   DECLARE_READ32_MEMBER(ide_r);
30   DECLARE_WRITE32_MEMBER(ide_w);
31   DECLARE_READ32_MEMBER(fdc_r);
32   DECLARE_WRITE32_MEMBER(fdc_w);
3330   DECLARE_DRIVER_INIT(photoply);
3431   virtual void machine_start();
35
36   required_device<ide_controller_device> m_ide;
3732};
3833
3934
4035
41READ32_MEMBER(photoply_state::ide_r)
42{
43   return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
44}
45
46WRITE32_MEMBER(photoply_state::ide_w)
47{
48   m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
49}
50
51READ32_MEMBER(photoply_state::fdc_r)
52{
53   return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
54}
55
56WRITE32_MEMBER(photoply_state::fdc_w)
57{
58   //mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
59   m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
60}
61
6236static ADDRESS_MAP_START( photoply_map, AS_PROGRAM, 32, photoply_state )
6337   AM_RANGE(0x00000000, 0x0009ffff) AM_RAM
6438   AM_RANGE(0x000a0000, 0x000bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffffffff) // VGA RAM
r23540r23541
7448static ADDRESS_MAP_START( photoply_io, AS_IO, 32, photoply_state )
7549   AM_IMPORT_FROM(pcat32_io_common)
7650   AM_RANGE(0x00e8, 0x00eb) AM_NOP
77   AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w)
51   AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
7852   AM_RANGE(0x0278, 0x027f) AM_RAM //parallel port 2
7953   AM_RANGE(0x0378, 0x037f) AM_RAM //parallel port
8054   //AM_RANGE(0x03bc, 0x03bf) AM_RAM //parallel port 3
8155   AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
8256   AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
8357   AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
84   AM_RANGE(0x03f0, 0x03f7) AM_READWRITE(fdc_r, fdc_w)
58   AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
8559ADDRESS_MAP_END
8660
8761#define AT_KEYB_HELPER(bit, text, key1) \
trunk/src/mame/drivers/midqslvr.c
r23540r23541
3434{
3535public:
3636   midqslvr_state(const machine_config &mconfig, device_type type, const char *tag)
37      : pcat_base_state(mconfig, type, tag),
38         m_ide(*this, "ide")
39         { }
37      : pcat_base_state(mconfig, type, tag)
38   {
39   }
4040
41   required_device<ide_controller_device> m_ide;
42
4341   UINT32 *m_bios_ram;
4442   UINT32 *m_bios_ext1_ram;
4543   UINT32 *m_bios_ext2_ram;
r23540r23541
5957   DECLARE_WRITE32_MEMBER( bios_ext4_ram_w );
6058
6159   DECLARE_WRITE32_MEMBER( bios_ram_w );
62   DECLARE_READ32_MEMBER(ide_r);
63   DECLARE_WRITE32_MEMBER(ide_w);
64   DECLARE_READ32_MEMBER(fdc_r);
65   DECLARE_WRITE32_MEMBER(fdc_w);
6660   virtual void machine_start();
6761   virtual void machine_reset();
6862   void intel82439tx_init();
r23540r23541
360354   }
361355}
362356
363READ32_MEMBER(midqslvr_state::ide_r)
364{
365   return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
366}
367
368WRITE32_MEMBER(midqslvr_state::ide_w)
369{
370   m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
371}
372
373READ32_MEMBER(midqslvr_state::fdc_r)
374{
375   return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
376}
377
378WRITE32_MEMBER(midqslvr_state::fdc_w)
379{
380   //mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
381   m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
382}
383
384357static ADDRESS_MAP_START(midqslvr_map, AS_PROGRAM, 32, midqslvr_state)
385358   AM_RANGE(0x00000000, 0x0009ffff) AM_RAM
386359   AM_RANGE(0x000a0000, 0x000bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffffffff)
r23540r23541
399372   AM_IMPORT_FROM(pcat32_io_common)
400373   AM_RANGE(0x00e8, 0x00ef) AM_NOP
401374
402   AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w)
375   AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
403376   AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
404377   AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
405378   AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
406   AM_RANGE(0x03f0, 0x03f7) AM_READWRITE(fdc_r, fdc_w)
379   AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
407380
408381   AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
409382ADDRESS_MAP_END
trunk/src/mame/drivers/calchase.c
r23540r23541
127127   calchase_state(const machine_config &mconfig, device_type type, const char *tag)
128128      : pcat_base_state(mconfig, type, tag),
129129         m_dac_l(*this, "dac_l"),
130         m_dac_r(*this, "dac_r"),
131         m_ide(*this, "ide")
132         { }
130         m_dac_r(*this, "dac_r")
131   {
132   }
133133
134134   UINT32 *m_bios_ram;
135135   UINT32 *m_bios_ext_ram;
r23540r23541
149149   DECLARE_WRITE16_MEMBER(calchase_dac_l_w);
150150   DECLARE_WRITE16_MEMBER(calchase_dac_r_w);
151151   DECLARE_DRIVER_INIT(calchase);
152   DECLARE_READ32_MEMBER(ide_r);
153   DECLARE_WRITE32_MEMBER(ide_w);
154   DECLARE_READ32_MEMBER(fdc_r);
155   DECLARE_WRITE32_MEMBER(fdc_w);
156152   virtual void machine_start();
157153   virtual void machine_reset();
158154   void intel82439tx_init();
159155   required_device<dac_device> m_dac_l;
160156   required_device<dac_device> m_dac_r;
161   required_device<ide_controller_device> m_ide;
162157};
163158
164159// Intel 82439TX System Controller (MXTC)
r23540r23541
374369   m_dac_r->write_unsigned16((data & 0xfff) << 4);
375370}
376371
377READ32_MEMBER(calchase_state::ide_r)
378{
379   return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
380}
381
382WRITE32_MEMBER(calchase_state::ide_w)
383{
384   m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
385}
386
387READ32_MEMBER(calchase_state::fdc_r)
388{
389   return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
390}
391
392WRITE32_MEMBER(calchase_state::fdc_w)
393{
394   //mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
395   m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
396}
397
398372static ADDRESS_MAP_START( calchase_map, AS_PROGRAM, 32, calchase_state )
399373   AM_RANGE(0x00000000, 0x0009ffff) AM_RAM
400374   AM_RANGE(0x000a0000, 0x000bffff) AM_DEVREADWRITE8("vga", trident_vga_device, mem_r, mem_w, 0xffffffff) // VGA VRAM
r23540r23541
435409   //AM_RANGE(0x00e8, 0x00eb) AM_NOP
436410   AM_RANGE(0x00e8, 0x00ef) AM_NOP //AMI BIOS write to this ports as delays between I/O ports operations sending al value -> NEWIODELAY
437411   AM_RANGE(0x0170, 0x0177) AM_NOP //To debug
438   AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w)
412   AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
439413   AM_RANGE(0x0200, 0x021f) AM_NOP //To debug
440414   AM_RANGE(0x0260, 0x026f) AM_NOP //To debug
441415   AM_RANGE(0x0278, 0x027b) AM_WRITENOP//AM_WRITE(pnp_config_w)
r23540r23541
454428   AM_RANGE(0x0378, 0x037f) AM_NOP //To debug
455429   // AM_RANGE(0x0300, 0x03af) AM_NOP
456430   // AM_RANGE(0x03b0, 0x03df) AM_NOP
457   AM_RANGE(0x03f0, 0x03f7) AM_READWRITE(fdc_r, fdc_w)
431   AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
458432   AM_RANGE(0x03f8, 0x03ff) AM_NOP // To debug Serial Port COM1:
459433   AM_RANGE(0x0a78, 0x0a7b) AM_WRITENOP//AM_WRITE(pnp_data_w)
460434   AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
trunk/src/mame/drivers/taitotz.c
r23540r23541
613613
614614   UINT8 m_rtcdata[8];
615615
616   UINT16 ide_cs0_latch_r;
617   UINT16 ide_cs0_latch_w;
618   UINT16 ide_cs1_latch_w;
616619
617620
618621   UINT32 m_reg105;
r23540r23541
21092112
21102113READ8_MEMBER(taitotz_state::tlcs_ide0_r)
21112114{
2112   static UINT16 ide_reg_latch;
21132115   int reg = offset >> 1;
21142116
21152117   if (reg == 0)
21162118   {
21172119      if ((offset & 1) == 0)
21182120      {
2119         ide_reg_latch = m_ide->ide_bus_r(0, reg);
2120         return (ide_reg_latch & 0xff);
2121         ide_cs0_latch_r = m_ide->read_cs0(space, reg, 0xffff);
2122         return (ide_cs0_latch_r & 0xff);
21212123      }
21222124      else
21232125      {
2124         return (ide_reg_latch >> 8) & 0xff;
2126         return (ide_cs0_latch_r >> 8) & 0xff;
21252127      }
21262128   }
21272129   else
r23540r23541
21292131      if (offset & 1)
21302132         fatalerror("tlcs_ide0_r: %02X, odd offset\n", offset);
21312133
2132      UINT8 d = m_ide->ide_bus_r(0, reg);
2134      UINT8 d = m_ide->read_cs0(space, reg, 0xff);
21332135      if (reg == 7)
21342136         d &= ~0x2;      // Type Zero doesn't like the index bit. It's defined as vendor-specific, so it probably shouldn't be up...
21352137                     // The status check explicitly checks for 0x50 (drive ready, seek complete).
r23540r23541
21392141
21402142WRITE8_MEMBER(taitotz_state::tlcs_ide0_w)
21412143{
2142   static UINT16 ide_reg_latch;
21432144   int reg = offset >> 1;
21442145
21452146   if (reg == 7 || reg == 0)
21462147   {
21472148      if ((offset & 1) == 0)
21482149      {
2149         ide_reg_latch &= 0xff00;
2150         ide_reg_latch |= data;
2150         ide_cs0_latch_w &= 0xff00;
2151         ide_cs0_latch_w |= data;
21512152      }
21522153      else
21532154      {
2154         ide_reg_latch &= 0x00ff;
2155         ide_reg_latch |= (UINT16)(data) << 8;
2156         m_ide->ide_bus_w(0, reg, ide_reg_latch);
2155         ide_cs0_latch_w &= 0x00ff;
2156         ide_cs0_latch_w |= (UINT16)(data) << 8;
2157         m_ide->write_cs0(space, reg, ide_cs0_latch_w, 0xffff);
21572158      }
21582159   }
21592160   else
21602161   {
21612162      if (offset & 1)
21622163         fatalerror("tlcs_ide0_w: %02X, %02X, odd offset\n", offset, data);
2163      m_ide->ide_bus_w(0, reg, data);
2164      m_ide->write_cs0(space, reg, data, 0xff);
21642165   }
21652166}
21662167
21672168READ8_MEMBER(taitotz_state::tlcs_ide1_r)
21682169{
2169   //static UINT16 ide_reg_latch;
21702170   int reg = offset >> 1;
21712171
21722172   if (reg != 6)
r23540r23541
21742174
21752175   if ((offset & 1) == 0)
21762176   {
2177      UINT8 d = m_ide->ide_bus_r(1, reg);
2177      UINT8 d = m_ide->read_cs1(space, reg, 0xff);
21782178      d &= ~0x2;      // Type Zero doesn't like the index bit. It's defined as vendor-specific, so it probably shouldn't be up...
21792179                  // The status check explicitly checks for 0x50 (drive ready, seek complete).
21802180      return d;
r23540r23541
21822182   else
21832183   {
21842184      //fatalerror("tlcs_ide1_r: %02X, odd offset\n", offset);
2185      UINT8 d = m_ide->ide_bus_r(1, reg);
2185      UINT8 d = m_ide->read_cs1(space, reg, 0xff);
21862186      d &= ~0x2;
21872187      return d;
21882188   }
r23540r23541
21902190
21912191WRITE8_MEMBER(taitotz_state::tlcs_ide1_w)
21922192{
2193   static UINT16 ide_reg_latch;
21942193   int reg = offset >> 1;
21952194
21962195   if (reg != 6)
r23540r23541
21982197
21992198   if ((offset & 1) == 0)
22002199   {
2201      ide_reg_latch &= 0xff00;
2202      ide_reg_latch |= data;
2200      ide_cs1_latch_w &= 0xff00;
2201      ide_cs1_latch_w |= data;
22032202   }
22042203   else
22052204   {
2206      ide_reg_latch &= 0x00ff;
2207      ide_reg_latch |= (UINT16)(data) << 16;
2208      m_ide->ide_bus_w(1, reg, ide_reg_latch);
2205      ide_cs1_latch_w &= 0x00ff;
2206      ide_cs1_latch_w |= (UINT16)(data) << 16;
2207      m_ide->write_cs1(space, reg, ide_cs1_latch_w, 0xffff);
22092208   }
22102209}
22112210
r23540r23541
25272526INPUT_PORTS_END
25282527
25292528
2530static void set_ide_drive_serial_number(device_t *device, int drive, const char *serial)
2531{
2532   ide_controller_device *ide = (ide_controller_device *) device;
2533   UINT8 *ide_features = ide->ide_get_features(drive);
2534
2535   for (int i=0; i < 20; i++)
2536   {
2537      ide_features[10*2+(i^1)] = serial[i];
2538   }
2539}
2540
2541
25422529void taitotz_state::machine_reset()
25432530{
25442531   if (m_hdd_serial_number != NULL)
25452532   {
2546      set_ide_drive_serial_number(m_ide, 0, m_hdd_serial_number);
2533      UINT8 *ide_features = m_ide->ide_get_features(0);
2534
2535      for (int i=0; i < 20; i++)
2536      {
2537         ide_features[10*2+(i^1)] = m_hdd_serial_number[i];
2538      }
25472539   }
25482540}
25492541
trunk/src/mame/drivers/cobra.c
r23540r23541
610610      m_gfx_pagetable(*this, "pagetable"),
611611      m_k001604(*this, "k001604"),
612612      m_ide(*this, "ide")
613   { }
613   {
614   }
614615
615616   required_device<cpu_device> m_maincpu;
616617   required_device<cpu_device> m_subcpu;
r23540r23541
638639   DECLARE_WRITE32_MEMBER(sub_config_w);
639640   DECLARE_READ32_MEMBER(sub_mainbd_r);
640641   DECLARE_WRITE32_MEMBER(sub_mainbd_w);
641   DECLARE_READ32_MEMBER(sub_ata0_r);
642   DECLARE_WRITE32_MEMBER(sub_ata0_w);
643   DECLARE_READ32_MEMBER(sub_ata1_r);
644   DECLARE_WRITE32_MEMBER(sub_ata1_w);
642   DECLARE_READ16_MEMBER(sub_ata0_r);
643   DECLARE_WRITE16_MEMBER(sub_ata0_w);
644   DECLARE_READ16_MEMBER(sub_ata1_r);
645   DECLARE_WRITE16_MEMBER(sub_ata1_w);
645646   DECLARE_READ32_MEMBER(sub_psac2_r);
646647   DECLARE_WRITE32_MEMBER(sub_psac2_w);
647648   DECLARE_WRITE32_MEMBER(sub_psac_palette_w);
r23540r23541
18141815{
18151816}
18161817
1817READ32_MEMBER(cobra_state::sub_ata0_r)
1818READ16_MEMBER(cobra_state::sub_ata0_r)
18181819{
1819   UINT32 r = 0;
1820   mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 );
18201821
1821   if (ACCESSING_BITS_16_31)
1822   {
1823      UINT16 v = m_ide->ide_bus_r(0, (offset << 1) + 0);
1824      r |= ((v << 8) | (v >> 8)) << 16;
1825   }
1826   if (ACCESSING_BITS_0_15)
1827   {
1828      UINT16 v = m_ide->ide_bus_r(0, (offset << 1) + 1);
1829      r |= ((v << 8) | (v >> 8)) << 0;
1830   }
1822   UINT32 data = m_ide->read_cs0(space, offset, mem_mask);
1823   data = ( data << 8 ) | ( data >> 8 );
18311824
1832   return r;
1825   return data;
18331826}
18341827
1835WRITE32_MEMBER(cobra_state::sub_ata0_w)
1828WRITE16_MEMBER(cobra_state::sub_ata0_w)
18361829{
1837   if (ACCESSING_BITS_16_31)
1838   {
1839      UINT16 d = ((data >> 24) & 0xff) | ((data >> 8) & 0xff00);
1840      m_ide->ide_bus_w(0, (offset << 1) + 0, d);
1841   }
1842   if (ACCESSING_BITS_0_15)
1843   {
1844      UINT16 d = ((data >> 8) & 0xff) | ((data << 8) & 0xff00);
1845      m_ide->ide_bus_w(0, (offset << 1) + 1, d);
1846   }
1830   mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 );
1831   data = ( data << 8 ) | ( data >> 8 );
1832
1833   m_ide->write_cs0(space, offset, data, mem_mask);
18471834}
18481835
1849READ32_MEMBER(cobra_state::sub_ata1_r)
1836READ16_MEMBER(cobra_state::sub_ata1_r)
18501837{
1851   UINT32 r = 0;
1838   mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 );
18521839
1853   if (ACCESSING_BITS_16_31)
1854   {
1855      UINT16 v = m_ide->ide_bus_r(1, (offset << 1) + 0);
1856      r |= ((v << 8) | (v >> 8)) << 16;
1857   }
1858   if (ACCESSING_BITS_0_15)
1859   {
1860      UINT16 v = m_ide->ide_bus_r(1, (offset << 1) + 1);
1861      r |= ((v << 8) | (v >> 8)) << 0;
1862   }
1840   UINT32 data = m_ide->read_cs1(space, offset, mem_mask);
18631841
1864   return r;
1842   return ( data << 8 ) | ( data >> 8 );
18651843}
18661844
1867WRITE32_MEMBER(cobra_state::sub_ata1_w)
1845WRITE16_MEMBER(cobra_state::sub_ata1_w)
18681846{
1869   if (ACCESSING_BITS_16_31)
1870   {
1871      UINT16 d = ((data >> 24) & 0xff) | ((data >> 8) & 0xff00);
1872      m_ide->ide_bus_w(1, (offset << 1) + 0, d);
1873   }
1874   if (ACCESSING_BITS_0_15)
1875   {
1876      UINT16 d = ((data >> 8) & 0xff) | ((data << 8) & 0xff00);
1877      m_ide->ide_bus_w(1, (offset << 1) + 1, d);
1878   }
1847   mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 );
1848   data = ( data << 8 ) | ( data >> 8 );
1849
1850   m_ide->write_cs1(space, offset, data, mem_mask);
18791851}
18801852
18811853READ32_MEMBER(cobra_state::sub_comram_r)
r23540r23541
19831955   AM_RANGE(0x70000000, 0x7003ffff) AM_MIRROR(0x80000000) AM_READWRITE(sub_comram_r, sub_comram_w)         // Double buffered shared RAM between Main and Sub
19841956//  AM_RANGE(0x78000000, 0x780000ff) AM_MIRROR(0x80000000) AM_NOP                                           // SCSI controller (unused)
19851957   AM_RANGE(0x78040000, 0x7804ffff) AM_MIRROR(0x80000000) AM_DEVREADWRITE16("rfsnd", rf5c400_device, rf5c400_r, rf5c400_w, 0xffffffff)
1986   AM_RANGE(0x78080000, 0x7808000f) AM_MIRROR(0x80000000) AM_READWRITE(sub_ata0_r, sub_ata0_w)
1987   AM_RANGE(0x780c0010, 0x780c001f) AM_MIRROR(0x80000000) AM_READWRITE(sub_ata1_r, sub_ata1_w)
1958   AM_RANGE(0x78080000, 0x7808000f) AM_MIRROR(0x80000000) AM_READWRITE16(sub_ata0_r, sub_ata0_w, 0xffffffff)
1959   AM_RANGE(0x780c0010, 0x780c001f) AM_MIRROR(0x80000000) AM_READWRITE16(sub_ata1_r, sub_ata1_w, 0xffffffff)
19881960   AM_RANGE(0x78200000, 0x782000ff) AM_MIRROR(0x80000000) AM_DEVREADWRITE_LEGACY("k001604", k001604_reg_r, k001604_reg_w)              // PSAC registers
19891961   AM_RANGE(0x78210000, 0x78217fff) AM_MIRROR(0x80000000) AM_RAM_WRITE(sub_psac_palette_w) AM_SHARE("paletteram")                      // PSAC palette RAM
19901962   AM_RANGE(0x78220000, 0x7823ffff) AM_MIRROR(0x80000000) AM_DEVREADWRITE_LEGACY("k001604", k001604_tile_r, k001604_tile_w)            // PSAC tile RAM
trunk/src/mame/drivers/vegas.c
r23540r23541
14591459static READ32_DEVICE_HANDLER( ide_main_r )
14601460{
14611461   ide_controller_device *ide = (ide_controller_device *) device;
1462   return ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
1462
1463   UINT32 data = 0;
1464   if (ACCESSING_BITS_0_15)
1465      data |= ide->read_cs0_pc(space, offset * 2, mem_mask);
1466   if (ACCESSING_BITS_16_31)
1467      data |= ide->read_cs0_pc(space, (offset * 2) + 1, mem_mask >> 16) << 16;
1468
1469   return data;
14631470}
14641471
14651472
14661473static WRITE32_DEVICE_HANDLER( ide_main_w )
14671474{
14681475   ide_controller_device *ide = (ide_controller_device *) device;
1469   ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
1476
1477   if (ACCESSING_BITS_0_15)
1478      ide->write_cs0_pc(space, offset * 2, data, mem_mask);
1479   if (ACCESSING_BITS_16_31)
1480      ide->write_cs0_pc(space, (offset * 2) + 1, data >> 16, mem_mask >> 16);
14701481}
14711482
14721483
14731484static READ32_DEVICE_HANDLER( ide_alt_r )
14741485{
14751486   ide_controller_device *ide = (ide_controller_device *) device;
1476   return ide->ide_controller32_r(space, 0x3f4/4 + offset, mem_mask);
1487
1488   UINT32 data = 0;
1489   if (ACCESSING_BITS_0_15)
1490      data |= ide->read_cs1_pc(space, (4/2) + (offset * 2), mem_mask);
1491   if (ACCESSING_BITS_16_31)
1492      data |= ide->read_cs1_pc(space, (4/2) + (offset * 2) + 1, mem_mask >> 16) << 16;
1493
1494   return data;
14771495}
14781496
14791497
14801498static WRITE32_DEVICE_HANDLER( ide_alt_w )
14811499{
14821500   ide_controller_device *ide = (ide_controller_device *) device;
1483   ide->ide_controller32_w(space, 0x3f4/4 + offset, data, mem_mask);
1501
1502   if (ACCESSING_BITS_0_15)
1503      ide->write_cs1_pc(space, 6/2 + offset * 2, data, mem_mask);
1504   if (ACCESSING_BITS_16_31)
1505      ide->write_cs1_pc(space, 6/2 + (offset * 2) + 1, data >> 16, mem_mask >> 16);
14841506}
14851507
14861508
trunk/src/mame/drivers/quakeat.c
r23540r23541
9292static ADDRESS_MAP_START( quake_io, AS_IO, 32, quakeat_state )
9393   AM_IMPORT_FROM(pcat32_io_common)
9494   AM_RANGE(0x00e8, 0x00eb) AM_NOP
95//  AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE_LEGACY("ide", ide_r, ide_w)
95//   AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
9696   AM_RANGE(0x0300, 0x03af) AM_NOP
9797   AM_RANGE(0x03b0, 0x03df) AM_NOP
9898//  AM_RANGE(0x0278, 0x027b) AM_WRITE(pnp_config_w)
99//  AM_RANGE(0x03f0, 0x03ff) AM_DEVREADWRITE_LEGACY("ide", fdc_r, fdc_w)
99//  AM_RANGE(0x03f0, 0x03ff) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
100100//  AM_RANGE(0x0a78, 0x0a7b) AM_WRITE(pnp_data_w)
101101//  AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_device, read, write)
102102ADDRESS_MAP_END
trunk/src/mame/drivers/twinkle.c
r23540r23541
247247      : driver_device(mconfig, type, tag),
248248      m_am53cf96(*this, "scsi:am53cf96"),
249249      m_maincpu(*this, "maincpu"),
250      m_audiocpu(*this, "audiocpu"),
251      m_ide(*this, "ide")
250      m_audiocpu(*this, "audiocpu")
252251   {
253252   }
254253
r23540r23541
273272   DECLARE_WRITE16_MEMBER(twinkle_waveram_w);
274273   DECLARE_READ16_MEMBER(shared_68k_r);
275274   DECLARE_WRITE16_MEMBER(shared_68k_w);
276   DECLARE_READ16_MEMBER(twinkle_ide_r);
277   DECLARE_WRITE16_MEMBER(twinkle_ide_w);
278275   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
279276   DECLARE_DRIVER_INIT(twinkle);
280277   required_device<cpu_device> m_maincpu;
281278   required_device<cpu_device> m_audiocpu;
282   required_device<ide_controller_device> m_ide;
283279};
284280
285281/* RTC */
r23540r23541
647643   }
648644}
649645
650READ16_MEMBER(twinkle_state::twinkle_ide_r)
651{
652   if (offset == 0)
653   {
654      return m_ide->ide_controller_r(0x1f0 + offset, 2);
655   }
656   else
657   {
658      return m_ide->ide_controller_r(0x1f0 + offset, 1);
659   }
660}
661
662WRITE16_MEMBER(twinkle_state::twinkle_ide_w)
663{
664   m_ide->ide_controller_w(0x1f0 + offset, 1, data);
665}
666
667646/*
668647    System control register (Konami always has one)
669648
r23540r23541
734713   // 250000 = write to initiate DMA?
735714   // 260000 = ???
736715   AM_RANGE(0x280000, 0x280fff) AM_READWRITE(shared_68k_r, shared_68k_w )
737   AM_RANGE(0x300000, 0x30000f) AM_READWRITE(twinkle_ide_r, twinkle_ide_w)
716   AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE("ide", ide_controller_device, read_cs0, write_cs0)
738717   // 34000E = ???
739718   AM_RANGE(0x400000, 0x400fff) AM_DEVREADWRITE("rfsnd", rf5c400_device, rf5c400_r, rf5c400_w)
740719   AM_RANGE(0x800000, 0xffffff) AM_READWRITE(twinkle_waveram_r, twinkle_waveram_w )    // 8 MB window wave RAM
trunk/src/mame/drivers/midvunit.c
r23540r23541
508508   AM_RANGE(0x990000, 0x99000f) AM_READWRITE_LEGACY(midway_ioasic_r, midway_ioasic_w)
509509   AM_RANGE(0x994000, 0x994000) AM_WRITE(midvunit_control_w)
510510   AM_RANGE(0x995020, 0x995020) AM_WRITE(midvunit_cmos_protect_w)
511   AM_RANGE(0x9a0000, 0x9a0007) AM_DEVREADWRITE_LEGACY("ide", midway_ide_asic_r, midway_ide_asic_w)
511   AM_RANGE(0x9a0000, 0x9a0007) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0x0000ffff)
512512   AM_RANGE(0x9c0000, 0x9c7fff) AM_RAM_WRITE(midvunit_paletteram_w) AM_SHARE("paletteram")
513513   AM_RANGE(0x9d0000, 0x9d000f) AM_READWRITE(midvplus_misc_r, midvplus_misc_w) AM_SHARE("midvplus_misc")
514514   AM_RANGE(0xa00000, 0xbfffff) AM_READWRITE(midvunit_textureram_r, midvunit_textureram_w) AM_SHARE("textureram")
trunk/src/mame/drivers/zn.c
r23540r23541
8282   DECLARE_WRITE8_MEMBER(coh1002m_bank_w);
8383   DECLARE_READ8_MEMBER(cbaj_sound_main_status_r);
8484   DECLARE_READ8_MEMBER(cbaj_sound_z80_status_r);
85   DECLARE_READ8_MEMBER(jdredd_idestat_r);
86   DECLARE_READ16_MEMBER(jdredd_ide_r);
87   DECLARE_WRITE16_MEMBER(jdredd_ide_w);
8885   DECLARE_DRIVER_INIT(coh1000ta);
8986   DECLARE_DRIVER_INIT(coh1000tb);
9087   DECLARE_DRIVER_INIT(coh1000c);
r23540r23541
109106
110107private:
111108   inline void ATTR_PRINTF(3,4) verboselog( int n_level, const char *s_fmt, ... );
112   inline UINT8 psxreadbyte( UINT32 *p_n_psxram, UINT32 n_address );
113   inline void psxwritebyte( UINT32 *p_n_psxram, UINT32 n_address, UINT8 n_data );
109   inline UINT16 psxreadword( UINT32 *p_n_psxram, UINT32 n_address );
110   inline void psxwriteword( UINT32 *p_n_psxram, UINT32 n_address, UINT16 n_data );
114111
115112   UINT8 m_n_znsecsel;
116113
r23540r23541
147144}
148145
149146#ifdef UNUSED_FUNCTION
150inline UINT8 zn_state::psxreadbyte( UINT32 *p_n_psxram, UINT32 n_address )
147inline UINT16 zn_state::psxreadword( UINT32 *p_n_psxram, UINT32 n_address )
151148{
152   return *( (UINT8 *)p_n_psxram + BYTE4_XOR_LE( n_address ) );
149   return *( (UINT16 *)( (UINT8 *)p_n_psxram + WORD_XOR_LE( n_address ) ) );
153150}
154151#endif
155152
156inline void zn_state::psxwritebyte( UINT32 *p_n_psxram, UINT32 n_address, UINT8 n_data )
153inline void zn_state::psxwriteword( UINT32 *p_n_psxram, UINT32 n_address, UINT16 n_data )
157154{
158   *( (UINT8 *)p_n_psxram + BYTE4_XOR_LE( n_address ) ) = n_data;
155   *( (UINT16 *)( (UINT8 *)p_n_psxram + WORD_XOR_LE( n_address ) ) ) = n_data;
159156}
160157
161158static const UINT8 ac01[ 8 ] = { 0x80, 0x1c, 0xe2, 0xfa, 0xf9, 0xf1, 0x30, 0xc0 };
r23540r23541
13411338      return;
13421339   }
13431340
1344   /* dma size is in 32-bit words, convert to bytes */
1345   n_size <<= 2;
1341//   printf( "%08x %08x %08x\n", n_address, n_size * 4, n_address + n_size * 4 );
1342
1343   /* dma size is in 32-bit words, convert to words */
1344   n_size <<= 1;
13461345   address_space &space = machine().firstcpu->space(AS_PROGRAM);
13471346   while( n_size > 0 )
13481347   {
1349      psxwritebyte( p_n_psxram, n_address, m_ide->ide_controller32_r( space, 0x1f0 / 4, 0x000000ff ) );
1350      n_address++;
1348      psxwriteword( p_n_psxram, n_address, m_ide->read_cs0( space, 0, 0xffff ) );
1349      n_address += 2;
13511350      n_size--;
13521351   }
1352
1353//   printf( "%08x\n", n_address );
13531354}
13541355
13551356void zn_state::atpsx_dma_write( UINT32 *p_n_psxram, UINT32 n_address, INT32 n_size )
r23540r23541
13611362   AM_RANGE(0x1f000000, 0x1f1fffff) AM_ROM AM_REGION("roms", 0)
13621363   AM_RANGE(0x1f000000, 0x1f000003) AM_WRITENOP
13631364   AM_RANGE(0x1f7e8000, 0x1f7e8003) AM_NOP
1364   AM_RANGE(0x1f7e4000, 0x1f7e4fff) AM_DEVREADWRITE("ide", ide_controller_device, ide_controller32_r, ide_controller32_w )
1365   AM_RANGE(0x1f7f4000, 0x1f7f4fff) AM_DEVREADWRITE("ide", ide_controller_device, ide_controller32_r, ide_controller32_w )
1365   AM_RANGE(0x1f7e4030, 0x1f7e403f) AM_DEVREADWRITE8("ide", ide_controller_device, read_via_config, write_via_config, 0xffffffff)
1366   AM_RANGE(0x1f7e41f0, 0x1f7e41f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
1367   AM_RANGE(0x1f7e43f0, 0x1f7e43f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
1368   AM_RANGE(0x1f7f41f0, 0x1f7f41f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
1369   AM_RANGE(0x1f7f43f0, 0x1f7f43f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff)
13661370
13671371   AM_IMPORT_FROM(zn_map)
13681372ADDRESS_MAP_END
r23540r23541
18741878      *         - Unpopulated DIP42 socket
18751879*/
18761880
1877READ8_MEMBER(zn_state::jdredd_idestat_r)
1878{
1879   return m_ide->ide_controller_r( 0x1f7, 1 );
1880}
1881
1882READ16_MEMBER(zn_state::jdredd_ide_r)
1883{
1884   UINT16 data = 0;
1885
1886   if( ACCESSING_BITS_0_7 )
1887   {
1888      data |= m_ide->ide_controller_r( 0x1f0 + offset, 1 ) << 0;
1889   }
1890   if( ACCESSING_BITS_8_15 )
1891   {
1892      data |= m_ide->ide_controller_r( 0x1f0 + offset, 1 ) << 8;
1893   }
1894
1895   return data;
1896}
1897
1898WRITE16_MEMBER(zn_state::jdredd_ide_w)
1899{
1900   if( ACCESSING_BITS_0_7 )
1901   {
1902      m_ide->ide_controller_w( 0x1f0 + offset, 1, data >> 0 );
1903   }
1904   if( ACCESSING_BITS_8_15 )
1905   {
1906      m_ide->ide_controller_w( 0x1f0 + offset, 1, data >> 8 );
1907   }
1908}
1909
19101881CUSTOM_INPUT_MEMBER(zn_state::jdredd_gun_mux_read)
19111882{
19121883   return m_jdredd_gun_mux;
r23540r23541
19881959ADDRESS_MAP_END
19891960
19901961static ADDRESS_MAP_START(jdredd_map, AS_PROGRAM, 32, zn_state)
1991   AM_RANGE(0x1fbfff8c, 0x1fbfff8f) AM_READ8(jdredd_idestat_r, 0x000000ff) AM_WRITENOP
1992   AM_RANGE(0x1fbfff90, 0x1fbfff9f) AM_READWRITE16(jdredd_ide_r, jdredd_ide_w, 0xffffffff)
1962   AM_RANGE(0x1fbfff80, 0x1fbfff8f) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
1963   AM_RANGE(0x1fbfff90, 0x1fbfff9f) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
19931964
19941965   AM_IMPORT_FROM(coh1000a_map)
19951966ADDRESS_MAP_END
trunk/src/mame/drivers/qdrmfgp.c
r23540r23541
181181
182182/*************/
183183
184READ16_MEMBER(qdrmfgp_state::ide_std_r)
185{
186   if (offset & 0x01)
187      return m_ide->ide_controller16_r(space, 0x1f0/2 + offset/2, 0xff00) >> 8;
188   else
189      return m_ide->ide_controller16_r(space, 0x1f0/2 + offset/2, 0xffff);
190}
191184
192WRITE16_MEMBER(qdrmfgp_state::ide_std_w)
193{
194   if (offset & 0x01)
195      m_ide->ide_controller16_w(space, 0x1f0/2 + offset/2, data << 8, 0xff00);
196   else
197      m_ide->ide_controller16_w(space, 0x1f0/2 + offset/2, data, 0xffff);
198}
199
200READ16_MEMBER(qdrmfgp_state::ide_alt_r)
201{
202   if (offset == 0)
203      return m_ide->ide_controller16_r(space, 0x3f6/2, 0x00ff);
204
205   return 0;
206}
207
208WRITE16_MEMBER(qdrmfgp_state::ide_alt_w)
209{
210   if (offset == 0)
211      m_ide->ide_controller16_w(space, 0x3f6/2, data, 0x00ff);
212}
213
214
215185READ16_MEMBER(qdrmfgp_state::gp2_ide_std_r)
216186{
217   if (offset & 0x01)
187   if (offset == 0x07)
218188   {
219      if (offset == 0x07)
189      switch (space.device().safe_pcbase())
220190      {
221         switch (space.device().safe_pcbase())
222         {
223            case 0xdb4c:
224               if ((m_workram[0x5fa4/2] - space.device().state().state_int(M68K_D0)) <= 0x10)
225                  m_gp2_irq_control = 1;
226               break;
227            case 0xdec2:
191         case 0xdb4c:
192            if ((m_workram[0x5fa4/2] - space.device().state().state_int(M68K_D0)) <= 0x10)
228193               m_gp2_irq_control = 1;
229            default:
230               break;
231         }
194            break;
195         case 0xdec2:
196            m_gp2_irq_control = 1;
197         default:
198            break;
232199      }
233
234      return m_ide->ide_controller16_r(space, 0x1f0/2 + offset/2, 0xff00) >> 8;
235200   }
236   else
237   {
238      return m_ide->ide_controller16_r(space, 0x1f0/2 + offset/2, 0xffff);
239   }
201
202   return m_ide->read_cs0(space, offset, mem_mask);
240203}
241204
242205
r23540r23541
328291   AM_RANGE(0x880000, 0x881fff) AM_DEVREADWRITE_LEGACY("k056832", k056832_ram_word_r, k056832_ram_word_w)          /* vram */
329292   AM_RANGE(0x882000, 0x883fff) AM_DEVREADWRITE_LEGACY("k056832", k056832_ram_word_r, k056832_ram_word_w)          /* vram (mirror) */
330293   AM_RANGE(0x900000, 0x901fff) AM_READ(v_rom_r)                                               /* gfxrom through */
331   AM_RANGE(0xa00000, 0xa0000f) AM_READWRITE(ide_std_r,ide_std_w)                  /* IDE control regs */
332   AM_RANGE(0xa4000c, 0xa4000f) AM_READWRITE(ide_alt_r,ide_alt_w)                  /* IDE status control reg */
294   AM_RANGE(0xa00000, 0xa0000f) AM_DEVREADWRITE("ide", ide_controller_device, read_cs0, write_cs0) /* IDE control regs */
295   AM_RANGE(0xa40000, 0xa4000f) AM_DEVREADWRITE("ide", ide_controller_device, read_cs1, write_cs1) /* IDE status control reg */
333296   AM_RANGE(0xc00000, 0xcbffff) AM_READWRITE(sndram_r, sndram_w)                               /* sound ram */
334297ADDRESS_MAP_END
335298
r23540r23541
351314   AM_RANGE(0x880000, 0x881fff) AM_READWRITE(gp2_vram_r, gp2_vram_w)                           /* vram */
352315   AM_RANGE(0x89f000, 0x8a0fff) AM_READWRITE(gp2_vram_mirror_r, gp2_vram_mirror_w)             /* vram (mirror) */
353316   AM_RANGE(0x900000, 0x901fff) AM_READ(v_rom_r)                                               /* gfxrom through */
354   AM_RANGE(0xa00000, 0xa0000f) AM_READ(gp2_ide_std_r) AM_WRITE(ide_std_w)         /* IDE control regs */
355   AM_RANGE(0xa4000c, 0xa4000f) AM_READWRITE(ide_alt_r,ide_alt_w)                  /* IDE status control reg */
317   AM_RANGE(0xa00000, 0xa0000f) AM_READ(gp2_ide_std_r) AM_DEVWRITE("ide", ide_controller_device, write_cs0) /* IDE control regs */
318   AM_RANGE(0xa40000, 0xa4000f) AM_DEVREADWRITE("ide", ide_controller_device, read_cs1, write_cs1) /* IDE status control reg */
356319   AM_RANGE(0xc00000, 0xcbffff) AM_READWRITE(sndram_r,sndram_w)                                /* sound ram */
357320ADDRESS_MAP_END
358321
trunk/src/mame/machine/midwayic.c
r23540r23541
10471047         break;
10481048   }
10491049}
1050
1051
1052
1053/*************************************
1054 *
1055 *  The IDE ASIC was used on War Gods
1056 *  and Killer Instinct to map the IDE
1057 *  registers
1058 *
1059 *************************************/
1060
1061READ32_DEVICE_HANDLER( midway_ide_asic_r )
1062{
1063   /* convert to standard IDE offsets */
1064   offs_t ideoffs = 0x1f0/4 + (offset >> 2);
1065   UINT8 shift = 8 * (offset & 3);
1066   UINT32 result;
1067
1068   ide_controller_device *ide = (ide_controller_device *) device;
1069
1070   /* offset 0 is a special case */
1071   if (offset == 0)
1072      result = ide->ide_controller32_r(space, ideoffs, 0x0000ffff);
1073
1074   /* everything else is byte-sized */
1075   else
1076      result = ide->ide_controller32_r(space, ideoffs, 0xff << shift) >> shift;
1077   return result;
1078}
1079
1080
1081WRITE32_DEVICE_HANDLER( midway_ide_asic_w )
1082{
1083   /* convert to standard IDE offsets */
1084   offs_t ideoffs = 0x1f0/4 + (offset >> 2);
1085   UINT8 shift = 8 * (offset & 3);
1086
1087   ide_controller_device *ide = (ide_controller_device *) device;
1088
1089   /* offset 0 is a special case */
1090   if (offset == 0)
1091      ide->ide_controller32_w(space, ideoffs, data, 0x0000ffff);
1092
1093   /* everything else is byte-sized */
1094   else
1095      ide->ide_controller32_w(space, ideoffs, data << shift, 0xff << shift);
1096}
trunk/src/mame/machine/midwayic.h
r23540r23541
4747   MIDWAY_IOASIC_SFRUSHRK,
4848   MIDWAY_IOASIC_HYPRDRIV
4949};
50
51
52
53/* IDE ASIC maps the IDE registers */
54DECLARE_READ32_DEVICE_HANDLER( midway_ide_asic_r );
55DECLARE_WRITE32_DEVICE_HANDLER( midway_ide_asic_w );
trunk/src/mame/includes/qdrmfgp.h
r23540r23541
3737   DECLARE_READ16_MEMBER(gp2_ide_std_r);
3838   DECLARE_CUSTOM_INPUT_MEMBER(inputs_r);
3939   DECLARE_CUSTOM_INPUT_MEMBER(battery_sensor_r);
40   DECLARE_READ16_MEMBER(ide_std_r);
41   DECLARE_WRITE16_MEMBER(ide_std_w);
42   DECLARE_READ16_MEMBER(ide_alt_r);
43   DECLARE_WRITE16_MEMBER(ide_alt_w);
4440   DECLARE_WRITE_LINE_MEMBER(qdrmfgp_irq3_ack_w);
4541   DECLARE_WRITE_LINE_MEMBER(qdrmfgp_irq4_ack_w);
4642   virtual void machine_reset();
trunk/src/mame/includes/jaguar.h
r23540r23541
88#include "machine/nvram.h"
99#include "sound/dac.h"
1010#include "machine/eeprom.h"
11#include "machine/idectrl.h"
1112#include "imagedev/snapquik.h"
1213
1314#ifndef ENABLE_SPEEDUP_HACKS
r23540r23541
5455         m_joystick_data(0),
5556         m_eeprom_bit_count(0),
5657         m_protection_check(0) ,
57      m_eeprom(*this, "eeprom") { }
58      m_eeprom(*this, "eeprom"),
59      m_ide(*this, "ide")
60   {
61   }
5862
5963   // devices
6064   required_device<cpu_device> m_maincpu;
r23540r23541
207211   DECLARE_WRITE32_MEMBER( blitter_w );
208212   DECLARE_READ16_MEMBER( tom_regs_r );
209213   DECLARE_WRITE16_MEMBER( tom_regs_w );
214   DECLARE_READ32_MEMBER( vt83c461_r );
215   DECLARE_WRITE32_MEMBER( vt83c461_w );
210216   DECLARE_READ32_MEMBER( cojag_gun_input_r );
211217   UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
212218
r23540r23541
319325   void jaguar_nvram_load();
320326   void jaguar_nvram_save();
321327   optional_device<eeprom_device> m_eeprom;
328   optional_device<ide_controller_device> m_ide;
322329};
trunk/src/mame/includes/djmain.h
r23540r23541
4242   DECLARE_WRITE32_MEMBER(unknown590000_w);
4343   DECLARE_WRITE32_MEMBER(unknown802000_w);
4444   DECLARE_WRITE32_MEMBER(unknownc02000_w);
45   DECLARE_READ32_MEMBER(ide_std_r);
46   DECLARE_WRITE32_MEMBER(ide_std_w);
47   DECLARE_READ32_MEMBER(ide_alt_r);
48   DECLARE_WRITE32_MEMBER(ide_alt_w);
4945   DECLARE_DRIVER_INIT(bm7thmix);
5046   DECLARE_DRIVER_INIT(bm6thmix);
5147   DECLARE_DRIVER_INIT(hmcompmx);
trunk/src/emu/machine/idectrl.c
r23540r23541
4242#define IDE_STATUS_DRIVE_READY              0x40
4343#define IDE_STATUS_BUSY                     0x80
4444
45#define BANK(b, v) (((v) << 4) | (b))
45#define IDE_BANK0_DATA                      0
46#define IDE_BANK0_ERROR                     1
47#define IDE_BANK0_SECTOR_COUNT              2
48#define IDE_BANK0_SECTOR_NUMBER             3
49#define IDE_BANK0_CYLINDER_LSB              4
50#define IDE_BANK0_CYLINDER_MSB              5
51#define IDE_BANK0_HEAD_NUMBER               6
52#define IDE_BANK0_STATUS_COMMAND            7
4653
47#define IDE_BANK0_DATA                      BANK(0, 0)
48#define IDE_BANK0_ERROR                     BANK(0, 1)
49#define IDE_BANK0_SECTOR_COUNT              BANK(0, 2)
50#define IDE_BANK0_SECTOR_NUMBER             BANK(0, 3)
51#define IDE_BANK0_CYLINDER_LSB              BANK(0, 4)
52#define IDE_BANK0_CYLINDER_MSB              BANK(0, 5)
53#define IDE_BANK0_HEAD_NUMBER               BANK(0, 6)
54#define IDE_BANK0_STATUS_COMMAND            BANK(0, 7)
54#define IDE_BANK1_STATUS_CONTROL            6
5555
56#define IDE_BANK1_STATUS_CONTROL            BANK(1, 6)
56#define IDE_BANK2_CONFIG_UNK                4
57#define IDE_BANK2_CONFIG_REGISTER           8
58#define IDE_BANK2_CONFIG_DATA               0xc
5759
58#define IDE_BANK2_CONFIG_UNK                BANK(2, 4)
59#define IDE_BANK2_CONFIG_REGISTER           BANK(2, 8)
60#define IDE_BANK2_CONFIG_DATA               BANK(2, 0xc)
61
6260#define IDE_COMMAND_READ_MULTIPLE           0x20
6361#define IDE_COMMAND_READ_MULTIPLE_NORETRY   0x21
6462#define IDE_COMMAND_WRITE_MULTIPLE          0x30
r23540r23541
226224   return size;
227225}
228226
229INLINE int convert_to_offset_and_size16(offs_t *offset, UINT32 mem_mask)
230{
231   int size = 2;
232227
233   /* determine which real offset */
234   if (!ACCESSING_BITS_0_7)
235      (*offset)++, size = 1;
236228
237   if (ACCESSING_BITS_8_15)
238      return size;
239   size--;
240   return size;
241}
242
243
244
245229/*************************************
246230 *
247231 *  Advance to the next sector
r23540r23541
968952 *
969953 *************************************/
970954
971UINT32 ide_controller_device::ide_controller_read(int bank, offs_t offset, int size)
955READ8_MEMBER( ide_controller_device::read_via_config )
972956{
973   UINT32 result = 0;
957   UINT16 result = 0;
958
959   /* logit */
960   LOG(("%s:IDE via config read at %X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask));
961
962   switch(offset)
963   {
964      /* unknown config register */
965      case IDE_BANK2_CONFIG_UNK:
966         result = config_unknown;
967         break;
968
969      /* active config register */
970      case IDE_BANK2_CONFIG_REGISTER:
971         result = config_register_num;
972         break;
973
974      /* data from active config register */
975      case IDE_BANK2_CONFIG_DATA:
976         if (config_register_num < IDE_CONFIG_REGISTERS)
977            result = config_register[config_register_num];
978         break;
979
980      default:
981         logerror("%s:unknown IDE via config read at %03X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask);
982         break;
983   }
984
985//   printf( "read via config %04x %04x %04x\n", offset, result, mem_mask );
986   return result;
987}
988
989READ16_MEMBER( ide_controller_device::read_cs0_pc )
990{
991   if (mem_mask == 0xffff && offset == 1 ) offset = 0; // hack for 32 bit read of data register
992   if (mem_mask == 0xff00)
993   {
994      return read_cs0(space, (offset * 2) + 1, 0xff) << 8;
995   }
996   else
997   {
998      return read_cs0(space, offset * 2, mem_mask);
999   }
1000}
1001
1002READ16_MEMBER( ide_controller_device::read_cs0 )
1003{
1004   UINT16 result = 0;
9741005   ide_device_interface *dev = slot[cur_drive]->dev();
9751006
9761007   /* logit */
977//  if (BANK(bank, offset) != IDE_BANK0_DATA && BANK(bank, offset) != IDE_BANK0_STATUS_COMMAND && BANK(bank, offset) != IDE_BANK1_STATUS_CONTROL)
978      LOG(("%s:IDE read at %d:%X, size=%d\n", machine().describe_context(), bank, offset, size));
1008//  if (offset != IDE_BANK0_DATA && offset != IDE_BANK0_STATUS_COMMAND)
1009      LOG(("%s:IDE cs0 read at %X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask));
9791010
9801011   if (dev != NULL)
9811012   {
r23540r23541
9931024      return status;
9941025   }
9951026
996   switch (BANK(bank, offset))
1027   switch (offset)
9971028   {
998      /* unknown config register */
999      case IDE_BANK2_CONFIG_UNK:
1000         return config_unknown;
1001
1002      /* active config register */
1003      case IDE_BANK2_CONFIG_REGISTER:
1004         return config_register_num;
1005
1006      /* data from active config register */
1007      case IDE_BANK2_CONFIG_DATA:
1008         if (config_register_num < IDE_CONFIG_REGISTERS)
1009            return config_register[config_register_num];
1010         return 0;
1011
10121029      /* read data if there's data to be read */
10131030      case IDE_BANK0_DATA:
10141031         if (status & IDE_STATUS_BUFFER_READY)
10151032         {
10161033            /* fetch the correct amount of data */
10171034            result = buffer[buffer_offset++];
1018            if (size > 1)
1035            if (mem_mask == 0xffff)
10191036               result |= buffer[buffer_offset++] << 8;
1020            if (size > 2)
1021            {
1022               result |= buffer[buffer_offset++] << 16;
1023               result |= buffer[buffer_offset++] << 24;
1024            }
10251037
10261038            /* if we're at the end of the buffer, handle it */
10271039            if (buffer_offset >= IDE_DISK_SECTOR_SIZE)
r23540r23541
10351047
10361048      /* return the current error */
10371049      case IDE_BANK0_ERROR:
1038         return error;
1050         result = error;
1051         break;
10391052
10401053      /* return the current sector count */
10411054      case IDE_BANK0_SECTOR_COUNT:
1042         return sector_count;
1055         result = sector_count;
1056         break;
10431057
10441058      /* return the current sector */
10451059      case IDE_BANK0_SECTOR_NUMBER:
1046         return dev->cur_sector;
1060         result = dev->cur_sector;
1061         break;
10471062
10481063      /* return the current cylinder LSB */
10491064      case IDE_BANK0_CYLINDER_LSB:
1050         return dev->cur_cylinder & 0xff;
1065         result = dev->cur_cylinder & 0xff;
1066         break;
10511067
10521068      /* return the current cylinder MSB */
10531069      case IDE_BANK0_CYLINDER_MSB:
1054         return dev->cur_cylinder >> 8;
1070         result = dev->cur_cylinder >> 8;
1071         break;
10551072
10561073      /* return the current head */
10571074      case IDE_BANK0_HEAD_NUMBER:
1058         return dev->cur_head_reg;
1075         result = dev->cur_head_reg;
1076         break;
10591077
10601078      /* return the current status and clear any pending interrupts */
10611079      case IDE_BANK0_STATUS_COMMAND:
1062      /* return the current status but don't clear interrupts */
1063      case IDE_BANK1_STATUS_CONTROL:
10641080         result = status;
10651081         if (last_status_timer->elapsed() > TIME_PER_ROTATION)
10661082         {
10671083            result |= IDE_STATUS_HIT_INDEX;
10681084            last_status_timer->adjust(attotime::never);
10691085         }
1086         if (interrupt_pending)
1087            clear_interrupt();
1088         break;
10701089
1071         /* clear interrutps only when reading the real status */
1072         if (BANK(bank, offset) == IDE_BANK0_STATUS_COMMAND)
1090      /* log anything else */
1091      default:
1092         logerror("%s:unknown IDE cs0 read at %03X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask);
1093         break;
1094   }
1095
1096//   printf( "read cs0 %04x %04x %04x\n", offset, result, mem_mask );
1097
1098   /* return the result */
1099   return result;
1100}
1101
1102
1103READ16_MEMBER( ide_controller_device::read_cs1_pc )
1104{
1105   if (mem_mask == 0xff00)
1106   {
1107      return read_cs1(space, (offset * 2) + 1, 0xff) << 8;
1108   }
1109   else
1110   {
1111      return read_cs1(space, offset * 2, mem_mask);
1112   }
1113}
1114
1115READ16_MEMBER( ide_controller_device::read_cs1 )
1116{
1117   UINT16 result = 0;
1118   ide_device_interface *dev = slot[cur_drive]->dev();
1119
1120   if (dev != NULL)
1121   {
1122      if (dev->is_ready()) {
1123         status |= IDE_STATUS_DRIVE_READY;
1124      } else {
1125         status &= ~IDE_STATUS_DRIVE_READY;
1126      }
1127   }
1128   else
1129   {
1130      /* even a do-nothing operation should take a little time */
1131
1132      status ^= IDE_STATUS_BUSY;
1133      return status;
1134   }
1135
1136   /* logit */
1137//  if (offset != IDE_BANK1_STATUS_CONTROL)
1138      LOG(("%s:IDE cs1 read at %X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask));
1139      /* return the current status but don't clear interrupts */
1140
1141   switch (offset)
1142   {
1143      case IDE_BANK1_STATUS_CONTROL:
1144         result = status;
1145         if (last_status_timer->elapsed() > TIME_PER_ROTATION)
10731146         {
1074            if (interrupt_pending)
1075               clear_interrupt();
1147            result |= IDE_STATUS_HIT_INDEX;
1148            last_status_timer->adjust(attotime::never);
10761149         }
10771150         break;
10781151
10791152      /* log anything else */
10801153      default:
1081         logerror("%s:unknown IDE read at %03X, size=%d\n", machine().describe_context(), offset, size);
1154         logerror("%s:unknown IDE cs1 read at %03X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask);
10821155         break;
10831156   }
10841157
1158//   printf( "read cs1 %04x %04x %04x\n", offset, result, mem_mask );
1159
10851160   /* return the result */
10861161   return result;
10871162}
10881163
10891164
1090
10911165/*************************************
10921166 *
10931167 *  IDE controller write
10941168 *
10951169 *************************************/
10961170
1097void ide_controller_device::ide_controller_write(int bank, offs_t offset, int size, UINT32 data)
1171WRITE8_MEMBER( ide_controller_device::write_via_config )
10981172{
1099   switch (BANK(bank, offset))
1100   {
1101      case IDE_BANK0_HEAD_NUMBER:
1102         cur_drive = (data & 0x10) >> 4;
1103         break;
1104   }
1173//   printf( "write via config %04x %04x %04x\n", offset, data, mem_mask );
11051174
1106   ide_device_interface *dev = slot[cur_drive]->dev();
1107   if (dev == NULL)
1108      return;
1109
11101175   /* logit */
1111   if (BANK(bank, offset) != IDE_BANK0_DATA)
1112      LOG(("%s:IDE write to %d:%X = %08X, size=%d\n", machine().describe_context(), bank, offset, data, size));
1113   //  fprintf(stderr, "ide write %03x %02x size=%d\n", offset, data, size);
1114   switch (BANK(bank, offset))
1176   LOG(("%s:IDE via config write to %X = %08X, mem_mask=%d\n", machine().describe_context(), offset, data, mem_mask));
1177
1178   switch (offset)
11151179   {
11161180      /* unknown config register */
11171181      case IDE_BANK2_CONFIG_UNK:
r23540r23541
11281192         if (config_register_num < IDE_CONFIG_REGISTERS)
11291193            config_register[config_register_num] = data;
11301194         break;
1195   }
1196}
11311197
1198WRITE16_MEMBER( ide_controller_device::write_cs0_pc )
1199{
1200   if (mem_mask == 0xffff && offset == 1 ) offset = 0; // hack for 32 bit write to data register
1201   if (mem_mask == 0xff00)
1202   {
1203      return write_cs0(space, (offset * 2) + 1, data >> 8, 0xff);
1204   }
1205   else
1206   {
1207      return write_cs0(space, offset * 2, data, mem_mask);
1208   }
1209}
1210
1211WRITE16_MEMBER( ide_controller_device::write_cs0 )
1212{
1213//   printf( "write cs0 %04x %04x %04x\n", offset, data, mem_mask );
1214
1215   switch (offset)
1216   {
1217      case IDE_BANK0_HEAD_NUMBER:
1218         cur_drive = (data & 0x10) >> 4;
1219         break;
1220   }
1221
1222   ide_device_interface *dev = slot[cur_drive]->dev();
1223   if (dev == NULL)
1224      return;
1225
1226   /* logit */
1227   if (offset != IDE_BANK0_DATA)
1228      LOG(("%s:IDE cs0 write to %X = %08X, mem_mask=%d\n", machine().describe_context(), offset, data, mem_mask));
1229   //  fprintf(stderr, "ide write %03x %02x mem_mask=%d\n", offset, data, size);
1230   switch (offset)
1231   {
11321232      /* write data */
11331233      case IDE_BANK0_DATA:
11341234         if (status & IDE_STATUS_BUFFER_READY)
11351235         {
11361236            /* store the correct amount of data */
11371237            buffer[buffer_offset++] = data;
1138            if (size > 1)
1238            if (mem_mask == 0xffff)
11391239               buffer[buffer_offset++] = data >> 8;
1140            if (size > 2)
1141            {
1142               buffer[buffer_offset++] = data >> 16;
1143               buffer[buffer_offset++] = data >> 24;
1144            }
11451240
11461241            /* if we're at the end of the buffer, handle it */
11471242            if (buffer_offset >= IDE_DISK_SECTOR_SIZE)
r23540r23541
12451340      case IDE_BANK0_STATUS_COMMAND:
12461341         handle_command(data);
12471342         break;
1343   }
1344}
12481345
1346WRITE16_MEMBER( ide_controller_device::write_cs1_pc )
1347{
1348   if (mem_mask == 0xff00)
1349   {
1350      return write_cs1(space, (offset * 2) + 1, data >> 8, 0xff);
1351   }
1352   else
1353   {
1354      return write_cs1(space, offset * 2, data, mem_mask);
1355   }
1356}
1357
1358WRITE16_MEMBER( ide_controller_device::write_cs1 )
1359{
1360//   printf( "write cs1 %04x %04x %04x\n", offset, data, mem_mask );
1361
1362   /* logit */
1363   LOG(("%s:IDE cs1 write to %X = %08X, mem_mask=%d\n", machine().describe_context(), offset, data, mem_mask));
1364
1365   switch (offset)
1366   {
12491367      /* adapter control */
12501368      case IDE_BANK1_STATUS_CONTROL:
12511369         adapter_control = data;
r23540r23541
12631381}
12641382
12651383
1266
12671384/*************************************
12681385 *
12691386 *  Bus master read
r23540r23541
13541471      bus_master_descriptor = data & 0xfffffffc;
13551472}
13561473
1357
1358
1359/*************************************
1360 *
1361 *  IDE direct handlers (16-bit)
1362 *
1363 *************************************/
1364
1365/*
1366    ide_bus_r()
1367
1368    Read a 16-bit word from the IDE bus directly.
1369
1370    select: 0->CS1Fx active, 1->CS3Fx active
1371    offset: register offset (state of DA2-DA0)
1372*/
1373int ide_controller_device::ide_bus_r(int select, int offset)
1374{
1375   return ide_controller_read(select ? 1 : 0, offset, select == 0 && offset == 0 ? 2 : 1);
1376}
1377
1378/*
1379    ide_bus_w()
1380
1381    Write a 16-bit word to the IDE bus directly.
1382
1383    select: 0->CS1Fx active, 1->CS3Fx active
1384    offset: register offset (state of DA2-DA0)
1385    data: data written (state of D0-D15 or D0-D7)
1386*/
1387void ide_controller_device::ide_bus_w(int select, int offset, int data)
1388{
1389   if (select == 0 && offset == 0)
1390      ide_controller_write(0, 0, 2, data);
1391   else
1392      ide_controller_write(select ? 1 : 0, offset, 1, data & 0xff);
1393}
1394
1395UINT32 ide_controller_device::ide_controller_r(int reg, int size)
1396{
1397   if (reg >= 0x1f0 && reg < 0x1f8)
1398      return ide_controller_read(0, reg & 7, size);
1399   if (reg >= 0x3f0 && reg < 0x3f8)
1400      return ide_controller_read(1, reg & 7, size);
1401   if (reg >= 0x030 && reg < 0x040)
1402      return ide_controller_read(2, reg & 0xf, size);
1403   return 0xffffffff;
1404}
1405
1406void ide_controller_device::ide_controller_w(int reg, int size, UINT32 data)
1407{
1408   if (reg >= 0x1f0 && reg < 0x1f8)
1409      ide_controller_write(0, reg & 7, size, data);
1410   if (reg >= 0x3f0 && reg < 0x3f8)
1411      ide_controller_write(1, reg & 7, size, data);
1412   if (reg >= 0x030 && reg < 0x040)
1413      ide_controller_write(2, reg & 0xf, size, data);
1414}
1415
1416
1417/*************************************
1418 *
1419 *  32-bit IDE handlers
1420 *
1421 *************************************/
1422
1423READ32_MEMBER( ide_controller_device::ide_controller32_r )
1424{
1425   int size;
1426
1427   offset *= 4;
1428   size = convert_to_offset_and_size32(&offset, mem_mask);
1429
1430   return ide_controller_r(offset, size) << ((offset & 3) * 8);
1431}
1432
1433
1434WRITE32_MEMBER( ide_controller_device::ide_controller32_w )
1435{
1436   int size;
1437
1438   offset *= 4;
1439   size = convert_to_offset_and_size32(&offset, mem_mask);
1440   data = data >> ((offset & 3) * 8);
1441
1442   ide_controller_w(offset, size, data);
1443}
1444
1445
1446READ16_MEMBER( ide_controller_device::ide_controller16_pcmcia_r )
1447{
1448   int size;
1449   UINT32 res = 0xffff;
1450
1451   offset *= 2;
1452   size = convert_to_offset_and_size16(&offset, mem_mask);
1453
1454   if (offset < 0x008)
1455      res = ide_controller_read(0, offset & 7, size);
1456   if (offset >= 0x008 && offset < 0x010)
1457      res = ide_controller_read(1, offset & 7, size);
1458
1459   return res << ((offset & 1) * 8);
1460}
1461
1462
1463WRITE16_MEMBER( ide_controller_device::ide_controller16_pcmcia_w )
1464{
1465   int size;
1466
1467   offset *= 2;
1468   size = convert_to_offset_and_size16(&offset, mem_mask);
1469   data = data >> ((offset & 1) * 8);
1470
1471   if (offset < 0x008)
1472      ide_controller_write(0, offset & 7, size, data);
1473   if (offset >= 0x008 && offset < 0x010)
1474      ide_controller_write(1, offset & 7, size, data);
1475}
1476
14771474READ32_MEMBER( ide_controller_device::ide_bus_master32_r )
14781475{
14791476   int size;
r23540r23541
14961493}
14971494
14981495
1499
1500/*************************************
1501 *
1502 *  16-bit IDE handlers
1503 *
1504 *************************************/
1505
1506READ16_MEMBER( ide_controller_device::ide_controller16_r )
1507{
1508   int size;
1509
1510   offset *= 2;
1511   size = convert_to_offset_and_size16(&offset, mem_mask);
1512
1513   return ide_controller_r(offset, size) << ((offset & 1) * 8);
1514}
1515
1516
1517WRITE16_MEMBER( ide_controller_device::ide_controller16_w )
1518{
1519   int size;
1520
1521   offset *= 2;
1522   size = convert_to_offset_and_size16(&offset, mem_mask);
1523
1524   ide_controller_w(offset, size, data >> ((offset & 1) * 8));
1525}
1526
15271496SLOT_INTERFACE_START(ide_devices)
15281497   SLOT_INTERFACE("hdd", IDE_HARDDISK)
15291498SLOT_INTERFACE_END
trunk/src/emu/machine/idectrl.h
r23540r23541
9090   void ide_set_master_password(const UINT8 *password);
9191   void ide_set_user_password(const UINT8 *password);
9292
93   int ide_bus_r(int select, int offset);
94   void ide_bus_w(int select, int offset, int data);
93   DECLARE_READ8_MEMBER(read_via_config);
94   DECLARE_WRITE8_MEMBER(write_via_config);
95   DECLARE_READ16_MEMBER(read_cs0);
96   DECLARE_READ16_MEMBER(read_cs1);
97   DECLARE_WRITE16_MEMBER(write_cs0);
98   DECLARE_WRITE16_MEMBER(write_cs1);
9599
96   UINT32 ide_controller_r(int reg, int size);
97   void ide_controller_w(int reg, int size, UINT32 data);
98
99   DECLARE_READ32_MEMBER( ide_controller32_r );
100   DECLARE_WRITE32_MEMBER( ide_controller32_w );
101   DECLARE_READ16_MEMBER( ide_controller16_pcmcia_r );
102   DECLARE_WRITE16_MEMBER( ide_controller16_pcmcia_w );
100   DECLARE_READ16_MEMBER(read_cs0_pc);
101   DECLARE_READ16_MEMBER(read_cs1_pc);
102   DECLARE_WRITE16_MEMBER(write_cs0_pc);
103   DECLARE_WRITE16_MEMBER(write_cs1_pc);
104   
103105   DECLARE_READ32_MEMBER( ide_bus_master32_r );
104106   DECLARE_WRITE32_MEMBER( ide_bus_master32_w );
105107
106   DECLARE_READ16_MEMBER( ide_controller16_r );
107   DECLARE_WRITE16_MEMBER( ide_controller16_w );
108
109   UINT32 ide_controller_read(int bank, offs_t offset, int size);
110   void ide_controller_write(int bank, offs_t offset, int size, UINT32 data);
111108   UINT32 ide_bus_master_read(offs_t offset, int size);
112109   void ide_bus_master_write(offs_t offset, int size, UINT32 data);
113110   void signal_interrupt();
trunk/src/emu/machine/rf5c296.c
r23540r23541
4141
4242WRITE16_MEMBER(rf5c296_device::io_w)
4343{
44   if(offset < 4)
44   /// TODO: find out if this should be done here.
45   offset *= 2;
46   if (mem_mask == 0xff00)
4547   {
46      m_pccard->write_memory(space, offset, data, mem_mask);
48      mem_mask >>= 8;
49      data >>= 8;
50      offset++;
4751   }
4852
49   if(offset == 0x3e0/2)
53   switch(offset)
5054   {
51      if(ACCESSING_BITS_0_7)
52         m_rf5c296_reg = data;
53      if(ACCESSING_BITS_8_15)
54         reg_w(m_rf5c296_reg, data >> 8);
55   case 0x3e0:
56      m_rf5c296_reg = data;
57      break;
58
59   case 0x3e1:
60      reg_w(m_rf5c296_reg, data);
61      break;
62
63   default:
64      m_pccard->write_memory(space, offset, data, mem_mask);
65      break;
5566   }
5667}
5768
5869READ16_MEMBER(rf5c296_device::io_r)
5970{
60   if(offset < 4)
71   /// TODO: find out if this should be done here.
72   offset *= 2;
73   int shift = 0;
74   if (mem_mask == 0xff00)
6175   {
62      return m_pccard->read_memory(space, offset, mem_mask);
76      shift = 8;
77      mem_mask >>= 8;
78      offset++;
6379   }
6480
65   offset *= 2;
81   UINT16 data;
6682
67   if(offset == 0x3e0/2)
83   switch( offset )
6884   {
69      UINT32 res = 0x0000;
70      if(ACCESSING_BITS_0_7)
71         res |= m_rf5c296_reg;
72      if(ACCESSING_BITS_8_15)
73         res |= reg_r(m_rf5c296_reg) << 8;
74      return res;
85   case 0x3e0:
86      data = m_rf5c296_reg;
87      break;
88
89   case 0x3e1:
90      data = reg_r(m_rf5c296_reg);
91      break;
92     
93   default:
94      data = m_pccard->read_memory(space, offset, mem_mask);
95      break;
7596   }
7697
77   return 0xffff;
98   return data << shift;
7899}
79100
80101// Hardcoded to reach the pcmcia CIS
trunk/src/emu/machine/ataflash.c
r23540r23541
4141
4242READ16_MEMBER( ata_flash_pccard_device::read_memory )
4343{
44   return m_card->ide_controller16_pcmcia_r(space, offset, mem_mask);
44   if(offset <= 7)
45   {
46      return m_card->read_cs0(space, offset, mem_mask);
47   }
48   else if(offset <= 15)
49   {
50      return m_card->read_cs1(space, offset & 7, mem_mask);
51   }
52   else
53   {
54      return 0xffff;
55   }
4556}
4657
4758WRITE16_MEMBER( ata_flash_pccard_device::write_memory )
4859{
49   m_card->ide_controller16_pcmcia_w(space, offset, data, mem_mask);
60   if(offset <= 7)
61   {
62      m_card->write_cs0(space, offset, data, mem_mask);
63   }
64   else if( offset <= 15)
65   {
66      m_card->write_cs1(space, offset, data & 7, mem_mask);
67   }
5068}
5169
5270READ16_MEMBER( ata_flash_pccard_device::read_reg )
trunk/src/mess/machine/ti99/tn_ide.c
r23540r23541
151151         case 2:     /* IDE registers set 1 (CS1Fx) */
152152            if (m_tms9995_mode ? (!(addr & 1)) : (addr & 1))
153153            {   /* first read triggers 16-bit read cycle */
154               m_input_latch = (! (addr & 0x10)) ? m_ide->ide_bus_r(0, (addr >> 1) & 0x7) : 0;
154               m_input_latch = (! (addr & 0x10)) ? m_ide->read_cs0(space, (addr >> 1) & 0x7, 0xffff) : 0;
155155            }
156156
157157            /* return latched input */
r23540r23541
162162         case 3:     /* IDE registers set 2 (CS3Fx) */
163163            if (m_tms9995_mode ? (!(addr & 1)) : (addr & 1))
164164            {   /* first read triggers 16-bit read cycle */
165               m_input_latch = (! (addr & 0x10)) ? m_ide->ide_bus_r(1, (addr >> 1) & 0x7) : 0;
165               m_input_latch = (! (addr & 0x10)) ? m_ide->read_cs1(space, (addr >> 1) & 0x7, 0xffff) : 0;
166166            }
167167
168168            /* return latched input */
r23540r23541
232232
233233            if (m_tms9995_mode ? (addr & 1) : (!(addr & 1)))
234234            {   /* second write triggers 16-bit write cycle */
235               m_ide->ide_bus_w(0, (addr >> 1) & 0x7, m_output_latch);
235               m_ide->write_cs0(space, (addr >> 1) & 0x7, m_output_latch, 0xffff);
236236            }
237237            break;
238238         case 3:     /* IDE registers set 2 (CS3Fx) */
r23540r23541
250250
251251            if (m_tms9995_mode ? (addr & 1) : (!(addr & 1)))
252252            {   /* second write triggers 16-bit write cycle */
253               m_ide->ide_bus_w(1, (addr >> 1) & 0x7, m_output_latch);
253               m_ide->write_cs1(space, (addr >> 1) & 0x7, m_output_latch, 0xffff);
254254            }
255255            break;
256256         }
trunk/src/mess/machine/a2cffa.c
r23540r23541
143143         break;
144144
145145      case 8:
146         m_lastdata = m_ide->ide_controller_r(0x1f0+offset-8, 2);
146         m_lastdata = m_ide->read_cs0(space, offset-8, 0xffff);
147147         return m_lastdata & 0xff;
148148
149149      case 9:
r23540r23541
153153      case 0xd:
154154      case 0xe:
155155      case 0xf:
156         return m_ide->ide_controller_r(0x1f0+offset-8, 1);
156         return m_ide->read_cs0(space, offset-8, 0xff);
157157   }
158158
159159   return 0xff;
r23540r23541
184184      case 8:
185185         m_lastdata &= 0xff00;
186186         m_lastdata |= data;
187         m_ide->ide_controller_w(0x1f0+offset-8, 2, m_lastdata);
187         m_ide->write_cs0(space, offset-8, m_lastdata, 0xffff);
188188         break;
189189
190190      case 9:
r23540r23541
194194      case 0xd:
195195      case 0xe:
196196      case 0xf:
197         m_ide->ide_controller_w(0x1f0+offset-8, 1, data);
197         m_ide->write_cs0(space, offset-8, data, 0xff);
198198         break;
199199   }
200200}
trunk/src/mess/machine/isa_ide8.c
r23540r23541
6262   if(offset == 0)
6363   {
6464      // Data register transfer low byte and latch high
65      result=ide->ide_controller_read(0, (offset & 0x07), 1);
66      ide8_d->set_latch_in(ide->ide_controller_read(0, (offset & 0x07), 1));
65      UINT16 data16 = ide->read_cs0(space, (offset & 0x07), 0xffff);
66      result = data16 & 0xff;
67      ide8_d->set_latch_in(data16>>8);
6768   }
6869   else if((offset > 0) && (offset < 8))
69      result=ide->ide_controller_read(0, (offset & 0x07), 1);
70      result=ide->read_cs0(space, (offset & 0x07), 0xff);
7071   else if(offset == 8)
7172      result=ide8_d->get_latch_in();
7273   else if(offset == 14)
73      result=ide->ide_controller_read(1, (offset & 0x07), 1);
74      result=ide->read_cs1(space, (offset & 0x07), 0xff);
7475
7576//  logerror("%s ide8_r: offset=%d, result=%2X\n",device->machine().describe_context(),offset,result);
7677
r23540r23541
8788   if(offset == 0)
8889   {
8990      // Data register transfer low byte and latched high
90      ide->ide_controller_write(0, (offset & 7), 1, data);
91      ide->ide_controller_write(0, (offset & 7), 1, ide8_d->get_latch_out());
91      UINT16 data16 = (ide8_d->get_latch_out() << 8) | data;
92      ide->write_cs0(space, (offset & 7), data16, 0xffff);
9293   }
9394   else if((offset > 0) && (offset < 8))
94      ide->ide_controller_write(0, (offset & 7), 1, data);
95      ide->write_cs0(space, (offset & 7), data, 0xff);
9596   else if(offset == 8)
9697      ide8_d->set_latch_out(data);
9798   else if(offset == 14)
98      ide->ide_controller_write(1, (offset & 7), 1, data);
99      ide->write_cs1(space, (offset & 7), data, 0xff);
99100}
100101
101102
trunk/src/mess/machine/bebox.c
r23540r23541
504504 *
505505 *************************************/
506506
507READ8_MEMBER(bebox_state::bebox_800001F0_r ) { return m_ide->ide_controller_r(offset + 0x1F0, 1); }
508WRITE8_MEMBER(bebox_state::bebox_800001F0_w ) { m_ide->ide_controller_w(offset + 0x1F0, 1, data); }
509
510READ64_MEMBER(bebox_state::bebox_800003F0_r )
511{
512   UINT64 result = 0;
513
514   if (((mem_mask >> 8) & 0xFF) == 0)
515   {
516      result |= m_ide->ide_controller_r(0x3F6, 1) << 8;
517   }
518   return result;
519}
520
521
522WRITE64_MEMBER(bebox_state::bebox_800003F0_w )
523{
524   if (((mem_mask >> 8) & 0xFF) == 0)
525      m_ide->ide_controller_w(0x3F6, 1, (data >> 8) & 0xFF);
526}
527
528
529507WRITE_LINE_MEMBER(bebox_state::bebox_ide_interrupt)
530508{
531509   bebox_set_irq_bit(machine(), 7, state);
trunk/src/mess/machine/adam_ide.c
r23540r23541
121121      case 0x05:
122122      case 0x06:
123123      case 0x07:
124         data = m_ide->ide_bus_r(0, offset & 0x07) & 0xff;
124         data = m_ide->read_cs0(space, offset & 0x07, 0xff);
125125         break;
126126
127127      case 0x40: // Printer status
r23540r23541
142142         break;
143143
144144      case 0x58:
145         m_ide_data = m_ide->ide_bus_r(0, 0);
145         m_ide_data = m_ide->read_cs0(space, 0, 0xffff);
146146
147147         data = m_ide_data & 0xff;
148148         break;
r23540r23541
152152         break;
153153
154154      case 0x5a:
155         data = m_ide->ide_bus_r(1, 6) & 0xff;
155         data = m_ide->read_cs1(space, 6, 0xff);
156156         break;
157157
158158      case 0x5b: // Digital Input Register
r23540r23541
181181      case 0x05:
182182      case 0x06:
183183      case 0x07:
184         m_ide->ide_bus_w(0, offset & 0x07, data);
184         m_ide->write_cs0(space, offset & 0x07, data, 0xff);
185185         break;
186186
187187      case 0x40:
r23540r23541
193193
194194      case 0x58:
195195         m_ide_data |= data;
196         m_ide->ide_bus_w(0, 0, m_ide_data);
196         m_ide->write_cs0(space, 0, m_ide_data, 0xffff);
197197         break;
198198
199199      case 0x59:
trunk/src/mess/machine/c64_ide64.c
r23540r23541
179179
180180      UINT8 io1_offset = offset & 0xff;
181181
182      if (io1_offset >= 0x20 && io1_offset < 0x30)
182      if (io1_offset >= 0x20 && io1_offset < 0x28)
183183      {
184         m_ide_data = m_ide->ide_bus_r(BIT(offset, 3), offset & 0x07);
184         m_ide_data = m_ide->read_cs0(space, offset & 0x07, 0xffff);
185185
186186         data = m_ide_data & 0xff;
187187      }
188      else if (io1_offset >= 0x28 && io1_offset < 0x30)
189      {
190         m_ide_data = m_ide->read_cs1(space, offset & 0x07, 0xffff);
191
192         data = m_ide_data & 0xff;
193      }
188194      else if (io1_offset == 0x31)
189195      {
190196         data = m_ide_data >> 8;
r23540r23541
274280
275281      UINT8 io1_offset = offset & 0xff;
276282
277      if (io1_offset >= 0x20 && io1_offset < 0x30)
283      if (io1_offset >= 0x20 && io1_offset < 0x28)
278284      {
279285         m_ide_data = (m_ide_data & 0xff00) | data;
280286
281         m_ide->ide_bus_w(BIT(offset, 3), offset & 0x07, m_ide_data);
287         m_ide->write_cs0(space, offset & 0x07, m_ide_data, 0xffff);
282288      }
289      else if (io1_offset >= 0x28 && io1_offset < 0x30)
290      {
291         m_ide_data = (m_ide_data & 0xff00) | data;
292
293         m_ide->write_cs1(space, offset & 0x07, m_ide_data, 0xffff);
294      }
283295      else if (io1_offset == 0x31)
284296      {
285297         m_ide_data = (data << 8) | (m_ide_data & 0xff);
trunk/src/mess/machine/a2vulcan.c
r23540r23541
151151   switch (offset)
152152   {
153153      case 0:
154         m_lastdata = m_ide->ide_controller_r(0x1f0+offset, 2);
154         m_lastdata = m_ide->read_cs0(space, offset, 0xffff);
155155//          printf("IDE: read %04x\n", m_lastdata);
156156         m_last_read_was_0 = true;
157157         return m_lastdata&0xff;
r23540r23541
164164         }
165165         else
166166         {
167            return m_ide->ide_controller_r(0x1f0+offset, 1);
167            return m_ide->read_cs0(space, offset, 0xff);
168168         }
169169         break;
170170
r23540r23541
174174      case 5:
175175      case 6:
176176      case 7:
177         return m_ide->ide_controller_r(0x1f0+offset, 1);
177         return m_ide->read_cs0(space, offset, 0xff);
178178
179179      default:
180180//          printf("Read @ C0n%x\n", offset);
r23540r23541
206206            m_lastdata &= 0x00ff;
207207            m_lastdata |= (data << 8);
208208//              printf("IDE: write %04x\n", m_lastdata);
209            m_ide->ide_controller_w(0x1f0, 2, m_lastdata);
209            m_ide->write_cs0(space, offset, m_lastdata, 0xffff);
210210         }
211211         else
212212         {
213            m_ide->ide_controller_w(0x1f0+offset, 1, data);
213            m_ide->write_cs0(space, offset, data, 0xff);
214214         }
215215         break;
216216
r23540r23541
221221      case 6:
222222      case 7:
223223//          printf("%02x to IDE controller @ %x\n", data, offset);
224         m_ide->ide_controller_w(0x1f0+offset, 1, data);
224         m_ide->write_cs0(space, offset, data, 0xff);
225225         break;
226226
227227      case 9: // ROM bank
trunk/src/mess/machine/kc_d004.c
r23540r23541
454454            data_shift = 8;
455455
456456         if (io_addr == 0x06 || io_addr == 0x07 || io_addr > 0x08 || (io_addr == 0x08 && !m_lh))
457            m_ide_data = m_ide->ide_bus_r(ide_cs, io_addr & 0x07);
457         {
458            if (ide_cs == 0 )
459            {
460               m_ide_data = m_ide->read_cs0(space, io_addr & 0x07, 0xffff);
461            }
462            else
463            {
464               m_ide_data = m_ide->read_cs1(space, io_addr & 0x07, 0xffff);
465            }
466         }
458467
459468         data = (m_ide_data >> data_shift) & 0xff;
460469      }
r23540r23541
494503         m_ide_data = (data << data_shift) | (m_ide_data & (0xff00 >> data_shift));
495504
496505         if (io_addr == 0x06 || io_addr == 0x07 || io_addr > 0x08 || (io_addr == 0x08 && m_lh))
497            m_ide->ide_bus_w(ide_cs, io_addr & 0x07, m_ide_data);
506         {
507            if (ide_cs == 0)
508            {
509               m_ide->write_cs0(space, io_addr & 0x07, m_ide_data, 0xffff);
510            }
511            else
512            {
513               m_ide->write_cs1(space, io_addr & 0x07, m_ide_data, 0xffff);
514            }
515         }
498516      }
499517
500518      m_lh = (io_addr == 0x08) ? !m_lh : ((io_addr > 0x08) ? 0 : m_lh);
trunk/src/mess/machine/a2zipdrive.c
r23540r23541
116116      case 5:
117117      case 6:
118118      case 7:
119         return m_ide->ide_controller_r(0x1f0+offset, 1);
119         return m_ide->read_cs0(space, offset, 0xff);
120120
121121      case 8: // data port
122         m_lastdata = m_ide->ide_controller_r(0x1f0, 2);
122         m_lastdata = m_ide->read_cs0(space, offset, 0xffff);
123123//          printf("%04x @ IDE data\n", m_lastdata);
124124         return m_lastdata&0xff;
125125
r23540r23541
152152      case 6:
153153      case 7:
154154//          printf("%02x to IDE controller @ %x\n", data, offset);
155         m_ide->ide_controller_w(0x1f0+offset, 1, data);
155         m_ide->write_cs0(space, offset, data, 0xff);
156156         break;
157157
158158      case 8:
r23540r23541
164164//          printf("%02x to IDE data hi\n", data);
165165         m_lastdata &= 0x00ff;
166166         m_lastdata |= (data << 8);
167         m_ide->ide_controller_w(0x1f0, 2, m_lastdata);
167         m_ide->write_cs0(space, offset, m_lastdata, 0xffff);
168168         break;
169169
170170      default:
trunk/src/mess/machine/isa_ide.c
r23540r23541
99#include "machine/idectrl.h"
1010#include "imagedev/harddriv.h"
1111
12READ16_MEMBER(isa16_ide_device::ide16_r)
13{
14   return m_ide->ide_controller16_r(space, 0x1f0/2 + offset, mem_mask);
15}
16
17WRITE16_MEMBER(isa16_ide_device::ide16_w)
18{
19   m_ide->ide_controller16_w(space, 0x1f0/2 + offset, data, mem_mask);
20}
21
2212READ8_MEMBER(isa16_ide_device::ide16_alt_r )
2313{
24   return m_ide->ide_controller16_r(space, 0x3f6/2, 0x00ff);
14   return m_ide->read_cs1_pc(space, 6/2, 0xff);
2515}
2616
2717WRITE8_MEMBER(isa16_ide_device::ide16_alt_w )
2818{
29   m_ide->ide_controller16_w(space, 0x3f6/2, data, 0x00ff);
19   m_ide->write_cs1_pc(space, 6/2, data, 0xff);
3020}
3121
3222DEVICE_ADDRESS_MAP_START(map, 16, isa16_ide_device)
33   AM_RANGE(0x0, 0x7) AM_READWRITE(ide16_r, ide16_w)
23   AM_RANGE(0x0, 0x7) AM_DEVREADWRITE("ide", ide_controller_device, read_cs0_pc, write_cs0_pc)
3424ADDRESS_MAP_END
3525
3626DEVICE_ADDRESS_MAP_START(alt_map, 8, isa16_ide_device)
trunk/src/mess/machine/isa_ide.h
r23540r23541
2828   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
2929   DECLARE_ADDRESS_MAP(map, 16);
3030   DECLARE_ADDRESS_MAP(alt_map, 8);
31   READ16_MEMBER(ide16_r);
32   WRITE16_MEMBER(ide16_w);
3331   READ8_MEMBER(ide16_alt_r);
3432   WRITE8_MEMBER(ide16_alt_w);
3533protected:
trunk/src/mess/includes/bebox.h
r23540r23541
3737         m_pic8259_1(*this, "pic8259_1"),
3838         m_pic8259_2(*this, "pic8259_2"),
3939         m_pit8254(*this, "pit8254"),
40         m_ram(*this, RAM_TAG),
41         m_ide(*this, "ide")
40         m_ram(*this, RAM_TAG)
4241   {
4342   }
4443
r23540r23541
5150   required_device<pic8259_device> m_pic8259_2;
5251   required_device<pit8254_device> m_pit8254;
5352   required_device<ram_device> m_ram;
54   required_device<ide_controller_device> m_ide;
5553   UINT32 m_cpu_imask[2];
5654   UINT32 m_interrupts;
5755   UINT32 m_crossproc_interrupts;
r23540r23541
7876   DECLARE_READ64_MEMBER(bebox_cpu1_imask_r);
7977   DECLARE_READ64_MEMBER(bebox_interrupt_sources_r);
8078   DECLARE_READ64_MEMBER(bebox_crossproc_interrupts_r);
81   DECLARE_READ8_MEMBER(bebox_800001F0_r);
82   DECLARE_READ64_MEMBER(bebox_800003F0_r);
8379   DECLARE_READ64_MEMBER(bebox_interrupt_ack_r);
8480   DECLARE_READ8_MEMBER(bebox_page_r);
8581   DECLARE_READ8_MEMBER(bebox_80000480_r);
trunk/src/mess/drivers/bebox.c
r23540r23541
5353   AM_RANGE(0x80000080, 0x8000009F) AM_READWRITE8(bebox_page_r, bebox_page_w, U64(0xffffffffffffffff) )
5454   AM_RANGE(0x800000A0, 0x800000BF) AM_DEVREADWRITE8("pic8259_2", pic8259_device, read, write, U64(0xffffffffffffffff) )
5555   AM_RANGE(0x800000C0, 0x800000DF) AM_READWRITE8(at_dma8237_1_r, at_dma8237_1_w, U64(0xffffffffffffffff))
56   AM_RANGE(0x800001F0, 0x800001F7) AM_READWRITE8(bebox_800001F0_r, bebox_800001F0_w, U64(0xffffffffffffffff) )
56   AM_RANGE(0x800001F0, 0x800001F7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, U64(0xffffffffffffffff) )
5757   AM_RANGE(0x800002F8, 0x800002FF) AM_DEVREADWRITE8( "ns16550_1", ns16550_device, ins8250_r, ins8250_w, U64(0xffffffffffffffff) )
5858   AM_RANGE(0x80000380, 0x80000387) AM_DEVREADWRITE8( "ns16550_2", ns16550_device, ins8250_r, ins8250_w, U64(0xffffffffffffffff) )
5959   AM_RANGE(0x80000388, 0x8000038F) AM_DEVREADWRITE8( "ns16550_3", ns16550_device, ins8250_r, ins8250_w, U64(0xffffffffffffffff) )
6060   AM_RANGE(0x800003b0, 0x800003bf) AM_DEVREADWRITE8("vga", cirrus_vga_device, port_03b0_r, port_03b0_w, U64(0xffffffffffffffff))
6161   AM_RANGE(0x800003c0, 0x800003cf) AM_DEVREADWRITE8("vga", cirrus_vga_device, port_03c0_r, port_03c0_w, U64(0xffffffffffffffff))
6262   AM_RANGE(0x800003d0, 0x800003df) AM_DEVREADWRITE8("vga", cirrus_vga_device, port_03d0_r, port_03d0_w, U64(0xffffffffffffffff))
63   AM_RANGE(0x800003F0, 0x800003F7) AM_READWRITE(bebox_800003F0_r, bebox_800003F0_w )
63   AM_RANGE(0x800003F0, 0x800003F7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, U64(0xffffffffffffffff) )
6464   AM_RANGE(0x800003F0, 0x800003F7) AM_DEVICE8( "smc37c78", smc37c78_device, map, U64(0xffffffffffffffff) )
6565   AM_RANGE(0x800003F8, 0x800003FF) AM_DEVREADWRITE8( "ns16550_0",ns16550_device,  ins8250_r, ins8250_w, U64(0xffffffffffffffff) )
6666   AM_RANGE(0x80000480, 0x8000048F) AM_READWRITE8(bebox_80000480_r, bebox_80000480_w, U64(0xffffffffffffffff) )

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