trunk/src/mess/drivers/wswan.c
| r22941 | r22942 | |
| 38 | 38 | AM_RANGE(0x00000, 0x03fff) AM_RAM /* 16kb RAM / 4 colour tiles */ |
| 39 | 39 | AM_RANGE(0x04000, 0x0ffff) AM_NOP /* nothing */ |
| 40 | 40 | AM_RANGE(0x10000, 0x1ffff) AM_READWRITE(wswan_sram_r, wswan_sram_w) /* SRAM bank */ |
| 41 | | AM_RANGE(0x20000, 0x2ffff) AM_ROMBANK("bank2") /* ROM bank 1 */ |
| 42 | | AM_RANGE(0x30000, 0x3ffff) AM_ROMBANK("bank3") /* ROM bank 2 */ |
| 43 | | AM_RANGE(0x40000, 0x4ffff) AM_ROMBANK("bank4") /* ROM bank 3 */ |
| 44 | | AM_RANGE(0x50000, 0x5ffff) AM_ROMBANK("bank5") /* ROM bank 4 */ |
| 45 | | AM_RANGE(0x60000, 0x6ffff) AM_ROMBANK("bank6") /* ROM bank 5 */ |
| 46 | | AM_RANGE(0x70000, 0x7ffff) AM_ROMBANK("bank7") /* ROM bank 6 */ |
| 47 | | AM_RANGE(0x80000, 0x8ffff) AM_ROMBANK("bank8") /* ROM bank 7 */ |
| 48 | | AM_RANGE(0x90000, 0x9ffff) AM_ROMBANK("bank9") /* ROM bank 8 */ |
| 49 | | AM_RANGE(0xA0000, 0xAffff) AM_ROMBANK("bank10") /* ROM bank 9 */ |
| 50 | | AM_RANGE(0xB0000, 0xBffff) AM_ROMBANK("bank11") /* ROM bank 10 */ |
| 51 | | AM_RANGE(0xC0000, 0xCffff) AM_ROMBANK("bank12") /* ROM bank 11 */ |
| 52 | | AM_RANGE(0xD0000, 0xDffff) AM_ROMBANK("bank13") /* ROM bank 12 */ |
| 53 | | AM_RANGE(0xE0000, 0xEffff) AM_ROMBANK("bank14") /* ROM bank 13 */ |
| 54 | | AM_RANGE(0xF0000, 0xFffff) AM_ROMBANK("bank15") /* ROM bank 14 */ |
| 41 | AM_RANGE(0x20000, 0x2ffff) AM_ROMBANK("rom1") /* ROM bank 1 */ |
| 42 | AM_RANGE(0x30000, 0x3ffff) AM_ROMBANK("rom2") /* ROM bank 2 */ |
| 43 | AM_RANGE(0x40000, 0x4ffff) AM_ROMBANK("rom3") /* ROM bank 3 */ |
| 44 | AM_RANGE(0x50000, 0x5ffff) AM_ROMBANK("rom4") /* ROM bank 4 */ |
| 45 | AM_RANGE(0x60000, 0x6ffff) AM_ROMBANK("rom5") /* ROM bank 5 */ |
| 46 | AM_RANGE(0x70000, 0x7ffff) AM_ROMBANK("rom6") /* ROM bank 6 */ |
| 47 | AM_RANGE(0x80000, 0x8ffff) AM_ROMBANK("rom7") /* ROM bank 7 */ |
| 48 | AM_RANGE(0x90000, 0x9ffff) AM_ROMBANK("rom8") /* ROM bank 8 */ |
| 49 | AM_RANGE(0xa0000, 0xaffff) AM_ROMBANK("rom9") /* ROM bank 9 */ |
| 50 | AM_RANGE(0xb0000, 0xbffff) AM_ROMBANK("rom10") /* ROM bank 10 */ |
| 51 | AM_RANGE(0xc0000, 0xcffff) AM_ROMBANK("rom11") /* ROM bank 11 */ |
| 52 | AM_RANGE(0xd0000, 0xdffff) AM_ROMBANK("rom12") /* ROM bank 12 */ |
| 53 | AM_RANGE(0xe0000, 0xeffff) AM_ROMBANK("rom13") /* ROM bank 13 */ |
| 54 | AM_RANGE(0xf0000, 0xfffff) AM_ROMBANK("rom14") /* ROM bank 14 */ |
| 55 | 55 | ADDRESS_MAP_END |
| 56 | 56 | |
| 57 | 57 | static ADDRESS_MAP_START (wscolor_mem, AS_PROGRAM, 8, wswan_state) |
| 58 | 58 | AM_RANGE(0x00000, 0x0ffff) AM_RAM /* 16kb RAM / 4 colour tiles, 16 colour tiles + palettes */ |
| 59 | 59 | AM_RANGE(0x10000, 0x1ffff) AM_READWRITE(wswan_sram_r, wswan_sram_w) /* SRAM bank */ |
| 60 | | AM_RANGE(0x20000, 0x2ffff) AM_ROMBANK("bank2") /* ROM bank 1 */ |
| 61 | | AM_RANGE(0x30000, 0x3ffff) AM_ROMBANK("bank3") /* ROM bank 2 */ |
| 62 | | AM_RANGE(0x40000, 0x4ffff) AM_ROMBANK("bank4") /* ROM bank 3 */ |
| 63 | | AM_RANGE(0x50000, 0x5ffff) AM_ROMBANK("bank5") /* ROM bank 4 */ |
| 64 | | AM_RANGE(0x60000, 0x6ffff) AM_ROMBANK("bank6") /* ROM bank 5 */ |
| 65 | | AM_RANGE(0x70000, 0x7ffff) AM_ROMBANK("bank7") /* ROM bank 6 */ |
| 66 | | AM_RANGE(0x80000, 0x8ffff) AM_ROMBANK("bank8") /* ROM bank 7 */ |
| 67 | | AM_RANGE(0x90000, 0x9ffff) AM_ROMBANK("bank9") /* ROM bank 8 */ |
| 68 | | AM_RANGE(0xA0000, 0xAffff) AM_ROMBANK("bank10") /* ROM bank 9 */ |
| 69 | | AM_RANGE(0xB0000, 0xBffff) AM_ROMBANK("bank11") /* ROM bank 10 */ |
| 70 | | AM_RANGE(0xC0000, 0xCffff) AM_ROMBANK("bank12") /* ROM bank 11 */ |
| 71 | | AM_RANGE(0xD0000, 0xDffff) AM_ROMBANK("bank13") /* ROM bank 12 */ |
| 72 | | AM_RANGE(0xE0000, 0xEffff) AM_ROMBANK("bank14") /* ROM bank 13 */ |
| 73 | | AM_RANGE(0xF0000, 0xFffff) AM_ROMBANK("bank15") /* ROM bank 14 */ |
| 60 | AM_RANGE(0x20000, 0x2ffff) AM_ROMBANK("rom1") /* ROM bank 1 */ |
| 61 | AM_RANGE(0x30000, 0x3ffff) AM_ROMBANK("rom2") /* ROM bank 2 */ |
| 62 | AM_RANGE(0x40000, 0x4ffff) AM_ROMBANK("rom3") /* ROM bank 3 */ |
| 63 | AM_RANGE(0x50000, 0x5ffff) AM_ROMBANK("rom4") /* ROM bank 4 */ |
| 64 | AM_RANGE(0x60000, 0x6ffff) AM_ROMBANK("rom5") /* ROM bank 5 */ |
| 65 | AM_RANGE(0x70000, 0x7ffff) AM_ROMBANK("rom6") /* ROM bank 6 */ |
| 66 | AM_RANGE(0x80000, 0x8ffff) AM_ROMBANK("rom7") /* ROM bank 7 */ |
| 67 | AM_RANGE(0x90000, 0x9ffff) AM_ROMBANK("rom8") /* ROM bank 8 */ |
| 68 | AM_RANGE(0xa0000, 0xaffff) AM_ROMBANK("rom9") /* ROM bank 9 */ |
| 69 | AM_RANGE(0xb0000, 0xbffff) AM_ROMBANK("rom10") /* ROM bank 10 */ |
| 70 | AM_RANGE(0xc0000, 0xcffff) AM_ROMBANK("rom11") /* ROM bank 11 */ |
| 71 | AM_RANGE(0xd0000, 0xdffff) AM_ROMBANK("rom12") /* ROM bank 12 */ |
| 72 | AM_RANGE(0xe0000, 0xeffff) AM_ROMBANK("rom13") /* ROM bank 13 */ |
| 73 | AM_RANGE(0xf0000, 0xfffff) AM_ROMBANK("rom14") /* ROM bank 14 */ |
| 74 | 74 | ADDRESS_MAP_END |
| 75 | 75 | |
| 76 | 76 | static ADDRESS_MAP_START (wswan_io, AS_IO, 8, wswan_state) |
trunk/src/mess/machine/wswan.c
| r22941 | r22942 | |
| 199 | 199 | } |
| 200 | 200 | } |
| 201 | 201 | |
| 202 | void wswan_state::wswan_setup_banks() |
| 203 | { |
| 204 | static const char *rom_bank_tags[14] = { "rom1", "rom2", "rom3", "rom4", "rom5", "rom6", "rom7", |
| 205 | "rom8", "rom9", "rom10", "rom11", "rom12", "rom13", "rom14" }; |
| 206 | for (int i = 0; i < 14; i++) |
| 207 | m_rom_bank[i] = membank(rom_bank_tags[i]); |
| 208 | } |
| 209 | |
| 210 | void wswan_state::wswan_register_save() |
| 211 | { |
| 212 | save_item(NAME(m_ws_portram)); |
| 213 | save_item(NAME(m_internal_eeprom)); |
| 214 | save_item(NAME(m_bios_disabled)); |
| 215 | save_item(NAME(m_rotate)); |
| 216 | save_item(NAME(m_bank_base)); |
| 217 | |
| 218 | save_item(NAME(m_vdp.layer_bg_enable)); |
| 219 | save_item(NAME(m_vdp.layer_fg_enable)); |
| 220 | save_item(NAME(m_vdp.sprites_enable)); |
| 221 | save_item(NAME(m_vdp.window_sprites_enable)); |
| 222 | save_item(NAME(m_vdp.window_fg_mode)); |
| 223 | save_item(NAME(m_vdp.current_line)); |
| 224 | save_item(NAME(m_vdp.line_compare)); |
| 225 | save_item(NAME(m_vdp.sprite_table_address)); |
| 226 | save_item(NAME(m_vdp.sprite_table_buffer)); |
| 227 | save_item(NAME(m_vdp.sprite_first)); |
| 228 | save_item(NAME(m_vdp.sprite_count)); |
| 229 | save_item(NAME(m_vdp.layer_bg_address)); |
| 230 | save_item(NAME(m_vdp.layer_fg_address)); |
| 231 | save_item(NAME(m_vdp.window_fg_left)); |
| 232 | save_item(NAME(m_vdp.window_fg_top)); |
| 233 | save_item(NAME(m_vdp.window_fg_right)); |
| 234 | save_item(NAME(m_vdp.window_fg_bottom)); |
| 235 | save_item(NAME(m_vdp.window_sprites_left)); |
| 236 | save_item(NAME(m_vdp.window_sprites_top)); |
| 237 | save_item(NAME(m_vdp.window_sprites_right)); |
| 238 | save_item(NAME(m_vdp.window_sprites_bottom)); |
| 239 | save_item(NAME(m_vdp.layer_bg_scroll_x)); |
| 240 | save_item(NAME(m_vdp.layer_bg_scroll_y)); |
| 241 | save_item(NAME(m_vdp.layer_fg_scroll_x)); |
| 242 | save_item(NAME(m_vdp.layer_fg_scroll_y)); |
| 243 | save_item(NAME(m_vdp.lcd_enable)); |
| 244 | save_item(NAME(m_vdp.icons)); |
| 245 | save_item(NAME(m_vdp.color_mode)); |
| 246 | save_item(NAME(m_vdp.colors_16)); |
| 247 | save_item(NAME(m_vdp.tile_packed)); |
| 248 | save_item(NAME(m_vdp.timer_hblank_enable)); |
| 249 | save_item(NAME(m_vdp.timer_hblank_mode)); |
| 250 | save_item(NAME(m_vdp.timer_hblank_reload)); |
| 251 | save_item(NAME(m_vdp.timer_vblank_enable)); |
| 252 | save_item(NAME(m_vdp.timer_vblank_mode)); |
| 253 | save_item(NAME(m_vdp.timer_vblank_reload)); |
| 254 | save_item(NAME(m_vdp.timer_vblank_count)); |
| 255 | save_item(NAME(m_vdp.main_palette)); |
| 256 | |
| 257 | save_item(NAME(m_eeprom.mode)); |
| 258 | save_item(NAME(m_eeprom.address)); |
| 259 | save_item(NAME(m_eeprom.command)); |
| 260 | save_item(NAME(m_eeprom.start)); |
| 261 | save_item(NAME(m_eeprom.write_enabled)); |
| 262 | save_item(NAME(m_eeprom.size)); |
| 263 | if (m_eeprom.size) |
| 264 | save_pointer(NAME(m_eeprom.data), m_eeprom.size); |
| 265 | |
| 266 | save_item(NAME(m_rtc.present)); |
| 267 | save_item(NAME(m_rtc.setting)); |
| 268 | save_item(NAME(m_rtc.year)); |
| 269 | save_item(NAME(m_rtc.month)); |
| 270 | save_item(NAME(m_rtc.day)); |
| 271 | save_item(NAME(m_rtc.day_of_week)); |
| 272 | save_item(NAME(m_rtc.hour)); |
| 273 | save_item(NAME(m_rtc.minute)); |
| 274 | save_item(NAME(m_rtc.second)); |
| 275 | save_item(NAME(m_rtc.index)); |
| 276 | |
| 277 | save_item(NAME(m_sound_dma.source)); |
| 278 | save_item(NAME(m_sound_dma.size)); |
| 279 | save_item(NAME(m_sound_dma.enable)); |
| 280 | |
| 281 | machine().save().register_postload(save_prepost_delegate(FUNC(wswan_state::wswan_postload), this)); |
| 282 | } |
| 283 | |
| 284 | void wswan_state::wswan_postload() |
| 285 | { |
| 286 | address_space &space = m_maincpu->space(AS_PROGRAM); |
| 287 | // restore the vdp pointers |
| 288 | m_vdp.vram = (UINT8*)space.get_read_ptr(0); |
| 289 | m_vdp.palette_vram = (UINT8*)space.get_read_ptr(( m_system_type == TYPE_WSC ) ? 0xFE00 : 0 ); |
| 290 | // restore banks |
| 291 | for (int i = 0; i < 14; i++) |
| 292 | m_rom_bank[i]->set_entry(m_bank_base[i]); |
| 293 | } |
| 294 | |
| 295 | |
| 202 | 296 | void wswan_state::machine_start() |
| 203 | 297 | { |
| 204 | 298 | m_ws_bios_bank = NULL; |
| r22941 | r22942 | |
| 208 | 302 | m_vdp.timer->adjust( attotime::from_ticks( 256, 3072000 ), 0, attotime::from_ticks( 256, 3072000 ) ); |
| 209 | 303 | |
| 210 | 304 | wswan_setup_bios(); |
| 305 | wswan_setup_banks(); |
| 306 | wswan_register_save(); |
| 211 | 307 | |
| 212 | 308 | /* Set up RTC timer */ |
| 213 | | if ( m_rtc.present ) |
| 309 | if (m_rtc.present) |
| 214 | 310 | machine().scheduler().timer_pulse(attotime::from_seconds(1), timer_expired_delegate(FUNC(wswan_state::wswan_rtc_callback),this)); |
| 215 | 311 | |
| 216 | 312 | machine().device<nvram_device>("nvram")->set_base(m_internal_eeprom, INTERNAL_EEPROM_SIZE); |
| r22941 | r22942 | |
| 225 | 321 | m_vdp.timer->adjust( attotime::from_ticks( 256, 3072000 ), 0, attotime::from_ticks( 256, 3072000 ) ); |
| 226 | 322 | |
| 227 | 323 | wswan_setup_bios(); |
| 324 | wswan_setup_banks(); |
| 325 | wswan_register_save(); |
| 228 | 326 | |
| 229 | 327 | /* Set up RTC timer */ |
| 230 | | if ( m_rtc.present ) |
| 328 | if (m_rtc.present) |
| 231 | 329 | machine().scheduler().timer_pulse(attotime::from_seconds(1), timer_expired_delegate(FUNC(wswan_state::wswan_rtc_callback),this)); |
| 232 | 330 | |
| 233 | 331 | machine().device<nvram_device>("nvram")->set_base(m_internal_eeprom, INTERNAL_EEPROM_SIZE); |
| r22941 | r22942 | |
| 235 | 333 | |
| 236 | 334 | void wswan_state::machine_reset() |
| 237 | 335 | { |
| 238 | | address_space &space = m_maincpu->space( AS_PROGRAM ); |
| 336 | address_space &space = m_maincpu->space(AS_PROGRAM); |
| 239 | 337 | |
| 240 | 338 | /* Intialize ports */ |
| 241 | | memcpy( m_ws_portram, ws_portram_init, 256 ); |
| 339 | memcpy(m_ws_portram, ws_portram_init, 256); |
| 242 | 340 | |
| 243 | 341 | /* Initialize VDP */ |
| 244 | | memset( &m_vdp, 0, sizeof( m_vdp ) ); |
| 342 | memset(&m_vdp, 0, sizeof(m_vdp)); |
| 245 | 343 | |
| 246 | 344 | m_vdp.vram = (UINT8*)space.get_read_ptr(0); |
| 247 | 345 | m_vdp.palette_vram = (UINT8*)space.get_read_ptr(( m_system_type == TYPE_WSC ) ? 0xFE00 : 0 ); |
| r22941 | r22942 | |
| 254 | 352 | target->set_view(m_rotate); |
| 255 | 353 | |
| 256 | 354 | /* Initialize sound DMA */ |
| 257 | | memset( &m_sound_dma, 0, sizeof( m_sound_dma ) ); |
| 355 | memset(&m_sound_dma, 0, sizeof(m_sound_dma)); |
| 258 | 356 | |
| 259 | 357 | /* Switch in the banks */ |
| 260 | | membank( "bank2" )->set_base( m_ROMMap[(m_ROMBanks - 1) & (m_ROMBanks - 1)] ); |
| 261 | | membank( "bank3" )->set_base( m_ROMMap[(m_ROMBanks - 1) & (m_ROMBanks - 1)] ); |
| 262 | | membank( "bank4" )->set_base( m_ROMMap[(m_ROMBanks - 12) & (m_ROMBanks - 1)] ); |
| 263 | | membank( "bank5" )->set_base( m_ROMMap[(m_ROMBanks - 11) & (m_ROMBanks - 1)] ); |
| 264 | | membank( "bank6" )->set_base( m_ROMMap[(m_ROMBanks - 10) & (m_ROMBanks - 1)] ); |
| 265 | | membank( "bank7" )->set_base( m_ROMMap[(m_ROMBanks - 9) & (m_ROMBanks - 1)] ); |
| 266 | | membank( "bank8" )->set_base( m_ROMMap[(m_ROMBanks - 8) & (m_ROMBanks - 1)] ); |
| 267 | | membank( "bank9" )->set_base( m_ROMMap[(m_ROMBanks - 7) & (m_ROMBanks - 1)] ); |
| 268 | | membank( "bank10" )->set_base( m_ROMMap[(m_ROMBanks - 6) & (m_ROMBanks - 1)] ); |
| 269 | | membank( "bank11" )->set_base( m_ROMMap[(m_ROMBanks - 5) & (m_ROMBanks - 1)] ); |
| 270 | | membank( "bank12" )->set_base( m_ROMMap[(m_ROMBanks - 4) & (m_ROMBanks - 1)] ); |
| 271 | | membank( "bank13" )->set_base( m_ROMMap[(m_ROMBanks - 3) & (m_ROMBanks - 1)] ); |
| 272 | | membank( "bank14" )->set_base( m_ROMMap[(m_ROMBanks - 2) & (m_ROMBanks - 1)] ); |
| 358 | for (int bank = 0; bank < 14; bank++) |
| 359 | { |
| 360 | for (int i = 0; i < m_ROMBanks; i++) |
| 361 | m_rom_bank[bank]->configure_entries(i, 1, m_ROMMap[i], 0x10000); |
| 362 | } |
| 363 | m_rom_bank[13]->configure_entries(m_ROMBanks, 1, m_ws_bios_bank, 0x10000); |
| 364 | |
| 365 | m_bank_base[0] = (m_ROMBanks - 1) & (m_ROMBanks - 1); |
| 366 | m_bank_base[1] = (m_ROMBanks - 1) & (m_ROMBanks - 1); |
| 367 | m_bank_base[2] = (m_ROMBanks - 12) & (m_ROMBanks - 1); |
| 368 | m_bank_base[3] = (m_ROMBanks - 11) & (m_ROMBanks - 1); |
| 369 | m_bank_base[4] = (m_ROMBanks - 10) & (m_ROMBanks - 1); |
| 370 | m_bank_base[5] = (m_ROMBanks - 9) & (m_ROMBanks - 1); |
| 371 | m_bank_base[6] = (m_ROMBanks - 8) & (m_ROMBanks - 1); |
| 372 | m_bank_base[7] = (m_ROMBanks - 7) & (m_ROMBanks - 1); |
| 373 | m_bank_base[8] = (m_ROMBanks - 6) & (m_ROMBanks - 1); |
| 374 | m_bank_base[9] = (m_ROMBanks - 5) & (m_ROMBanks - 1); |
| 375 | m_bank_base[10] = (m_ROMBanks - 4) & (m_ROMBanks - 1); |
| 376 | m_bank_base[11] = (m_ROMBanks - 3) & (m_ROMBanks - 1); |
| 377 | m_bank_base[12] = (m_ROMBanks - 2) & (m_ROMBanks - 1); |
| 378 | m_bank_base[13] = m_ROMBanks; // the last bank is mapped to bios at start! |
| 379 | |
| 273 | 380 | m_bios_disabled = 0; |
| 274 | | membank( "bank15" )->set_base( m_ws_bios_bank ); |
| 275 | | // membank( 15 )->set_base( m_ROMMap[(m_ROMBanks - 1) & (m_ROMBanks - 1)] ); |
| 381 | |
| 382 | for (int i = 0; i < 14; i++) |
| 383 | m_rom_bank[i]->set_entry(m_bank_base[i]); |
| 276 | 384 | } |
| 277 | 385 | |
| 278 | 386 | READ8_MEMBER( wswan_state::wswan_sram_r ) |
| r22941 | r22942 | |
| 846 | 954 | Bit 0-3 - Master volume |
| 847 | 955 | Bit 4-7 - Unknown |
| 848 | 956 | */ |
| 849 | | machine().device<wswan_sound_device>("custom")->wswan_sound_port_w( space, offset, data ); |
| 957 | m_sound->port_w( space, offset, data ); |
| 850 | 958 | break; |
| 851 | 959 | case 0xa0: /* Hardware type - this is probably read only |
| 852 | 960 | Bit 0 - Enable cartridge slot and/or disable bios |
| 853 | 961 | Bit 1 - Hardware type: 0 = WS, 1 = WSC |
| 854 | 962 | Bit 2-7 - Unknown |
| 855 | 963 | */ |
| 856 | | if ( ( data & 0x01 ) && !m_bios_disabled ) |
| 964 | if ((data & 0x01) && !m_bios_disabled) |
| 857 | 965 | { |
| 858 | 966 | m_bios_disabled = 1; |
| 859 | | membank( "bank15" )->set_base( m_ROMMap[ ( ( ( m_ws_portram[0xc0] & 0x0F ) << 4 ) | 15 ) & ( m_ROMBanks - 1 ) ] ); |
| 967 | m_bank_base[13] = (((m_ws_portram[0xc0] & 0x0f) << 4) | 15) & (m_ROMBanks - 1); |
| 968 | m_rom_bank[13]->set_entry(m_bank_base[13]); |
| 860 | 969 | } |
| 861 | 970 | break; |
| 862 | 971 | case 0xa2: /* Timer control |
| r22941 | r22942 | |
| 1050 | 1159 | logerror( "Unsupported internal EEPROM command: %X\n", data ); |
| 1051 | 1160 | } |
| 1052 | 1161 | break; |
| 1053 | | case 0xc0: /* ROM bank select for banks 4-15 |
| 1054 | | Bit 0-3 - ROM bank base register for banks 4-15 |
| 1055 | | Bit 4-7 - Unknown |
| 1056 | | */ |
| 1057 | | membank( "bank4" )->set_base( m_ROMMap[ ( ( ( data & 0x0F ) << 4 ) | 4 ) & ( m_ROMBanks - 1 ) ] ); |
| 1058 | | membank( "bank5" )->set_base( m_ROMMap[ ( ( ( data & 0x0F ) << 4 ) | 5 ) & ( m_ROMBanks - 1 ) ] ); |
| 1059 | | membank( "bank6" )->set_base( m_ROMMap[ ( ( ( data & 0x0F ) << 4 ) | 6 ) & ( m_ROMBanks - 1 ) ] ); |
| 1060 | | membank( "bank7" )->set_base( m_ROMMap[ ( ( ( data & 0x0F ) << 4 ) | 7 ) & ( m_ROMBanks - 1 ) ] ); |
| 1061 | | membank( "bank8" )->set_base( m_ROMMap[ ( ( ( data & 0x0F ) << 4 ) | 8 ) & ( m_ROMBanks - 1 ) ] ); |
| 1062 | | membank( "bank9" )->set_base( m_ROMMap[ ( ( ( data & 0x0F ) << 4 ) | 9 ) & ( m_ROMBanks - 1 ) ] ); |
| 1063 | | membank( "bank10" )->set_base( m_ROMMap[ ( ( ( data & 0x0F ) << 4 ) | 10 ) & ( m_ROMBanks - 1 ) ] ); |
| 1064 | | membank( "bank11" )->set_base( m_ROMMap[ ( ( ( data & 0x0F ) << 4 ) | 11 ) & ( m_ROMBanks - 1 ) ] ); |
| 1065 | | membank( "bank12" )->set_base( m_ROMMap[ ( ( ( data & 0x0F ) << 4 ) | 12 ) & ( m_ROMBanks - 1 ) ] ); |
| 1066 | | membank( "bank13" )->set_base( m_ROMMap[ ( ( ( data & 0x0F ) << 4 ) | 13 ) & ( m_ROMBanks - 1 ) ] ); |
| 1067 | | membank( "bank14" )->set_base( m_ROMMap[ ( ( ( data & 0x0F ) << 4 ) | 14 ) & ( m_ROMBanks - 1 ) ] ); |
| 1068 | | if ( m_bios_disabled ) |
| 1162 | case 0xc0: |
| 1163 | // Bit 0-3 - ROM bank base register for rom3-rom14 |
| 1164 | // Bit 4-7 - Unknown |
| 1165 | m_bank_base[2] = (((data & 0x0f) << 4) | 4) & (m_ROMBanks - 1); |
| 1166 | m_bank_base[3] = (((data & 0x0f) << 4) | 5) & (m_ROMBanks - 1); |
| 1167 | m_bank_base[4] = (((data & 0x0f) << 4) | 6) & (m_ROMBanks - 1); |
| 1168 | m_bank_base[5] = (((data & 0x0f) << 4) | 7) & (m_ROMBanks - 1); |
| 1169 | m_bank_base[6] = (((data & 0x0f) << 4) | 8) & (m_ROMBanks - 1); |
| 1170 | m_bank_base[7] = (((data & 0x0f) << 4) | 9) & (m_ROMBanks - 1); |
| 1171 | m_bank_base[8] = (((data & 0x0f) << 4) | 10) & (m_ROMBanks - 1); |
| 1172 | m_bank_base[9] = (((data & 0x0f) << 4) | 11) & (m_ROMBanks - 1); |
| 1173 | m_bank_base[10] = (((data & 0x0f) << 4) | 12) & (m_ROMBanks - 1); |
| 1174 | m_bank_base[11] = (((data & 0x0f) << 4) | 13) & (m_ROMBanks - 1); |
| 1175 | m_bank_base[12] = (((data & 0x0f) << 4) | 14) & (m_ROMBanks - 1); |
| 1176 | for (int i = 2; i < 13; i++) |
| 1177 | m_rom_bank[i]->set_entry(m_bank_base[i]); |
| 1178 | |
| 1179 | m_bank_base[13] = m_ROMBanks; // the last bank is mapped to bios at start! |
| 1180 | if (m_bios_disabled) |
| 1069 | 1181 | { |
| 1070 | | membank( "bank15" )->set_base( m_ROMMap[ ( ( ( data & 0x0F ) << 4 ) | 15 ) & ( m_ROMBanks - 1 ) ] ); |
| 1182 | m_bank_base[13] = (((data & 0x0f) << 4) | 14) & (m_ROMBanks - 1); |
| 1183 | m_rom_bank[13]->set_entry(m_bank_base[13]); |
| 1071 | 1184 | } |
| 1072 | 1185 | break; |
| 1073 | 1186 | case 0xc1: /* SRAM bank select |
| r22941 | r22942 | |
| 1078 | 1191 | m_eeprom.page = &m_eeprom.data[ ( data * 64 * 1024 ) & ( m_eeprom.size - 1 ) ]; |
| 1079 | 1192 | } |
| 1080 | 1193 | break; |
| 1081 | | case 0xc2: /* ROM bank select for segment 2 (0x20000 - 0x2ffff) |
| 1082 | | Bit 0-7 - ROM bank for segment 2 |
| 1083 | | */ |
| 1084 | | membank( "bank2" )->set_base( m_ROMMap[ data & ( m_ROMBanks - 1 ) ]); |
| 1194 | case 0xc2: |
| 1195 | // Bit 0-7 - ROM bank for segment 2 (0x20000 - 0x2ffff) |
| 1196 | m_bank_base[0] = data & (m_ROMBanks - 1); |
| 1197 | m_rom_bank[0]->set_entry(m_bank_base[0]); |
| 1085 | 1198 | break; |
| 1086 | | case 0xc3: /* ROM bank select for segment 3 (0x30000-0x3ffff) |
| 1087 | | Bit 0-7 - ROM bank for segment 3 |
| 1088 | | */ |
| 1089 | | membank( "bank3" )->set_base( m_ROMMap[ data & ( m_ROMBanks - 1 ) ]); |
| 1199 | case 0xc3: |
| 1200 | // Bit 0-7 - ROM bank for segment 3 (0x30000 - 0x3ffff) |
| 1201 | m_bank_base[1] = data & (m_ROMBanks - 1); |
| 1202 | m_rom_bank[1]->set_entry(m_bank_base[1]); |
| 1090 | 1203 | break; |
| 1091 | 1204 | case 0xc6: /* EEPROM address lower bits port/EEPROM address and command port |
| 1092 | 1205 | 1KBit EEPROM: |
| r22941 | r22942 | |
| 1353 | 1466 | |
| 1354 | 1467 | DEVICE_IMAGE_LOAD_MEMBER(wswan_state,wswan_cart) |
| 1355 | 1468 | { |
| 1356 | | UINT32 ii, size; |
| 1469 | UINT32 size; |
| 1357 | 1470 | const char *sram_str; |
| 1358 | 1471 | |
| 1359 | 1472 | if (image.software_entry() == NULL) |
| r22941 | r22942 | |
| 1365 | 1478 | memset(m_ws_ram, 0, 0xffff); |
| 1366 | 1479 | m_ROMBanks = size / 65536; |
| 1367 | 1480 | |
| 1368 | | for (ii = 0; ii < m_ROMBanks; ii++) |
| 1481 | for (int i = 0; i < m_ROMBanks; i++) |
| 1369 | 1482 | { |
| 1370 | | if ((m_ROMMap[ii] = auto_alloc_array(machine(), UINT8, 0x10000))) |
| 1483 | if ((m_ROMMap[i] = auto_alloc_array(machine(), UINT8, 0x10000))) |
| 1371 | 1484 | { |
| 1372 | 1485 | if (image.software_entry() == NULL) |
| 1373 | 1486 | { |
| 1374 | | if (image.fread( m_ROMMap[ii], 0x10000) != 0x10000) |
| 1487 | if (image.fread( m_ROMMap[i], 0x10000) != 0x10000) |
| 1375 | 1488 | { |
| 1376 | 1489 | image.seterror(IMAGE_ERROR_INVALIDIMAGE, "Wrongly sized ROM"); |
| 1377 | 1490 | image.message(" Wrongly sized ROM"); |
| r22941 | r22942 | |
| 1380 | 1493 | } |
| 1381 | 1494 | } |
| 1382 | 1495 | else |
| 1383 | | memcpy(m_ROMMap[ii], image.get_software_region("rom") + ii * 0x10000, 0x10000); |
| 1496 | memcpy(m_ROMMap[i], image.get_software_region("rom") + i * 0x10000, 0x10000); |
| 1384 | 1497 | } |
| 1385 | 1498 | else |
| 1386 | 1499 | { |
| r22941 | r22942 | |
| 1407 | 1520 | logerror("\tSRAM size: %s\n", sram_str); |
| 1408 | 1521 | logerror("\tFeatures: %X\n", m_ROMMap[m_ROMBanks - 1][0xfffc]); |
| 1409 | 1522 | logerror("\tRTC: %s\n", m_ROMMap[m_ROMBanks - 1][0xfffd] ? "yes" : "no"); |
| 1410 | | for (ii = 0; ii < m_ROMBanks; ii++) |
| 1523 | for (int i = 0; i < m_ROMBanks; i++) |
| 1411 | 1524 | { |
| 1412 | 1525 | int count; |
| 1413 | 1526 | for (count = 0; count < 0x10000; count++) |
| 1414 | 1527 | { |
| 1415 | | sum += m_ROMMap[ii][count]; |
| 1528 | sum += m_ROMMap[i][count]; |
| 1416 | 1529 | } |
| 1417 | 1530 | } |
| 1418 | 1531 | sum -= m_ROMMap[m_ROMBanks - 1][0xffff]; |