trunk/src/mame/drivers/stuntair.c
| r22892 | r22893 | |
|---|
| 83 | 83 | m_audiocpu(*this, "audiocpu"), |
| 84 | 84 | m_fgram(*this, "fgram"), |
| 85 | 85 | m_bgram(*this, "bgram"), |
| 86 | | m_bgattrram(*this, "bgattrram") |
| 86 | m_bgattrram(*this, "bgattrram"), |
| 87 | m_sprram(*this, "sprram") |
| 87 | 88 | { |
| 88 | 89 | m_bg_xscroll = 0; |
| 89 | 90 | } |
| r22892 | r22893 | |
|---|
| 93 | 94 | required_shared_ptr<UINT8> m_fgram; |
| 94 | 95 | required_shared_ptr<UINT8> m_bgram; |
| 95 | 96 | required_shared_ptr<UINT8> m_bgattrram; |
| 97 | required_shared_ptr<UINT8> m_sprram; |
| 96 | 98 | |
| 97 | 99 | tilemap_t *m_fg_tilemap; |
| 98 | 100 | tilemap_t *m_bg_tilemap; |
| r22892 | r22893 | |
|---|
| 128 | 130 | AM_RANGE(0xc000, 0xc7ff) AM_RAM |
| 129 | 131 | AM_RANGE(0xc800, 0xcbff) AM_RAM_WRITE(stuntair_bgattrram_w) AM_SHARE("bgattrram") // bg attr |
| 130 | 132 | AM_RANGE(0xd000, 0xd3ff) AM_RAM_WRITE(stuntair_bgram_w) AM_SHARE("bgram") // bg |
| 131 | | AM_RANGE(0xd800, 0xdfff) AM_RAM |
| 133 | AM_RANGE(0xd800, 0xdfff) AM_RAM AM_SHARE("sprram") |
| 132 | 134 | |
| 133 | | AM_RANGE(0xe000, 0xe000) AM_READ(stuntair_unk_r) |
| 134 | | AM_RANGE(0xe800, 0xe800) AM_READ(stuntair_unk_r) AM_WRITE(stuntair_bgxscroll_w) |
| 135 | AM_RANGE(0xe000, 0xe000) AM_READ_PORT("DSWB") |
| 136 | AM_RANGE(0xe800, 0xe800 )AM_READ_PORT("DSWA") AM_WRITE(stuntair_bgxscroll_w) |
| 135 | 137 | |
| 136 | | AM_RANGE(0xf000, 0xf000) AM_READ(stuntair_unk_r) |
| 138 | AM_RANGE(0xf000, 0xf000) AM_READ_PORT("IN2") |
| 137 | 139 | AM_RANGE(0xf001, 0xf001) AM_WRITENOP // might be nmi enable |
| 138 | | AM_RANGE(0xf002, 0xf002) AM_READ(stuntair_unk_r) |
| 139 | | AM_RANGE(0xf003, 0xf003) AM_READ(stuntair_unk_r) |
| 140 | AM_RANGE(0xf002, 0xf002) AM_READ_PORT("IN3") |
| 141 | AM_RANGE(0xf003, 0xf003) AM_READ_PORT("IN4") |
| 140 | 142 | // AM_RANGE(0xf004, 0xf004) AM_WRITENOP |
| 141 | 143 | // AM_RANGE(0xf005, 0xf005) AM_WRITENOP |
| 142 | 144 | // AM_RANGE(0xf006, 0xf006) AM_WRITENOP |
| r22892 | r22893 | |
|---|
| 165 | 167 | |
| 166 | 168 | |
| 167 | 169 | static INPUT_PORTS_START( stuntair ) |
| 170 | PORT_START("DSWB") // the bit order logic doesn't seem to match the info in the text.. must be wired up in an odd way, might be better to do a bitswap in the read port handler |
| 171 | PORT_DIPNAME( 0x18, 0x00, DEF_STR( Coin_A ) ) // SW 1 2 |
| 172 | PORT_DIPSETTING( 0x00, "0" ) |
| 173 | PORT_DIPSETTING( 0x08, "1" ) |
| 174 | PORT_DIPSETTING( 0x10, "2" ) |
| 175 | PORT_DIPSETTING( 0x18, "3" ) |
| 176 | PORT_DIPNAME( 0x24, 0x00, DEF_STR( Coin_B ) ) // SW 3 4 |
| 177 | PORT_DIPSETTING( 0x00, "0" ) |
| 178 | PORT_DIPSETTING( 0x04, "1" ) |
| 179 | PORT_DIPSETTING( 0x20, "2" ) |
| 180 | PORT_DIPSETTING( 0x24, "3" ) |
| 181 | PORT_DIPNAME( 0x42, 0x40, DEF_STR( Bonus_Life ) ) // SW 5 6 |
| 182 | PORT_DIPSETTING( 0x00, "10000" ) |
| 183 | PORT_DIPSETTING( 0x40, "20000" ) |
| 184 | PORT_DIPSETTING( 0x02, "30000" ) |
| 185 | PORT_DIPSETTING( 0x42, "50000" ) |
| 186 | PORT_DIPNAME( 0x81, 0x81, "Lives" ) // SW 7 8 |
| 187 | PORT_DIPSETTING( 0x00, "0" ) |
| 188 | PORT_DIPSETTING( 0x01, "1" ) |
| 189 | PORT_DIPSETTING( 0x80, "2" ) |
| 190 | PORT_DIPSETTING( 0x81, "3" ) |
| 191 | |
| 192 | PORT_START("DSWA") |
| 193 | PORT_DIPNAME( 0x10, 0x10, "DSWA:1" ) // SW1 |
| 194 | PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) |
| 195 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 196 | PORT_DIPNAME( 0x08, 0x08, "DSWA:2" ) // SW 2 |
| 197 | PORT_DIPSETTING( 0x08, DEF_STR( Off ) ) |
| 198 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 199 | PORT_DIPNAME( 0x20, 0x20, "DSWA:3" ) // SW 3 |
| 200 | PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) |
| 201 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 202 | PORT_DIPNAME( 0x04, 0x00, "Infinite Lives" ) // SW 4 |
| 203 | PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) |
| 204 | PORT_DIPSETTING( 0x04, DEF_STR( On ) ) |
| 205 | PORT_DIPNAME( 0x40, 0x40, "DSWA:5" ) |
| 206 | PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) |
| 207 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 208 | PORT_DIPNAME( 0x02, 0x02, "DSWA:6" ) |
| 209 | PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) |
| 210 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 211 | PORT_DIPNAME( 0x80, 0x80, "DSWA:7" ) |
| 212 | PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) |
| 213 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 214 | PORT_DIPNAME( 0x01, 0x01, "DSWA:8" ) |
| 215 | PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) |
| 216 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 217 | |
| 218 | PORT_START("IN2") |
| 219 | PORT_DIPNAME( 0x01, 0x01, "IN2:0" ) |
| 220 | PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) |
| 221 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 222 | PORT_DIPNAME( 0x02, 0x02, "IN2:1" ) |
| 223 | PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) |
| 224 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 225 | PORT_DIPNAME( 0x04, 0x04, "IN2:2" ) |
| 226 | PORT_DIPSETTING( 0x04, DEF_STR( Off ) ) |
| 227 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 228 | PORT_DIPNAME( 0x08, 0x08, "IN2:3" ) |
| 229 | PORT_DIPSETTING( 0x08, DEF_STR( Off ) ) |
| 230 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 231 | PORT_DIPNAME( 0x10, 0x10, "IN2:4" ) |
| 232 | PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) |
| 233 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 234 | PORT_DIPNAME( 0x20, 0x20, "IN2:5" ) |
| 235 | PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) |
| 236 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 237 | PORT_DIPNAME( 0x40, 0x40, "IN2:6" ) |
| 238 | PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) |
| 239 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 240 | PORT_DIPNAME( 0x80, 0x80, "IN2:7" ) |
| 241 | PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) |
| 242 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 243 | |
| 244 | PORT_START("IN3") |
| 245 | PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 ) |
| 246 | PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 ) |
| 247 | PORT_DIPNAME( 0x04, 0x04, "Clear Credits on Reset" ) // I doubt this is a real switch |
| 248 | PORT_DIPSETTING( 0x04, DEF_STR( Off ) ) |
| 249 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 250 | PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 ) |
| 251 | PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN2 ) |
| 252 | PORT_DIPNAME( 0x20, 0x20, "IN3:5" ) |
| 253 | PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) |
| 254 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 255 | PORT_DIPNAME( 0x40, 0x40, "IN3:6" ) |
| 256 | PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) |
| 257 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 258 | PORT_DIPNAME( 0x80, 0x80, "IN3:7" ) |
| 259 | PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) |
| 260 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 261 | |
| 262 | PORT_START("IN4") |
| 263 | PORT_DIPNAME( 0x01, 0x01, "IN4:0" ) |
| 264 | PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) |
| 265 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 266 | PORT_DIPNAME( 0x02, 0x02, "IN4:1" ) |
| 267 | PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) |
| 268 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 269 | PORT_DIPNAME( 0x04, 0x04, "IN4:2" ) |
| 270 | PORT_DIPSETTING( 0x04, DEF_STR( Off ) ) |
| 271 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 272 | PORT_DIPNAME( 0x08, 0x08, "IN4:3" ) |
| 273 | PORT_DIPSETTING( 0x08, DEF_STR( Off ) ) |
| 274 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 275 | PORT_DIPNAME( 0x10, 0x10, "IN4:4" ) |
| 276 | PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) |
| 277 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 278 | PORT_DIPNAME( 0x20, 0x20, "IN4:5" ) |
| 279 | PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) |
| 280 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 281 | PORT_DIPNAME( 0x40, 0x40, "IN4:6" ) |
| 282 | PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) |
| 283 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 284 | PORT_DIPNAME( 0x80, 0x80, "IN4:7" ) |
| 285 | PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) |
| 286 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 287 | |
| 168 | 288 | INPUT_PORTS_END |
| 169 | 289 | |
| 170 | 290 | static const gfx_layout tiles8x8_layout = |