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r22841 Wednesday 15th May, 2013 at 21:24:30 UTC by smf
changed i/o to 8/16 bit (nw)
[src/mame/drivers]twinkle.c

trunk/src/mame/drivers/twinkle.c
r22840r22841
259259   int m_output_last[ 0x100 ];
260260   int m_last_io_offset;
261261   UINT8 m_sector_buffer[ 4096 ];
262   DECLARE_WRITE32_MEMBER(twinkle_io_w);
263   DECLARE_READ32_MEMBER(twinkle_io_r);
264   DECLARE_WRITE32_MEMBER(twinkle_output_w);
265   DECLARE_WRITE32_MEMBER(serial_w);
266   DECLARE_WRITE32_MEMBER(shared_psx_w);
267   DECLARE_READ32_MEMBER(shared_psx_r);
262   DECLARE_WRITE8_MEMBER(twinkle_io_w);
263   DECLARE_READ8_MEMBER(twinkle_io_r);
264   DECLARE_WRITE16_MEMBER(twinkle_output_w);
265   DECLARE_WRITE16_MEMBER(serial_w);
266   DECLARE_WRITE8_MEMBER(shared_psx_w);
267   DECLARE_READ8_MEMBER(shared_psx_r);
268268   DECLARE_WRITE16_MEMBER(twinkle_spu_ctrl_w);
269269   DECLARE_READ16_MEMBER(twinkle_waveram_r);
270270   DECLARE_WRITE16_MEMBER(twinkle_waveram_w);
r22840r22841
440440   0, //
441441};
442442
443WRITE32_MEMBER(twinkle_state::twinkle_io_w)
443WRITE8_MEMBER(twinkle_state::twinkle_io_w)
444444{
445   if( ACCESSING_BITS_16_23 )
445   switch( offset )
446446   {
447      m_io_offset = ( data >> 16 ) & 0xff;
448   }
449   if( ACCESSING_BITS_0_7 )
450   {
451      if( m_output_last[ m_io_offset ] != ( data & 0xff ) )
447   case 0:
448      if( m_output_last[ m_io_offset ] != data )
452449      {
453         m_output_last[ m_io_offset ] = ( data & 0xff );
450         m_output_last[ m_io_offset ] = data;
454451
455452         switch( m_io_offset )
456453         {
r22840r22841
492489
493490            if( ( data & 0xfe ) != 0xfe )
494491            {
495               printf("%02x = %02x\n", m_io_offset, data & 0xff );
492               printf("%02x = %02x\n", m_io_offset, data );
496493            }
497494            break;
498495
499496         default:
500            printf( "unknown io %02x = %02x\n", m_io_offset, data & 0xff );
497            printf( "unknown io %02x = %02x\n", m_io_offset, data );
501498            break;
502499         }
503500      }
501      break;
502
503   case 1:
504      m_io_offset = data;
505      break;
504506   }
505507}
506508
507READ32_MEMBER(twinkle_state::twinkle_io_r)
509READ8_MEMBER(twinkle_state::twinkle_io_r)
508510{
509   UINT32 data = 0;
511   UINT8 data = 0;
510512
511   if( ACCESSING_BITS_0_7 )
513   switch( offset )
512514   {
515   case 0:
513516      switch( m_io_offset )
514517      {
515518         case 0x07:
516            data |= ioport( "IN0" )->read();
519            data = ioport( "IN0" )->read();
517520            break;
518521
519522         case 0x0f:
520            data |= ioport( "IN1" )->read();
523            data = ioport( "IN1" )->read();
521524            break;
522525
523526         case 0x17:
524            data |= ioport( "IN2" )->read();
527            data = ioport( "IN2" )->read();
525528            break;
526529
527530         case 0x1f:
528            data |= ioport( "IN3" )->read();
531            data = ioport( "IN3" )->read();
529532            break;
530533
531534         case 0x27:
532            data |= ioport( "IN4" )->read();
535            data = ioport( "IN4" )->read();
533536            break;
534537
535538         case 0x2f:
536            data |= ioport( "IN5" )->read();
539            data = ioport( "IN5" )->read();
537540            break;
538541
539542         default:
r22840r22841
541544            {
542545               m_last_io_offset = m_io_offset;
543546            }
544
545547            break;
546548      }
547   }
549      break;
548550
549   if( ACCESSING_BITS_8_15 )
550   {
551   case 1:
551552      /* led status? 1100 */
553      break;
552554   }
553555
554556   return data;
555557}
556558
557WRITE32_MEMBER(twinkle_state::twinkle_output_w)
559WRITE16_MEMBER(twinkle_state::twinkle_output_w)
558560{
559561   switch( offset )
560562   {
561563   case 0x00:
562564      /* offset */
563565      break;
564   case 0x02:
566   case 0x04:
565567      /* data */
566568      break;
567   case 0x04:
569   case 0x08:
568570      /* ?? */
569571      break;
570   case 0x08:
572   case 0x10:
571573      /* bit 0 = clock?? */
572574      /* bit 1 = data?? */
573575      /* bit 2 = reset?? */
574576      break;
575   case 0x0c:
577   case 0x18:
576578      /* ?? */
577579      break;
578   case 0x15:
580   case 0x30:
579581      /* ?? */
580582      break;
581   case 0x24:
583   case 0x48:
582584      /* ?? */
583585      break;
584586   }
585587}
586588
587WRITE32_MEMBER(twinkle_state::serial_w)
589WRITE16_MEMBER(twinkle_state::serial_w)
588590{
589591/*
590592    int _do = ( data >> 4 ) & 1;
r22840r22841
595597*/
596598}
597599
598WRITE32_MEMBER(twinkle_state::shared_psx_w)
600WRITE8_MEMBER(twinkle_state::shared_psx_w)
599601{
600   if (mem_mask == 0xff)
601   {
602      m_spu_shared[offset*2] = data;
603//      printf("shared_psx_w: %x to %x (%x), mask %x (PC=%x)\n", data, offset, offset*2, mem_mask, space.device().safe_pc());
604   }
605   else if (mem_mask == 0xff0000)
606   {
607      m_spu_shared[(offset*2)+1] = data;
608//      printf("shared_psx_w: %x to %x (%x), mask %x (PC=%x)\n", data, offset, (offset*2)+1, mem_mask, space.device().safe_pc());
609   }
610   else
611   {
612      fatalerror("shared_psx_w: Unknown mask %x\n", mem_mask);
613   }
602   m_spu_shared[offset] = data;
603//  printf("shared_psx_w: %x to %x, mask %x (PC=%x)\n", data, offset, mem_mask, space.device().safe_pc());
614604}
615605
616READ32_MEMBER(twinkle_state::shared_psx_r)
606READ8_MEMBER(twinkle_state::shared_psx_r)
617607{
618   UINT32 result;
608   UINT32 result = m_spu_shared[offset];
619609
620   result = m_spu_shared[offset*2] | m_spu_shared[(offset*2)+1]<<16;
610//  printf("shared_psx_r: @ %x, mask %x (PC=%x)\n", offset, mem_mask, result, space.device().safe_pc());
621611
622//  printf("shared_psx_r: @ %x (%x %x), mask %x = %x (PC=%x)\n", offset, offset*2, (offset*2)+1, mem_mask, result, space.device().safe_pc());
623
624612   result = 0; // HACK to prevent the games from freezing while we sort out the rest of the 68k's boot sequence
625613
626614   return result;
627615}
628616
629617static ADDRESS_MAP_START( main_map, AS_PROGRAM, 32, twinkle_state )
630   AM_RANGE(0x1f000000, 0x1f0007ff) AM_READWRITE(shared_psx_r, shared_psx_w)
618   AM_RANGE(0x1f000000, 0x1f0007ff) AM_READWRITE8(shared_psx_r, shared_psx_w, 0x00ff00ff)
631619   AM_RANGE(0x1f200000, 0x1f20001f) AM_DEVREADWRITE8("scsi:am53cf96", am53cf96_device, read, write, 0x00ff00ff)
632620   AM_RANGE(0x1f20a01c, 0x1f20a01f) AM_WRITENOP /* scsi? */
633621   AM_RANGE(0x1f210400, 0x1f2107ff) AM_READNOP
634   AM_RANGE(0x1f218000, 0x1f218003) AM_WRITE(watchdog_reset32_w) /* LTC1232 */
635   AM_RANGE(0x1f220000, 0x1f220003) AM_WRITE(twinkle_io_w)
636   AM_RANGE(0x1f220004, 0x1f220007) AM_READ(twinkle_io_r)
622   AM_RANGE(0x1f218000, 0x1f218003) AM_WRITE8(watchdog_reset_w, 0x000000ff) /* LTC1232 */
623   AM_RANGE(0x1f220000, 0x1f220003) AM_WRITE8(twinkle_io_w, 0x00ff00ff)
624   AM_RANGE(0x1f220004, 0x1f220007) AM_READ8(twinkle_io_r, 0x00ff00ff)
637625   AM_RANGE(0x1f230000, 0x1f230003) AM_WRITENOP
638626   AM_RANGE(0x1f240000, 0x1f240003) AM_READ_PORT("IN6")
639627   AM_RANGE(0x1f250000, 0x1f250003) AM_WRITENOP
640   AM_RANGE(0x1f260000, 0x1f260003) AM_WRITE(serial_w)
628   AM_RANGE(0x1f260000, 0x1f260003) AM_WRITE16(serial_w, 0x0000ffff)
641629   AM_RANGE(0x1f270000, 0x1f270003) AM_WRITE_PORT("OUTSEC")
642630   AM_RANGE(0x1f280000, 0x1f280003) AM_READ_PORT("INSEC")
643631   AM_RANGE(0x1f290000, 0x1f29007f) AM_DEVREADWRITE8("rtc", rtc65271_device, rtc_r, rtc_w, 0x00ff00ff)
644632   AM_RANGE(0x1f2a0000, 0x1f2a007f) AM_DEVREADWRITE8("rtc", rtc65271_device, xram_r, xram_w, 0x00ff00ff)
645   AM_RANGE(0x1f2b0000, 0x1f2b00ff) AM_WRITE(twinkle_output_w)
633   AM_RANGE(0x1f2b0000, 0x1f2b00ff) AM_WRITE16(twinkle_output_w, 0xffffffff)
646634ADDRESS_MAP_END
647635
648636/* SPU board */

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