trunk/src/mess/machine/nes_slot.c
| r22715 | r22716 | |
| 130 | 130 | m_has_trainer(FALSE), |
| 131 | 131 | m_x1_005_alt_mirroring(FALSE), |
| 132 | 132 | m_bus_conflict(TRUE), |
| 133 | m_open_bus(0), |
| 133 | 134 | m_prg_chunks(0), |
| 134 | 135 | m_prg_mask(0xffff), |
| 135 | 136 | m_chr_source(CHRRAM), |
| r22715 | r22716 | |
| 656 | 657 | |
| 657 | 658 | READ8_MEMBER(device_nes_cart_interface::read_l) |
| 658 | 659 | { |
| 659 | | return ((offset + 0x4100) & 0xff00) >> 8; // open bus |
| 660 | return m_open_bus; |
| 660 | 661 | } |
| 661 | 662 | |
| 662 | 663 | READ8_MEMBER(device_nes_cart_interface::read_m) |
| r22715 | r22716 | |
| 666 | 667 | if (m_prgram) |
| 667 | 668 | return m_prgram[offset & (m_prgram_size - 1)]; |
| 668 | 669 | |
| 669 | | return ((offset + 0x6000) & 0xff00) >> 8; // open bus |
| 670 | return m_open_bus; |
| 670 | 671 | } |
| 671 | 672 | |
| 672 | 673 | WRITE8_MEMBER(device_nes_cart_interface::write_l) |
| r22715 | r22716 | |
| 993 | 994 | READ8_MEMBER(nes_cart_slot_device::read_l) |
| 994 | 995 | { |
| 995 | 996 | if (m_cart) |
| 996 | | return m_cart->read_l(space, offset); |
| 997 | { |
| 998 | UINT8 val = m_cart->read_l(space, offset); |
| 999 | // update open bus |
| 1000 | m_cart->set_open_bus(((offset + 0x4100) & 0xff00) >> 8); |
| 1001 | return val; |
| 1002 | } |
| 997 | 1003 | else |
| 998 | 1004 | return 0xff; |
| 999 | 1005 | } |
| r22715 | r22716 | |
| 1001 | 1007 | READ8_MEMBER(nes_cart_slot_device::read_m) |
| 1002 | 1008 | { |
| 1003 | 1009 | if (m_cart) |
| 1004 | | return m_cart->read_m(space, offset); |
| 1010 | { |
| 1011 | UINT8 val = m_cart->read_m(space, offset); |
| 1012 | // update open bus |
| 1013 | m_cart->set_open_bus(((offset + 0x6000) & 0xff00) >> 8); |
| 1014 | return val; |
| 1015 | } |
| 1005 | 1016 | else |
| 1006 | 1017 | return 0xff; |
| 1007 | 1018 | } |
| r22715 | r22716 | |
| 1009 | 1020 | READ8_MEMBER(nes_cart_slot_device::read_h) |
| 1010 | 1021 | { |
| 1011 | 1022 | if (m_cart) |
| 1012 | | return m_cart->read_h(space, offset); |
| 1023 | { |
| 1024 | UINT8 val = m_cart->read_h(space, offset); |
| 1025 | // update open bus |
| 1026 | m_cart->set_open_bus(((offset + 0x8000) & 0xff00) >> 8); |
| 1027 | return val; |
| 1028 | } |
| 1013 | 1029 | else |
| 1014 | 1030 | return 0xff; |
| 1015 | 1031 | } |
| r22715 | r22716 | |
| 1017 | 1033 | READ8_MEMBER(nes_cart_slot_device::read_ex) |
| 1018 | 1034 | { |
| 1019 | 1035 | if (m_cart) |
| 1020 | | return m_cart->read_ex(space, offset); |
| 1036 | { |
| 1037 | UINT8 val = m_cart->read_ex(space, offset); |
| 1038 | // update open bus |
| 1039 | m_cart->set_open_bus(((offset + 0x4020) & 0xff00) >> 8); |
| 1040 | return val; |
| 1041 | } |
| 1021 | 1042 | else |
| 1022 | 1043 | return 0xff; |
| 1023 | 1044 | } |
| r22715 | r22716 | |
| 1030 | 1051 | WRITE8_MEMBER(nes_cart_slot_device::write_l) |
| 1031 | 1052 | { |
| 1032 | 1053 | if (m_cart) |
| 1054 | { |
| 1033 | 1055 | m_cart->write_l(space, offset, data); |
| 1056 | // update open bus |
| 1057 | m_cart->set_open_bus(((offset + 0x4100) & 0xff00) >> 8); |
| 1058 | } |
| 1034 | 1059 | } |
| 1035 | 1060 | |
| 1036 | 1061 | WRITE8_MEMBER(nes_cart_slot_device::write_m) |
| 1037 | 1062 | { |
| 1038 | 1063 | if (m_cart) |
| 1064 | { |
| 1039 | 1065 | m_cart->write_m(space, offset, data); |
| 1066 | // update open bus |
| 1067 | m_cart->set_open_bus(((offset + 0x6000) & 0xff00) >> 8); |
| 1068 | } |
| 1040 | 1069 | } |
| 1041 | 1070 | |
| 1042 | 1071 | WRITE8_MEMBER(nes_cart_slot_device::write_h) |
| 1043 | 1072 | { |
| 1044 | 1073 | if (m_cart) |
| 1074 | { |
| 1045 | 1075 | m_cart->write_h(space, offset, data); |
| 1076 | // update open bus |
| 1077 | m_cart->set_open_bus(((offset + 0x8000) & 0xff00) >> 8); |
| 1078 | } |
| 1046 | 1079 | } |
| 1047 | 1080 | |
| 1048 | 1081 | WRITE8_MEMBER(nes_cart_slot_device::write_ex) |
| 1049 | 1082 | { |
| 1050 | 1083 | if (m_cart) |
| 1084 | { |
| 1051 | 1085 | m_cart->write_ex(space, offset, data); |
| 1086 | // update open bus |
| 1087 | m_cart->set_open_bus(((offset + 0x4020) & 0xff00) >> 8); |
| 1088 | } |
| 1052 | 1089 | } |
| 1053 | 1090 | |
| 1054 | 1091 | |
trunk/src/mess/machine/nes_slot.h
| r22715 | r22716 | |
| 192 | 192 | void set_vrc_lines(int PRG_A, int PRG_B, int CHR) { m_vrc_ls_prg_a = PRG_A; m_vrc_ls_prg_b = PRG_B; m_vrc_ls_chr = CHR; } |
| 193 | 193 | void set_x1_005_alt(bool val) { m_x1_005_alt_mirroring = val; } |
| 194 | 194 | void set_bus_conflict(bool val) { m_bus_conflict = val; } |
| 195 | void set_open_bus(UINT8 val) { m_open_bus = val; } |
| 195 | 196 | |
| 196 | 197 | UINT8* get_prg_base() { return m_prg; } |
| 197 | 198 | UINT8* get_prgram_base() { return m_prgram; } |
| r22715 | r22716 | |
| 252 | 253 | bool m_pcb_ctrl_mirror, m_four_screen_vram, m_has_trainer; |
| 253 | 254 | bool m_x1_005_alt_mirroring; // temp hack for two kind of mirroring in Taito X1-005 boards (to be replaced with pin checking) |
| 254 | 255 | bool m_bus_conflict; |
| 256 | UINT8 m_open_bus; |
| 255 | 257 | |
| 256 | 258 | // PRG |
| 257 | 259 | inline int prg_8k_bank_num(int bank); |
trunk/src/mess/machine/nes_namcot.c
| r22715 | r22716 | |
| 520 | 520 | if (m_battery && offset < m_battery_size && m_wram_enable) |
| 521 | 521 | return m_battery[offset & (m_battery_size - 1)]; |
| 522 | 522 | |
| 523 | | return ((offset + 0x6000) & 0xff00) >> 8; // open bus |
| 523 | return m_open_bus; // open bus |
| 524 | 524 | } |
| 525 | 525 | |
| 526 | 526 | WRITE8_MEMBER(nes_namcot175_device::write_m) |
| r22715 | r22716 | |
| 602 | 602 | if (m_battery && offset < m_battery_size) |
| 603 | 603 | return m_battery[offset & (m_battery_size - 1)]; |
| 604 | 604 | |
| 605 | | return ((offset + 0x6000) & 0xff00) >> 8; // open bus |
| 605 | return m_open_bus; // open bus |
| 606 | 606 | } |
| 607 | 607 | |
| 608 | 608 | WRITE8_MEMBER(nes_namcot163_device::write_m) |
trunk/src/mess/machine/nes_taito.c
| r22715 | r22716 | |
| 366 | 366 | if (offset >= 0x1f00 && m_latch == 0xa3) |
| 367 | 367 | return m_x1_005_ram[offset & 0x7f]; |
| 368 | 368 | |
| 369 | | return ((offset + 0x6000) & 0xff00) >> 8; // open bus |
| 369 | return m_open_bus; // open bus |
| 370 | 370 | } |
| 371 | 371 | |
| 372 | 372 | /*------------------------------------------------- |
| r22715 | r22716 | |
| 469 | 469 | if (offset < 0x1400 && m_reg[2] == 0x84) |
| 470 | 470 | return m_x1_017_ram[0x1000 + (offset & 0x3ff)]; |
| 471 | 471 | |
| 472 | | return ((offset + 0x6000) & 0xff00) >> 8; // open bus |
| 472 | return m_open_bus; // open bus |
| 473 | 473 | } |
trunk/src/mess/machine/nes_mmc1.c
| r22715 | r22716 | |
| 293 | 293 | return m_prgram[((bank * 0x2000) + offset) & (m_prgram_size - 1)]; |
| 294 | 294 | } |
| 295 | 295 | |
| 296 | | return ((offset + 0x6000) & 0xff00) >> 8; // open bus |
| 296 | return m_open_bus; // open bus |
| 297 | 297 | } |
| 298 | 298 | |
| 299 | 299 | // SOROM has two RAM banks, the first is not battery backed up, the second is. |
| r22715 | r22716 | |
| 324 | 324 | return m_prgram[offset & (m_prgram_size - 1)]; |
| 325 | 325 | } |
| 326 | 326 | |
| 327 | | return ((offset + 0x6000) & 0xff00) >> 8; // open bus |
| 327 | return m_open_bus; // open bus |
| 328 | 328 | } |
| 329 | 329 | |
| 330 | 330 | // MMC1A boards have no wram enable/disable bit |
| r22715 | r22716 | |
| 349 | 349 | if (m_prgram) |
| 350 | 350 | return m_prgram[((bank * 0x2000) + offset) & (m_prgram_size - 1)]; |
| 351 | 351 | |
| 352 | | return ((offset + 0x6000) & 0xff00) >> 8; // open bus |
| 352 | return m_open_bus; // open bus |
| 353 | 353 | } |
| 354 | 354 | |
| 355 | 355 | WRITE8_MEMBER(nes_sorom_a_device::write_m) |
trunk/src/mess/machine/nes_mmc3.c
| r22715 | r22716 | |
| 340 | 340 | return m_prgram[offset & (m_prgram_size - 1)]; |
| 341 | 341 | } |
| 342 | 342 | |
| 343 | | return ((offset + 0x6000) & 0xff00) >> 8; // open bus |
| 343 | return m_open_bus; // open bus |
| 344 | 344 | } |
| 345 | 345 | |
| 346 | 346 | |
| r22715 | r22716 | |
| 376 | 376 | LOG_MMC(("hkrom read_m, offset: %04x\n", offset)); |
| 377 | 377 | |
| 378 | 378 | if (offset < 0x1000) |
| 379 | | return 0xff; // here it should be open bus |
| 379 | return m_open_bus; // open bus |
| 380 | 380 | |
| 381 | 381 | if (!(m_mmc6_reg & 0xa0)) |
| 382 | | return 0xff; // here it should be open bus |
| 382 | return m_open_bus; // open bus |
| 383 | 383 | |
| 384 | 384 | if (BIT(offset, 9) && BIT(m_mmc6_reg, 7)) // access to upper half of 1k when upper read is enabled |
| 385 | 385 | return m_mmc6_ram[offset & 0x3ff]; |
trunk/src/mess/machine/nes_sunsoft_dcs.c
| r22715 | r22716 | |
| 231 | 231 | if (m_timer_on) |
| 232 | 232 | return m_subslot->m_cart->read(space, offset, mem_mask); |
| 233 | 233 | else |
| 234 | | return ((offset + 0x8000) & 0xff00) >> 8; // after the timer is off, this returns open bus... |
| 234 | return m_open_bus; // after the timer is off, this returns open bus... |
| 235 | 235 | } |
| 236 | 236 | else |
| 237 | 237 | return hi_access_rom(offset); |
| r22715 | r22716 | |
| 262 | 262 | if (m_prgram && m_wram_enable) |
| 263 | 263 | return m_prgram[offset & (m_prgram_size - 1)]; |
| 264 | 264 | |
| 265 | | return ((offset + 0x6000) & 0xff00) >> 8; // open bus |
| 265 | return m_open_bus; // open bus |
| 266 | 266 | } |
| 267 | 267 | |
| 268 | 268 | //------------------------------------------------- |
trunk/src/mess/machine/nes_multigame.c
| r22715 | r22716 | |
| 1476 | 1476 | // m_dipsetting = ioport("CARTDIPS")->read(); |
| 1477 | 1477 | |
| 1478 | 1478 | if (m_latch == 1) |
| 1479 | | return (offset & 0xff00) >> 8; // open bus |
| 1479 | return m_open_bus; // open bus |
| 1480 | 1480 | else |
| 1481 | 1481 | return hi_access_rom(offset); |
| 1482 | 1482 | } |
| r22715 | r22716 | |
| 2458 | 2458 | LOG_MMC(("bmc_gold150 read_h, offset: %04x\n", offset)); |
| 2459 | 2459 | |
| 2460 | 2460 | if (m_latch) // open bus |
| 2461 | | return (offset & 0xff00) >> 8; |
| 2461 | return m_open_bus; |
| 2462 | 2462 | else |
| 2463 | 2463 | return hi_access_rom(offset); |
| 2464 | 2464 | } |
| r22715 | r22716 | |
| 2511 | 2511 | LOG_MMC(("bmc_ch001 read_h, offset: %04x\n", offset)); |
| 2512 | 2512 | |
| 2513 | 2513 | if (m_latch && offset < 0x4000) // open bus |
| 2514 | | return (offset & 0xff00) >> 8; |
| 2514 | return m_open_bus; |
| 2515 | 2515 | else |
| 2516 | 2516 | return hi_access_rom(offset); |
| 2517 | 2517 | } |