Previous 199869 Revisions Next

r22713 Wednesday 8th May, 2013 at 17:45:07 UTC by David Haywood
improve logging details (nw)
[src/emu/machine]mcf5206e.c

trunk/src/emu/machine/mcf5206e.c
r22712r22713
405405      invalidlog("%s: invalid PPDDR_r %d\n", this->machine().describe_context(), offset);
406406      return 0;
407407   case 1: // '$1C5'
408      debuglog("%s: PPDDR_r\n", this->machine().describe_context());
408      debuglog("%s: (Port A Data Direction Register) PPDDR_r\n", this->machine().describe_context());
409409      return m_PPDDR;
410410   }
411411
r22712r22713
423423      break;
424424   case 1: // '$1C5'
425425      m_PPDDR = data;
426      debuglog("%s: PPDDR_w %02x\n", this->machine().describe_context(), data);
426      debuglog("%s: (Port A Data Direction Register) PPDDR_w %02x\n", this->machine().describe_context(), data);
427427      break;
428428   }
429429}
r22712r22713
438438      invalidlog("%s: invalid PPDAT_r %d\n", this->machine().describe_context(), offset);
439439      return 0;
440440   case 1: // '$1C9'
441      debuglog("%s: PPDAT_r\n", this->machine().describe_context());
441      debuglog("%s: (Port A Data Register) PPDAT_r\n", this->machine().describe_context());
442442      return m_PPDAT; // should use a callback.
443443   }
444444
r22712r22713
456456      break;
457457   case 1: // '$1C9'
458458      m_PPDAT = data; // should use a callback.
459      debuglog("%s: PPDAT_w %02x\n", this->machine().describe_context(), data);
459      debuglog("%s: (Port A Data Register) PPDAT_w %02x\n", this->machine().describe_context(), data);
460460      break;
461461   }
462462
r22712r22713
468468   switch (offset)
469469   {
470470   case 0:
471      debuglog("%s: MBCR_r\n", this->machine().describe_context());
471      debuglog("%s: (M-Bus Control Register) MBCR_r\n", this->machine().describe_context());
472472      return m_MBCR;
473473   case 1:
474474   case 2:
r22712r22713
486486   {
487487   case 0:
488488      m_MBCR = data;
489      debuglog("%s: MBCR_w %02x\n", this->machine().describe_context(), data);
489      debuglog("%s: (M-Bus Control Register) MBCR_w %02x\n", this->machine().describe_context(), data);
490490      break;
491491   case 1:
492492   case 2:
r22712r22713
502502   switch (offset)
503503   {
504504   case 0:
505      debuglog("%s: MFDR_r\n", this->machine().describe_context());
505      debuglog("%s: (M-Bus Frequency Divider Register) MFDR_r\n", this->machine().describe_context());
506506      return m_MFDR;
507507   case 1:
508508   case 2:
r22712r22713
520520   {
521521   case 0:
522522      m_MFDR = data;
523      debuglog("%s: MFDR_w %02x\n", this->machine().describe_context(), data);
523      debuglog("%s: (M-Bus Frequency Divider Register) MFDR_w %02x\n", this->machine().describe_context(), data);
524524      break;
525525   case 1:
526526   case 2:
r22712r22713
545545   case 0:
546546   {
547547      hack ^= (machine().rand()&0xff);
548      debuglog("%s: MBSR_r\n", this->machine().describe_context());
548      debuglog("%s: (M-Bus Status Register) MBSR_r\n", this->machine().describe_context());
549549      return m_MBSR ^ hack; // will loop on this after a while
550550   }
551551   case 1:
r22712r22713
564564   {
565565   case 0:
566566      m_MBSR = data;
567      debuglog("%s: MBSR_w %02x\n", this->machine().describe_context(), data);
567      debuglog("%s: (M-Bus Status Register) MBSR_w %02x\n", this->machine().describe_context(), data);
568568      break;
569569   case 1:
570570   case 2:
r22712r22713
587587   case 0:
588588   {
589589      hack ^= (machine().rand()&0xff);
590      debuglog("%s: MBDR_r\n", this->machine().describe_context());
590      debuglog("%s: (M-Bus Data I/O Register) MBDR_r\n", this->machine().describe_context());
591591      return m_MBDR ^ hack;
592592   }
593593   case 1:
r22712r22713
606606   {
607607   case 0:
608608      m_MBDR = data;
609      debuglog("%s: MBDR_w %02x\n", this->machine().describe_context(), data);
609      debuglog("%s: (M-Bus Data I/O Register) MBDR_w %02x\n", this->machine().describe_context(), data);
610610      break;
611611   case 1:
612612   case 2:
r22712r22713
624624   switch (offset)
625625   {
626626   case 1:
627      debuglog("%s: IMR_r %04x\n", this->machine().describe_context(), mem_mask);
627      debuglog("%s: (Interrupt Mask Register) IMR_r %04x\n", this->machine().describe_context(), mem_mask);
628628      return m_IMR;
629629   case 0:
630630      invalidlog("%s: invalid IMR_r %d %04x\n", this->machine().describe_context(), offset, mem_mask);
r22712r22713
640640   {
641641   case 1:
642642      COMBINE_DATA(&m_IMR);
643      debuglog("%s: IMR_w %04x %04x\n", this->machine().describe_context(), data, mem_mask);
643      debuglog("%s: (Interrupt Mask Register) IMR_w %04x %04x\n", this->machine().describe_context(), data, mem_mask);
644644      break;
645645   case 0:
646646      invalidlog("%s: invalid IMR_w %d, %04x %04x\n", this->machine().describe_context(), offset, data, mem_mask);
r22712r22713
681681   switch (offset)
682682   {
683683   case 0:
684      debuglogtimer("%s: TMR1_r %04x\n", this->machine().describe_context(), mem_mask);
684      debuglogtimer("%s: (Timer 1 Mode Register) TMR1_r %04x\n", this->machine().describe_context(), mem_mask);
685685      return m_TMR1;
686686   case 1:
687687      invalidlog("%s: invalid TMR1_r %d %04x\n", this->machine().describe_context(), offset, mem_mask);
r22712r22713
697697   {
698698   case 0:
699699      COMBINE_DATA(&m_TMR1);
700      debuglogtimer("%s: TMR1_w %04x %04x\n", this->machine().describe_context(), data, mem_mask);
700      debuglogtimer("%s: (Timer 1 Mode Register) TMR1_w %04x %04x\n", this->machine().describe_context(), data, mem_mask);
701701
702702      debuglogtimer("   (Prescale) PS : %02x  (Capture Edge/Interrupt) CE : %01x (Output Mode) OM : %01x  (Output Reference Interrupt En) ORI : %01x   Free Run (FRR) : %01x  Input Clock Source (ICLK) : %01x  (Reset Timer) RST : %01x  \n", (m_TMR1 & 0xff00)>>8, (m_TMR1 & 0x00c0)>>6,  (m_TMR1 & 0x0020)>>5, (m_TMR1 & 0x0010)>>4, (m_TMR1 & 0x0008)>>3, (m_TMR1 & 0x0006)>>1, (m_TMR1 & 0x0001)>>0);   
703703     
r22712r22713
724724   switch (offset)
725725   {
726726   case 0:
727      debuglogtimer("%s: TRR1_r %04x\n", this->machine().describe_context(), mem_mask);
727      debuglogtimer("%s: (Timer 1 Reference Register) TRR1_r %04x\n", this->machine().describe_context(), mem_mask);
728728      return m_TRR1;
729729   case 1:
730730      invalidlog("%s: invalid TRR1_r %d %04x\n", this->machine().describe_context(), offset, mem_mask);
r22712r22713
740740   {
741741   case 0:
742742      COMBINE_DATA(&m_TRR1);
743      debuglogtimer("%s: TRR1_w %04x %04x\n", this->machine().describe_context(), data, mem_mask);
743      debuglogtimer("%s: (Timer 1 Reference Register) TRR1_w %04x %04x\n", this->machine().describe_context(), data, mem_mask);
744744      break;
745745   case 1:
746746      debuglog("%s: invalid TRR1_w %d, %04x %04x\n", this->machine().describe_context(), offset, data, mem_mask);
r22712r22713
790790   switch (offset)
791791   {
792792   case 0:
793      debuglogtimer("%s: TCN1_r %04x\n", this->machine().describe_context(), mem_mask);
793      debuglogtimer("%s: (Timer 1 Counter) TCN1_r %04x\n", this->machine().describe_context(), mem_mask);
794794      // return 0x9c40;
795795      return 0x8ca0 -1;// m_TCN1; // this should be the counter, code has a hardcoded >= check against 8ca0.
796796   case 1:
r22712r22713
807807   {
808808   case 0:
809809      COMBINE_DATA(&m_TCN1);
810      debuglogtimer("%s: TCN1_w %04x %04x\n", this->machine().describe_context(), data, mem_mask);
810      debuglogtimer("%s: (Timer 1 Counter) TCN1_w %04x %04x\n", this->machine().describe_context(), data, mem_mask);
811811      break;
812812   case 1:
813813      invalidlog("%s: invalid TCN1_w %d, %04x %04x\n", this->machine().describe_context(), offset, data, mem_mask);

Previous 199869 Revisions Next

© 1997-2024 The MAME Team