trunk/src/mess/drivers/cp1.c
| r22675 | r22676 | |
| 9 | 9 | 6 * 7 seg led display |
| 10 | 10 | |
| 11 | 11 | ****************************************************************************/ |
| 12 | |
| 12 | 13 | #include "emu.h" |
| 13 | 14 | #include "cpu/mcs48/mcs48.h" |
| 15 | #include "machine/i8155.h" |
| 16 | #include "imagedev/cassette.h" |
| 17 | #include "cp1.lh" |
| 14 | 18 | |
| 15 | 19 | class cp1_state : public driver_device |
| 16 | 20 | { |
| 17 | 21 | public: |
| 18 | 22 | cp1_state(const machine_config &mconfig, device_type type, const char *tag) |
| 19 | 23 | : driver_device(mconfig, type, tag) , |
| 20 | | m_maincpu(*this, "maincpu") { } |
| 24 | m_maincpu(*this, "maincpu"), |
| 25 | m_i8155(*this, "i8155"), |
| 26 | m_i8155_cp3(*this, "i8155_cp3"), |
| 27 | m_cassette(*this, "cassette"), |
| 28 | m_io_line0(*this, "LINE0"), |
| 29 | m_io_line1(*this, "LINE1"), |
| 30 | m_io_line2(*this, "LINE2"), |
| 31 | m_io_line3(*this, "LINE3"), |
| 32 | m_io_line4(*this, "LINE4"), |
| 33 | m_io_config(*this, "CONFIG") |
| 34 | { } |
| 21 | 35 | |
| 22 | | DECLARE_READ8_MEMBER(getp1); |
| 23 | | DECLARE_READ8_MEMBER(getp2); |
| 36 | required_device<cpu_device> m_maincpu; |
| 37 | required_device<i8155_device> m_i8155; |
| 38 | required_device<i8155_device> m_i8155_cp3; |
| 39 | required_device<cassette_image_device> m_cassette; |
| 40 | required_ioport m_io_line0; |
| 41 | required_ioport m_io_line1; |
| 42 | required_ioport m_io_line2; |
| 43 | required_ioport m_io_line3; |
| 44 | required_ioport m_io_line4; |
| 45 | required_ioport m_io_config; |
| 46 | |
| 47 | virtual void machine_reset(); |
| 48 | DECLARE_READ8_MEMBER(port1_r); |
| 49 | DECLARE_READ8_MEMBER(port2_r); |
| 24 | 50 | DECLARE_READ8_MEMBER(getbus); |
| 25 | 51 | DECLARE_READ8_MEMBER(t0_r); |
| 26 | 52 | DECLARE_READ8_MEMBER(t1_r); |
| 27 | | DECLARE_WRITE8_MEMBER(putp1); |
| 28 | | DECLARE_WRITE8_MEMBER(putp2); |
| 53 | DECLARE_WRITE8_MEMBER(port1_w); |
| 54 | DECLARE_WRITE8_MEMBER(port2_w); |
| 29 | 55 | DECLARE_WRITE8_MEMBER(putbus); |
| 30 | | required_device<cpu_device> m_maincpu; |
| 56 | |
| 57 | DECLARE_READ8_MEMBER(i8155_read); |
| 58 | DECLARE_WRITE8_MEMBER(i8155_write); |
| 59 | DECLARE_WRITE8_MEMBER(i8155_porta_w); |
| 60 | DECLARE_READ8_MEMBER(i8155_portb_r); |
| 61 | DECLARE_WRITE8_MEMBER(i8155_portb_w); |
| 62 | DECLARE_WRITE8_MEMBER(i8155_portc_w); |
| 63 | |
| 64 | private: |
| 65 | UINT8 m_7seg; |
| 66 | UINT8 m_port2; |
| 67 | UINT8 m_matrix; |
| 31 | 68 | }; |
| 32 | 69 | |
| 33 | | READ8_MEMBER(cp1_state::getp1) |
| 70 | READ8_MEMBER(cp1_state::port1_r) |
| 34 | 71 | { |
| 35 | | logerror("getp1\n"); |
| 36 | | return 0; |
| 72 | logerror("Read from expansion port 1\n"); |
| 73 | |
| 74 | UINT8 data = 0; |
| 75 | |
| 76 | if (m_io_config->read() & 0x01) |
| 77 | data |= (m_cassette->input() > 0.03) ? 0x80 : 0x00; |
| 78 | |
| 79 | return data; |
| 37 | 80 | } |
| 38 | | READ8_MEMBER(cp1_state::getp2) |
| 81 | |
| 82 | WRITE8_MEMBER(cp1_state::port1_w) |
| 39 | 83 | { |
| 40 | | logerror("getp2\n"); |
| 41 | | return 0; |
| 84 | logerror("Write to expansion port 1 %x\n", data); |
| 85 | |
| 86 | if (m_io_config->read() & 0x01) |
| 87 | m_cassette->output(data & 0x80 ? +1.0 : -1.0); |
| 42 | 88 | } |
| 43 | | READ8_MEMBER(cp1_state::getbus) |
| 89 | |
| 90 | READ8_MEMBER(cp1_state::port2_r) |
| 44 | 91 | { |
| 45 | | logerror("getbus\n"); |
| 46 | | return 0; |
| 92 | // x--- ---- I8155 IO/M |
| 93 | // -x-- ---- I8155 RESET |
| 94 | // --x- ---- expansion port CE |
| 95 | // ---x ---- I8155 CE |
| 96 | // ---- xxxx keyboard input |
| 97 | |
| 98 | ioport_port* portnames[] = { m_io_line0, m_io_line1, m_io_line2, m_io_line3, m_io_line4 }; |
| 99 | UINT8 data = 0; |
| 100 | |
| 101 | for(int i=0; i<5; i++) |
| 102 | if (!(m_matrix & (1<<i))) |
| 103 | data |= portnames[i]->read(); |
| 104 | |
| 105 | return (data & 0x0f) | (m_port2 & 0xf0); |
| 47 | 106 | } |
| 107 | |
| 108 | WRITE8_MEMBER(cp1_state::port2_w) |
| 109 | { |
| 110 | if (data & 0x40) |
| 111 | { |
| 112 | m_i8155->reset(); |
| 113 | |
| 114 | if (m_io_config->read() & 0x02) |
| 115 | m_i8155_cp3->reset(); |
| 116 | } |
| 117 | |
| 118 | m_port2 = data; |
| 119 | } |
| 120 | |
| 48 | 121 | READ8_MEMBER(cp1_state::t0_r) |
| 49 | 122 | { |
| 50 | 123 | logerror("t0_r\n"); |
| 51 | 124 | return 0; |
| 52 | 125 | } |
| 126 | |
| 53 | 127 | READ8_MEMBER(cp1_state::t1_r) |
| 54 | 128 | { |
| 55 | 129 | logerror("t1_r\n"); |
| 56 | 130 | return 0; |
| 57 | 131 | } |
| 58 | | WRITE8_MEMBER(cp1_state::putp1) |
| 132 | |
| 133 | READ8_MEMBER(cp1_state::getbus) |
| 59 | 134 | { |
| 60 | | logerror("putp1\n"); |
| 135 | logerror("getbus\n"); |
| 136 | return 0; |
| 61 | 137 | } |
| 62 | | WRITE8_MEMBER(cp1_state::putp2) |
| 63 | | { |
| 64 | | logerror("putp2\n"); |
| 65 | | } |
| 138 | |
| 66 | 139 | WRITE8_MEMBER(cp1_state::putbus) |
| 67 | 140 | { |
| 68 | 141 | logerror("putbus\n"); |
| 69 | 142 | } |
| 70 | 143 | |
| 71 | | static ADDRESS_MAP_START(cp1_mem, AS_PROGRAM, 8, cp1_state) |
| 72 | | ADDRESS_MAP_UNMAP_HIGH |
| 73 | | AM_RANGE( 0x0000, 0x07ff) AM_ROM |
| 74 | | ADDRESS_MAP_END |
| 144 | READ8_MEMBER(cp1_state::i8155_read) |
| 145 | { |
| 146 | UINT8 data = 0; |
| 75 | 147 | |
| 148 | if (!(m_port2 & 0x10)) |
| 149 | { |
| 150 | m_i8155->ale_w(space, BIT(m_port2, 7), offset); |
| 151 | data |= m_i8155->read(space, offset); |
| 152 | } |
| 153 | if ((m_io_config->read() & 0x02) && !(m_port2 & 0x20)) |
| 154 | { |
| 155 | // CP3 RAM expansion |
| 156 | m_i8155_cp3->ale_w(space, BIT(m_port2, 7), offset); |
| 157 | data |= m_i8155_cp3->read(space, offset); |
| 158 | } |
| 159 | |
| 160 | return data; |
| 161 | } |
| 162 | |
| 163 | WRITE8_MEMBER(cp1_state::i8155_write) |
| 164 | { |
| 165 | if (!(m_port2 & 0x10)) |
| 166 | { |
| 167 | m_i8155->ale_w(space, BIT(m_port2, 7), offset); |
| 168 | m_i8155->write(space, offset, data); |
| 169 | } |
| 170 | if ((m_io_config->read() & 0x02) && !(m_port2 & 0x20)) |
| 171 | { |
| 172 | // CP3 RAM expansion |
| 173 | m_i8155_cp3->ale_w(space, BIT(m_port2, 7), offset); |
| 174 | m_i8155_cp3->write(space, offset, data); |
| 175 | } |
| 176 | } |
| 177 | |
| 178 | WRITE8_MEMBER(cp1_state::i8155_porta_w) |
| 179 | { |
| 180 | data &= 0x7f; // PA7 is not connected |
| 181 | |
| 182 | if (m_7seg) |
| 183 | { |
| 184 | if (!(m_matrix & 0x01)) output_set_digit_value(5, data); |
| 185 | if (!(m_matrix & 0x02)) output_set_digit_value(4, data); |
| 186 | if (!(m_matrix & 0x04)) output_set_digit_value(3, data); |
| 187 | if (!(m_matrix & 0x08)) output_set_digit_value(2, data | 0x80); // this digit has always the dot active |
| 188 | if (!(m_matrix & 0x10)) output_set_digit_value(1, data); |
| 189 | if (!(m_matrix & 0x20)) output_set_digit_value(0, data); |
| 190 | } |
| 191 | |
| 192 | m_7seg ^= 0x01; |
| 193 | } |
| 194 | |
| 195 | READ8_MEMBER(cp1_state::i8155_portb_r) |
| 196 | { |
| 197 | logerror("read from expansion port 2\n"); |
| 198 | return 0; |
| 199 | } |
| 200 | |
| 201 | WRITE8_MEMBER(cp1_state::i8155_portb_w) |
| 202 | { |
| 203 | logerror("Write to expansion port 2 %x\n", data); |
| 204 | } |
| 205 | |
| 206 | WRITE8_MEMBER(cp1_state::i8155_portc_w) |
| 207 | { |
| 208 | // --xx xxxx keyboard matrix |
| 209 | |
| 210 | m_matrix = data & 0x3f; |
| 211 | } |
| 212 | |
| 213 | |
| 76 | 214 | static ADDRESS_MAP_START( cp1_io , AS_IO, 8, cp1_state) |
| 77 | 215 | ADDRESS_MAP_UNMAP_HIGH |
| 78 | | AM_RANGE( MCS48_PORT_P1, MCS48_PORT_P1) AM_READWRITE( getp1, putp1 ) |
| 79 | | AM_RANGE( MCS48_PORT_P2, MCS48_PORT_P2) AM_READWRITE( getp2, putp2 ) |
| 216 | AM_RANGE( 0x00, 0xff ) AM_READWRITE( i8155_read, i8155_write) |
| 217 | AM_RANGE( MCS48_PORT_P1, MCS48_PORT_P1) AM_READWRITE( port1_r, port1_w ) |
| 218 | AM_RANGE( MCS48_PORT_P2, MCS48_PORT_P2) AM_READWRITE( port2_r, port2_w ) |
| 80 | 219 | AM_RANGE( MCS48_PORT_BUS, MCS48_PORT_BUS) AM_READWRITE( getbus, putbus ) |
| 81 | 220 | AM_RANGE( MCS48_PORT_T0, MCS48_PORT_T0) AM_READ( t0_r ) |
| 82 | 221 | AM_RANGE( MCS48_PORT_T1, MCS48_PORT_T1) AM_READ( t1_r ) |
| r22675 | r22676 | |
| 84 | 223 | |
| 85 | 224 | /* Input ports */ |
| 86 | 225 | INPUT_PORTS_START( cp1 ) |
| 226 | PORT_START("LINE0") |
| 227 | PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_K) PORT_NAME("CAS [Cass. speichern]") |
| 228 | PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_DEL) PORT_NAME("CLR [Irrtum]") |
| 229 | PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_C) PORT_NAME("PC [Programmzahler]") |
| 230 | PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_A) PORT_NAME("ACC [Akku]") |
| 231 | PORT_START("LINE1") |
| 232 | PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_L) PORT_NAME("CAL [Cass. lesen]") |
| 233 | PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_S) PORT_NAME("STEP [Schritt]") |
| 234 | PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_B) PORT_NAME("STP [Stopp]") |
| 235 | PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_R) PORT_NAME("RUN [Lauf]") |
| 236 | PORT_START("LINE2") |
| 237 | PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_8) PORT_NAME("8") |
| 238 | PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_9) PORT_NAME("9") |
| 239 | PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_O) PORT_NAME("OUT [Auslesen]") |
| 240 | PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_I) PORT_NAME("INP [Eingeben]") |
| 241 | PORT_START("LINE3") |
| 242 | PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_4) PORT_NAME("4") |
| 243 | PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_5) PORT_NAME("5") |
| 244 | PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_6) PORT_NAME("6") |
| 245 | PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_7) PORT_NAME("7") |
| 246 | PORT_START("LINE4") |
| 247 | PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_0) PORT_NAME("0") |
| 248 | PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_1) PORT_NAME("1") |
| 249 | PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_2) PORT_NAME("2") |
| 250 | PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_3) PORT_NAME("3") |
| 251 | |
| 252 | PORT_START("CONFIG") |
| 253 | PORT_CONFNAME( 0x01, 0x01, "CP2 Cassette Interface" ) |
| 254 | PORT_CONFSETTING( 0x00, DEF_STR( No ) ) |
| 255 | PORT_CONFSETTING( 0x01, DEF_STR( Yes ) ) |
| 256 | PORT_CONFNAME( 0x02, 0x00, "CP3 RAM Expansion" ) |
| 257 | PORT_CONFSETTING( 0x00, DEF_STR( No ) ) |
| 258 | PORT_CONFSETTING( 0x02, DEF_STR( Yes ) ) |
| 87 | 259 | INPUT_PORTS_END |
| 88 | 260 | |
| 261 | void cp1_state::machine_reset() |
| 262 | { |
| 263 | m_port2 = 0; |
| 264 | m_matrix = 0; |
| 265 | m_7seg = 0; |
| 266 | m_cassette->change_state(CASSETTE_STOPPED, CASSETTE_MASK_UISTATE); |
| 267 | } |
| 268 | |
| 269 | static I8155_INTERFACE( i8155_intf ) |
| 270 | { |
| 271 | DEVCB_NULL, // port A read |
| 272 | DEVCB_DRIVER_MEMBER(cp1_state, i8155_porta_w), // port A write |
| 273 | DEVCB_DRIVER_MEMBER(cp1_state, i8155_portb_r), // port B read |
| 274 | DEVCB_DRIVER_MEMBER(cp1_state, i8155_portb_w), // port B write |
| 275 | DEVCB_NULL, // port C read |
| 276 | DEVCB_DRIVER_MEMBER(cp1_state, i8155_portc_w), // port C write |
| 277 | DEVCB_NULL // timer output |
| 278 | }; |
| 279 | |
| 280 | static I8155_INTERFACE( i8155_cp3_intf ) |
| 281 | { |
| 282 | DEVCB_NULL, // port A read |
| 283 | DEVCB_NULL, // port A write |
| 284 | DEVCB_NULL, // port B read |
| 285 | DEVCB_NULL, // port B write |
| 286 | DEVCB_NULL, // port C read |
| 287 | DEVCB_NULL, // port C write |
| 288 | DEVCB_NULL // timer output |
| 289 | }; |
| 290 | |
| 89 | 291 | static MACHINE_CONFIG_START( cp1, cp1_state ) |
| 90 | 292 | /* basic machine hardware */ |
| 91 | | MCFG_CPU_ADD("maincpu",I8048, XTAL_6MHz) |
| 92 | | MCFG_CPU_PROGRAM_MAP(cp1_mem) |
| 293 | MCFG_CPU_ADD("maincpu", I8049, XTAL_6MHz) |
| 93 | 294 | MCFG_CPU_IO_MAP(cp1_io) |
| 295 | |
| 296 | MCFG_I8155_ADD("i8155", 0, i8155_intf) |
| 297 | MCFG_I8155_ADD("i8155_cp3", 0, i8155_cp3_intf) |
| 298 | |
| 299 | MCFG_DEFAULT_LAYOUT(layout_cp1) |
| 300 | |
| 301 | MCFG_CASSETTE_ADD("cassette", default_cassette_interface) |
| 94 | 302 | MACHINE_CONFIG_END |
| 95 | 303 | |
| 96 | 304 | /* ROM definition */ |