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r22657 Friday 3rd May, 2013 at 16:41:54 UTC by David Haywood
slightly more realistic handling (nw)
[src/emu/machine]mcf5206e.c

trunk/src/emu/machine/mcf5206e.c
r22656r22657
55#include "emu.h"
66#include "mcf5206e.h"
77
8void CLIB_DECL nolog(const char *format, ...) {}
9
810//#define debuglog printf
911#define debuglog logerror
1012
1113#define invalidlog printf
1214//#define invalidlog logerror
1315
16//#define debuglogtimer printf
17//#define debuglogtimer logerror
18#define debuglogtimer nolog
1419
1520static ADDRESS_MAP_START( coldfire_regs_map, AS_0, 32, mcf5206e_peripheral_device )
1621   
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652657   debuglog("(Unused bits) : %01x\n", (ICR&0x60)>>5);
653658}
654659
655/* The timer module seems practically the same as the 68307 one, possibly make into a common device once the code isn't a hardcoded piece of junk ;-) */
656660
661
657662TIMER_CALLBACK_MEMBER(mcf5206e_peripheral_device::timer1_callback)
658663{
659664   UINT8 ICR = m_ICR[ICR9];
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664669      if (!(m_IMR & 0x0200)) m_cpu->set_input_line((ICR&0x1c)>>2, HOLD_LINE);
665670   }
666671
667   debuglog("timer1_callback\n");
672   debuglogtimer("timer1_callback\n");
673   m_TER1 |= 0x02;
668674   
669675   timer1->adjust(attotime::from_msec(10)); // completely made up value just to fire our timers for now
670676}
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675681   switch (offset)
676682   {
677683   case 0:
678      debuglog("%s: TMR1_r %04x\n", this->machine().describe_context(), mem_mask);
684      debuglogtimer("%s: TMR1_r %04x\n", this->machine().describe_context(), mem_mask);
679685      return m_TMR1;
680686   case 1:
681687      invalidlog("%s: invalid TMR1_r %d %04x\n", this->machine().describe_context(), offset, mem_mask);
r22656r22657
691697   {
692698   case 0:
693699      COMBINE_DATA(&m_TMR1);
694      debuglog("%s: TMR1_w %04x %04x\n", this->machine().describe_context(), data, mem_mask);
700      debuglogtimer("%s: TMR1_w %04x %04x\n", this->machine().describe_context(), data, mem_mask);
695701
696      debuglog("   (Prescale) PS : %02x  (Capture Edge/Interrupt) CE : %01x (Output Mode) OM : %01x  (Output Reference Interrupt En) ORI : %01x   Free Run (FRR) : %01x  Input Clock Source (ICLK) : %01x  (Reset Timer) RST : %01x  \n", (m_TMR1 & 0xff00)>>8, (m_TMR1 & 0x00c0)>>6,  (m_TMR1 & 0x0020)>>5, (m_TMR1 & 0x0010)>>4, (m_TMR1 & 0x0008)>>3, (m_TMR1 & 0x0006)>>1, (m_TMR1 & 0x0001)>>0);   
702      debuglogtimer("   (Prescale) PS : %02x  (Capture Edge/Interrupt) CE : %01x (Output Mode) OM : %01x  (Output Reference Interrupt En) ORI : %01x   Free Run (FRR) : %01x  Input Clock Source (ICLK) : %01x  (Reset Timer) RST : %01x  \n", (m_TMR1 & 0xff00)>>8, (m_TMR1 & 0x00c0)>>6,  (m_TMR1 & 0x0020)>>5, (m_TMR1 & 0x0010)>>4, (m_TMR1 & 0x0008)>>3, (m_TMR1 & 0x0006)>>1, (m_TMR1 & 0x0001)>>0);   
697703     
698704      if (m_TMR1 & 0x0001)
699705      {
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718724   switch (offset)
719725   {
720726   case 0:
721      debuglog("%s: TRR1_r %04x\n", this->machine().describe_context(), mem_mask);
727      debuglogtimer("%s: TRR1_r %04x\n", this->machine().describe_context(), mem_mask);
722728      return m_TRR1;
723729   case 1:
724730      invalidlog("%s: invalid TRR1_r %d %04x\n", this->machine().describe_context(), offset, mem_mask);
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734740   {
735741   case 0:
736742      COMBINE_DATA(&m_TRR1);
737      debuglog("%s: TRR1_w %04x %04x\n", this->machine().describe_context(), data, mem_mask);
743      debuglogtimer("%s: TRR1_w %04x %04x\n", this->machine().describe_context(), data, mem_mask);
738744      break;
739745   case 1:
740746      debuglog("%s: invalid TRR1_w %d, %04x %04x\n", this->machine().describe_context(), offset, data, mem_mask);
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750756   switch (offset)
751757   {
752758   case 1:
753      debuglog("%s: TER1_r\n", this->machine().describe_context());
754      return 2; // hack, timer events should set bits, this just stops the code going crazy for now
759      debuglogtimer("%s: TER1_r\n", this->machine().describe_context());
760      return m_TER1; // set on timer events, cleared by writing below
755761   case 0:
756762   case 2:
757763   case 3:
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767773   switch (offset)
768774   {
769775   case 1:
770      m_TER1 = data; // writes should clear the bits..
771      debuglog("%s: TER1_w %02x\n", this->machine().describe_context(), data);
776      m_TER1 &= ~data; // writes should clear the bits..
777      debuglogtimer("%s: TER1_w %02x\n", this->machine().describe_context(), data);
772778      break;
773779   case 0:
774780   case 2:
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784790   switch (offset)
785791   {
786792   case 0:
787      debuglog("%s: TCN1_r %04x\n", this->machine().describe_context(), mem_mask);
788      return  machine().rand(); // 0x8ca0 -1;// m_TCN1; // this should be the counter, code has a hardcoded >= check against 8ca0.
793      debuglogtimer("%s: TCN1_r %04x\n", this->machine().describe_context(), mem_mask);
794      // return 0x9c40;
795      return 0x8ca0 -1;// m_TCN1; // this should be the counter, code has a hardcoded >= check against 8ca0.
789796   case 1:
790797      invalidlog("%s: invalid TCN1_r %d %04x\n", this->machine().describe_context(), offset, mem_mask);
791798      return 0;
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800807   {
801808   case 0:
802809      COMBINE_DATA(&m_TCN1);
803      debuglog("%s: TCN1_w %04x %04x\n", this->machine().describe_context(), data, mem_mask);
810      debuglogtimer("%s: TCN1_w %04x %04x\n", this->machine().describe_context(), data, mem_mask);
804811      break;
805812   case 1:
806813      invalidlog("%s: invalid TCN1_w %d, %04x %04x\n", this->machine().describe_context(), offset, data, mem_mask);

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