MAME SVN History

199869 Revisions

r22616 Tuesday 30th April, 2013 at 06:36:06 UTC by Miodrag Milanović
Cleanups and version bump

[hash]	megadriv.xml nes.xml svmu.xml
[src]	version.c
[src/emu]	emu.mak
[src/emu/cpu/psx]	gte.c
[src/emu/cpu/z8000]	8000dasm.c z8000.h
[src/emu/debug]	debugcpu.c
[src/emu/machine]	6850acia.h 8042kbdc.c 8042kbdc.h mcf5206e.c mcf5206e.h s3c2400.h s3c2410.h s3c2440.h
[src/emu/sound]	spu.c
[src/emu/video]	dl1416.c psx.c voodoo.c voodoo.h
[src/lib/util]	simple_set.h
[src/mame]	mame.lst mame.mak
[src/mame/drivers]	1942.c 2mindril.c 39in1.c 40love.c alpha68k.c amspdwy.c angelkds.c aquarium.c ashnojoe.c atarifb.c atvtrack.c battlane.c bking.c blockout.c boxer.c brkthru.c btime.c bwing.c calchase.c capbowl.c cave.c champbas.c chanbara.c chinagat.c citycon.c commando.c cop01.c cps2.c crgolf.c crospang.c csplayh5.c cubeqst.c dacholer.c ddayjlc.c ddragon3.c destroyr.c discoboy.c dlair.c dogfgt.c egghunt.c espial.c exerion.c fcombat.c fcrash.c flyball.c fruitpc.c funkball.c gaiden.c gamecstl.c gammagic.c ghosteo.c ginganin.c gladiatr.c gluck2.c gotcha.c gridlee.c hikaru.c hvyunit.c hyprduel.c ironhors.c iteagle.c junofrst.c karnov.c kas89.c kchamp.c kncljoe.c kopunch.c kyugo.c ladybug.c ladyfrog.c lasso.c lazercmd.c legionna.c lethal.c liberate.c m14.c macrossp.c madmotor.c magtouch.c mazerbla.c mediagx.c metlclsh.c mgolf.c midqslvr.c mikie.c mlanding.c mouser.c mrflea.c msisaac.c munchmo.c n8080.c naomi.c nightgal.c nmg5.c norautp.c ojankohs.c oneshot.c opwolf.c orbit.c pasha2.c pbaction.c pcat_nit.c pgm.c photoply.c pinball2k.c pipedrm.c pooyan.c popper.c psikyo.c psikyo4.c psikyosh.c queen.c redclash.c savquest.c seattle.c segac2.c skyfox.c snk.c sonson.c su2000.c suna16.c taito_l.c taitojc.c taitowlf.c topspeed.c trvquest.c unico.c vlc.c voyager.c xtom3d.c yunsun16.c zn.c
[src/mame/includes]	asuka.h bublbobl.h dec8.h deco32.h docastle.h dynax.h eprom.h exzisus.h galaga.h jaguar.h leland.h mario.h meadows.h metro.h mitchell.h namcos21.h nbmj8688.h nbmj9195.h niyanpai.h nmk16.h psikyo4.h rainbow.h scramble.h slapshot.h spdodgeb.h suna16.h taitojc.h tbowl.h thunderj.h toaplan1.h turbo.h xexex.h
[src/mame/machine]	nitedrvr.c pcecommn.h pcshare.c pcshare.h
[src/mame/video]	taitoic.h
[src/mess/audio]	vrc6.c vrc6.h
[src/mess/drivers]	bebox.c bigbord2.c coco3.c dmv.c fk1.c fmtowns.c ip22.c kyocera.c merlin.c mini2440.c mz3500.c p8k.c palmz22.c pc9801.c tsispch.c
[src/mess/includes]	aim65.h amstr_pc.h apple2gs.h avigo.h bbc.h c128.h c64.h c65.h cgenie.h cosmicos.h electron.h enterp.h europc.h gb.h gp32.h hp48.h kc.h lviv.h mac.h nascom1.h nc.h nes.h partner.h pc.h pcw.h pet.h plus4.h tandy1t.h tmc1800.h trs80m2.h tvc.h vc4000.h vidbrain.h x1.h x68k.h
[src/mess/machine]	apple2gs.c bebox.c cgenie.c dragon.c europc.c galaxy.c isa_ide8.c isa_ide8.h mac.c md_rom.c nes_ave.c nes_bandai.c nes_bandai.h nes_bootleg.c nes_bootleg.h nes_camerica.c nes_cony.c nes_cony.h nes_discrete.c nes_irem.c nes_irem.h nes_jaleco.c nes_jaleco.h nes_kaiser.c nes_kaiser.h nes_konami.c nes_konami.h nes_legacy.h nes_mmc1.c nes_mmc3.c nes_namcot.c nes_namcot.h nes_nxrom.c nes_pirate.c nes_pirate.h nes_sachen.c nes_slot.c nes_slot.h nes_somari.c nes_sunsoft.c nes_sunsoft.h nes_taito.c nes_txc.c nes_waixing.c pc.c primo.c psxcd.c rmnimbus.c s3c44b0.c sms.c upd71071.c upd71071.h vtech2.c
[src/mess/video]	cgenie.c fm7.c pc_aga.h rmnimbus.c tx0.c vic4567.h
[src/osd/sdl]	debugqtdasmwindow.h debugqtlogwindow.h debugqtmainwindow.c debugqtmainwindow.h debugqtmemorywindow.h debugqtwindow.h sdldir.c

trunk/hash/svmu.xml
r22615	r22616
7	7	<description>Chao Adventure</description>
8	8	<year>1999</year>
9	9	<publisher>Sega</publisher>
10		<info name="source" value="Sonic Adventure" />
	10	<info name="source" value="Sonic Adventure" />
11	11	<part name="quik" interface="svmu_quik">
12	12	<dataarea name="rom" size="65536">
13	13	<rom name="chao adventure (1999)(sega)[sonic adventure].vms" size="65536" crc="09e93592" sha1="f35738795fd1799bbffb6c3df8d4f208ccf437b5" offset="0" />
r22615	r22616
19	19	<description>Chao Adventure 2</description>
20	20	<year>2001</year>
21	21	<publisher>Sega</publisher>
22		<info name="source" value="Sonic Adventure 2" />
	22	<info name="source" value="Sonic Adventure 2" />
23	23	<part name="quik" interface="svmu_quik">
24	24	<dataarea name="rom" size="65536">
25	25	<rom name="chao adventure 2 (sega)(2001)[sonic adventure 2].vms" size="65536" crc="9c464d76" sha1="4190654ed0cede2d852fbe7c7f612a4c1b4a45b3" offset="0" />
r22615	r22616
31	31	<description>Chao Adventure 2 (Fra)</description>
32	32	<year>2001</year>
33	33	<publisher>Sega</publisher>
34		<info name="source" value="Sonic Adventure 2" />
	34	<info name="source" value="Sonic Adventure 2" />
35	35	<part name="quik" interface="svmu_quik">
36	36	<dataarea name="rom" size="65536">
37	37	<rom name="chao adventure 2 (2001)(sega)(fr)[sonic adventure 2].vms" size="65536" crc="20f25e00" sha1="6e57f9447fdbcf69fddbb3b7a187f7043dcd9de0" offset="0" />
r22615	r22616
43	43	<description>Linear Watch</description>
44	44	<year>2000</year>
45	45	<publisher>ESP Software</publisher>
46		<info name="source" value="Evolution 2" />
	46	<info name="source" value="Evolution 2" />
47	47	<part name="quik" interface="svmu_quik">
48	48	<dataarea name="rom" size="15360">
49	49	<rom name="linear watch (2000)(esp software)[evolution 2].vms" size="15360" crc="16b6f34c" sha1="556b7d4235c08e03e1eec0bb6527f63dc5ec78a4" offset="0" />
r22615	r22616
55	55	<description>Marvel VS. Capcom 2 vs. Com (Jpn)</description>
56	56	<year>2000</year>
57	57	<publisher>Capcom</publisher>
58		<info name="source" value="Marvel vs. Capcom 2" />
	58	<info name="source" value="Marvel vs. Capcom 2" />
59	59	<part name="quik" interface="svmu_quik">
60	60	<dataarea name="rom" size="32768">
61	61	<rom name="marvel vs. capcom 2 vs. com (2000)(capcom)(jp)[marvel vs. capcom 2].vms" size="32768" crc="3f621910" sha1="b52bed579019bec07b818c802b72277be0c4430c" offset="0" />
r22615	r22616
67	67	<description>Pop 'n Music Vol. 1 (Jpn)</description>
68	68	<year>1999</year>
69	69	<publisher>Konami</publisher>
70		<info name="source" value="Pop 'n Music" />
	70	<info name="source" value="Pop 'n Music" />
71	71	<part name="quik" interface="svmu_quik">
72	72	<dataarea name="rom" size="28672">
73	73	<rom name="pop 'n music vol. 1 (1999)(konami)(jp)[pop 'n music].vms" size="28672" crc="7ce75350" sha1="339ebf13c557c14851e171202d3b105dee9fce6b" offset="0" />
r22615	r22616
79	79	<description>Pop 'n Music Vol. 2 (Jpn)</description>
80	80	<year>2000</year>
81	81	<publisher>Konami</publisher>
82		<info name="source" value="Pop 'n Music" />
	82	<info name="source" value="Pop 'n Music" />
83	83	<part name="quik" interface="svmu_quik">
84	84	<dataarea name="rom" size="30720">
85	85	<rom name="pop 'n music vol. 2 (2000)(konami)(jp)[pop 'n music].vms" size="30720" crc="c2a1cd70" sha1="3dfbd8cf625728040676e17409b10914cb9917e7" offset="0" />
r22615	r22616
91	91	<description>Pop 'n Music Vol. 3 (Jpn)</description>
92	92	<year>2000</year>
93	93	<publisher>Konami</publisher>
94		<info name="source" value="Pop 'n Music" />
	94	<info name="source" value="Pop 'n Music" />
95	95	<part name="quik" interface="svmu_quik">
96	96	<dataarea name="rom" size="30720">
97	97	<rom name="pop 'n music vol. 3 (2000)(konami)(jp)[pop 'n music].vms" size="30720" crc="96fef522" sha1="56a46d89187a04d26fe20cc4b697b23eebedb96e" offset="0" />
r22615	r22616
103	103	<description>Powerstone Mini</description>
104	104	<year>1999</year>
105	105	<publisher>Capcom</publisher>
106		<info name="source" value="Power Stone" />
	106	<info name="source" value="Power Stone" />
107	107	<part name="quik" interface="svmu_quik">
108	108	<dataarea name="rom" size="65536">
109	109	<rom name="powerstone mini (1999)(capcom)[power stone].vms" size="65536" crc="04d6a41f" sha1="177781ab7023de28216b33d237d2ee7e57b66205" offset="0" />
r22615	r22616
115	115	<description>Power Stone 2 Mini Store (Jpn)</description>
116	116	<year>2000</year>
117	117	<publisher>Capcom</publisher>
118		<info name="source" value="Power Stone 2" />
	118	<info name="source" value="Power Stone 2" />
119	119	<part name="quik" interface="svmu_quik">
120	120	<dataarea name="rom" size="65536">
121	121	<rom name="power stone 2 mini store (2000)(capcom)(jp)[power stone 2].vms" size="65536" crc="81d456d2" sha1="6ff653848c3dc3205d72363357fc63db4cbf359c" offset="0" />
r22615	r22616
127	127	<description>Sega GT Pocket America</description>
128	128	<year>2000</year>
129	129	<publisher>Sega</publisher>
130		<info name="source" value="Sega GT" />
	130	<info name="source" value="Sega GT" />
131	131	<part name="quik" interface="svmu_quik">
132	132	<dataarea name="rom" size="65536">
133	133	<rom name="sega gt pocket america (2000)(sega - wow-ent)[sega gt].vms" size="65536" crc="20084dc1" sha1="5268f5a02bc21239fd0ea2d25b08cbc00bc83220" offset="0" />
r22615	r22616
139	139	<description>Sega GT (Jpn)</description>
140	140	<year>2000</year>
141	141	<publisher>Sega</publisher>
142		<info name="source" value="Sega GT" />
	142	<info name="source" value="Sega GT" />
143	143	<part name="quik" interface="svmu_quik">
144	144	<dataarea name="rom" size="65536">
145	145	<rom name="sega gt (2000)(sega)(jp)[sega gt].vms" size="65536" crc="9eed83ea" sha1="8ea70e846a9a42877a62a790d8329dd72fe4749f" offset="0" />
r22615	r22616
151	151	<description>Sega GT Pocket Europe</description>
152	152	<year>2000</year>
153	153	<publisher>Sega</publisher>
154		<info name="source" value="Sega GT" />
	154	<info name="source" value="Sega GT" />
155	155	<part name="quik" interface="svmu_quik">
156	156	<dataarea name="rom" size="65536">
157	157	<rom name="sega gt pocket europe (2000)(sega - wow-ent)[sega gt].vms" size="65536" crc="c8490720" sha1="e82dce08ad914ff275f1cfcf64e90d4c8c00d58a" offset="0" />
r22615	r22616
163	163	<description>Sega GT Pocket Japan</description>
164	164	<year>2000</year>
165	165	<publisher>Sega</publisher>
166		<info name="source" value="Sega GT" />
	166	<info name="source" value="Sega GT" />
167	167	<part name="quik" interface="svmu_quik">
168	168	<dataarea name="rom" size="65536">
169	169	<rom name="sega gt pocket japan (2000)(sega - wow-ent)[sega gt].vms" size="65536" crc="7d4b5c34" sha1="32e0dae07dd17de9981c84de9e12b2af6677353d" offset="0" />
r22615	r22616
175	175	<description>Shenmue (Jpn)</description>
176	176	<year>1999</year>
177	177	<publisher>Sega</publisher>
178		<info name="source" value="Shenmue" />
	178	<info name="source" value="Shenmue" />
179	179	<part name="quik" interface="svmu_quik">
180	180	<dataarea name="rom" size="25600">
181	181	<rom name="shenmue (1999)(sega)(jp)[shenmue].vms" size="25600" crc="3fcab726" sha1="ea52613cf39b965266ad32501d8caa6286de4e57" offset="0" />
r22615	r22616
187	187	<description>Soul Calibur 3-1 Mini (Jpn)</description>
188	188	<year>1999</year>
189	189	<publisher>Namco</publisher>
190		<info name="source" value="SoulCalibur" />
	190	<info name="source" value="SoulCalibur" />
191	191	<part name="quik" interface="svmu_quik">
192	192	<dataarea name="rom" size="50176">
193	193	<rom name="soul calibur 3-1 mini (1999)(namco)(jp)[soulcalibur].vms" size="50176" crc="d23dfe42" sha1="bf34e85fb481a3e920dab7517dd170c28f5c4ad5" offset="0" />
r22615	r22616
199	199	<description>SoulCalibur Text Adventure (Jpn)</description>
200	200	<year>1999</year>
201	201	<publisher>Namco</publisher>
202		<info name="source" value="SoulCalibur" />
	202	<info name="source" value="SoulCalibur" />
203	203	<part name="quik" interface="svmu_quik">
204	204	<dataarea name="rom" size="50688">
205	205	<rom name="soulcalibur text adventure (1999)(namco)(jp)[soulcalibur].vms" size="50688" crc="eedc89ee" sha1="3783708b76cdfd2a5f027c39ff45236c1244baa4" offset="0" />
r22615	r22616
211	211	<description>SoulCalibur VMU Game Pack </description>
212	212	<year>1999</year>
213	213	<publisher>Namco</publisher>
214		<info name="source" value="SoulCalibur" />
	214	<info name="source" value="SoulCalibur" />
215	215	<part name="quik" interface="svmu_quik">
216	216	<dataarea name="rom" size="50176">
217	217	<rom name="soulcalibur vmu game pack (1999)(namco)[soulcalibur].vms" size="50176" crc="6068eb49" sha1="b3d87d67b8ca59887e9680b4213239881bb4360c" offset="0" />
r22615	r22616
223	223	<description>TrickStyle Junior</description>
224	224	<year>1999</year>
225	225	<publisher>Acclaim</publisher>
226		<info name="source" value="TrickStyle" />
	226	<info name="source" value="TrickStyle" />
227	227	<part name="quik" interface="svmu_quik">
228	228	<dataarea name="rom" size="3584">
229	229	<rom name="trickstyle junior (1999)(acclaim)[trickstyle].vms" size="3584" crc="966659f9" sha1="5b46e07f30ecf53ebdfc17eb4accaf3e3d4fa92a" offset="0" />
r22615	r22616
247	247	<description>Zombie Revenge Training Game</description>
248	248	<year>1999</year>
249	249	<publisher>Sega</publisher>
250		<info name="source" value="Zombie Revenge" />
	250	<info name="source" value="Zombie Revenge" />
251	251	<part name="quik" interface="svmu_quik">
252	252	<dataarea name="rom" size="56320">
253	253	<rom name="zombie revenge training game (1999)(sega)[zombie revenge].vms" size="56320" crc="7b4ce3c7" sha1="68b584f7c5c7ac119c12641e8b1f01a726c58881" offset="0" />

trunk/hash/nes.xml
r22615	r22616
51007	51007	<info name="alt_title" value="中國大亨"/>
51008	51008	<part name="cart" interface="nes_cart">
51009	51009	<feature name="slot" value="txrom" />
51010		<feature name="pcb" value="NES-TLROM" /> <!-- Original header was mapper 116, but it's not a SOMARI pcb... -->
	51010	<feature name="pcb" value="NES-TLROM" /> <!-- Original header was mapper 116, but it's not a SOMARI pcb... -->
51011	51011	<dataarea name="chr" size="131072">
51012	51012	<rom name="chuugoku taitei (asia) (unl).chr" size="131072" crc="d9203c08" sha1="b32ef62e4583b216aea84f7d0da0269c01b61e26" offset="00000" status="baddump" />
51013	51013	</dataarea>
r22615	r22616
54017	54017	<info name="serial" value="ES-1109"/>
54018	54018	<info name="alt_title" value="神鬼传奇"/>
54019	54019	<part name="cart" interface="nes_cart">
54020		<feature name="slot" value="hengg_srich" /> <!-- it seems to work even with FS-304... investigate relation between the two... -->
	54020	<feature name="slot" value="hengg_srich" /> <!-- it seems to work even with FS-304... investigate relation between the two... -->
54021	54021	<feature name="pcb" value="HENGGEDIANZI" /> <!-- header says mapper 162, which should be a modified version of 163... -->
54022	54022	<dataarea name="prg" size="1048576">
54023	54023	<rom name="mummy (es-1109) (c).prg" size="1048576" crc="08fbf3f0" sha1="6dc200340d4b7b9397e4d4f28fa307059ce834ec" offset="00000" status="baddump" />

trunk/hash/megadriv.xml
r22615	r22616
4028	4028	<part name="cart" interface="megadriv_cart">
4029	4029	<feature name="pcb" value="670115 REV 3" />
4030	4030	<feature name="ic1" value="MORTAL KOMBAT VER 1.00 S220, MORTAL KOMBAT S215 VER 1.00" />
4031		<!-- USA cart, on a REV 4 PCB has chip labeled as MPR-15748-SM -->
	4031	<!-- USA cart, on a REV 4 PCB has chip labeled as MPR-15748-SM -->
4032	4032	<dataarea name="rom" size="2097152">
4033	4033	<rom name="mortal kombat ver 1.00 s220.ic1" size="2097152" crc="1aa3a207" sha1="c098bf38ddd755ab7caa4612d025be2039009eb2" offset="000000" loadflag="load16_word_swap" />
4034	4034	</dataarea>
r22615	r22616
7882	7882	<part name="cart" interface="megadriv_cart">
7883	7883	<!-- The PCB contains 4 different ROMs, but it is unknown how the dump should be split (maybe we can reconstruct that from the checksums?) -->
7884	7884	<feature name="pcb" value="" />
7885		<feature name="u1" value="MO 1 6/26 56 CE41" /> <!-- The 56 might be a 95 written upside down -->
	7885	<feature name="u1" value="MO 1 6/26 56 CE41" /> <!-- The 56 might be a 95 written upside down -->
7886	7886	<feature name="u2" value="Real Monsters 7-7-95" />
7887	7887	<feature name="u3" value="(unmarked eeprom)" />
7888		<feature name="u4" value="MO 2 6/26 56 FD68" /> <!-- The 56 might be a 95 written upside down -->
	7888	<feature name="u4" value="MO 2 6/26 56 FD68" /> <!-- The 56 might be a 95 written upside down -->
7889	7889	<feature name="u5" value="MC74HC139N" />
7890	7890	<dataarea name="rom" size="2097152">
7891	7891	<rom name="killertomatoes.5b74.bin" size="2097152" crc="f4b44b82" sha1="b0f1885e74e5aa39872f09444d82c8ebf284eba1" offset="000000" loadflag="load16_word_swap" />
r22615	r22616
30580	30580
30581	30581	<!--
30582	30582	Investigation by Eke:
30583		this dump has the PC pointing to $1FE1DE, which does not hold any valid 68k program data in the ROM,
30584		so the game actually does not even starts when the 68k resets => either the dump is incomplete or it
30585		is a bad dump, there is no way bankswitching can be "triggered" before the CPU has reseted and
30586		fetches the PC, only possibility would be that this ROM area is only activated if some signal conditions
30587		is met (I know that some pirate carts will need to have the !RESET lines set HIGH like with the real console,
	30583	this dump has the PC pointing to $1FE1DE, which does not hold any valid 68k program data in the ROM,
	30584	so the game actually does not even starts when the 68k resets => either the dump is incomplete or it
	30585	is a bad dump, there is no way bankswitching can be "triggered" before the CPU has reseted and
	30586	fetches the PC, only possibility would be that this ROM area is only activated if some signal conditions
	30587	is met (I know that some pirate carts will need to have the !RESET lines set HIGH like with the real console,
30588	30588	which most dumpers ignore)
30589	30589	This dump is either a bad dump or a wrongly patched one.
30590	30590	-->

trunk/src/mame/drivers/mazerbla.c
r22615	r22616
1429	1429
1430	1430	void mazerbla_state::machine_start()
1431	1431	{
1432
1433	1432	save_item(NAME(m_vcu_video_reg));
1434	1433	save_item(NAME(m_vcu_gfx_addr));
1435	1434	save_item(NAME(m_vcu_gfx_param_addr));

trunk/src/mame/drivers/metlclsh.c
r22615	r22616
262	262
263	263	void metlclsh_state::machine_start()
264	264	{
265
266	265	save_item(NAME(m_write_mask));
267	266	save_item(NAME(m_gfxbank));
268	267	}

trunk/src/mame/drivers/pgm.c
r22615	r22616
2527	2527	#define DDP2_PROGRAM_102 \
2528	2528	ROM_REGION( 0x600000, "maincpu", 0 ) /* 68000 Code */ \
2529	2529	PGM_68K_BIOS \
2530		ROM_LOAD16_WORD_SWAP( "v102.u8", 0x100000, 0x200000, CRC(5a9ea040) SHA1(51eaec46c368f7cfc5245e64896092f52b1193e0) ) \
2531
	2530	ROM_LOAD16_WORD_SWAP( "v102.u8", 0x100000, 0x200000, CRC(5a9ea040) SHA1(51eaec46c368f7cfc5245e64896092f52b1193e0) )
2532	2531	#define DDP2_PROGRAM_101 \
2533	2532	ROM_REGION( 0x600000, "maincpu", 0 ) /* 68000 Code */ \
2534	2533	PGM_68K_BIOS \
2535		ROM_LOAD16_WORD_SWAP( "v101_16m.u8", 0x100000, 0x200000, CRC(5e5786fd) SHA1(c6fc2956b5dc6a97c0d7d808a8c58aa21fa023b9) ) \
2536
	2534	ROM_LOAD16_WORD_SWAP( "v101_16m.u8", 0x100000, 0x200000, CRC(5e5786fd) SHA1(c6fc2956b5dc6a97c0d7d808a8c58aa21fa023b9) )
2537	2535	#define DDP2_PROGRAM_100 \
2538	2536	ROM_REGION( 0x600000, "maincpu", 0 ) /* 68000 Code */ \
2539	2537	PGM_68K_BIOS \
2540		ROM_LOAD16_WORD_SWAP( "v100.u8", 0x100000, 0x200000, CRC(0c8aa8ea) SHA1(57e33224622607a1df8daabf26ba063cf8a6d3fc) ) \
	2538	ROM_LOAD16_WORD_SWAP( "v100.u8", 0x100000, 0x200000, CRC(0c8aa8ea) SHA1(57e33224622607a1df8daabf26ba063cf8a6d3fc) )
2541	2539
2542	2540
2543
2544	2541	ROM_START( ddp2 )
2545	2542	DDP2_PROGRAM_102
2546	2543	DDP2_ASIC027_WORLD

trunk/src/mame/drivers/kyugo.c
r22615	r22616
495	495
496	496	void kyugo_state::machine_start()
497	497	{
498
499	498	save_item(NAME(m_scroll_x_lo));
500	499	save_item(NAME(m_scroll_x_hi));
501	500	save_item(NAME(m_scroll_y));

trunk/src/mame/drivers/fcrash.c
r22615	r22616
1382	1382
1383	1383	MACHINE_START_MEMBER(cps_state,kodb)
1384	1384	{
1385
1386	1385	m_layer_enable_reg = 0x20;
1387	1386	m_layer_mask_reg[0] = 0x2e;
1388	1387	m_layer_mask_reg[1] = 0x2c;

trunk/src/mame/drivers/yunsun16.c
r22615	r22616
556	556
557	557	void yunsun16_state::machine_start()
558	558	{
559
560	559	save_item(NAME(m_sprites_scrolldx));
561	560	save_item(NAME(m_sprites_scrolldy));
562	561	}

trunk/src/mame/drivers/fruitpc.c
r22615	r22616
3	3	"Fruit" (c) ???? (DOSBox runs it with half the screen missing)
4	4
5	5	preliminary driver by R. Belmont
6
	6
7	7	Hardware:
8	8	- ST STPCD0166BTC3 486/66 + PC + VGA all on one chip
9	9	- 4x AS4LC1M16E5-60TC 1M x 16 EDO DRAM
r22615	r22616
553	553	MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
554	554
555	555	MCFG_MC146818_ADD( "rtc", MC146818_STANDARD )
556
	556
557	557	MCFG_KBDC8042_ADD("kbdc", at8042)
558
	558
559	559	/* video hardware */
560	560	MCFG_FRAGMENT_ADD( pcvideo_vga )
561	561
r22615	r22616
569	569
570	570	ROM_START( fruitpc )
571	571	ROM_REGION( 0x20000, "bios", 0 )
572		ROM_LOAD( "at-gs001.bin", 0x000000, 0x020000, CRC(7dec34d0) SHA1(81d194d67fef9f6531bd3cd1ee0baacb5c2558bf) )
	572	ROM_LOAD( "at-gs001.bin", 0x000000, 0x020000, CRC(7dec34d0) SHA1(81d194d67fef9f6531bd3cd1ee0baacb5c2558bf) )
573	573
574		DISK_REGION( "drive_0" ) // 8 MB Compact Flash card
	574	DISK_REGION( "drive_0" ) // 8 MB Compact Flash card
575	575	DISK_IMAGE( "fruit", 0,SHA1(df250ff06a97fa141a4144034f7035ac2947c53c) )
576	576	ROM_END
577	577

trunk/src/mame/drivers/hyprduel.c
r22615	r22616
628	628
629	629	MACHINE_START_MEMBER(hyprduel_state,hyprduel)
630	630	{
631
632	631	save_item(NAME(m_blitter_bit));
633	632	save_item(NAME(m_requested_int));
634	633	save_item(NAME(m_subcpu_resetline));

trunk/src/mame/drivers/lazercmd.c
r22615	r22616
515	515	PORT_DIPSETTING( 0x01, "3 seconds" )
516	516	PORT_DIPSETTING( 0x03, "5 seconds" )
517	517	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
518		// PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) // dupe
	518	// PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) // dupe
519	519	PORT_BIT( 0x9C, IP_ACTIVE_LOW, IPT_UNUSED )
520	520	PORT_DIPNAME( 0x20, 0x00, "Video Invert" )
521	521	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )

trunk/src/mame/drivers/pcat_nit.c
r22615	r22616
111	111	DECLARE_READ8_MEMBER(pcat_nit_io_r);
112	112	DECLARE_WRITE_LINE_MEMBER(at_com_interrupt_1);
113	113	DECLARE_DRIVER_INIT(pcat_nit);
114		virtual void machine_start();
	114	virtual void machine_start();
115	115	};
116	116
117	117	WRITE_LINE_MEMBER(pcat_nit_state::microtouch_out)

trunk/src/mame/drivers/citycon.c
r22615	r22616
188	188
189	189	void citycon_state::machine_start()
190	190	{
191
192	191	save_item(NAME(m_bg_image));
193	192	}
194	193

trunk/src/mame/drivers/capbowl.c
r22615	r22616
334	334
335	335	void capbowl_state::machine_start()
336	336	{
337
338	337	save_item(NAME(m_blitter_addr));
339	338	save_item(NAME(m_last_trackball_val[0]));
340	339	save_item(NAME(m_last_trackball_val[1]));

trunk/src/mame/drivers/su2000.c
r22615	r22616
258	258	MCFG_SCREEN_REFRESH_RATE(60)
259	259	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) // TODO
260	260
261		MCFG_FRAGMENT_ADD(pcat_common)
	261	MCFG_FRAGMENT_ADD(pcat_common)
262	262	MACHINE_CONFIG_END
263	263
264	264

trunk/src/mame/drivers/magtouch.c
r22615	r22616
199	199	void magtouch_state::machine_start()
200	200	{
201	201	m_maincpu->set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(magtouch_state::irq_callback),this));
202
	202
203	203	membank("rombank")->configure_entries(0, 0x80, memregion("game_prg")->base(), 0x8000 );
204	204	membank("rombank")->set_entry(0);
205	205

trunk/src/mame/drivers/dacholer.c
r22615	r22616
56	56	required_shared_ptr<UINT8> m_bgvideoram;
57	57	required_shared_ptr<UINT8> m_fgvideoram;
58	58	required_shared_ptr<UINT8> m_spriteram;
59
	59
60	60	optional_device<msm5205_device> m_msm;
61	61
62	62	/* video-related */

trunk/src/mame/drivers/cop01.c
r22615	r22616
425	425
426	426	void cop01_state::machine_start()
427	427	{
428
429	428	save_item(NAME(m_pulse));
430	429	save_item(NAME(m_timer));
431	430	save_item(NAME(m_vreg));

trunk/src/mame/drivers/mikie.c
r22615	r22616
247	247
248	248	void mikie_state::machine_start()
249	249	{
250
251	250	save_item(NAME(m_palettebank));
252	251	save_item(NAME(m_last_irq));
253	252	}

trunk/src/mame/drivers/ironhors.c
r22615	r22616
356	356
357	357	void ironhors_state::machine_start()
358	358	{
359
360	359	save_item(NAME(m_palettebank));
361	360	save_item(NAME(m_charbank));
362	361	save_item(NAME(m_spriterambank));

trunk/src/mame/drivers/munchmo.c
r22615	r22616
303	303
304	304	void munchmo_state::machine_start()
305	305	{
306
307	306	save_item(NAME(m_palette_bank));
308	307	save_item(NAME(m_flipscreen));
309	308	save_item(NAME(m_nmi_enable));

trunk/src/mame/drivers/voyager.c
r22615	r22616
763	763	MCFG_PCI_BUS_LEGACY_DEVICE(7, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
764	764
765	765	MCFG_KBDC8042_ADD("kbdc", at8042)
766
	766
767	767	/* video hardware */
768	768	MCFG_FRAGMENT_ADD( pcvideo_trident_vga )
769
	769
770	770	/* sound hardware */
771	771	MCFG_SPEAKER_STANDARD_STEREO("lspeaker","rspeaker")
772	772	MACHINE_CONFIG_END

trunk/src/mame/drivers/mlanding.c
r22615	r22616
324	324	m_dma_active = 1;
325	325	machine().scheduler().timer_set(attotime::from_msec(20), timer_expired_delegate(FUNC(mlanding_state::dma_complete),this));
326	326	}
327
	327
328	328	// 0 (falling edge?) starts cpus in this order:
329
	329
330	330	if (!(data & 0x40)) // $09b0 d6: sub cpu
331	331	m_subcpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
332	332
r22615	r22616
369	369	// d7: ?
370	370	UINT8 throttle = ioport("STICK1")->read();
371	371	UINT16 x = ioport("STICK2")->read();
372
	372
373	373	UINT8 res = 0xf0;
374	374
375	375	if (throttle & 0x80)
376	376	res ^= 0x2f;
377	377	else if (throttle > 0)
378	378	res ^= 0x40;
379
	379
380	380	if (!(x & 0x800) && x > 0)
381	381	res ^= 0x10;
382
	382
383	383	return res;
384	384	}
385	385
r22615	r22616
399	399	// d7: ?
400	400	UINT16 x = ioport("STICK2")->read();
401	401	UINT16 y = ioport("STICK3")->read();
402
	402
403	403	UINT8 res = (y >> 8 & 0x0f) \| 0xf0;
404	404
405	405	if (y & 0x800)
406	406	res ^= 0x40;
407	407	else if (y > 0)
408	408	res ^= 0x10;
409
	409
410	410	if (x & 0x800)
411	411	res ^= 0x20;
412
	412
413	413	return res;
414	414	}
415	415
r22615	r22616
439	439	AM_RANGE(0x1c4000, 0x1cffff) AM_RAM AM_SHARE("share1")
440	440
441	441	AM_RANGE(0x1d0000, 0x1d0001) AM_WRITE(ml_sub_reset_w)
442		// AM_RANGE(0x1d0002, 0x1d0003) AM_WRITENOP // ?
	442	// AM_RANGE(0x1d0002, 0x1d0003) AM_WRITENOP // ?
443	443
444	444	AM_RANGE(0x2d0000, 0x2d0001) AM_READNOP AM_DEVWRITE8("tc0140syt", tc0140syt_device, tc0140syt_port_w, 0x00ff)
445	445	AM_RANGE(0x2d0002, 0x2d0003) AM_DEVREADWRITE8("tc0140syt", tc0140syt_device, tc0140syt_comm_r, tc0140syt_comm_w, 0x00ff)

trunk/src/mame/drivers/n8080.c
r22615	r22616
468	468
469	469	MACHINE_START_MEMBER(n8080_state,n8080)
470	470	{
471
472	471	save_item(NAME(m_shift_data));
473	472	save_item(NAME(m_shift_bits));
474	473	save_item(NAME(m_inte));

trunk/src/mame/drivers/alpha68k.c
r22615	r22616
1862	1862
1863	1863	MACHINE_START_MEMBER(alpha68k_state,common)
1864	1864	{
1865
1866	1865	save_item(NAME(m_trigstate));
1867	1866	save_item(NAME(m_deposits1));
1868	1867	save_item(NAME(m_deposits2));

trunk/src/mame/drivers/unico.c
r22615	r22616
49	49	***************************************************************************/
50	50
51	51	WRITE16_MEMBER(unico_state::burglarx_sound_bank_w)
52		{
	52	{
53	53	if (ACCESSING_BITS_8_15)
54	54	{
55	55	int bank = (data >> 8 ) & 1;

trunk/src/mame/drivers/ojankohs.c
r22615	r22616
56	56	}
57	57
58	58	WRITE8_MEMBER(ojankohs_state::ojankohs_adpcm_reset_w)
59		{
	59	{
60	60	m_adpcm_reset = BIT(data, 0);
61	61	m_vclk_left = 0;
62	62

trunk/src/mame/drivers/lasso.c
r22615	r22616
470	470
471	471	void lasso_state::machine_start()
472	472	{
473
474	473	save_item(NAME(m_gfxbank));
475	474	}
476	475

trunk/src/mame/drivers/trvquest.c
r22615	r22616
166	166
167	167	MACHINE_START_MEMBER(gameplan_state,trvquest)
168	168	{
169
170	169	/* register for save states */
171	170	save_item(NAME(m_video_x));
172	171	save_item(NAME(m_video_y));

trunk/src/mame/drivers/gridlee.c
r22615	r22616
135	135
136	136	void gridlee_state::machine_start()
137	137	{
138
139	138	/* create the polynomial tables */
140	139	poly17_init();
141	140

trunk/src/mame/drivers/dogfgt.c
r22615	r22616
207	207
208	208	void dogfgt_state::machine_start()
209	209	{
210
211	210	save_item(NAME(m_bm_plane));
212	211	save_item(NAME(m_lastflip));
213	212	save_item(NAME(m_pixcolor));

trunk/src/mame/drivers/nmg5.c
r22615	r22616
987	987
988	988	void nmg5_state::machine_start()
989	989	{
990
991	990	save_item(NAME(m_gfx_bank));
992	991	save_item(NAME(m_priority_reg));
993	992	save_item(NAME(m_input_data));

trunk/src/mame/drivers/ladyfrog.c
r22615	r22616
275	275
276	276	void ladyfrog_state::machine_start()
277	277	{
278
279	278	save_item(NAME(m_tilebank));
280	279	save_item(NAME(m_palette_bank));
281	280	save_item(NAME(m_sound_nmi_enable));

trunk/src/mame/drivers/crgolf.c
r22615	r22616
73	73
74	74	void crgolf_state::machine_start()
75	75	{
76
77	76	/* configure the banking */
78	77	membank("bank1")->configure_entries(0, 16, memregion("maincpu")->base() + 0x10000, 0x2000);
79	78	membank("bank1")->set_entry(0);

trunk/src/mame/drivers/blockout.c
r22615	r22616
271	271
272	272	void blockout_state::machine_start()
273	273	{
274
275	274	save_item(NAME(m_color));
276	275	}
277	276

trunk/src/mame/drivers/amspdwy.c
r22615	r22616
240	240
241	241	void amspdwy_state::machine_start()
242	242	{
243
244	243	save_item(NAME(m_flipscreen));
245	244	save_item(NAME(m_wheel_old));
246	245	save_item(NAME(m_wheel_return));

trunk/src/mame/drivers/gluck2.c
r22615	r22616
189	189
190	190
191	191	#define MASTER_CLOCK XTAL_10MHz
192		#define SND_CLOCK XTAL_3_579545MHz
	192	#define SND_CLOCK XTAL_3_579545MHz
193	193
194	194	#include "emu.h"
195	195	#include "cpu/m6502/m6502.h"
r22615	r22616
250	250	*/
251	251	int attr = m_colorram[tile_index];
252	252	int code = m_videoram[tile_index];
253		int bank = ((attr & 0xc0) >> 5 ) + ((attr & 0x02) >> 1 ); /* bits 1-6-7 handle the gfx banks */
254		int color = (attr & 0x3c) >> 2; /* bits 2-3-4-5 handle the color */
	253	int bank = ((attr & 0xc0) >> 5 ) + ((attr & 0x02) >> 1 ); /* bits 1-6-7 handle the gfx banks */
	254	int color = (attr & 0x3c) >> 2; /* bits 2-3-4-5 handle the color */
255	255
256	256	SET_TILE_INFO_MEMBER(bank, code, color, 0);
257	257	}
r22615	r22616
337	337	AM_RANGE(0x0000, 0x07ff) AM_RAM AM_SHARE("nvram")
338	338	AM_RANGE(0x0800, 0x0800) AM_DEVWRITE("crtc", mc6845_device, address_w)
339	339	AM_RANGE(0x0801, 0x0801) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
340		AM_RANGE(0x0844, 0x084b) AM_NOP /* see below */
	340	AM_RANGE(0x0844, 0x084b) AM_NOP /* see below */
341	341	AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE(gluck2_videoram_w) AM_SHARE("videoram") /* 6116 #1 (2K x 8) RAM (only 1st half used) */
342	342	AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE(gluck2_colorram_w) AM_SHARE("colorram") /* 6116 #2 (2K x 8) RAM (only 1st half used) */
343	343	AM_RANGE(0x2000, 0x2000) AM_READ_PORT("SW1")
r22615	r22616
367	367	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_GAMBLE_D_UP )
368	368	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_GAMBLE_DEAL )
369	369	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_POKER_CANCEL )
370		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_NAME("Note In")
	370	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_NAME("Note In")
371	371	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_GAMBLE_KEYOUT )
372	372	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
373	373
r22615	r22616
391	391	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_CODE(KEYCODE_R) PORT_NAME("Reset")
392	392	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
393	393
394		PORT_START("SW1") // 2000
395		PORT_DIPNAME( 0x01, 0x01, "Paytable" ) PORT_DIPLOCATION("SW1:1")
	394	PORT_START("SW1") // 2000
	395	PORT_DIPNAME( 0x01, 0x01, "Paytable" ) PORT_DIPLOCATION("SW1:1")
396	396	PORT_DIPSETTING( 0x01, "Strings and Numbers" )
397	397	PORT_DIPSETTING( 0x00, "Only Numbers" )
398		PORT_DIPNAME( 0x02, 0x02, "SW1:2" ) PORT_DIPLOCATION("SW1:2")
	398	PORT_DIPNAME( 0x02, 0x02, "SW1:2" ) PORT_DIPLOCATION("SW1:2")
399	399	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
400	400	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
401		PORT_DIPNAME( 0x04, 0x04, "SW1:3" ) PORT_DIPLOCATION("SW1:3")
	401	PORT_DIPNAME( 0x04, 0x04, "SW1:3" ) PORT_DIPLOCATION("SW1:3")
402	402	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
403	403	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
404		PORT_DIPNAME( 0x08, 0x08, "SW1:4" ) PORT_DIPLOCATION("SW1:4")
	404	PORT_DIPNAME( 0x08, 0x08, "SW1:4" ) PORT_DIPLOCATION("SW1:4")
405	405	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
406	406	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
407		PORT_DIPNAME( 0x10, 0x10, "SW1:5" ) PORT_DIPLOCATION("SW1:5")
	407	PORT_DIPNAME( 0x10, 0x10, "SW1:5" ) PORT_DIPLOCATION("SW1:5")
408	408	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
409	409	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
410		PORT_DIPNAME( 0x20, 0x20, "SW1:6" ) PORT_DIPLOCATION("SW1:6")
	410	PORT_DIPNAME( 0x20, 0x20, "SW1:6" ) PORT_DIPLOCATION("SW1:6")
411	411	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
412	412	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
413		PORT_DIPNAME( 0x40, 0x40, "SW1:7" ) PORT_DIPLOCATION("SW1:7")
	413	PORT_DIPNAME( 0x40, 0x40, "SW1:7" ) PORT_DIPLOCATION("SW1:7")
414	414	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
415	415	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
416		PORT_DIPNAME( 0x80, 0x80, "SW1:8" ) PORT_DIPLOCATION("SW1:8")
	416	PORT_DIPNAME( 0x80, 0x80, "SW1:8" ) PORT_DIPLOCATION("SW1:8")
417	417	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
418	418	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
419	419
420		PORT_START("SW2") // 3D01: AY8910 port B
421		PORT_DIPNAME( 0x01, 0x01, "SW2:8" ) PORT_DIPLOCATION("SW2:8")
	420	PORT_START("SW2") // 3D01: AY8910 port B
	421	PORT_DIPNAME( 0x01, 0x01, "SW2:8" ) PORT_DIPLOCATION("SW2:8")
422	422	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
423	423	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
424		PORT_DIPNAME( 0x06, 0x02, "Bet Max" ) PORT_DIPLOCATION("SW2:7, 6")
	424	PORT_DIPNAME( 0x06, 0x02, "Bet Max" ) PORT_DIPLOCATION("SW2:7, 6")
425	425	PORT_DIPSETTING( 0x00, "10" )
426	426	PORT_DIPSETTING( 0x02, "20" )
427	427	PORT_DIPSETTING( 0x04, "30" )
428	428	PORT_DIPSETTING( 0x06, "40" )
429		PORT_DIPNAME( 0x08, 0x08, "SW2:5" ) PORT_DIPLOCATION("SW2:5")
	429	PORT_DIPNAME( 0x08, 0x08, "SW2:5" ) PORT_DIPLOCATION("SW2:5")
430	430	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
431	431	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
432		PORT_DIPNAME( 0x10, 0x10, "SW2:4" ) PORT_DIPLOCATION("SW2:4")
	432	PORT_DIPNAME( 0x10, 0x10, "SW2:4" ) PORT_DIPLOCATION("SW2:4")
433	433	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
434	434	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
435		PORT_DIPNAME( 0x20, 0x20, "SW2:3" ) PORT_DIPLOCATION("SW2:3")
	435	PORT_DIPNAME( 0x20, 0x20, "SW2:3" ) PORT_DIPLOCATION("SW2:3")
436	436	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
437	437	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
438		PORT_DIPNAME( 0xc0, 0xc0, "Note In" ) PORT_DIPLOCATION("SW2:2, 1")
	438	PORT_DIPNAME( 0xc0, 0xc0, "Note In" ) PORT_DIPLOCATION("SW2:2, 1")
439	439	PORT_DIPSETTING( 0x00, "10" )
440	440	PORT_DIPSETTING( 0x40, "20" )
441	441	PORT_DIPSETTING( 0x80, "50" )
442	442	PORT_DIPSETTING( 0xc0, "100" )
443	443
444		PORT_START("SW3") // 3D01: AY8910 port A
445		PORT_DIPNAME( 0x01, 0x01, "SW3:1" ) PORT_DIPLOCATION("SW3:1")
	444	PORT_START("SW3") // 3D01: AY8910 port A
	445	PORT_DIPNAME( 0x01, 0x01, "SW3:1" ) PORT_DIPLOCATION("SW3:1")
446	446	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
447	447	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
448		PORT_DIPNAME( 0x02, 0x02, "SW3:8" ) PORT_DIPLOCATION("SW3:8")
	448	PORT_DIPNAME( 0x02, 0x02, "SW3:8" ) PORT_DIPLOCATION("SW3:8")
449	449	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
450	450	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
451		PORT_DIPNAME( 0x04, 0x04, "Graphics" ) PORT_DIPLOCATION("SW3:7")
	451	PORT_DIPNAME( 0x04, 0x04, "Graphics" ) PORT_DIPLOCATION("SW3:7")
452	452	PORT_DIPSETTING( 0x04, "Turtles" )
453	453	PORT_DIPSETTING( 0x00, "Cards" )
454		PORT_DIPNAME( 0x18, 0x18, "Coin In" ) PORT_DIPLOCATION("SW3:6, 5")
	454	PORT_DIPNAME( 0x18, 0x18, "Coin In" ) PORT_DIPLOCATION("SW3:6, 5")
455	455	PORT_DIPSETTING( 0x00, "1" )
456	456	PORT_DIPSETTING( 0x08, "2" )
457	457	PORT_DIPSETTING( 0x10, "5" )
458	458	PORT_DIPSETTING( 0x18, "10" )
459		PORT_DIPNAME( 0x20, 0x20, "SW3:4" ) PORT_DIPLOCATION("SW3:4")
	459	PORT_DIPNAME( 0x20, 0x20, "SW3:4" ) PORT_DIPLOCATION("SW3:4")
460	460	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
461	461	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
462		PORT_DIPNAME( 0x40, 0x40, "SW3:3" ) PORT_DIPLOCATION("SW3:3")
	462	PORT_DIPNAME( 0x40, 0x40, "SW3:3" ) PORT_DIPLOCATION("SW3:3")
463	463	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
464	464	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
465		PORT_DIPNAME( 0x80, 0x80, "SW3:2" ) PORT_DIPLOCATION("SW3:2")
	465	PORT_DIPNAME( 0x80, 0x80, "SW3:2" ) PORT_DIPLOCATION("SW3:2")
466	466	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
467	467	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
468	468
r22615	r22616
476	476	static const gfx_layout tilelayout =
477	477	{
478	478	8, 8,
479		256, // 0x100 tiles per bank.
	479	256, // 0x100 tiles per bank.
480	480	3,
481	481	{ 0, RGN_FRAC(1,3), RGN_FRAC(2,3) },
482	482	{ 0, 1, 2, 3, 4, 5, 6, 7 },
r22615	r22616
535	535	/* Output ports have a minimal activity during init.
536	536	They seems unused (at least for Good Luck II)
537	537	*/
538		DEVCB_NULL,
	538	DEVCB_NULL,
539	539	DEVCB_NULL
540	540	};
541	541
r22615	r22616
574	574	/* sound hardware */
575	575	MCFG_SPEAKER_STANDARD_MONO("mono")
576	576
577		MCFG_SOUND_ADD("ay8910", AY8910, MASTER_CLOCK/8) /* guess */
	577	MCFG_SOUND_ADD("ay8910", AY8910, MASTER_CLOCK/8) /* guess */
578	578	MCFG_SOUND_CONFIG(ay8910_intf)
579	579	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
580	580
r22615	r22616
597	597	ROM_LOAD( "2.u32", 0x08000, 0x8000, CRC(6a621a98) SHA1(9c83eab9f0858735e0176e5335651dd2dc620229) )
598	598	ROM_LOAD( "1.u31", 0x10000, 0x8000, CRC(ea33db1a) SHA1(69c67944f5e8bd060335b5e14628c0e0828271a4) )
599	599
600		ROM_REGION( 0x0300, "proms", 0 ) // RGB
	600	ROM_REGION( 0x0300, "proms", 0 ) // RGB
601	601	ROM_LOAD( "v1.u27", 0x0000, 0x0100, CRC(1aa5479f) SHA1(246cc99e7b351d5546060807b8a0b8acfe2f8e39) )
602	602	ROM_LOAD( "v2.u26", 0x0100, 0x0100, CRC(8da53489) SHA1(b90f5dd4bc5b64009e8bfad8f79f23d4020e537b) )
603	603	ROM_LOAD( "v3.u25", 0x0200, 0x0100, CRC(a4d2c9c3) SHA1(a799875b8b92391696419081244da2e56216e024) )

trunk/src/mame/drivers/kchamp.c
r22615	r22616
379	379
380	380	MACHINE_START_MEMBER(kchamp_state,kchamp)
381	381	{
382
383	382	save_item(NAME(m_nmi_enable));
384	383	save_item(NAME(m_sound_nmi_enable));
385	384	}

trunk/src/mame/drivers/dlair.c
r22615	r22616
55	55	m_22vp932(*this, "ld_22vp932") ,
56	56	m_videoram(*this, "videoram"),
57	57	m_maincpu(*this, "maincpu"),
58		m_beeper(*this, "beeper") { }
	58	m_beeper(*this, "beeper") { }
59	59
60	60	void laserdisc_data_w(UINT8 data)
61	61	{

trunk/src/mame/drivers/pbaction.c
r22615	r22616
256	256
257	257	void pbaction_state::machine_start()
258	258	{
259
260	259	save_item(NAME(m_scroll));
261	260	}
262	261

trunk/src/mame/drivers/2mindril.c
r22615	r22616
423	423
424	424	MACHINE_START_MEMBER(_2mindril_state,drill)
425	425	{
426
427	426	save_item(NAME(m_defender_sensor));
428	427	save_item(NAME(m_shutter_sensor));
429	428	}

trunk/src/mame/drivers/taitowlf.c
r22615	r22616
673	673	MCFG_MC146818_ADD( "rtc", MC146818_STANDARD )
674	674
675	675	MCFG_KBDC8042_ADD("kbdc", at8042)
676
	676
677	677	/* video hardware */
678	678	#if ENABLE_VGA
679	679	MCFG_FRAGMENT_ADD( pcvideo_vga )

trunk/src/mame/drivers/funkball.c
r22615	r22616
1144	1144	MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
1145	1145
1146	1146	MCFG_KBDC8042_ADD("kbdc", at8042)
1147
	1147
1148	1148	/* video hardware */
1149	1149	MCFG_3DFX_VOODOO_1_ADD("voodoo_0", STD_VOODOO_1_CLOCK, voodoo_intf)
1150	1150

trunk/src/mame/drivers/gotcha.c
r22615	r22616
236	236
237	237	void gotcha_state::machine_start()
238	238	{
239
240	239	save_item(NAME(m_banksel));
241	240	save_item(NAME(m_gfxbank));
242	241	save_item(NAME(m_scroll));

trunk/src/mame/drivers/ladybug.c
r22615	r22616
729	729
730	730	MACHINE_START_MEMBER(ladybug_state,sraider)
731	731	{
732
733	732	save_item(NAME(m_grid_color));
734	733	save_item(NAME(m_sound_low));
735	734	save_item(NAME(m_sound_high));

trunk/src/mame/drivers/cave.c
r22615	r22616
1777	1777
1778	1778	MACHINE_START_MEMBER(cave_state,cave)
1779	1779	{
1780
1781	1780	save_item(NAME(m_soundbuf_len));
1782	1781	save_item(NAME(m_soundbuf_data));
1783	1782

trunk/src/mame/drivers/taito_l.c
r22615	r22616
139	139
140	140	MACHINE_START_MEMBER(taitol_state,taito_l)
141	141	{
142
143	142	save_item(NAME(m_rambanks));
144	143	save_item(NAME(m_palette_ram));
145	144	save_item(NAME(m_empty_ram));

trunk/src/mame/drivers/bwing.c
r22615	r22616
331	331
332	332	void bwing_state::machine_start()
333	333	{
334
335	334	save_item(NAME(m_palatch));
336	335	save_item(NAME(m_srbank));
337	336	save_item(NAME(m_mapmask));

trunk/src/mame/drivers/fcombat.c
r22615	r22616
257	257
258	258	void fcombat_state::machine_start()
259	259	{
260
261	260	save_item(NAME(m_cocktail_flip));
262	261	save_item(NAME(m_char_palette));
263	262	save_item(NAME(m_sprite_palette));

trunk/src/mame/drivers/macrossp.c
r22615	r22616
593	593
594	594	void macrossp_state::machine_start()
595	595	{
596
597	596	save_item(NAME(m_sndpending));
598	597	save_item(NAME(m_snd_toggle));
599	598	save_item(NAME(m_fade_effect));

trunk/src/mame/drivers/gladiatr.c
r22615	r22616
278	278
279	279	/Sound Functions/
280	280	WRITE8_MEMBER(gladiatr_state::glad_adpcm_w)
281		{
	281	{
282	282	UINT8 *rom = memregion("audiocpu")->base() + 0x10000;
283	283
284	284	/* bit6 = bank offset */

trunk/src/mame/drivers/gamecstl.c
r22615	r22616
730	730	MCFG_MC146818_ADD( "rtc", MC146818_STANDARD )
731	731
732	732	MCFG_KBDC8042_ADD("kbdc", at8042)
733
	733
734	734	/* video hardware */
735	735	MCFG_SCREEN_ADD("screen", RASTER)
736	736	MCFG_SCREEN_REFRESH_RATE(60)

trunk/src/mame/drivers/pinball2k.c
r22615	r22616
1		/*
	1	/*
2	2	Pinball 2000
3
	3
4	4	Skeleton by R. Belmont, based on mediagx.c by Ville Linde
5
	5
6	6	TODO:
7		- Everything!
8		- BIOS hangs waiting for port 0400h to return 0x80. If you make that happy it jumps off into the weeds.
9		- MediaGX features should be moved out to machine/ and shared with mediagx.c once we know what these games need
10
	7	- Everything!
	8	- BIOS hangs waiting for port 0400h to return 0x80. If you make that happy it jumps off into the weeds.
	9	- MediaGX features should be moved out to machine/ and shared with mediagx.c once we know what these games need
	10
11	11	Hardware:
12		- Cyrix MediaGX processor/VGA
13		- Cyrix CX5520 northbridge?
14		- VS9824AG SuperI/O standard PC I/O chip
15		- 1 ISA, 2 PCI slots, 2 IDE headers
16		- "Prism" PCI card with PLX PCI9052 PCI-to-random stuff bridge
17		Card also contains DCS2 Stereo sound system with ADSP-2104
	12	- Cyrix MediaGX processor/VGA
	13	- Cyrix CX5520 northbridge?
	14	- VS9824AG SuperI/O standard PC I/O chip
	15	- 1 ISA, 2 PCI slots, 2 IDE headers
	16	- "Prism" PCI card with PLX PCI9052 PCI-to-random stuff bridge
	17	Card also contains DCS2 Stereo sound system with ADSP-2104
18	18	*/
19	19
20	20	#include "emu.h"
r22615	r22616
919	919	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
920	920	MACHINE_CONFIG_END
921	921
922
	922
923	923	void pinball2k_state::init_mediagx()
924	924	{
925	925	m_frame_width = m_frame_height = 1;
r22615	r22616
934	934
935	935	ROM_START( swe1pb )
936	936	ROM_REGION32_LE(0x40000, "bios", 0)
937		ROM_LOAD( "awdbios.bin", 0x000000, 0x040000, CRC(854ce8c6) SHA1(7826de74026e052dacce8516382f664004c327ad) )
	937	ROM_LOAD( "awdbios.bin", 0x000000, 0x040000, CRC(854ce8c6) SHA1(7826de74026e052dacce8516382f664004c327ad) )
938	938
939	939	ROM_REGION(0x4800000, "prism", 0)
940		ROM_LOAD( "swe1_u100.rom", 0x0000000, 0x800000, CRC(db2c9709) SHA1(14e8db2c0b09c4da6306a4a1f7fe54b2a334c5ed) )
941		ROM_LOAD( "swe1_u101.rom", 0x0800000, 0x800000, CRC(a039e80d) SHA1(8f63e8ab83e043232fc17ed3dff1f251396a178a) )
942		ROM_LOAD( "swe1_u102.rom", 0x1000000, 0x800000, CRC(c9feb7bc) SHA1(a34acd34c3f91f082b67e385b1f4da2e5b6e5087) )
943		ROM_LOAD( "swe1_u103.rom", 0x1800000, 0x800000, CRC(7a692466) SHA1(9adf5ae9c12bd5b6314913f6c01d4566ee453fe1) )
944		ROM_LOAD( "swe1_u104.rom", 0x2000000, 0x800000, CRC(76e2dd7e) SHA1(9bc20a1423b11c46eb2f5a514e985151defb5651) )
945		ROM_LOAD( "swe1_u105.rom", 0x2800000, 0x800000, CRC(87f2460c) SHA1(cdc05e017367f61280e3d5682096e67e4c200150) )
946		ROM_LOAD( "swe1_u106.rom", 0x3000000, 0x800000, CRC(84877e2f) SHA1(6dd8c761b2e26313ae9e159690b3a4a170cb3bd8) )
947		ROM_LOAD( "swe1_u107.rom", 0x3800000, 0x800000, CRC(dc433c89) SHA1(9f1273debc9168c04202078503cfc4f1ca8cb30b) )
948		ROM_LOAD( "swe1_u109.rom", 0x4000000, 0x400000, CRC(cc08936b) SHA1(fc428393e8a0cf37b800dd475fd293a1a98c4bcf) )
949		ROM_LOAD( "swe1_u110.rom", 0x4400000, 0x400000, CRC(6011ecd9) SHA1(8575958c8942a6cbcb2ac18f291fcada6f8cbc09) )
	940	ROM_LOAD( "swe1_u100.rom", 0x0000000, 0x800000, CRC(db2c9709) SHA1(14e8db2c0b09c4da6306a4a1f7fe54b2a334c5ed) )
	941	ROM_LOAD( "swe1_u101.rom", 0x0800000, 0x800000, CRC(a039e80d) SHA1(8f63e8ab83e043232fc17ed3dff1f251396a178a) )
	942	ROM_LOAD( "swe1_u102.rom", 0x1000000, 0x800000, CRC(c9feb7bc) SHA1(a34acd34c3f91f082b67e385b1f4da2e5b6e5087) )
	943	ROM_LOAD( "swe1_u103.rom", 0x1800000, 0x800000, CRC(7a692466) SHA1(9adf5ae9c12bd5b6314913f6c01d4566ee453fe1) )
	944	ROM_LOAD( "swe1_u104.rom", 0x2000000, 0x800000, CRC(76e2dd7e) SHA1(9bc20a1423b11c46eb2f5a514e985151defb5651) )
	945	ROM_LOAD( "swe1_u105.rom", 0x2800000, 0x800000, CRC(87f2460c) SHA1(cdc05e017367f61280e3d5682096e67e4c200150) )
	946	ROM_LOAD( "swe1_u106.rom", 0x3000000, 0x800000, CRC(84877e2f) SHA1(6dd8c761b2e26313ae9e159690b3a4a170cb3bd8) )
	947	ROM_LOAD( "swe1_u107.rom", 0x3800000, 0x800000, CRC(dc433c89) SHA1(9f1273debc9168c04202078503cfc4f1ca8cb30b) )
	948	ROM_LOAD( "swe1_u109.rom", 0x4000000, 0x400000, CRC(cc08936b) SHA1(fc428393e8a0cf37b800dd475fd293a1a98c4bcf) )
	949	ROM_LOAD( "swe1_u110.rom", 0x4400000, 0x400000, CRC(6011ecd9) SHA1(8575958c8942a6cbcb2ac18f291fcada6f8cbc09) )
950	950
951	951	ROM_REGION(0x08100, "gfx1", 0)
952	952	ROM_LOAD("cga.chr", 0x00000, 0x01000, CRC(42009069) SHA1(ed08559ce2d7f97f68b9f540bddad5b6295294dd))
r22615	r22616
954	954
955	955	ROM_START( rfmpb )
956	956	ROM_REGION32_LE(0x40000, "bios", 0)
957		ROM_LOAD( "awdbios.bin", 0x000000, 0x040000, CRC(854ce8c6) SHA1(7826de74026e052dacce8516382f664004c327ad) )
	957	ROM_LOAD( "awdbios.bin", 0x000000, 0x040000, CRC(854ce8c6) SHA1(7826de74026e052dacce8516382f664004c327ad) )
958	958
959	959	ROM_REGION(0x4000000, "prism", 0)
960		ROM_LOAD( "rfm_u100.rom", 0x0000000, 0x800000, CRC(b3548b1b) SHA1(874a16282bb778886cea2567d68ec7024dc5ed22) )
961		ROM_LOAD( "rfm_u101.rom", 0x0800000, 0x800000, CRC(8bef301d) SHA1(2eade00b1a4cd3f5e98ebe8ed8f549e328188e77) )
962		ROM_LOAD( "rfm_u102.rom", 0x1000000, 0x800000, CRC(749f5c59) SHA1(2d8850e7f8ea3e07e8b444d7dd4dc4195a547ae7) )
963		ROM_LOAD( "rfm_u103.rom", 0x1800000, 0x800000, CRC(a9ec5e97) SHA1(ce7c38dcbf34ce10d6e204a3176cd2c7a83b525a) )
964		ROM_LOAD( "rfm_u104.rom", 0x2000000, 0x800000, CRC(0a1acd70) SHA1(dcca4de92eadeb82ac776953326410a9687838cb) )
965		ROM_LOAD( "rfm_u105.rom", 0x2800000, 0x800000, CRC(1ef31684) SHA1(141900a7426ad483384606cddb018d186952f439) )
966		ROM_LOAD( "rfm_u106.rom", 0x3000000, 0x800000, CRC(daf4e1dc) SHA1(0612495468fb962b833057e50f620c5f69cd5840) )
967		ROM_LOAD( "rfm_u107.rom", 0x3800000, 0x800000, CRC(e737ab39) SHA1(0e978923db19e2893fdb4aae69d6ed3c3f664a31) )
	960	ROM_LOAD( "rfm_u100.rom", 0x0000000, 0x800000, CRC(b3548b1b) SHA1(874a16282bb778886cea2567d68ec7024dc5ed22) )
	961	ROM_LOAD( "rfm_u101.rom", 0x0800000, 0x800000, CRC(8bef301d) SHA1(2eade00b1a4cd3f5e98ebe8ed8f549e328188e77) )
	962	ROM_LOAD( "rfm_u102.rom", 0x1000000, 0x800000, CRC(749f5c59) SHA1(2d8850e7f8ea3e07e8b444d7dd4dc4195a547ae7) )
	963	ROM_LOAD( "rfm_u103.rom", 0x1800000, 0x800000, CRC(a9ec5e97) SHA1(ce7c38dcbf34ce10d6e204a3176cd2c7a83b525a) )
	964	ROM_LOAD( "rfm_u104.rom", 0x2000000, 0x800000, CRC(0a1acd70) SHA1(dcca4de92eadeb82ac776953326410a9687838cb) )
	965	ROM_LOAD( "rfm_u105.rom", 0x2800000, 0x800000, CRC(1ef31684) SHA1(141900a7426ad483384606cddb018d186952f439) )
	966	ROM_LOAD( "rfm_u106.rom", 0x3000000, 0x800000, CRC(daf4e1dc) SHA1(0612495468fb962b833057e50f620c5f69cd5840) )
	967	ROM_LOAD( "rfm_u107.rom", 0x3800000, 0x800000, CRC(e737ab39) SHA1(0e978923db19e2893fdb4aae69d6ed3c3f664a31) )
968	968
969	969	ROM_REGION(0x08100, "gfx1", 0)
970	970	ROM_LOAD("cga.chr", 0x00000, 0x01000, CRC(42009069) SHA1(ed08559ce2d7f97f68b9f540bddad5b6295294dd))
r22615	r22616
972	972
973	973	ROM_START( rfmpbr2 )
974	974	ROM_REGION32_LE(0x40000, "bios", 0)
975		ROM_LOAD( "awdbios.bin", 0x000000, 0x040000, CRC(854ce8c6) SHA1(7826de74026e052dacce8516382f664004c327ad) )
	975	ROM_LOAD( "awdbios.bin", 0x000000, 0x040000, CRC(854ce8c6) SHA1(7826de74026e052dacce8516382f664004c327ad) )
976	976
977	977	ROM_REGION(0x4800000, "prism", 0)
978		ROM_LOAD( "rfm_u100r2.rom", 0x0000000, 0x800000, CRC(d4278a9b) SHA1(ec07b97190acb6b34b9ed6cda505ee8fefd66fec) )
979		ROM_LOAD( "rfm_u101r2.rom", 0x0800000, 0x800000, CRC(e5d4c0ed) SHA1(cfc7d9d2324cc02c9eaf53fd674f7db24736699c) )
980		ROM_LOAD( "rfm_u102.rom", 0x1000000, 0x800000, CRC(749f5c59) SHA1(2d8850e7f8ea3e07e8b444d7dd4dc4195a547ae7) )
981		ROM_LOAD( "rfm_u103.rom", 0x1800000, 0x800000, CRC(a9ec5e97) SHA1(ce7c38dcbf34ce10d6e204a3176cd2c7a83b525a) )
982		ROM_LOAD( "rfm_u104.rom", 0x2000000, 0x800000, CRC(0a1acd70) SHA1(dcca4de92eadeb82ac776953326410a9687838cb) )
983		ROM_LOAD( "rfm_u105.rom", 0x2800000, 0x800000, CRC(1ef31684) SHA1(141900a7426ad483384606cddb018d186952f439) )
984		ROM_LOAD( "rfm_u106.rom", 0x3000000, 0x800000, CRC(daf4e1dc) SHA1(0612495468fb962b833057e50f620c5f69cd5840) )
985		ROM_LOAD( "rfm_u107.rom", 0x3800000, 0x800000, CRC(e737ab39) SHA1(0e978923db19e2893fdb4aae69d6ed3c3f664a31) )
986		ROM_LOAD( "rfm_u109.bin", 0x4000000, 0x400000, CRC(a20b2abb) SHA1(0010d7dbf60b03f50cc1d314fdf786721161b064) )
987		ROM_LOAD( "rfm_u110.bin", 0x4400000, 0x400000, CRC(095abec9) SHA1(87ce156bbf673ebd50bbd7dcca4c6924d24fc823) )
	978	ROM_LOAD( "rfm_u100r2.rom", 0x0000000, 0x800000, CRC(d4278a9b) SHA1(ec07b97190acb6b34b9ed6cda505ee8fefd66fec) )
	979	ROM_LOAD( "rfm_u101r2.rom", 0x0800000, 0x800000, CRC(e5d4c0ed) SHA1(cfc7d9d2324cc02c9eaf53fd674f7db24736699c) )
	980	ROM_LOAD( "rfm_u102.rom", 0x1000000, 0x800000, CRC(749f5c59) SHA1(2d8850e7f8ea3e07e8b444d7dd4dc4195a547ae7) )
	981	ROM_LOAD( "rfm_u103.rom", 0x1800000, 0x800000, CRC(a9ec5e97) SHA1(ce7c38dcbf34ce10d6e204a3176cd2c7a83b525a) )
	982	ROM_LOAD( "rfm_u104.rom", 0x2000000, 0x800000, CRC(0a1acd70) SHA1(dcca4de92eadeb82ac776953326410a9687838cb) )
	983	ROM_LOAD( "rfm_u105.rom", 0x2800000, 0x800000, CRC(1ef31684) SHA1(141900a7426ad483384606cddb018d186952f439) )
	984	ROM_LOAD( "rfm_u106.rom", 0x3000000, 0x800000, CRC(daf4e1dc) SHA1(0612495468fb962b833057e50f620c5f69cd5840) )
	985	ROM_LOAD( "rfm_u107.rom", 0x3800000, 0x800000, CRC(e737ab39) SHA1(0e978923db19e2893fdb4aae69d6ed3c3f664a31) )
	986	ROM_LOAD( "rfm_u109.bin", 0x4000000, 0x400000, CRC(a20b2abb) SHA1(0010d7dbf60b03f50cc1d314fdf786721161b064) )
	987	ROM_LOAD( "rfm_u110.bin", 0x4400000, 0x400000, CRC(095abec9) SHA1(87ce156bbf673ebd50bbd7dcca4c6924d24fc823) )
988	988
989	989	ROM_REGION(0x08100, "gfx1", 0)
990	990	ROM_LOAD("cga.chr", 0x00000, 0x01000, CRC(42009069) SHA1(ed08559ce2d7f97f68b9f540bddad5b6295294dd))
r22615	r22616
995	995	GAME( 1999, swe1pb, 0 , mediagx, mediagx, pinball2k_state, pinball2k, ROT0, "Midway", "Pinball 2000: Star Wars Episode 1", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_MECHANICAL )
996	996	GAME( 1999, rfmpb, 0 , mediagx, mediagx, pinball2k_state, pinball2k, ROT0, "Midway", "Pinball 2000: Revenge From Mars (rev. 1)", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_MECHANICAL )
997	997	GAME( 1999, rfmpbr2, rfmpb , mediagx, mediagx, pinball2k_state, pinball2k, ROT0, "Midway", "Pinball 2000: Revenge From Mars (rev. 2)", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_MECHANICAL )
998

trunk/src/mame/drivers/mgolf.c
r22615	r22616
308	308
309	309	void mgolf_state::machine_start()
310	310	{
311
312	311	save_item(NAME(m_prev));
313	312	save_item(NAME(m_mask));
314	313	}

trunk/src/mame/drivers/champbas.c
r22615	r22616
578	578
579	579	MACHINE_START_MEMBER(champbas_state,exctsccr)
580	580	{
581
582	581	// FIXME
583	582	machine().scheduler().timer_pulse(attotime::from_hz(75), timer_expired_delegate(FUNC(champbas_state::exctsccr_fm_callback),this)); /* updates fm */
584	583

trunk/src/mame/drivers/brkthru.c
r22615	r22616
363	363
364	364	void brkthru_state::machine_start()
365	365	{
366
367	366	save_item(NAME(m_bgscroll));
368	367	save_item(NAME(m_bgbasecolor));
369	368	save_item(NAME(m_flipscreen));

trunk/src/mame/drivers/gammagic.c
r22615	r22616
80	80	m_pic8259_1(*this, "pic8259_1" ),
81	81	m_pic8259_2(*this, "pic8259_2" ),
82	82	m_dma8237_1(*this, "dma8237_1" ),
83		m_dma8237_2(*this, "dma8237_2" ),
	83	m_dma8237_2(*this, "dma8237_2" ),
84	84	m_maincpu(*this, "maincpu") { }
85	85
86	86	int m_dma_channel;
r22615	r22616
120	120	DECLARE_WRITE_LINE_MEMBER(pc_dack0_w);
121	121	DECLARE_WRITE_LINE_MEMBER(pc_dack1_w);
122	122	DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
123		DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
	123	DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
124	124	DECLARE_WRITE_LINE_MEMBER(gammagic_pic8259_1_set_int_line);
125	125	DECLARE_READ8_MEMBER(get_slave_ack);
126
	126
127	127	virtual void machine_start();
128	128	virtual void machine_reset();
129	129	void atapi_init();
r22615	r22616
781	781	// MCFG_PCI_BUS_DEVICE(1, "i82371sb", i82371sb_pci_read, i82371sb_pci_write)
782	782	/* video hardware */
783	783	MCFG_FRAGMENT_ADD( pcvideo_vga )
784
	784
785	785	MCFG_KBDC8042_ADD("kbdc", at8042)
786	786
787	787	MACHINE_CONFIG_END

trunk/src/mame/drivers/cubeqst.c
r22615	r22616
42	42	required_device<simutrek_special_device> m_laserdisc;
43	43	required_device<cpu_device> m_rotatecpu;
44	44	required_device<cpu_device> m_linecpu;
45		required_device<cpu_device> m_soundcpu;
	45	required_device<cpu_device> m_soundcpu;
46	46	rgb_t *m_colormap;
47	47	DECLARE_WRITE16_MEMBER(palette_w);
48	48	DECLARE_READ16_MEMBER(line_r);

trunk/src/mame/drivers/exerion.c
r22615	r22616
379	379
380	380	void exerion_state::machine_start()
381	381	{
382
383	382	save_item(NAME(m_porta));
384	383	save_item(NAME(m_portb));
385	384	save_item(NAME(m_cocktail_flip));

trunk/src/mame/drivers/battlane.c
r22615	r22616
266	266
267	267	void battlane_state::machine_start()
268	268	{
269
270	269	save_item(NAME(m_video_ctrl));
271	270	save_item(NAME(m_cpu_control));
272	271	}

trunk/src/mame/drivers/bking.c
r22615	r22616
390	390
391	391	void bking_state::machine_start()
392	392	{
393
394	393	/* video */
395	394	save_item(NAME(m_pc3259_output));
396	395	save_item(NAME(m_pc3259_mask));

trunk/src/mame/drivers/crospang.c
r22615	r22616
328	328
329	329	void crospang_state::machine_start()
330	330	{
331
332	331	save_item(NAME(m_bestri_tilebank));
333	332
334	333	}

trunk/src/mame/drivers/orbit.c
r22615	r22616
269	269
270	270	void orbit_state::machine_start()
271	271	{
272
273	272	save_item(NAME(m_misc_flags));
274	273	save_item(NAME(m_flip_screen));
275	274	}

trunk/src/mame/drivers/csplayh5.c
r22615	r22616
85	85	TIMER_DEVICE_CALLBACK_MEMBER(csplayh5_irq);
86	86	DECLARE_WRITE_LINE_MEMBER(csplayh5_vdp0_interrupt);
87	87	required_device<dac_device> m_dac1;
88		required_device<dac_device> m_dac2;
	88	required_device<dac_device> m_dac2;
89	89	};
90	90
91	91

trunk/src/mame/drivers/ddragon3.c
r22615	r22616
540	540
541	541	void ddragon3_state::machine_start()
542	542	{
543
544	543	save_item(NAME(m_vreg));
545	544	save_item(NAME(m_bg_scrollx));
546	545	save_item(NAME(m_bg_scrolly));

trunk/src/mame/drivers/mouser.c
r22615	r22616
182	182
183	183	void mouser_state::machine_start()
184	184	{
185
186	185	save_item(NAME(m_sound_byte));
187	186	save_item(NAME(m_nmi_enable));
188	187	}

trunk/src/mame/drivers/discoboy.c
r22615	r22616
456	456
457	457	void discoboy_state::machine_start()
458	458	{
459
460	459	save_item(NAME(m_ram_bank));
461	460	save_item(NAME(m_port_00));
462	461	save_item(NAME(m_gfxbank));

trunk/src/mame/drivers/gaiden.c
r22615	r22616
306	306
307	307	MACHINE_START_MEMBER(gaiden_state,raiga)
308	308	{
309
310	309	save_item(NAME(m_prot));
311	310	save_item(NAME(m_jumpcode));
312	311

trunk/src/mame/drivers/xtom3d.c
r22615	r22616
673	673	MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
674	674
675	675	MCFG_KBDC8042_ADD("kbdc", at8042)
676
	676
677	677	/* video hardware */
678	678	MCFG_FRAGMENT_ADD( pcvideo_vga )
679	679	MACHINE_CONFIG_END

trunk/src/mame/drivers/btime.c
r22615	r22616
1240	1240
1241	1241	MACHINE_START_MEMBER(btime_state,btime)
1242	1242	{
1243
1244	1243	save_item(NAME(m_btime_palette));
1245	1244	save_item(NAME(m_bnj_scroll1));
1246	1245	save_item(NAME(m_bnj_scroll2));

trunk/src/mame/drivers/atvtrack.c
r22615	r22616
148	148	// old = m_area1_data[addr];
149	149	m_area1_data[addr] = dat;
150	150	if (addr == (0x00020000-0x00020000)/4) {
151		if (data & 4) {
	151	if (data & 4) {
152	152	m_subcpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
153	153	}
154	154	}

trunk/src/mame/drivers/cps2.c
r22615	r22616
1240	1240
1241	1241	MACHINE_START_MEMBER(cps_state,cps2)
1242	1242	{
1243
1244	1243	if (m_audiocpu != NULL) // gigaman2 has no audiocpu
1245	1244	membank("bank1")->configure_entries(0, (QSOUND_SIZE - 0x10000) / 0x4000, memregion("audiocpu")->base() + 0x10000, 0x4000);
1246	1245	}

trunk/src/mame/drivers/chinagat.c
r22615	r22616
239	239	}
240	240
241	241	WRITE8_MEMBER(chinagat_state::saiyugoub1_adpcm_control_w )
242		{
	242	{
243	243	/* i8748 Port 2 write */
244	244	UINT8 *saiyugoub1_adpcm_rom = memregion("adpcm")->base();
245	245
r22615	r22616
291	291	/* to the xtal pins of the MSM5205 */
292	292
293	293	/* Actually, T0 output clk mode is not supported by the i8048 core */
294		#if 0
	294	#if 0
295	295	m_m5205_clk++;
296	296	if (m_m5205_clk == 8)
297	297	{

trunk/src/mame/drivers/chanbara.c
r22615	r22616
385	385
386	386	void chanbara_state::machine_start()
387	387	{
388
389	388	save_item(NAME(m_scroll));
390	389	save_item(NAME(m_scrollhi));
391	390	}

trunk/src/mame/drivers/espial.c
r22615	r22616
54	54
55	55	void espial_state::machine_start()
56	56	{
57
58	57	//state_save_register_global_array(machine(), mcu_out[1]);
59	58	save_item(NAME(m_sound_nmi_enabled));
60	59	}

trunk/src/mame/drivers/iteagle.c
r22615	r22616
5	5	skeleton by R. Belmont
6	6
7	7	Known games on this hardware and their security chip IDs:
8		* E2-LED0 (c) 2000 Golden Tee Fore!
9		* E2-BBH0 (c) 2000 Big Buck Hunter
10		* G42-US-U (c) 2001 Golden Tee Fore! 2002
11		* BB15-US (c) 2002 Big Buck Hunter: Shooter's Challenge (AKA Big Buck Hunter v1.5)
12		* BBH2-US (c) 2002 Big Buck Hunter II: Sportsman's Paradise
13		* CK1-US (C) 2002 Carnival King
14		* G43-US-U (c) 2002 Golden Tee Fore! 2003
15		* G44-US-U (c) 2003 Golden Tee Fore! 2004
16		* G45-US-U (c) 2004 Golden Tee Fore! 2005
17		* CW-US-U (c) 2005 Big Buck Hunter: Call of the Wild
18		* G4C-US-U (c) 2006 Golden Tee Complete
19		* ???????? (c) ???? Virtual Pool (not on IT's website master list but known to exist)
20
21		Valid regions: US = USA, CAN = Canada, ENG = England, EUR = Euro, SWD = Sweden, AUS = Australia, NZ = New Zealand, SA = South Africa
22
	8	* E2-LED0 (c) 2000 Golden Tee Fore!
	9	* E2-BBH0 (c) 2000 Big Buck Hunter
	10	* G42-US-U (c) 2001 Golden Tee Fore! 2002
	11	* BB15-US (c) 2002 Big Buck Hunter: Shooter's Challenge (AKA Big Buck Hunter v1.5)
	12	* BBH2-US (c) 2002 Big Buck Hunter II: Sportsman's Paradise
	13	* CK1-US (C) 2002 Carnival King
	14	* G43-US-U (c) 2002 Golden Tee Fore! 2003
	15	* G44-US-U (c) 2003 Golden Tee Fore! 2004
	16	* G45-US-U (c) 2004 Golden Tee Fore! 2005
	17	* CW-US-U (c) 2005 Big Buck Hunter: Call of the Wild
	18	* G4C-US-U (c) 2006 Golden Tee Complete
	19	* ???????? (c) ???? Virtual Pool (not on IT's website master list but known to exist)
	20
	21	Valid regions: US = USA, CAN = Canada, ENG = England, EUR = Euro, SWD = Sweden, AUS = Australia, NZ = New Zealand, SA = South Africa
	22
23	23	Hardware overview:
24	24	* NEC VR4310 CPU (similar to the N64's VR4300)
25	25	* NEC VR4373 "Nile 3" system controller / PCI bridge
26		* 3DFX Voodoo Banshee video
27		* Creative/Ensoniq AudioPCI ES1373 audio
28		* Atmel 90S2313 AVR-based microcontroller for protection
29		* STM48T02 NVRAM
30		* Conexant CX88168 modem
31
	26	* 3DFX Voodoo Banshee video
	27	* Creative/Ensoniq AudioPCI ES1373 audio
	28	* Atmel 90S2313 AVR-based microcontroller for protection
	29	* STM48T02 NVRAM
	30	* Conexant CX88168 modem
	31
32	32	TODO:
33		* Everything (need new PCI subsystem to do this right)
34
	33	* Everything (need new PCI subsystem to do this right)
	34
35	35	***************************************************************************/
36	36
37		/*
38
	37	/*
	38
39	39	Big Buck Hunter II
40	40	Incredible Technologies 2004
41	41
r22615	r22616
78	78	\| \| \| \|VRC 4373 \| \|
79	79	\| \|--------\| \|REV1.0 \| CREATIVE \|
80	80	\|PAL(E2-RE53) \|-----------\| ES1373 \|
81		\|--------------------------------------------------------------------\|
82
	81	\|--------------------------------------------------------------------\|
	82
83	83	*/
84	84
85	85	#include "emu.h"
r22615	r22616
101	101
102	102	DECLARE_DRIVER_INIT(iteagle);
103	103	DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
104		DECLARE_WRITE_LINE_MEMBER(vblank_assert);
	104	DECLARE_WRITE_LINE_MEMBER(vblank_assert);
105	105	UINT32 screen_update_iteagle(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
106	106	virtual void machine_start();
107	107	};
r22615	r22616
151	151
152	152	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 32, iteagle_state )
153	153	ADDRESS_MAP_UNMAP_HIGH
154		AM_RANGE(0x00000000, 0x01ffffff) AM_RAM
	154	AM_RANGE(0x00000000, 0x01ffffff) AM_RAM
155	155	// Nile 3 northbridge/PCI controller at 0f000000
156	156	AM_RANGE(0x1fc00000, 0x1fcfffff) AM_ROM AM_REGION("maincpu", 0) AM_SHARE("rombase")
157	157	ADDRESS_MAP_END
r22615	r22616
188	188
189	189	static const mips3_config r4310_config =
190	190	{
191		16384, /* code cache size */
192		16384 /* data cache size */
	191	16384, /* code cache size */
	192	16384 /* data cache size */
193	193	};
194	194
195	195	static MACHINE_CONFIG_START( gtfore, iteagle_state )
r22615	r22616
224	224	*************************************/
225	225
226	226	#define EAGLE_BIOS \
227		ROM_REGION( 0x100000, "maincpu", 0 ) /* MIPS code */ \
	227	ROM_REGION( 0x100000, "maincpu", 0 ) /* MIPS code */ \
228	228	ROM_SYSTEM_BIOS( 0, "209", "bootrom 2.09" ) \
229		ROM_LOAD( "eagle209.u15", 0x000000, 0x100000, CRC(e0fc1a16) SHA1(c9524f7ee6b95bd484a3b75bcbe2243cb273f84c) ) \
	229	ROM_LOAD( "eagle209.u15", 0x000000, 0x100000, CRC(e0fc1a16) SHA1(c9524f7ee6b95bd484a3b75bcbe2243cb273f84c) ) \
230	230	ROM_SYSTEM_BIOS( 1, "208", "bootrom 2.08" ) \
231		ROM_LOAD( "eagle208.u15", 0x000000, 0x100000, CRC(772f2864) SHA1(085063a4e34f29ebe3814823cd2c6323a050da36) ) \
	231	ROM_LOAD( "eagle208.u15", 0x000000, 0x100000, CRC(772f2864) SHA1(085063a4e34f29ebe3814823cd2c6323a050da36) ) \
232	232	ROM_SYSTEM_BIOS( 2, "204", "bootrom 2.04" ) \
233		ROM_LOAD( "eagle204.u15", 0x000000, 0x100000, CRC(f02e5523) SHA1(b979cf72a6992f1ecad9695a08c8d51e315ab537) ) \
	233	ROM_LOAD( "eagle204.u15", 0x000000, 0x100000, CRC(f02e5523) SHA1(b979cf72a6992f1ecad9695a08c8d51e315ab537) ) \
234	234	ROM_SYSTEM_BIOS( 3, "201", "bootrom 2.01" ) \
235		ROM_LOAD( "eagle201.u15", 0x000000, 0x100000, CRC(e180442b) SHA1(4f50821fed5bcd786d989520aa2559d6c416fb1f) ) \
	235	ROM_LOAD( "eagle201.u15", 0x000000, 0x100000, CRC(e180442b) SHA1(4f50821fed5bcd786d989520aa2559d6c416fb1f) ) \
236	236	ROM_SYSTEM_BIOS( 4, "107", "bootrom 1.07" ) \
237		ROM_LOAD( "eagle107.u15", 0x000000, 0x100000, CRC(97a01fc9) SHA1(a421dbf4d097b2f50cc005d3cd0d63e562e03df8) ) \
	237	ROM_LOAD( "eagle107.u15", 0x000000, 0x100000, CRC(97a01fc9) SHA1(a421dbf4d097b2f50cc005d3cd0d63e562e03df8) ) \
238	238	ROM_SYSTEM_BIOS( 5, "106a", "bootrom 1.06a" ) \
239		ROM_LOAD( "eagle106a.u15", 0x000000, 0x100000, CRC(9c79b7ad) SHA1(ccf1c86e79d65bee30f399e0fa33a7839570d93b) ) \
	239	ROM_LOAD( "eagle106a.u15", 0x000000, 0x100000, CRC(9c79b7ad) SHA1(ccf1c86e79d65bee30f399e0fa33a7839570d93b) ) \
240	240	ROM_SYSTEM_BIOS( 6, "106", "bootrom 1.06" ) \
241		ROM_LOAD( "eagle106.u15", 0x000000, 0x100000, CRC(56bc193d) SHA1(e531d208ef27f777d0784414885f390d1be654b9) ) \
	241	ROM_LOAD( "eagle106.u15", 0x000000, 0x100000, CRC(56bc193d) SHA1(e531d208ef27f777d0784414885f390d1be654b9) ) \
242	242	ROM_SYSTEM_BIOS( 7, "105", "bootrom 1.05" ) \
243		ROM_LOAD( "eagle105.u15", 0x000000, 0x100000, CRC(3870dbe0) SHA1(09be2d86c7259cd81d945c757044b167a76f30db) ) \
	243	ROM_LOAD( "eagle105.u15", 0x000000, 0x100000, CRC(3870dbe0) SHA1(09be2d86c7259cd81d945c757044b167a76f30db) ) \
244	244	ROM_SYSTEM_BIOS( 8, "103", "bootrom 1.03" ) \
245		ROM_LOAD( "eagle103.u15", 0x000000, 0x100000, CRC(c35f4cf2) SHA1(45301c18c7f8f78754c8ad60ea4d2da5a7dc55fb) ) \
	245	ROM_LOAD( "eagle103.u15", 0x000000, 0x100000, CRC(c35f4cf2) SHA1(45301c18c7f8f78754c8ad60ea4d2da5a7dc55fb) ) \
246	246	ROM_SYSTEM_BIOS( 9, "102", "bootrom 1.02" ) \
247	247	ROM_LOAD( "eagle102.u15", 0x000000, 0x100000, CRC(1fd39e73) SHA1(d1ac758f94defc5c55c62594b3999a406dd9ef1f) ) \
248	248	ROM_SYSTEM_BIOS( 10, "101", "bootrom 1.01" ) \
249		ROM_LOAD( "eagle101.u15", 0x000000, 0x100000, CRC(2600bc2b) SHA1(c4b89e69c51e4a3bb1874407c4d30b6caed4f396) ) \
	249	ROM_LOAD( "eagle101.u15", 0x000000, 0x100000, CRC(2600bc2b) SHA1(c4b89e69c51e4a3bb1874407c4d30b6caed4f396) ) \
250	250	ROM_REGION( 0x30000, "fpga", 0 ) \
251	251	ROM_LOAD( "17s20lpc_sb4.u26", 0x000000, 0x008000, CRC(62c4af8a) SHA1(6eca277b9c66a401990599e98fdca64a9e38cc9a) ) \
252	252	ROM_LOAD( "17s20lpc_sb5.u26", 0x008000, 0x008000, CRC(c88b9d42) SHA1(b912d0fc50ecdc6a198c626f6e1644e8405fac6e) ) \
253	253	ROM_LOAD( "17s50a_red1.u26", 0x010000, 0x020000, CRC(f5cf3187) SHA1(83b4a14de9959e5a776d97d424945d43501bda7f) ) \
254	254	ROM_REGION( 0x2000, "pals", 0 ) \
255	255	ROM_LOAD( "e2-card1.u22.jed", 0x000000, 0x000bd1, CRC(9d1e1ace) SHA1(287d6a30e9f32137ef4eba54f0effa092c97a6eb) ) \
256		ROM_LOAD( "e2-res3.u117.jed", 0x001000, 0x000bd1, CRC(4f1ff45a) SHA1(213cbdd6cd37ad9b5bfc9545084892a68d29f5ff) )
	256	ROM_LOAD( "e2-res3.u117.jed", 0x001000, 0x000bd1, CRC(4f1ff45a) SHA1(213cbdd6cd37ad9b5bfc9545084892a68d29f5ff) )
257	257
258	258	ROM_START( iteagle )
259		EAGLE_BIOS
	259	EAGLE_BIOS
260	260
261	261	DISK_REGION( "drive_0" )
262	262	ROM_END
263	263
264	264	ROM_START( gtfore04 )
265		EAGLE_BIOS
	265	EAGLE_BIOS
266	266
267	267	DISK_REGION( "drive_0" )
268	268	DISK_IMAGE( "gt2004", 0, SHA1(739a52d6ce13bb6ac7a543ee0e8086fb66be19b9) )
269	269	ROM_END
270	270
271	271	ROM_START( gtfore05 )
272		EAGLE_BIOS
	272	EAGLE_BIOS
273	273
274	274	DISK_REGION( "drive_0" )
275	275	DISK_IMAGE( "gt2005", 0, SHA1(d8de569d8cf97b5aaada10ce896eb3c75f1b37f1) )
r22615	r22616
288	288	GAME( 2000, iteagle, 0, gtfore, gtfore, iteagle_state, iteagle, ROT0, "Incredible Technologies", "Eagle BIOS", GAME_IS_BIOS_ROOT )
289	289	GAME( 2003, gtfore04, iteagle, gtfore, gtfore, iteagle_state, iteagle, ROT0, "Incredible Technologies", "Golden Tee Fore! 2004", GAME_NOT_WORKING \| GAME_NO_SOUND )
290	290	GAME( 2004, gtfore05, iteagle, gtfore, gtfore, iteagle_state, iteagle, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005", GAME_NOT_WORKING \| GAME_NO_SOUND )
291

trunk/src/mame/drivers/psikyo.c
r22615	r22616
1010	1010
1011	1011	void psikyo_state::machine_start()
1012	1012	{
1013
1014	1013	save_item(NAME(m_soundlatch));
1015	1014	save_item(NAME(m_z80_nmi));
1016	1015	save_item(NAME(m_mcu_status));

trunk/src/mame/drivers/taitojc.c
r22615	r22616
391	391	// lookup tables for densha de go analog controls/meters
392	392	static const int dendego_odometer_table[0x100] =
393	393	{
394		0, 3, 7, 10, 14, 17, 21, 24, 28, 31, 34, 38, 41, 45, 48, 52,
395		55, 59, 62, 66, 69, 72, 76, 79, 83, 86, 90, 93, 97, 100, 105, 111,
396		116, 121, 126, 132, 137, 142, 147, 153, 158, 163, 168, 174, 179, 184, 189, 195,
397		200, 206, 211, 217, 222, 228, 233, 239, 244, 250, 256, 261, 267, 272, 278, 283,
398		289, 294, 300, 306, 311, 317, 322, 328, 333, 339, 344, 350, 356, 361, 367, 372,
399		378, 383, 389, 394, 400, 406, 412, 418, 424, 429, 435, 441, 447, 453, 459, 465,
400		471, 476, 482, 488, 494, 500, 505, 511, 516, 521, 526, 532, 537, 542, 547, 553,
401		558, 563, 568, 574, 579, 584, 589, 595, 600, 607, 613, 620, 627, 633, 640, 647,
402		653, 660, 667, 673, 680, 687, 693, 700, 705, 711, 716, 721, 726, 732, 737, 742,
403		747, 753, 758, 763, 768, 774, 779, 784, 789, 795, 800, 806, 812, 818, 824, 829,
404		835, 841, 847, 853, 859, 865, 871, 876, 882, 888, 894, 900, 906, 911, 917, 922,
405		928, 933, 939, 944, 950, 956, 961, 967, 972, 978, 983, 989, 994, 1000, 1005, 1011,
	394	0, 3, 7, 10, 14, 17, 21, 24, 28, 31, 34, 38, 41, 45, 48, 52,
	395	55, 59, 62, 66, 69, 72, 76, 79, 83, 86, 90, 93, 97, 100, 105, 111,
	396	116, 121, 126, 132, 137, 142, 147, 153, 158, 163, 168, 174, 179, 184, 189, 195,
	397	200, 206, 211, 217, 222, 228, 233, 239, 244, 250, 256, 261, 267, 272, 278, 283,
	398	289, 294, 300, 306, 311, 317, 322, 328, 333, 339, 344, 350, 356, 361, 367, 372,
	399	378, 383, 389, 394, 400, 406, 412, 418, 424, 429, 435, 441, 447, 453, 459, 465,
	400	471, 476, 482, 488, 494, 500, 505, 511, 516, 521, 526, 532, 537, 542, 547, 553,
	401	558, 563, 568, 574, 579, 584, 589, 595, 600, 607, 613, 620, 627, 633, 640, 647,
	402	653, 660, 667, 673, 680, 687, 693, 700, 705, 711, 716, 721, 726, 732, 737, 742,
	403	747, 753, 758, 763, 768, 774, 779, 784, 789, 795, 800, 806, 812, 818, 824, 829,
	404	835, 841, 847, 853, 859, 865, 871, 876, 882, 888, 894, 900, 906, 911, 917, 922,
	405	928, 933, 939, 944, 950, 956, 961, 967, 972, 978, 983, 989, 994, 1000, 1005, 1011,
406	406	1016, 1021, 1026, 1032, 1037, 1042, 1047, 1053, 1058, 1063, 1068, 1074, 1079, 1084, 1089, 1095,
407	407	1100, 1107, 1113, 1120, 1127, 1133, 1140, 1147, 1153, 1160, 1167, 1173, 1180, 1187, 1193, 1200,
408	408	1203, 1206, 1209, 1212, 1216, 1219, 1222, 1225, 1228, 1231, 1234, 1238, 1241, 1244, 1247, 1250,
r22615	r22616
411	411
412	412	static const int dendego_pressure_table[0x100] =
413	413	{
414		0, 0, 0, 0, 5, 10, 14, 19, 24, 29, 33, 38, 43, 48, 52, 57,
415		62, 67, 71, 76, 81, 86, 90, 95, 100, 106, 112, 119, 125, 131, 138, 144,
416		150, 156, 162, 169, 175, 181, 188, 194, 200, 206, 212, 219, 225, 231, 238, 244,
417		250, 256, 262, 269, 275, 281, 288, 294, 300, 306, 312, 318, 324, 329, 335, 341,
418		347, 353, 359, 365, 371, 376, 382, 388, 394, 400, 407, 413, 420, 427, 433, 440,
419		447, 453, 460, 467, 473, 480, 487, 493, 500, 507, 514, 521, 529, 536, 543, 550,
420		557, 564, 571, 579, 586, 593, 600, 607, 614, 621, 629, 636, 643, 650, 657, 664,
421		671, 679, 686, 693, 700, 706, 712, 719, 725, 731, 738, 744, 750, 756, 762, 769,
422		775, 781, 788, 794, 800, 807, 814, 821, 829, 836, 843, 850, 857, 864, 871, 879,
423		886, 893, 900, 907, 914, 921, 929, 936, 943, 950, 957, 964, 971, 979, 986, 993,
	414	0, 0, 0, 0, 5, 10, 14, 19, 24, 29, 33, 38, 43, 48, 52, 57,
	415	62, 67, 71, 76, 81, 86, 90, 95, 100, 106, 112, 119, 125, 131, 138, 144,
	416	150, 156, 162, 169, 175, 181, 188, 194, 200, 206, 212, 219, 225, 231, 238, 244,
	417	250, 256, 262, 269, 275, 281, 288, 294, 300, 306, 312, 318, 324, 329, 335, 341,
	418	347, 353, 359, 365, 371, 376, 382, 388, 394, 400, 407, 413, 420, 427, 433, 440,
	419	447, 453, 460, 467, 473, 480, 487, 493, 500, 507, 514, 521, 529, 536, 543, 550,
	420	557, 564, 571, 579, 586, 593, 600, 607, 614, 621, 629, 636, 643, 650, 657, 664,
	421	671, 679, 686, 693, 700, 706, 712, 719, 725, 731, 738, 744, 750, 756, 762, 769,
	422	775, 781, 788, 794, 800, 807, 814, 821, 829, 836, 843, 850, 857, 864, 871, 879,
	423	886, 893, 900, 907, 914, 921, 929, 936, 943, 950, 957, 964, 971, 979, 986, 993,
424	424	1000, 1008, 1015, 1023, 1031, 1038, 1046, 1054, 1062, 1069, 1077, 1085, 1092, 1100, 1108, 1115,
425	425	1123, 1131, 1138, 1146, 1154, 1162, 1169, 1177, 1185, 1192, 1200, 1207, 1214, 1221, 1229, 1236,
426	426	1243, 1250, 1257, 1264, 1271, 1279, 1286, 1293, 1300, 1307, 1314, 1321, 1329, 1336, 1343, 1350,

trunk/src/mame/drivers/kas89.c
r22615	r22616
263	263
264	264	void kas89_state::machine_start()
265	265	{
266
267	266	output_set_lamp_value(37, 0); /* turning off the operator led */
268	267	}
269	268

trunk/src/mame/drivers/mrflea.c
r22615	r22616
327	327
328	328	void mrflea_state::machine_start()
329	329	{
330
331	330	save_item(NAME(m_gfx_bank));
332	331	save_item(NAME(m_io));
333	332	save_item(NAME(m_main));

trunk/src/mame/drivers/boxer.c
r22615	r22616
428	428
429	429	void boxer_state::machine_start()
430	430	{
431
432	431	save_item(NAME(m_pot_state));
433	432	save_item(NAME(m_pot_latch));
434	433	}

trunk/src/mame/drivers/seattle.c
r22615	r22616
482	482	DECLARE_READ32_MEMBER(seattle_ide_r);
483	483	DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
484	484	DECLARE_WRITE_LINE_MEMBER(vblank_assert);
485		DECLARE_WRITE_LINE_MEMBER(voodoo_stall);
	485	DECLARE_WRITE_LINE_MEMBER(voodoo_stall);
486	486	DECLARE_DRIVER_INIT(sfrush);
487	487	DECLARE_DRIVER_INIT(blitz2k);
488	488	DECLARE_DRIVER_INIT(carnevil);

trunk/src/mame/drivers/flyball.c
r22615	r22616
375	375
376	376	void flyball_state::machine_start()
377	377	{
378
379	378	save_item(NAME(m_pitcher_vert));
380	379	save_item(NAME(m_pitcher_horz));
381	380	save_item(NAME(m_pitcher_pic));

trunk/src/mame/drivers/opwolf.c
r22615	r22616
478	478	}
479	479
480	480	WRITE8_MEMBER(opwolf_state::opwolf_adpcm_b_w)
481		{
	481	{
482	482	int start;
483	483	int end;
484	484

trunk/src/mame/drivers/suna16.c
r22615	r22616
446	446	JOY(4)
447	447
448	448	PORT_START("DSW1") /* $a00008.w */
449		PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2,3")
	449	PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2,3")
450	450	PORT_DIPSETTING( 0x0000, DEF_STR( 4C_1C ) )
451	451	PORT_DIPSETTING( 0x0001, DEF_STR( 3C_1C ) )
452	452	PORT_DIPSETTING( 0x0002, DEF_STR( 2C_1C ) )
r22615	r22616
455	455	PORT_DIPSETTING( 0x0005, DEF_STR( 1C_3C ) )
456	456	PORT_DIPSETTING( 0x0004, DEF_STR( 1C_4C ) )
457	457	PORT_DIPSETTING( 0x0003, DEF_STR( 1C_5C ) )
458		PORT_DIPNAME( 0x0018, 0x0018, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW1:4,5")
	458	PORT_DIPNAME( 0x0018, 0x0018, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW1:4,5")
459	459	PORT_DIPSETTING( 0x0010, DEF_STR( Easy ) )
460	460	PORT_DIPSETTING( 0x0018, DEF_STR( Normal ) )
461	461	PORT_DIPSETTING( 0x0008, DEF_STR( Hard ) )
462	462	PORT_DIPSETTING( 0x0000, "Hardest?" ) // duplicate of "HARD" not shown as supported in manual - but possible to set on PCB
463		PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:6")
	463	PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:6")
464	464	PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
465	465	PORT_DIPSETTING( 0x0020, DEF_STR( On ) )
466		PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:7")
	466	PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:7")
467	467	PORT_DIPSETTING( 0x0040, DEF_STR( Off ) )
468	468	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
469	469	PORT_SERVICE_DIPLOC( 0x0080, IP_ACTIVE_LOW, "SW1:8" )
470	470
471		PORT_DIPNAME( 0x0300, 0x0300, "Play Time P1" ) PORT_DIPLOCATION("SW2:1,2")
	471	PORT_DIPNAME( 0x0300, 0x0300, "Play Time P1" ) PORT_DIPLOCATION("SW2:1,2")
472	472	PORT_DIPSETTING( 0x0300, "1:30" )
473	473	PORT_DIPSETTING( 0x0200, "1:45" )
474	474	PORT_DIPSETTING( 0x0100, "2:00" )
475	475	PORT_DIPSETTING( 0x0000, "2:15" )
476		PORT_DIPNAME( 0x0c00, 0x0c00, "Play Time P2" ) PORT_DIPLOCATION("SW2:3,4")
	476	PORT_DIPNAME( 0x0c00, 0x0c00, "Play Time P2" ) PORT_DIPLOCATION("SW2:3,4")
477	477	PORT_DIPSETTING( 0x0c00, "1:30" )
478	478	PORT_DIPSETTING( 0x0800, "1:45" )
479	479	PORT_DIPSETTING( 0x0400, "2:00" )
480	480	PORT_DIPSETTING( 0x0000, "2:15" )
481		PORT_DIPNAME( 0x3000, 0x3000, "Play Time P3" ) PORT_DIPLOCATION("SW2:5,6")
	481	PORT_DIPNAME( 0x3000, 0x3000, "Play Time P3" ) PORT_DIPLOCATION("SW2:5,6")
482	482	PORT_DIPSETTING( 0x3000, "1:30" )
483	483	PORT_DIPSETTING( 0x2000, "1:45" )
484	484	PORT_DIPSETTING( 0x1000, "2:00" )
485	485	PORT_DIPSETTING( 0x0000, "2:15" )
486		PORT_DIPNAME( 0xc000, 0xc000, "Play Time P4" ) PORT_DIPLOCATION("SW2:7,8")
	486	PORT_DIPNAME( 0xc000, 0xc000, "Play Time P4" ) PORT_DIPLOCATION("SW2:7,8")
487	487	PORT_DIPSETTING( 0xc000, "1:30" )
488	488	PORT_DIPSETTING( 0x8000, "1:45" )
489	489	PORT_DIPSETTING( 0x4000, "2:00" )
490	490	PORT_DIPSETTING( 0x0000, "2:15" )
491	491
492	492	PORT_START("DSW2") /* $a0000b.b - JP3, JP6 & JP7 and what else?? */
493		PORT_DIPNAME( 0x0001, 0x0001, "Copyright" ) PORT_DIPLOCATION("Jumper:1") // these 4 are shown in test mode
	493	PORT_DIPNAME( 0x0001, 0x0001, "Copyright" ) PORT_DIPLOCATION("Jumper:1") // these 4 are shown in test mode
494	494	PORT_DIPSETTING( 0x0001, "Distributer Unico" )
495	495	PORT_DIPSETTING( 0x0000, "All Rights Reserved" )
496		PORT_DIPNAME( 0x0002, 0x0002, DEF_STR( Unknown ) ) PORT_DIPLOCATION("Jumper:2") // used!
	496	PORT_DIPNAME( 0x0002, 0x0002, DEF_STR( Unknown ) ) PORT_DIPLOCATION("Jumper:2") // used!
497	497	PORT_DIPSETTING( 0x0002, DEF_STR( Off ) )
498	498	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
499		PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) ) PORT_DIPLOCATION("Jumper:3")
	499	PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) ) PORT_DIPLOCATION("Jumper:3")
500	500	PORT_DIPSETTING( 0x0004, DEF_STR( Off ) )
501	501	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
502		PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) ) PORT_DIPLOCATION("Jumper:4")
	502	PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) ) PORT_DIPLOCATION("Jumper:4")
503	503	PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
504	504	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
505	505	PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_COIN1 )
r22615	r22616
554	554	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_COIN2 )
555	555
556	556	PORT_START("DSW1") /* $600005.b */
557		PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2,3")
	557	PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2,3")
558	558	PORT_DIPSETTING( 0x0000, DEF_STR( 5C_1C ) )
559	559	PORT_DIPSETTING( 0x0001, DEF_STR( 4C_1C ) )
560	560	PORT_DIPSETTING( 0x0002, DEF_STR( 3C_1C ) )
r22615	r22616
563	563	PORT_DIPSETTING( 0x0006, DEF_STR( 1C_2C ) )
564	564	PORT_DIPSETTING( 0x0005, DEF_STR( 1C_3C ) )
565	565	PORT_DIPSETTING( 0x0004, DEF_STR( 1C_4C ) )
566		PORT_DIPNAME( 0x0018, 0x0018, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW1:4,5")
	566	PORT_DIPNAME( 0x0018, 0x0018, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW1:4,5")
567	567	PORT_DIPSETTING( 0x0010, "2" )
568	568	PORT_DIPSETTING( 0x0018, "3" )
569	569	PORT_DIPSETTING( 0x0008, "4" )
570	570	PORT_DIPSETTING( 0x0000, "5" )
571		PORT_DIPNAME( 0x0060, 0x0060, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW1:6,7")
	571	PORT_DIPNAME( 0x0060, 0x0060, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW1:6,7")
572	572	PORT_DIPSETTING( 0x0040, DEF_STR( Easy ) )
573	573	PORT_DIPSETTING( 0x0060, DEF_STR( Normal ) )
574	574	PORT_DIPSETTING( 0x0020, DEF_STR( Hard ) )
r22615	r22616
576	576	PORT_SERVICE_DIPLOC( 0x0080, IP_ACTIVE_LOW, "SW1:8" )
577	577
578	578	PORT_START("DSW2") /* $600007.b */
579		PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW2:1")
	579	PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW2:1")
580	580	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
581	581	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
582		PORT_DIPNAME( 0x0002, 0x0002, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SW2:2")
	582	PORT_DIPNAME( 0x0002, 0x0002, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SW2:2")
583	583	PORT_DIPSETTING( 0x0002, DEF_STR( Upright ) )
584	584	PORT_DIPSETTING( 0x0000, DEF_STR( Cocktail ) )
585		PORT_DIPNAME( 0x001c, 0x001c, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:3,4,5")
	585	PORT_DIPNAME( 0x001c, 0x001c, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:3,4,5")
586	586	PORT_DIPSETTING( 0x001c, "200K" )
587	587	PORT_DIPSETTING( 0x0010, "300K, 1000K" )
588	588	PORT_DIPSETTING( 0x0018, "400K" )
r22615	r22616
591	591	PORT_DIPSETTING( 0x0004, "500K, 3000K" )
592	592	PORT_DIPSETTING( 0x0014, "600K" )
593	593	PORT_DIPSETTING( 0x0000, DEF_STR( None ) )
594		PORT_DIPNAME( 0x0020, 0x0020, "Unknown DSW2-6*" ) PORT_DIPLOCATION("SW2:6")
	594	PORT_DIPNAME( 0x0020, 0x0020, "Unknown DSW2-6*" ) PORT_DIPLOCATION("SW2:6")
595	595	PORT_DIPSETTING( 0x0020, DEF_STR( Off ) )
596	596	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
597		PORT_DIPNAME( 0x0040, 0x0040, "Unknown DSW2-7*" ) PORT_DIPLOCATION("SW2:7")
	597	PORT_DIPNAME( 0x0040, 0x0040, "Unknown DSW2-7*" ) PORT_DIPLOCATION("SW2:7")
598	598	PORT_DIPSETTING( 0x0040, DEF_STR( Off ) )
599	599	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
600		PORT_DIPNAME( 0x0080, 0x0000, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:8")
	600	PORT_DIPNAME( 0x0080, 0x0000, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:8")
601	601	PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
602	602	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
603	603	INPUT_PORTS_END
r22615	r22616
698	698	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_COIN2 )
699	699
700	700	PORT_START("DSW") /* 500004.w */
701		PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SWA:1,2,3")
	701	PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SWA:1,2,3")
702	702	PORT_DIPSETTING( 0x0000, DEF_STR( 5C_1C ) )
703	703	PORT_DIPSETTING( 0x0001, DEF_STR( 4C_1C ) )
704	704	PORT_DIPSETTING( 0x0002, DEF_STR( 3C_1C ) )
r22615	r22616
707	707	PORT_DIPSETTING( 0x0006, DEF_STR( 1C_2C ) )
708	708	PORT_DIPSETTING( 0x0005, DEF_STR( 1C_3C ) )
709	709	PORT_DIPSETTING( 0x0004, DEF_STR( 1C_4C ) )
710		PORT_DIPNAME( 0x0018, 0x0010, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SWA:4,5")
	710	PORT_DIPNAME( 0x0018, 0x0010, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SWA:4,5")
711	711	PORT_DIPSETTING( 0x0018, DEF_STR( Easy ) )
712	712	PORT_DIPSETTING( 0x0010, DEF_STR( Normal ) )
713	713	PORT_DIPSETTING( 0x0008, DEF_STR( Hard ) )
714	714	PORT_DIPSETTING( 0x0000, DEF_STR( Hardest ) )
715		PORT_DIPNAME( 0x0020, 0x0020, "Display Combos" ) PORT_DIPLOCATION("SWA:6")
	715	PORT_DIPNAME( 0x0020, 0x0020, "Display Combos" ) PORT_DIPLOCATION("SWA:6")
716	716	PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
717	717	PORT_DIPSETTING( 0x0020, DEF_STR( On ) )
718	718	PORT_SERVICE_DIPLOC( 0x0040, IP_ACTIVE_LOW, "SWA:7" )
719		PORT_DIPNAME( 0x0080, 0x0000, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SWA:8")
	719	PORT_DIPNAME( 0x0080, 0x0000, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SWA:8")
720	720	PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
721	721	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
722	722
723		PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SWB:1")
	723	PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SWB:1")
724	724	PORT_DIPSETTING( 0x0100, DEF_STR( Off ) )
725	725	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
726		PORT_DIPNAME( 0x0600, 0x0400, "Play Time" ) PORT_DIPLOCATION("SWB:2,3")
	726	PORT_DIPNAME( 0x0600, 0x0400, "Play Time" ) PORT_DIPLOCATION("SWB:2,3")
727	727	PORT_DIPSETTING( 0x0600, "1:10" )
728	728	PORT_DIPSETTING( 0x0400, "1:20" )
729	729	PORT_DIPSETTING( 0x0200, "1:30" )
r22615	r22616
853	853	static MACHINE_CONFIG_START( uballoon, suna16_state )
854	854
855	855	/* basic machine hardware */
856		MCFG_CPU_ADD("maincpu", M68000, XTAL_32MHz/4) /* 8MHz */
	856	MCFG_CPU_ADD("maincpu", M68000, XTAL_32MHz/4) /* 8MHz */
857	857	MCFG_CPU_PROGRAM_MAP(uballoon_map)
858	858	MCFG_CPU_VBLANK_INT_DRIVER("screen", suna16_state, irq1_line_hold)
859	859
860		MCFG_CPU_ADD("audiocpu", Z80, XTAL_14_31818MHz/4) /* Z80B at 3.579545MHz */
	860	MCFG_CPU_ADD("audiocpu", Z80, XTAL_14_31818MHz/4) /* Z80B at 3.579545MHz */
861	861	MCFG_CPU_PROGRAM_MAP(uballoon_sound_map)
862	862
863		MCFG_CPU_ADD("pcm1", Z80, XTAL_32MHz/6) /* Z80B at 5MHz */
	863	MCFG_CPU_ADD("pcm1", Z80, XTAL_32MHz/6) /* Z80B at 5MHz */
864	864	MCFG_CPU_PROGRAM_MAP(uballoon_pcm_1_map)
865	865	MCFG_CPU_IO_MAP(uballoon_pcm_1_io_map)
866	866
r22615	r22616
885	885	/* sound hardware */
886	886	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
887	887
888		MCFG_YM2151_ADD("ymsnd", XTAL_14_31818MHz/4) /* 3.579545MHz */
	888	MCFG_YM2151_ADD("ymsnd", XTAL_14_31818MHz/4) /* 3.579545MHz */
889	889	MCFG_SOUND_ROUTE(0, "lspeaker", 0.50)
890	890	MCFG_SOUND_ROUTE(1, "rspeaker", 0.50)
891	891
r22615	r22616
903	903	static MACHINE_CONFIG_START( sunaq, suna16_state )
904	904
905	905	/* basic machine hardware */
906		MCFG_CPU_ADD("maincpu", M68000, XTAL_24MHz/4) /* 6MHz */
	906	MCFG_CPU_ADD("maincpu", M68000, XTAL_24MHz/4) /* 6MHz */
907	907	MCFG_CPU_PROGRAM_MAP(sunaq_map)
908	908	MCFG_CPU_VBLANK_INT_DRIVER("screen", suna16_state, irq1_line_hold)
909	909
910		MCFG_CPU_ADD("audiocpu", Z80, XTAL_14_31818MHz/4) /* Z80B at 3.579545MHz */
	910	MCFG_CPU_ADD("audiocpu", Z80, XTAL_14_31818MHz/4) /* Z80B at 3.579545MHz */
911	911	MCFG_CPU_PROGRAM_MAP(sunaq_sound_map)
912	912
913		MCFG_CPU_ADD("pcm1", Z80, XTAL_24MHz/4) /* Z80B at 6MHz */
	913	MCFG_CPU_ADD("pcm1", Z80, XTAL_24MHz/4) /* Z80B at 6MHz */
914	914	MCFG_CPU_PROGRAM_MAP(bssoccer_pcm_1_map)
915	915	MCFG_CPU_IO_MAP(bssoccer_pcm_1_io_map)
916	916
r22615	r22616
933	933	/* sound hardware */
934	934	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
935	935
936		MCFG_YM2151_ADD("ymsnd", XTAL_14_31818MHz/4) /* 3.579545MHz */
	936	MCFG_YM2151_ADD("ymsnd", XTAL_14_31818MHz/4) /* 3.579545MHz */
937	937	MCFG_SOUND_ROUTE(0, "lspeaker", 0.50)
938	938	MCFG_SOUND_ROUTE(1, "rspeaker", 0.50)
939	939
r22615	r22616
969	969	static MACHINE_CONFIG_START( bestbest, suna16_state )
970	970
971	971	/* basic machine hardware */
972		MCFG_CPU_ADD("maincpu", M68000, XTAL_24MHz/4) /* 6MHz */
	972	MCFG_CPU_ADD("maincpu", M68000, XTAL_24MHz/4) /* 6MHz */
973	973	MCFG_CPU_PROGRAM_MAP(bestbest_map)
974	974	MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", suna16_state, bssoccer_interrupt, "screen", 0, 1)
975	975
976		MCFG_CPU_ADD("audiocpu", Z80, XTAL_24MHz/4) /* 6MHz */
	976	MCFG_CPU_ADD("audiocpu", Z80, XTAL_24MHz/4) /* 6MHz */
977	977	MCFG_CPU_PROGRAM_MAP(bestbest_sound_map)
978	978
979		MCFG_CPU_ADD("pcm1", Z80, XTAL_24MHz/4) /* 6MHz */
	979	MCFG_CPU_ADD("pcm1", Z80, XTAL_24MHz/4) /* 6MHz */
980	980	MCFG_CPU_PROGRAM_MAP(bestbest_pcm_1_map)
981	981	MCFG_CPU_IO_MAP(bestbest_pcm_1_iomap)
982	982
r22615	r22616
999	999	/* sound hardware */
1000	1000	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
1001	1001
1002		MCFG_SOUND_ADD("aysnd", AY8910, XTAL_24MHz/16) /* 1.5MHz */
	1002	MCFG_SOUND_ADD("aysnd", AY8910, XTAL_24MHz/16) /* 1.5MHz */
1003	1003	MCFG_SOUND_CONFIG(bestbest_ay8910_interface)
1004	1004	MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
1005	1005	MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
1006	1006
1007		MCFG_SOUND_ADD("ymsnd", YM3526, XTAL_24MHz/8) /* 3MHz */
	1007	MCFG_SOUND_ADD("ymsnd", YM3526, XTAL_24MHz/8) /* 3MHz */
1008	1008	MCFG_SOUND_CONFIG(bestbest_ym3526_interface)
1009	1009	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
1010	1010	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)

trunk/src/mame/drivers/hikaru.c
r22615	r22616
665	665	ROM_LOAD32_WORD( "epr-21994.ic29", 0x000000, 0x200000, CRC(31b0a754) SHA1(b49c998a15fbc790b780ed6665a56681d4edd369) )
666	666	ROM_LOAD32_WORD( "epr-21995.ic30", 0x000002, 0x200000, CRC(bcccb56b) SHA1(6e7a69934e5b47495ae8e90c57759573bc519d24) )
667	667	ROM_LOAD32_WORD( "epr-21996.ic31", 0x400000, 0x200000, CRC(a8f88e17) SHA1(dbbd2a73335c740bcf2ff9680c575841af29b340) )
668		ROM_LOAD32_WORD( "epr-21997.ic32", 0x400002, 0x200000, CRC(36641a7f) SHA1(37931bde1ddebef61fa6d8caca3cb67328fd0b90) )
	668	ROM_LOAD32_WORD( "epr-21997.ic32", 0x400002, 0x200000, CRC(36641a7f) SHA1(37931bde1ddebef61fa6d8caca3cb67328fd0b90) )
669	669	ROM_LOAD32_WORD( "epr-21998.ic33", 0x800000, 0x200000, CRC(bd1df696) SHA1(fd937894763fab5cb50f33c40f8047e0d3adc93b) )
670	670	ROM_LOAD32_WORD( "epr-21999.ic34", 0x800002, 0x200000, CRC(9425eee0) SHA1(0f6a23163022bbd7ec54dd638094f3e317a87919) )
671	671	/* ic35 unpopulated */
r22615	r22616
673	673
674	674	/* ROM board using 64M SOP44 MASKROM */
675	675	ROM_REGION( 0xc000000, "user2", ROMREGION_ERASE00)
676		ROM_LOAD( "mpr-22000.ic37", 0x0000000, 0x800000, CRC(53d641d6) SHA1(f47d7c77d0e36c4ec3b7171fd7a017f9f58ca5a0) )
677		ROM_LOAD( "mpr-22001.ic38", 0x0800000, 0x800000, CRC(234bc48f) SHA1(177c46884de0ba4bac1f9b778f99c905410a9345) )
678		ROM_LOAD( "mpr-22002.ic39", 0x1000000, 0x800000, CRC(d8f3aa9e) SHA1(f73208034fdd51fed086e912cb8580d2270122b6) )
679		ROM_LOAD( "mpr-22003.ic40", 0x1800000, 0x800000, CRC(2560fe98) SHA1(9bb5ffb6212ec6aa3f92e437eb424141f3b15e43) )
680		ROM_LOAD( "mpr-22004.ic41", 0x2000000, 0x800000, CRC(4e24d71d) SHA1(503344dd8cdd8e65ec7c801b0efae83b3f1f9ae2) )
681		ROM_LOAD( "mpr-22005.ic42", 0x2800000, 0x800000, CRC(2b96c97f) SHA1(707070c85f4b044236694daa13970c241b242d4d) )
682		ROM_LOAD( "mpr-22006.ic43", 0x3000000, 0x800000, CRC(f793a3ba) SHA1(80acd1d4f71cafd7328ff9b9ce30e5169b8f4f8c) )
683		ROM_LOAD( "mpr-22007.ic44", 0x3800000, 0x800000, CRC(62616e31) SHA1(dbe0d4b8fc085ed97884c105fd527af5cd8fbe79) )
684		ROM_LOAD( "mpr-22008.ic45", 0x4000000, 0x800000, CRC(e6905de8) SHA1(6bb4e43b1394788add15f0b78ccd5ab14f86516c) )
685		ROM_LOAD( "mpr-22009.ic46", 0x4800000, 0x800000, CRC(c37dfa5c) SHA1(5a3a5f2eb5a13831e36ca215147ec3c9740c50fc) )
686		ROM_LOAD( "mpr-22010.ic47", 0x5000000, 0x800000, CRC(b570b46c) SHA1(6e512fd1a2c8835f6aee307865b42d57ddf90ef5) )
687		ROM_LOAD( "mpr-22011.ic48", 0x5800000, 0x800000, CRC(d1f5fb58) SHA1(08a1282e00bda52d8d938225c65f67d22abfea05) )
688		ROM_LOAD( "mpr-22012.ic49", 0x6000000, 0x800000, CRC(3ab79029) SHA1(d4708446ba700d5f7c89827c80177ad2d1c0b222) )
689		ROM_LOAD( "mpr-22013.ic50", 0x6800000, 0x800000, CRC(42d8d00b) SHA1(ddce3c95258d8cf51792f2115f89ca658ffe97b6) )
690		ROM_LOAD( "mpr-22014.ic51", 0x7000000, 0x800000, CRC(0f49c00f) SHA1(877c654268edc9526ae3e21e21e3ecca706f300b) )
691		ROM_LOAD( "mpr-22015.ic52", 0x7800000, 0x800000, CRC(d3696e61) SHA1(247161c99c7061b8f391543af1812764a82399cb) )
692		ROM_LOAD( "mpr-22016.ic53s", 0x8000000, 0x800000, CRC(c1015e00) SHA1(f2ce2009d4f4f0f3cbfcce7a36fab2c54e738b07) )
693		ROM_LOAD( "mpr-22017.ic54s", 0x8800000, 0x800000, CRC(222a7cb0) SHA1(9f98ae3f13f85fae4596b671ea508b07c2116ab6) )
694		ROM_LOAD( "mpr-22018.ic55s", 0x9000000, 0x800000, CRC(f160e115) SHA1(ecf7f9f58fce6bff220568972ba7763537c9d7d7) )
695		ROM_LOAD( "mpr-22019.ic56s", 0x9800000, 0x800000, CRC(468b2f10) SHA1(f3fc0af7d4dd3f30ba84e684f3d9c217730564bb) )
696		ROM_LOAD( "mpr-22020.ic57s", 0xa000000, 0x800000, CRC(0c018d8a) SHA1(0447d7ad64061cca4c1231733e660ba51de5a216) )
697		ROM_LOAD( "mpr-22021.ic58s", 0xa800000, 0x800000, CRC(43b08604) SHA1(681142d8b95b2f9664d70b23262a64938774d4e3) )
698		ROM_LOAD( "mpr-22022.ic59s", 0xb000000, 0x800000, CRC(abd3d888) SHA1(9654c3a38feab46b4983a602831fb29cccdd0526) )
699		ROM_LOAD( "mpr-22023.ic60s", 0xb800000, 0x800000, CRC(07f00869) SHA1(92282d09d72d3e65a91128e06bb0d4426bb90be5) )
	676	ROM_LOAD( "mpr-22000.ic37", 0x0000000, 0x800000, CRC(53d641d6) SHA1(f47d7c77d0e36c4ec3b7171fd7a017f9f58ca5a0) )
	677	ROM_LOAD( "mpr-22001.ic38", 0x0800000, 0x800000, CRC(234bc48f) SHA1(177c46884de0ba4bac1f9b778f99c905410a9345) )
	678	ROM_LOAD( "mpr-22002.ic39", 0x1000000, 0x800000, CRC(d8f3aa9e) SHA1(f73208034fdd51fed086e912cb8580d2270122b6) )
	679	ROM_LOAD( "mpr-22003.ic40", 0x1800000, 0x800000, CRC(2560fe98) SHA1(9bb5ffb6212ec6aa3f92e437eb424141f3b15e43) )
	680	ROM_LOAD( "mpr-22004.ic41", 0x2000000, 0x800000, CRC(4e24d71d) SHA1(503344dd8cdd8e65ec7c801b0efae83b3f1f9ae2) )
	681	ROM_LOAD( "mpr-22005.ic42", 0x2800000, 0x800000, CRC(2b96c97f) SHA1(707070c85f4b044236694daa13970c241b242d4d) )
	682	ROM_LOAD( "mpr-22006.ic43", 0x3000000, 0x800000, CRC(f793a3ba) SHA1(80acd1d4f71cafd7328ff9b9ce30e5169b8f4f8c) )
	683	ROM_LOAD( "mpr-22007.ic44", 0x3800000, 0x800000, CRC(62616e31) SHA1(dbe0d4b8fc085ed97884c105fd527af5cd8fbe79) )
	684	ROM_LOAD( "mpr-22008.ic45", 0x4000000, 0x800000, CRC(e6905de8) SHA1(6bb4e43b1394788add15f0b78ccd5ab14f86516c) )
	685	ROM_LOAD( "mpr-22009.ic46", 0x4800000, 0x800000, CRC(c37dfa5c) SHA1(5a3a5f2eb5a13831e36ca215147ec3c9740c50fc) )
	686	ROM_LOAD( "mpr-22010.ic47", 0x5000000, 0x800000, CRC(b570b46c) SHA1(6e512fd1a2c8835f6aee307865b42d57ddf90ef5) )
	687	ROM_LOAD( "mpr-22011.ic48", 0x5800000, 0x800000, CRC(d1f5fb58) SHA1(08a1282e00bda52d8d938225c65f67d22abfea05) )
	688	ROM_LOAD( "mpr-22012.ic49", 0x6000000, 0x800000, CRC(3ab79029) SHA1(d4708446ba700d5f7c89827c80177ad2d1c0b222) )
	689	ROM_LOAD( "mpr-22013.ic50", 0x6800000, 0x800000, CRC(42d8d00b) SHA1(ddce3c95258d8cf51792f2115f89ca658ffe97b6) )
	690	ROM_LOAD( "mpr-22014.ic51", 0x7000000, 0x800000, CRC(0f49c00f) SHA1(877c654268edc9526ae3e21e21e3ecca706f300b) )
	691	ROM_LOAD( "mpr-22015.ic52", 0x7800000, 0x800000, CRC(d3696e61) SHA1(247161c99c7061b8f391543af1812764a82399cb) )
	692	ROM_LOAD( "mpr-22016.ic53s", 0x8000000, 0x800000, CRC(c1015e00) SHA1(f2ce2009d4f4f0f3cbfcce7a36fab2c54e738b07) )
	693	ROM_LOAD( "mpr-22017.ic54s", 0x8800000, 0x800000, CRC(222a7cb0) SHA1(9f98ae3f13f85fae4596b671ea508b07c2116ab6) )
	694	ROM_LOAD( "mpr-22018.ic55s", 0x9000000, 0x800000, CRC(f160e115) SHA1(ecf7f9f58fce6bff220568972ba7763537c9d7d7) )
	695	ROM_LOAD( "mpr-22019.ic56s", 0x9800000, 0x800000, CRC(468b2f10) SHA1(f3fc0af7d4dd3f30ba84e684f3d9c217730564bb) )
	696	ROM_LOAD( "mpr-22020.ic57s", 0xa000000, 0x800000, CRC(0c018d8a) SHA1(0447d7ad64061cca4c1231733e660ba51de5a216) )
	697	ROM_LOAD( "mpr-22021.ic58s", 0xa800000, 0x800000, CRC(43b08604) SHA1(681142d8b95b2f9664d70b23262a64938774d4e3) )
	698	ROM_LOAD( "mpr-22022.ic59s", 0xb000000, 0x800000, CRC(abd3d888) SHA1(9654c3a38feab46b4983a602831fb29cccdd0526) )
	699	ROM_LOAD( "mpr-22023.ic60s", 0xb800000, 0x800000, CRC(07f00869) SHA1(92282d09d72d3e65a91128e06bb0d4426bb90be5) )
700	700	ROM_END
701	701
702	702	ROM_START( sgnascar )

trunk/src/mame/drivers/redclash.c
r22615	r22616
325	325
326	326	MACHINE_START_MEMBER(ladybug_state,redclash)
327	327	{
328
329	328	save_item(NAME(m_star_speed));
330	329	save_item(NAME(m_gfxbank));
331	330	save_item(NAME(m_stars_enable));

trunk/src/mame/drivers/1942.c
r22615	r22616
238	238
239	239	void _1942_state::machine_start()
240	240	{
241
242	241	save_item(NAME(m_palette_bank));
243	242	save_item(NAME(m_scroll));
244	243	}

trunk/src/mame/drivers/naomi.c
r22615	r22616
6751	6751	DISK_REGION( "gdrom" )
6752	6752	DISK_IMAGE_READONLY( "gds-0013", 0, SHA1(47372ae3bd5ada0981e549f9b4d974f0112ce4c8) )
6753	6753
6754		ROM_REGION( 0x4000, "pic", ROMREGION_ERASEFF) // 317-0315-COM
	6754	ROM_REGION( 0x4000, "pic", ROMREGION_ERASEFF) // 317-0315-COM
6755	6755	ROM_LOAD( "317-0315-com.pic", 0x000000, 0x004000, CRC(c225b08b) SHA1(37ac664524a9e4e37cc9af1e509759295f659e0d) )
6756	6756	ROM_END
6757	6757
r22615	r22616
8207	8207	// 0012A Virtua Fighter 4 (Rev A)
8208	8208	/* 0012B */ GAME( 2001, vf4b, vf4, naomi2gd, naomi, naomi_state, naomi2, ROT0, "Sega", "Virtua Fighter 4 (Rev B) (GDS-0012B)", GAME_FLAGS )
8209	8209	/* 0012C */ GAME( 2001, vf4c, vf4, naomi2gd, naomi, naomi_state, naomi2, ROT0, "Sega", "Virtua Fighter 4 (Rev C) (GDS-0012C)", GAME_FLAGS )
8210		/* 0013 */ GAME( 2001, shaktmsp, naomigd, naomigd, shaktamb, naomi_state, naomigd, ROT0, "Sega", "Shakatto Tambourine 2K1 SPR (GDS-0013)", GAME_FLAGS )
	8210	/* 0013 */ GAME( 2001, shaktmsp, naomigd, naomigd, shaktamb, naomi_state, naomigd, ROT0, "Sega", "Shakatto Tambourine 2K1 SPR (GDS-0013)", GAME_FLAGS )
8211	8211	/* 0014 */ GAME( 2001, beachspi, naomi2, naomi2gd, naomi, naomi_state, naomi2, ROT0, "Sega", "Beach Spikers (GDS-0014)", GAME_FLAGS )
8212	8212	// 0015 Virtua Tennis 2 / Power Smash 2
8213	8213	/* 0015A */ GAME( 2001, vtennis2, naomigd, naomigd, naomi, naomi_state, naomigd, ROT0, "Sega", "Virtua Tennis 2 / Power Smash 2 (Rev A) (GDS-0015A)", GAME_FLAGS )

trunk/src/mame/drivers/queen.c
r22615	r22616
538	538
539	539	/* video hardware */
540	540	MCFG_FRAGMENT_ADD( pcvideo_vga )
541
	541
542	542	MCFG_KBDC8042_ADD("kbdc", at8042)
543	543	MACHINE_CONFIG_END
544	544

trunk/src/mame/drivers/aquarium.c
r22615	r22616
287	287
288	288	void aquarium_state::machine_start()
289	289	{
290
291	290	save_item(NAME(m_aquarium_snd_ack));
292	291	}
293	292

trunk/src/mame/drivers/angelkds.c
r22615	r22616
569	569
570	570	void angelkds_state::machine_start()
571	571	{
572
573	572	save_item(NAME(m_layer_ctrl));
574	573	save_item(NAME(m_txbank));
575	574	save_item(NAME(m_bgbotbank));

trunk/src/mame/drivers/nightgal.c
r22615	r22616
876	876
877	877	void nightgal_state::machine_start()
878	878	{
879
880	879	save_item(NAME(m_nsc_latch));
881	880	save_item(NAME(m_z80_latch));
882	881	save_item(NAME(m_mux_data));

trunk/src/mame/drivers/ghosteo.c
r22615	r22616
86	86	m_system_memory(*this, "systememory"),
87	87	m_i2cmem(*this, "i2cmem"),
88	88	m_s3c2410(*this, "s3c2410"),
89		m_maincpu(*this, "maincpu") { }
	89	m_maincpu(*this, "maincpu") { }
90	90
91	91	required_shared_ptr<UINT32> m_system_memory;
92	92	required_device<i2cmem_device> m_i2cmem;
r22615	r22616
599	599
600	600	void ghosteo_state::machine_reset()
601	601	{
602		m_maincpu->space(AS_PROGRAM).install_read_handler(0x4d000010, 0x4d000013,read32_delegate(FUNC(ghosteo_state::bballoon_speedup_r), this));
	602	m_maincpu->space(AS_PROGRAM).install_read_handler(0x4d000010, 0x4d000013,read32_delegate(FUNC(ghosteo_state::bballoon_speedup_r), this));
603	603	}
604	604
605	605	static MACHINE_CONFIG_START( ghosteo, ghosteo_state )

trunk/src/mame/drivers/kncljoe.c
r22615	r22616
263	263
264	264	void kncljoe_state::machine_start()
265	265	{
266
267	266	save_item(NAME(m_port1));
268	267	save_item(NAME(m_port2));
269	268	save_item(NAME(m_tile_bank));

trunk/src/mame/drivers/commando.c
r22615	r22616
225	225
226	226	void commando_state::machine_start()
227	227	{
228
229	228	save_item(NAME(m_scroll_x));
230	229	save_item(NAME(m_scroll_y));
231	230	}

trunk/src/mame/drivers/liberate.c
r22615	r22616
793	793
794	794	MACHINE_START_MEMBER(liberate_state,liberate)
795	795	{
796
797	796	save_item(NAME(m_background_disable));
798	797	save_item(NAME(m_background_color));
799	798	save_item(NAME(m_gfx_rom_readback));

trunk/src/mame/drivers/40love.c
r22615	r22616
968	968
969	969	MACHINE_START_MEMBER(fortyl_state,40love)
970	970	{
971
972	971	/* video */
973	972	save_item(NAME(m_pix1));
974	973	save_item(NAME(m_pix2));

trunk/src/mame/drivers/popper.c
r22615	r22616
311	311
312	312	void popper_state::machine_start()
313	313	{
314
315	314	save_item(NAME(m_flipscreen));
316	315	save_item(NAME(m_e002));
317	316	save_item(NAME(m_gfx_bank));

trunk/src/mame/drivers/psikyo4.c
r22615	r22616
656	656
657	657	void psikyo4_state::machine_start()
658	658	{
659
660	659	save_item(NAME(m_oldbrt1));
661	660	save_item(NAME(m_oldbrt2));
662	661	}

trunk/src/mame/drivers/junofrst.c
r22615	r22616
94	94	public:
95	95	junofrst_state(const machine_config &mconfig, device_type type, const char *tag)
96	96	: tutankhm_state(mconfig, type, tag),
97		m_audiocpu(*this, "audiocpu"),
98		m_i8039(*this, "mcu") { }
	97	m_audiocpu(*this, "audiocpu"),
	98	m_i8039(*this, "mcu") { }
99	99
100	100	UINT8 m_blitterdata[4];
101	101	int m_i8039_status;

trunk/src/mame/drivers/ginganin.c
r22615	r22616
228	228
229	229	void ginganin_state::machine_start()
230	230	{
231
232	231	save_item(NAME(m_layers_ctrl));
233	232	save_item(NAME(m_flipscreen));
234	233	}

trunk/src/mame/drivers/lethal.c
r22615	r22616
580	580	membank("bank1")->set_entry(0);
581	581
582	582	m_generic_paletteram_8.allocate(0x3800 + 0x02);
583
	583
584	584	save_item(NAME(m_cur_control2));
585	585	save_item(NAME(m_sprite_colorbase));
586	586	save_item(NAME(m_layer_colorbase));

trunk/src/mame/drivers/oneshot.c
r22615	r22616
338	338
339	339	void oneshot_state::machine_start()
340	340	{
341
342	341	save_item(NAME(m_gun_x_p1));
343	342	save_item(NAME(m_gun_y_p1));
344	343	save_item(NAME(m_gun_x_p2));

trunk/src/mame/drivers/atarifb.c
r22615	r22616
506	506
507	507	void atarifb_state::machine_start()
508	508	{
509
510	509	save_item(NAME(m_CTRLD));
511	510	save_item(NAME(m_sign_x_1));
512	511	save_item(NAME(m_sign_x_2));

trunk/src/mame/drivers/topspeed.c
r22615	r22616
671	671	void topspeed_state::machine_start()
672	672	{
673	673	membank("bank10")->configure_entries(0, 4, memregion("audiocpu")->base() + 0xc000, 0x4000);
674
	674
675	675	m_msm_chip[0] = m_msm1;
676	676	m_msm_chip[1] = m_msm2;
677	677	m_msm_rom[0] = memregion("adpcm")->base();

trunk/src/mame/drivers/legionna.c
r22615	r22616
224	224
225	225
226	226	WRITE8_MEMBER(legionna_state::okim_rombank_w)
227		{
	227	{
228	228	// popmessage("%08x",0x40000 * (data & 0x07));
229	229	m_oki->set_bank_base(0x40000 * (data & 0x7));
230	230	}

trunk/src/mame/drivers/msisaac.c
r22615	r22616
238	238	{
239	239	m_snd_ctrl0 = data & 0xff;
240	240	//popmessage("SND0 0=%2x 1=%2x", m_snd_ctrl0, m_snd_ctrl1);
241
	241
242	242	m_msm->set_output_gain(0, m_vol_ctrl[m_snd_ctrl0 & 15] / 100.0); /* group1 from msm5232 */
243	243	m_msm->set_output_gain(1, m_vol_ctrl[m_snd_ctrl0 & 15] / 100.0); /* group1 from msm5232 */
244	244	m_msm->set_output_gain(2, m_vol_ctrl[m_snd_ctrl0 & 15] / 100.0); /* group1 from msm5232 */
r22615	r22616
429	429
430	430	void msisaac_state::machine_start()
431	431	{
432
433	432	/* video */
434	433	save_item(NAME(m_bg2_textbank));
435	434	/* sound */

trunk/src/mame/drivers/segac2.c
r22615	r22616
1315	1315	void genesis_vdp_sndirqline_callback_segac2(running_machine &machine, bool state)
1316	1316	{
1317	1317	segac2_state *drvstate = machine.driver_data<segac2_state>();
1318
	1318
1319	1319	if (state==true)
1320	1320	drvstate->m_maincpu->set_input_line(6, HOLD_LINE);
1321	1321	}

trunk/src/mame/drivers/psikyosh.c
r22615	r22616
793	793
794	794	void psikyosh_state::machine_start()
795	795	{
796
797	796	membank("bank2")->configure_entries(0, 0x1000, memregion("gfx1")->base(), 0x20000);
798	797	}
799	798

trunk/src/mame/drivers/ddayjlc.c
r22615	r22616
450	450
451	451	void ddayjlc_state::machine_start()
452	452	{
453
454	453	save_item(NAME(m_char_bank));
455	454	save_item(NAME(m_bgadr));
456	455	save_item(NAME(m_sound_nmi_enable));

trunk/src/mame/drivers/vlc.c
r22615	r22616
696	696	* Machine Reset *
697	697	*************************/
698	698
699		void nevada_state::machine_reset()
	699	void nevada_state::machine_reset()
700	700	{
701	701	m_duart18_68681 = machine().device( "duart18_68681" );
702	702	m_duart39_68681 = machine().device( "duart39_68681" );

trunk/src/mame/drivers/egghunt.c
r22615	r22616
394	394
395	395	void egghunt_state::machine_start()
396	396	{
397
398	397	save_item(NAME(m_gfx_banking));
399	398	save_item(NAME(m_okibanking));
400	399	save_item(NAME(m_vidram_bank));

trunk/src/mame/drivers/39in1.c
r22615	r22616
1440	1440	{
1441	1441	m_dmadac[0] = machine().device<dmadac_sound_device>("dac1");
1442	1442	m_dmadac[1] = machine().device<dmadac_sound_device>("dac2");
1443
	1443
1444	1444	address_space &space = m_maincpu->space(AS_PROGRAM);
1445	1445	space.install_read_handler (0xa0151648, 0xa015164b, read32_delegate(FUNC(_39in1_state::prot_cheater_r), this));
1446	1446	}

trunk/src/mame/drivers/destroyr.c
r22615	r22616
433	433
434	434	void destroyr_state::machine_start()
435	435	{
436
437	436	save_item(NAME(m_cursor));
438	437	save_item(NAME(m_wavemod));
439	438	save_item(NAME(m_attract));

trunk/src/mame/drivers/pooyan.c
r22615	r22616
172	172
173	173	void pooyan_state::machine_start()
174	174	{
175
176	175	save_item(NAME(m_irq_enable));
177	176	}
178	177

trunk/src/mame/drivers/zn.c
r22615	r22616
1387	1387	{
1388	1388	device_t *ide = machine().device("ide");
1389	1389
1390		// logerror("DMA read: %d bytes (%d words) to %08x\n", n_size<<2, n_size, n_address);
	1390	// logerror("DMA read: %d bytes (%d words) to %08x\n", n_size<<2, n_size, n_address);
1391	1391
1392	1392	if (n_address < 0x10000)
1393	1393	{

trunk/src/mame/drivers/hvyunit.c
r22615	r22616
132	132	UINT32 screen_update_hvyunit(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
133	133	void screen_eof_hvyunit(screen_device &screen, bool state);
134	134	TIMER_DEVICE_CALLBACK_MEMBER(hvyunit_scanline);
135		required_device<cpu_device> m_soundcpu;
	135	required_device<cpu_device> m_soundcpu;
136	136	};
137	137
138	138

trunk/src/mame/drivers/pasha2.c
r22615	r22616
115	115	UINT32 screen_update_pasha2(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
116	116	required_device<cpu_device> m_maincpu;
117	117	required_device<okim6295_device> m_oki1;
118		required_device<okim6295_device> m_oki2;
	118	required_device<okim6295_device> m_oki2;
119	119	};
120	120
121	121

trunk/src/mame/drivers/skyfox.c
r22615	r22616
219	219
220	220	void skyfox_state::machine_start()
221	221	{
222
223	222	save_item(NAME(m_bg_pos));
224	223	save_item(NAME(m_bg_ctrl));
225	224	}

trunk/src/mame/drivers/savquest.c
r22615	r22616
641	641
642	642	/* video hardware */
643	643	MCFG_FRAGMENT_ADD( pcvideo_vga )
644
	644
645	645	MCFG_KBDC8042_ADD("kbdc", at8042)
646	646	MACHINE_CONFIG_END
647	647

trunk/src/mame/drivers/sonson.c
r22615	r22616
227	227
228	228	void sonson_state::machine_start()
229	229	{
230
231	230	save_item(NAME(m_last_irq));
232	231	}
233	232

trunk/src/mame/drivers/photoply.c
r22615	r22616
398	398	MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
399	399
400	400	MCFG_FRAGMENT_ADD( pcvideo_vga )
401
	401
402	402	MCFG_KBDC8042_ADD("kbdc", at8042)
403	403	MACHINE_CONFIG_END
404	404

trunk/src/mame/drivers/madmotor.c
r22615	r22616
220	220
221	221	void madmotor_state::machine_start()
222	222	{
223
224	223	save_item(NAME(m_flipscreen));
225	224	}
226	225

trunk/src/mame/drivers/pipedrm.c
r22615	r22616
607	607
608	608	MACHINE_START_MEMBER(pipedrm_state,pipedrm)
609	609	{
610
611	610	/* initialize main Z80 bank */
612	611	membank("bank1")->configure_entries(0, 8, memregion("maincpu")->base() + 0x10000, 0x2000);
613	612	membank("bank1")->set_entry(0);

trunk/src/mame/drivers/mediagx.c
r22615	r22616
1225	1225	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
1226	1226	MACHINE_CONFIG_END
1227	1227
1228
	1228
1229	1229	void mediagx_state::init_mediagx()
1230	1230	{
1231	1231	m_frame_width = m_frame_height = 1;

trunk/src/mame/drivers/midqslvr.c
r22615	r22616
682	682	MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
683	683
684	684	MCFG_KBDC8042_ADD("kbdc", at8042)
685
	685
686	686	/* video hardware */
687	687	MCFG_FRAGMENT_ADD( pcvideo_vga )
688	688	MACHINE_CONFIG_END

trunk/src/mame/drivers/karnov.c
r22615	r22616
758	758
759	759	void karnov_state::machine_start()
760	760	{
761
762	761	save_item(NAME(m_flipscreen));
763	762	save_item(NAME(m_scroll));
764	763

trunk/src/mame/drivers/m14.c
r22615	r22616
316	316
317	317	void m14_state::machine_start()
318	318	{
319
320	319	save_item(NAME(m_hop_mux));
321	320	}
322	321

trunk/src/mame/drivers/norautp.c
r22615	r22616
3458	3458	*/
3459	3459
3460	3460	ROM_START( pkii_dm )
3461		ROM_REGION( 0x10000, "maincpu", 0 ) /* no stack, call's RET go to PC=0 */
	3461	ROM_REGION( 0x10000, "maincpu", 0 ) /* no stack, call's RET go to PC=0 */
3462	3462	ROM_LOAD( "12.u12", 0x0000, 0x1000, CRC(048e70d8) SHA1(f0eb16ba68455638de2ce68f51f305a13d0df287) )
3463	3463	ROM_LOAD( "13.u18", 0x1000, 0x1000, CRC(06cf6789) SHA1(587d883c399348b518e3be4d1dc2581824055328) )
3464	3464
r22615	r22616
3665	3665	GAME( 198?, dphlunkb, 0, dphl, norautp, driver_device, 0, ROT0, "SMS Manufacturing Corp.", "Draw Poker HI-LO (unknown, rev 2)", GAME_NOT_WORKING )
3666	3666
3667	3667	GAME( 198?, pkii_dm, 0, nortest1, norautp, driver_device, 0, ROT0, "<unknown>", "Unknown Poker PKII/DM", GAME_NOT_WORKING )
3668

trunk/src/mame/drivers/snk.c
r22615	r22616
2423	2423
2424	2424
2425	2425	static INPUT_PORTS_START( fitegolfu )
2426		PORT_INCLUDE( fitegolf )
	2426	PORT_INCLUDE( fitegolf )
2427	2427
2428	2428	PORT_MODIFY("DSW2")
2429	2429	PORT_DIPNAME( 0x01, 0x01, "Shot Time" ) PORT_DIPLOCATION("DSW2:1")
r22615	r22616
4630	4630	ROM_LOAD( "pal20l8a.6r", 0x0400, 0x0144, CRC(0f011673) SHA1(383e6f6e78daec9c874d5b48378111ca60f5ed64) )
4631	4631	ROM_END
4632	4632
4633		ROM_START( fitegolfu ) /* Later US version containing enhancements to make the game a little easier */
	4633	ROM_START( fitegolfu ) /* Later US version containing enhancements to make the game a little easier */
4634	4634	ROM_REGION( 0x10000, "maincpu", 0 )
4635	4635	ROM_LOAD( "np45.128", 0x0000, 0x4000, CRC(16e8e763) SHA1(0b5296f2a91a7f3176b7461ca4958865ce998241) )
4636	4636	ROM_LOAD( "mn45.256", 0x4000, 0x8000, CRC(a4fa09d5) SHA1(ae7f0cb47de06006ae71252c4201a93a01a26887) )

trunk/src/mame/drivers/calchase.c
r22615	r22616
925	925	MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
926	926	MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
927	927	MCFG_PCI_BUS_LEGACY_DEVICE(7, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
928
	928
929	929	MCFG_KBDC8042_ADD("kbdc", at8042)
930
	930
931	931	/* video hardware */
932	932	MCFG_FRAGMENT_ADD( pcvideo_trident_vga )
933	933

trunk/src/mame/drivers/ashnojoe.c
r22615	r22616
326	326
327	327	void ashnojoe_state::machine_start()
328	328	{
329
330	329	save_item(NAME(m_adpcm_byte));
331	330	save_item(NAME(m_soundlatch_status));
332	331	save_item(NAME(m_msm5205_vclk_toggle));

trunk/src/mame/drivers/kopunch.c
r22615	r22616
169	169
170	170	void kopunch_state::machine_start()
171	171	{
172
173	172	save_item(NAME(m_gfxbank));
174	173	}
175	174

trunk/src/mame/mame.lst
r22615	r22616
2510	2510	twinadv // (c) 1995 Barko Corp
2511	2511	twinadvk // (c) 1995 Barko Corp
2512	2512	snowbro3 // (c) 2002 Syrmex
2513		ballboy // bootleg
	2513	ballboy // bootleg
2514	2514	// SemiCom games on "SnowBros"-like hardware
2515	2515	finalttr // (c) 1993 Jeil Computer System
2516	2516	hyperpac // (c) 1995 SemiCom
r22615	r22616
5083	5083	derbyocw // 2001.?? Derby Owners Club World Edition (Rev. D)
5084	5084	shootplm // 2001.?? Shootout Pool Medal
5085	5085	// 2001.?? Star Horse 2001
5086		shaktmsp // 2001.?? Shakatto Tambourine 2K1 SPR
	5086	shaktmsp // 2001.?? Shakatto Tambourine 2K1 SPR
5087	5087	vathlete // 2002.03 Virtua Athletics / Virtua Athlete
5088	5088	luptype // 2002.04 Lupin The Third - The Typing (Rev A)
5089	5089	cleoftp // 2002.05 Cleopatra Fortune Plus
r22615	r22616
8741	8741	bestbest // (c) 1994 SunA
8742	8742	sunaq // (c) 1994 SunA
8743	8743	bssoccer // (c) 1996 SunA
8744		bssoccera // (c) 1996 SunA
	8744	bssoccera // (c) 1996 SunA
8745	8745	uballoon // (c) 1996 SunA
8746	8746	go2000 // (c) 2000 SA
8747	8747
r22615	r22616
9279	9279	olds // (c) 1999 Oriental Legend Super / Special
9280	9280	olds100 //
9281	9281	olds100a //
9282		olds103t //
	9282	olds103t //
9283	9283	kov2 // (c) 2000 Knights of Valor 2
9284	9284	kov2106 //
9285	9285	kov2103 //
r22615	r22616
9291	9291	ddp2 // (c) 2001 DoDonPachi 2 - Bee Storm
9292	9292	ddp2101 //
9293	9293	ddp2100 //
9294		ddp2hk //
9295		ddp2101hk //
9296		ddp2100hk //
9297		ddp2k //
9298		ddp2101k //
9299		ddp2100k //
9300		ddp2j //
9301		ddp2101j //
9302		ddp2100j //
9303		ddp2t //
9304		ddp2101t //
9305		ddp2100t //
9306		ddp2c //
9307		ddp2101c //
9308		ddp2100c //
	9294	ddp2hk //
	9295	ddp2101hk //
	9296	ddp2100hk //
	9297	ddp2k //
	9298	ddp2101k //
	9299	ddp2100k //
	9300	ddp2j //
	9301	ddp2101j //
	9302	ddp2100j //
	9303	ddp2t //
	9304	ddp2101t //
	9305	ddp2100t //
	9306	ddp2c //
	9307	ddp2101c //
	9308	ddp2100c //
9309	9309	puzzli2 // (c) 1999 Puzzli 2
9310	9310	puzzli2s // (c) 2001 Puzzli 2 Super
9311	9311	martmast // (c) 2001 Martial Masters

trunk/src/mame/machine/pcshare.c
r22615	r22616
45	45	READ8_MEMBER(pcat_base_state::pc_dma_read_byte)
46	46	{
47	47	address_space& prog_space = m_maincpu->space(AS_PROGRAM); // get the right address space
48
	48
49	49	offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16)
50	50	& 0xFF0000;
51	51
r22615	r22616
246	246	MCFG_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
247	247	MCFG_PIT8254_ADD( "pit8254", at_pit8254_config )
248	248	// MCFG_MC146818_ADD( "rtc", MC146818_STANDARD )
249
	249
250	250	MCFG_KBDC8042_ADD("kbdc", at8042)
251	251	MACHINE_CONFIG_END

trunk/src/mame/machine/pcshare.h
r22615	r22616
11	11	m_dma8237_1(*this, "dma8237_1"),
12	12	m_pic8259_1(*this, "pic8259_1"),
13	13	m_pic8259_2(*this, "pic8259_2"),
14		m_pit8254(*this, "pit8254") { }
	14	m_pit8254(*this, "pit8254") { }
15	15
16	16	IRQ_CALLBACK_MEMBER(irq_callback);
17	17
r22615	r22616
20	20	required_device<pic8259_device> m_pic8259_1;
21	21	required_device<pic8259_device> m_pic8259_2;
22	22	required_device<pit8254_device> m_pit8254;
23
	23
24	24	DECLARE_WRITE_LINE_MEMBER(pc_dma_hrq_changed);
25	25	DECLARE_READ8_MEMBER(pc_dma_read_byte);
26	26	DECLARE_WRITE8_MEMBER(pc_dma_write_byte);

trunk/src/mame/machine/pcecommn.h
r22615	r22616
24	24	DECLARE_DRIVER_INIT(pce_common);
25	25
26	26	required_device<cpu_device> m_maincpu;
27
	27
28	28	virtual UINT8 joy_read();
29	29	private:
30	30	UINT8 m_io_port_options; /driver-specific options for the PCE/

trunk/src/mame/machine/nitedrvr.c
r22615	r22616
272	272
273	273	void nitedrvr_state::machine_start()
274	274	{
275
276	275	save_item(NAME(m_gear));
277	276	save_item(NAME(m_track));
278	277	save_item(NAME(m_steering_buf));

trunk/src/mame/video/taitoic.h
r22615	r22616
527	527	DECLARE_READ16_DEVICE_HANDLER( tc0180vcu_word_r );
528	528	DECLARE_WRITE16_DEVICE_HANDLER( tc0180vcu_word_w );
529	529	void tc0180vcu_tilemap_draw(device_t *device, bitmap_ind16 &bitmap, const rectangle &cliprect, int tmap_num, int plane);
530		#endif
		No newline at end of file
	530	#endif

trunk/src/mame/mame.mak
r22615	r22616
787	787
788	788	$(MAMEOBJ)/ibmpc.a: \
789	789	$(DRIVERS)/calchase.o \
790		$(DRIVERS)/fruitpc.o \
	790	$(DRIVERS)/fruitpc.o \
791	791	$(DRIVERS)/pangofun.o \
792	792	$(DRIVERS)/pcat_dyn.o \
793	793	$(DRIVERS)/pcat_nit.o \
r22615	r22616
846	846	$(DRIVERS)/capbowl.o $(VIDEO)/capbowl.o \
847	847	$(DRIVERS)/itech8.o $(MACHINE)/slikshot.o $(VIDEO)/itech8.o \
848	848	$(DRIVERS)/itech32.o $(VIDEO)/itech32.o \
849		$(DRIVERS)/iteagle.o \
	849	$(DRIVERS)/iteagle.o \
850	850
851	851	$(MAMEOBJ)/jaleco.a: \
852	852	$(DRIVERS)/aeroboto.o $(VIDEO)/aeroboto.o \
r22615	r22616
1055	1055	$(DRIVERS)/midyunit.o $(MACHINE)/midyunit.o $(VIDEO)/midyunit.o \
1056	1056	$(DRIVERS)/midzeus.o $(VIDEO)/midzeus.o $(VIDEO)/midzeus2.o \
1057	1057	$(DRIVERS)/omegrace.o \
1058		$(DRIVERS)/pinball2k.o \
	1058	$(DRIVERS)/pinball2k.o \
1059	1059	$(DRIVERS)/seattle.o \
1060	1060	$(DRIVERS)/tmaster.o \
1061	1061	$(DRIVERS)/vegas.o $(DRIVERS)/wmg.o \

trunk/src/mame/includes/exzisus.h
r22615	r22616
18	18	required_shared_ptr<UINT8> m_objectram0;
19	19	required_shared_ptr<UINT8> m_videoram0;
20	20	required_device<cpu_device> m_cpuc;
21
	21
22	22	int m_cpua_bank;
23	23	int m_cpub_bank;
24	24

trunk/src/mame/includes/meadows.h
r22615	r22616
15	15	m_videoram(*this, "videoram"),
16	16	m_maincpu(*this, "maincpu"),
17	17	m_dac(*this, "dac"),
18		m_samples(*this, "samples") { }
	18	m_samples(*this, "samples") { }
19	19
20	20	optional_shared_ptr<UINT8> m_spriteram;
21	21	required_shared_ptr<UINT8> m_videoram;

trunk/src/mame/includes/niyanpai.h
r22615	r22616
96	96	void niyanpai_soundbank_w(int data);
97	97	required_device<cpu_device> m_maincpu;
98	98	required_device<dac_device> m_dac1;
99		required_device<dac_device> m_dac2;
	99	required_device<dac_device> m_dac2;
100	100	};

trunk/src/mame/includes/leland.h
r22615	r22616
31	31	required_device<cpu_device> m_master;
32	32	required_device<cpu_device> m_slave;
33	33	required_device<eeprom_device> m_eeprom;
34
	34
35	35	UINT8 m_dac_control;
36	36	UINT8 *m_alleymas_kludge_mem;
37	37	UINT8 *m_ataxx_qram;

trunk/src/mame/includes/tbowl.h
r22615	r22616
66	66	required_device<cpu_device> m_maincpu;
67	67	required_device<cpu_device> m_audiocpu;
68	68	required_device<msm5205_device> m_msm1;
69		required_device<msm5205_device> m_msm2;
	69	required_device<msm5205_device> m_msm2;
70	70	};

trunk/src/mame/includes/asuka.h
r22615	r22616
42	42	/* devices */
43	43	required_device<cpu_device> m_maincpu;
44	44	required_device<cpu_device> m_audiocpu;
45		optional_device<msm5205_device> m_msm;
	45	optional_device<msm5205_device> m_msm;
46	46	required_device<pc090oj_device> m_pc090oj;
47	47	required_device<tc0100scn_device> m_tc0100scn;
48	48	DECLARE_WRITE8_MEMBER(sound_bankswitch_w);

trunk/src/mame/includes/nmk16.h
r22615	r22616
182	182	required_device<cpu_device> m_maincpu;
183	183	optional_device<cpu_device> m_audiocpu;
184	184	optional_device<okim6295_device> m_oki1;
185		optional_device<okim6295_device> m_oki2;
	185	optional_device<okim6295_device> m_oki2;
186	186	};

trunk/src/mame/includes/eprom.h
r22615	r22616
11	11	public:
12	12	eprom_state(const machine_config &mconfig, device_type type, const char *tag)
13	13	: atarigen_state(mconfig, type, tag),
14		m_extra(*this, "extra") { }
	14	m_extra(*this, "extra") { }
15	15
16	16	int m_screen_intensity;
17	17	int m_video_disable;

trunk/src/mame/includes/suna16.h
r22615	r22616
18	18	required_shared_ptr<UINT16> m_spriteram;
19	19	optional_shared_ptr<UINT16> m_spriteram2;
20	20	required_device<dac_device> m_dac1;
21		required_device<dac_device> m_dac2;
	21	required_device<dac_device> m_dac2;
22	22	optional_device<dac_device> m_dac3;
23		optional_device<dac_device> m_dac4;
	23	optional_device<dac_device> m_dac4;
24	24	UINT8 m_prot;
25	25	UINT16 *m_paletteram;
26	26	int m_color_bank;

trunk/src/mame/includes/jaguar.h
r22615	r22616
53	53	m_main_gpu_wait(NULL),
54	54	m_joystick_data(0),
55	55	m_eeprom_bit_count(0),
56		m_protection_check(0) ,
	56	m_protection_check(0) ,
57	57	m_eeprom(*this, "eeprom") { }
58	58
59	59	// devices

trunk/src/mame/includes/toaplan1.h
r22615	r22616
15	15	m_spriteram(*this, "spriteram"),
16	16	m_maincpu(*this, "maincpu"),
17	17	m_audiocpu(*this, "audiocpu"),
18		m_dsp(*this, "dsp") { }
	18	m_dsp(*this, "dsp") { }
19	19
20	20	int m_unk_reset_port;
21	21	required_shared_ptr<UINT16> m_colorram1;

trunk/src/mame/includes/dynax.h
r22615	r22616
13	13	: driver_device(mconfig, type, tag),
14	14	m_dsw_sel16(*this, "dsw_sel16"),
15	15	m_protection1(*this, "protection1"),
16		m_protection2(*this, "protection2"),
	16	m_protection2(*this, "protection2"),
17	17	m_maincpu(*this, "maincpu"),
18	18	m_soundcpu(*this, "soundcpu"),
19	19	m_oki(*this, "oki"),

trunk/src/mame/includes/scramble.h
r22615	r22616
8	8	: galaxold_state(mconfig, type, tag),
9	9	m_ppi8255_0(*this, "ppi8255_0"),
10	10	m_ppi8255_1(*this, "ppi8255_1"),
11		m_soundram(*this, "soundram")
	11	m_soundram(*this, "soundram")
12	12	{ }
13	13
14	14	optional_device<i8255_device> m_ppi8255_0;

trunk/src/mame/includes/namcos21.h
r22615	r22616
46	46	required_shared_ptr<UINT16> m_mpSharedRAM1;
47	47	required_shared_ptr<UINT8> m_mpDualPortRAM;
48	48	optional_shared_ptr<UINT16> m_master_dsp_code;
49
	49
50	50	optional_device<cpu_device> m_dsp;
51	51
52	52	UINT8 *m_videoram;

trunk/src/mame/includes/rainbow.h
r22615	r22616
14	14	m_maincpu(*this, "maincpu"),
15	15	m_audiocpu(*this, "audiocpu"),
16	16	m_pc080sn(*this, "pc080sn"),
17		m_pc090oj(*this, "pc090oj") { }
	17	m_pc090oj(*this, "pc090oj") { }
18	18
19	19	/* memory pointers */
20	20	optional_shared_ptr<UINT16> m_spriteram;

trunk/src/mame/includes/galaga.h
r22615	r22616
148	148	char m_battles_customio_command_count;
149	149	char m_battles_customio_data;
150	150	char m_battles_sound_played;
151
	151
152	152	optional_device<cpu_device> m_subcpu3;
153	153	};
154	154

trunk/src/mame/includes/spdodgeb.h
r22615	r22616
61	61	DECLARE_WRITE_LINE_MEMBER(spd_adpcm_int_2);
62	62	required_device<cpu_device> m_audiocpu;
63	63	required_device<msm5205_device> m_msm1;
64		required_device<msm5205_device> m_msm2;
	64	required_device<msm5205_device> m_msm2;
65	65	};

trunk/src/mame/includes/dec8.h
r22615	r22616
25	25	/* memory pointers */
26	26	required_shared_ptr<UINT8> m_videoram;
27	27	optional_shared_ptr<UINT8> m_bg_data;
28
	28
29	29	optional_device<msm5205_device> m_msm;
30	30	UINT8 * m_pf1_data;
31	31	UINT8 * m_row;

trunk/src/mame/includes/xexex.h
r22615	r22616
17	17	m_workram(*this, "workram"),
18	18	m_spriteram(*this, "spriteram"),
19	19	m_maincpu(*this, "maincpu"),
20		m_audiocpu(*this, "audiocpu"),
	20	m_audiocpu(*this, "audiocpu"),
21	21	m_k054539(*this, "k054539"),
22	22	m_filter1l(*this, "filter1l"),
23	23	m_filter1r(*this, "filter1r"),

trunk/src/mame/includes/nbmj8688.h
r22615	r22616
89	89	DECLARE_VIDEO_START(mbmj8688_hybrid_12bit);
90	90	DECLARE_VIDEO_START(mbmj8688_pure_16bit);
91	91	DECLARE_READ8_MEMBER(dipsw1_r);
92		DECLARE_READ8_MEMBER(dipsw2_r);
	92	DECLARE_READ8_MEMBER(dipsw2_r);
93	93	UINT32 screen_update_mbmj8688(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
94	94	UINT32 screen_update_mbmj8688_lcd0(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
95	95	UINT32 screen_update_mbmj8688_lcd1(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);

trunk/src/mame/includes/slapshot.h
r22615	r22616
58	58
59	59	/* devices */
60	60	required_device<cpu_device> m_maincpu;
61		required_device<cpu_device> m_audiocpu;
	61	required_device<cpu_device> m_audiocpu;
62	62	required_device<tc0140syt_device> m_tc0140syt;
63	63	required_device<tc0480scp_device> m_tc0480scp;
64	64	required_device<tc0360pri_device> m_tc0360pri;

trunk/src/mame/includes/metro.h
r22615	r22616
62	62	optional_shared_ptr<UINT16> m_screenctrl;
63	63	optional_shared_ptr<UINT16> m_input_sel;
64	64	optional_shared_ptr<UINT16> m_k053936_ram;
65
	65
66	66	optional_device<eeprom_device> m_eeprom;
67	67
68	68

trunk/src/mame/includes/turbo.h
r22615	r22616
44	44	required_shared_ptr<UINT8> m_videoram;
45	45	required_shared_ptr<UINT8> m_spriteram;
46	46	required_shared_ptr<UINT8> m_sprite_position;
47
	47
48	48	required_device<samples_device> m_samples;
49	49
50	50	UINT8 * m_buckrog_bitmap_ram;

trunk/src/mame/includes/taitojc.h
r22615	r22616
168	168	void taitojc_clear_frame();
169	169	void debug_dsp_command();
170	170	};
171

trunk/src/mame/includes/thunderj.h
r22615	r22616
11	11	public:
12	12	thunderj_state(const machine_config &mconfig, device_type type, const char *tag)
13	13	: atarigen_state(mconfig, type, tag),
14		m_extra(*this, "extra") { }
	14	m_extra(*this, "extra") { }
15	15
16	16	UINT8 m_alpha_tile_bank;
17	17	virtual void update_interrupts();

trunk/src/mame/includes/mario.h
r22615	r22616
93	93	DECLARE_WRITE8_MEMBER(mario_sh1_w);
94	94	DECLARE_WRITE8_MEMBER(mario_sh2_w);
95	95	DECLARE_READ8_MEMBER(memory_read_byte);
96		DECLARE_WRITE8_MEMBER(memory_write_byte);
	96	DECLARE_WRITE8_MEMBER(memory_write_byte);
97	97	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect);
98	98	required_device<cpu_device> m_maincpu;
99	99	required_device<cpu_device> m_audiocpu;

trunk/src/mame/includes/deco32.h
r22615	r22616
45	45	optional_device<decospr_device> m_sprgen;
46	46	optional_device<decospr_device> m_sprgen1;
47	47	optional_device<decospr_device> m_sprgen2;
48
	48
49	49	optional_device<eeprom_device> m_eeprom;
50	50	optional_device<okim6295_device> m_oki1;
51	51	optional_device<okim6295_device> m_oki2;

trunk/src/mame/includes/mitchell.h
r22615	r22616
31	31	/* memory pointers */
32	32	required_shared_ptr<UINT8> m_colorram;
33	33	required_shared_ptr<UINT8> m_videoram;
34
	34
35	35	optional_device<eeprom_device> m_eeprom;
36	36	optional_device<msm5205_device> m_msm;
37	37

trunk/src/mame/includes/bublbobl.h
r22615	r22616
9	9	m_mcu_sharedram(*this, "mcu_sharedram"),
10	10	m_maincpu(*this, "maincpu"),
11	11	m_mcu(*this, "mcu"),
12		m_audiocpu(*this, "audiocpu"),
	12	m_audiocpu(*this, "audiocpu"),
13	13	m_slave(*this, "slave"){ }
14	14
15	15	/* memory pointers */

trunk/src/mame/includes/docastle.h
r22615	r22616
32	32	required_device<cpu_device> m_maincpu;
33	33	required_device<cpu_device> m_slave;
34	34	optional_device<msm5205_device> m_msm;
35
	35
36	36	DECLARE_READ8_MEMBER(docastle_shared0_r);
37	37	DECLARE_READ8_MEMBER(docastle_shared1_r);
38	38	DECLARE_WRITE8_MEMBER(docastle_shared0_w);

trunk/src/mame/includes/psikyo4.h
r22615	r22616
38	38	/* devices */
39	39	required_device<cpu_device> m_maincpu;
40	40	required_device<eeprom_device> m_eeprom;
41
	41
42	42	DECLARE_WRITE32_MEMBER(ps4_paletteram32_RRRRRRRRGGGGGGGGBBBBBBBBxxxxxxxx_dword_w);
43	43	DECLARE_WRITE32_MEMBER(ps4_bgpen_1_dword_w);
44	44	DECLARE_WRITE32_MEMBER(ps4_bgpen_2_dword_w);

trunk/src/mame/includes/nbmj9195.h
r22615	r22616
132	132	void mscoutm_inputportsel_w(int data);
133	133	required_device<cpu_device> m_maincpu;
134	134	required_device<dac_device> m_dac1;
135		required_device<dac_device> m_dac2;
	135	required_device<dac_device> m_dac2;
136	136	};

trunk/src/osd/sdl/debugqtmemorywindow.h
r22615	r22616
59	59	}
60	60
61	61	~MemoryWindowQtConfig() {}
62
	62
63	63	// Settings
64	64	int m_reverse;
65	65	int m_addressMode;
66	66	int m_chunkSize;
67	67	int m_memoryRegion;
68
	68
69	69	void buildFromQWidget(QWidget* widget);
70	70	void applyToQWidget(QWidget* widget);
71	71	void addToXmlDataNode(xml_data_node* node) const;

trunk/src/osd/sdl/debugqtmainwindow.c
r22615	r22616
125	125	void MainWindow::closeEvent(QCloseEvent* event)
126	126	{
127	127	debugActQuit();
128
	128
129	129	// Insure the window doesn't disappear before we get a chance to save its parameters
130	130	event->ignore();
131	131	}

trunk/src/osd/sdl/debugqtmainwindow.h
r22615	r22616
171	171	m_rightBar(0),
172	172	m_windowState()
173	173	{}
174
	174
175	175	~MainWindowQtConfig() {}
176
	176
177	177	// Settings
178	178	int m_rightBar;
179	179	QByteArray m_windowState;
180
	180
181	181	void buildFromQWidget(QWidget* widget);
182	182	void applyToQWidget(QWidget* widget);
183	183	void addToXmlDataNode(xml_data_node* node) const;

trunk/src/osd/sdl/sdldir.c
r22615	r22616
89	89	case DT_REG:
90	90	return ENTTYPE_FILE;
91	91
92		case DT_LNK:
	92	case DT_LNK:
93	93	{
94	94	struct stat s;
95	95

trunk/src/osd/sdl/debugqtwindow.h
r22615	r22616
77	77	m_next(NULL)
78	78	{}
79	79	virtual ~WindowQtConfig() {}
80
	80
81	81	// Settings
82	82	WindowType m_type;
83	83	QPoint m_size;
84	84	QPoint m_position;
85
	85
86	86	// Dues for becoming a member of a simple_list
87	87	WindowQtConfig* m_next;
88	88	WindowQtConfig* next() const { return m_next; }
89
90
	89
	90
91	91	virtual void buildFromQWidget(QWidget* widget);
92	92	virtual void applyToQWidget(QWidget* widget);
93	93	virtual void addToXmlDataNode(xml_data_node* node) const;

trunk/src/osd/sdl/debugqtlogwindow.h
r22615	r22616
35	35	WindowQtConfig(WIN_TYPE_LOG)
36	36	{
37	37	}
38
	38
39	39	~LogWindowQtConfig() {}
40
	40
41	41	void buildFromQWidget(QWidget* widget);
42	42	void applyToQWidget(QWidget* widget);
43	43	void addToXmlDataNode(xml_data_node* node) const;

trunk/src/osd/sdl/debugqtdasmwindow.h
r22615	r22616
52	52	m_rightBar(0)
53	53	{
54	54	}
55
	55
56	56	~DasmWindowQtConfig() {}
57
	57
58	58	// Settings
59	59	int m_cpu;
60	60	int m_rightBar;
61
	61
62	62	void buildFromQWidget(QWidget* widget);
63	63	void applyToQWidget(QWidget* widget);
64	64	void addToXmlDataNode(xml_data_node* node) const;

trunk/src/version.c
r22615	r22616
38	38	***************************************************************************/
39	39
40	40	extern const char build_version[];
41		const char build_version[] = "0.148u3 ("__DATE__")";
	41	const char build_version[] = "0.148u4 ("__DATE__")";

trunk/src/lib/util/simple_set.h
r22615	r22616
31	31	// PUBLIC OPERATIONS:
32	32	// size, empty, clear, insert, remove, find, contains, merge, & assignment.
33	33	//
34
	34
35	35	template <class T>
36	36	class simple_set
37	37	{
38		friend class simple_set_iterator<T>;
39		typedef avl_tree_node<T> tree_node;
	38	friend class simple_set_iterator<T>;
	39	typedef avl_tree_node<T> tree_node;
40	40
41	41	public:
42		// Construction
43		simple_set(resource_pool &pool = global_resource_pool())
44		: m_root(NULL),
45		m_pool(pool)
46		{ }
	42	// Construction
	43	simple_set(resource_pool &pool = global_resource_pool())
	44	: m_root(NULL),
	45	m_pool(pool)
	46	{ }
47	47
48		simple_set(const simple_set& rhs)
49		: m_root(NULL)
50		{
51		*this = rhs;
52		}
	48	simple_set(const simple_set& rhs)
	49	: m_root(NULL)
	50	{
	51	*this = rhs;
	52	}
53	53
54		~simple_set()
55		{
56		clear();
57		}
	54	~simple_set()
	55	{
	56	clear();
	57	}
58	58
59	59
60		// A reference to the resource pool
	60	// A reference to the resource pool
61	61	resource_pool &pool() const { return m_pool; }
62	62
63	63
64		// Returns number of elements in the tree -- O(n)
65		int size() const
66		{
67		if (empty()) return 0;
	64	// Returns number of elements in the tree -- O(n)
	65	int size() const
	66	{
	67	if (empty()) return 0;
68	68
69		const tree_node* currentNode = m_root;
70		const int nodeCount = sizeRecurse(currentNode);
71		return nodeCount;
72		}
	69	const tree_node* currentNode = m_root;
	70	const int nodeCount = sizeRecurse(currentNode);
	71	return nodeCount;
	72	}
73	73
74	74
75		// Test for emptiness -- O(1).
76		bool empty() const
77		{
78		return m_root == NULL;
79		}
	75	// Test for emptiness -- O(1).
	76	bool empty() const
	77	{
	78	return m_root == NULL;
	79	}
80	80
81	81
82		// Empty the tree -- O(n).
83		void clear()
84		{
85		clearRecurse(m_root);
86		}
	82	// Empty the tree -- O(n).
	83	void clear()
	84	{
	85	clearRecurse(m_root);
	86	}
87	87
88	88
89		// Insert x into the avl tree; duplicates are ignored -- O(log n).
90		bool insert(const T& x)
91		{
92		bool retVal = insert(x, m_root);
	89	// Insert x into the avl tree; duplicates are ignored -- O(log n).
	90	bool insert(const T& x)
	91	{
	92	bool retVal = insert(x, m_root);
93	93
94		// Whether the node was successfully inserted or not (i.e. wasn't a duplicate)
95		return retVal;
96		}
97
98
99		// Remove x from the tree. Nothing is done if x is not found -- O(n).
100		bool remove(const T& x)
101		{
102		// First find the node in the tree
103		tree_node* currNode = find(x, m_root);
	94	// Whether the node was successfully inserted or not (i.e. wasn't a duplicate)
	95	return retVal;
	96	}
104	97
105		// Only do this when the current node is valid
106		if (currNode)
107		{
108		// See if it's a leaf
109		if (currNode->isLeaf())
110		{
111		// If we're a leaf and we have no parent, then the tree will be emptied
112		if (!currNode->parent)
113		{
114		m_root = NULL;
115		}
116	98
117		// If it's a leaf node, simply remove it
118		removeNode(currNode);
119		pool_free(m_pool, currNode);
120		}
121		else
122		{
123		// Get the parent object
124		tree_node* parentNode = currNode->parent;
	99	// Remove x from the tree. Nothing is done if x is not found -- O(n).
	100	bool remove(const T& x)
	101	{
	102	// First find the node in the tree
	103	tree_node* currNode = find(x, m_root);
125	104
126		// Remove the child and reconnect the smallest node in the right sub tree
127		// (in order successor)
128		tree_node* replaceNode = findMin(currNode->right);
	105	// Only do this when the current node is valid
	106	if (currNode)
	107	{
	108	// See if it's a leaf
	109	if (currNode->isLeaf())
	110	{
	111	// If we're a leaf and we have no parent, then the tree will be emptied
	112	if (!currNode->parent)
	113	{
	114	m_root = NULL;
	115	}
129	116
130		// See if there's even a right-most node
131		if (!replaceNode)
132		{
133		// Get the largest node on the left (because the right doesn't exist)
134		replaceNode = findMax(currNode->left);
135		}
	117	// If it's a leaf node, simply remove it
	118	removeNode(currNode);
	119	pool_free(m_pool, currNode);
	120	}
	121	else
	122	{
	123	// Get the parent object
	124	tree_node* parentNode = currNode->parent;
136	125
137		// Disconnect the replacement node's branch
138		removeNode(replaceNode);
	126	// Remove the child and reconnect the smallest node in the right sub tree
	127	// (in order successor)
	128	tree_node* replaceNode = findMin(currNode->right);
139	129
140		// Disconnect the current node
141		removeNode(currNode);
	130	// See if there's even a right-most node
	131	if (!replaceNode)
	132	{
	133	// Get the largest node on the left (because the right doesn't exist)
	134	replaceNode = findMax(currNode->left);
	135	}
142	136
143		// Get the current node's left and right branches
144		tree_node* left = currNode->left;
145		tree_node* right = currNode->right;
	137	// Disconnect the replacement node's branch
	138	removeNode(replaceNode);
146	139
147		// We no longer need this node
148		pool_free(m_pool, currNode);
	140	// Disconnect the current node
	141	removeNode(currNode);
149	142
150		// Check to see if we removed the root node
151		if (!parentNode)
152		{
153		// Merge the branches into the parent node of what we deleted
154		merge(replaceNode, parentNode);
155		merge(left, parentNode);
156		merge(right, parentNode);
	143	// Get the current node's left and right branches
	144	tree_node* left = currNode->left;
	145	tree_node* right = currNode->right;
157	146
158		// Now we're the the root
159		m_root = parentNode;
160		}
161		else
162		{
163		// Merge the branches into the parent node of what we
164		// deleted, we let the merge algorithm decide where to
165		// put the branches
166		merge(replaceNode, parentNode);
167		merge(left, parentNode);
168		merge(right, parentNode);
169		}
170		}
	147	// We no longer need this node
	148	pool_free(m_pool, currNode);
171	149
172		// Balance the tree
173		balanceTree();
	150	// Check to see if we removed the root node
	151	if (!parentNode)
	152	{
	153	// Merge the branches into the parent node of what we deleted
	154	merge(replaceNode, parentNode);
	155	merge(left, parentNode);
	156	merge(right, parentNode);
174	157
175		// The node was found and removed successfully
176		return true;
177		}
178		else
179		{
180		// The node was not found
181		return false;
182		}
183		}
184
	158	// Now we're the the root
	159	m_root = parentNode;
	160	}
	161	else
	162	{
	163	// Merge the branches into the parent node of what we
	164	// deleted, we let the merge algorithm decide where to
	165	// put the branches
	166	merge(replaceNode, parentNode);
	167	merge(left, parentNode);
	168	merge(right, parentNode);
	169	}
	170	}
185	171
186		// Find item x in the tree. Returns a pointer to the matching item
187		// or NULL if not found -- O(log n)
188		T* find(const T& x) const
189		{
190		tree_node* found = find(x, m_root);
191		if (found == NULL) return NULL;
192		return &found->element;
193		}
194
	172	// Balance the tree
	173	balanceTree();
195	174
196		// Is the data present in the set? -- O(log n)
197		bool contains(const T& x) const
198		{
199		if (find(x) != NULL)
200		return true;
201		else
202		return false;
203		}
	175	// The node was found and removed successfully
	176	return true;
	177	}
	178	else
	179	{
	180	// The node was not found
	181	return false;
	182	}
	183	}
204	184
205	185
206		// Merge a different tree with ours -- O(n).
207		bool merge(const simple_set<T>& b)
208		{
209		tree_node* c = b->clone();
210		bool retVal = merge(c->m_root, m_root);
	186	// Find item x in the tree. Returns a pointer to the matching item
	187	// or NULL if not found -- O(log n)
	188	T* find(const T& x) const
	189	{
	190	tree_node* found = find(x, m_root);
	191	if (found == NULL) return NULL;
	192	return &found->element;
	193	}
211	194
212		// Re-balance the tree if the merge was successful
213		if (retVal)
214		{
215		balanceTree();
216		}
217		else
218		{
219		pool_free(m_pool, c);
220		}
221	195
222		return retVal;
223		}
	196	// Is the data present in the set? -- O(log n)
	197	bool contains(const T& x) const
	198	{
	199	if (find(x) != NULL)
	200	return true;
	201	else
	202	return false;
	203	}
224	204
225	205
226		// Replace this set with another -- O(n)
227		const simple_set& operator=(const simple_set& rhs)
228		{
229		// Don't clone if it's the same pointer
230		if (this != &rhs)
231		{
232		clear();
	206	// Merge a different tree with ours -- O(n).
	207	bool merge(const simple_set<T>& b)
	208	{
	209	tree_node* c = b->clone();
	210	bool retVal = merge(c->m_root, m_root);
233	211
234		m_root = clone(rhs.m_root);
235		}
	212	// Re-balance the tree if the merge was successful
	213	if (retVal)
	214	{
	215	balanceTree();
	216	}
	217	else
	218	{
	219	pool_free(m_pool, c);
	220	}
236	221
237		return *this;
238		}
	222	return retVal;
	223	}
239	224
240	225
	226	// Replace this set with another -- O(n)
	227	const simple_set& operator=(const simple_set& rhs)
	228	{
	229	// Don't clone if it's the same pointer
	230	if (this != &rhs)
	231	{
	232	clear();
	233
	234	m_root = clone(rhs.m_root);
	235	}
	236
	237	return *this;
	238	}
	239
	240
241	241	#ifdef SIMPLE_SET_DEBUG
242		// Debug -- O(n log n)
243		void printTree(std::ostream& out = std::cout) const
244		{
245		if(empty())
246		{
247		out << "Empty tree" << std::endl;
248		}
249		else
250		{
251		printTree(out, m_root);
252		}
253		}
	242	// Debug -- O(n log n)
	243	void printTree(std::ostream& out = std::cout) const
	244	{
	245	if(empty())
	246	{
	247	out << "Empty tree" << std::endl;
	248	}
	249	else
	250	{
	251	printTree(out, m_root);
	252	}
	253	}
254	254	#endif
255	255
256	256
257	257	private:
258		// The AVL tree's root
259		tree_node* m_root;
	258	// The AVL tree's root
	259	tree_node* m_root;
260	260
261		// Resource pool where objects are freed
262		resource_pool& m_pool;
	261	// Resource pool where objects are freed
	262	resource_pool& m_pool;
263	263
264	264
265		// Find a node in the tree
266		tree_node* findNode(const T& x) const
267		{
268		tree_node* node = find(x, m_root);
269		if (node)
270		{
271		return node;
272		}
273		else
274		{
275		return NULL;
276		}
277		}
	265	// Find a node in the tree
	266	tree_node* findNode(const T& x) const
	267	{
	268	tree_node* node = find(x, m_root);
	269	if (node)
	270	{
	271	return node;
	272	}
	273	else
	274	{
	275	return NULL;
	276	}
	277	}
278	278
279	279
280		// Insert item x into a subtree t (root) -- O(log n)
281		bool insert(const T& x, tree_node*& t)
282		{
283		if (t == NULL)
284		{
285		t = pool_alloc(m_pool, tree_node(x, NULL, NULL, NULL));
	280	// Insert item x into a subtree t (root) -- O(log n)
	281	bool insert(const T& x, tree_node*& t)
	282	{
	283	if (t == NULL)
	284	{
	285	t = pool_alloc(m_pool, tree_node(x, NULL, NULL, NULL));
286	286
287		// An empty sub-tree here, insertion successful
288		return true;
289		}
290		else if (x < t->element)
291		{
292		// O(log n)
293		bool retVal = insert(x, t->left);
	287	// An empty sub-tree here, insertion successful
	288	return true;
	289	}
	290	else if (x < t->element)
	291	{
	292	// O(log n)
	293	bool retVal = insert(x, t->left);
294	294
295		if (retVal)
296		{
297		t->left->setParent(t);
298		if(t->balanceFactor() < -1)
299		{
300		// See if it went left of the left
301		if(x < t->left->element)
302		{
303		rotateWithLeftChild(t);
304		}
305		else
306		{
307		// The element goes on the right of the left
308		doubleWithLeftChild(t);
309		}
310		}
311		}
	295	if (retVal)
	296	{
	297	t->left->setParent(t);
	298	if(t->balanceFactor() < -1)
	299	{
	300	// See if it went left of the left
	301	if(x < t->left->element)
	302	{
	303	rotateWithLeftChild(t);
	304	}
	305	else
	306	{
	307	// The element goes on the right of the left
	308	doubleWithLeftChild(t);
	309	}
	310	}
	311	}
312	312
313		return retVal;
314		}
315		else if (t->element < x)
316		{
317		bool retVal = insert(x, t->right);
	313	return retVal;
	314	}
	315	else if (t->element < x)
	316	{
	317	bool retVal = insert(x, t->right);
318	318
319		// Only do this if the insertion was successful
320		if (retVal)
321		{
322		t->right->setParent(t);
	319	// Only do this if the insertion was successful
	320	if (retVal)
	321	{
	322	t->right->setParent(t);
323	323
324		if (t->balanceFactor() > 1)
325		{
326		// See if it went right of the right
327		if(t->right->element < x)
328		{
329		rotateWithRightChild(t);
330		}
331		else
332		{
333		// The element goes on the left of the right
334		doubleWithRightChild(t);
335		}
336		}
337		}
	324	if (t->balanceFactor() > 1)
	325	{
	326	// See if it went right of the right
	327	if(t->right->element < x)
	328	{
	329	rotateWithRightChild(t);
	330	}
	331	else
	332	{
	333	// The element goes on the left of the right
	334	doubleWithRightChild(t);
	335	}
	336	}
	337	}
338	338
339		return retVal;
340		}
341		else
342		{
343		return false; // Duplicate
344		}
345		}
	339	return retVal;
	340	}
	341	else
	342	{
	343	return false; // Duplicate
	344	}
	345	}
346	346
347
348		// Recursively free all nodes in the tree -- O(n).
349		void clearRecurse(tree_node*& t) const
350		{
351		if(t != NULL)
352		{
353		clearRecurse(t->left);
354		clearRecurse(t->right);
355	347
356		pool_free(m_pool, t);
357		}
358		t = NULL;
359		}
	348	// Recursively free all nodes in the tree -- O(n).
	349	void clearRecurse(tree_node*& t) const
	350	{
	351	if(t != NULL)
	352	{
	353	clearRecurse(t->left);
	354	clearRecurse(t->right);
360	355
	356	pool_free(m_pool, t);
	357	}
	358	t = NULL;
	359	}
361	360
362		// Merge a tree with this one. Private because external care is required.
363		bool merge(tree_node* b, tree_node*& t)
364		{
365		if (!b)
366		{
367		return false;
368		}
369		else
370		{
371		bool retVal = false;
372	361
373		if (t == NULL)
374		{
375		// Set this element to that subtree
376		t = b;
	362	// Merge a tree with this one. Private because external care is required.
	363	bool merge(tree_node* b, tree_node*& t)
	364	{
	365	if (!b)
	366	{
	367	return false;
	368	}
	369	else
	370	{
	371	bool retVal = false;
377	372
378		// The parent here should be NULL anyway, but we
379		// set it just to be sure. This pointer will be
380		// used as a flag to indicate where in the call
381		// stack the tree was actually set.
382		//
383		// The middle layers of this method's call will
384		// all have their parent references in tact since
385		// no operations took place there.
386		//
387		//t->parent = NULL;
388		t->setParent(NULL);
	373	if (t == NULL)
	374	{
	375	// Set this element to that subtree
	376	t = b;
389	377
390		// We were successful in merging
391		retVal = true;
392		}
393		else if (b->element < t->element)
394		{
395		retVal = merge(b, t->left);
	378	// The parent here should be NULL anyway, but we
	379	// set it just to be sure. This pointer will be
	380	// used as a flag to indicate where in the call
	381	// stack the tree was actually set.
	382	//
	383	// The middle layers of this method's call will
	384	// all have their parent references in tact since
	385	// no operations took place there.
	386	//
	387	//t->parent = NULL;
	388	t->setParent(NULL);
396	389
397		// Only do this if the insertion actually took place
398		if (retVal && !t->left->parent)
399		{
400		t->left->setParent(t);
401		}
402		}
403		else if (t->element < b->element)
404		{
405		retVal = merge(b, t->right);
	390	// We were successful in merging
	391	retVal = true;
	392	}
	393	else if (b->element < t->element)
	394	{
	395	retVal = merge(b, t->left);
406	396
407		// Only do this if the insertion was successful
408		if (retVal && !t->right->parent)
409		{
410		t->right->setParent(t);
411		}
	397	// Only do this if the insertion actually took place
	398	if (retVal && !t->left->parent)
	399	{
	400	t->left->setParent(t);
	401	}
	402	}
	403	else if (t->element < b->element)
	404	{
	405	retVal = merge(b, t->right);
412	406
413		return retVal;
414		}
	407	// Only do this if the insertion was successful
	408	if (retVal && !t->right->parent)
	409	{
	410	t->right->setParent(t);
	411	}
415	412
416		return retVal;
417		}
418		}
	413	return retVal;
	414	}
419	415
	416	return retVal;
	417	}
	418	}
420	419
421		// Find the smallest item's node in a subtree t -- O(log n).
422		tree_node* findMin(tree_node* t) const
423		{
424		if(t == NULL)
425		{
426		return t;
427		}
428	420
429		while(t->left != NULL)
430		{
431		t = t->left;
432		}
	421	// Find the smallest item's node in a subtree t -- O(log n).
	422	tree_node* findMin(tree_node* t) const
	423	{
	424	if(t == NULL)
	425	{
	426	return t;
	427	}
433	428
434		return t;
435		}
436
437
438		// Find the smallest item's node in a subtree t -- O(log n).
439		tree_node* findMax(tree_node* t) const
440		{
441		if(t == NULL)
442		{
443		return t;
444		}
	429	while(t->left != NULL)
	430	{
	431	t = t->left;
	432	}
445	433
446		while(t->right != NULL)
447		{
448		t = t->right;
449		}
	434	return t;
	435	}
450	436
451		return t;
452		}
453	437
	438	// Find the smallest item's node in a subtree t -- O(log n).
	439	tree_node* findMax(tree_node* t) const
	440	{
	441	if(t == NULL)
	442	{
	443	return t;
	444	}
454	445
455		// Find item x's node in subtree t -- O(log n)
456		tree_node* find(const T& x, tree_node* t) const
457		{
458		while(t != NULL)
459		{
460		if (x < t->element)
461		{
462		t = t->left;
463		}
464		else if (t->element < x)
465		{
466		t = t->right;
467		}
468		else
469		{
470		return t; // Match
471		}
472		}
	446	while(t->right != NULL)
	447	{
	448	t = t->right;
	449	}
473	450
474		return NULL; // No match
475		}
	451	return t;
	452	}
476	453
477	454
478		// Clone a subtree -- O(n)
479		tree_node* clone(const tree_node* t) const
480		{
481		if(t == NULL)
482		{
483		return NULL;
484		}
485		else
486		{
487		// Create a node with the left and right nodes and a parent set to NULL
488		tree_node* retVal = pool_alloc(m_pool, tree_node(t->element, NULL, clone(t->left), clone(t->right)));
	455	// Find item x's node in subtree t -- O(log n)
	456	tree_node* find(const T& x, tree_node* t) const
	457	{
	458	while(t != NULL)
	459	{
	460	if (x < t->element)
	461	{
	462	t = t->left;
	463	}
	464	else if (t->element < x)
	465	{
	466	t = t->right;
	467	}
	468	else
	469	{
	470	return t; // Match
	471	}
	472	}
489	473
490		// Now set our children's parent node reference
491		if (retVal->left) { retVal->left->setParent(retVal); }
492		if (retVal->right) { retVal->right->setParent(retVal); }
	474	return NULL; // No match
	475	}
493	476
494		return retVal;
495		}
496		}
497	477
	478	// Clone a subtree -- O(n)
	479	tree_node* clone(const tree_node* t) const
	480	{
	481	if(t == NULL)
	482	{
	483	return NULL;
	484	}
	485	else
	486	{
	487	// Create a node with the left and right nodes and a parent set to NULL
	488	tree_node* retVal = pool_alloc(m_pool, tree_node(t->element, NULL, clone(t->left), clone(t->right)));
498	489
499		// Rotate binary tree node with left child.
500		// Single rotation for case 1 -- O(1).
501		void rotateWithLeftChild(tree_node*& k2) const
502		{
503		tree_node* k1 = k2->left;
504		tree_node* k2Parent = k2->parent;
	490	// Now set our children's parent node reference
	491	if (retVal->left) { retVal->left->setParent(retVal); }
	492	if (retVal->right) { retVal->right->setParent(retVal); }
505	493
506		k2->setLeft(k1->right);
507		if (k2->left) { k2->left->setParent(k2); }
	494	return retVal;
	495	}
	496	}
508	497
509		k1->setRight(k2);
510		if (k1->right) { k1->right->setParent(k1); }
511	498
512		k2 = k1;
513		k2->setParent(k2Parent);
514		}
	499	// Rotate binary tree node with left child.
	500	// Single rotation for case 1 -- O(1).
	501	void rotateWithLeftChild(tree_node*& k2) const
	502	{
	503	tree_node* k1 = k2->left;
	504	tree_node* k2Parent = k2->parent;
515	505
516
517		// Rotate binary tree node with right child.
518		// Single rotation for case 4 -- O(1).
519		void rotateWithRightChild(tree_node*& k1) const
520		{
521		tree_node* k2 = k1->right;
522		tree_node* k1Parent = k1->parent;
	506	k2->setLeft(k1->right);
	507	if (k2->left) { k2->left->setParent(k2); }
523	508
524		k1->setRight(k2->left);
525		if (k1->right) { k1->right->setParent(k1); }
	509	k1->setRight(k2);
	510	if (k1->right) { k1->right->setParent(k1); }
526	511
527		k2->setLeft(k1);
528		if (k2->left) { k2->left->setParent(k2); }
	512	k2 = k1;
	513	k2->setParent(k2Parent);
	514	}
529	515
530		k1 = k2;
531		k1->setParent(k1Parent);
532		}
533	516
534
535		// Double rotate binary tree node: first left child
536		// with its right child; then node k3 with new left child.
537		// Double rotation for case 2 -- O(1).
538		void doubleWithLeftChild(tree_node*& k3) const
539		{
540		rotateWithRightChild(k3->left);
541		rotateWithLeftChild(k3);
542		}
	517	// Rotate binary tree node with right child.
	518	// Single rotation for case 4 -- O(1).
	519	void rotateWithRightChild(tree_node*& k1) const
	520	{
	521	tree_node* k2 = k1->right;
	522	tree_node* k1Parent = k1->parent;
543	523
544
545		// Double rotate binary tree node: first right child
546		// with its left child; then node k1 with new right child.
547		// Double rotation for case 3 -- O(1).
548		void doubleWithRightChild(tree_node*& k1) const
549		{
550		rotateWithLeftChild(k1->right);
551		rotateWithRightChild(k1);
552		}
	524	k1->setRight(k2->left);
	525	if (k1->right) { k1->right->setParent(k1); }
553	526
	527	k2->setLeft(k1);
	528	if (k2->left) { k2->left->setParent(k2); }
554	529
555		// Removes a node. Returns true if the node was on the left side of its parent -- O(1).
556		void removeNode(tree_node*& node)
557		{
558		// It is a leaf, simply remove the item and disconnect the parent
559		if (node->isLeft())
560		{
561		node->parent->setLeft(NULL);
562		}
563		else // (node == node->parent->right)
564		{
565		if (node->parent) { node->parent->setRight(NULL); }
566		}
	530	k1 = k2;
	531	k1->setParent(k1Parent);
	532	}
567	533
568		node->setParent(NULL);
569		}
570	534
	535	// Double rotate binary tree node: first left child
	536	// with its right child; then node k3 with new left child.
	537	// Double rotation for case 2 -- O(1).
	538	void doubleWithLeftChild(tree_node*& k3) const
	539	{
	540	rotateWithRightChild(k3->left);
	541	rotateWithLeftChild(k3);
	542	}
571	543
572		// Swap one node with another -- O(1).
573		void replaceNode(tree_node& node1, tree_node& node2)
574		{
575		// Save both parent references
576		simple_set<T>* node1Parent = node1->parent;
577		simple_set<T>* node2Parent = node2->parent;
578	544
579		// First move node2 into node1's place
580		if (node1Parent)
581		{
582		if (isLeft(node1))
583		{
584		node1Parent->setLeft(node2);
585		}
586		else // node1 is on the right
587		{
588		node1Parent->setRight(node2);
589		}
590		}
591		node2->setParent(node1Parent);
	545	// Double rotate binary tree node: first right child
	546	// with its left child; then node k1 with new right child.
	547	// Double rotation for case 3 -- O(1).
	548	void doubleWithRightChild(tree_node*& k1) const
	549	{
	550	rotateWithLeftChild(k1->right);
	551	rotateWithRightChild(k1);
	552	}
592	553
593		// Now move node1 into node2's place
594		if (node2Parent)
595		{
596		if (isLeft(node2))
597		{
598		node2Parent->setLeft(node1);
599		}
600		else // node2 is on the right
601		{
602		node2Parent->setRight(node1);
603		}
604		}
605		node1->setParent(node2Parent);
606		}
607	554
	555	// Removes a node. Returns true if the node was on the left side of its parent -- O(1).
	556	void removeNode(tree_node*& node)
	557	{
	558	// It is a leaf, simply remove the item and disconnect the parent
	559	if (node->isLeft())
	560	{
	561	node->parent->setLeft(NULL);
	562	}
	563	else // (node == node->parent->right)
	564	{
	565	if (node->parent) { node->parent->setRight(NULL); }
	566	}
608	567
609		// Balances the tree starting at the root node
610		void balanceTree() { balanceTree(m_root); }
	568	node->setParent(NULL);
	569	}
611	570
612	571
613		// Balance the tree starting at the given node -- O(n).
614		void balanceTree(tree_node*& node)
615		{
616		if (node)
617		{
618		// First see what the balance factor for this node is
619		int balFactor = node->balanceFactor();
	572	// Swap one node with another -- O(1).
	573	void replaceNode(tree_node& node1, tree_node& node2)
	574	{
	575	// Save both parent references
	576	simple_set<T>* node1Parent = node1->parent;
	577	simple_set<T>* node2Parent = node2->parent;
620	578
621		if (balFactor < -1)
622		{
623		// See if we're heavy left of the left
624		if(node->left->balanceFactor() < 0)
625		{
626		rotateWithLeftChild(node);
627		}
628		else // if (node->left->balanceFactor() > 0)
629		{
630		// We're heavy on the right of the left
631		doubleWithLeftChild(node);
632		}
633		}
634		else if (balFactor > 1)
635		{
636		// See if it we're heavy right of the right
637		if(node->right->balanceFactor() > 0)
638		{
639		rotateWithRightChild(node);
640		}
641		else // if (node->right->balanceFactor() < 0)
642		{
643		// The element goes on the left of the right
644		doubleWithRightChild(node);
645		}
646		}
647		else // if (balFactor >= -1 && balFactor <= 1)
648		{
649		// We're balanced here, but are our children balanced?
650		balanceTree(node->left);
651		balanceTree(node->right);
652		}
653		}
654		}
	579	// First move node2 into node1's place
	580	if (node1Parent)
	581	{
	582	if (isLeft(node1))
	583	{
	584	node1Parent->setLeft(node2);
	585	}
	586	else // node1 is on the right
	587	{
	588	node1Parent->setRight(node2);
	589	}
	590	}
	591	node2->setParent(node1Parent);
655	592
	593	// Now move node1 into node2's place
	594	if (node2Parent)
	595	{
	596	if (isLeft(node2))
	597	{
	598	node2Parent->setLeft(node1);
	599	}
	600	else // node2 is on the right
	601	{
	602	node2Parent->setRight(node1);
	603	}
	604	}
	605	node1->setParent(node2Parent);
	606	}
656	607
657		// Recursive helper function for public size()
658		int sizeRecurse(const tree_node* currentNode) const
659		{
660		int nodeCount = 1;
661		if (currentNode->left != NULL)
662		nodeCount += sizeRecurse(currentNode->left);
663		if (currentNode->right != NULL)
664		nodeCount += sizeRecurse(currentNode->right);
665		return nodeCount;
666		}
667	608
	609	// Balances the tree starting at the root node
	610	void balanceTree() { balanceTree(m_root); }
668	611
	612
	613	// Balance the tree starting at the given node -- O(n).
	614	void balanceTree(tree_node*& node)
	615	{
	616	if (node)
	617	{
	618	// First see what the balance factor for this node is
	619	int balFactor = node->balanceFactor();
	620
	621	if (balFactor < -1)
	622	{
	623	// See if we're heavy left of the left
	624	if(node->left->balanceFactor() < 0)
	625	{
	626	rotateWithLeftChild(node);
	627	}
	628	else // if (node->left->balanceFactor() > 0)
	629	{
	630	// We're heavy on the right of the left
	631	doubleWithLeftChild(node);
	632	}
	633	}
	634	else if (balFactor > 1)
	635	{
	636	// See if it we're heavy right of the right
	637	if(node->right->balanceFactor() > 0)
	638	{
	639	rotateWithRightChild(node);
	640	}
	641	else // if (node->right->balanceFactor() < 0)
	642	{
	643	// The element goes on the left of the right
	644	doubleWithRightChild(node);
	645	}
	646	}
	647	else // if (balFactor >= -1 && balFactor <= 1)
	648	{
	649	// We're balanced here, but are our children balanced?
	650	balanceTree(node->left);
	651	balanceTree(node->right);
	652	}
	653	}
	654	}
	655
	656
	657	// Recursive helper function for public size()
	658	int sizeRecurse(const tree_node* currentNode) const
	659	{
	660	int nodeCount = 1;
	661	if (currentNode->left != NULL)
	662	nodeCount += sizeRecurse(currentNode->left);
	663	if (currentNode->right != NULL)
	664	nodeCount += sizeRecurse(currentNode->right);
	665	return nodeCount;
	666	}
	667
	668
669	669	#ifdef SIMPLE_SET_DEBUG
670		// Debug. Print from the start node, down -- O(n log n).
671		void printTree(std::ostream& out, tree_node* t=NULL, int numTabs=0, char lr='_') const
672		{
673		if(t != NULL)
674		{
675		for (int i =0; i < numTabs; i++) { out << " "; } out << "\|_" << lr << "__ ";
676		out << t->element << " {h = " << t->height() << ", b = " << t->balanceFactor() << "} ";
677		// TODO: Reinstate out << std::hex << t << " (p = " << t->parent << ")" << std::dec;
678		out << std::endl;
	670	// Debug. Print from the start node, down -- O(n log n).
	671	void printTree(std::ostream& out, tree_node* t=NULL, int numTabs=0, char lr='_') const
	672	{
	673	if(t != NULL)
	674	{
	675	for (int i =0; i < numTabs; i++) { out << " "; } out << "\|_" << lr << "__ ";
	676	out << t->element << " {h = " << t->height() << ", b = " << t->balanceFactor() << "} ";
	677	// TODO: Reinstate out << std::hex << t << " (p = " << t->parent << ")" << std::dec;
	678	out << std::endl;
679	679
680		printTree(out, t->left, numTabs + 1, '<');
681		printTree(out, t->right, numTabs + 1, '>');
682		}
683		}
	680	printTree(out, t->left, numTabs + 1, '<');
	681	printTree(out, t->right, numTabs + 1, '>');
	682	}
	683	}
684	684	#endif
685	685	};
686	686
r22615	r22616
692	692
693	693	template <class T> class avl_tree_node
694	694	{
695		friend class simple_set<T>;
696		friend class simple_set_iterator<T>;
697		typedef avl_tree_node<T> tree_node;
	695	friend class simple_set<T>;
	696	friend class simple_set_iterator<T>;
	697	typedef avl_tree_node<T> tree_node;
698	698
699	699	public:
700		// Construction
701		avl_tree_node(const T& theElement, avl_tree_node* p, avl_tree_node* lt, avl_tree_node* rt)
702		: element(theElement),
703		parent(p),
704		left(lt),
705		right(rt),
706		m_height(1),
707		m_balanceFactor(0)
708		{ }
	700	// Construction
	701	avl_tree_node(const T& theElement, avl_tree_node* p, avl_tree_node* lt, avl_tree_node* rt)
	702	: element(theElement),
	703	parent(p),
	704	left(lt),
	705	right(rt),
	706	m_height(1),
	707	m_balanceFactor(0)
	708	{ }
709	709
710	710
711		// Are we to our parent's left?
712		bool isLeft()
713		{
714		if (parent && this == parent->left)
715		{
716		return true;
717		}
718		else
719		{
720		return false;
721		}
722		}
	711	// Are we to our parent's left?
	712	bool isLeft()
	713	{
	714	if (parent && this == parent->left)
	715	{
	716	return true;
	717	}
	718	else
	719	{
	720	return false;
	721	}
	722	}
723	723
724	724
725		// Are we a leaf node?
726		bool isLeaf() { return !left && !right; }
	725	// Are we a leaf node?
	726	bool isLeaf() { return !left && !right; }
727	727
728	728
729		// Set the parent pointer
730		void setParent(tree_node* p)
731		{
732		// Set our new parent
733		parent = p;
	729	// Set the parent pointer
	730	void setParent(tree_node* p)
	731	{
	732	// Set our new parent
	733	parent = p;
734	734
735		// If we have a valid parent, set its height
736		if (parent)
737		{
738		// Set the parent's height to include this tree. If the parent
739		// already has a tree that is taller than the one we're attaching
740		// then the parent's height remains unchanged
741		int rightHeight = (parent->right ? parent->right->m_height : 0);
742		int leftHeight = (parent->left ? parent->left->m_height : 0);
	735	// If we have a valid parent, set its height
	736	if (parent)
	737	{
	738	// Set the parent's height to include this tree. If the parent
	739	// already has a tree that is taller than the one we're attaching
	740	// then the parent's height remains unchanged
	741	int rightHeight = (parent->right ? parent->right->m_height : 0);
	742	int leftHeight = (parent->left ? parent->left->m_height : 0);
743	743
744		// The height of the tallest branch + 1
745		parent->m_height = maxInt(rightHeight, leftHeight) + 1;
	744	// The height of the tallest branch + 1
	745	parent->m_height = maxInt(rightHeight, leftHeight) + 1;
746	746
747		// Also set the balance factor
748		parent->m_balanceFactor = rightHeight - leftHeight;
749		}
750		}
	747	// Also set the balance factor
	748	parent->m_balanceFactor = rightHeight - leftHeight;
	749	}
	750	}
751	751
752	752
753		// Set the left child pointer
754		void setLeft(tree_node* l)
755		{
756		// Set our new left node
757		left = l;
	753	// Set the left child pointer
	754	void setLeft(tree_node* l)
	755	{
	756	// Set our new left node
	757	left = l;
758	758
759		// Set the height and balance factor
760		int rightHeight = (right ? right->m_height : 0);
761		int leftHeight = (left ? left->m_height : 0);
	759	// Set the height and balance factor
	760	int rightHeight = (right ? right->m_height : 0);
	761	int leftHeight = (left ? left->m_height : 0);
762	762
763		m_height = maxInt(rightHeight, leftHeight) + 1;
764		m_balanceFactor = (right ? right->m_height : 0) - (left ? left->m_height : 0);
765		}
766
	763	m_height = maxInt(rightHeight, leftHeight) + 1;
	764	m_balanceFactor = (right ? right->m_height : 0) - (left ? left->m_height : 0);
	765	}
767	766
768		// Set the right child pointer
769		void setRight(tree_node* r)
770		{
771		// Set our new right node
772		right = r;
773	767
774		// Set the height and balance factor
775		int rightHeight = (right ? right->m_height : 0);
776		int leftHeight = (left ? left->m_height : 0);
	768	// Set the right child pointer
	769	void setRight(tree_node* r)
	770	{
	771	// Set our new right node
	772	right = r;
777	773
778		m_height = maxInt(rightHeight, leftHeight) + 1;
779		m_balanceFactor = (right ? right->m_height : 0) - (left ? left->m_height : 0);
780		}
	774	// Set the height and balance factor
	775	int rightHeight = (right ? right->m_height : 0);
	776	int leftHeight = (left ? left->m_height : 0);
781	777
	778	m_height = maxInt(rightHeight, leftHeight) + 1;
	779	m_balanceFactor = (right ? right->m_height : 0) - (left ? left->m_height : 0);
	780	}
782	781
783		// Recover the height
784		int height() const
785		{
786		// The height is equal to the maximum of the right or left side's height plus 1
787		// Trading memory for operation time can be done O(n) like this =>
788		// return max(left ? left->height() : 0, right ? right->height() : 0) + 1;
789		return m_height;
790		}
791	782
	783	// Recover the height
	784	int height() const
	785	{
	786	// The height is equal to the maximum of the right or left side's height plus 1
	787	// Trading memory for operation time can be done O(n) like this =>
	788	// return max(left ? left->height() : 0, right ? right->height() : 0) + 1;
	789	return m_height;
	790	}
792	791
793		// Recover the balance factor
794		int balanceFactor() const
795		{
796		// The weight of a node is equal to the difference between
797		// the weight of the left subtree and the weight of the
798		// right subtree
799		//
800		// O(n) version =>
801		// return (right ? right->height() : 0) - (left ? left->height() : 0);
802		//
803		return m_balanceFactor;
804		}
805	792
	793	// Recover the balance factor
	794	int balanceFactor() const
	795	{
	796	// The weight of a node is equal to the difference between
	797	// the weight of the left subtree and the weight of the
	798	// right subtree
	799	//
	800	// O(n) version =>
	801	// return (right ? right->height() : 0) - (left ? left->height() : 0);
	802	//
	803	return m_balanceFactor;
	804	}
806	805
	806
807	807	private:
808		// Calculates all of the heights for this node and its ancestors -- O(log n).
809		void calcHeights()
810		{
811		// Calculate our own height -- O(1)
812		m_height = maxInt(left ? left->m_height : 0, right ? right->m_height : 0) + 1;
	808	// Calculates all of the heights for this node and its ancestors -- O(log n).
	809	void calcHeights()
	810	{
	811	// Calculate our own height -- O(1)
	812	m_height = maxInt(left ? left->m_height : 0, right ? right->m_height : 0) + 1;
813	813
814		// And our parent's height (and recurse) -- O(log n)
815		if (parent)
816		{
817		parent->calcHeights();
818		}
819		}
	814	// And our parent's height (and recurse) -- O(log n)
	815	if (parent)
	816	{
	817	parent->calcHeights();
	818	}
	819	}
820	820
821	821
822		// Utility function - TODO replace
823		int maxInt(const int& lhs, const int& rhs) const
824		{
825		return lhs > rhs ? lhs : rhs;
826		}
	822	// Utility function - TODO replace
	823	int maxInt(const int& lhs, const int& rhs) const
	824	{
	825	return lhs > rhs ? lhs : rhs;
	826	}
827	827
828	828
829	829	private:
830		T element;
	830	T element;
831	831
832		avl_tree_node* parent;
833		avl_tree_node* left;
834		avl_tree_node* right;
	832	avl_tree_node* parent;
	833	avl_tree_node* left;
	834	avl_tree_node* right;
835	835
836		int m_height;
837		int m_balanceFactor;
	836	int m_height;
	837	int m_balanceFactor;
838	838	};
839	839
840	840
r22615	r22616
850	850	template <class T>
851	851	class simple_set_iterator
852	852	{
853		typedef avl_tree_node<T> tree_node;
	853	typedef avl_tree_node<T> tree_node;
854	854
855	855	public:
856		enum TraversalType { PRE_ORDER, IN_ORDER, POST_ORDER, LEVEL_ORDER };
	856	enum TraversalType { PRE_ORDER, IN_ORDER, POST_ORDER, LEVEL_ORDER };
857	857
858	858	public:
859		// construction
860		simple_set_iterator(simple_set<T>& set, const TraversalType& tt=IN_ORDER)
861		: m_set(&set),
862		m_traversalType(tt),
863		m_currentNode(NULL),
864		m_endNode(NULL) { }
	859	// construction
	860	simple_set_iterator(simple_set<T>& set, const TraversalType& tt=IN_ORDER)
	861	: m_set(&set),
	862	m_traversalType(tt),
	863	m_currentNode(NULL),
	864	m_endNode(NULL) { }
865	865
866		~simple_set_iterator() { }
	866	~simple_set_iterator() { }
867	867
868
869		// getters
870		T* current() const { return m_currentNode; }
871	868
	869	// getters
	870	T* current() const { return m_currentNode; }
872	871
873		// reset and return first item
874		T* first()
875		{
876		m_currentNode = m_set->m_root;
877		switch (m_traversalType)
878		{
879		case IN_ORDER:
880		{
881		// The current node is the smallest value
882		m_currentNode = m_set->findMin(m_set->m_root);
883
884		// The end case is the largest value
885		m_endNode = m_set->findMax(m_set->m_root);
886
887		return &m_currentNode->element;
888		}
889	872
890		default:
891		{
892		// TODO (better error message):
893		printf("simple_set_iterator: Traversal type not yet supported.\n");
894		return NULL;
895		}
896		}
897		return NULL;
898		}
	873	// reset and return first item
	874	T* first()
	875	{
	876	m_currentNode = m_set->m_root;
	877	switch (m_traversalType)
	878	{
	879	case IN_ORDER:
	880	{
	881	// The current node is the smallest value
	882	m_currentNode = m_set->findMin(m_set->m_root);
899	883
900
901		T* last()
902		{
903		return NULL;
904		}
	884	// The end case is the largest value
	885	m_endNode = m_set->findMax(m_set->m_root);
905	886
	887	return &m_currentNode->element;
	888	}
906	889
907		// advance according to current state and traversal type
908		T* next()
909		{
910		if (m_currentNode == NULL) return NULL;
911
912		switch (m_traversalType)
913		{
914		case IN_ORDER:
915		{
916		// You are at the end
917		if (m_currentNode == m_endNode)
918		return NULL;
919
920		if (m_currentNode->right != NULL)
921		{
922		// Gather the furthest left node of right subtree
923		m_currentNode = m_currentNode->right;
924		while (m_currentNode->left != NULL)
925		{
926		m_currentNode = m_currentNode->left;
927		}
928		}
929		else
930		{
931		// No right subtree? Move up the tree, looking for a left child link.
932		tree_node* p = m_currentNode->parent;
933		while (p != NULL && m_currentNode == p->right)
934		{
935		m_currentNode = p;
936		p = p->parent;
937		}
938		m_currentNode = p;
939		}
940
941		return &m_currentNode->element;
942		}
	890	default:
	891	{
	892	// TODO (better error message):
	893	printf("simple_set_iterator: Traversal type not yet supported.\n");
	894	return NULL;
	895	}
	896	}
	897	return NULL;
	898	}
943	899
944		default:
945		{
946		// TODO (better error message):
947		printf("simple_set_iterator: Traversal type not yet supported.\n");
948		return NULL;
949		}
950		}
951
952		return NULL;
953		}
954	900
	901	T* last()
	902	{
	903	return NULL;
	904	}
955	905
956		// return the number of items available
957		int count()
958		{
959		return m_set->size();
960		}
961	906
	907	// advance according to current state and traversal type
	908	T* next()
	909	{
	910	if (m_currentNode == NULL) return NULL;
962	911
963		// return the index of a given item in the virtual list
964		// note: this function is destructive to any in-progress iterations!
965		int indexof(T inData)
966		{
967		int index = 0;
968		for (T* data = first(); data != last(); data = next(), index++)
969		if (!(data < inData) && !(inData < data))
970		return index;
971		return -1;
972		}
	912	switch (m_traversalType)
	913	{
	914	case IN_ORDER:
	915	{
	916	// You are at the end
	917	if (m_currentNode == m_endNode)
	918	return NULL;
973	919
	920	if (m_currentNode->right != NULL)
	921	{
	922	// Gather the furthest left node of right subtree
	923	m_currentNode = m_currentNode->right;
	924	while (m_currentNode->left != NULL)
	925	{
	926	m_currentNode = m_currentNode->left;
	927	}
	928	}
	929	else
	930	{
	931	// No right subtree? Move up the tree, looking for a left child link.
	932	tree_node* p = m_currentNode->parent;
	933	while (p != NULL && m_currentNode == p->right)
	934	{
	935	m_currentNode = p;
	936	p = p->parent;
	937	}
	938	m_currentNode = p;
	939	}
974	940
975		// return the indexed item in the list
976		// note: this function is destructive to any in-progress iterations!
977		T* byindex(int index)
978		{
979		int count = 0;
980		for (T* data = first(); data != last(); data = next(), count++)
981		if (count == index)
982		return data;
983		return NULL;
984		}
	941	return &m_currentNode->element;
	942	}
985	943
	944	default:
	945	{
	946	// TODO (better error message):
	947	printf("simple_set_iterator: Traversal type not yet supported.\n");
	948	return NULL;
	949	}
	950	}
986	951
	952	return NULL;
	953	}
	954
	955
	956	// return the number of items available
	957	int count()
	958	{
	959	return m_set->size();
	960	}
	961
	962
	963	// return the index of a given item in the virtual list
	964	// note: this function is destructive to any in-progress iterations!
	965	int indexof(T inData)
	966	{
	967	int index = 0;
	968	for (T* data = first(); data != last(); data = next(), index++)
	969	if (!(data < inData) && !(inData < data))
	970	return index;
	971	return -1;
	972	}
	973
	974
	975	// return the indexed item in the list
	976	// note: this function is destructive to any in-progress iterations!
	977	T* byindex(int index)
	978	{
	979	int count = 0;
	980	for (T* data = first(); data != last(); data = next(), count++)
	981	if (count == index)
	982	return data;
	983	return NULL;
	984	}
	985
	986
987	987	private:
988		simple_set<T>* m_set;
	988	simple_set<T>* m_set;
989	989
990		TraversalType m_traversalType;
991		tree_node* m_currentNode;
992		tree_node* m_endNode;
	990	TraversalType m_traversalType;
	991	tree_node* m_currentNode;
	992	tree_node* m_endNode;
993	993	};
994	994
995	995	#endif

trunk/src/emu/video/voodoo.c
r22615	r22616
1033	1033	{
1034	1034	if (LOG_VBLANK_SWAP) logerror("---- vblank flush begin\n");
1035	1035	flush_fifos(v, machine.time());
1036		if (LOG_VBLANK_SWAP) logerror("---- vblank flush end\n");
	1036	if (LOG_VBLANK_SWAP) logerror("---- vblank flush end\n");
1037	1037	}
1038	1038
1039	1039	/* increment the count */

trunk/src/emu/video/voodoo.h
r22615	r22616
74	74	UINT8 tmumem1;
75	75	const char * screen;
76	76	const char * cputag;
77		devcb_write_line vblank;
	77	devcb_write_line vblank;
78	78	devcb_write_line stall;
79	79	};
80	80

trunk/src/emu/video/psx.c
r22615	r22616
1347	1347	n_leftpoint = n_point; \
1348	1348	} \
1349	1349	} \
1350		n_rightpoint = n_leftpoint; \
1351
	1350	n_rightpoint = n_leftpoint;
1352	1351	void psxgpu_device::FlatPolygon( int n_points )
1353	1352	{
1354	1353	INT16 n_y;

trunk/src/emu/video/dl1416.c
r22615	r22616
127	127	static DEVICE_START( dl1416 )
128	128	{
129	129	dl1416_state *dl1416 = get_safe_token(device);
130
	130
131	131	/* register for state saving */
132	132	state_save_register_item(device->machine(), "dl1416", device->tag(), 0, dl1416->chip_enable);
133	133	state_save_register_item(device->machine(), "dl1416", device->tag(), 0, dl1416->cursor_enable);

trunk/src/emu/sound/spu.c
r22615	r22616
2488	2488	m_cd_out_ptr=(m_cd_out_ptr+2)&0x3ff;
2489	2489
2490	2490	//if((m_cd_out_ptr == ((spureg.irq_addr << 3) & ~0x400)) && (spureg.ctrl & spuctrl_irq_enable))
2491		// m_irq_handler(1);
	2491	// m_irq_handler(1);
2492	2492
2493	2493	dp[0]=clamp(dp[0]+vl);
2494	2494	dp[1]=clamp(dp[1]+vr);

trunk/src/emu/emu.mak
r22615	r22616
251	251	$(EMUMACHINE)/pc16552d.o \
252	252	$(EMUMACHINE)/pcf8593.o \
253	253	$(EMUMACHINE)/pci.o \
254		$(EMUMACHINE)/pckeybrd.o \
	254	$(EMUMACHINE)/pckeybrd.o \
255	255	$(EMUMACHINE)/pd4990a.o \
256	256	$(EMUMACHINE)/pic8259.o \
257	257	$(EMUMACHINE)/pit8253.o \

trunk/src/emu/machine/6850acia.h
r22615	r22616
173	173	serial_state m_rx_state;
174	174	serial_state m_tx_state;
175	175	int m_irq;
176		bool m_dcd_triggered;
	176	bool m_dcd_triggered;
177	177
178	178	emu_timer *m_rx_timer;
179	179	emu_timer *m_tx_timer;

trunk/src/emu/machine/s3c2440.h
r22615	r22616
970	970	devcb_resolved_write8 command_w;
971	971	devcb_resolved_write8 address_w;
972	972	devcb_resolved_read8 nand_data_r;
973		devcb_resolved_write8 nand_data_w;
	973	devcb_resolved_write8 nand_data_w;
974	974	};
975	975
976	976	#endif

trunk/src/emu/machine/mcf5206e.c
r22615	r22616
30	30
31	31	void mcf5206e_peripheral_device::device_config_complete()
32	32	{
33
34	33	}
35	34
36	35
r22615	r22616
40	39
41	40	void mcf5206e_peripheral_device::device_start()
42	41	{
43
44	42	}
45	43
46	44
r22615	r22616
52	50
53	51	WRITE32_MEMBER(mcf5206e_peripheral_device::dev_w)
54	52	{
55
56	53	}
57	54
58	55
r22615	r22616
86	83
87	84	ADDRESS REG WIDTH NAME/DESCRIPTION INIT VALUE (MR=Master Reset, NR=Normal Reset) Read or Write access
88	85
89		op MOVEC with $C0F MBAR 32 Module Base Address Register uninit (except V=0) W
90		$003 SIMR 8 SIM Configuration Register C0 R/W
91		$014 ICR1 8 Interrupt Control Register 1 - External IRQ1/IPL1 04 R/W
92		$015 ICR2 8 Interrupt Control Register 2 - External IPL2 08 R/W
93		$016 ICR3 8 Interrupt Control Register 3 - External IPL3 0C R/W
94		$017 ICR4 8 Interrupt Control Register 4 - External IRQ4/IPL4 10 R/W
95		$018 ICR5 8 Interrupt Control Register 5 - External IPL5 14 R/W
96		$019 ICR6 8 Interrupt Control Register 6 - External IPL6 18 R/W
97		$01A ICR7 8 Interrupt Control Register 7 - External IRQ7/IPL7 1C R/W
98		$01B ICR8 8 Interrupt Control Register 8 - SWT 1C R/W
99		$01C ICR9 8 Interrupt Control Register 9 - Timer 1 Interrupt 80 R/W
100		$01D ICR10 8 Interrupt Control Register 10 - Timer 2 Interrupt 80 R/W
101		$01E ICR11 8 Interrupt Control Register 11 - MBUS Interrupt 80 R/W
102		$01F ICR12 8 Interrupt Control Register 12 - UART 1 Interrupt 00 R/W
103		$020 ICR13 8 Interrupt Control Register 13 - UART 2 Interrupt 00 R/W
104		$036 IMR 16 Interrupt Mask Register 3FFE R/W
105		$03A IPR 16 Interrupt Pending Register 0000 R
106		$040 RSR 8 Reset Status Register 80 / 20 R/W
107		$041 SYPCR 8 System Protection Control Register 00 R/W
108		$042 SWIVR 8 Software Watchdog Interrupt Vector Register 0F R/W
109		$043 SWSR 8 Software Watchdog Service Register uninit W
110		$046 DCRR 16 DRAM Controller Refresh MR 0000 - NR uninit R/W
111		$04A DCTR 16 DRAM Controller Timing Register MR 0000 - NR uninit R/W
112		$04C DCAR0 16 DRAM Controller 0 Address Register MR uninit - NR uninit R/W
113		$050 DCMR0 32 DRAM Controller 0 Mask Register MR uninit - NR uninit R/W
114		$057 DCCR0 8 DRAM Controller 0 Control Register MR 00 - NR 00 R/W
115		$058 DCAR1 16 DRAM Controller 1 Address Register MR uninit - NR uninit R/W
116		$05C DCMR1 32 DRAM Controller 1 Mask Register MR uninit - NR uninit R/W
117		$063 DCCR1 8 DRAM Controller 1 Control Register MR 00 - NR 00 R/W
	86	op MOVEC with $C0F MBAR 32 Module Base Address Register uninit (except V=0) W
	87	$003 SIMR 8 SIM Configuration Register C0 R/W
	88	$014 ICR1 8 Interrupt Control Register 1 - External IRQ1/IPL1 04 R/W
	89	$015 ICR2 8 Interrupt Control Register 2 - External IPL2 08 R/W
	90	$016 ICR3 8 Interrupt Control Register 3 - External IPL3 0C R/W
	91	$017 ICR4 8 Interrupt Control Register 4 - External IRQ4/IPL4 10 R/W
	92	$018 ICR5 8 Interrupt Control Register 5 - External IPL5 14 R/W
	93	$019 ICR6 8 Interrupt Control Register 6 - External IPL6 18 R/W
	94	$01A ICR7 8 Interrupt Control Register 7 - External IRQ7/IPL7 1C R/W
	95	$01B ICR8 8 Interrupt Control Register 8 - SWT 1C R/W
	96	$01C ICR9 8 Interrupt Control Register 9 - Timer 1 Interrupt 80 R/W
	97	$01D ICR10 8 Interrupt Control Register 10 - Timer 2 Interrupt 80 R/W
	98	$01E ICR11 8 Interrupt Control Register 11 - MBUS Interrupt 80 R/W
	99	$01F ICR12 8 Interrupt Control Register 12 - UART 1 Interrupt 00 R/W
	100	$020 ICR13 8 Interrupt Control Register 13 - UART 2 Interrupt 00 R/W
	101	$036 IMR 16 Interrupt Mask Register 3FFE R/W
	102	$03A IPR 16 Interrupt Pending Register 0000 R
	103	$040 RSR 8 Reset Status Register 80 / 20 R/W
	104	$041 SYPCR 8 System Protection Control Register 00 R/W
	105	$042 SWIVR 8 Software Watchdog Interrupt Vector Register 0F R/W
	106	$043 SWSR 8 Software Watchdog Service Register uninit W
	107	$046 DCRR 16 DRAM Controller Refresh MR 0000 - NR uninit R/W
	108	$04A DCTR 16 DRAM Controller Timing Register MR 0000 - NR uninit R/W
	109	$04C DCAR0 16 DRAM Controller 0 Address Register MR uninit - NR uninit R/W
	110	$050 DCMR0 32 DRAM Controller 0 Mask Register MR uninit - NR uninit R/W
	111	$057 DCCR0 8 DRAM Controller 0 Control Register MR 00 - NR 00 R/W
	112	$058 DCAR1 16 DRAM Controller 1 Address Register MR uninit - NR uninit R/W
	113	$05C DCMR1 32 DRAM Controller 1 Mask Register MR uninit - NR uninit R/W
	114	$063 DCCR1 8 DRAM Controller 1 Control Register MR 00 - NR 00 R/W
118	115	--------- CHIP SELECTS -----------
119		$064 CSAR0 16 Chip-Select 0 Address Register 0000 R/W
120		$068 CSMR0 32 Chip-Select 0 Mask Register 00000000 R/W
121		$06E CSCR0 16 Chip-Select 0 Control Register 3C1F, 3C5F, 3C9F, 3CDF, 3D1F, 3D5F, 3D9F, 3DDF R/W
122		AA set by IRQ 7 at reset
123		PS1 set by IRQ 4 at reset
124		PS0 set by IRQ 1 at reset
125		$070 CSAR1 16 Chip-Select 1 Address Register uninit R/W
126		$074 CSMR1 32 Chip-Select 1 Mask Register uninit R/W
127		$07A CSCR1 16 Chip-Select 1 Control Register uninit *1 R/W
128		$07C CSAR2 16 Chip-Select 2 Address Register uninit R/W
129		$080 CSMR2 32 Chip-Select 2 Mask Register uninit R/W
130		$086 CSCR2 16 Chip-Select 2 Control Register uninit *1 R/W
131		$088 CSAR3 16 Chip-Select 3 Address Register uninit R/W
132		$08C CSMR3 32 Chip-Select 3 Mask Register uninit R/W
133		$092 CSCR3 16 Chip-Select 3 Control Register uninit *1 R/W
134		$094 CSAR4 16 Chip-Select 4 Address Register uninit R/W
135		$098 CSMR4 32 Chip-Select 4 Mask Register uninit R/W
136		$09E CSCR4 16 Chip-Select 4 Control Register uninit *1 R/W
137		$0A0 CSAR5 16 Chip-Select 5 Address Register uninit R/W
138		$0A4 CSMR5 32 Chip-Select 5 Mask Register uninit R/W
139		$0AA CSCR5 16 Chip-Select 5 Control Register uninit *1 R/W
140		$0AC CSAR6 16 Chip-Select 6 Address Register uninit R/W
141		$0B0 CSMR6 32 Chip-Select 6 Mask Register uninit R/W
142		$0B6 CSCR6 16 Chip-Select 6 Control Register uninit *1 R/W
143		$0B8 CSAR7 16 Chip-Select 7 Address Register uninit R/W
144		$0BC CSMR7 32 Chip-Select 7 Mask Register uninit R/W
145		$0C2 CSCR7 16 Chip-Select 7 Control Register uninit *1 R/W
146		$0C6 DMCR 16 Default Memory Control Register 0000 R/W
147		$0CA PAR 16 Pin Assignment Register 00 R/W
	116	$064 CSAR0 16 Chip-Select 0 Address Register 0000 R/W
	117	$068 CSMR0 32 Chip-Select 0 Mask Register 00000000 R/W
	118	$06E CSCR0 16 Chip-Select 0 Control Register 3C1F, 3C5F, 3C9F, 3CDF, 3D1F, 3D5F, 3D9F, 3DDF R/W
	119	AA set by IRQ 7 at reset
	120	PS1 set by IRQ 4 at reset
	121	PS0 set by IRQ 1 at reset
	122	$070 CSAR1 16 Chip-Select 1 Address Register uninit R/W
	123	$074 CSMR1 32 Chip-Select 1 Mask Register uninit R/W
	124	$07A CSCR1 16 Chip-Select 1 Control Register uninit *1 R/W
	125	$07C CSAR2 16 Chip-Select 2 Address Register uninit R/W
	126	$080 CSMR2 32 Chip-Select 2 Mask Register uninit R/W
	127	$086 CSCR2 16 Chip-Select 2 Control Register uninit *1 R/W
	128	$088 CSAR3 16 Chip-Select 3 Address Register uninit R/W
	129	$08C CSMR3 32 Chip-Select 3 Mask Register uninit R/W
	130	$092 CSCR3 16 Chip-Select 3 Control Register uninit *1 R/W
	131	$094 CSAR4 16 Chip-Select 4 Address Register uninit R/W
	132	$098 CSMR4 32 Chip-Select 4 Mask Register uninit R/W
	133	$09E CSCR4 16 Chip-Select 4 Control Register uninit *1 R/W
	134	$0A0 CSAR5 16 Chip-Select 5 Address Register uninit R/W
	135	$0A4 CSMR5 32 Chip-Select 5 Mask Register uninit R/W
	136	$0AA CSCR5 16 Chip-Select 5 Control Register uninit *1 R/W
	137	$0AC CSAR6 16 Chip-Select 6 Address Register uninit R/W
	138	$0B0 CSMR6 32 Chip-Select 6 Mask Register uninit R/W
	139	$0B6 CSCR6 16 Chip-Select 6 Control Register uninit *1 R/W
	140	$0B8 CSAR7 16 Chip-Select 7 Address Register uninit R/W
	141	$0BC CSMR7 32 Chip-Select 7 Mask Register uninit R/W
	142	$0C2 CSCR7 16 Chip-Select 7 Control Register uninit *1 R/W
	143	$0C6 DMCR 16 Default Memory Control Register 0000 R/W
	144	$0CA PAR 16 Pin Assignment Register 00 R/W
148	145	--------- TIMER MODULE -----------
149		$100 TMR1 16 Timer 1 Mode Register 0000 R/W
150		$104 TRR1 16 Timer 1 Reference Register FFFF R/W
151		$108 TCR1 16 Timer 1 Capture Register 0000 R
152		$10C TCN1 16 Timer 1 Counter 0000 R/W
153		$111 TER1 8 Timer 1 Event Register 00 R/W
154		$120 TMR2 16 Timer 2 Mode Register 0000 R/W
155		$124 TRR2 16 Timer 2 Reference Register FFFF R/W
156		$128 TCR2 16 Timer 2 Capture Register 0000 R
157		$12C TCN2 16 Timer 2 Counter 0000 R/W
158		$131 TER2 8 Timer 2 Event Register 00 R/W
	146	$100 TMR1 16 Timer 1 Mode Register 0000 R/W
	147	$104 TRR1 16 Timer 1 Reference Register FFFF R/W
	148	$108 TCR1 16 Timer 1 Capture Register 0000 R
	149	$10C TCN1 16 Timer 1 Counter 0000 R/W
	150	$111 TER1 8 Timer 1 Event Register 00 R/W
	151	$120 TMR2 16 Timer 2 Mode Register 0000 R/W
	152	$124 TRR2 16 Timer 2 Reference Register FFFF R/W
	153	$128 TCR2 16 Timer 2 Capture Register 0000 R
	154	$12C TCN2 16 Timer 2 Counter 0000 R/W
	155	$131 TER2 8 Timer 2 Event Register 00 R/W
159	156	------------ UART SERIAL PORTS -----------
160		$140 UMR1,2 8 UART 1 Mode Registers 00 R/W
161		$144 USR 8 UART 1 Status Register 00 R
162		UCSR 8 UART 1 Clock-Select Register DD W
163		$148 UCR 8 UART 1 Command Register 00 W
164		$14C URB 8 UART 1 Receive Buffer FF R
165		UTB 8 UART 1 Transmit Buffer 00 W
166		$150 UIPCR 8 UART Input Port Change Register 0F R
167		UACR 8 UART 1 Auxilary Control Register 00 W
168		$154 UISR 8 UART 1 Interrupt Status Register 00 R
169		UIMR 8 UART 1 Interrupt Mask Register 00 W
170		$158 UBG1 8 UART 1 Baud Rate Generator Prescale MSB uninit W
171		$15C UBG2 8 UART 1 Baud Rate Generator Prescale LSB uninit W
172		$170 UIVR 8 UART 1 Interrupt Vector Register 0F R/W
173		$174 UIP 8 UART 1 Input Port Register FF R
174		$178 UOP1 8 UART 1 Output Port Bit Set CMD UOP1[7-1]=undef; UOP1=0 W
175		$17C UOP0 8 UART 1 Output Port Bit Reset CMD uninit W
	157	$140 UMR1,2 8 UART 1 Mode Registers 00 R/W
	158	$144 USR 8 UART 1 Status Register 00 R
	159	UCSR 8 UART 1 Clock-Select Register DD W
	160	$148 UCR 8 UART 1 Command Register 00 W
	161	$14C URB 8 UART 1 Receive Buffer FF R
	162	UTB 8 UART 1 Transmit Buffer 00 W
	163	$150 UIPCR 8 UART Input Port Change Register 0F R
	164	UACR 8 UART 1 Auxilary Control Register 00 W
	165	$154 UISR 8 UART 1 Interrupt Status Register 00 R
	166	UIMR 8 UART 1 Interrupt Mask Register 00 W
	167	$158 UBG1 8 UART 1 Baud Rate Generator Prescale MSB uninit W
	168	$15C UBG2 8 UART 1 Baud Rate Generator Prescale LSB uninit W
	169	$170 UIVR 8 UART 1 Interrupt Vector Register 0F R/W
	170	$174 UIP 8 UART 1 Input Port Register FF R
	171	$178 UOP1 8 UART 1 Output Port Bit Set CMD UOP1[7-1]=undef; UOP1=0 W
	172	$17C UOP0 8 UART 1 Output Port Bit Reset CMD uninit W
176	173
177		$180 UMR1,2 8 UART 2 Mode Registers 00 R/W
178		$184 USR 8 UART 2 Status Register 00 R
179		UCSR 8 UART 2 Clock-Select Register DD W
180		$188 UCR 8 UART 2 Command Register 00 W
181		$18C URB 8 UART 2 Receive Buffer FF R
182		UTB 8 UART 2 Transmit Buffer 00 W
183		$190 UIPCR 8 UART 2 Input Port Change Register 0F R
184		UACR 8 UART 2 Auxilary Control Register 00 W
185		$194 UISR 8 UART 2 Interrupt Status Register 00 R
186		UIMR 8 UART 2 Interrupt Mask Register 00 W
187		$198 UBG1 8 UART 2 Baud Rate Generator Prescale MSB uninit R/W
188		$19C UBG2 8 UART 2 Barud Rate Generator Prescale LSB uninit R/W
189		$1B0 UIVR 8 UART 2 Interrupt Vector Register 0F R/W
190		$1B4 UIP 8 UART 2 Input Port Register FF R
191		$1B8 UOP1 8 UART 2 Output Port Bit Set CMD UOP1[7-1]=undef; UOP1=0 W
192		$1BC UOP0 8 UART 2 Output Port Bit Reset CMD uninit W
	174	$180 UMR1,2 8 UART 2 Mode Registers 00 R/W
	175	$184 USR 8 UART 2 Status Register 00 R
	176	UCSR 8 UART 2 Clock-Select Register DD W
	177	$188 UCR 8 UART 2 Command Register 00 W
	178	$18C URB 8 UART 2 Receive Buffer FF R
	179	UTB 8 UART 2 Transmit Buffer 00 W
	180	$190 UIPCR 8 UART 2 Input Port Change Register 0F R
	181	UACR 8 UART 2 Auxilary Control Register 00 W
	182	$194 UISR 8 UART 2 Interrupt Status Register 00 R
	183	UIMR 8 UART 2 Interrupt Mask Register 00 W
	184	$198 UBG1 8 UART 2 Baud Rate Generator Prescale MSB uninit R/W
	185	$19C UBG2 8 UART 2 Barud Rate Generator Prescale LSB uninit R/W
	186	$1B0 UIVR 8 UART 2 Interrupt Vector Register 0F R/W
	187	$1B4 UIP 8 UART 2 Input Port Register FF R
	188	$1B8 UOP1 8 UART 2 Output Port Bit Set CMD UOP1[7-1]=undef; UOP1=0 W
	189	$1BC UOP0 8 UART 2 Output Port Bit Reset CMD uninit W
193	190
194		$1C5 PPDDR 8 Port A Data Direction Register 00 R/W
195		$1C9 PPDAT 8 Port A Data Register 00 R/W
	191	$1C5 PPDDR 8 Port A Data Direction Register 00 R/W
	192	$1C9 PPDAT 8 Port A Data Register 00 R/W
196	193	------------ MBUS -----------
197		$1E0 MADR 8 M-Bus Address Register 00 R/W
198		$1E4 MFDR 8 M-Bus Frequency Divider Register 00 R/W
199		$1E8 MBCR 8 M-Bus Control Register 00 R/W
200		$1EC MBSR 8 M-Bus Status Register 00 R/W
201		$1F0 MBDR 8 M-Bus Data I/O Register 00 R/W
	194	$1E0 MADR 8 M-Bus Address Register 00 R/W
	195	$1E4 MFDR 8 M-Bus Frequency Divider Register 00 R/W
	196	$1E8 MBCR 8 M-Bus Control Register 00 R/W
	197	$1EC MBSR 8 M-Bus Status Register 00 R/W
	198	$1F0 MBDR 8 M-Bus Data I/O Register 00 R/W
202	199	------------ DMA Controller -----------
203		$200 DMASAR0 32 Source Address Register 0 00 R/W
204		$204 DMADAR0 32 Destination Address Register 0 00 R/W
205		$208 DCR0 16 DMA Control Register 0 00 R/W
206		$20C BCR0 16 Byte Count Register 0 00 R/W
207		$210 DSR0 8 Status Register 0 00 R/W
208		$214 DIVR0 8 Interrupt Vector Register 0 0F R/W
209		$240 DMASAR1 32 Source Address Register 1 00 R/W
210		$244 DMADAR1 32 Destination Address Register 1 00 R/W
211		$248 DCR1 16 DMA Control Register 1 00 R/W
212		$24C BCR1 16 Byte Count Register 1 00 R/W
213		$250 DSR1 8 Status Register 1 00 R/W
214		$254 DIVR1 8 Interrupt Vector Register 1 0F R/W
	200	$200 DMASAR0 32 Source Address Register 0 00 R/W
	201	$204 DMADAR0 32 Destination Address Register 0 00 R/W
	202	$208 DCR0 16 DMA Control Register 0 00 R/W
	203	$20C BCR0 16 Byte Count Register 0 00 R/W
	204	$210 DSR0 8 Status Register 0 00 R/W
	205	$214 DIVR0 8 Interrupt Vector Register 0 0F R/W
	206	$240 DMASAR1 32 Source Address Register 1 00 R/W
	207	$244 DMADAR1 32 Destination Address Register 1 00 R/W
	208	$248 DCR1 16 DMA Control Register 1 00 R/W
	209	$24C BCR1 16 Byte Count Register 1 00 R/W
	210	$250 DSR1 8 Status Register 1 00 R/W
	211	$254 DIVR1 8 Interrupt Vector Register 1 0F R/W
215	212
216	213	*1 - uninit except BRST=ASET=WRAH=RDAH=WR=RD=0
217	214
218		*/
		No newline at end of file
	215	*/

trunk/src/emu/machine/mcf5206e.h
r22615	r22616
18	18	***************************************************************************/
19	19
20	20	#define MCFG_MCF5206E_PERIPHERAL_ADD(_tag) \
21		MCFG_DEVICE_ADD(_tag, MCF5206E_PERIPHERAL, 0) \
	21	MCFG_DEVICE_ADD(_tag, MCF5206E_PERIPHERAL, 0)
22	22
23
24	23	/***************************************************************************
25	24	TYPE DEFINITIONS
26	25	***************************************************************************/

trunk/src/emu/machine/s3c2400.h
r22615	r22616
753	753	devcb_resolved_write8 address_w;
754	754	devcb_resolved_read8 nand_data_r;
755	755	devcb_resolved_write8 nand_data_w;
756
	756
757	757	};
758	758
759	759	#endif

trunk/src/emu/machine/8042kbdc.c
r22615	r22616
225	225	memset(&m_gate_a20_cb, 0, sizeof(m_gate_a20_cb));
226	226	memset(&m_input_buffer_full_func, 0, sizeof(m_input_buffer_full_func));
227	227	memset(&m_output_buffer_empty_cb, 0, sizeof(m_output_buffer_empty_cb));
228		memset(&m_speaker_cb, 0, sizeof(m_speaker_cb));
	228	memset(&m_speaker_cb, 0, sizeof(m_speaker_cb));
229	229	}
230	230	}
231	231

trunk/src/emu/machine/8042kbdc.h
r22615	r22616
34	34
35	35	struct kbdc8042_interface
36	36	{
37		kbdc8042_type_t m_keybtype;
	37	kbdc8042_type_t m_keybtype;
38	38	// interface to the host pc
39	39	devcb_write_line m_system_reset_cb;
40	40	devcb_write_line m_gate_a20_cb;
41	41	devcb_write_line m_input_buffer_full_cb;
42	42	devcb_write_line m_output_buffer_empty_cb;
43
44		devcb_write8 m_speaker_cb;
45		devcb_read8 m_getout2_cb;
	43
	44	devcb_write8 m_speaker_cb;
	45	devcb_read8 m_getout2_cb;
46	46	};
47	47
48		// ======================> kbdc8042_device
	48	// ======================> kbdc8042_device
49	49
50	50	class kbdc8042_device : public device_t,
51	51	public kbdc8042_interface
r22615	r22616
53	53	public:
54	54	// construction/destruction
55	55	kbdc8042_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
56
	56
57	57	DECLARE_READ8_MEMBER( data_r );
58	58	DECLARE_WRITE8_MEMBER( data_w );
59	59
r22615	r22616
68	68	virtual void device_start();
69	69	virtual void device_reset();
70	70	virtual void device_config_complete();
71
	71
72	72	UINT8 m_inport, m_outport, m_data, m_command;
73	73
74	74	struct {
r22615	r22616
93	93	int m_offset1;
94	94
95	95	int m_poll_delay;
96
	96
97	97	devcb_resolved_write_line m_system_reset_func;
98	98	devcb_resolved_write_line m_gate_a20_func;
99	99	devcb_resolved_write_line m_input_buffer_full_func;
100	100	devcb_resolved_write_line m_output_buffer_empty_func;
101
102		devcb_resolved_write8 m_speaker_func;
103		devcb_resolved_read8 m_getout2_func;
	101
	102	devcb_resolved_write8 m_speaker_func;
	103	devcb_resolved_read8 m_getout2_func;
104	104	};
105	105
106	106	// device type definition

trunk/src/emu/machine/s3c2410.h
r22615	r22616
900	900	devcb_resolved_write8 address_w;
901	901	devcb_resolved_read8 nand_data_r;
902	902	devcb_resolved_write8 nand_data_w;
903
	903
904	904	};
905	905
906	906	#endif

trunk/src/emu/debug/debugcpu.c
r22615	r22616
2672	2672
2673	2673	const char *device_debug::comment_text(offs_t addr) const
2674	2674	{
2675		const UINT32 crc = compute_opcode_crc32(addr);
	2675	const UINT32 crc = compute_opcode_crc32(addr);
2676	2676	dasm_comment* comment = m_comment_set.find(dasm_comment(addr, crc, "", 0));
2677	2677	if (comment == NULL) return NULL;
2678	2678	return comment->m_text;
r22615	r22616
3523	3523
3524	3524	device_debug::dasm_pc_tag::dasm_pc_tag(const offs_t& address, const UINT32& crc)
3525	3525	: m_address(address),
3526		m_crc(crc)
	3526	m_crc(crc)
3527	3527	{
3528	3528	}
3529	3529
r22615	r22616
3533	3533
3534	3534	device_debug::dasm_comment::dasm_comment(offs_t address, UINT32 crc, const char *text, rgb_t color)
3535	3535	: dasm_pc_tag(address, crc),
3536		m_text(text),
3537		m_color(color)
	3536	m_text(text),
	3537	m_color(color)
3538	3538	{
3539	3539	}

trunk/src/emu/cpu/psx/gte.c
r22615	r22616
296	296	{
297	297	FLAG \|= max_flag;
298	298	}
299
	299
300	300	if( value.negative_overflow() )
301	301	{
302	302	FLAG \|= min_flag;

trunk/src/emu/cpu/z8000/z8000.h
r22615	r22616
38	38
39	39	/* possible values for z8k_segm_mode */
40	40	#define Z8K_SEGM_MODE_NONSEG 0
41		#define Z8K_SEGM_MODE_SEG 1
42		#define Z8K_SEGM_MODE_AUTO 2
	41	#define Z8K_SEGM_MODE_SEG 1
	42	#define Z8K_SEGM_MODE_AUTO 2
43	43
44	44	#endif /* __Z8000_H__ */

trunk/src/emu/cpu/z8000/8000dasm.c
r22615	r22616
81	81	"", "vi", "nvi", "vi,nvi"
82	82	};
83	83
84		int z8k_segm; /* Current disassembler mode: 0 - non-segmented, 1 - segmented */
85		int z8k_segm_mode = Z8K_SEGM_MODE_AUTO; /* User disassembler mode setting: segmented, non-segmented, auto */
	84	int z8k_segm; /* Current disassembler mode: 0 - non-segmented, 1 - segmented */
	85	int z8k_segm_mode = Z8K_SEGM_MODE_AUTO; /* User disassembler mode setting: segmented, non-segmented, auto */
86	86
87	87	void z8k_disass_mode(running_machine &machine, int ref, int params, const char *param[])
88	88	{

trunk/src/mess/machine/s3c44b0.c
r22615	r22616
2011	2011	s3c44b0->sda_w.resolve(s3c44b0->iface->i2c.sda_w, *device);
2012	2012	s3c44b0->adc_data_r.resolve(s3c44b0->iface->adc.data_r, *device);
2013	2013	s3c44b0->i2s_data_w.resolve(s3c44b0->iface->i2s.data_w, *device);
2014
2015
	2014
	2015
2016	2016	s3c44b0->space = &space;
2017	2017	s3c44b0->cpu = downcast<cpu_device *>(device->machine().device( "maincpu"));
2018	2018	for (int i = 0; i < 6; i++) s3c44b0->pwm.timer[i] = machine.scheduler().timer_alloc(FUNC(s3c44b0_pwm_timer_exp), (void*)device);

trunk/src/mess/machine/apple2gs.c
r22615	r22616
1793	1793	WRITE8_MEMBER( apple2gs_state::apple2gs_E12xxx_w ) { apple2gs_Exxxxx_w(space, offset + 0x12000, data, mem_mask); }
1794	1794
1795	1795	WRITE8_MEMBER( apple2gs_state::apple2gs_slowmem_w )
1796		{
	1796	{
1797	1797	m_slowmem[offset] = data;
1798	1798
1799	1799	if ((offset >= 0x19e00) && (offset < 0x19fff))
r22615	r22616
1810	1810	// Because the bank address multiplexes on the 65816 data bus, reading a memory area
1811	1811	// which doesn't drive the bus results in reading back the bank number.
1812	1812	READ8_MEMBER(apple2gs_state::apple2gs_bank_echo_r)
1813		{
	1813	{
1814	1814	return m_echo_bank + (offset>>16);
1815	1815	}
1816	1816

trunk/src/mess/machine/vtech2.c
r22615	r22616
332	332	}
333	333
334	334	device_t *vtech2_state::laser_file()
335		{
	335	{
336	336	return machine().device(m_laser_drive ? FLOPPY_1 : FLOPPY_0);
337	337	}
338	338

trunk/src/mess/machine/cgenie.c
r22615	r22616
171	171	#define FF_BGD (FF_BGD0 \| FF_BGD1 \| FF_BGD2)
172	172
173	173	WRITE8_MEMBER( cgenie_state::cgenie_port_ff_w )
174		{
	174	{
175	175	int port_ff_changed = m_port_ff ^ data;
176	176
177	177	m_cassette->output(data & 0x01 ? -1.0 : 1.0 );
r22615	r22616
243	243
244	244
245	245	READ8_MEMBER( cgenie_state::cgenie_port_ff_r )
246		{
	246	{
247	247	UINT8 data = m_port_ff & ~0x01;
248	248
249	249	data \|= m_cass_bit;
r22615	r22616
264	264
265	265
266	266	READ8_MEMBER( cgenie_state::cgenie_psg_port_a_r )
267		{
	267	{
268	268	return m_psg_a_inp;
269	269	}
270	270
271	271	READ8_MEMBER( cgenie_state::cgenie_psg_port_b_r )
272		{
	272	{
273	273	if( m_psg_a_out < 0xd0 )
274	274	{
275	275	/* comparator value */
r22615	r22616
314	314	}
315	315
316	316	WRITE8_MEMBER( cgenie_state::cgenie_psg_port_a_w )
317		{
	317	{
318	318	m_psg_a_out = data;
319	319	}
320	320
r22615	r22616
396	396	}
397	397
398	398	READ8_MEMBER( cgenie_state::cgenie_irq_status_r )
399		{
	399	{
400	400	int result = m_irq_status;
401	401
402	402	m_irq_status &= ~(IRQ_TIMER \| IRQ_FDC);
r22615	r22616
441	441	};
442	442
443	443	WRITE8_MEMBER( cgenie_state::cgenie_motor_w )
444		{
	444	{
445	445	device_t *fdc = machine().device("wd179x");
446	446	UINT8 drive = 255;
447	447
r22615	r22616
514	514	}
515	515
516	516	WRITE8_MEMBER( cgenie_state::cgenie_videoram_w )
517		{
	517	{
518	518	UINT8 *videoram = m_videoram;
519	519	/* write to video RAM */
520	520	if( data == videoram[offset] )
r22615	r22616
528	528	}
529	529
530	530	WRITE8_MEMBER( cgenie_state::cgenie_colorram_w )
531		{
	531	{
532	532	/* only bits 0 to 3 */
533	533	data &= 15;
534	534	/* nothing changed ? */
r22615	r22616
542	542	}
543	543
544	544	READ8_MEMBER( cgenie_state::cgenie_fontram_r )
545		{
	545	{
546	546	return m_fontram[offset];
547	547	}
548	548
549	549	WRITE8_MEMBER( cgenie_state::cgenie_fontram_w )
550		{
	550	{
551	551	UINT8 *dp;
552	552
553	553	if( data == m_fontram[offset] )

trunk/src/mess/machine/pc.c
r22615	r22616
1407	1407	m_pc_keyb_int_cb = set_keyb_int_func;
1408	1408	m_pc_keyb_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(pc_state::pc_keyb_timer),this));
1409	1409	}
1410
	1410
1411	1411	void pc_state::mess_init_pc_common(void (*set_keyb_int_func)(running_machine &, int))
1412	1412	{
1413	1413	if ( set_keyb_int_func != NULL )
r22615	r22616
1530	1530	{
1531	1531	pc_int_delay_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(pc_state::pcjr_delayed_pic8259_irq),this));
1532	1532	m_pcjr_watchdog = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(pc_state::pcjr_fdc_watchdog),this));
1533		pcjr_keyb.keyb_signal_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(pc_state::pcjr_keyb_signal_callback),this));
	1533	pcjr_keyb.keyb_signal_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(pc_state::pcjr_keyb_signal_callback),this));
1534	1534	m_maincpu->set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(pc_state::pc_irq_callback),this));
1535	1535
1536	1536	machine().device<upd765a_device>("upd765")->set_ready_line_connected(false);
r22615	r22616
1838	1838	m_turbo_cur_val = -1;
1839	1839	m_turbo_off_speed = off_speed;
1840	1840	m_turbo_on_speed = on_speed;
1841		machine().scheduler().timer_pulse(attotime::from_msec(100), timer_expired_delegate(FUNC(pc_state::pc_turbo_callback),this));
	1841	machine().scheduler().timer_pulse(attotime::from_msec(100), timer_expired_delegate(FUNC(pc_state::pc_turbo_callback),this));
1842	1842	}

trunk/src/mess/machine/nes_sachen.c
r22615	r22616
21	21	* Sachen 8259 [mapper 141 (A), 138 (B), 139 (C), 137 (D)]
22	22
23	23	Known issues on specific mappers:
24
	24
25	25	* 133 Qi Wang starts with corrupted graphics (ingame seems better)
26	26
27	27

trunk/src/mess/machine/nes_namcot.c
r22615	r22616
147	147	common_start();
148	148	irq_timer = timer_alloc(TIMER_IRQ);
149	149	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
150
	150
151	151	save_item(NAME(m_irq_enable));
152	152	save_item(NAME(m_irq_count));
153	153
r22615	r22616
175	175	common_start();
176	176	irq_timer = timer_alloc(TIMER_IRQ);
177	177	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
178
	178
179	179	save_item(NAME(m_irq_enable));
180	180	save_item(NAME(m_irq_count));
181	181	save_item(NAME(m_wram_enable));
r22615	r22616
205	205	common_start();
206	206	irq_timer = timer_alloc(TIMER_IRQ);
207	207	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
208
	208
209	209	save_item(NAME(m_irq_enable));
210	210	save_item(NAME(m_irq_count));
211	211	save_item(NAME(m_wram_protect));
r22615	r22616
408	408	{
409	409	if (m_irq_enable)
410	410	{
411		if (m_irq_count == 0x7fff) // counter does not wrap to 0!
	411	if (m_irq_count == 0x7fff) // counter does not wrap to 0!
412	412	machine().device("maincpu")->execute().set_input_line(M6502_IRQ_LINE, ASSERT_LINE);
413	413	else
414	414	m_irq_count++;

trunk/src/mess/machine/nes_slot.c
r22615	r22616
1	1	/***********************************************************************************************************
2
3
	2
	3
4	4	Nintendo NES/FC cart emulation
5	5	(through slot devices)
6	6
r22615	r22616
9	9	0x6000-0x7fff to read_m/write_m (here are usually installed NVRAM & WRAM, if any)
10	10	0x8000-0xffff to write_h (reads are directed to 4 x 8K PRG banks)
11	11	Default implementations of these handlers are available here, to be rewritten by PCB-specific ones when needed.
12
	12
13	13	Additional handlers are available, but have to be manually installed at machine_start
14	14	* read_ex/write_ex for address range 0x4020-0x40ff
15	15	* read_h for address range 0x8000-0xffff when a cart does some protection or address scramble before reading ROM
r22615	r22616
21	21
22	22	Plus a few of latch functions are available: ppu_latch (see MMC2), hblank_irq and scanline_irq (see e.g. MMC3),
23	23	but these might be subject to future changes when the PPU is revisited.
24
	24
25	25	Notes:
26		- Differently from later systems (like SNES or MD), it is uncommon to find PRG ROMs of NES games which are not a
	26	- Differently from later systems (like SNES or MD), it is uncommon to find PRG ROMs of NES games which are not a
27	27	power of 2K, so we do not perform any mirroring by default.
28		A bunch of pcb types, though, come with 1.5MB of PRG (some Waixing translations) or with multiple PRG chips
29		having peculiar size (32K + 16K, 32K + 8K, 32K + 2K). Hence, if such a configuration is detected, we provide
30		a m_prg_bank_map array to handle internally PRG mirroring up to the next power of 2K, as long as the size is
31		a multiple of 8K (i.e. the unit chunk for standard PRG).
32		For the case of PRG chips which are not-multiple of 8K (e.g. UNL-MARIO2-MALEE pcb), the handling has to be
	28	A bunch of pcb types, though, come with 1.5MB of PRG (some Waixing translations) or with multiple PRG chips
	29	having peculiar size (32K + 16K, 32K + 8K, 32K + 2K). Hence, if such a configuration is detected, we provide
	30	a m_prg_bank_map array to handle internally PRG mirroring up to the next power of 2K, as long as the size is
	31	a multiple of 8K (i.e. the unit chunk for standard PRG).
	32	For the case of PRG chips which are not-multiple of 8K (e.g. UNL-MARIO2-MALEE pcb), the handling has to be
33	33	handled in the pcb-specific code!
34	34	- Our open bus emulation is very sketchy, by simply returning the higher 8bits of the accessed address. This seems
35	35	enough for most games (only two sets have issues with this). A slightly better implementation is almost ready
36	36	to fix these two remaining cases, but I plan to revisit the whole implementation in an accurate way at a later
37	37	stage
38	38	- Bus conflict is implemented based on latest tests by Blargg. There is some uncertainty about AxROM behavior
39		(some AOROM pcbs suffers from bus conflict, some do not... since no AOROM game is known to glitch due to lack
	39	(some AOROM pcbs suffers from bus conflict, some do not... since no AOROM game is known to glitch due to lack
40	40	of bus conflict it seems safe to emulate the board without bus conflict, but eventually it would be good to
41	41	differentiate the real variants)
42	42
r22615	r22616
44	44	Many information about the mappers/pcbs come from the wonderful doc written by Disch.
45	45	Current info (when used) are based on v0.6.1 of his docs.
46	46	You can find the latest version of the doc at http://www.romhacking.net/docs/362/
47
48		A lot of details have been based on the researches carried on at NesDev forums (by Blargg, Quietust and many more)
	47
	48	A lot of details have been based on the researches carried on at NesDev forums (by Blargg, Quietust and many more)
49	49	and collected on the NesDev Wiki http://wiki.nesdev.com/
50
	50
51	51	Particular thanks go to
52	52	- Martin Freij for his work on NEStopia
53	53	- Cah4e3 for his efforts on FCEUMM and the reverse engineering of pirate boards
54	54	- BootGod, lidnariq and naruko for the PCB tests which made possible
55	55
56
	56
57	57	***********************************************************************************************************/
58	58
59	59	/*****************************************************************************************
60
	60
61	61	A few Mappers suffer of hardware conflict: original dumpers have used the same mapper number for more than
62	62	a kind of boards. In these cases (and only in these cases) we exploit nes.hsi to set up accordingly
63	63	emulation. Games which requires this hack are the following:
r22615	r22616
69	69	* 113 - HES 6-in-1 requires mirroring (check Bookyman playfield), while other games break with this (check AV Soccer)
70	70	* 153 - Famicom Jump II uses a different board (or the same in a very different way)
71	71	* 242 - DQ8 has no mirroring (missing graphics is due to other reasons though)
72
	72
73	73	crc_hacks have been added also to handle a few wiring settings which would require submappers:
74	74	* CHR protection pins for mapper 185
75	75	* VRC-2, VRC-4 and VRC-6 line wiring
76
	76
77	77	Remember that the MMC # does not equal the mapper #. In particular, Mapper 4 is
78	78	in fact MMC3, Mapper 9 is MMC2 and Mapper 10 is MMC4. Makes perfect sense, right?
79
	79
80	80	****************************************************************************************/
81	81
82	82
r22615	r22616
170	170
171	171	m_prg_mask = ((m_prg_chunks << 1) - 1);
172	172
173		// printf("first mask %x!\n", m_prg_mask);
	173	// printf("first mask %x!\n", m_prg_mask);
174	174	if ((m_prg_chunks << 1) & m_prg_mask)
175	175	{
176	176	int mask_bits = 0, temp = (m_prg_chunks << 1), mapsize;
177	177	// contrary to what happens with later systems, like e.g. SNES or MD,
178	178	// only half a dozen of NES carts have PRG which is not a power of 2
179	179	// so we use this bank_map only as an exception
180		// printf("uneven rom!\n");
	180	// printf("uneven rom!\n");
181	181
182	182	// 1. redefine mask as (next power of 2)-1
183	183	for (; temp; )
r22615	r22616
186	186	temp >>= 1;
187	187	}
188	188	m_prg_mask = (1 << mask_bits) - 1;
189		// printf("new mask %x!\n", m_prg_mask);
	189	// printf("new mask %x!\n", m_prg_mask);
190	190	mapsize = (1 << mask_bits)/2;
191	191
192	192	// 2. create a bank_map for banks in the range mask/2 -> mask
r22615	r22616
196	196	int j;
197	197	for (j = mapsize; j < (m_prg_chunks << 1); j++)
198	198	m_prg_bank_map[j - mapsize] = j;
199
	199
200	200	while (j % mapsize)
201	201	{
202	202	int k = 0, repeat_banks;
r22615	r22616
207	207	m_prg_bank_map[(j - mapsize) + l] = m_prg_bank_map[(j - mapsize) + l - repeat_banks];
208	208	j += repeat_banks;
209	209	}
210
	210
211	211	// check bank map!
212		// for (int i = 0; i < mapsize; i++)
213		// {
214		// printf("bank %3d = %3d\t", i, m_prg_bank_map[i]);
215		// if ((i%8) == 7)
216		// printf("\n");
217		// }
	212	// for (int i = 0; i < mapsize; i++)
	213	// {
	214	// printf("bank %3d = %3d\t", i, m_prg_bank_map[i]);
	215	// if ((i%8) == 7)
	216	// printf("\n");
	217	// }
218	218	}
219	219	}
220	220	}
r22615	r22616
275	275	return bank_8k;
276	276
277	277	// case 2: otherwise return a mirror using the bank_map!
278		// UINT8 temp = bank_8k;
	278	// UINT8 temp = bank_8k;
279	279	bank_8k &= m_prg_mask;
280	280	bank_8k -= (m_prg_mask/2 + 1);
281		// printf("bank: accessed %x (top: %x), returned %x\n", temp, (m_prg_chunks << 1) - 1, m_prg_bank_map[bank_8k]);
	281	// printf("bank: accessed %x (top: %x), returned %x\n", temp, (m_prg_chunks << 1) - 1, m_prg_bank_map[bank_8k]);
282	282	return m_prg_bank_map[bank_8k];
283	283	}
284	284
r22615	r22616
289	289	assert(prg_bank >= 0);
290	290	assert(prg_bank < ARRAY_LENGTH(m_prg_bank));
291	291	assert(prg_bank < ARRAY_LENGTH(m_prg_bank_mem));
292
	292
293	293	m_prg_bank_mem[prg_bank]->set_entry(m_prg_bank[prg_bank]);
294	294	}
295	295	}
r22615	r22616
299	299	/* if there is only 16k PRG, return */
300	300	if (!(m_prg_chunks >> 1))
301	301	return;
302
	302
303	303	/* assumes that bank references a 32k chunk */
304	304	bank = prg_8k_bank_num(bank * 4);
305	305
r22615	r22616
314	314	{
315	315	/* assumes that bank references a 16k chunk */
316	316	bank = prg_8k_bank_num(bank * 2);
317
	317
318	318	m_prg_bank[0] = bank + 0;
319	319	m_prg_bank[1] = bank + 1;
320	320	update_prg_banks(0, 1);
r22615	r22616
324	324	{
325	325	/* assumes that bank references a 16k chunk */
326	326	bank = prg_8k_bank_num(bank * 2);
327
	327
328	328	m_prg_bank[2] = bank + 0;
329	329	m_prg_bank[3] = bank + 1;
330	330	update_prg_banks(2, 3);
r22615	r22616
334	334	{
335	335	/* assumes that bank references an 8k chunk */
336	336	bank = prg_8k_bank_num(bank);
337
	337
338	338	m_prg_bank[0] = bank;
339	339	update_prg_banks(0, 0);
340	340	}
r22615	r22616
343	343	{
344	344	/* assumes that bank references an 8k chunk */
345	345	bank = prg_8k_bank_num(bank);
346
	346
347	347	m_prg_bank[1] = bank;
348	348	update_prg_banks(1, 1);
349	349	}
r22615	r22616
352	352	{
353	353	/* assumes that bank references an 8k chunk */
354	354	bank = prg_8k_bank_num(bank);
355
	355
356	356	m_prg_bank[2] = bank;
357	357	update_prg_banks(2, 2);
358	358	}
r22615	r22616
361	361	{
362	362	/* assumes that bank references an 8k chunk */
363	363	bank = prg_8k_bank_num(bank);
364
	364
365	365	m_prg_bank[3] = bank;
366	366	update_prg_banks(3, 3);
367	367	}
r22615	r22616
370	370	void device_nes_cart_interface::prg8_x(int start, int bank)
371	371	{
372	372	assert(start < 4);
373
	373
374	374	/* assumes that bank references an 8k chunk */
375	375	bank = prg_8k_bank_num(bank);
376
	376
377	377	m_prg_bank[start] = bank;
378	378	update_prg_banks(start, start);
379	379	}
r22615	r22616
386	386	{
387	387	if (source == CHRRAM && m_vram == NULL)
388	388	fatalerror("CHRRAM bankswitch with no VRAM\n");
389
	389
390	390	if (source == CHRROM && m_vrom == NULL)
391	391	fatalerror("CHRROM bankswitch with no VROM\n");
392	392	}
r22615	r22616
394	394	void device_nes_cart_interface::chr8(int bank, int source)
395	395	{
396	396	chr_sanity_check(source);
397
	397
398	398	if (source == CHRRAM)
399	399	{
400	400	bank &= (m_vram_chunks - 1);
r22615	r22616
420	420	void device_nes_cart_interface::chr4_x(int start, int bank, int source)
421	421	{
422	422	chr_sanity_check(source);
423
	423
424	424	if (source == CHRRAM)
425	425	{
426	426	bank &= ((m_vram_chunks << 1) - 1);
r22615	r22616
446	446	void device_nes_cart_interface::chr2_x(int start, int bank, int source)
447	447	{
448	448	chr_sanity_check(source);
449
	449
450	450	if (source == CHRRAM)
451	451	{
452	452	bank &= ((m_vram_chunks << 2) - 1);
r22615	r22616
472	472	void device_nes_cart_interface::chr1_x(int start, int bank, int source)
473	473	{
474	474	chr_sanity_check(source);
475
	475
476	476	if (source == CHRRAM)
477	477	{
478	478	bank &= ((m_vram_chunks << 3) - 1);
r22615	r22616
517	517	base_ptr = m_ciram;
518	518	break;
519	519	}
520
	520
521	521	page &= 3; /* mask down to the 4 logical pages */
522	522	m_nt_src[page] = source;
523
	523
524	524	if (base_ptr != NULL)
525	525	{
526	526	m_nt_orig[page] = bank * 0x400;
527	527	m_nt_access[page] = base_ptr + m_nt_orig[page];
528	528	}
529
	529
530	530	m_nt_writable[page] = writable;
531	531	}
532	532
r22615	r22616
541	541	set_nt_page(2, CIRAM, 0, 1);
542	542	set_nt_page(3, CIRAM, 1, 1);
543	543	break;
544
	544
545	545	case PPU_MIRROR_HORZ:
546	546	set_nt_page(0, CIRAM, 0, 1);
547	547	set_nt_page(1, CIRAM, 0, 1);
548	548	set_nt_page(2, CIRAM, 1, 1);
549	549	set_nt_page(3, CIRAM, 1, 1);
550	550	break;
551
	551
552	552	case PPU_MIRROR_HIGH:
553	553	set_nt_page(0, CIRAM, 1, 1);
554	554	set_nt_page(1, CIRAM, 1, 1);
555	555	set_nt_page(2, CIRAM, 1, 1);
556	556	set_nt_page(3, CIRAM, 1, 1);
557	557	break;
558
	558
559	559	case PPU_MIRROR_LOW:
560	560	set_nt_page(0, CIRAM, 0, 1);
561	561	set_nt_page(1, CIRAM, 0, 1);
r22615	r22616
570	570	set_nt_page(2, CART_NTRAM, 2, 1);
571	571	set_nt_page(3, CART_NTRAM, 3, 1);
572	572	break;
573
	573
574	574	case PPU_MIRROR_NONE:
575	575	default:
576	576	set_nt_page(0, CIRAM, 0, 1);
r22615	r22616
596	596
597	597	// Helper function for the few mappers subject to bus conflict at write.
598	598	// Tests by blargg showed that in many of the boards suffering of CPU/ROM
599		// conflicts the behaviour can be accurately emulated by writing not the
	599	// conflicts the behaviour can be accurately emulated by writing not the
600	600	// original data, but data & rom[offset]
601	601	UINT8 device_nes_cart_interface::account_bus_conflict(UINT32 offset, UINT8 data)
602	602	{
r22615	r22616
604	604	// so we allow to set m_bus_conflict to FALSE at loading time when necessary
605	605	if (m_bus_conflict)
606	606	return data & hi_access_rom(offset);
607		else
	607	else
608	608	return data;
609	609	}
610	610
r22615	r22616
616	616	WRITE8_MEMBER(device_nes_cart_interface::chr_w)
617	617	{
618	618	int bank = offset >> 10;
619
	619
620	620	if (m_chr_src[bank] == CHRRAM)
621	621	m_chr_access[bank][offset & 0x3ff] = data;
622	622	}
r22615	r22616
631	631	WRITE8_MEMBER(device_nes_cart_interface::nt_w)
632	632	{
633	633	int page = ((offset & 0xc00) >> 10);
634
	634
635	635	if (!m_nt_writable[page])
636	636	return;
637
	637
638	638	m_nt_access[page][offset & 0x3ff] = data;
639	639	}
640	640
r22615	r22616
649	649	// Base memory accessors (emulating open bus
650	650	// behaviour and/or WRAM accesses)
651	651	// Open bus emulation is defective, but it should
652		// be enough for the few cases known to rely on
	652	// be enough for the few cases known to rely on
653	653	// this (more in the comments at the top of the
654	654	// source)
655	655	//-------------------------------------------------
656	656
657		READ8_MEMBER(device_nes_cart_interface::read_l)
658		{
659		return ((offset + 0x4100) & 0xff00) >> 8; // open bus
	657	READ8_MEMBER(device_nes_cart_interface::read_l)
	658	{
	659	return ((offset + 0x4100) & 0xff00) >> 8; // open bus
660	660	}
661	661
662		READ8_MEMBER(device_nes_cart_interface::read_m)
663		{
	662	READ8_MEMBER(device_nes_cart_interface::read_m)
	663	{
664	664	if (m_battery)
665	665	return m_battery[offset & (m_battery_size - 1)];
666	666	if (m_prgram)
667	667	return m_prgram[offset & (m_prgram_size - 1)];
668
669		return ((offset + 0x6000) & 0xff00) >> 8; // open bus
	668
	669	return ((offset + 0x6000) & 0xff00) >> 8; // open bus
670	670	}
671	671
672		WRITE8_MEMBER(device_nes_cart_interface::write_l)
673		{
	672	WRITE8_MEMBER(device_nes_cart_interface::write_l)
	673	{
674	674	}
675	675
676		WRITE8_MEMBER(device_nes_cart_interface::write_m)
677		{
	676	WRITE8_MEMBER(device_nes_cart_interface::write_m)
	677	{
678	678	if (m_battery)
679	679	m_battery[offset & (m_battery_size - 1)] = data;
680	680	if (m_prgram)
681	681	m_prgram[offset & (m_prgram_size - 1)] = data;
682	682	}
683	683
684		WRITE8_MEMBER(device_nes_cart_interface::write_h)
685		{
	684	WRITE8_MEMBER(device_nes_cart_interface::write_h)
	685	{
686	686	}
687	687
688	688
r22615	r22616
743	743	m_prg_bank_mem[i]->set_entry(i);
744	744	m_prg_bank[i] = i;
745	745	}
746
	746
747	747	// Setup CHR
748	748	m_chr_source = m_vrom_chunks ? CHRROM : CHRRAM;
749	749	chr8(0, m_chr_source);
750
	750
751	751	// Setup NT
752	752	m_ciram = ciram_ptr;
753	753
r22615	r22616
846	846
847	847
848	848	/*-------------------------------------------------
849
	849
850	850	Load from xml list and identify the required slot device
851
	851
852	852	-------------------------------------------------*/
853	853
854	854	/* Include emulation of NES PCBs for softlist */
r22615	r22616
856	856
857	857
858	858	/*-------------------------------------------------
859
	859
860	860	Load .unf files (UNIF boards) and identify the required slot device
861
	861
862	862	-------------------------------------------------*/
863	863
864	864	/* Include emulation of UNIF Boards for .unf files */
r22615	r22616
866	866
867	867
868	868	/*-------------------------------------------------
869
	869
870	870	Load .nes files (iNES mappers) and identify the required slot devices
871
	871
872	872	-------------------------------------------------*/
873	873
874	874	/* Include emulation of iNES Mappers for .nes files */
r22615	r22616
975	975
976	976	if ((ROM[0] == 'U') && (ROM[1] == 'N') && (ROM[2] == 'I') && (ROM[3] == 'F'))
977	977	slot_string = get_default_card_unif(ROM, len);
978
	978
979	979	global_free(ROM);
980	980	clear();
981
	981
982	982	return slot_string;
983	983	}
984	984	else
r22615	r22616
1058	1058	//-------------------------------------------------
1059	1059
1060	1060	void nes_partialhash(hash_collection &dest, const unsigned char *data,
1061		unsigned long length, const char *functions)
	1061	unsigned long length, const char *functions)
1062	1062	{
1063	1063	if (length <= 16)
1064	1064	return;
1065	1065	dest.compute(&data[16], length - 16, functions);
1066	1066	}
1067

trunk/src/mess/machine/nes_pirate.c
r22615	r22616
11	11
12	12	TODO:
13	13	- Are the scrolling glitches (check status bar) in Magic Dragon correct? FWIW, NEStopia behaves similarly
14
	14
15	15	***********************************************************************************************************/
16	16
17	17
r22615	r22616
429	429	common_start();
430	430	irq_timer = timer_alloc(TIMER_IRQ);
431	431	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
432
	432
433	433	save_item(NAME(m_prg_reg));
434	434	save_item(NAME(m_prg_mode));
435	435	save_item(NAME(m_irq_enable));

trunk/src/mess/machine/nes_namcot.h
r22615	r22616
88	88	protected:
89	89	UINT16 m_irq_count;
90	90	int m_irq_enable;
91
	91
92	92	static const device_timer_id TIMER_IRQ = 0;
93	93	emu_timer *irq_timer;
94
	94
95	95	// Namcot-163 chip contains 8K of internal ram, possibly battery backed up (not emulated yet)
96	96	// was it also present in 175 & 340 chips?
97	97	UINT8 *m_n163_ram;

trunk/src/mess/machine/nes_slot.h
r22615	r22616
12	12	enum
13	13	{
14	14	STD_NROM = 0,
15		STD_AXROM, STD_AMROM, STD_BXROM,
	15	STD_AXROM, STD_AMROM, STD_BXROM,
16	16	STD_CNROM, STD_CPROM,
17	17	STD_EXROM, STD_FXROM, STD_GXROM,
18	18	STD_HKROM, STD_PXROM,
19	19	STD_SXROM, STD_TXROM, STD_TXSROM,
20		STD_TKROM, STD_TQROM,
	20	STD_TKROM, STD_TQROM,
21	21	STD_UXROM, STD_UN1ROM, UXROM_CC,
22		HVC_FAMBASIC, NES_QJ, PAL_ZZ, STD_EVENT,
	22	HVC_FAMBASIC, NES_QJ, PAL_ZZ, STD_EVENT,
23	23	STD_SXROM_A, STD_SOROM, STD_SOROM_A,
24	24	/* Discrete components boards (by various manufacturer) */
25	25	DIS_74X161X138, DIS_74X139X74,
r22615	r22616
77	77	TXC_22211, TXC_DUMARACING, TXC_MJBLOCK,
78	78	TXC_COMMANDOS, TXC_TW, TXC_STRIKEW,
79	79	/* Multigame Carts */
80		BMC_64IN1NR, BMC_190IN1, BMC_A65AS,
	80	BMC_64IN1NR, BMC_190IN1, BMC_A65AS,
81	81	BMC_HIK8IN1, BMC_NOVEL1, BMC_NOVEL2, BMC_S24IN1SC03, BMC_T262,
82	82	BMC_WS, BMC_SUPERBIG_7IN1, BMC_SUPERHIK_4IN1, BMC_BALLGAMES_11IN1,
83	83	BMC_MARIOPARTY_7IN1, BMC_GOLD_7IN1, BMC_SUPER_700IN1, BMC_FAMILY_4646,
r22615	r22616
85	85	BMC_15IN1, BMC_SUPERHIK_300IN1, BMC_SUPERGUN_20IN1,
86	86	BMC_GOLDENCARD_6IN1, BMC_72IN1, BMC_SUPER_42IN1, BMC_76IN1,
87	87	BMC_31IN1, BMC_22GAMES, BMC_20IN1, BMC_110IN1,
88		BMC_70IN1, BMC_800IN1, BMC_1200IN1,
	88	BMC_70IN1, BMC_800IN1, BMC_1200IN1,
89	89	BMC_GKA, BMC_GKB, BMC_VT5201, BMC_BENSHIENG, BMC_810544,
90	90	BMC_NTD_03, BMC_G63IN1, BMC_FK23C, BMC_FK23CA, BMC_PJOY84,
91		BMC_POWERFUL_255, BMC_11160, BMC_G146, BMC_8157, BMC_830118C,
	91	BMC_POWERFUL_255, BMC_11160, BMC_G146, BMC_8157, BMC_830118C,
92	92	BMC_411120C, BMC_GOLD150, BMC_GOLD260, BMC_CH001, BMC_SUPER22,
93	93	BMC_12IN1, BMC_4IN1RESET, BMC_42IN1RESET,
94	94	/* Unlicensed */
r22615	r22616
97	97	UNL_UXROM, UNL_MK2, UNL_XIAOZY, UNL_KOF96,
98	98	UNL_SF3, UNL_RACERMATE, UNL_EDU2K, UNL_LH32, UNL_LH10,
99	99	UNL_STUDYNGAME, UNL_603_5052, UNL_H2288, UNL_2708,
100		UNL_MALISB, UNL_BB, UNL_AC08, UNL_A9746, UNL_WORLDHERO,
	100	UNL_MALISB, UNL_BB, UNL_AC08, UNL_A9746, UNL_WORLDHERO,
101	101	UNL_43272, UNL_TF1201, UNL_CITYFIGHT,
102	102	/* Bootleg boards */
103	103	BTL_SMB2JA, BTL_MARIOBABY, BTL_AISENSHINICOL, BTL_TOBIDASE,
r22615	r22616
108	108	MAGICSERIES_MD, KASING_BOARD, FUTUREMEDIA_BOARD, FUKUTAKE_BOARD, SOMARI_SL12,
109	109	HENGG_SRICH, HENGG_XHZS, HENGG_SHJY3, SUBOR_TYPE0, SUBOR_TYPE1,
110	110	KAISER_KS7058, KAISER_KS7032, KAISER_KS7022, KAISER_KS7017, KAISER_KS7012, KAISER_KS7013B, KAISER_KS202,
111		CNE_DECATHLON, CNE_FSB, CNE_SHLZ, CONY_BOARD, YOKO_BOARD,
	111	CNE_DECATHLON, CNE_FSB, CNE_SHLZ, CONY_BOARD, YOKO_BOARD,
112	112	RCM_GS2015, RCM_GS2004, RCM_GS2013, RCM_TF9IN1, RCM_3DBLOCK,
113	113	WAIXING_TYPE_A, WAIXING_TYPE_A1, WAIXING_TYPE_B, WAIXING_TYPE_C, WAIXING_TYPE_D,
114	114	WAIXING_TYPE_E, WAIXING_TYPE_F, WAIXING_TYPE_G, WAIXING_TYPE_H, WAIXING_TYPE_H1,
r22615	r22616
164	164	virtual DECLARE_READ8_MEMBER(read_h) { return 0xff; }
165	165	virtual DECLARE_READ8_MEMBER(read_ex) { return 0xff; }
166	166	virtual DECLARE_WRITE8_MEMBER(write_l);
167		virtual DECLARE_WRITE8_MEMBER(write_m);
	167	virtual DECLARE_WRITE8_MEMBER(write_m);
168	168	virtual DECLARE_WRITE8_MEMBER(write_h);
169	169	virtual DECLARE_WRITE8_MEMBER(write_ex) { }
170	170
r22615	r22616
188	188	bool get_trainer() { return m_has_trainer; }
189	189	void set_trainer(bool val) { m_has_trainer = val; }
190	190
191		void set_ce(int mask, int state) { m_ce_mask = mask; m_ce_state = state; }
	191	void set_ce(int mask, int state) { m_ce_mask = mask; m_ce_state = state; }
192	192	void set_vrc_lines(int PRG_A, int PRG_B, int CHR) { m_vrc_ls_prg_a = PRG_A; m_vrc_ls_prg_b = PRG_B; m_vrc_ls_chr = CHR; }
193	193	void set_x1_005_alt(bool val) { m_x1_005_alt_mirroring = val; }
194	194	void set_bus_conflict(bool val) { m_bus_conflict = val; }
r22615	r22616
211	211	virtual void hblank_irq(int scanline, int vblank, int blanked) {}
212	212	virtual void scanline_irq(int scanline, int vblank, int blanked) {}
213	213
214		virtual void pcb_reset() {} // many pcb expect specific PRG/CHR banking at start
	214	virtual void pcb_reset() {} // many pcb expect specific PRG/CHR banking at start
215	215	void pcb_start(running_machine &machine, UINT8 *ciram_ptr);
216	216	void pcb_reg_postload(running_machine &machine);
217	217	void nes_banks_restore();
218	218
219		UINT8 hi_access_rom(UINT32 offset); // helper ROM access for a bunch of PCB reading 0x8000-0xffff for protection too
	219	UINT8 hi_access_rom(UINT32 offset); // helper ROM access for a bunch of PCB reading 0x8000-0xffff for protection too
220	220	UINT8 account_bus_conflict(UINT32 offset, UINT8 data);
221	221
222	222	protected:
r22615	r22616
228	228	UINT8 *m_vram;
229	229	UINT8 *m_battery;
230	230	UINT8 *m_ciram;
231
	231
232	232	UINT32 m_prg_size;
233	233	UINT32 m_prgram_size;
234	234	UINT32 m_vrom_size;
235	235	UINT32 m_vram_size;
236	236	UINT32 m_battery_size;
237
	237
238	238	// these are specific of some boards but must be accessible from the driver
239	239	// E.g. additional save ram for HKROM, X1-005 & X1-017 boards, or ExRAM for MMC5
240	240	UINT8 *m_mapper_sram;
r22615	r22616
247	247	int m_vrc_ls_prg_a;
248	248	int m_vrc_ls_prg_b;
249	249	int m_vrc_ls_chr;
250
	250
251	251	int m_mirroring;
252	252	bool m_pcb_ctrl_mirror, m_four_screen_vram, m_has_trainer;
253		bool m_x1_005_alt_mirroring; // temp hack for two kind of mirroring in Taito X1-005 boards (to be replaced with pin checking)
	253	bool m_x1_005_alt_mirroring; // temp hack for two kind of mirroring in Taito X1-005 boards (to be replaced with pin checking)
254	254	bool m_bus_conflict;
255	255
256	256	// PRG
r22615	r22616
271	271	void prg8_ef(int bank);
272	272	void prg8_x(int start, int bank);
273	273
274
	274
275	275	// CHR
276		int m_chr_source; // global source for the 8 VROM banks
	276	int m_chr_source; // global source for the 8 VROM banks
277	277	inline void chr_sanity_check(int source);
278	278
279		//these were previously called chr_map. they are a quick banking structure,
	279	//these were previously called chr_map. they are a quick banking structure,
280	280	//because some of these change multiple times per scanline!
281	281	int m_chr_src[8]; //defines source of base pointer
282	282	int m_chr_orig[8]; //defines offset of 0x400 byte segment at base pointer
r22615	r22616
305	305	void chr1_6(int bank, int source) { chr1_x(6, bank, source); };
306	306	void chr1_7(int bank, int source) { chr1_x(7, bank, source); };
307	307
308
	308
309	309	// NameTable & Mirroring
310	310	//these were previously called nt_page. they are a quick banking structure for a maximum of 4K of RAM/ROM/ExRAM
311	311	int m_nt_src[4];
r22615	r22616
375	375	virtual DECLARE_WRITE8_MEMBER(write_ex);
376	376
377	377	int get_pcb_id() { return m_pcb_id; };
378
	378
379	379	void pcb_start(UINT8 *ciram_ptr);
380	380	void pcb_reset();
381	381

trunk/src/mess/machine/nes_pirate.h
r22615	r22616
343	343	UINT8 m_prg_reg, m_prg_mode;
344	344	UINT16 m_irq_count;
345	345	int m_irq_enable;
346
	346
347	347	static const device_timer_id TIMER_IRQ = 0;
348	348	emu_timer *irq_timer;
349
	349
350	350	UINT8 m_mmc_vrom_bank[8];
351	351	};
352	352

trunk/src/mess/machine/primo.c
r22615	r22616
333	333	{
334	334	int i;
335	335
336
	336
337	337	UINT16 load_addr;
338	338	UINT16 start_addr;
339	339

trunk/src/mess/machine/nes_somari.c
r22615	r22616
181	181	update_mirror();
182	182	update_prg();
183	183	update_chr();
184
	184
185	185	m_count = 0;
186	186	}
187	187	}
r22615	r22616
287	287	break;
288	288	case SOMARI_MMC3_MODE:
289	289	{
290		UINT8 prg_flip = (m_latch & 0x40) ? 2 : 0;
	290	UINT8 prg_flip = (m_latch & 0x40) ? 2 : 0;
291	291	prg8_x(0, m_mmc_prg_bank[0 ^ prg_flip]);
292	292	prg8_x(1, m_mmc_prg_bank[1]);
293	293	prg8_x(2, m_mmc_prg_bank[2 ^ prg_flip]);
r22615	r22616
295	295	}
296	296	break;
297	297	case SOMARI_MMC1_MODE:
298		// case SOMARI_MMC1_MODE_AGAIN:
	298	// case SOMARI_MMC1_MODE_AGAIN:
299	299	{
300	300	UINT8 prg_offset = m_mmc1_reg[1] & 0x10;
301	301
r22615	r22616
341	341	}
342	342	break;
343	343	case SOMARI_MMC1_MODE:
344		// case SOMARI_MMC1_MODE_AGAIN:
	344	// case SOMARI_MMC1_MODE_AGAIN:
345	345	if (BIT(m_mmc1_reg[0], 4))
346	346	{
347	347	chr4_0(m_mmc1_reg[1] & 0x1f, CHRROM);
r22615	r22616
364	364	set_nt_mirroring(m_mmc3_mirror_reg ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
365	365	break;
366	366	case SOMARI_MMC1_MODE:
367		// case SOMARI_MMC1_MODE_AGAIN:
	367	// case SOMARI_MMC1_MODE_AGAIN:
368	368	switch (m_mmc1_reg[0] & 0x03)
369	369	{
370	370	case 0x00: set_nt_mirroring(PPU_MIRROR_LOW); break;

trunk/src/mess/machine/nes_cony.c
r22615	r22616
13	13	* UNL-YOKO
14	14
15	15	TODO: fix glitches and emulate properly the variants
16
	16
17	17	***********************************************************************************************************/
18	18
19	19
r22615	r22616
63	63	common_start();
64	64	irq_timer = timer_alloc(TIMER_IRQ);
65	65	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
66
	66
67	67	save_item(NAME(m_irq_enable));
68	68	save_item(NAME(m_irq_count));
69	69
r22615	r22616
99	99	common_start();
100	100	irq_timer = timer_alloc(TIMER_IRQ);
101	101	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
102
	102
103	103	save_item(NAME(m_irq_enable));
104	104	save_item(NAME(m_irq_count));
105	105

trunk/src/mess/machine/nes_cony.h
r22615	r22616
28	28
29	29	UINT16 m_irq_count;
30	30	int m_irq_enable;
31
	31
32	32	static const device_timer_id TIMER_IRQ = 0;
33	33	emu_timer *irq_timer;
34
	34
35	35	UINT8 m_latch1, m_latch2;
36	36	UINT8 m_low_reg[4];
37	37	UINT8 m_reg[10];

trunk/src/mess/machine/nes_taito.c
r22615	r22616
13	13	* Taito TC0190FMC+PAL16R4 [mapper 48]
14	14	* Taito X1-005 [mapper 80, 207]
15	15	* Taito X1-017 [mapper 82]
16
	16
17	17	TODO:
18	18	- Akira does not work. Investigate why!
19	19	- Don Doko Don 2 freezes when you get to the first boss
20
21	20
	21
22	22	***********************************************************************************************************/
23	23
24	24

trunk/src/mess/machine/nes_nxrom.c
r22615	r22616
19	19	* Nintendo UN1ROM [mapper 94]
20	20
21	21	Known issues on specific mappers:
22
	22
23	23	* 000 F1 Race requires more precise PPU timing. It currently has plenty of 1-line glitches.
24	24	* 003 Firehouse Rescue has flashing graphics (same PPU issue as Back to the Future 2 & 3?)
25	25	* 007 Marble Madness has small graphics corruptions
26	26	* 034 Titanic 1912 (pirate BxROM) has missing gfx (same PPU issue of many Waixing titles almost for sure)
27
	27
28	28	***********************************************************************************************************/
29	29
30	30

trunk/src/mess/machine/rmnimbus.c
r22615	r22616
2373	2373
2374	2374	void rmnimbus_state::hdc_reset()
2375	2375	{
2376
2377	2376	m_nimbus_drives.reg410_in=0;
2378	2377	m_nimbus_drives.reg410_in \|= (m_scsibus->scsi_req_r() ? 0 : HDC_REQ_MASK);
2379	2378	m_nimbus_drives.reg410_in \|= (m_scsibus->scsi_cd_r() ? 0 : HDC_CD_MASK);
r22615	r22616
2386	2385
2387	2386	void rmnimbus_state::hdc_ctrl_write(UINT8 data)
2388	2387	{
2389
2390	2388	// If we enable the HDC interupt, and an interrupt is pending, go deal with it.
2391	2389	if(((data & HDC_IRQ_MASK) && (~m_nimbus_drives.reg410_out & HDC_IRQ_MASK)) &&
2392	2390	((~m_nimbus_drives.reg410_in & HDC_INT_TRIGGER)==HDC_INT_TRIGGER))
r22615	r22616
2400	2398
2401	2399	void rmnimbus_state::hdc_post_rw()
2402	2400	{
2403
2404	2401	if((m_nimbus_drives.reg410_in & HDC_REQ_MASK)==0)
2405	2402	m_scsibus->scsi_ack_w(1);
2406	2403

trunk/src/mess/machine/bebox.c
r22615	r22616
1016	1016	space_0.install_readwrite_bank(0, m_ram->size() - 1, 0, 0x02000000, "bank3");
1017	1017	space_1.install_readwrite_bank(0, m_ram->size() - 1, 0, 0x02000000, "bank3");
1018	1018	membank("bank3")->set_base(m_ram->pointer());
1019
	1019
1020	1020	/* The following is a verrrry ugly hack put in to support NetBSD for
1021	1021	* NetBSD. When NetBSD/bebox it does most of its work on CPU #0 and then
1022	1022	* lets CPU #1 go. However, it seems that CPU #1 jumps into never-never

trunk/src/mess/machine/nes_discrete.c
r22615	r22616
7	7	Visit http://mamedev.org for licensing and usage restrictions.
8	8
9	9	Here we emulate the following PCBs
10
	10
11	11	* PCB with IC 74x161x161x32 [mapper 70 & 152]
12		* PCB with IC 74x139x74 [mapper 87]
	12	* PCB with IC 74x139x74 [mapper 87]
13	13	* PCB with IC 74x377 [mapper 11]
14	14	* PCB with IC 74x161x138 [mapper 38]
15
	15
16	16	TODO:
17	17	- Investigating missing inputs in Crime Busters
18
	18
19	19	***********************************************************************************************************/
20	20
21	21

trunk/src/mess/machine/mac.c
r22615	r22616
707	707
708	708	void mac_state::kbd_shift_out(int data)
709	709	{
710
711	710	if (m_kbd_comm == TRUE)
712	711	{
713	712	m_kbd_shift_reg = data;
r22615	r22616
746	745	*/
747	746	void mac_state::keyboard_receive(int val)
748	747	{
749
750	748	switch (val)
751	749	{
752	750	case 0x10:
r22615	r22616
2025	2023
2026	2024	void mac_state::mac_driver_init(model_t model)
2027	2025	{
2028
2029	2026	m_overlay = 1;
2030	2027	m_scsi_interrupt = 0;
2031	2028	m_model = model;

trunk/src/mess/machine/nes_waixing.c
r22615	r22616
10	10	Here we emulate the various PCBs used by Waixing for its games
11	11
12	12	TODO:
13		- investigate the PPU issues causing some games not to have sprites (e.g. some games using mappers 15, 164,
	13	- investigate the PPU issues causing some games not to have sprites (e.g. some games using mappers 15, 164,
14	14	242, 249)
15	15
16	16	***********************************************************************************************************/

trunk/src/mess/machine/upd71071.c
r22615	r22616
110	110	const upd71071_intf* intf;
111	111	devcb_resolved_write_line m_out_hreq_func;
112	112	devcb_resolved_write_line m_out_eop_func;
113		devcb_resolved_read16 m_dma_read[4];
114		devcb_resolved_write16 m_dma_write[4];
	113	devcb_resolved_read16 m_dma_read[4];
	114	devcb_resolved_write16 m_dma_write[4];
115	115	devcb_resolved_write_line m_out_dack_func[4];
116	116	int m_hreq;
117	117	int m_eop;

trunk/src/mess/machine/upd71071.h
r22615	r22616
9	9	int clock;
10	10	devcb_write_line m_out_hreq_cb;
11	11	devcb_write_line m_out_eop_cb;
12		devcb_read16 m_dma_read[4];
13		devcb_write16 m_dma_write[4];
	12	devcb_read16 m_dma_read[4];
	13	devcb_write16 m_dma_write[4];
14	14	devcb_write_line m_out_dack_cb[4];
15	15	};
16	16

trunk/src/mess/machine/europc.c
r22615	r22616
212	212	reg 9:
213	213	reg a:
214	214	reg b: 0x10 written
215		bit 0,1: 0 video startup mode: 0=specialadapter, 1=color40, 2=color80, 3=monochrom
216		bit 2: internal video on
217		bit 4: color
218		bit 6,7: clock
	215	bit 0,1: 0 video startup mode: 0=specialadapter, 1=color40, 2=color80, 3=monochrom
	216	bit 2: internal video on
	217	bit 4: color
	218	bit 6,7: clock
219	219	reg c:
220		bit 0,1: language/country
	220	bit 0,1: language/country
221	221	reg d: xor checksum
222	222	reg e:
223	223	reg 0f: 01 status ok, when not 01 written

trunk/src/mess/machine/nes_bandai.c
r22615	r22616
146	146	common_start();
147	147	irq_timer = timer_alloc(TIMER_IRQ);
148	148	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
149
	149
150	150	save_item(NAME(m_irq_enable));
151	151	save_item(NAME(m_irq_count));
152	152	}
r22615	r22616
167	167	common_start();
168	168	irq_timer = timer_alloc(TIMER_IRQ);
169	169	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
170
	170
171	171	save_item(NAME(m_irq_enable));
172	172	save_item(NAME(m_irq_count));
173	173	save_item(NAME(m_i2c_mem));
r22615	r22616
192	192	common_start();
193	193	irq_timer = timer_alloc(TIMER_IRQ);
194	194	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
195
	195
196	196	save_item(NAME(m_reg));
197	197	}
198	198
r22615	r22616
256	256	update_chr();
257	257	}
258	258	#endif
259
	259
260	260	m_nt_access[page][offset & 0x3ff] = data;
261	261	}
262	262
263	263	READ8_MEMBER(nes_oekakids_device::nt_r)
264	264	{
265	265	int page = ((offset & 0xc00) >> 10);
266
	266
267	267	#if 0
268	268	if (offset < 0x1000 && (m_latch != (offset & 0x300) >> 8))
269	269	{
r22615	r22616
271	271	update_chr();
272	272	}
273	273	#endif
274
	274
275	275	return m_nt_access[page][offset & 0x3ff];
276	276	}
277	277
278	278	void nes_oekakids_device::update_chr()
279		{
	279	{
280	280	chr4_0(m_reg \| m_latch, CHRRAM);
281	281	chr4_4(m_reg \| 0x03, CHRRAM);
282	282	}
r22615	r22616
332	332	if (m_irq_enable)
333	333	{
334	334	// 16bit counter, IRQ fired when the counter goes from 1 to 0
335		// after firing, the counter is not reloaded, but next clock
336		// counter wraps around from 0 to 0xffff
	335	// after firing, the counter is not reloaded, but next clock
	336	// counter wraps around from 0 to 0xffff
337	337	if (!m_irq_count)
338	338	m_irq_count = 0xffff;
339	339	else
340	340	m_irq_count--;
341
	341
342	342	if (!m_irq_count)
343	343	{
344	344	machine().device("maincpu")->execute().set_input_line(M6502_IRQ_LINE, ASSERT_LINE);
r22615	r22616
487	487	prg16_cdef(prg_base \| 0x0f);
488	488	}
489	489
490		READ8_MEMBER(nes_fjump2_device::read_m)
491		{
	490	READ8_MEMBER(nes_fjump2_device::read_m)
	491	{
492	492	LOG_MMC(("fjump2 read_m, offset: %04x\n", offset));
493	493	return m_battery[offset & (m_battery_size - 1)];
494	494	}
495	495
496		WRITE8_MEMBER(nes_fjump2_device::write_m)
497		{
	496	WRITE8_MEMBER(nes_fjump2_device::write_m)
	497	{
498	498	LOG_MMC(("fjump2 write_m, offset: %04x, data: %02x\n", offset, data));
499	499	m_battery[offset & (m_battery_size - 1)] = data;
500	500	}

trunk/src/mess/machine/nes_bandai.h
r22615	r22616
69	69	protected:
70	70	UINT16 m_irq_count;
71	71	int m_irq_enable;
72
	72
73	73	static const device_timer_id TIMER_IRQ = 0;
74	74	emu_timer *irq_timer;
75	75	};

trunk/src/mess/machine/nes_camerica.c
r22615	r22616
15	15
16	16
17	17	TODO:
18		- check what causes flickering from PPU in Fire Hawk, Poogie and Big Nose (same PPU issue as Back to
	18	- check what causes flickering from PPU in Fire Hawk, Poogie and Big Nose (same PPU issue as Back to
19	19	Future 2&3?)
20	20	- not all the Golden Five games work. investigate!
21	21

trunk/src/mess/machine/nes_kaiser.c
r22615	r22616
19	19
20	20	The Kaiser KS7057 bootleg board is emulated in nes_mmc3_clones.c
21	21
22
	22
23	23	TODO:
24		- FCEUmm lists more Kaiser PCBs:
25		* KS7030 (for Yume Koujou Doki Doki Panic by Kaiser?)
	24	- FCEUmm lists more Kaiser PCBs:
	25	* KS7030 (for Yume Koujou Doki Doki Panic by Kaiser?)
26	26	* KS7031 (for Dracula II?)
27		* KS7037
	27	* KS7037
28	28	but there seem to be no available dumps...
29	29
30	30	***********************************************************************************************************/
r22615	r22616
134	134	common_start();
135	135	irq_timer = timer_alloc(TIMER_IRQ);
136	136	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
137
	137
138	138	save_item(NAME(m_latch));
139	139	save_item(NAME(m_irq_enable));
140	140	save_item(NAME(m_irq_count));
r22615	r22616
160	160	common_start();
161	161	irq_timer = timer_alloc(TIMER_IRQ);
162	162	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
163
	163
164	164	save_item(NAME(m_latch));
165	165	save_item(NAME(m_irq_enable));
166	166	save_item(NAME(m_irq_count));

trunk/src/mess/machine/nes_kaiser.h
r22615	r22616
66	66
67	67	UINT16 m_irq_count;
68	68	int m_irq_enable;
69
	69
70	70	static const device_timer_id TIMER_IRQ = 0;
71	71	emu_timer *irq_timer;
72	72	};
r22615	r22616
109	109	UINT16 m_irq_count;
110	110	UINT8 m_irq_status;
111	111	int m_irq_enable;
112
	112
113	113	static const device_timer_id TIMER_IRQ = 0;
114	114	emu_timer *irq_timer;
115	115	};

trunk/src/mess/machine/galaxy.c
r22615	r22616
62	62
63	63	void galaxy_state::galaxy_setup_snapshot (const UINT8 * data, UINT32 size)
64	64	{
65
66	65	switch (size)
67	66	{
68	67	case GALAXY_SNAPSHOT_V1_SIZE:

trunk/src/mess/machine/dragon.c
r22615	r22616
146	146	offs_t offset = romswitch
147	147	? 0x0000 // This is the 32k mode basic(64)/boot rom(alpha)
148	148	: 0x8000; // This is the 64k mode basic(64)/basic rom(alpha)
149		m_sam->set_bank_offset(1, offset); // 0x8000-0x9FFF
150		m_sam->set_bank_offset(2, offset); // 0xA000-0xBFFF
	149	m_sam->set_bank_offset(1, offset); // 0x8000-0x9FFF
	150	m_sam->set_bank_offset(2, offset); // 0xA000-0xBFFF
151	151	}

trunk/src/mess/machine/nes_jaleco.c
r22615	r22616
210	210	common_start();
211	211	irq_timer = timer_alloc(TIMER_IRQ);
212	212	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
213
	213
214	214	save_item(NAME(m_mmc_prg_bank));
215	215	save_item(NAME(m_mmc_vrom_bank));
216	216	save_item(NAME(m_irq_enable));
r22615	r22616
430	430	{
431	431	if (m_irq_enable)
432	432	{
433		if (m_irq_mode & 0x08) // 4bits counter
	433	if (m_irq_mode & 0x08) // 4bits counter
434	434	{
435	435	if (!(m_irq_count & 0x000f))
436	436	{
r22615	r22616
440	440	else
441	441	m_irq_count = (m_irq_count & 0xfff0) \| ((m_irq_count & 0x000f) - 1);
442	442	}
443		else if (m_irq_mode & 0x04) // 8bits counter
	443	else if (m_irq_mode & 0x04) // 8bits counter
444	444	{
445	445	if (!(m_irq_count & 0x00ff))
446	446	{
r22615	r22616
450	450	else
451	451	m_irq_count = (m_irq_count & 0xff00) \| ((m_irq_count & 0x00ff) - 1);
452	452	}
453		else if (m_irq_mode & 0x02) // 12bits counter
	453	else if (m_irq_mode & 0x02) // 12bits counter
454	454	{
455	455	if (!(m_irq_count & 0x0fff))
456	456	{
r22615	r22616
460	460	else
461	461	m_irq_count = (m_irq_count & 0xf000) \| ((m_irq_count & 0x0fff) - 1);
462	462	}
463		else // 16bits counter
	463	else // 16bits counter
464	464	{
465	465	if (!m_irq_count)
466	466	{

trunk/src/mess/machine/nes_sunsoft.c
r22615	r22616
18	18
19	19	TODO:
20	20	- check 1-line glitches due to IRQ in Sunsoft-3
21
	21
22	22	***********************************************************************************************************/
23	23
24	24
r22615	r22616
124	124	common_start();
125	125	irq_timer = timer_alloc(TIMER_IRQ);
126	126	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
127
	127
128	128	save_item(NAME(m_irq_enable));
129	129	save_item(NAME(m_irq_toggle));
130	130	save_item(NAME(m_irq_count));
r22615	r22616
169	169	irq_timer = timer_alloc(TIMER_IRQ);
170	170	// this has to be hardcoded because some some scanline code only suits NTSC... it will be fixed with PPU rewrite
171	171	irq_timer->adjust(attotime::zero, 0, attotime::from_hz((21477272.724 / 12)));
172		// irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
173
	172	// irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
	173
174	174	save_item(NAME(m_wram_bank));
175	175	save_item(NAME(m_latch));
176	176	save_item(NAME(m_irq_enable));

trunk/src/mess/machine/nes_jaleco.h
r22615	r22616
147	147	UINT16 m_irq_count, m_irq_count_latch;
148	148	UINT8 m_irq_mode;
149	149	int m_irq_enable;
150
	150
151	151	static const device_timer_id TIMER_IRQ = 0;
152	152	emu_timer *irq_timer;
153
	153
154	154	UINT8 m_mmc_prg_bank[3];
155	155	UINT8 m_mmc_vrom_bank[8];
156	156

trunk/src/mess/machine/nes_sunsoft.h
r22615	r22616
55	55	private:
56	56	UINT16 m_irq_count;
57	57	int m_irq_enable, m_irq_toggle;
58
	58
59	59	static const device_timer_id TIMER_IRQ = 0;
60	60	emu_timer *irq_timer;
61	61	};
r22615	r22616
106	106	private:
107	107	UINT16 m_irq_count;
108	108	int m_irq_enable;
109
	109
110	110	static const device_timer_id TIMER_IRQ = 0;
111	111	emu_timer *irq_timer;
112
	112
113	113	UINT8 m_latch;
114	114	UINT8 m_wram_bank;
115	115	};

trunk/src/mess/machine/nes_irem.c
r22615	r22616
132	132	common_start();
133	133	irq_timer = timer_alloc(TIMER_IRQ);
134	134	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
135
	135
136	136	save_item(NAME(m_irq_enable));
137	137	save_item(NAME(m_irq_count));
138	138	save_item(NAME(m_irq_count_latch));
r22615	r22616
162	162	Games: Napoleon Senki
163	163
164	164	iNES: mapper 77
165
	165
166	166	This board should use 2KB of CHRRAM as NTRAM, instead
167		of using directly 4-screen mirroring, but for the
	167	of using directly 4-screen mirroring, but for the
168	168	moment we cheat in this way...
169	169
170	170	-------------------------------------------------*/
r22615	r22616
185	185	Irem Holy Diver board emulation
186	186
187	187	iNES: mapper 78 (shared with JF-16)
188
	188
189	189	-------------------------------------------------*/
190	190
191	191	WRITE8_MEMBER(nes_holydivr_device::write_h)
r22615	r22616
284	284	// after firing, the counter is not reloaded and does not wrap
285	285	if (m_irq_count > 0)
286	286	m_irq_count--;
287
	287
288	288	if (!m_irq_count)
289	289	{
290	290	machine().device("maincpu")->execute().set_input_line(M6502_IRQ_LINE, ASSERT_LINE);

trunk/src/mess/machine/nes_mmc1.c
r22615	r22616
10	10	Here we emulate the Nintendo SxROM / MMC-1 PCBs + older variants without WRAM protect bit
11	11
12	12	Known issues on specific mappers:
13
14		* 001 Yoshi flashes in-game.
	13
	14	* 001 Yoshi flashes in-game.
15	15	* 001 Back to the Future have heavily corrupted graphics (since forever).
16
	16
17	17	***********************************************************************************************************/
18	18
19	19

trunk/src/mess/machine/nes_irem.h
r22615	r22616
89	89	protected:
90	90	UINT16 m_irq_count, m_irq_count_latch;
91	91	int m_irq_enable;
92
	92
93	93	static const device_timer_id TIMER_IRQ = 0;
94	94	emu_timer *irq_timer;
95	95	};

trunk/src/mess/machine/isa_ide8.c
r22615	r22616
4	4
5	5	As implemented by the Vintage computer forums XT-IDE controller.
6	6
7		Card has jumpers for I/O base address, and ROM base address, for the time
	7	Card has jumpers for I/O base address, and ROM base address, for the time
8	8	being we'll emulate an I/O base of 0x300 and a ROM base of 0xC8000.
9	9
10		If the I/O address is changed then the ROM will need to be patched.
	10	If the I/O address is changed then the ROM will need to be patched.
11	11	The opensource bios is available from :
12	12	http://code.google.com/p/xtideuniversalbios/
13	13
14	14	The data high register is connected to a pair of latches that have the MSB of
15		the 16 bit data word latched into so that 16 bit IO may be performmed, this
	15	the 16 bit data word latched into so that 16 bit IO may be performmed, this
16	16	involves the following :
17	17
18	18	A Data read will read the data register first, and obtain the bottom 8 bits
19		of the data word, the top 8 bits will be latched at the same time these are
	19	of the data word, the top 8 bits will be latched at the same time these are
20	20	then read from the latch to the processor.
21	21
22		A data write will first write the top 8 bits to the latch, and then the bottom
23		8 bits to the normal data register, this will also transfer the top 8 bits to
	22	A data write will first write the top 8 bits to the latch, and then the bottom
	23	8 bits to the normal data register, this will also transfer the top 8 bits to
24	24	the drive.
25	25
26		IDE Register XTIDE rev 1 rev 2 or modded rev 1
27		Data (XTIDE Data Low) 0 0
28		Error (in), Features (out) 1 8
29		Sector Count 2 2
30		Sector Number,
31		LBA bits 0...7,
32		LBA48 bits 24...31 3 10
33		Low Cylinder,
34		LBA bits 8...15,
35		LBA48 bits 32...39 4 4
36		High Cylinder,
37		LBA bits 16...23,
38		LBA48 bits 40...47 5 12
	26	IDE Register XTIDE rev 1 rev 2 or modded rev 1
	27	Data (XTIDE Data Low) 0 0
	28	Error (in), Features (out) 1 8
	29	Sector Count 2 2
	30	Sector Number,
	31	LBA bits 0...7,
	32	LBA48 bits 24...31 3 10
	33	Low Cylinder,
	34	LBA bits 8...15,
	35	LBA48 bits 32...39 4 4
	36	High Cylinder,
	37	LBA bits 16...23,
	38	LBA48 bits 40...47 5 12
39	39	Drive and Head Select,
40		LBA28 bits 24...27 6 6
41		Status (in), Command (out) 7 14
42		XTIDE Data High 8 1
43		Alternative Status (in),
44		Device Control (out) 14 7
	40	LBA28 bits 24...27 6 6
	41	Status (in), Command (out) 7 14
	42	XTIDE Data High 8 1
	43	Alternative Status (in),
	44	Device Control (out) 14 7
45	45
46	46	***************************************************************************/
47	47
r22615	r22616
55	55
56	56	static READ8_DEVICE_HANDLER( ide8_r )
57	57	{
58		ide_controller_device ide = (ide_controller_device ) device;
59		isa8_ide_device ide8_d = downcast<isa8_ide_device >(device->owner());
60		UINT8 result = 0;
61
	58	ide_controller_device ide = (ide_controller_device ) device;
	59	isa8_ide_device ide8_d = downcast<isa8_ide_device >(device->owner());
	60	UINT8 result = 0;
	61
62	62	if(offset == 0)
63	63	{
64	64	// Data register transfer low byte and latch high
r22615	r22616
72	72	else if(offset == 14)
73	73	result=ide->ide_controller_read(1, (offset & 0x07), 1);
74	74
75		// logerror("%s ide8_r: offset=%d, result=%2X\n",device->machine().describe_context(),offset,result);
	75	// logerror("%s ide8_r: offset=%d, result=%2X\n",device->machine().describe_context(),offset,result);
76	76
77	77	return result;
78	78	}
79	79
80	80	static WRITE8_DEVICE_HANDLER( ide8_w )
81	81	{
82		ide_controller_device ide = (ide_controller_device ) device;
83		isa8_ide_device ide8_d = downcast<isa8_ide_device >(device->owner());
84
85		// logerror("%s ide8_w: offset=%d, data=%2X\n",device->machine().describe_context(),offset,data);
	82	ide_controller_device ide = (ide_controller_device ) device;
	83	isa8_ide_device ide8_d = downcast<isa8_ide_device >(device->owner());
86	84
	85	// logerror("%s ide8_w: offset=%d, data=%2X\n",device->machine().describe_context(),offset,data);
	86
87	87	if(offset == 0)
88	88	{
89	89	// Data register transfer low byte and latched high
r22615	r22616
168	168	ROM_START( ide8 )
169	169	ROM_REGION(0x04000,"ide8", 0)
170	170	// XT-IDE universal bios from : http://code.google.com/p/xtideuniversalbios/
171		ROM_LOAD("ide_xtl.bin", 0x00000, 0x03800, CRC(68801d16) SHA1(f3f5bed385d00ac444d85f492c879aa68a864160))
	171	ROM_LOAD("ide_xtl.bin", 0x00000, 0x03800, CRC(68801d16) SHA1(f3f5bed385d00ac444d85f492c879aa68a864160))
172	172	ROM_END
173	173
174	174	//**************************************************************************
r22615	r22616
234	234
235	235	void isa8_ide_device::device_reset()
236	236	{
237		int base_address = ((ioport("BIOS_BASE")->read() & 0x0F) * 16 * 1024) + 0xC0000;
238		int io_address = ((ioport("IO_ADDRESS")->read() & 0x0F) * 0x20) + 0x200;
239		irq = (ioport("IRQ")->read() & 0x07);
240
	237	int base_address = ((ioport("BIOS_BASE")->read() & 0x0F) * 16 * 1024) + 0xC0000;
	238	int io_address = ((ioport("IO_ADDRESS")->read() & 0x0F) * 0x20) + 0x200;
	239	irq = (ioport("IRQ")->read() & 0x07);
	240
241	241	m_isa->install_rom(this, base_address, base_address + (16*1024) -1 , 0, 0, "ide8", "ide8");
242	242	m_isa->install_device(subdevice("ide"), io_address, io_address+15, 0, 0, FUNC(ide8_r), FUNC(ide8_w) );
243	243

trunk/src/mess/machine/isa_ide8.h
r22615	r22616
31	31	void set_latch_in(UINT8 new_latch) { data_high_in=new_latch; }
32	32	UINT8 get_latch_out() { return data_high_out; }
33	33	void set_latch_out(UINT8 new_latch) { data_high_out=new_latch; }
34
35	34
	35
36	36	protected:
37	37	// device-level overrides
38	38	virtual void device_start();
r22615	r22616
41	41
42	42	private:
43	43	// internal state
44		// bool m_is_primary;
45
	44	// bool m_is_primary;
	45
46	46	// Interupt request
47		UINT8 irq;
48
	47	UINT8 irq;
	48
49	49	// Data latch for high byte in and out
50	50	UINT8 data_high_in;
51	51	UINT8 data_high_out;

trunk/src/mess/machine/nes_mmc3.c
r22615	r22616
18	18
19	19
20	20	Known issues on specific mappers:
21
	21
22	22	* 004 Mendel Palace has never worked properly
23	23	* 004 Ninja Gaiden 2 has flashing bg graphics in the second level
24	24	* 119 Pin Bot has glitches when the ball is in the upper half of the screen
25
	25
26	26	***********************************************************************************************************/
27	27
28	28

trunk/src/mess/machine/nes_ave.c
r22615	r22616
115	115
116	116	iNES: mapper 34
117	117
118		Notice that in this board the bankswitch regs
	118	Notice that in this board the bankswitch regs
119	119	overlaps WRAM, so that writes to the regs are
120	120	then readable back in WRAM (WRAM is tested by
121	121	Impossible Mission II at start)
122
	122
123	123	In MESS: Supported.
124	124
125	125	-------------------------------------------------*/
r22615	r22616
127	127	WRITE8_MEMBER(nes_nina001_device::write_m)
128	128	{
129	129	LOG_MMC(("nina-001 write_m, offset: %04x, data: %02x\n", offset, data));
130
	130
131	131	switch (offset)
132	132	{
133	133	case 0x1ffd:

trunk/src/mess/machine/nes_konami.c
r22615	r22616
158	158	common_start();
159	159	irq_timer = timer_alloc(TIMER_IRQ);
160	160	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
161
	161
162	162	save_item(NAME(m_irq_mode));
163	163	save_item(NAME(m_irq_prescale));
164	164	save_item(NAME(m_irq_enable));
r22615	r22616
201	201	common_start();
202	202	irq_timer = timer_alloc(TIMER_IRQ);
203	203	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
204
	204
205	205	save_item(NAME(m_irq_mode));
206	206	save_item(NAME(m_irq_prescale));
207	207	save_item(NAME(m_irq_enable));
r22615	r22616
367	367	{
368	368	if (m_irq_enable)
369	369	{
370		if (m_irq_mode) // 8bits mode
	370	if (m_irq_mode) // 8bits mode
371	371	{
372	372	if ((m_irq_count & 0x00ff) == 0xff)
373	373	{
r22615	r22616
377	377	else
378	378	m_irq_count = (m_irq_count & 0xff00) \| ((m_irq_count & 0x00ff) + 1);
379	379	}
380		else // 16bits mode
	380	else // 16bits mode
381	381	{
382	382	if (m_irq_count == 0xffff)
383	383	{
r22615	r22616
455	455	{
456	456	if (m_irq_enable)
457	457	{
458		if (m_irq_mode) // cycle mode
	458	if (m_irq_mode) // cycle mode
459	459	irq_tick();
460		else // scanline mode
	460	else // scanline mode
461	461	{
462		// A prescaler divides the passing CPU cycles by 114, 114, then 113 (and repeats that order).
	462	// A prescaler divides the passing CPU cycles by 114, 114, then 113 (and repeats that order).
463	463	// This approximates 113+2/3 CPU cycles, which is one NTSC scanline.
464	464	// Since this is a CPU-based IRQ, though, it is triggered also during non visible scanlines...
465	465	if (m_irq_prescale < 3)
r22615	r22616
584	584	case 0x4000:
585	585	prg8_cd(data);
586	586	break;
587		case 0x1000: // pulse 1 & global control
	587	case 0x1000: // pulse 1 & global control
588	588	m_vrc6snd->write(space, add_lines>>8, data);
589	589	break;
590		case 0x2000: // pulse 2
	590	case 0x2000: // pulse 2
591	591	m_vrc6snd->write(space, (add_lines>>8) \| 0x100, data);
592	592	break;
593	593	case 0x3000:
r22615	r22616
601	601	case 0x0c: set_nt_mirroring(PPU_MIRROR_HIGH); break;
602	602	}
603	603	}
604		else // saw
	604	else // saw
605	605	{
606	606	m_vrc6snd->write(space, (add_lines>>8) \| 0x200, data);
607	607	}

trunk/src/mess/machine/nes_konami.h
r22615	r22616
65	65	UINT16 m_irq_count, m_irq_count_latch;
66	66	int m_irq_enable, m_irq_enable_latch;
67	67	int m_irq_mode;
68
	68
69	69	static const device_timer_id TIMER_IRQ = 0;
70	70	emu_timer *irq_timer;
71	71	};
r22615	r22616
95	95	void irq_tick();
96	96	UINT16 m_irq_count, m_irq_count_latch;
97	97	int m_irq_enable, m_irq_enable_latch;
98		int m_irq_mode;
	98	int m_irq_mode;
99	99	int m_irq_prescale;
100
	100
101	101	static const device_timer_id TIMER_IRQ = 0;
102	102	emu_timer *irq_timer;
103	103	};

trunk/src/mess/machine/md_rom.c
r22615	r22616
619	619	}
620	620	return 0;
621	621	}
622
	622
623	623	// non-protection accesses
624	624	if (offset < 0x400000/2)
625	625	return m_rom[MD_ADDR(offset)];

trunk/src/mess/machine/sms.c
r22615	r22616
1512	1512
1513	1513	int sms_state::detect_lphaser_xoffset( UINT8 *rom )
1514	1514	{
1515
1516	1515	static const UINT8 signatures[6][16] =
1517	1516	{
1518	1517	/* Spacegun */

trunk/src/mess/machine/nes_bootleg.c
r22615	r22616
238	238	common_start();
239	239	irq_timer = timer_alloc(TIMER_IRQ);
240	240	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
241
	241
242	242	save_item(NAME(m_irq_enable));
243	243	save_item(NAME(m_irq_count));
244	244	}
r22615	r22616
292	292	common_start();
293	293	irq_timer = timer_alloc(TIMER_IRQ);
294	294	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
295
	295
296	296	save_item(NAME(m_irq_enable));
297	297	save_item(NAME(m_irq_count));
298	298	}
r22615	r22616
305	305	prg8_ab(0);
306	306	prg8_cd(0);
307	307	prg8_ef(9);
308
	308
309	309	m_irq_enable = 0;
310	310	m_irq_count = 0;
311	311	}
r22615	r22616
315	315	common_start();
316	316	irq_timer = timer_alloc(TIMER_IRQ);
317	317	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
318
	318
319	319	save_item(NAME(m_irq_enable));
320	320	save_item(NAME(m_irq_count));
321	321	}
r22615	r22616
338	338	common_start();
339	339	irq_timer = timer_alloc(TIMER_IRQ);
340	340	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
341
	341
342	342	save_item(NAME(m_irq_enable));
343	343	save_item(NAME(m_irq_count));
344	344	}
r22615	r22616
903	903	Games: Super Mario Bros. 2 Pirate (LF36)
904	904
905	905	iNES: mapper 43
906
	906
907	907	In MESS: Supported.
908	908
909	909	-------------------------------------------------*/
r22615	r22616
930	930	{
931	931	LOG_MMC(("smb2j write_l, offset: %04x, data: %02x\n", offset, data));
932	932	offset += 0x100;
933
934		if (offset == 0x122) // $4122
935		m_irq_enable = data & 3; // maybe also m_irq_count = 0?!?
	933
	934	if (offset == 0x122) // $4122
	935	m_irq_enable = data & 3; // maybe also m_irq_count = 0?!?
936	936	}
937	937
938	938	WRITE8_MEMBER(nes_smb2j_device::write_h)
939	939	{
940	940	LOG_MMC(("smb2j write_h, offset: %04x, data: %02x\n", offset, data));
941
942		if (offset == 0x122) // $8122 too?
	941
	942	if (offset == 0x122) // $8122 too?
943	943	m_irq_enable = data & 3;
944	944	}
945	945
946	946	WRITE8_MEMBER(nes_smb2j_device::write_ex)
947	947	{
948	948	LOG_MMC(("smb2j write_ex, offset: %04x, data: %02x\n", offset, data));
949
	949
950	950	if (offset == 2)
951	951	{
952	952	int temp = 0;
953
	953
954	954	// According to hardware tests
955	955	if (data & 1)
956	956	temp = 3;
957	957	else
958	958	temp = 4 + ((data & 7) >> 1);
959
	959
960	960	prg8_cd(temp);
961	961	}
962	962	}
r22615	r22616
965	965	{
966	966	LOG_MMC(("smb2j read_l, offset: %04x\n", offset));
967	967	offset += 0x100;
968
	968
969	969	if (offset >= 0x1000)
970	970	return m_prg[0x10000 + (offset & 0x0fff)];
971
972		return ((offset + 0x4000) & 0xff00) >> 8; // open bus
	971
	972	return ((offset + 0x4000) & 0xff00) >> 8; // open bus
973	973	}
974	974
975	975	READ8_MEMBER(nes_smb2j_device::read_m)
r22615	r22616
1105	1105	}
1106	1106
1107	1107	/*-------------------------------------------------
1108
	1108
1109	1109	(UNL-)09-034A
1110
	1110
1111	1111	Games: Zanac FDS conversion with two PRG chips and
1112		no CHRROM and Volleyball FDS conversion with two PRG
	1112	no CHRROM and Volleyball FDS conversion with two PRG
1113	1113	chips and CHRROM.
1114	1114	Originally dumps were marked as UNL-SMB2J pcb
1115
1116		iNES:
1117
	1115
	1116	iNES:
	1117
1118	1118	In MESS: Supported.
1119
	1119
1120	1120	-------------------------------------------------*/
1121	1121
1122	1122	WRITE8_MEMBER(nes_09034a_device::write_ex)
1123	1123	{
1124	1124	LOG_MMC(("09-034a write_ex, offset: %04x, data: %02x\n", offset, data));
1125
1126		if (offset == 7) // $4027
	1125
	1126	if (offset == 7) // $4027
1127	1127	m_reg = data & 1;
1128	1128	}
1129	1129

trunk/src/mess/machine/nes_bootleg.h
r22615	r22616
110	110	private:
111	111	UINT16 m_irq_count;
112	112	int m_irq_enable;
113
	113
114	114	static const device_timer_id TIMER_IRQ = 0;
115	115	emu_timer *irq_timer;
116	116	};
r22615	r22616
163	163	public:
164	164	// construction/destruction
165	165	nes_smb2j_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
166
	166
167	167	// device-level overrides
168	168	virtual void device_start();
169	169	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
r22615	r22616
172	172	virtual DECLARE_WRITE8_MEMBER(write_ex);
173	173	virtual DECLARE_WRITE8_MEMBER(write_l);
174	174	virtual DECLARE_WRITE8_MEMBER(write_h);
175
	175
176	176	virtual void pcb_reset();
177
	177
178	178	private:
179	179	UINT16 m_irq_count;
180	180	int m_irq_enable;
181
	181
182	182	static const device_timer_id TIMER_IRQ = 0;
183	183	emu_timer *irq_timer;
184	184	};
r22615	r22616
203	203	private:
204	204	UINT16 m_irq_count;
205	205	int m_irq_enable;
206
	206
207	207	static const device_timer_id TIMER_IRQ = 0;
208	208	emu_timer *irq_timer;
209	209	};
r22615	r22616
229	229	private:
230	230	UINT16 m_irq_count;
231	231	int m_irq_enable;
232
	232
233	233	static const device_timer_id TIMER_IRQ = 0;
234	234	emu_timer *irq_timer;
235	235	};
r22615	r22616
242	242	public:
243	243	// construction/destruction
244	244	nes_09034a_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
245
	245
246	246	// device-level overrides
247	247	virtual void device_start();
248	248	virtual DECLARE_WRITE8_MEMBER(write_ex);
249	249	virtual DECLARE_READ8_MEMBER(read_m);
250
	250
251	251	virtual void pcb_reset();
252
	252
253	253	private:
254	254	UINT8 m_reg;
255	255	};

trunk/src/mess/machine/nes_legacy.h
r22615	r22616
42	42	protected:
43	43	UINT16 m_irq_count;
44	44	int m_irq_enable;
45
	45
46	46	static const device_timer_id TIMER_IRQ = 0;
47	47	emu_timer *irq_timer;
48
	48
49	49	UINT8 m_latch;
50	50	UINT8 *m_exram;
51	51	int m_exram_enabled;

trunk/src/mess/machine/nes_txc.c
r22615	r22616
14	14	* TXC Mahjong Block [mapper 172]
15	15	* TXC Strike Wolf [mapper 36]
16	16	* TXC Commandos (and many more) [mapper 241]
17
18		TODO:
	17
	18	TODO:
19	19	- Does Commandos indeed use this board?
20	20
21	21

trunk/src/mess/machine/psxcd.c
r22615	r22616
1084	1084	return;
1085	1085	}
1086	1086	send_result(intr_complete);
1087		status \|= status_reading;
	1087	status \|= status_reading;
1088	1088
1089	1089	m_cursec=sectail=0;
1090	1090

trunk/src/mess/video/fm7.c
r22615	r22616
645	645	return 0xff;
646	646
647	647	if(m_alu.command & 0x80) // ALU active, writes to VRAM even when reading it (go figure)
648		{
	648	{
649	649	fm7_alu_function(offset+page);
650	650	}
651	651

trunk/src/mess/video/rmnimbus.c
r22615	r22616
82	82	*/
83	83
84	84	READ16_MEMBER(rmnimbus_state::nimbus_video_io_r)
85		{
	85	{
86	86	int pc=space.device().safe_pc();
87	87	UINT16 result;
88	88
r22615	r22616
242	242	*/
243	243
244	244	WRITE16_MEMBER(rmnimbus_state::nimbus_video_io_w)
245		{
	245	{
246	246	int pc=space.device().safe_pc();
247	247
248	248	if(offset<reg028)

trunk/src/mess/video/cgenie.c
r22615	r22616
57	57	Write to an indexed register of the 6845 CRTC
58	58	***************************************************************************/
59	59	WRITE8_MEMBER( cgenie_state::cgenie_register_w )
60		{
	60	{
61	61	//int addr;
62	62
63	63	switch (m_crt.idx)
r22615	r22616
166	166	Read from an indexed register of the 6845 CRTC
167	167	***************************************************************************/
168	168	READ8_MEMBER( cgenie_state::cgenie_register_r )
169		{
	169	{
170	170	return cgenie_get_register(m_crt.idx);
171	171	}
172	172
r22615	r22616
217	217	Read the index register of the 6845 CRTC
218	218	***************************************************************************/
219	219	READ8_MEMBER( cgenie_state::cgenie_index_r )
220		{
	220	{
221	221	return m_crt.idx;
222	222	}
223	223

trunk/src/mess/video/tx0.c
r22615	r22616
54	54	*/
55	55	void tx0_state::tx0_plot(int x, int y)
56	56	{
57
58	57	/* compute pixel coordinates and plot */
59	58	x = x*crt_window_width/0777;
60	59	y = y*crt_window_height/0777;

trunk/src/mess/video/pc_aga.h
r22615	r22616
44	44	DECLARE_READ16_HANDLER( pc200_cga16le_r );
45	45	DECLARE_WRITE16_HANDLER( pc200_cga16le_w );
46	46
47		#endif
		No newline at end of file
	47	#endif

trunk/src/mess/video/vic4567.h
r22615	r22616
25	25	const char *screen;
26	26	const char *cpu;
27	27
28		vic3_type type;
	28	vic3_type type;
29	29
30	30	devcb_read8 x_cb;
31	31	devcb_read8 y_cb;
32		devcb_read8 button_cb;
	32	devcb_read8 button_cb;
33	33
34	34	devcb_read8 dma_read;
35		devcb_read8 dma_read_color;
	35	devcb_read8 dma_read_color;
36	36	devcb_write_line irq;
37	37
38	38	devcb_write8 port_changed;

trunk/src/mess/includes/cgenie.h
r22615	r22616
85	85	required_device<cpu_device> m_maincpu;
86	86	required_device<cassette_image_device> m_cassette;
87	87	required_device<ram_device> m_ram;
88
	88
89	89	void cgenie_offset_xy();
90	90	int cgenie_get_register(int indx);
91	91	void cgenie_mode_select(int mode);
r22615	r22616
131	131
132	132	DECLARE_WRITE8_MEMBER( cgenie_index_w );
133	133	DECLARE_WRITE8_MEMBER( cgenie_register_w );
134
	134
135	135	};
136	136
137	137

trunk/src/mess/includes/c65.h
r22615	r22616
162	162	DECLARE_READ8_MEMBER( c65_read_io );
163	163	DECLARE_READ8_MEMBER( c65_read_io_dc00 );
164	164	DECLARE_QUICKLOAD_LOAD_MEMBER( cbm_c65 );
165
	165
166	166	int c64_paddle_read( device_t *device, address_space &space, int which );
167	167	void c65_nmi( );
168	168	void c65_irq( int level );

trunk/src/mess/includes/mac.h
r22615	r22616
398	398
399	399	DECLARE_WRITE_LINE_MEMBER(cuda_reset_w);
400	400	DECLARE_WRITE_LINE_MEMBER(adb_linechange_w);
401
	401
402	402	DECLARE_WRITE_LINE_MEMBER(mac_scsi_irq);
403	403
404	404	DECLARE_DIRECT_UPDATE_MEMBER(overlay_opbaseoverride);

trunk/src/mess/includes/amstr_pc.h
r22615	r22616
14	14	public:
15	15	amstrad_pc_state(const machine_config &mconfig, device_type type, const char *tag)
16	16	: pc_state(mconfig, type, tag)
17		{ m_mouse.x =0; m_mouse.y=0;}
	17	{ m_mouse.x =0; m_mouse.y=0;}
18	18
19	19	DECLARE_READ8_MEMBER( pc1640_port60_r );
20	20	DECLARE_WRITE8_MEMBER( pc1640_port60_w );
r22615	r22616
30	30	DECLARE_READ8_MEMBER( pc1640_port3d0_r );
31	31	DECLARE_READ8_MEMBER( pc1640_port4278_r );
32	32	DECLARE_READ8_MEMBER( pc1640_port278_r );
33
	33
34	34	DECLARE_DRIVER_INIT(pc1512);
35		DECLARE_DRIVER_INIT(pc1640);
	35	DECLARE_DRIVER_INIT(pc1640);
36	36	DECLARE_DRIVER_INIT(ppc512);
37	37	DECLARE_DRIVER_INIT(pc200);
38
	38
39	39	private:
40	40	struct {
41	41	UINT8 x,y; //byte clipping needed
r22615	r22616
47	47	UINT8 m_port62;
48	48	UINT8 m_port65;
49	49
50		int m_dipstate;
	50	int m_dipstate;
51	51	};
52	52
53	53	INPUT_PORTS_EXTERN( amstrad_keyboard );

trunk/src/mess/includes/cosmicos.h
r22615	r22616
110	110	DECLARE_DIRECT_UPDATE_MEMBER(cosmicos_direct_update_handler);
111	111
112	112	DECLARE_QUICKLOAD_LOAD_MEMBER( cosmicos );
113
	113
114	114	void set_cdp1802_mode(int mode);
115	115	void clear_input_data();
116	116	void set_ram_mode();

trunk/src/mess/includes/nes.h
r22615	r22616
249	249	SLOT_INTERFACE_INTERNAL("gs2004", NES_GS2004)
250	250	SLOT_INTERFACE_INTERNAL("gs2013", NES_GS2013)
251	251	SLOT_INTERFACE_INTERNAL("tf9in1", NES_TF9IN1)
252		SLOT_INTERFACE_INTERNAL("3dblock", NES_3DBLOCK) // NROM + IRQ?
	252	SLOT_INTERFACE_INTERNAL("3dblock", NES_3DBLOCK) // NROM + IRQ?
253	253	SLOT_INTERFACE_INTERNAL("racermate", NES_RACERMATE) // mapper 168
254	254	SLOT_INTERFACE_INTERNAL("agci_50282", NES_AGCI_50282)
255	255	SLOT_INTERFACE_INTERNAL("dreamtech01", NES_DREAMTECH01)
r22615	r22616
283	283	SLOT_INTERFACE_INTERNAL("tobidase", NES_TOBIDASE) // mapper 120
284	284	SLOT_INTERFACE_INTERNAL("mmalee2", NES_MMALEE) // mapper 55?
285	285	SLOT_INTERFACE_INTERNAL("unl_2708", NES_2708) // mapper 103
286		SLOT_INTERFACE_INTERNAL("unl_lh32", NES_LH32) // used by Monty no Doki Doki Daidassou FDS conversion
	286	SLOT_INTERFACE_INTERNAL("unl_lh32", NES_LH32) // used by Monty no Doki Doki Daidassou FDS conversion
287	287	SLOT_INTERFACE_INTERNAL("unl_lh10", NES_LH10) // used in Fuuun Shaolin Kyo (FDS Conversion)
288	288	SLOT_INTERFACE_INTERNAL("unl_ac08", NES_AC08) // used by Green Beret FDS conversion
289	289	SLOT_INTERFACE_INTERNAL("unl_bb", NES_UNL_BB) // used by a few FDS conversions

trunk/src/mess/includes/europc.h
r22615	r22616
15	15	public:
16	16	europc_pc_state(const machine_config &mconfig, device_type type, const char *tag)
17	17	: pc_state(mconfig, type, tag),
18		m_jim_state(0),
19		m_port61(0) { }
	18	m_jim_state(0),
	19	m_port61(0) { }
20	20
21	21	DECLARE_WRITE8_MEMBER( europc_pio_w );
22	22	DECLARE_READ8_MEMBER( europc_pio_r );
r22615	r22616
27	27
28	28	DECLARE_READ8_MEMBER( europc_rtc_r );
29	29	DECLARE_WRITE8_MEMBER( europc_rtc_w );
30
	30
31	31	TIMER_CALLBACK_MEMBER(europc_rtc_timer);
32
	32
33	33	DECLARE_DRIVER_INIT(europc);
34	34
35	35	void europc_rtc_set_time();

trunk/src/mess/includes/enterp.h
r22615	r22616
64	64	void Nick_UpdateLPT();
65	65	void Nick_ReloadLPT();
66	66	void Nick_DoLine();
67		void Nick_DoScreen(bitmap_ind16 &bm);
	67	void Nick_DoScreen(bitmap_ind16 &bm);
68	68	};
69	69
70	70

trunk/src/mess/includes/vidbrain.h
r22615	r22616
97	97	DECLARE_WRITE_LINE_MEMBER( ext_int_w );
98	98	DECLARE_WRITE_LINE_MEMBER( hblank_w );
99	99	DECLARE_READ8_MEMBER(memory_read_byte);
100
101	100
	101
102	102	IRQ_CALLBACK_MEMBER(vidbrain_int_ack);
103	103
104	104	void interrupt_check();

trunk/src/mess/includes/avigo.h
r22615	r22616
107	107	virtual void palette_init();
108	108	TIMER_DEVICE_CALLBACK_MEMBER(avigo_scan_timer);
109	109	TIMER_DEVICE_CALLBACK_MEMBER(avigo_1hz_timer);
110
	110
111	111	DECLARE_QUICKLOAD_LOAD_MEMBER( avigo);
112	112	};
113	113	#endif /* AVIGO_H_ */

trunk/src/mess/includes/apple2gs.h
r22615	r22616
238	238	UINT8 apple2gs_xxCxxx_r(address_space &space, offs_t address);
239	239	void apple2gs_xxCxxx_w(address_space &space, offs_t address, UINT8 data);
240	240	void apple2gs_setup_memory();
241
	241
242	242	DECLARE_READ8_MEMBER( gssnd_r );
243	243	DECLARE_WRITE8_MEMBER( gssnd_w );
244	244	DECLARE_READ8_MEMBER( apple2gs_00Cxxx_r );
245	245	DECLARE_READ8_MEMBER( apple2gs_01Cxxx_r );
246	246	DECLARE_READ8_MEMBER( apple2gs_E0Cxxx_r );
247	247	DECLARE_READ8_MEMBER( apple2gs_E1Cxxx_r );
248		DECLARE_WRITE8_MEMBER( apple2gs_00Cxxx_w );
249		DECLARE_WRITE8_MEMBER( apple2gs_01Cxxx_w );
250		DECLARE_WRITE8_MEMBER( apple2gs_E0Cxxx_w );
251		DECLARE_WRITE8_MEMBER( apple2gs_E1Cxxx_w );
	248	DECLARE_WRITE8_MEMBER( apple2gs_00Cxxx_w );
	249	DECLARE_WRITE8_MEMBER( apple2gs_01Cxxx_w );
	250	DECLARE_WRITE8_MEMBER( apple2gs_E0Cxxx_w );
	251	DECLARE_WRITE8_MEMBER( apple2gs_E1Cxxx_w );
252	252	DECLARE_WRITE8_MEMBER( apple2gs_Exxxxx_w );
253	253	DECLARE_WRITE8_MEMBER( apple2gs_E004xx_w );
254	254	DECLARE_WRITE8_MEMBER( apple2gs_E02xxx_w );
255	255	DECLARE_WRITE8_MEMBER( apple2gs_E104xx_w );
256	256	DECLARE_WRITE8_MEMBER( apple2gs_E12xxx_w );
257	257	DECLARE_WRITE8_MEMBER( apple2gs_slowmem_w );
258		DECLARE_READ8_MEMBER(apple2gs_bank_echo_r);
	258	DECLARE_READ8_MEMBER(apple2gs_bank_echo_r);
259	259	};
260	260
261	261

trunk/src/mess/includes/hp48.h
r22615	r22616
110	110	#define HP48_IO_8(x) (m_io[(x)] \| (m_io[(x)+1] << 4))
111	111	#define HP48_IO_12(x) (m_io[(x)] \| (m_io[(x)+1] << 4) \| (m_io[(x)+2] << 8))
112	112	#define HP48_IO_20(x) (m_io[(x)] \| (m_io[(x)+1] << 4) \| (m_io[(x)+2] << 8) \| \
113		(m_io[(x)+3] << 12) \| (m_io[(x)+4] << 16))
	113	(m_io[(x)+3] << 12) \| (m_io[(x)+4] << 16))
114	114
115	115
116	116	/----------- defined in machine/hp48.c -----------/

trunk/src/mess/includes/pet.h
r22615	r22616
128	128	DECLARE_WRITE_LINE_MEMBER( pia2_irqb_w );
129	129
130	130	TIMER_DEVICE_CALLBACK_MEMBER( sync_tick );
131
	131
132	132	DECLARE_QUICKLOAD_LOAD_MEMBER( cbm_pet );
133
	133
134	134	enum
135	135	{
136	136	SEL0 = 0,

trunk/src/mess/includes/pcw.h
r22615	r22616
28	28	public:
29	29	pcw_state(const machine_config &mconfig, device_type type, const char *tag)
30	30	: driver_device(mconfig, type, tag),
31		m_maincpu(*this, "maincpu"),
32		m_screen(*this, "screen"),
33		m_fdc(*this, "upd765"),
34		m_ram(*this, RAM_TAG),
35		m_beeper(*this, "beeper")
	31	m_maincpu(*this, "maincpu"),
	32	m_screen(*this, "screen"),
	33	m_fdc(*this, "upd765"),
	34	m_ram(*this, RAM_TAG),
	35	m_beeper(*this, "beeper")
36	36	{ }
37	37
38	38	int m_boot;
r22615	r22616
122	122	required_device<upd765a_device> m_fdc;
123	123	required_device<ram_device> m_ram;
124	124	required_device<beep_device> m_beeper;
125
	125
126	126	inline void pcw_plot_pixel(bitmap_ind16 &bitmap, int x, int y, UINT32 color);
127	127	void pcw_update_interrupt_counter();
128	128	void pcw_update_irqs();

trunk/src/mess/includes/partner.h
r22615	r22616
34	34	void partner_window_2(UINT8 bank_num, UINT16 offset,UINT8 *rom);
35	35	void partner_iomap_bank(UINT8 *rom);
36	36	void partner_bank_switch();
37		required_device<ram_device> m_ram;
	37	required_device<ram_device> m_ram;
38	38	};
39	39
40	40

trunk/src/mess/includes/tvc.h
r22615	r22616
116	116	DECLARE_READ8_MEMBER(tvc_expansion_r);
117	117	DECLARE_READ8_MEMBER(tvc_exp_id_r);
118	118	DECLARE_WRITE8_MEMBER(tvc_expint_ack_w);
119
	119
120	120	DECLARE_QUICKLOAD_LOAD_MEMBER( tvc64);
121	121
122	122	tvcexp_slot_device * m_expansions[4];

trunk/src/mess/includes/tmc1800.h
r22615	r22616
29	29	m_maincpu(*this, CDP1802_TAG),
30	30	m_cassette(*this, "cassette"),
31	31	m_rom(*this, CDP1802_TAG),
32		m_run(*this, "RUN"),
	32	m_run(*this, "RUN"),
33	33	m_ram(*this, RAM_TAG),
34	34	m_beeper(*this, "beeper")
35	35	{ }

trunk/src/mess/includes/x68k.h
r22615	r22616
382	382	void x68k_draw_gfx_scanline(bitmap_ind16 &bitmap, rectangle cliprect, UINT8 priority);
383	383	void x68k_draw_gfx(bitmap_ind16 &bitmap,rectangle cliprect);
384	384	void x68k_draw_sprites(bitmap_ind16 &bitmap, int priority, rectangle cliprect);
385		public:
	385	public:
386	386	required_device<cpu_device> m_maincpu;
387	387	required_device<okim6258_device> m_okim6258;
388	388	required_device<ram_device> m_ram;

trunk/src/mess/includes/nascom1.h
r22615	r22616
63	63	DECLARE_DEVICE_IMAGE_UNLOAD_MEMBER( nascom1_cassette );
64	64	required_device<cpu_device> m_maincpu;
65	65	required_device<cassette_image_device> m_cassette;
66		required_device<ram_device> m_ram;
	66	required_device<ram_device> m_ram;
67	67	DECLARE_SNAPSHOT_LOAD_MEMBER( nascom1 );
68	68	};
69	69

trunk/src/mess/includes/pc.h
r22615	r22616
166	166	int m_turbo_cur_val;
167	167	double m_turbo_off_speed;
168	168	double m_turbo_on_speed;
169
	169
170	170	// keyboard
171	171	void init_pc_common(void (*set_keyb_int_func)(running_machine &, int));
172	172	TIMER_CALLBACK_MEMBER( pc_keyb_timer );
173	173	void pc_keyboard();
174	174	UINT8 pc_keyb_read();
175	175	void pc_keyb_set_clock(int on);
176		void pc_keyb_clear();
	176	void pc_keyb_clear();
177	177	void (*m_pc_keyb_int_cb)(running_machine &, int);
178	178	emu_timer *m_pc_keyb_timer;
179	179	UINT8 m_pc_keyb_data;

trunk/src/mess/includes/vc4000.h
r22615	r22616
90	90	#else
91	91	m_joys(*this, "JOYS"),
92	92	m_config(*this, "CONFIG") { }
93		#endif
	93	#endif
94	94
95	95	DECLARE_WRITE8_MEMBER(vc4000_sound_ctl);
96	96	DECLARE_READ8_MEMBER(vc4000_key_r);

trunk/src/mess/includes/c128.h
r22615	r22616
193	193
194	194	DECLARE_INPUT_CHANGED_MEMBER( restore );
195	195	DECLARE_INPUT_CHANGED_MEMBER( caps_lock );
196
	196
197	197	DECLARE_QUICKLOAD_LOAD_MEMBER( cbm_c64 );
198	198	// memory state
199	199	int m_z80en;

trunk/src/mess/includes/lviv.h
r22615	r22616
56	56	void lviv_setup_snapshot (UINT8 * data);
57	57	void dump_registers();
58	58	int lviv_verify_snapshot (UINT8 * data, UINT32 size);
59		DECLARE_SNAPSHOT_LOAD_MEMBER( lviv );
	59	DECLARE_SNAPSHOT_LOAD_MEMBER( lviv );
60	60	};
61	61
62	62

trunk/src/mess/includes/kc.h
r22615	r22616
149	149	TIMER_CALLBACK_MEMBER(kc_cassette_oneshot_timer);
150	150	TIMER_CALLBACK_MEMBER(kc_cassette_timer_callback);
151	151	TIMER_DEVICE_CALLBACK_MEMBER(kc_scanline);
152
	152
153	153	DECLARE_QUICKLOAD_LOAD_MEMBER( kc );
154	154	};
155	155

trunk/src/mess/includes/electron.h
r22615	r22616
60	60	: driver_device(mconfig, type, tag),
61	61	m_maincpu(*this, "maincpu"),
62	62	m_cassette(*this, "cassette"),
63		m_beeper(*this, "beeper") { }
	63	m_beeper(*this, "beeper") { }
64	64
65	65	ULA m_ula;
66	66	emu_timer *m_tape_timer;

trunk/src/mess/includes/gp32.h
r22615	r22616
229	229	void iic_resume();
230	230	void s3c240x_machine_start();
231	231	void s3c240x_machine_reset();
232		inline rgb_t s3c240x_get_color_5551( UINT16 data);
	232	inline rgb_t s3c240x_get_color_5551( UINT16 data);
233	233	UINT32 s3c240x_lcd_dma_read( );
234	234	void s3c240x_lcd_render_01( );
235	235	void s3c240x_lcd_render_02( );

trunk/src/mess/includes/aim65.h
r22615	r22616
61	61	virtual void machine_start();
62	62	TIMER_CALLBACK_MEMBER(aim65_printer_timer);
63	63	void aim65_pia();
64
	64
65	65	DECLARE_WRITE16_MEMBER(aim65_update_ds1);
66	66	DECLARE_WRITE16_MEMBER(aim65_update_ds2);
67	67	DECLARE_WRITE16_MEMBER(aim65_update_ds3);

trunk/src/mess/includes/tandy1t.h
r22615	r22616
23	23	DECLARE_READ8_MEMBER( tandy1000_bank_r );
24	24	DECLARE_WRITE8_MEMBER( tandy1000_bank_w );
25	25
26		int tandy1000_read_eeprom();
	26	int tandy1000_read_eeprom();
27	27	void tandy1000_write_eeprom(UINT8 data);
28	28	void tandy1000_set_bios_bank();
29
30		DECLARE_MACHINE_RESET(tandy1000rl);
31
	29
	30	DECLARE_MACHINE_RESET(tandy1000rl);
	31
32	32	struct
33	33	{
34	34	UINT8 low, high;
35		} m_eeprom_ee[0x40]; /* only 0 to 4 used in hx, addressing seems to allow this */
36
37		private:
	35	} m_eeprom_ee[0x40]; /* only 0 to 4 used in hx, addressing seems to allow this */
	36
	37	private:
38	38	int m_eeprom_state;
39	39	int m_eeprom_clock;
40	40	UINT8 m_eeprom_oper;

trunk/src/mess/includes/c64.h
r22615	r22616
138	138	DECLARE_WRITE_LINE_MEMBER( exp_reset_w );
139	139
140	140	DECLARE_QUICKLOAD_LOAD_MEMBER( cbm_c64 );
141
	141
142	142	// memory state
143	143	int m_loram;
144	144	int m_hiram;

trunk/src/mess/includes/nc.h
r22615	r22616
110	110	required_device<ram_device> m_ram;
111	111	required_device<beep_device> m_beeper1;
112	112	required_device<beep_device> m_beeper2;
113
	113
114	114	void nc200_video_set_backlight(int state);
115	115	void nc_card_save(device_image_interface &image);
116	116	int nc_card_calculate_mask(int size);

trunk/src/mess/includes/plus4.h
r22615	r22616
120	120	DECLARE_WRITE_LINE_MEMBER( acia_irq_w );
121	121
122	122	DECLARE_WRITE_LINE_MEMBER( exp_irq_w );
123
	123
124	124	DECLARE_QUICKLOAD_LOAD_MEMBER( cbm_c16 );
125	125
126	126	enum

trunk/src/mess/includes/bbc.h
r22615	r22616
32	32	m_trom(*this, "saa505x"),
33	33	m_cassette(*this, "cassette"),
34	34	m_acia(*this, "acia6850"),
35		m_ACCCON_IRR(CLEAR_LINE),
	35	m_ACCCON_IRR(CLEAR_LINE),
36	36	m_via_system_irq(CLEAR_LINE),
37	37	m_via_user_irq(CLEAR_LINE),
38	38	m_acia_irq(CLEAR_LINE),
r22615	r22616
374	374	void MC6850_Receive_Clock(int new_clock);
375	375	void BBC_Cassette_motor(unsigned char status);
376	376	void bbc_update_fdq_int(int state);
377		public:
	377	public:
378	378	unsigned int calculate_video_address(int ma,int ra);
379	379	};
380	380

trunk/src/mess/includes/gb.h
r22615	r22616
214	214	required_memory_region m_region_maincpu;
215	215	optional_memory_bank m_rambank; // cgb
216	216	required_ioport m_inputs;
217		optional_device<ram_device> m_ram;
	217	optional_device<ram_device> m_ram;
218	218
219	219	void gb_timer_increment();
220	220	void gb_timer_check_irq();

trunk/src/mess/includes/x1.h
r22615	r22616
223	223	int priority_mixer_pri(int color);
224	224	void cmt_command( UINT8 cmd );
225	225	UINT16 jis_convert(int kanji_addr);
226
	226
227	227	DECLARE_READ8_MEMBER(memory_read_byte);
228	228	DECLARE_WRITE8_MEMBER(memory_write_byte);
229	229	DECLARE_READ8_MEMBER(io_read_byte);

trunk/src/mess/includes/trs80m2.h
r22615	r22616
127	127
128	128	TIMER_DEVICE_CALLBACK_MEMBER(ctc_tick);
129	129	DECLARE_READ8_MEMBER(io_read_byte);
130		DECLARE_WRITE8_MEMBER(io_write_byte);
	130	DECLARE_WRITE8_MEMBER(io_write_byte);
131	131	};
132	132
133	133	class trs80m16_state : public trs80m2_state

trunk/src/mess/drivers/dmv.c
r22615	r22616
49	49	DECLARE_READ8_MEMBER(fdc_dma_r);
50	50	DECLARE_WRITE8_MEMBER(fdc_dma_w);
51	51	DECLARE_READ8_MEMBER(memory_read_byte);
52		DECLARE_WRITE8_MEMBER(memory_write_byte);
	52	DECLARE_WRITE8_MEMBER(memory_write_byte);
53	53
54	54	void fdc_irq(bool state);
55	55	void fdc_drq(bool state);

trunk/src/mess/drivers/mz3500.c
r22615	r22616
58	58	required_device<upd765a_device> m_fdc;
59	59	required_shared_ptr<UINT8> m_video_ram;
60	60	required_device<beep_device> m_beeper;
61
	61
62	62	UINT8 *m_ipl_rom;
63	63	UINT8 *m_basic_rom;
64	64	UINT8 *m_work_ram;

trunk/src/mess/drivers/mini2440.c
r22615	r22616
49	49	DECLARE_WRITE8_MEMBER(s3c2440_nand_data_w );
50	50	DECLARE_WRITE16_MEMBER(s3c2440_i2s_data_w );
51	51	DECLARE_READ32_MEMBER(s3c2440_adc_data_r );
52
	52
53	53	};
54	54
55	55	inline void ATTR_PRINTF(3,4) mini2440_state::verboselog( int n_level, const char *s_fmt, ...)

trunk/src/mess/drivers/bebox.c
r22615	r22616
159	159	}
160	160	}
161	161
162		READ8_MEMBER(bebox_state::bebox_get_out2)
	162	READ8_MEMBER(bebox_state::bebox_get_out2)
163	163	{
164	164	return pit8253_get_output(machine().device("pit8254"), 2 );
165	165	}
r22615	r22616
171	171	DEVCB_NULL,
172	172	DEVCB_DRIVER_LINE_MEMBER(bebox_state,bebox_keyboard_interrupt),
173	173	DEVCB_NULL,
174
	174
175	175	DEVCB_NULL,
176	176	DEVCB_DRIVER_MEMBER(bebox_state,bebox_get_out2)
177	177	};

trunk/src/mess/drivers/merlin.c
r22615	r22616
17	17	public:
18	18	merlin_state(const machine_config &mconfig, device_type type, const char *tag)
19	19	: driver_device(mconfig, type, tag),
20		m_speaker(*this, "speaker") ,
	20	m_speaker(*this, "speaker") ,
21	21	m_maincpu(*this, "maincpu") { }
22	22
23	23	virtual void machine_start();

trunk/src/mess/drivers/bigbord2.c
r22615	r22616
150	150	DECLARE_READ8_MEMBER(memory_read_byte);
151	151	DECLARE_WRITE8_MEMBER(memory_write_byte);
152	152	DECLARE_READ8_MEMBER(io_read_byte);
153		DECLARE_WRITE8_MEMBER(io_write_byte);
	153	DECLARE_WRITE8_MEMBER(io_write_byte);
154	154	};
155	155
156	156	/* Status port

trunk/src/mess/drivers/palmz22.c
r22615	r22616
149	149	/*
150	150	READ8_MEMBER( palmz22_state::s3c2410_nand_busy_r )
151	151	{
152		UINT8 data = m_nand->is_busy();
153		verboselog(9, "s3c2410_nand_busy_r %02X\n", data);
154		return data;
	152	UINT8 data = m_nand->is_busy();
	153	verboselog(9, "s3c2410_nand_busy_r %02X\n", data);
	154	return data;
155	155	}
156	156	*/
157	157

trunk/src/mess/drivers/ip22.c
r22615	r22616
1498	1498	DEVCB_NULL,
1499	1499	DEVCB_NULL,
1500	1500	DEVCB_NULL,
1501
	1501
1502	1502	DEVCB_NULL,
1503		DEVCB_DRIVER_MEMBER(ip22_state,ip22_get_out2)
	1503	DEVCB_DRIVER_MEMBER(ip22_state,ip22_get_out2)
1504	1504	};
1505	1505
1506	1506	DRIVER_INIT_MEMBER(ip22_state,ip225015)
r22615	r22616
1642	1642	MCFG_SOUND_MODIFY( "scsi:cdrom:cdda" )
1643	1643	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "^^^lspeaker", 1.0)
1644	1644	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "^^^rspeaker", 1.0)
1645
	1645
1646	1646	MCFG_KBDC8042_ADD("kbdc", at8042)
1647	1647	MACHINE_CONFIG_END
1648	1648

trunk/src/mess/drivers/tsispch.c
r22615	r22616
207	207	and (probably) the p0-to-ir0 masking of the upd77p20; there are two
208	208	unknown and seemingly unused bits as well.
209	209	see the top of the file for more info.
210		*/
	210	*/
211	211	m_paramReg = data;
212	212	m_dsp->set_input_line(INPUT_LINE_RESET, BIT(data,6)?CLEAR_LINE:ASSERT_LINE);
213	213	#ifdef DEBUG_PARAM

trunk/src/mess/drivers/fk1.c
r22615	r22616
25	25
26	26	required_device<cpu_device> m_maincpu;
27	27	required_device<ram_device> m_ram;
28
	28
29	29	DECLARE_WRITE8_MEMBER(fk1_ppi_1_a_w);
30	30	DECLARE_WRITE8_MEMBER(fk1_ppi_1_b_w);
31	31	DECLARE_WRITE8_MEMBER(fk1_ppi_1_c_w);

trunk/src/mess/drivers/p8k.c
r22615	r22616
110	110	DECLARE_READ8_MEMBER(memory_read_byte);
111	111	DECLARE_WRITE8_MEMBER(memory_write_byte);
112	112	DECLARE_READ8_MEMBER(io_read_byte);
113		DECLARE_WRITE8_MEMBER(io_write_byte);
	113	DECLARE_WRITE8_MEMBER(io_write_byte);
114	114	};
115	115
116	116	/***************************************************************************

trunk/src/mess/drivers/coco3.c
r22615	r22616
40	40	AM_RANGE(0xFF40, 0xFF5F) AM_READWRITE(ff40_read, ff40_write)
41	41	AM_RANGE(0xFF60, 0xFF8F) AM_READWRITE(ff60_read, ff60_write)
42	42	AM_RANGE(0xFF90, 0xFFDF) AM_DEVREADWRITE(GIME_TAG, gime_base_device, read, write)
43
	43
44	44	// While Tepolt and other sources say that the interrupt vectors are mapped to
45	45	// the same memory accessed at $BFFx, William Astle offered evidence that this
46	46	// memory on a CoCo 3 is not the same.

trunk/src/mess/drivers/pc9801.c
r22615	r22616
382	382	required_shared_ptr<UINT8> m_video_ram_1;
383	383	required_shared_ptr<UINT8> m_video_ram_2;
384	384	required_device<beep_device> m_beeper;
385		optional_device<ram_device> m_ram;
	385	optional_device<ram_device> m_ram;
386	386
387	387	virtual void video_start();
388	388	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);

trunk/src/mess/drivers/fmtowns.c
r22615	r22616
1930	1930
1931	1931	void towns_state::rtc_hour()
1932	1932	{
1933
1934	1933	m_towns_rtc_reg[4]++;
1935	1934	if(m_towns_rtc_reg[4] > 4 && m_towns_rtc_reg[5] == 2)
1936	1935	{
r22615	r22616
1946	1945
1947	1946	void towns_state::rtc_minute()
1948	1947	{
1949
1950	1948	m_towns_rtc_reg[2]++;
1951	1949	if(m_towns_rtc_reg[2] > 9)
1952	1950	{

trunk/src/mess/drivers/kyocera.c
r22615	r22616
42	42	- tandy200 TCM5089 DTMF sound
43	43	- international keyboard option ROMs
44	44
45		10 FOR A=0 TO 255
46		20 PRINT CHR$(A);
47		30 NEXT A
	45	10 FOR A=0 TO 255
	46	20 PRINT CHR$(A);
	47	30 NEXT A
48	48
49	49	*/
50	50

trunk/src/mess/audio/vrc6.c
r22615	r22616
4	4	Konami VRC6 additional sound channels
5	5
6	6	Emulation by R. Belmont
7
	7
8	8	References:
9	9	http://wiki.nesdev.com/w/index.php/VRC6_audio
10		http://nesdev.com/vrcvi.txt
11
	10	http://nesdev.com/vrcvi.txt
	11
12	12	***************************************************************************/
13	13
14	14	#include "emu.h"
15	15	#include "vrc6.h"
16	16
17		#define DISABLE_VRC6_SOUND // not ready yet
	17	#define DISABLE_VRC6_SOUND // not ready yet
18	18
19	19	// device type definition
20	20	const device_type VRC6 = &device_creator<vrc6snd_device>;
r22615	r22616
29	29
30	30	vrc6snd_device::vrc6snd_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
31	31	: device_t(mconfig, VRC6, "VRC6 sound", tag, owner, clock),
32		device_sound_interface(mconfig, *this)
	32	device_sound_interface(mconfig, *this)
33	33	{
34	34	}
35	35
r22615	r22616
175	175	{
176	176	m_ticks[2]--;
177	177	if (m_ticks[2] == 0)
178		{
	178	{
179	179	m_ticks[2] = m_sawfrql \| (m_sawfrqh & 0xf)<<4;
180	180
181	181	// only update on even steps
r22615	r22616
199	199	}
200	200
201	201	// sum 2 4-bit pulses, 1 5-bit saw = unsigned 6 bit output
202		tmp = (INT16)(UINT8)(m_output[0] + m_output[1] + m_output[2]);
	202	tmp = (INT16)(UINT8)(m_output[0] + m_output[1] + m_output[2]);
203	203	tmp <<= 8;
204	204
205	205	out[i] = tmp;
r22615	r22616
316	316	}
317	317
318	318	}
319
320

trunk/src/mess/audio/vrc6.h
r22615	r22616
57	57
58	58
59	59	#endif /* __VRC6_H__ */
60
61

199869 Revisions