MAME SVN History

199869 Revisions

r22614 Monday 29th April, 2013 at 22:40:10 UTC by David Haywood
preparation for some fruit machine work I'm doing (nw)

[src/emu]	emu.mak
[src/emu/machine]	mcf5206e.c* mcf5206e.h*
[src/mame/drivers]	bfm_sc5.c gamtor.c seta2.c
[src/mame/includes]	bfm_sc5.h seta2.h

trunk/src/emu/emu.mak
r22613	r22614
228	228	$(EMUMACHINE)/mc6854.o \
229	229	$(EMUMACHINE)/mc68901.o \
230	230	$(EMUMACHINE)/mccs1850.o \
	231	$(EMUMACHINE)/mcf5206e.o \
231	232	$(EMUMACHINE)/microtch.o \
232	233	$(EMUMACHINE)/mm58274c.o \
233	234	$(EMUMACHINE)/mm74c922.o \

trunk/src/emu/machine/mcf5206e.c
r0	r22614
	1	/* Modern device for the MCF5206e Peripherals
	2	this can be hooked properly to the CPU once the CPU is a modern device too
	3	*/
	4
	5	#include "emu.h"
	6	#include "mcf5206e.h"
	7
	8
	9	//**************************************************************************
	10	// LIVE DEVICE
	11	//**************************************************************************
	12
	13	// device type definition
	14	const device_type MCF5206E_PERIPHERAL = &device_creator<mcf5206e_peripheral_device>;
	15
	16	//-------------------------------------------------
	17	// mcf5206e_peripheral_device - constructor
	18	//-------------------------------------------------
	19
	20	mcf5206e_peripheral_device::mcf5206e_peripheral_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	21	: device_t(mconfig, MCF5206E_PERIPHERAL, "MCF5206E Peripheral", tag, owner, clock)
	22	{
	23	}
	24
	25	//-------------------------------------------------
	26	// device_config_complete - perform any
	27	// operations now that the configuration is
	28	// complete
	29	//-------------------------------------------------
	30
	31	void mcf5206e_peripheral_device::device_config_complete()
	32	{
	33
	34	}
	35
	36
	37	//-------------------------------------------------
	38	// device_start - device-specific startup
	39	//-------------------------------------------------
	40
	41	void mcf5206e_peripheral_device::device_start()
	42	{
	43
	44	}
	45
	46
	47
	48	READ32_MEMBER(mcf5206e_peripheral_device::dev_r)
	49	{
	50	return 0;
	51	}
	52
	53	WRITE32_MEMBER(mcf5206e_peripheral_device::dev_w)
	54	{
	55
	56	}
	57
	58
	59	// ColdFire peripherals
	60
	61	enum {
	62	CF_PPDAT = 0x1c8/4,
	63	CF_MBSR = 0x1ec/4
	64	};
	65
	66	WRITE32_MEMBER(mcf5206e_peripheral_device::seta2_coldfire_regs_w)
	67	{
	68	COMBINE_DATA( &m_coldfire_regs[offset] );
	69	}
	70
	71	READ32_MEMBER(mcf5206e_peripheral_device::seta2_coldfire_regs_r)
	72	{
	73	switch( offset )
	74	{
	75	case CF_MBSR:
	76	return machine().rand();
	77
	78	case CF_PPDAT:
	79	return ioport(":BATTERY")->read() << 16;
	80	}
	81
	82	return m_coldfire_regs[offset];
	83	}
	84
	85	/*
	86
	87	ADDRESS REG WIDTH NAME/DESCRIPTION INIT VALUE (MR=Master Reset, NR=Normal Reset) Read or Write access
	88
	89	op MOVEC with $C0F MBAR 32 Module Base Address Register uninit (except V=0) W
	90	$003 SIMR 8 SIM Configuration Register C0 R/W
	91	$014 ICR1 8 Interrupt Control Register 1 - External IRQ1/IPL1 04 R/W
	92	$015 ICR2 8 Interrupt Control Register 2 - External IPL2 08 R/W
	93	$016 ICR3 8 Interrupt Control Register 3 - External IPL3 0C R/W
	94	$017 ICR4 8 Interrupt Control Register 4 - External IRQ4/IPL4 10 R/W
	95	$018 ICR5 8 Interrupt Control Register 5 - External IPL5 14 R/W
	96	$019 ICR6 8 Interrupt Control Register 6 - External IPL6 18 R/W
	97	$01A ICR7 8 Interrupt Control Register 7 - External IRQ7/IPL7 1C R/W
	98	$01B ICR8 8 Interrupt Control Register 8 - SWT 1C R/W
	99	$01C ICR9 8 Interrupt Control Register 9 - Timer 1 Interrupt 80 R/W
	100	$01D ICR10 8 Interrupt Control Register 10 - Timer 2 Interrupt 80 R/W
	101	$01E ICR11 8 Interrupt Control Register 11 - MBUS Interrupt 80 R/W
	102	$01F ICR12 8 Interrupt Control Register 12 - UART 1 Interrupt 00 R/W
	103	$020 ICR13 8 Interrupt Control Register 13 - UART 2 Interrupt 00 R/W
	104	$036 IMR 16 Interrupt Mask Register 3FFE R/W
	105	$03A IPR 16 Interrupt Pending Register 0000 R
	106	$040 RSR 8 Reset Status Register 80 / 20 R/W
	107	$041 SYPCR 8 System Protection Control Register 00 R/W
	108	$042 SWIVR 8 Software Watchdog Interrupt Vector Register 0F R/W
	109	$043 SWSR 8 Software Watchdog Service Register uninit W
	110	$046 DCRR 16 DRAM Controller Refresh MR 0000 - NR uninit R/W
	111	$04A DCTR 16 DRAM Controller Timing Register MR 0000 - NR uninit R/W
	112	$04C DCAR0 16 DRAM Controller 0 Address Register MR uninit - NR uninit R/W
	113	$050 DCMR0 32 DRAM Controller 0 Mask Register MR uninit - NR uninit R/W
	114	$057 DCCR0 8 DRAM Controller 0 Control Register MR 00 - NR 00 R/W
	115	$058 DCAR1 16 DRAM Controller 1 Address Register MR uninit - NR uninit R/W
	116	$05C DCMR1 32 DRAM Controller 1 Mask Register MR uninit - NR uninit R/W
	117	$063 DCCR1 8 DRAM Controller 1 Control Register MR 00 - NR 00 R/W
	118	--------- CHIP SELECTS -----------
	119	$064 CSAR0 16 Chip-Select 0 Address Register 0000 R/W
	120	$068 CSMR0 32 Chip-Select 0 Mask Register 00000000 R/W
	121	$06E CSCR0 16 Chip-Select 0 Control Register 3C1F, 3C5F, 3C9F, 3CDF, 3D1F, 3D5F, 3D9F, 3DDF R/W
	122	AA set by IRQ 7 at reset
	123	PS1 set by IRQ 4 at reset
	124	PS0 set by IRQ 1 at reset
	125	$070 CSAR1 16 Chip-Select 1 Address Register uninit R/W
	126	$074 CSMR1 32 Chip-Select 1 Mask Register uninit R/W
	127	$07A CSCR1 16 Chip-Select 1 Control Register uninit *1 R/W
	128	$07C CSAR2 16 Chip-Select 2 Address Register uninit R/W
	129	$080 CSMR2 32 Chip-Select 2 Mask Register uninit R/W
	130	$086 CSCR2 16 Chip-Select 2 Control Register uninit *1 R/W
	131	$088 CSAR3 16 Chip-Select 3 Address Register uninit R/W
	132	$08C CSMR3 32 Chip-Select 3 Mask Register uninit R/W
	133	$092 CSCR3 16 Chip-Select 3 Control Register uninit *1 R/W
	134	$094 CSAR4 16 Chip-Select 4 Address Register uninit R/W
	135	$098 CSMR4 32 Chip-Select 4 Mask Register uninit R/W
	136	$09E CSCR4 16 Chip-Select 4 Control Register uninit *1 R/W
	137	$0A0 CSAR5 16 Chip-Select 5 Address Register uninit R/W
	138	$0A4 CSMR5 32 Chip-Select 5 Mask Register uninit R/W
	139	$0AA CSCR5 16 Chip-Select 5 Control Register uninit *1 R/W
	140	$0AC CSAR6 16 Chip-Select 6 Address Register uninit R/W
	141	$0B0 CSMR6 32 Chip-Select 6 Mask Register uninit R/W
	142	$0B6 CSCR6 16 Chip-Select 6 Control Register uninit *1 R/W
	143	$0B8 CSAR7 16 Chip-Select 7 Address Register uninit R/W
	144	$0BC CSMR7 32 Chip-Select 7 Mask Register uninit R/W
	145	$0C2 CSCR7 16 Chip-Select 7 Control Register uninit *1 R/W
	146	$0C6 DMCR 16 Default Memory Control Register 0000 R/W
	147	$0CA PAR 16 Pin Assignment Register 00 R/W
	148	--------- TIMER MODULE -----------
	149	$100 TMR1 16 Timer 1 Mode Register 0000 R/W
	150	$104 TRR1 16 Timer 1 Reference Register FFFF R/W
	151	$108 TCR1 16 Timer 1 Capture Register 0000 R
	152	$10C TCN1 16 Timer 1 Counter 0000 R/W
	153	$111 TER1 8 Timer 1 Event Register 00 R/W
	154	$120 TMR2 16 Timer 2 Mode Register 0000 R/W
	155	$124 TRR2 16 Timer 2 Reference Register FFFF R/W
	156	$128 TCR2 16 Timer 2 Capture Register 0000 R
	157	$12C TCN2 16 Timer 2 Counter 0000 R/W
	158	$131 TER2 8 Timer 2 Event Register 00 R/W
	159	------------ UART SERIAL PORTS -----------
	160	$140 UMR1,2 8 UART 1 Mode Registers 00 R/W
	161	$144 USR 8 UART 1 Status Register 00 R
	162	UCSR 8 UART 1 Clock-Select Register DD W
	163	$148 UCR 8 UART 1 Command Register 00 W
	164	$14C URB 8 UART 1 Receive Buffer FF R
	165	UTB 8 UART 1 Transmit Buffer 00 W
	166	$150 UIPCR 8 UART Input Port Change Register 0F R
	167	UACR 8 UART 1 Auxilary Control Register 00 W
	168	$154 UISR 8 UART 1 Interrupt Status Register 00 R
	169	UIMR 8 UART 1 Interrupt Mask Register 00 W
	170	$158 UBG1 8 UART 1 Baud Rate Generator Prescale MSB uninit W
	171	$15C UBG2 8 UART 1 Baud Rate Generator Prescale LSB uninit W
	172	$170 UIVR 8 UART 1 Interrupt Vector Register 0F R/W
	173	$174 UIP 8 UART 1 Input Port Register FF R
	174	$178 UOP1 8 UART 1 Output Port Bit Set CMD UOP1[7-1]=undef; UOP1=0 W
	175	$17C UOP0 8 UART 1 Output Port Bit Reset CMD uninit W
	176
	177	$180 UMR1,2 8 UART 2 Mode Registers 00 R/W
	178	$184 USR 8 UART 2 Status Register 00 R
	179	UCSR 8 UART 2 Clock-Select Register DD W
	180	$188 UCR 8 UART 2 Command Register 00 W
	181	$18C URB 8 UART 2 Receive Buffer FF R
	182	UTB 8 UART 2 Transmit Buffer 00 W
	183	$190 UIPCR 8 UART 2 Input Port Change Register 0F R
	184	UACR 8 UART 2 Auxilary Control Register 00 W
	185	$194 UISR 8 UART 2 Interrupt Status Register 00 R
	186	UIMR 8 UART 2 Interrupt Mask Register 00 W
	187	$198 UBG1 8 UART 2 Baud Rate Generator Prescale MSB uninit R/W
	188	$19C UBG2 8 UART 2 Barud Rate Generator Prescale LSB uninit R/W
	189	$1B0 UIVR 8 UART 2 Interrupt Vector Register 0F R/W
	190	$1B4 UIP 8 UART 2 Input Port Register FF R
	191	$1B8 UOP1 8 UART 2 Output Port Bit Set CMD UOP1[7-1]=undef; UOP1=0 W
	192	$1BC UOP0 8 UART 2 Output Port Bit Reset CMD uninit W
	193
	194	$1C5 PPDDR 8 Port A Data Direction Register 00 R/W
	195	$1C9 PPDAT 8 Port A Data Register 00 R/W
	196	------------ MBUS -----------
	197	$1E0 MADR 8 M-Bus Address Register 00 R/W
	198	$1E4 MFDR 8 M-Bus Frequency Divider Register 00 R/W
	199	$1E8 MBCR 8 M-Bus Control Register 00 R/W
	200	$1EC MBSR 8 M-Bus Status Register 00 R/W
	201	$1F0 MBDR 8 M-Bus Data I/O Register 00 R/W
	202	------------ DMA Controller -----------
	203	$200 DMASAR0 32 Source Address Register 0 00 R/W
	204	$204 DMADAR0 32 Destination Address Register 0 00 R/W
	205	$208 DCR0 16 DMA Control Register 0 00 R/W
	206	$20C BCR0 16 Byte Count Register 0 00 R/W
	207	$210 DSR0 8 Status Register 0 00 R/W
	208	$214 DIVR0 8 Interrupt Vector Register 0 0F R/W
	209	$240 DMASAR1 32 Source Address Register 1 00 R/W
	210	$244 DMADAR1 32 Destination Address Register 1 00 R/W
	211	$248 DCR1 16 DMA Control Register 1 00 R/W
	212	$24C BCR1 16 Byte Count Register 1 00 R/W
	213	$250 DSR1 8 Status Register 1 00 R/W
	214	$254 DIVR1 8 Interrupt Vector Register 1 0F R/W
	215
	216	*1 - uninit except BRST=ASET=WRAH=RDAH=WR=RD=0
	217
	218	*/
		No newline at end of file

Property changes on: trunk/src/emu/machine/mcf5206e.c
Added: svn:mime-type + text/plain Added: svn:eol-style + native

trunk/src/emu/machine/mcf5206e.h
r0	r22614
	1	/***************************************************************************
	2
	3	Konami 033906
	4
	5	***************************************************************************/
	6
	7	#pragma once
	8
	9	#ifndef __MCF5206E_PERIPHERAL_H__
	10	#define __MCF5206E_PERIPHERAL_H__
	11
	12	#include "emu.h"
	13
	14
	15
	16	/***************************************************************************
	17	DEVICE CONFIGURATION MACROS
	18	***************************************************************************/
	19
	20	#define MCFG_MCF5206E_PERIPHERAL_ADD(_tag) \
	21	MCFG_DEVICE_ADD(_tag, MCF5206E_PERIPHERAL, 0) \
	22
	23
	24	/***************************************************************************
	25	TYPE DEFINITIONS
	26	***************************************************************************/
	27
	28
	29
	30	// ======================> mcf5206e_peripheral_device
	31
	32	class mcf5206e_peripheral_device : public device_t
	33	{
	34	public:
	35	// construction/destruction
	36	mcf5206e_peripheral_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	37
	38	DECLARE_READ32_MEMBER( dev_r );
	39	DECLARE_WRITE32_MEMBER( dev_w );
	40	DECLARE_READ32_MEMBER( seta2_coldfire_regs_r );
	41	DECLARE_WRITE32_MEMBER( seta2_coldfire_regs_w );
	42
	43	protected:
	44	// device-level overrides
	45	virtual void device_config_complete();
	46	virtual void device_start();
	47	virtual void device_reset() { }
	48	virtual void device_post_load() { }
	49	virtual void device_clock_changed() { }
	50	UINT32 m_coldfire_regs[0x400/4];
	51
	52	private:
	53	};
	54
	55
	56	// device type definition
	57	extern const device_type MCF5206E_PERIPHERAL;
	58
	59	#endif /* __MCF5206E_PERIPHERAL_H__ */

Property changes on: trunk/src/emu/machine/mcf5206e.h
Added: svn:eol-style + native Added: svn:mime-type + text/plain

trunk/src/mame/drivers/bfm_sc5.c
r22613	r22614
11	11
12	12	#include "emu.h"
13	13	#include "includes/bfm_sc5.h"
	14	#include "machine/mcf5206e.h"
14	15
15	16
16	17	static ADDRESS_MAP_START( sc5_map, AS_PROGRAM, 32, bfm_sc5_state )
17	18	AM_RANGE(0x00000000, 0x002fffff) AM_ROM
18	19	AM_RANGE(0x01000000, 0x0100ffff) AM_RAM
19		AM_RANGE(0x40000000, 0x40000fff) AM_RAM
	20	AM_RANGE(0x40000000, 0x4000ffff) AM_RAM
	21
	22	AM_RANGE(0xffff0000, 0xffff03ff) AM_DEVREADWRITE("maincpu_onboard", mcf5206e_peripheral_device, dev_r, dev_w) // technically this can be moved with MBAR
20	23	ADDRESS_MAP_END
21	24
22	25	INPUT_PORTS_START( bfm_sc5 )
23	26	INPUT_PORTS_END
24	27
	28
	29
	30	WRITE_LINE_MEMBER(bfm_sc5_state::bfm_sc5_ym_irqhandler)
	31	{
	32	logerror("YMZ280 is generating an interrupt. State=%08x\n",state);
	33	}
	34
	35	static const ymz280b_interface ymz280b_config =
	36	{
	37	DEVCB_DRIVER_LINE_MEMBER(bfm_sc5_state,bfm_sc5_ym_irqhandler)
	38	};
	39
	40
25	41	INTERRUPT_GEN_MEMBER(bfm_sc5_state::sc5_fake_timer_int)
26	42	{
27	43	// this should be coming from the Timer / SIM modules of the Coldfire
r22613	r22614
32	48	MCFG_CPU_ADD("maincpu", MCF5206E, 40000000) /* MCF5206eFT */
33	49	MCFG_CPU_PROGRAM_MAP(sc5_map)
34	50	MCFG_CPU_PERIODIC_INT_DRIVER(bfm_sc5_state, sc5_fake_timer_int, 1000)
	51	MCFG_MCF5206E_PERIPHERAL_ADD("maincpu_onboard")
35	52
36		MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
37		/* unknown sound */
	53	/* sound hardware */
	54	MCFG_SPEAKER_STANDARD_MONO("mono")
	55
	56	MCFG_SOUND_ADD("ymz", YMZ280B, 16000000) // ?? Mhz
	57	MCFG_SOUND_CONFIG(ymz280b_config)
	58	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
38	59	MACHINE_CONFIG_END

trunk/src/mame/drivers/seta2.c
r22613	r22614
116	116	#include "machine/eeprom.h"
117	117	#include "machine/nvram.h"
118	118	#include "machine/ticket.h"
	119	#include "machine/mcf5206e.h"
119	120
120	121	/***************************************************************************
121	122
r22613	r22614
545	546
546	547	// Main CPU
547	548
548		// ColdFire peripherals
549	549
550		enum {
551		CF_PPDAT = 0x1c8/4,
552		CF_MBSR = 0x1ec/4
553		};
554
555		WRITE32_MEMBER(seta2_state::coldfire_regs_w)
556		{
557		COMBINE_DATA( &m_coldfire_regs[offset] );
558		}
559
560		READ32_MEMBER(seta2_state::coldfire_regs_r)
561		{
562		switch( offset )
563		{
564		case CF_MBSR:
565		return machine().rand();
566
567		case CF_PPDAT:
568		return ioport("BATTERY")->read() << 16;
569		}
570
571		return m_coldfire_regs[offset];
572		}
573
574	550	READ32_MEMBER(seta2_state::funcube_debug_r)
575	551	{
576	552	UINT32 ret = ioport("DEBUG")->read();
r22613	r22614
615	591
616	592	AM_RANGE( 0x00c00000, 0x00c002ff ) AM_READWRITE(funcube_nvram_dword_r, funcube_nvram_dword_w )
617	593
618		AM_RANGE(0xf0000000, 0xf00001ff ) AM_READWRITE(coldfire_re~~gs_~~r, coldfire_regs_w ~~) AM~~_~~SHARE("~~coldfire_regs") // ~~Modu~~le
	594	AM_RANGE(0xf0000000, 0xf00001ff) AM_DEVREADWRITE("maincpu_onboard", mcf5206e_peripheral_device, seta2_coldfire_regs_r, seta2_coldfire_regs_w) // technically this can be moved with MBAR
619	595	AM_RANGE(0xffffe000, 0xffffffff ) AM_RAM // SRAM
620	596	ADDRESS_MAP_END
621	597
r22613	r22614
634	610
635	611	AM_RANGE( 0x00c00000, 0x00c002ff ) AM_READWRITE(funcube_nvram_dword_r, funcube_nvram_dword_w )
636	612
637		AM_RANGE(0xf0000000, 0xf00001ff ) AM_READWRITE(coldfire_re~~gs_~~r, coldfire_regs_w ~~) AM~~_~~SHARE("~~coldfire_regs") // ~~Modu~~le
	613	AM_RANGE(0xf0000000, 0xf00001ff) AM_DEVREADWRITE("maincpu_onboard", mcf5206e_peripheral_device, seta2_coldfire_regs_r, seta2_coldfire_regs_w) // technically this can be moved with MBAR
638	614	AM_RANGE(0xffffe000, 0xffffffff ) AM_RAM // SRAM
639	615	ADDRESS_MAP_END
640	616
r22613	r22614
2212	2188	MCFG_CPU_IO_MAP(funcube_sub_io)
2213	2189	MCFG_CPU_PERIODIC_INT_DRIVER(seta2_state, funcube_sub_timer_irq, 60*10)
2214	2190
	2191	MCFG_MCF5206E_PERIPHERAL_ADD("maincpu_onboard")
	2192
2215	2193	MCFG_NVRAM_ADD_0FILL("nvram")
2216	2194
2217	2195	MCFG_MACHINE_RESET_OVERRIDE(seta2_state, funcube )

trunk/src/mame/drivers/gamtor.c
r22613	r22614
27	27	#include "emu.h"
28	28	#include "cpu/m68000/m68000.h"
29	29	#include "video/pc_vga.h"
	30	#include "machine/mcf5206e.h"
30	31
31	32	class gaminator_state : public driver_device
32	33	{
r22613	r22614
77	78	MCFG_CPU_ADD("maincpu", MCF5206E, 40000000) /* definitely Coldfire, model / clock uncertain */
78	79	MCFG_CPU_PROGRAM_MAP(gaminator_map)
79	80	MCFG_CPU_VBLANK_INT_DRIVER("screen", gaminator_state, irq6_line_hold) // irq6 seems to be needed to get past the ROM checking
	81	MCFG_MCF5206E_PERIPHERAL_ADD("maincpu_onboard")
80	82
81	83	MCFG_FRAGMENT_ADD( pcvideo_gamtor_vga )
82	84

trunk/src/mame/includes/bfm_sc5.h
r22613	r22614
16	16	public:
17	17	DECLARE_DRIVER_INIT(sc5);
18	18	INTERRUPT_GEN_MEMBER(sc5_fake_timer_int);
	19	DECLARE_WRITE_LINE_MEMBER(bfm_sc5_ym_irqhandler);
	20
19	21	};

trunk/src/mame/includes/seta2.h
r22613	r22614
10	10	m_nvram(*this, "nvram") ,
11	11	m_spriteram(*this, "spriteram", 0),
12	12	m_vregs(*this, "vregs", 0),
13		m_coldfire_regs(*this, "coldfire_regs"),
14	13	m_funcube_outputs(*this, "funcube_outputs"),
15	14	m_funcube_leds(*this, "funcube_leds"),
16	15	m_oki(*this, "oki"),
r22613	r22614
21	20
22	21	optional_shared_ptr<UINT16> m_spriteram;
23	22	optional_shared_ptr<UINT16> m_vregs;
24		optional_shared_ptr<UINT32> m_coldfire_regs;
25	23
26	24	optional_shared_ptr<UINT8> m_funcube_outputs;
27	25	optional_shared_ptr<UINT8> m_funcube_leds;

199869 Revisions