Previous

199869 Revisions

Next

r22593 Sunday 28th April, 2013 at 15:34:30 UTC by R. Belmont
Games added as GAME_NOT_WORKING ------------------------------- Pinball 2000: Star Wars Episode 1 [R. Belmont, José Renato Castro Milanez] Pinball 2000: Revenge From Mars (rev. 1) [R. Belmont, José Renato Castro Milanez] Pinball 2000: Revenge From Mars (rev. 2) [José Renato Castro Milanez]

[src/mame]	mame.lst mame.mak
[src/mame/drivers]	pinball2k.c*

trunk/src/mame/drivers/pinball2k.c

r0	r22593
	1	/*
	2	Pinball 2000
	3
	4	Skeleton by R. Belmont, based on mediagx.c by Ville Linde
	5
	6	TODO:
	7	MediaGX features should be moved out to machine/ and shared with mediagx.c once we know what these games need
	8
	9	Hardware:
	10	- Cyrix MediaGX processor/VGA
	11	- Cyrix CX5520 northbridge?
	12	- VS9824AG SuperI/O standard PC I/O chip
	13	- 1 ISA, 2 PCI slots, 2 IDE headers
	14	- "Prism" PCI card with PLX PCI9052 PCI-to-random stuff bridge
	15	Card also contains DCS2 Stereo sound system with ADSP-2104
	16	*/
	17
	18	#include "emu.h"
	19	#include "cpu/i386/i386.h"
	20	#include "machine/8237dma.h"
	21	#include "machine/pic8259.h"
	22	#include "machine/pit8253.h"
	23	#include "machine/mc146818.h"
	24	#include "machine/pci.h"
	25	#include "machine/8042kbdc.h"
	26	#include "machine/pckeybrd.h"
	27	#include "machine/idectrl.h"
	28	#include "video/ramdac.h"
	29
	30	class pinball2k_state : public driver_device
	31	{
	32	public:
	33	pinball2k_state(const machine_config &mconfig, device_type type, const char *tag)
	34	: driver_device(mconfig, type, tag),
	35	m_main_ram(*this, "main_ram"),
	36	m_cga_ram(*this, "cga_ram"),
	37	m_bios_ram(*this, "bios_ram"),
	38	m_vram(*this, "vram"),
	39	m_maincpu(*this, "maincpu") { }
	40
	41	required_shared_ptr<UINT32> m_main_ram;
	42	required_shared_ptr<UINT32> m_cga_ram;
	43	required_shared_ptr<UINT32> m_bios_ram;
	44	required_shared_ptr<UINT32> m_vram;
	45	UINT8 m_pal[768];
	46
	47
	48	UINT32 m_disp_ctrl_reg[256/4];
	49	int m_frame_width;
	50	int m_frame_height;
	51
	52	UINT32 m_memory_ctrl_reg[256/4];
	53	int m_pal_index;
	54
	55	UINT32 m_biu_ctrl_reg[256/4];
	56
	57	UINT8 m_mediagx_config_reg_sel;
	58	UINT8 m_mediagx_config_regs[256];
	59
	60	//UINT8 m_controls_data;
	61	UINT8 m_parallel_pointer;
	62	UINT8 m_parallel_latched;
	63	UINT32 m_parport;
	64	//int m_control_num;
	65	//int m_control_num2;
	66	//int m_control_read;
	67
	68	UINT32 m_cx5510_regs[256/4];
	69
	70	pit8254_device  *m_pit8254;
	71	pic8259_device  *m_pic8259_1;
	72	pic8259_device  *m_pic8259_2;
	73	i8237_device    *m_dma8237_1;
	74	i8237_device    *m_dma8237_2;
	75
	76	int m_dma_channel;
	77	UINT8 m_dma_offset[2][4];
	78	UINT8 m_at_pages[0x10];
	79
	80	DECLARE_READ32_MEMBER(disp_ctrl_r);
	81	DECLARE_WRITE32_MEMBER(disp_ctrl_w);
	82	DECLARE_READ32_MEMBER(memory_ctrl_r);
	83	DECLARE_WRITE32_MEMBER(memory_ctrl_w);
	84	DECLARE_READ32_MEMBER(biu_ctrl_r);
	85	DECLARE_WRITE32_MEMBER(biu_ctrl_w);
	86	DECLARE_WRITE32_MEMBER(bios_ram_w);
	87	DECLARE_READ32_MEMBER(parallel_port_r);
	88	DECLARE_WRITE32_MEMBER(parallel_port_w);
	89	DECLARE_READ32_MEMBER(ad1847_r);
	90	DECLARE_WRITE32_MEMBER(ad1847_w);
	91	DECLARE_READ8_MEMBER(at_page8_r);
	92	DECLARE_WRITE8_MEMBER(at_page8_w);
	93	DECLARE_READ8_MEMBER(pc_dma_read_byte);
	94	DECLARE_WRITE8_MEMBER(pc_dma_write_byte);
	95	DECLARE_READ8_MEMBER(at_dma8237_2_r);
	96	DECLARE_WRITE8_MEMBER(at_dma8237_2_w);
	97	DECLARE_READ32_MEMBER(ide_r);
	98	DECLARE_WRITE32_MEMBER(ide_w);
	99	DECLARE_READ32_MEMBER(fdc_r);
	100	DECLARE_WRITE32_MEMBER(fdc_w);
	101	DECLARE_READ8_MEMBER(io20_r);
	102	DECLARE_WRITE8_MEMBER(io20_w);
	103	DECLARE_WRITE_LINE_MEMBER(pc_dma_hrq_changed);
	104	DECLARE_WRITE_LINE_MEMBER(pc_dack0_w);
	105	DECLARE_WRITE_LINE_MEMBER(pc_dack1_w);
	106	DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
	107	DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
	108	DECLARE_WRITE_LINE_MEMBER(mediagx_pic8259_1_set_int_line);
	109	DECLARE_READ8_MEMBER(get_slave_ack);
	110	DECLARE_DRIVER_INIT(pinball2k);
	111	virtual void machine_start();
	112	virtual void machine_reset();
	113	virtual void video_start();
	114	UINT32 screen_update_mediagx(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
	115	DECLARE_READ8_MEMBER(get_out2);
	116	IRQ_CALLBACK_MEMBER(irq_callback);
	117	void draw_char(bitmap_rgb32 &bitmap, const rectangle &cliprect, gfx_element *gfx, int ch, int att, int x, int y);
	118	void draw_framebuffer(bitmap_rgb32 &bitmap, const rectangle &cliprect);
	119	void draw_cga(bitmap_rgb32 &bitmap, const rectangle &cliprect);
	120	void init_mediagx();
	121	required_device<cpu_device> m_maincpu;
	122	};
	123
	124	// Display controller registers
	125	#define DC_UNLOCK               0x00/4
	126	#define DC_GENERAL_CFG          0x04/4
	127	#define DC_TIMING_CFG           0x08/4
	128	#define DC_OUTPUT_CFG           0x0c/4
	129	#define DC_FB_ST_OFFSET         0x10/4
	130	#define DC_CB_ST_OFFSET         0x14/4
	131	#define DC_CUR_ST_OFFSET        0x18/4
	132	#define DC_VID_ST_OFFSET        0x20/4
	133	#define DC_LINE_DELTA           0x24/4
	134	#define DC_BUF_SIZE             0x28/4
	135	#define DC_H_TIMING_1           0x30/4
	136	#define DC_H_TIMING_2           0x34/4
	137	#define DC_H_TIMING_3           0x38/4
	138	#define DC_FP_H_TIMING          0x3c/4
	139	#define DC_V_TIMING_1           0x40/4
	140	#define DC_V_TIMING_2           0x44/4
	141	#define DC_V_TIMING_3           0x48/4
	142	#define DC_FP_V_TIMING          0x4c/4
	143	#define DC_CURSOR_X             0x50/4
	144	#define DC_V_LINE_CNT           0x54/4
	145	#define DC_CURSOR_Y             0x58/4
	146	#define DC_SS_LINE_CMP          0x5c/4
	147	#define DC_PAL_ADDRESS          0x70/4
	148	#define DC_PAL_DATA             0x74/4
	149	#define DC_DFIFO_DIAG           0x78/4
	150	#define DC_CFIFO_DIAG           0x7c/4
	151
	152
	153
	154
	155
	156
	157	static const rgb_t cga_palette[16] =
	158	{
	159	MAKE_RGB( 0x00, 0x00, 0x00 ), MAKE_RGB( 0x00, 0x00, 0xaa ), MAKE_RGB( 0x00, 0xaa, 0x00 ), MAKE_RGB( 0x00, 0xaa, 0xaa ),
	160	MAKE_RGB( 0xaa, 0x00, 0x00 ), MAKE_RGB( 0xaa, 0x00, 0xaa ), MAKE_RGB( 0xaa, 0x55, 0x00 ), MAKE_RGB( 0xaa, 0xaa, 0xaa ),
	161	MAKE_RGB( 0x55, 0x55, 0x55 ), MAKE_RGB( 0x55, 0x55, 0xff ), MAKE_RGB( 0x55, 0xff, 0x55 ), MAKE_RGB( 0x55, 0xff, 0xff ),
	162	MAKE_RGB( 0xff, 0x55, 0x55 ), MAKE_RGB( 0xff, 0x55, 0xff ), MAKE_RGB( 0xff, 0xff, 0x55 ), MAKE_RGB( 0xff, 0xff, 0xff ),
	163	};
	164
	165	void pinball2k_state::video_start()
	166	{
	167	int i;
	168	for (i=0; i < 16; i++)
	169	{
	170	palette_set_color(machine(), i, cga_palette[i]);
	171	}
	172	}
	173
	174	void pinball2k_state::draw_char(bitmap_rgb32 &bitmap, const rectangle &cliprect, gfx_element *gfx, int ch, int att, int x, int y)
	175	{
	176	int i,j;
	177	const UINT8 *dp;
	178	int index = 0;
	179	const pen_t *pens = gfx->machine().pens;
	180
	181	dp = gfx->get_data(ch);
	182
	183	for (j=y; j < y+8; j++)
	184	{
	185	UINT32 *p = &bitmap.pix32(j);
	186	for (i=x; i < x+8; i++)
	187	{
	188	UINT8 pen = dp[index++];
	189	if (pen)
	190	p[i] = pens[gfx->colorbase() + (att & 0xf)];
	191	else
	192	{
	193	if (((att >> 4) & 7) > 0)
	194	p[i] = pens[gfx->colorbase() + ((att >> 4) & 0x7)];
	195	}
	196	}
	197	}
	198	}
	199
	200	void pinball2k_state::draw_framebuffer(bitmap_rgb32 &bitmap, const rectangle &cliprect)
	201	{
	202	int i, j;
	203	int width, height;
	204	int line_delta = (m_disp_ctrl_reg[DC_LINE_DELTA] & 0x3ff) * 4;
	205
	206	width = (m_disp_ctrl_reg[DC_H_TIMING_1] & 0x7ff) + 1;
	207	if (m_disp_ctrl_reg[DC_TIMING_CFG] & 0x8000)     // pixel double
	208	{
	209	width >>= 1;
	210	}
	211	width += 4;
	212
	213	height = (m_disp_ctrl_reg[DC_V_TIMING_1] & 0x7ff) + 1;
	214
	215	if ( (width != m_frame_width || height != m_frame_height) &&
	216	(width > 1 && height > 1 && width <= 640 && height <= 480) )
	217	{
	218	rectangle visarea;
	219
	220	m_frame_width = width;
	221	m_frame_height = height;
	222
	223	visarea.set(0, width - 1, 0, height - 1);
	224	machine().primary_screen->configure(width, height * 262 / 240, visarea, machine().primary_screen->frame_period().attoseconds);
	225	}
	226
	227	if (m_disp_ctrl_reg[DC_OUTPUT_CFG] & 0x1)        // 8-bit mode
	228	{
	229	UINT8 *framebuf = (UINT8*)&m_vram[m_disp_ctrl_reg[DC_FB_ST_OFFSET]/4];
	230	UINT8 *pal = m_pal;
	231
	232	for (j=0; j < m_frame_height; j++)
	233	{
	234	UINT32 *p = &bitmap.pix32(j);
	235	UINT8 *si = &framebuf[j * line_delta];
	236	for (i=0; i < m_frame_width; i++)
	237	{
	238	int c = *si++;
	239	int r = pal[(c*3)+0] << 2;
	240	int g = pal[(c*3)+1] << 2;
	241	int b = pal[(c*3)+2] << 2;
	242
	243	p[i] = r << 16 | g << 8 | b;
	244	}
	245	}
	246	}
	247	else            // 16-bit
	248	{
	249	UINT16 *framebuf = (UINT16*)&m_vram[m_disp_ctrl_reg[DC_FB_ST_OFFSET]/4];
	250
	251	// RGB 5-6-5 mode
	252	if ((m_disp_ctrl_reg[DC_OUTPUT_CFG] & 0x2) == 0)
	253	{
	254	for (j=0; j < m_frame_height; j++)
	255	{
	256	UINT32 *p = &bitmap.pix32(j);
	257	UINT16 *si = &framebuf[j * (line_delta/2)];
	258	for (i=0; i < m_frame_width; i++)
	259	{
	260	UINT16 c = *si++;
	261	int r = ((c >> 11) & 0x1f) << 3;
	262	int g = ((c >> 5) & 0x3f) << 2;
	263	int b = (c & 0x1f) << 3;
	264
	265	p[i] = r << 16 | g << 8 | b;
	266	}
	267	}
	268	}
	269	// RGB 5-5-5 mode
	270	else
	271	{
	272	for (j=0; j < m_frame_height; j++)
	273	{
	274	UINT32 *p = &bitmap.pix32(j);
	275	UINT16 *si = &framebuf[j * (line_delta/2)];
	276	for (i=0; i < m_frame_width; i++)
	277	{
	278	UINT16 c = *si++;
	279	int r = ((c >> 10) & 0x1f) << 3;
	280	int g = ((c >> 5) & 0x1f) << 3;
	281	int b = (c & 0x1f) << 3;
	282
	283	p[i] = r << 16 | g << 8 | b;
	284	}
	285	}
	286	}
	287	}
	288	}
	289
	290	void pinball2k_state::draw_cga(bitmap_rgb32 &bitmap, const rectangle &cliprect)
	291	{
	292	int i, j;
	293	gfx_element *gfx = machine().gfx[0];
	294	UINT32 *cga = m_cga_ram;
	295	int index = 0;
	296
	297	for (j=0; j < 25; j++)
	298	{
	299	for (i=0; i < 80; i+=2)
	300	{
	301	int att0 = (cga[index] >> 8) & 0xff;
	302	int ch0 = (cga[index] >> 0) & 0xff;
	303	int att1 = (cga[index] >> 24) & 0xff;
	304	int ch1 = (cga[index] >> 16) & 0xff;
	305
	306	draw_char(bitmap, cliprect, gfx, ch0, att0, i*8, j*8);
	307	draw_char(bitmap, cliprect, gfx, ch1, att1, (i*8)+8, j*8);
	308	index++;
	309	}
	310	}
	311	}
	312
	313	UINT32 pinball2k_state::screen_update_mediagx(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
	314	{
	315	bitmap.fill(0, cliprect);
	316
	317	draw_framebuffer( bitmap, cliprect);
	318
	319	if (m_disp_ctrl_reg[DC_OUTPUT_CFG] & 0x1)   // don't show MDA text screen on 16-bit mode. this is basically a hack
	320	{
	321	draw_cga(bitmap, cliprect);
	322	}
	323	return 0;
	324	}
	325
	326	READ32_MEMBER(pinball2k_state::disp_ctrl_r)
	327	{
	328	UINT32 r = m_disp_ctrl_reg[offset];
	329
	330	switch (offset)
	331	{
	332	case DC_TIMING_CFG:
	333	r |= 0x40000000;
	334
	335	if (machine().primary_screen->vpos() >= m_frame_height)
	336	r &= ~0x40000000;
	337	break;
	338	}
	339
	340	return r;
	341	}
	342
	343	WRITE32_MEMBER(pinball2k_state::disp_ctrl_w)
	344	{
	345	//  printf("disp_ctrl_w %08X, %08X, %08X\n", data, offset*4, mem_mask);
	346	COMBINE_DATA(m_disp_ctrl_reg + offset);
	347	}
	348
	349
	350	READ8_MEMBER(pinball2k_state::at_dma8237_2_r)
	351	{
	352	return m_dma8237_2->i8237_r(space, offset / 2);
	353	}
	354
	355	WRITE8_MEMBER(pinball2k_state::at_dma8237_2_w)
	356	{
	357	m_dma8237_2->i8237_w(space, offset / 2, data);
	358	}
	359
	360
	361	READ32_MEMBER(pinball2k_state::ide_r)
	362	{
	363	device_t *device = machine().device("ide");
	364	return ide_controller32_r(device, space, 0x1f0/4 + offset, mem_mask);
	365	}
	366
	367	WRITE32_MEMBER(pinball2k_state::ide_w)
	368	{
	369	device_t *device = machine().device("ide");
	370	ide_controller32_w(device, space, 0x1f0/4 + offset, data, mem_mask);
	371	}
	372
	373	READ32_MEMBER(pinball2k_state::fdc_r)
	374	{
	375	device_t *device = machine().device("ide");
	376	return ide_controller32_r(device, space, 0x3f0/4 + offset, mem_mask);
	377	}
	378
	379	WRITE32_MEMBER(pinball2k_state::fdc_w)
	380	{
	381	device_t *device = machine().device("ide");
	382	ide_controller32_w(device, space, 0x3f0/4 + offset, data, mem_mask);
	383	}
	384
	385
	386
	387	READ32_MEMBER(pinball2k_state::memory_ctrl_r)
	388	{
	389	return m_memory_ctrl_reg[offset];
	390	}
	391
	392	WRITE32_MEMBER(pinball2k_state::memory_ctrl_w)
	393	{
	394	//  printf("memory_ctrl_w %08X, %08X, %08X\n", data, offset*4, mem_mask);
	395	if (offset == 0x20/4)
	396	{
	397	ramdac_device *ramdac = machine().device<ramdac_device>("ramdac");
	398
	399	if((m_disp_ctrl_reg[DC_GENERAL_CFG] & 0x00e00000) == 0x00400000)
	400	{
	401	// guess: crtc params?
	402	// ...
	403	}
	404	else if((m_disp_ctrl_reg[DC_GENERAL_CFG] & 0x00f00000) == 0x00000000)
	405	{
	406	m_pal_index = data;
	407	ramdac->index_w( space, 0, data );
	408	}
	409	else if((m_disp_ctrl_reg[DC_GENERAL_CFG] & 0x00f00000) == 0x00100000)
	410	{
	411	m_pal[m_pal_index] = data & 0xff;
	412	m_pal_index++;
	413	if (m_pal_index >= 768)
	414	{
	415	m_pal_index = 0;
	416	}
	417	ramdac->pal_w( space, 0, data );
	418	}
	419	}
	420	else
	421	{
	422	COMBINE_DATA(m_memory_ctrl_reg + offset);
	423	}
	424	}
	425
	426
	427
	428	READ32_MEMBER(pinball2k_state::biu_ctrl_r)
	429	{
	430	if (offset == 0)
	431	{
	432	return 0xffffff;
	433	}
	434	return m_biu_ctrl_reg[offset];
	435	}
	436
	437	WRITE32_MEMBER(pinball2k_state::biu_ctrl_w)
	438	{
	439	//mame_printf_debug("biu_ctrl_w %08X, %08X, %08X\n", data, offset, mem_mask);
	440	COMBINE_DATA(m_biu_ctrl_reg + offset);
	441
	442	if (offset == 3)        // BC_XMAP_3 register
	443	{
	444	//mame_printf_debug("BC_XMAP_3: %08X, %08X, %08X\n", data, offset, mem_mask);
	445	}
	446	}
	447
	448	#ifdef UNUSED_FUNCTION
	449	WRITE32_MEMBER(pinball2k_state::bios_ram_w)
	450	{
	451	}
	452	#endif
	453
	454	static UINT8 mediagx_config_reg_r(device_t *device)
	455	{
	456	pinball2k_state *state = device->machine().driver_data<pinball2k_state>();
	457
	458	//mame_printf_debug("mediagx_config_reg_r %02X\n", mediagx_config_reg_sel);
	459	return state->m_mediagx_config_regs[state->m_mediagx_config_reg_sel];
	460	}
	461
	462	static void mediagx_config_reg_w(device_t *device, UINT8 data)
	463	{
	464	pinball2k_state *state = device->machine().driver_data<pinball2k_state>();
	465
	466	//mame_printf_debug("mediagx_config_reg_w %02X, %02X\n", mediagx_config_reg_sel, data);
	467	state->m_mediagx_config_regs[state->m_mediagx_config_reg_sel] = data;
	468	}
	469
	470	READ8_MEMBER(pinball2k_state::io20_r)
	471	{
	472	device_t *device = machine().device("pic8259_master");
	473	UINT8 r = 0;
	474
	475	// 0x22, 0x23, Cyrix configuration registers
	476	if (offset == 0x02)
	477	{
	478	}
	479	else if (offset == 0x03)
	480	{
	481	r = mediagx_config_reg_r(device);
	482	}
	483	else
	484	{
	485	r = pic8259_r(device, space, offset);
	486	}
	487	return r;
	488	}
	489
	490	WRITE8_MEMBER(pinball2k_state::io20_w)
	491	{
	492	device_t *device = machine().device("pic8259_master");
	493
	494	// 0x22, 0x23, Cyrix configuration registers
	495	if (offset == 0x02)
	496	{
	497	m_mediagx_config_reg_sel = data;
	498	}
	499	else if (offset == 0x03)
	500	{
	501	mediagx_config_reg_w(device, data);
	502	}
	503	else
	504	{
	505	pic8259_w(device, space, offset, data);
	506	}
	507	}
	508
	509	READ32_MEMBER(pinball2k_state::parallel_port_r)
	510	{
	511	UINT32 r = 0;
	512
	513	return r;
	514	}
	515
	516	WRITE32_MEMBER(pinball2k_state::parallel_port_w)
	517	{
	518	}
	519
	520	static UINT32 cx5510_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask)
	521	{
	522	pinball2k_state *state = busdevice->machine().driver_data<pinball2k_state>();
	523
	524	//mame_printf_debug("CX5510: PCI read %d, %02X, %08X\n", function, reg, mem_mask);
	525	switch (reg)
	526	{
	527	case 0:     return 0x00001078;
	528	}
	529
	530	return state->m_cx5510_regs[reg/4];
	531	}
	532
	533	static void cx5510_pci_w(device_t *busdevice, device_t *device, int function, int reg, UINT32 data, UINT32 mem_mask)
	534	{
	535	pinball2k_state *state = busdevice->machine().driver_data<pinball2k_state>();
	536
	537	//mame_printf_debug("CX5510: PCI write %d, %02X, %08X, %08X\n", function, reg, data, mem_mask);
	538	COMBINE_DATA(state->m_cx5510_regs + (reg/4));
	539	}
	540
	541	/*************************************************************************
	542	*
	543	*      PC DMA stuff
	544	*
	545	*************************************************************************/
	546
	547
	548	READ8_MEMBER(pinball2k_state::at_page8_r)
	549	{
	550	UINT8 data = m_at_pages[offset % 0x10];
	551
	552	switch(offset % 8)
	553	{
	554	case 1:
	555	data = m_dma_offset[(offset / 8) & 1][2];
	556	break;
	557	case 2:
	558	data = m_dma_offset[(offset / 8) & 1][3];
	559	break;
	560	case 3:
	561	data = m_dma_offset[(offset / 8) & 1][1];
	562	break;
	563	case 7:
	564	data = m_dma_offset[(offset / 8) & 1][0];
	565	break;
	566	}
	567	return data;
	568	}
	569
	570
	571	WRITE8_MEMBER(pinball2k_state::at_page8_w)
	572	{
	573	m_at_pages[offset % 0x10] = data;
	574
	575	switch(offset % 8)
	576	{
	577	case 1:
	578	m_dma_offset[(offset / 8) & 1][2] = data;
	579	break;
	580	case 2:
	581	m_dma_offset[(offset / 8) & 1][3] = data;
	582	break;
	583	case 3:
	584	m_dma_offset[(offset / 8) & 1][1] = data;
	585	break;
	586	case 7:
	587	m_dma_offset[(offset / 8) & 1][0] = data;
	588	break;
	589	}
	590	}
	591
	592
	593	WRITE_LINE_MEMBER(pinball2k_state::pc_dma_hrq_changed)
	594	{
	595	m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
	596
	597	/* Assert HLDA */
	598	m_dma8237_1->i8237_hlda_w( state );
	599	}
	600
	601
	602	READ8_MEMBER(pinball2k_state::pc_dma_read_byte)
	603	{
	604	offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16)
	605	& 0xFF0000;
	606
	607	return space.read_byte(page_offset + offset);
	608	}
	609
	610
	611	WRITE8_MEMBER(pinball2k_state::pc_dma_write_byte)
	612	{
	613	offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16)
	614	& 0xFF0000;
	615
	616	space.write_byte(page_offset + offset, data);
	617	}
	618
	619	static void set_dma_channel(device_t *device, int channel, int _state)
	620	{
	621	pinball2k_state *state = device->machine().driver_data<pinball2k_state>();
	622
	623	if (!_state) state->m_dma_channel = channel;
	624	}
	625
	626	WRITE_LINE_MEMBER(pinball2k_state::pc_dack0_w){ set_dma_channel(m_dma8237_1, 0, state); }
	627	WRITE_LINE_MEMBER(pinball2k_state::pc_dack1_w){ set_dma_channel(m_dma8237_1, 1, state); }
	628	WRITE_LINE_MEMBER(pinball2k_state::pc_dack2_w){ set_dma_channel(m_dma8237_1, 2, state); }
	629	WRITE_LINE_MEMBER(pinball2k_state::pc_dack3_w){ set_dma_channel(m_dma8237_1, 3, state); }
	630
	631	static I8237_INTERFACE( dma8237_1_config )
	632	{
	633	DEVCB_DRIVER_LINE_MEMBER(pinball2k_state,pc_dma_hrq_changed),
	634	DEVCB_NULL,
	635	DEVCB_DRIVER_MEMBER(pinball2k_state, pc_dma_read_byte),
	636	DEVCB_DRIVER_MEMBER(pinball2k_state, pc_dma_write_byte),
	637	{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
	638	{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
	639	{ DEVCB_DRIVER_LINE_MEMBER(pinball2k_state,pc_dack0_w), DEVCB_DRIVER_LINE_MEMBER(pinball2k_state,pc_dack1_w), DEVCB_DRIVER_LINE_MEMBER(pinball2k_state,pc_dack2_w), DEVCB_DRIVER_LINE_MEMBER(pinball2k_state,pc_dack3_w) }
	640	};
	641
	642	static I8237_INTERFACE( dma8237_2_config )
	643	{
	644	DEVCB_NULL,
	645	DEVCB_NULL,
	646	DEVCB_NULL,
	647	DEVCB_NULL,
	648	{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
	649	{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
	650	{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
	651	};
	652
	653
	654	/*****************************************************************************/
	655
	656	static ADDRESS_MAP_START( mediagx_map, AS_PROGRAM, 32, pinball2k_state )
	657	AM_RANGE(0x00000000, 0x0009ffff) AM_RAM AM_SHARE("main_ram")
	658	AM_RANGE(0x000a0000, 0x000affff) AM_RAM
	659	AM_RANGE(0x000b0000, 0x000b7fff) AM_RAM AM_SHARE("cga_ram")
	660	AM_RANGE(0x000c0000, 0x000fffff) AM_RAM AM_SHARE("bios_ram")
	661	AM_RANGE(0x00100000, 0x00ffffff) AM_RAM
	662	AM_RANGE(0x40008000, 0x400080ff) AM_READWRITE(biu_ctrl_r, biu_ctrl_w)
	663	AM_RANGE(0x40008300, 0x400083ff) AM_READWRITE(disp_ctrl_r, disp_ctrl_w)
	664	AM_RANGE(0x40008400, 0x400084ff) AM_READWRITE(memory_ctrl_r, memory_ctrl_w)
	665	AM_RANGE(0x40800000, 0x40bfffff) AM_RAM AM_SHARE("vram")
	666	AM_RANGE(0xfffc0000, 0xffffffff) AM_ROM AM_REGION("bios", 0)    /* System BIOS */
	667	ADDRESS_MAP_END
	668
	669	static ADDRESS_MAP_START(mediagx_io, AS_IO, 32, pinball2k_state )
	670	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", i8237_device, i8237_r, i8237_w, 0xffffffff)
	671	AM_RANGE(0x0020, 0x003f) AM_READWRITE8(io20_r, io20_w, 0xffffffff)
	672	AM_RANGE(0x0040, 0x005f) AM_DEVREADWRITE8_LEGACY("pit8254", pit8253_r, pit8253_w, 0xffffffff)
	673	AM_RANGE(0x0060, 0x006f) AM_DEVREADWRITE8("kbdc", kbdc8042_device, data_r, data_w, 0xffffffff)
	674	AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8("rtc", mc146818_device, read, write, 0xffffffff)
	675	AM_RANGE(0x0080, 0x009f) AM_READWRITE8(at_page8_r,              at_page8_w, 0xffffffff)
	676	AM_RANGE(0x00a0, 0x00bf) AM_DEVREADWRITE8_LEGACY("pic8259_slave", pic8259_r, pic8259_w, 0xffffffff)
	677	AM_RANGE(0x00c0, 0x00df) AM_READWRITE8(at_dma8237_2_r, at_dma8237_2_w, 0xffffffff)
	678	AM_RANGE(0x00e8, 0x00eb) AM_NOP     // I/O delay port
	679	AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w)
	680	AM_RANGE(0x0378, 0x037b) AM_READWRITE(parallel_port_r, parallel_port_w)
	681	AM_RANGE(0x03f0, 0x03ff) AM_READWRITE(fdc_r, fdc_w)
	682	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
	683	ADDRESS_MAP_END
	684
	685	/*****************************************************************************/
	686
	687	static const gfx_layout CGA_charlayout =
	688	{
	689	8,8,                    /* 8 x 16 characters */
	690	256,                    /* 256 characters */
	691	1,                      /* 1 bits per pixel */
	692	{ 0 },                  /* no bitplanes; 1 bit per pixel */
	693	/* x offsets */
	694	{ 0,1,2,3,4,5,6,7 },
	695	/* y offsets */
	696	{ 0*8,1*8,2*8,3*8,
	697	4*8,5*8,6*8,7*8 },
	698	8*8                     /* every char takes 8 bytes */
	699	};
	700
	701	static GFXDECODE_START( CGA )
	702	/* Support up to four CGA fonts */
	703	GFXDECODE_ENTRY( "gfx1", 0x0000, CGA_charlayout, 0, 256 )   /* Font 0 */
	704	GFXDECODE_ENTRY( "gfx1", 0x0800, CGA_charlayout, 0, 256 )   /* Font 1 */
	705	GFXDECODE_ENTRY( "gfx1", 0x1000, CGA_charlayout, 0, 256 )   /* Font 2 */
	706	GFXDECODE_ENTRY( "gfx1", 0x1800, CGA_charlayout, 0, 256 )   /* Font 3*/
	707	GFXDECODE_END
	708
	709	static INPUT_PORTS_START(mediagx)
	710	PORT_START("IN0")
	711	PORT_SERVICE_NO_TOGGLE( 0x001, IP_ACTIVE_HIGH )
	712	PORT_BIT( 0x002, IP_ACTIVE_HIGH, IPT_SERVICE1 )
	713	PORT_BIT( 0x004, IP_ACTIVE_HIGH, IPT_SERVICE2 )
	714	PORT_BIT( 0x008, IP_ACTIVE_HIGH, IPT_VOLUME_DOWN )
	715	PORT_BIT( 0x010, IP_ACTIVE_HIGH, IPT_COIN1 )
	716	PORT_BIT( 0x020, IP_ACTIVE_HIGH, IPT_COIN2 )
	717	PORT_BIT( 0x040, IP_ACTIVE_HIGH, IPT_COIN3 )
	718	PORT_BIT( 0x080, IP_ACTIVE_HIGH, IPT_COIN4 )
	719	PORT_BIT( 0x100, IP_ACTIVE_HIGH, IPT_START1 )
	720	PORT_BIT( 0x200, IP_ACTIVE_HIGH, IPT_START2 )
	721	PORT_BIT( 0x400, IP_ACTIVE_HIGH, IPT_START3 )
	722	PORT_BIT( 0x800, IP_ACTIVE_HIGH, IPT_START4 )
	723
	724	PORT_START("IN1")
	725	PORT_BIT( 0x00f, IP_ACTIVE_HIGH, IPT_BUTTON1 )
	726	PORT_BIT( 0x0f0, IP_ACTIVE_HIGH, IPT_BUTTON2 )
	727	PORT_BIT( 0xf00, IP_ACTIVE_HIGH, IPT_BUTTON3 )
	728
	729	PORT_START("IN2")
	730	PORT_BIT( 0x00f, IP_ACTIVE_HIGH, IPT_BUTTON4 )
	731	PORT_BIT( 0x0f0, IP_ACTIVE_HIGH, IPT_BUTTON5 )
	732	PORT_BIT( 0xf00, IP_ACTIVE_HIGH, IPT_BUTTON6 )
	733
	734	PORT_START("IN3")
	735	PORT_BIT( 0x00f, IP_ACTIVE_HIGH, IPT_BUTTON7 )
	736	PORT_BIT( 0x0f0, IP_ACTIVE_HIGH, IPT_BUTTON8 )
	737	PORT_BIT( 0xf00, IP_ACTIVE_HIGH, IPT_BUTTON9 )
	738
	739	PORT_START("IN4")
	740	PORT_BIT( 0x00f, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(2)
	741	PORT_BIT( 0x0f0, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_PLAYER(2)
	742	PORT_BIT( 0xf00, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_PLAYER(2)
	743
	744	PORT_START("IN5")
	745	PORT_BIT( 0x00f, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(3)
	746	PORT_BIT( 0x0f0, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_PLAYER(3)
	747	PORT_BIT( 0xf00, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_PLAYER(3)
	748
	749	PORT_START("IN6")
	750	PORT_BIT( 0x00f, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP )
	751	PORT_BIT( 0x0f0, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN )
	752	PORT_BIT( 0xf00, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT )
	753
	754	PORT_START("IN7")
	755	PORT_BIT( 0x00f, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
	756	PORT_BIT( 0x0f0, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
	757	PORT_BIT( 0xf00, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
	758
	759	PORT_START("IN8")
	760	PORT_BIT( 0x00f, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_PLAYER(3)
	761	PORT_BIT( 0x0f0, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_PLAYER(3)
	762	PORT_BIT( 0xf00, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_PLAYER(3)
	763	INPUT_PORTS_END
	764
	765	IRQ_CALLBACK_MEMBER(pinball2k_state::irq_callback)
	766	{
	767	return pic8259_acknowledge(m_pic8259_1);
	768	}
	769
	770	void pinball2k_state::machine_start()
	771	{
	772	m_pit8254 = machine().device<pit8254_device>( "pit8254" );
	773	m_pic8259_1 = machine().device<pic8259_device>( "pic8259_master" );
	774	m_pic8259_2 = machine().device<pic8259_device>( "pic8259_slave" );
	775	m_dma8237_1 = machine().device<i8237_device>( "dma8237_1" );
	776	m_dma8237_2 = machine().device<i8237_device>( "dma8237_2" );
	777	}
	778
	779	void pinball2k_state::machine_reset()
	780	{
	781	UINT8 *rom = memregion("bios")->base();
	782
	783	m_maincpu->set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(pinball2k_state::irq_callback),this));
	784
	785	memcpy(m_bios_ram, rom, 0x40000);
	786	m_maincpu->reset();
	787
	788	machine().device("ide")->reset();
	789	}
	790
	791	/*************************************************************
	792	*
	793	* pic8259 configuration
	794	*
	795	*************************************************************/
	796
	797	WRITE_LINE_MEMBER(pinball2k_state::mediagx_pic8259_1_set_int_line)
	798	{
	799	m_maincpu->set_input_line(0, state ? HOLD_LINE : CLEAR_LINE);
	800	}
	801
	802	READ8_MEMBER(pinball2k_state::get_slave_ack)
	803	{
	804	if (offset==2) { // IRQ = 2
	805	return pic8259_acknowledge(m_pic8259_2);
	806	}
	807	return 0x00;
	808	}
	809
	810	static const struct pic8259_interface mediagx_pic8259_1_config =
	811	{
	812	DEVCB_DRIVER_LINE_MEMBER(pinball2k_state,mediagx_pic8259_1_set_int_line),
	813	DEVCB_LINE_VCC,
	814	DEVCB_DRIVER_MEMBER(pinball2k_state,get_slave_ack)
	815	};
	816
	817	static const struct pic8259_interface mediagx_pic8259_2_config =
	818	{
	819	DEVCB_DEVICE_LINE("pic8259_master", pic8259_ir2_w),
	820	DEVCB_LINE_GND,
	821	DEVCB_NULL
	822	};
	823
	824
	825	/*************************************************************
	826	*
	827	* pit8254 configuration
	828	*
	829	*************************************************************/
	830
	831	static const struct pit8253_config mediagx_pit8254_config =
	832	{
	833	{
	834	{
	835	4772720/4,              /* heartbeat IRQ */
	836	DEVCB_NULL,
	837	DEVCB_DEVICE_LINE("pic8259_master", pic8259_ir0_w)
	838	}, {
	839	4772720/4,              /* dram refresh */
	840	DEVCB_NULL,
	841	DEVCB_NULL
	842	}, {
	843	4772720/4,              /* pio port c pin 4, and speaker polling enough */
	844	DEVCB_NULL,
	845	DEVCB_NULL
	846	}
	847	}
	848	};
	849
	850	static ADDRESS_MAP_START( ramdac_map, AS_0, 8, pinball2k_state )
	851	AM_RANGE(0x000, 0x3ff) AM_DEVREADWRITE("ramdac",ramdac_device,ramdac_pal_r,ramdac_rgb666_w)
	852	ADDRESS_MAP_END
	853
	854	static RAMDAC_INTERFACE( ramdac_intf )
	855	{
	856	0
	857	};
	858
	859	READ8_MEMBER(pinball2k_state::get_out2)
	860	{
	861	return pit8253_get_output( m_pit8254, 2 );
	862	}
	863
	864	static const struct kbdc8042_interface at8042 =
	865	{
	866	KBDC8042_AT386,
	867	DEVCB_CPU_INPUT_LINE("maincpu", INPUT_LINE_RESET),
	868	DEVCB_CPU_INPUT_LINE("maincpu", INPUT_LINE_A20),
	869	DEVCB_DEVICE_LINE_MEMBER("pic8259_master", pic8259_device, ir1_w),
	870	DEVCB_NULL,
	871
	872	DEVCB_NULL,
	873	DEVCB_DRIVER_MEMBER(pinball2k_state,get_out2)
	874	};
	875
	876	static MACHINE_CONFIG_START( mediagx, pinball2k_state )
	877
	878	/* basic machine hardware */
	879	MCFG_CPU_ADD("maincpu", MEDIAGX, 166000000)
	880	MCFG_CPU_PROGRAM_MAP(mediagx_map)
	881	MCFG_CPU_IO_MAP(mediagx_io)
	882
	883
	884	MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
	885	MCFG_PCI_BUS_LEGACY_DEVICE(18, NULL, cx5510_pci_r, cx5510_pci_w)
	886
	887	MCFG_PIT8254_ADD( "pit8254", mediagx_pit8254_config )
	888
	889	MCFG_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, dma8237_1_config )
	890
	891	MCFG_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
	892
	893	MCFG_PIC8259_ADD( "pic8259_master", mediagx_pic8259_1_config )
	894
	895	MCFG_PIC8259_ADD( "pic8259_slave", mediagx_pic8259_2_config )
	896
	897	MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
	898	MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_slave", pic8259_device, ir6_w))
	899
	900	MCFG_MC146818_ADD( "rtc", MC146818_STANDARD )
	901
	902	MCFG_RAMDAC_ADD("ramdac", ramdac_intf, ramdac_map)
	903
	904	/* video hardware */
	905	MCFG_SCREEN_ADD("screen", RASTER)
	906	MCFG_SCREEN_REFRESH_RATE(60)
	907	MCFG_SCREEN_SIZE(640, 480)
	908	MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 239)
	909	MCFG_SCREEN_UPDATE_DRIVER(pinball2k_state, screen_update_mediagx)
	910
	911	MCFG_GFXDECODE(CGA)
	912	MCFG_PALETTE_LENGTH(256)
	913
	914	MCFG_KBDC8042_ADD("kbdc", at8042)
	915
	916	/* sound hardware */
	917	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
	918	MACHINE_CONFIG_END
	919
	920
	921	void pinball2k_state::init_mediagx()
	922	{
	923	m_frame_width = m_frame_height = 1;
	924	}
	925
	926	DRIVER_INIT_MEMBER(pinball2k_state, pinball2k)
	927	{
	928	init_mediagx();
	929	}
	930
	931	/*****************************************************************************/
	932
	933	ROM_START( swe1pb )
	934	ROM_REGION32_LE(0x40000, "bios", 0)
	935	ROM_LOAD( "awdbios.bin",  0x000000, 0x040000, CRC(854ce8c6) SHA1(7826de74026e052dacce8516382f664004c327ad) )
	936
	937	ROM_REGION(0x4800000, "prism", 0)
	938	ROM_LOAD( "swe1_u100.rom", 0x0000000, 0x800000, CRC(db2c9709) SHA1(14e8db2c0b09c4da6306a4a1f7fe54b2a334c5ed) )
	939	ROM_LOAD( "swe1_u101.rom", 0x0800000, 0x800000, CRC(a039e80d) SHA1(8f63e8ab83e043232fc17ed3dff1f251396a178a) )
	940	ROM_LOAD( "swe1_u102.rom", 0x1000000, 0x800000, CRC(c9feb7bc) SHA1(a34acd34c3f91f082b67e385b1f4da2e5b6e5087) )
	941	ROM_LOAD( "swe1_u103.rom", 0x1800000, 0x800000, CRC(7a692466) SHA1(9adf5ae9c12bd5b6314913f6c01d4566ee453fe1) )
	942	ROM_LOAD( "swe1_u104.rom", 0x2000000, 0x800000, CRC(76e2dd7e) SHA1(9bc20a1423b11c46eb2f5a514e985151defb5651) )
	943	ROM_LOAD( "swe1_u105.rom", 0x2800000, 0x800000, CRC(87f2460c) SHA1(cdc05e017367f61280e3d5682096e67e4c200150) )
	944	ROM_LOAD( "swe1_u106.rom", 0x3000000, 0x800000, CRC(84877e2f) SHA1(6dd8c761b2e26313ae9e159690b3a4a170cb3bd8) )
	945	ROM_LOAD( "swe1_u107.rom", 0x3800000, 0x800000, CRC(dc433c89) SHA1(9f1273debc9168c04202078503cfc4f1ca8cb30b) )
	946	ROM_LOAD( "swe1_u109.rom", 0x4000000, 0x400000, CRC(cc08936b) SHA1(fc428393e8a0cf37b800dd475fd293a1a98c4bcf) )
	947	ROM_LOAD( "swe1_u110.rom", 0x4400000, 0x400000, CRC(6011ecd9) SHA1(8575958c8942a6cbcb2ac18f291fcada6f8cbc09) )
	948
	949	ROM_REGION(0x08100, "gfx1", 0)
	950	ROM_LOAD("cga.chr",     0x00000, 0x01000, CRC(42009069) SHA1(ed08559ce2d7f97f68b9f540bddad5b6295294dd))
	951	ROM_END
	952
	953	ROM_START( rfmpb )
	954	ROM_REGION32_LE(0x40000, "bios", 0)
	955	ROM_LOAD( "awdbios.bin",  0x000000, 0x040000, CRC(854ce8c6) SHA1(7826de74026e052dacce8516382f664004c327ad) )
	956
	957	ROM_REGION(0x4000000, "prism", 0)
	958	ROM_LOAD( "rfm_u100.rom", 0x0000000, 0x800000, CRC(b3548b1b) SHA1(874a16282bb778886cea2567d68ec7024dc5ed22) )
	959	ROM_LOAD( "rfm_u101.rom", 0x0800000, 0x800000, CRC(8bef301d) SHA1(2eade00b1a4cd3f5e98ebe8ed8f549e328188e77) )
	960	ROM_LOAD( "rfm_u102.rom", 0x1000000, 0x800000, CRC(749f5c59) SHA1(2d8850e7f8ea3e07e8b444d7dd4dc4195a547ae7) )
	961	ROM_LOAD( "rfm_u103.rom", 0x1800000, 0x800000, CRC(a9ec5e97) SHA1(ce7c38dcbf34ce10d6e204a3176cd2c7a83b525a) )
	962	ROM_LOAD( "rfm_u104.rom", 0x2000000, 0x800000, CRC(0a1acd70) SHA1(dcca4de92eadeb82ac776953326410a9687838cb) )
	963	ROM_LOAD( "rfm_u105.rom", 0x2800000, 0x800000, CRC(1ef31684) SHA1(141900a7426ad483384606cddb018d186952f439) )
	964	ROM_LOAD( "rfm_u106.rom", 0x3000000, 0x800000, CRC(daf4e1dc) SHA1(0612495468fb962b833057e50f620c5f69cd5840) )
	965	ROM_LOAD( "rfm_u107.rom", 0x3800000, 0x800000, CRC(e737ab39) SHA1(0e978923db19e2893fdb4aae69d6ed3c3f664a31) )
	966
	967	ROM_REGION(0x08100, "gfx1", 0)
	968	ROM_LOAD("cga.chr",     0x00000, 0x01000, CRC(42009069) SHA1(ed08559ce2d7f97f68b9f540bddad5b6295294dd))
	969	ROM_END
	970
	971	ROM_START( rfmpbr2 )
	972	ROM_REGION32_LE(0x40000, "bios", 0)
	973	ROM_LOAD( "awdbios.bin",  0x000000, 0x040000, CRC(854ce8c6) SHA1(7826de74026e052dacce8516382f664004c327ad) )
	974
	975	ROM_REGION(0x4800000, "prism", 0)
	976	ROM_LOAD( "rfm_u100r2.rom", 0x0000000, 0x800000, CRC(d4278a9b) SHA1(ec07b97190acb6b34b9ed6cda505ee8fefd66fec) )
	977	ROM_LOAD( "rfm_u101r2.rom", 0x0800000, 0x800000, CRC(e5d4c0ed) SHA1(cfc7d9d2324cc02c9eaf53fd674f7db24736699c) )
	978	ROM_LOAD( "rfm_u102.rom",   0x1000000, 0x800000, CRC(749f5c59) SHA1(2d8850e7f8ea3e07e8b444d7dd4dc4195a547ae7) )
	979	ROM_LOAD( "rfm_u103.rom",   0x1800000, 0x800000, CRC(a9ec5e97) SHA1(ce7c38dcbf34ce10d6e204a3176cd2c7a83b525a) )
	980	ROM_LOAD( "rfm_u104.rom",   0x2000000, 0x800000, CRC(0a1acd70) SHA1(dcca4de92eadeb82ac776953326410a9687838cb) )
	981	ROM_LOAD( "rfm_u105.rom",   0x2800000, 0x800000, CRC(1ef31684) SHA1(141900a7426ad483384606cddb018d186952f439) )
	982	ROM_LOAD( "rfm_u106.rom",   0x3000000, 0x800000, CRC(daf4e1dc) SHA1(0612495468fb962b833057e50f620c5f69cd5840) )
	983	ROM_LOAD( "rfm_u107.rom",   0x3800000, 0x800000, CRC(e737ab39) SHA1(0e978923db19e2893fdb4aae69d6ed3c3f664a31) )
	984	ROM_LOAD( "rfm_u109.bin",   0x4000000, 0x400000, CRC(a20b2abb) SHA1(0010d7dbf60b03f50cc1d314fdf786721161b064) )
	985	ROM_LOAD( "rfm_u110.bin",   0x4400000, 0x400000, CRC(095abec9) SHA1(87ce156bbf673ebd50bbd7dcca4c6924d24fc823) )
	986
	987	ROM_REGION(0x08100, "gfx1", 0)
	988	ROM_LOAD("cga.chr",     0x00000, 0x01000, CRC(42009069) SHA1(ed08559ce2d7f97f68b9f540bddad5b6295294dd))
	989	ROM_END
	990
	991	/*****************************************************************************/
	992
	993	GAME( 1999, swe1pb,   0       , mediagx, mediagx, pinball2k_state, pinball2k, ROT0,   "Midway",  "Pinball 2000: Star Wars Episode 1", GAME_NOT_WORKING | GAME_NO_SOUND | GAME_MECHANICAL )
	994	GAME( 1999, rfmpb,    0       , mediagx, mediagx, pinball2k_state, pinball2k, ROT0,   "Midway",  "Pinball 2000: Revenge From Mars (rev. 1)", GAME_NOT_WORKING | GAME_NO_SOUND | GAME_MECHANICAL )
	995	GAME( 1999, rfmpbr2,  rfmpb   , mediagx, mediagx, pinball2k_state, pinball2k, ROT0,   "Midway",  "Pinball 2000: Revenge From Mars (rev. 2)", GAME_NOT_WORKING | GAME_NO_SOUND | GAME_MECHANICAL )
	996

Property changes on: trunk/src/mame/drivers/pinball2k.c

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/mame/mame.lst

r22592	r22593
7801	7801	galgbios        // (c) 1998 Creative Electronics & Software (CES)
7802	7802	galgame2        // (c) 1998 Creative Electronics & Software (CES) / Namco
7803	7803
	7804	// Williams/Bally/Midway Pinball 2000
	7805	swe1pb
	7806	rfmpb
	7807	rfmpbr2
	7808
7804	7809	// Creative Electronics & Software
7805	7810	tapatune
7806	7811	hrclass

trunk/src/mame/mame.mak

r22592	r22593
1055	1055	$(DRIVERS)/midyunit.o $(MACHINE)/midyunit.o $(VIDEO)/midyunit.o \
1056	1056	$(DRIVERS)/midzeus.o $(VIDEO)/midzeus.o $(VIDEO)/midzeus2.o \
1057	1057	$(DRIVERS)/omegrace.o \
	1058	$(DRIVERS)/pinball2k.o \
1058	1059	$(DRIVERS)/seattle.o \
1059	1060	$(DRIVERS)/tmaster.o \
1060	1061	$(DRIVERS)/vegas.o $(DRIVERS)/wmg.o \

Previous

199869 Revisions

Next

---

© 1997-2024 The MAME Team