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r22560 Friday 26th April, 2013 at 16:51:38 UTC by smf
PSX CPU creates a ram device, this has exposed a problem with not removing the child devices from the hash map when removing replacing devices. At the moment I have changed device.c so that when any device is removed the hash maps are reset. [smf]

[src/emu]	device.c
[src/emu/cpu/psx]	psx.c psx.h
[src/mame/drivers]	konamigq.c konamigv.c ksys573.c namcos10.c namcos11.c namcos12.c taitogn.c twinkle.c zn.c
[src/mess/drivers]	psx.c

trunk/src/mame/drivers/ksys573.c

r22559	r22560
535	535	driver_device(mconfig, type, tag),
536	536	m_psxirq(*this, ":maincpu:irq"),
537	537	m_cr589(*this, ":cdrom"),
538		m_maincpu(*this, "maincpu") { }
	538	m_maincpu(*this, "maincpu"),
	539	m_ram(*this, "maincpu:ram")
	540	{
	541	}
539	542
540	543	required_device<psxirq_device> m_psxirq;
541	544
r22559	r22560
667	670	void mamboagg_output_callback( int offset, int data );
668	671	void punchmania_output_callback( int offset, int data );
669	672	required_device<psxcpu_device> m_maincpu;
	673	required_device<ram_device> m_ram;
670	674	};
671	675
672	676	void ATTR_PRINTF(3,4)  ksys573_state::verboselog( int n_level, const char *s_fmt, ... )
r22559	r22560
1462	1466	{
1463	1467	/* patch out security-plate error */
1464	1468
1465		UINT32 *p_n_psxram = m_maincpu->ram();
	1469	UINT32 *p_n_psxram = (UINT32 *) m_ram->pointer();
1466	1470
1467	1471	/* install cd */
1468	1472
r22559	r22560
1486	1490	{
1487	1491	/* patch out security-plate error */
1488	1492
1489		UINT32 *p_n_psxram = m_maincpu->ram();
	1493	UINT32 *p_n_psxram = (UINT32 *) m_ram->pointer();
1490	1494
1491	1495	/* 8001f850: jal $8003221c */
1492	1496	if( p_n_psxram[ 0x1f850 / 4 ] == 0x0c00c887 )
r22559	r22560
3056	3060	static MACHINE_CONFIG_START( konami573, ksys573_state )
3057	3061	/* basic machine hardware */
3058	3062	MCFG_CPU_ADD( "maincpu", CXD8530CQ, XTAL_67_7376MHz )
3059		MCFG_PSX_RAM_SIZE( 0x400000 )
3060	3063	MCFG_CPU_PROGRAM_MAP( konami573_map )
3061	3064
	3065	MCFG_RAM_MODIFY("maincpu:ram")
	3066	MCFG_RAM_DEFAULT_SIZE("4M")
	3067
3062	3068	MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 5, psx_dma_read_delegate( FUNC( ksys573_state::cdrom_dma_read ), (ksys573_state *) owner ) )
3063	3069	MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 5, psx_dma_write_delegate( FUNC( ksys573_state::cdrom_dma_write ), (ksys573_state *) owner ) )
3064	3070

trunk/src/mame/drivers/taitogn.c

r22559	r22560
833	833	static MACHINE_CONFIG_START( coh3002t, taitogn_state )
834	834	/* basic machine hardware */
835	835	MCFG_CPU_ADD( "maincpu", CXD8661R, XTAL_100MHz )
836		MCFG_PSX_RAM_SIZE( 0x400000 )
837	836	MCFG_CPU_PROGRAM_MAP(taitogn_map)
838	837
	838	MCFG_RAM_MODIFY("maincpu:ram")
	839	MCFG_RAM_DEFAULT_SIZE("4M")
	840
839	841	MCFG_DEVICE_ADD("maincpu:sio0:znsec0", ZNSEC, 0)
840	842	MCFG_DEVICE_ADD("maincpu:sio0:znsec1", ZNSEC, 0)
841	843	MCFG_DEVICE_ADD("maincpu:sio0:zndip", ZNDIP, 0)

trunk/src/mame/drivers/namcos11.c

r22559	r22560
1010	1010	static MACHINE_CONFIG_START( coh100, namcos11_state )
1011	1011	/* basic machine hardware */
1012	1012	MCFG_CPU_ADD( "maincpu", CXD8530AQ, XTAL_67_7376MHz )
1013		MCFG_PSX_RAM_SIZE( 0x400000 )
1014	1013	MCFG_CPU_PROGRAM_MAP( namcos11_map )
1015	1014
	1015	MCFG_RAM_MODIFY("maincpu:ram")
	1016	MCFG_RAM_DEFAULT_SIZE("4M")
	1017
1016	1018	MCFG_CPU_ADD("c76", M37702, 16934400)
1017	1019	MCFG_CPU_PROGRAM_MAP(c76_map)
1018	1020	MCFG_CPU_IO_MAP(c76_io_map)
r22559	r22560
1038	1040
1039	1041	static MACHINE_CONFIG_DERIVED( coh110, coh100 )
1040	1042	MCFG_CPU_REPLACE( "maincpu", CXD8530CQ, XTAL_67_7376MHz )
1041		MCFG_PSX_RAM_SIZE( 0x400000 )
1042	1043	MCFG_CPU_PROGRAM_MAP( namcos11_map )
1043	1044
	1045	MCFG_RAM_MODIFY("maincpu:ram")
	1046	MCFG_RAM_DEFAULT_SIZE("4M")
	1047
1044	1048	MCFG_PSXGPU_REPLACE( "maincpu", "gpu", CXD8561Q, 0x200000, XTAL_53_693175MHz )
1045	1049	MACHINE_CONFIG_END
1046	1050

trunk/src/mame/drivers/konamigv.c

r22559	r22560
306	306	static MACHINE_CONFIG_START( konamigv, konamigv_state )
307	307	/* basic machine hardware */
308	308	MCFG_CPU_ADD( "maincpu", CXD8530BQ, XTAL_67_7376MHz )
309		MCFG_PSX_RAM_SIZE( 0x200000 )
310	309	MCFG_CPU_PROGRAM_MAP( konamigv_map )
311	310
	311	MCFG_RAM_MODIFY("maincpu:ram")
	312	MCFG_RAM_DEFAULT_SIZE("2M")
	313
312	314	MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 5, psx_dma_read_delegate( FUNC( konamigv_state::scsi_dma_read ), (konamigv_state *) owner ) )
313	315	MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 5, psx_dma_write_delegate( FUNC( konamigv_state::scsi_dma_write ), (konamigv_state *) owner ) )
314	316

trunk/src/mame/drivers/zn.c

r22559	r22560
39	39	m_znsec1(*this,"maincpu:sio0:znsec1"),
40	40	m_zndip(*this,"maincpu:sio0:zndip"),
41	41	m_maincpu(*this, "maincpu"),
42		m_audiocpu(*this, "audiocpu") {
	42	m_audiocpu(*this, "audiocpu"),
	43	m_ram(*this, "maincpu:ram")
	44	{
43	45	}
44	46
45	47	required_device<psxgpu_device> m_gpu;
r22559	r22560
66	68	DECLARE_READ32_MEMBER(znsecsel_r);
67	69	DECLARE_WRITE32_MEMBER(znsecsel_w);
68	70	DECLARE_READ32_MEMBER(boardconfig_r);
69		DECLARE_READ32_MEMBER(boardconfig_8M_r);
70	71	DECLARE_READ32_MEMBER(unknown_r);
71	72	DECLARE_WRITE32_MEMBER(coin_w);
72	73	DECLARE_READ32_MEMBER(capcom_kickharness_r);
r22559	r22560
136	137	DECLARE_WRITE_LINE_MEMBER(irqhandler);
137	138	required_device<cpu_device> m_maincpu;
138	139	optional_device<cpu_device> m_audiocpu;
	140	required_device<ram_device> m_ram;
139	141	};
140	142
141	143	inline void ATTR_PRINTF(3,4) zn_state::verboselog( int n_level, const char *s_fmt, ... )
r22559	r22560
360	362	111----- rev=5
361	363	*/
362	364
	365	int boardconfig = 64 | 32;
	366
363	367	if( machine().primary_screen->height() == 1024 )
364	368	{
365		return 64|32|8;
	369	boardconfig |= 8;
366	370	}
367		else
	371
	372	switch( m_ram->size() )
368	373	{
369		return 64|32;
370		}
371		}
	374	case 0x400000:
	375	boardconfig |= 1;
	376	break;
372	377
373		READ32_MEMBER(zn_state::boardconfig_8M_r)
374		{
375		/*
376		------00 mem=4M
377		------01 mem=4M
378		------10 mem=8M
379		------11 mem=16M
380		-----0-- smem=hM
381		-----1-- smem=2M
382		----0--- vmem=1M
383		----1--- vmem=2M
384		000----- rev=-2
385		001----- rev=-1
386		010----- rev=0
387		011----- rev=1
388		100----- rev=2
389		101----- rev=3
390		110----- rev=4
391		111----- rev=5
392		*/
	378	case 0x800000:
	379	boardconfig |= 2;
	380	break;
393	381
394		if( machine().primary_screen->height() == 1024 )
395		{
396		return 64|32|8|2;
	382	case 0x1000000:
	383	boardconfig |= 3;
	384	break;
397	385	}
398		else
399		{
400		return 64|32|2;
401		}
	386
	387	return boardconfig;
402	388	}
403	389
404	390	READ32_MEMBER(zn_state::unknown_r)
r22559	r22560
441	427	AM_RANGE(0xbfc00000, 0xbfc7ffff) AM_WRITENOP AM_ROM AM_SHARE("share2") /* bios mirror */
442	428	ADDRESS_MAP_END
443	429
444		static ADDRESS_MAP_START( zn_8M_map, AS_PROGRAM, 32, zn_state )
445		AM_RANGE(0x1fa10200, 0x1fa10203) AM_READ(boardconfig_8M_r)
446		AM_IMPORT_FROM(zn_map)
447		ADDRESS_MAP_END
448
449	430	static ADDRESS_MAP_START( link_map, AS_PROGRAM, 8, zn_state )
450	431	ADDRESS_MAP_END
451	432
r22559	r22560
470	451	static MACHINE_CONFIG_START( zn1_1mb_vram, zn_state )
471	452	/* basic machine hardware */
472	453	MCFG_CPU_ADD( "maincpu", CXD8530CQ, XTAL_67_7376MHz )
473		MCFG_PSX_RAM_SIZE( 0x400000 )
474	454	MCFG_CPU_PROGRAM_MAP( zn_map)
475	455
	456	MCFG_RAM_MODIFY("maincpu:ram")
	457	MCFG_RAM_DEFAULT_SIZE("4M")
	458
476	459	MCFG_DEVICE_ADD("maincpu:sio0:znsec0", ZNSEC, 0)
477	460	MCFG_DEVICE_ADD("maincpu:sio0:znsec1", ZNSEC, 0)
478	461	MCFG_DEVICE_ADD("maincpu:sio0:zndip", ZNDIP, 0)
r22559	r22560
498	481	static MACHINE_CONFIG_START( zn2, zn_state )
499	482	/* basic machine hardware */
500	483	MCFG_CPU_ADD( "maincpu", CXD8661R, XTAL_100MHz )
501		MCFG_PSX_RAM_SIZE( 0x400000 )
502	484	MCFG_CPU_PROGRAM_MAP( zn_map)
503	485
	486	MCFG_RAM_MODIFY("maincpu:ram")
	487	MCFG_RAM_DEFAULT_SIZE("4M")
	488
504	489	MCFG_DEVICE_ADD("maincpu:sio0:znsec0", ZNSEC, 0)
505	490	MCFG_DEVICE_ADD("maincpu:sio0:znsec1", ZNSEC, 0)
506	491	MCFG_DEVICE_ADD("maincpu:sio0:zndip", ZNDIP, 0)
r22559	r22560
1447	1432	}
1448	1433
1449	1434	static MACHINE_CONFIG_DERIVED( coh1000w, zn1_2mb_vram )
1450		MCFG_CPU_MODIFY("maincpu")
1451		MCFG_PSX_RAM_SIZE( 0x800000 )
1452		MCFG_CPU_PROGRAM_MAP(zn_8M_map)
	1435	MCFG_RAM_MODIFY("maincpu:ram")
	1436	MCFG_RAM_DEFAULT_SIZE("8M")
1453	1437
1454	1438	MCFG_MACHINE_RESET_OVERRIDE(zn_state, coh1000w )
1455	1439

trunk/src/mame/drivers/namcos10.c

r22559	r22560
595	595	static MACHINE_CONFIG_START( namcos10_memm, namcos10_state )
596	596	/* basic machine hardware */
597	597	MCFG_CPU_ADD( "maincpu", CXD8606BQ, XTAL_101_4912MHz )
598		MCFG_PSX_RAM_SIZE( 0x1000000 )
599	598	MCFG_CPU_PROGRAM_MAP( namcos10_memm_map )
600	599
	600	MCFG_RAM_MODIFY("maincpu:ram")
	601	MCFG_RAM_DEFAULT_SIZE("16M")
	602
601	603	MCFG_MACHINE_RESET_OVERRIDE(namcos10_state, namcos10 )
602	604
603	605	/* video hardware */
r22559	r22560
610	612	static MACHINE_CONFIG_START( namcos10_memn, namcos10_state )
611	613	/* basic machine hardware */
612	614	MCFG_CPU_ADD( "maincpu", CXD8606BQ, XTAL_101_4912MHz )
613		MCFG_PSX_RAM_SIZE( 0x1000000 )
614	615	MCFG_CPU_PROGRAM_MAP( namcos10_memn_map )
615	616
	617	MCFG_RAM_MODIFY("maincpu:ram")
	618	MCFG_RAM_DEFAULT_SIZE("16M")
	619
616	620	MCFG_MACHINE_RESET_OVERRIDE(namcos10_state, namcos10 )
617	621
618	622	/* video hardware */

trunk/src/mame/drivers/namcos12.c

r22559	r22560
1044	1044	public:
1045	1045	namcos12_state(const machine_config &mconfig, device_type type, const char *tag)
1046	1046	: driver_device(mconfig, type, tag),
1047		m_rtc(*this, "rtc"),
1048		m_sharedram(*this, "sharedram") ,
1049		m_maincpu(*this, "maincpu") { }
	1047	m_rtc(*this, "rtc"),
	1048	m_sharedram(*this, "sharedram") ,
	1049	m_maincpu(*this, "maincpu"),
	1050	m_ram(*this, "maincpu:ram")
	1051	{
	1052	}
1050	1053
1051	1054	required_device<rtc4543_device> m_rtc;
1052	1055	required_shared_ptr<UINT32> m_sharedram;
r22559	r22560
1102	1105	void namcos12_sub_irq( screen_device &screen, bool vblank_state );
1103	1106	void system11gun_install(  );
1104	1107	required_device<psxcpu_device> m_maincpu;
	1108	required_device<ram_device> m_ram;
1105	1109	};
1106	1110
1107	1111	inline void ATTR_PRINTF(3,4) namcos12_state::verboselog( int n_level, const char *s_fmt, ... )
r22559	r22560
1193	1197	INT32 n_ramleft;
1194	1198
1195	1199	// TODO: the check for going past the end of ram should be in dma.c
1196		UINT32 m_n_psxramsize = m_maincpu->ram_size();
	1200	UINT32 m_n_psxramsize = m_ram->size();
1197	1201
1198	1202	if(m_has_tektagt_dma && !m_n_dmaoffset)
1199	1203	{
r22559	r22560
1621	1625	static MACHINE_CONFIG_START( coh700, namcos12_state )
1622	1626	/* basic machine hardware */
1623	1627	MCFG_CPU_ADD( "maincpu", CXD8661R, XTAL_100MHz )
1624		MCFG_PSX_RAM_SIZE( 0x400000 )
1625	1628	MCFG_CPU_PROGRAM_MAP( namcos12_map)
1626	1629
	1630	MCFG_RAM_MODIFY("maincpu:ram")
	1631	MCFG_RAM_DEFAULT_SIZE("4M")
	1632
1627	1633	MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 5, psx_dma_read_delegate( FUNC( namcos12_state::namcos12_rom_read ), (namcos12_state *) owner ) )
1628	1634
1629	1635	MCFG_CPU_ADD("sub", H83002, 16737350 )

trunk/src/mame/drivers/konamigq.c

r22559	r22560
311	311	static MACHINE_CONFIG_START( konamigq, konamigq_state )
312	312	/* basic machine hardware */
313	313	MCFG_CPU_ADD( "maincpu", CXD8530BQ, XTAL_67_7376MHz )
314		MCFG_PSX_RAM_SIZE( 0x400000 )
315	314	MCFG_CPU_PROGRAM_MAP( konamigq_map )
316	315
	316	MCFG_RAM_MODIFY("maincpu:ram")
	317	MCFG_RAM_DEFAULT_SIZE("4M")
	318
317	319	MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 5, psx_dma_read_delegate( FUNC( konamigq_state::scsi_dma_read ), (konamigq_state *) owner ) )
318	320	MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 5, psx_dma_write_delegate( FUNC( konamigq_state::scsi_dma_write ), (konamigq_state *) owner ) )
319	321

trunk/src/mame/drivers/twinkle.c

r22559	r22560
853	853	static MACHINE_CONFIG_START( twinkle, twinkle_state )
854	854	/* basic machine hardware */
855	855	MCFG_CPU_ADD( "maincpu", CXD8530CQ, XTAL_67_7376MHz )
856		MCFG_PSX_RAM_SIZE( 0x400000 )
857	856	MCFG_CPU_PROGRAM_MAP( main_map )
858	857
	858	MCFG_RAM_MODIFY("maincpu:ram")
	859	MCFG_RAM_DEFAULT_SIZE("4M")
	860
859	861	MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 5, psx_dma_read_delegate( FUNC( scsi_dma_read ), (twinkle_state *) owner ) )
860	862	MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 5, psx_dma_write_delegate( FUNC( scsi_dma_write ), (twinkle_state *) owner ) )
861	863

trunk/src/emu/cpu/psx/psx.c

r22559	r22560
1294	1294	break;
1295	1295	}
1296	1296
1297		assert( m_ram_size != 0 );
	1297	UINT32 ram_size = m_ram->size();
	1298	UINT8 *pointer = m_ram->pointer();
	1299
1298	1300	assert( window_size != 0 );
1299	1301
1300	1302	int start = 0;
1301	1303	while( start < window_size )
1302	1304	{
1303		m_program->install_ram( start + 0x00000000, start + 0x00000000 + m_ram_size - 1, m_ram );
1304		m_program->install_ram( start + 0x80000000, start + 0x80000000 + m_ram_size - 1, m_ram );
1305		m_program->install_ram( start + 0xa0000000, start + 0xa0000000 + m_ram_size - 1, m_ram );
	1305	m_program->install_ram( start + 0x00000000, start + 0x00000000 + ram_size - 1, pointer );
	1306	m_program->install_ram( start + 0x80000000, start + 0x80000000 + ram_size - 1, pointer );
	1307	m_program->install_ram( start + 0xa0000000, start + 0xa0000000 + ram_size - 1, pointer );
1306	1308
1307		start += m_ram_size;
	1309	start += ram_size;
1308	1310	}
1309	1311
1310	1312	m_program->install_readwrite_handler( 0x00000000 + window_size, 0x1effffff, read32_delegate( FUNC(psxcpu_device::berr_r), this ), write32_delegate( FUNC(psxcpu_device::berr_w), this ) );
r22559	r22560
1625	1627	m_spu_write_handler(*this),
1626	1628	m_cd_read_handler(*this),
1627	1629	m_cd_write_handler(*this),
1628		m_ram_size(0)
	1630	m_ram(*this, "ram")
1629	1631	{
1630	1632	}
1631	1633
r22559	r22560
1660	1662	}
1661	1663
1662	1664	//-------------------------------------------------
1663		//  set_ram_size - configuration helper
1664		//  to set the ram size
1665		//-------------------------------------------------
1666
1667		void psxcpu_device::set_ram_size(device_t &device, UINT32 ram_size)
1668		{
1669		downcast<psxcpu_device &>(device).m_ram_size = ram_size;
1670		}
1671
1672
1673		//-------------------------------------------------
1674		//  ram_size - temporary kludge to allow
1675		//  access to the current ram size
1676		//-------------------------------------------------
1677
1678		UINT32 psxcpu_device::ram_size()
1679		{
1680		return m_ram_size;
1681		}
1682
1683		//-------------------------------------------------
1684		//  ram - temporary kludge to allow
1685		//  access to the current ram
1686		//-------------------------------------------------
1687
1688		UINT32 *psxcpu_device::ram()
1689		{
1690		return m_ram;
1691		}
1692
1693		//-------------------------------------------------
1694	1665	//  device_start - start up the device
1695	1666	//-------------------------------------------------
1696	1667
r22559	r22560
1847	1818	m_spu_write_handler.resolve_safe();
1848	1819	m_cd_read_handler.resolve_safe(0);
1849	1820	m_cd_write_handler.resolve_safe();
1850
1851		m_ram = global_alloc_array( UINT32, m_ram_size / 4 );
1852		save_pointer( NAME(m_ram), m_ram_size / 4 );
1853
1854		m_ram_config = 0x800;
1855		update_ram_config();
1856
1857		/// TODO: get dma to acess ram through the memory map?
1858		psxdma_device *psxdma = subdevice<psxdma_device>( "dma" );
1859		psxdma->m_ram = m_ram;
1860		psxdma->m_ramsize = m_ram_size;
1861	1821	}
1862	1822
1863	1823
1864	1824	//-------------------------------------------------
1865		//  device_stop - stop the device
1866		//-------------------------------------------------
1867
1868		void psxcpu_device::device_stop()
1869		{
1870		global_free( m_ram );
1871		}
1872
1873
1874		//-------------------------------------------------
1875	1825	//  device_reset - reset the device
1876	1826	//-------------------------------------------------
1877	1827
1878	1828	void psxcpu_device::device_reset()
1879	1829	{
	1830	m_ram_config = 0x800;
	1831	update_ram_config();
	1832
	1833	/// TODO: get dma to access ram through the memory map?
	1834	psxdma_device *psxdma = subdevice<psxdma_device>( "dma" );
	1835	psxdma->m_ram = (UINT32 *) m_ram->pointer();
	1836	psxdma->m_ramsize = m_ram->size();
	1837
1880	1838	m_delayr = 0;
1881	1839	m_delayv = 0;
1882	1840	m_berr = 0;
r22559	r22560
3320	3278
3321	3279	MCFG_DEVICE_ADD("sio1", PSX_SIO1, 0)
3322	3280	MCFG_PSX_SIO_IRQ_HANDLER(DEVWRITELINE("irq", psxirq_device, intin8))
	3281
	3282	MCFG_RAM_ADD("ram")
3323	3283	MACHINE_CONFIG_END
3324	3284
3325	3285	//-------------------------------------------------

trunk/src/emu/cpu/psx/psx.h

r22559	r22560
10	10	#ifndef __PSXCPU_H__
11	11	#define __PSXCPU_H__
12	12
	13	#include "emu.h"
	14	#include "machine/ram.h"
13	15	#include "dma.h"
14	16	#include "gte.h"
15	17	#include "irq.h"
r22559	r22560
125	127	#define MCFG_PSX_CD_WRITE_HANDLER(_devcb) \
126	128	devcb = &psxcpu_device::set_cd_write_handler(*device, DEVCB2_##_devcb);
127	129
128		#define MCFG_PSX_RAM_SIZE( size ) \
129		psxcpu_device::set_ram_size( *device, size );
130
131	130	//**************************************************************************
132	131	//  TYPE DEFINITIONS
133	132	//**************************************************************************
r22559	r22560
147	146	template<class _Object> static devcb2_base &set_spu_write_handler(device_t &device, _Object object) { return downcast<psxcpu_device &>(device).m_spu_write_handler.set_callback(object); }
148	147	template<class _Object> static devcb2_base &set_cd_read_handler(device_t &device, _Object object) { return downcast<psxcpu_device &>(device).m_cd_read_handler.set_callback(object); }
149	148	template<class _Object> static devcb2_base &set_cd_write_handler(device_t &device, _Object object) { return downcast<psxcpu_device &>(device).m_cd_write_handler.set_callback(object); }
150		static void set_ram_size(device_t &device, UINT32 size);
151	149
152	150	// public interfaces
153	151	DECLARE_WRITE32_MEMBER( berr_w );
r22559	r22560
173	171
174	172	static psxcpu_device *getcpu( device_t &device, const char *cputag );
175	173
176		UINT32 ram_size();
177		UINT32 *ram();
178
179	174	protected:
180	175	psxcpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
181	176
182	177	// device-level overrides
183	178	virtual void device_start();
184		virtual void device_stop();
185	179	virtual void device_reset();
186	180	virtual void device_post_load();
187	181	virtual machine_config_constructor device_mconfig_additions() const;
r22559	r22560
319	313	devcb2_write16 m_spu_write_handler;
320	314	devcb2_read8 m_cd_read_handler;
321	315	devcb2_write8 m_cd_write_handler;
322		UINT32 *m_ram;
323		UINT32 m_ram_size;
	316	required_device<ram_device> m_ram;
324	317	};
325	318
326	319	class cxd8530aq_device : public psxcpu_device

trunk/src/emu/device.c

r22559	r22560
817	817	// iterate over all devices and remove any references to the old device
818	818	device_iterator iter(mconfig().root_device());
819	819	for (device_t *scan = iter.first(); scan != NULL; scan = iter.next())
820		scan->m_device_map.remove(&old);
	820	scan->m_device_map.reset(); //remove(&old);
821	821
822	822	// create a new device, and substitute it for the old one
823	823	device_t *device = (*type)(mconfig(), tag, this, clock);
r22559	r22560
840	840	// iterate over all devices and remove any references
841	841	device_iterator iter(mconfig().root_device());
842	842	for (device_t *scan = iter.first(); scan != NULL; scan = iter.next())
843		scan->m_device_map.remove(&device);
	843	scan->m_device_map.reset(); //remove(&device);
844	844
845	845	// remove from our list
846	846	m_subdevice_list.remove(device);

trunk/src/mess/drivers/psx.c

r22559	r22560
25	25	public:
26	26	psx1_state(const machine_config &mconfig, device_type type, const char *tag)
27	27	: driver_device(mconfig, type, tag) ,
28		m_maincpu(*this, "maincpu") { }
	28	m_maincpu(*this, "maincpu"),
	29	m_ram(*this, "maincpu:ram")
	30	{
	31	}
29	32
30	33	UINT8 *m_exe_buffer;
31	34	int m_exe_size;
r22559	r22560
52	55	void cd_dma_write( UINT32 *p_n_psxram, UINT32 n_address, INT32 n_size );
53	56	DECLARE_QUICKLOAD_LOAD_MEMBER( psx_exe_load );
54	57	required_device<psxcpu_device> m_maincpu;
	58	required_device<ram_device> m_ram;
55	59	};
56	60
57	61
r22559	r22560
113	117	if( n_len >= sizeof( struct PSXEXE_HEADER ) &&
114	118	memcmp( psxexe_header->id, "PS-X EXE", 8 ) == 0 )
115	119	{
116		UINT8 *p_ram;
117		UINT8 *p_psxexe;
118		UINT32 n_stack;
119		UINT32 n_ram;
120		UINT32 n_address;
121		UINT32 n_size;
122
123	120	psxexe_conv32( &psxexe_header->text );
124	121	psxexe_conv32( &psxexe_header->data );
125	122	psxexe_conv32( &psxexe_header->pc0 );
r22559	r22560
146	143	logerror( "psx_exe_load: sp    %08x\n", psxexe_header->s_addr );
147	144	logerror( "psx_exe_load: len   %08x\n", psxexe_header->s_size );
148	145
149		p_ram = (UINT8 *)m_maincpu->ram();
150		n_ram = m_maincpu->ram_size();
	146	UINT8 *p_ram = m_ram->pointer();
	147	UINT32 n_ram = m_ram->size();
151	148
152		p_psxexe = p_n_file + sizeof( struct PSXEXE_HEADER );
	149	UINT8 *p_psxexe = p_n_file + sizeof( struct PSXEXE_HEADER );
153	150
154		n_address = psxexe_header->t_addr;
155		n_size = psxexe_header->t_size;
	151	UINT32 n_address = psxexe_header->t_addr;
	152	UINT32 n_size = psxexe_header->t_size;
156	153	while( n_size != 0 )
157	154	{
158	155	p_ram[ BYTE4_XOR_LE( n_address ) % n_ram ] = *( p_psxexe );
r22559	r22560
163	160
164	161	cpu->set_state_int( PSXCPU_PC, psxexe_header->pc0 );
165	162	cpu->set_state_int( PSXCPU_R28, psxexe_header->gp0 );
166		n_stack = psxexe_header->s_addr + psxexe_header->s_size;
	163	UINT32 n_stack = psxexe_header->s_addr + psxexe_header->s_size;
167	164	if( n_stack != 0 )
168	165	{
169	166	cpu->set_state_int( PSXCPU_R29, n_stack );
r22559	r22560
249	246	( (int)p_n_file[ n_offset + 6 ] << 16 ) |
250	247	( (int)p_n_file[ n_offset + 7 ] << 24 );
251	248
252		UINT8 *p_ram = (UINT8 *)m_maincpu->ram();
253		UINT32 n_ram = m_maincpu->ram_size();
	249	UINT8 *p_ram = m_ram->pointer();
	250	UINT32 n_ram = m_ram->size();
254	251
255	252	n_offset += 8;
256	253
r22559	r22560
496	493	static MACHINE_CONFIG_START( psxntsc, psx1_state )
497	494	/* basic machine hardware */
498	495	MCFG_CPU_ADD( "maincpu", CXD8530CQ, XTAL_67_7376MHz )
499		MCFG_PSX_RAM_SIZE( 0x200000 )
500	496	MCFG_CPU_PROGRAM_MAP( psx_map )
501	497
	498	MCFG_RAM_MODIFY("maincpu:ram")
	499	MCFG_RAM_DEFAULT_SIZE("2M")
	500
502	501	MCFG_DEVICE_ADD("maincpu:sio0:controllers", PSXCONTROLLERPORTS, 0)
503	502	MCFG_PSX_CTRL_PORT_ADD("port1", psx_controllers, "digital_pad", NULL)
504	503	MCFG_PSX_CTRL_PORT_ADD("port2", psx_controllers, "digital_pad", NULL)
r22559	r22560
530	529	static MACHINE_CONFIG_START( psxpal, psx1_state )
531	530	/* basic machine hardware */
532	531	MCFG_CPU_ADD( "maincpu", CXD8530AQ, XTAL_67_7376MHz )
533		MCFG_PSX_RAM_SIZE( 0x200000 )
534	532	MCFG_CPU_PROGRAM_MAP( psx_map)
535	533
	534	MCFG_RAM_MODIFY("maincpu:ram")
	535	MCFG_RAM_DEFAULT_SIZE("2M")
	536
536	537	MCFG_DEVICE_ADD("maincpu:sio0:controllers", PSXCONTROLLERPORTS, 0)
537	538	MCFG_PSX_CTRL_PORT_ADD("port1", psx_controllers, "digital_pad", NULL)
538	539	MCFG_PSX_CTRL_PORT_ADD("port2", psx_controllers, "digital_pad", NULL)

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