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r22524 Wednesday 24th April, 2013 at 09:50:14 UTC by Miodrag Milanović
modernized 2 drivers skipped in past (nw)

[src/mame/drivers]

gammagic.c vlc.c

trunk/src/mame/drivers/gammagic.c

r22523	r22524
76	76	public:
77	77	gammagic_state(const machine_config &mconfig, device_type type, const char *tag)
78	78	: driver_device(mconfig, type, tag),
	79	m_pit8254(*this, "pit8254" ),
	80	m_pic8259_1(*this, "pic8259_1" ),
	81	m_pic8259_2(*this,  "pic8259_2" ),
	82	m_dma8237_1(*this, "dma8237_1" ),
	83	m_dma8237_2(*this, "dma8237_2" ),
79	84	m_maincpu(*this, "maincpu") { }
80	85
81	86	int m_dma_channel;
82	87	UINT8 m_dma_offset[2][4];
83	88	UINT8 m_at_pages[0x10];
84	89
85		device_t    *m_pit8254;
86		device_t    *m_pic8259_1;
87		device_t    *m_pic8259_2;
88		i8237_device    *m_dma8237_1;
89		i8237_device    *m_dma8237_2;
	90	required_device<device_t> m_pit8254;
	91	required_device<device_t> m_pic8259_1;
	92	required_device<device_t> m_pic8259_2;
	93	required_device<i8237_device> m_dma8237_1;
	94	required_device<i8237_device> m_dma8237_2;
90	95
91	96	emu_timer *m_atapi_timer;
92	97	//SCSIInstance *m_inserted_cdrom;
r22523	r22524
104	109	DECLARE_DRIVER_INIT(gammagic);
105	110	IRQ_CALLBACK_MEMBER(irq_callback);
106	111	DECLARE_READ8_MEMBER(get_out2);
	112	DECLARE_READ8_MEMBER(at_page8_r);
	113	DECLARE_WRITE8_MEMBER(at_page8_w);
	114	DECLARE_READ8_MEMBER(pc_dma_read_byte);
	115	DECLARE_WRITE8_MEMBER(pc_dma_write_byte);
	116	DECLARE_READ8_MEMBER(at_dma8237_2_r);
	117	DECLARE_WRITE8_MEMBER(at_dma8237_2_w);
	118	DECLARE_WRITE_LINE_MEMBER(pc_dma_hrq_changed);
	119	void set_dma_channel(int channel, int state);
	120	DECLARE_WRITE_LINE_MEMBER(pc_dack0_w);
	121	DECLARE_WRITE_LINE_MEMBER(pc_dack1_w);
	122	DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
	123	DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
	124	DECLARE_WRITE_LINE_MEMBER(gammagic_pic8259_1_set_int_line);
	125	DECLARE_READ8_MEMBER(get_slave_ack);
	126
	127	virtual void machine_start();
	128	virtual void machine_reset();
	129	void atapi_init();
107	130	required_device<cpu_device> m_maincpu;
108	131	};
109	132
110		//static void atapi_irq(running_machine &machine, int state);
111
112		static READ8_DEVICE_HANDLER(at_dma8237_2_r)
	133	READ8_MEMBER(gammagic_state::at_dma8237_2_r)
113	134	{
114		gammagic_state *state = space.machine().driver_data<gammagic_state>();
115		return state->m_dma8237_2->i8237_r(space, offset / 2);
	135	return m_dma8237_2->i8237_r(space, offset / 2);
116	136	}
117	137
118		static WRITE8_DEVICE_HANDLER(at_dma8237_2_w)
	138	WRITE8_MEMBER(gammagic_state::at_dma8237_2_w)
119	139	{
120		gammagic_state *state = space.machine().driver_data<gammagic_state>();
121		state->m_dma8237_2->i8237_w(space, offset / 2, data);
	140	m_dma8237_2->i8237_w(space, offset / 2, data);
122	141	}
123	142
124		static READ8_HANDLER(at_page8_r)
	143	READ8_MEMBER(gammagic_state::at_page8_r)
125	144	{
126		gammagic_state *state = space.machine().driver_data<gammagic_state>();
127		UINT8 data = state->m_at_pages[offset % 0x10];
	145	UINT8 data = m_at_pages[offset % 0x10];
128	146
129	147	switch(offset % 8) {
130	148	case 1:
131		data = state->m_dma_offset[(offset / 8) & 1][2];
	149	data = m_dma_offset[(offset / 8) & 1][2];
132	150	break;
133	151	case 2:
134		data = state->m_dma_offset[(offset / 8) & 1][3];
	152	data = m_dma_offset[(offset / 8) & 1][3];
135	153	break;
136	154	case 3:
137		data = state->m_dma_offset[(offset / 8) & 1][1];
	155	data = m_dma_offset[(offset / 8) & 1][1];
138	156	break;
139	157	case 7:
140		data = state->m_dma_offset[(offset / 8) & 1][0];
	158	data = m_dma_offset[(offset / 8) & 1][0];
141	159	break;
142	160	}
143	161	return data;
144	162	}
145	163
146		static WRITE8_HANDLER(at_page8_w)
	164
	165	WRITE8_MEMBER(gammagic_state::at_page8_w)
147	166	{
148		gammagic_state *state = space.machine().driver_data<gammagic_state>();
149		state->m_at_pages[offset % 0x10] = data;
	167	m_at_pages[offset % 0x10] = data;
150	168
151	169	switch(offset % 8) {
152	170	case 1:
153		state->m_dma_offset[(offset / 8) & 1][2] = data;
	171	m_dma_offset[(offset / 8) & 1][2] = data;
154	172	break;
155	173	case 2:
156		state->m_dma_offset[(offset / 8) & 1][3] = data;
	174	m_dma_offset[(offset / 8) & 1][3] = data;
157	175	break;
158	176	case 3:
159		state->m_dma_offset[(offset / 8) & 1][1] = data;
	177	m_dma_offset[(offset / 8) & 1][1] = data;
160	178	break;
161	179	case 7:
162		state->m_dma_offset[(offset / 8) & 1][0] = data;
	180	m_dma_offset[(offset / 8) & 1][0] = data;
163	181	break;
164	182	}
165	183	}
166	184
167		static WRITE_LINE_DEVICE_HANDLER( pc_dma_hrq_changed )
	185
	186	WRITE_LINE_MEMBER(gammagic_state::pc_dma_hrq_changed)
168	187	{
169		gammagic_state *drvstate = device->machine().driver_data<gammagic_state>();
170		drvstate->m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
	188	m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
171	189
172	190	/* Assert HLDA */
173		drvstate->m_dma8237_1->i8237_hlda_w( state );
	191	m_dma8237_1->i8237_hlda_w(state);
174	192	}
175	193
176		static READ8_HANDLER( pc_dma_read_byte )
	194
	195	READ8_MEMBER(gammagic_state::pc_dma_read_byte)
177	196	{
178		gammagic_state *state = space.machine().driver_data<gammagic_state>();
179		offs_t page_offset = (((offs_t) state->m_dma_offset[0][state->m_dma_channel]) << 16)
	197	offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16)
180	198	& 0xFF0000;
181	199
182	200	return space.read_byte(page_offset + offset);
183	201	}
184	202
185		static WRITE8_HANDLER( pc_dma_write_byte )
	203
	204	WRITE8_MEMBER(gammagic_state::pc_dma_write_byte)
186	205	{
187		gammagic_state *state = space.machine().driver_data<gammagic_state>();
188		offs_t page_offset = (((offs_t) state->m_dma_offset[0][state->m_dma_channel]) << 16)
	206	offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16)
189	207	& 0xFF0000;
190	208
191	209	space.write_byte(page_offset + offset, data);
192	210	}
193	211
194		static void set_dma_channel(device_t *device, int channel, int state)
	212	void gammagic_state::set_dma_channel(int channel, int state)
195	213	{
196		gammagic_state *drvstate = device->machine().driver_data<gammagic_state>();
197		if (!state) drvstate->m_dma_channel = channel;
	214	if (!state) m_dma_channel = channel;
198	215	}
199	216
200		static WRITE_LINE_DEVICE_HANDLER( pc_dack0_w ) { set_dma_channel(device, 0, state); }
201		static WRITE_LINE_DEVICE_HANDLER( pc_dack1_w ) { set_dma_channel(device, 1, state); }
202		static WRITE_LINE_DEVICE_HANDLER( pc_dack2_w ) { set_dma_channel(device, 2, state); }
203		static WRITE_LINE_DEVICE_HANDLER( pc_dack3_w ) { set_dma_channel(device, 3, state); }
	217	WRITE_LINE_MEMBER(gammagic_state::pc_dack0_w){ set_dma_channel(0, state); }
	218	WRITE_LINE_MEMBER(gammagic_state::pc_dack1_w){ set_dma_channel(1, state); }
	219	WRITE_LINE_MEMBER(gammagic_state::pc_dack2_w){ set_dma_channel(2, state); }
	220	WRITE_LINE_MEMBER(gammagic_state::pc_dack3_w){ set_dma_channel(3, state); }
204	221
205	222	static I8237_INTERFACE( dma8237_1_config )
206	223	{
207		DEVCB_LINE(pc_dma_hrq_changed),
	224	DEVCB_DRIVER_LINE_MEMBER(gammagic_state,pc_dma_hrq_changed),
208	225	DEVCB_NULL,
209		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_read_byte),
210		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_write_byte),
	226	DEVCB_DRIVER_MEMBER(gammagic_state, pc_dma_read_byte),
	227	DEVCB_DRIVER_MEMBER(gammagic_state, pc_dma_write_byte),
211	228	{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
212	229	{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
213		{ DEVCB_LINE(pc_dack0_w), DEVCB_LINE(pc_dack1_w), DEVCB_LINE(pc_dack2_w), DEVCB_LINE(pc_dack3_w) }
	230	{ DEVCB_DRIVER_LINE_MEMBER(gammagic_state,pc_dack0_w), DEVCB_DRIVER_LINE_MEMBER(gammagic_state,pc_dack1_w), DEVCB_DRIVER_LINE_MEMBER(gammagic_state,pc_dack2_w), DEVCB_DRIVER_LINE_MEMBER(gammagic_state,pc_dack3_w) }
214	231	};
215	232
216	233	static I8237_INTERFACE( dma8237_2_config )
r22523	r22524
224	241	{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
225	242	};
226	243	/*
227		static READ32_HANDLER( atapi_r )
	244	READ32_MEMBER( gammagic_state::atapi_r )
228	245	{
229		gammagic_state *state = space.machine().driver_data<gammagic_state>();
230		UINT8 *atapi_regs = state->m_atapi_regs;
	246	UINT8 *atapi_regs = m_atapi_regs;
231	247	//running_machine &machine = space.machine();
232	248	int reg, data;
233	249
234	250	if (mem_mask == 0x0000ffff) // word-wide command read
235	251	{
236		logerror("ATAPI: packet read = %04x\n", state->m_atapi_data[state->m_atapi_data_ptr]);
	252	logerror("ATAPI: packet read = %04x\n", m_atapi_data[m_atapi_data_ptr]);
237	253
238	254	// assert IRQ and drop DRQ
239		if (state->m_atapi_data_ptr == 0 && state->m_atapi_data_len == 0)
	255	if (m_atapi_data_ptr == 0 && m_atapi_data_len == 0)
240	256	{
241	257	// get the data from the device
242		if( state->m_atapi_xferlen > 0 )
	258	if( m_atapi_xferlen > 0 )
243	259	{
244		SCSIReadData( state->m_inserted_cdrom, state->m_atapi_data, state->m_atapi_xferlen );
245		state->m_atapi_data_len = state->m_atapi_xferlen;
	260	SCSIReadData( m_inserted_cdrom, m_atapi_data, m_atapi_xferlen );
	261	m_atapi_data_len = m_atapi_xferlen;
246	262	}
247	263
248		if (state->m_atapi_xfermod > MAX_TRANSFER_SIZE)
	264	if (m_atapi_xfermod > MAX_TRANSFER_SIZE)
249	265	{
250		state->m_atapi_xferlen = MAX_TRANSFER_SIZE;
251		state->m_atapi_xfermod = state->m_atapi_xfermod - MAX_TRANSFER_SIZE;
	266	m_atapi_xferlen = MAX_TRANSFER_SIZE;
	267	m_atapi_xfermod = m_atapi_xfermod - MAX_TRANSFER_SIZE;
252	268	}
253	269	else
254	270	{
255		state->m_atapi_xferlen = state->m_atapi_xfermod;
256		state->m_atapi_xfermod = 0;
	271	m_atapi_xferlen = m_atapi_xfermod;
	272	m_atapi_xfermod = 0;
257	273	}
258	274
259		//verboselog\\( machine, 2, "atapi_r: atapi_xferlen=%d\n", state->m_atapi_xferlen );
260		if( state->m_atapi_xferlen != 0 )
	275	//verboselog\\( machine, 2, "atapi_r: atapi_xferlen=%d\n", m_atapi_xferlen );
	276	if( m_atapi_xferlen != 0 )
261	277	{
262	278	atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ | ATAPI_STAT_SERVDSC;
263	279	atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
r22523	r22524
269	285	atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
270	286	}
271	287
272		atapi_regs[ATAPI_REG_COUNTLOW] = state->m_atapi_xferlen & 0xff;
273		atapi_regs[ATAPI_REG_COUNTHIGH] = (state->m_atapi_xferlen>>8)&0xff;
	288	atapi_regs[ATAPI_REG_COUNTLOW] = m_atapi_xferlen & 0xff;
	289	atapi_regs[ATAPI_REG_COUNTHIGH] = (m_atapi_xferlen>>8)&0xff;
274	290
275	291	atapi_irq(space.machine(), ASSERT_LINE);
276	292	}
277	293
278		if( state->m_atapi_data_ptr < state->m_atapi_data_len )
	294	if( m_atapi_data_ptr < m_atapi_data_len )
279	295	{
280		data = state->m_atapi_data[state->m_atapi_data_ptr++];
281		data |= ( state->m_atapi_data[state->m_atapi_data_ptr++] << 8 );
282		if( state->m_atapi_data_ptr >= state->m_atapi_data_len )
	296	data = m_atapi_data[m_atapi_data_ptr++];
	297	data |= ( m_atapi_data[m_atapi_data_ptr++] << 8 );
	298	if( m_atapi_data_ptr >= m_atapi_data_len )
283	299	{
284	300
285		state->m_atapi_data_ptr = 0;
286		state->m_atapi_data_len = 0;
	301	m_atapi_data_ptr = 0;
	302	m_atapi_data_len = 0;
287	303
288		if( state->m_atapi_xferlen == 0 )
	304	if( m_atapi_xferlen == 0 )
289	305	{
290	306	atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
291	307	atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
r22523	r22524
330	346	return data;
331	347	}
332	348
333		static WRITE32_HANDLER( atapi_w )
	349	WRITE32_MEMBER( gammagic_state::atapi_w )
334	350	{
335		gammagic_state *state = space.machine().driver_data<gammagic_state>();
336		UINT8 *atapi_regs = state->m_atapi_regs;
337		UINT8 *atapi_data = state->m_atapi_data;
	351	UINT8 *atapi_regs = m_atapi_regs;
	352	UINT8 *atapi_data = m_atapi_data;
338	353	int reg;
339	354	if (mem_mask == 0x0000ffff) // word-wide command write
340	355	{
341		atapi_data[state->m_atapi_data_ptr++] = data & 0xff;
342		atapi_data[state->m_atapi_data_ptr++] = data >> 8;
	356	atapi_data[m_atapi_data_ptr++] = data & 0xff;
	357	atapi_data[m_atapi_data_ptr++] = data >> 8;
343	358
344		if (state->m_atapi_cdata_wait)
	359	if (m_atapi_cdata_wait)
345	360	{
346		logerror("ATAPI: waiting, ptr %d wait %d\n", state->m_atapi_data_ptr, state->m_atapi_cdata_wait);
347		if (state->m_atapi_data_ptr == state->m_atapi_cdata_wait)
	361	logerror("ATAPI: waiting, ptr %d wait %d\n", m_atapi_data_ptr, m_atapi_cdata_wait);
	362	if (m_atapi_data_ptr == m_atapi_cdata_wait)
348	363	{
349	364	// send it to the device
350		SCSIWriteData( state->m_inserted_cdrom, atapi_data, state->m_atapi_cdata_wait );
	365	SCSIWriteData( m_inserted_cdrom, atapi_data, m_atapi_cdata_wait );
351	366
352	367	// assert IRQ
353	368	atapi_irq(space.machine(), ASSERT_LINE);
r22523	r22524
357	372	}
358	373	}
359	374
360		else if ( state->m_atapi_data_ptr == 12 )
	375	else if ( m_atapi_data_ptr == 12 )
361	376	{
362	377	int phase;
363	378	// reset data pointer for reading SCSI results
364		state->m_atapi_data_ptr = 0;
365		state->m_atapi_data_len = 0;
	379	m_atapi_data_ptr = 0;
	380	m_atapi_data_len = 0;
366	381
367	382	// send it to the SCSI device
368		SCSISetCommand( state->m_inserted_cdrom, state->m_atapi_data, 12 );
369		SCSIExecCommand( state->m_inserted_cdrom, &state->m_atapi_xferlen );
370		SCSIGetPhase( state->m_inserted_cdrom, &phase );
	383	SCSISetCommand( m_inserted_cdrom, m_atapi_data, 12 );
	384	SCSIExecCommand( m_inserted_cdrom, &m_atapi_xferlen );
	385	SCSIGetPhase( m_inserted_cdrom, &phase );
371	386
372		if (state->m_atapi_xferlen != -1)
	387	if (m_atapi_xferlen != -1)
373	388	{
374		logerror("ATAPI: SCSI command %02x returned %d bytes from the device\n", atapi_data[0]&0xff, state->m_atapi_xferlen);
	389	logerror("ATAPI: SCSI command %02x returned %d bytes from the device\n", atapi_data[0]&0xff, m_atapi_xferlen);
375	390
376	391	// store the returned command length in the ATAPI regs, splitting into
377	392	// multiple transfers if necessary
378		state->m_atapi_xfermod = 0;
379		if (state->m_atapi_xferlen > MAX_TRANSFER_SIZE)
	393	m_atapi_xfermod = 0;
	394	if (m_atapi_xferlen > MAX_TRANSFER_SIZE)
380	395	{
381		state->m_atapi_xfermod = state->m_atapi_xferlen - MAX_TRANSFER_SIZE;
382		state->m_atapi_xferlen = MAX_TRANSFER_SIZE;
	396	m_atapi_xfermod = m_atapi_xferlen - MAX_TRANSFER_SIZE;
	397	m_atapi_xferlen = MAX_TRANSFER_SIZE;
383	398	}
384	399
385		atapi_regs[ATAPI_REG_COUNTLOW] = state->m_atapi_xferlen & 0xff;
386		atapi_regs[ATAPI_REG_COUNTHIGH] = (state->m_atapi_xferlen>>8)&0xff;
	400	atapi_regs[ATAPI_REG_COUNTLOW] = m_atapi_xferlen & 0xff;
	401	atapi_regs[ATAPI_REG_COUNTHIGH] = (m_atapi_xferlen>>8)&0xff;
387	402
388		if (state->m_atapi_xferlen == 0)
	403	if (m_atapi_xferlen == 0)
389	404	{
390	405	// if no data to return, set the registers properly
391	406	atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRDY;
r22523	r22524
401	416	switch( phase )
402	417	{
403	418	case SCSI_PHASE_DATAOUT:
404		state->m_atapi_cdata_wait = state->m_atapi_xferlen;
	419	m_atapi_cdata_wait = m_atapi_xferlen;
405	420	break;
406	421	}
407	422
r22523	r22524
415	430
416	431	case 0x45: // PLAY
417	432	atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_BSY;
418		state->m_atapi_timer->adjust( downcast<cpu_device *>(&space->device())->cycles_to_attotime( ATAPI_CYCLES_PER_SECTOR ) );
	433	m_atapi_timer->adjust( downcast<cpu_device *>(&space->device())->cycles_to_attotime( ATAPI_CYCLES_PER_SECTOR ) );
419	434	break;
420	435	}
421	436
r22523	r22524
466	481	atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ;
467	482	atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_COMMAND;
468	483
469		state->m_atapi_data_ptr = 0;
470		state->m_atapi_data_len = 0;
	484	m_atapi_data_ptr = 0;
	485	m_atapi_data_len = 0;
471	486
472	487	// we have no data
473		state->m_atapi_xferlen = 0;
474		state->m_atapi_xfermod = 0;
	488	m_atapi_xferlen = 0;
	489	m_atapi_xfermod = 0;
475	490
476		state->m_atapi_cdata_wait = 0;
	491	m_atapi_cdata_wait = 0;
477	492	break;
478	493
479	494	case 0xa1:  // IDENTIFY PACKET DEVICE
480	495	atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ;
481	496
482		state->m_atapi_data_ptr = 0;
483		state->m_atapi_data_len = 512;
	497	m_atapi_data_ptr = 0;
	498	m_atapi_data_len = 512;
484	499
485	500	// we have no data
486		state->m_atapi_xferlen = 0;
487		state->m_atapi_xfermod = 0;
	501	m_atapi_xferlen = 0;
	502	m_atapi_xfermod = 0;
488	503
489		memset( atapi_data, 0, state->m_atapi_data_len );
	504	memset( atapi_data, 0, m_atapi_data_len );
490	505
491	506	atapi_data[ 0 ^ 1 ] = 0x85; // ATAPI device, cmd set 5 compliant, DRQ within 3 ms of PACKET command
492	507	atapi_data[ 1 ^ 1 ] = 0x80; // ATAPI device, removable media
r22523	r22524
532	547	case 0xef:  // SET FEATURES
533	548	atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
534	549
535		state->m_atapi_data_ptr = 0;
536		state->m_atapi_data_len = 0;
	550	m_atapi_data_ptr = 0;
	551	m_atapi_data_len = 0;
537	552
538	553	atapi_irq(space.machine(), ASSERT_LINE);
539	554	break;
r22523	r22524
561	576	AM_RANGE(0x0040, 0x005f) AM_DEVREADWRITE8_LEGACY("pit8254", pit8253_r, pit8253_w, 0xffffffff)
562	577	AM_RANGE(0x0060, 0x006f) AM_DEVREADWRITE8("kbdc", kbdc8042_device, data_r, data_w, 0xffffffff)
563	578	AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8("rtc", mc146818_device, read, write, 0xffffffff)
564		AM_RANGE(0x0080, 0x009f) AM_READWRITE8_LEGACY(at_page8_r, at_page8_w, 0xffffffff)
	579	AM_RANGE(0x0080, 0x009f) AM_READWRITE8(at_page8_r, at_page8_w, 0xffffffff)
565	580	AM_RANGE(0x00a0, 0x00bf) AM_DEVREADWRITE8_LEGACY("pic8259_2", pic8259_r, pic8259_w, 0xffffffff)
566		AM_RANGE(0x00c0, 0x00df) AM_DEVREADWRITE8_LEGACY("dma8237_2", at_dma8237_2_r, at_dma8237_2_w, 0xffffffff)
	581	AM_RANGE(0x00c0, 0x00df) AM_READWRITE8(at_dma8237_2_r, at_dma8237_2_w, 0xffffffff)
567	582	AM_RANGE(0x00e8, 0x00ef) AM_NOP
568	583	AM_RANGE(0x00f0, 0x01ef) AM_NOP
569	584	//AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(atapi_r, atapi_w)
r22523	r22524
632	647	return pic8259_acknowledge(m_pic8259_1);
633	648	}
634	649
635		static MACHINE_START(gammagic)
	650	void gammagic_state::machine_start()
636	651	{
637		gammagic_state *state = machine.driver_data<gammagic_state>();
638		state->m_maincpu->set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(gammagic_state::irq_callback),state));
639
640		state->m_pit8254 = machine.device( "pit8254" );
641		state->m_pic8259_1 = machine.device( "pic8259_1" );
642		state->m_pic8259_2 = machine.device( "pic8259_2" );
643		state->m_dma8237_1 = machine.device<i8237_device>( "dma8237_1" );
644		state->m_dma8237_2 = machine.device<i8237_device>( "dma8237_2" );
	652	m_maincpu->set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(gammagic_state::irq_callback),this));
645	653	}
646	654
647		static MACHINE_RESET( gammagic )
	655	void gammagic_state::machine_reset()
648	656	{
649		//gammagic_state *state = machine.driver_data<gammagic_state>();
650
651	657	//void *cd;
652		//SCSIGetDevice( state->m_inserted_cdrom, &cd );
	658	//SCSIGetDevice( m_inserted_cdrom, &cd );
653	659
654	660	}
655	661
656	662
657		/*static void atapi_irq(running_machine &machine, int state)
	663	/*void gammagic_state::atapi_irq(int state)
658	664	{
659		gammagic_state *drvstate = machine.driver_data<gammagic_state>();
660		pic8259_ir6_w(drvstate->m_pic8259_2, state);
	665	pic8259_ir6_w(m_pic8259_2, state);
661	666	}
662	667
663		static void atapi_exit(running_machine& machine)
	668	void gammagic_state::atapi_exit(running_machine& machine)
664	669	{
665		gammagic_state *state = machine.driver_data<gammagic_state>();
666		SCSIDeleteInstance(state->m_inserted_cdrom);
	670	SCSIDeleteInstance(m_inserted_cdrom);
667	671
668	672	}
669	673	*/
670	674
671		static void atapi_init(running_machine &machine)
	675	void gammagic_state::atapi_init()
672	676	{
673		gammagic_state *state = machine.driver_data<gammagic_state>();
	677	m_atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
	678	m_atapi_regs[ATAPI_REG_ERRFEAT] = 1;
	679	m_atapi_regs[ATAPI_REG_COUNTLOW] = 0x14;
	680	m_atapi_regs[ATAPI_REG_COUNTHIGH] = 0xeb;
	681	m_atapi_data_ptr = 0;
	682	m_atapi_data_len = 0;
	683	m_atapi_cdata_wait = 0;
674	684
675		state->m_atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
676		state->m_atapi_regs[ATAPI_REG_ERRFEAT] = 1;
677		state->m_atapi_regs[ATAPI_REG_COUNTLOW] = 0x14;
678		state->m_atapi_regs[ATAPI_REG_COUNTHIGH] = 0xeb;
679		state->m_atapi_data_ptr = 0;
680		state->m_atapi_data_len = 0;
681		state->m_atapi_cdata_wait = 0;
	685	//SCSIAllocInstance( machine, &SCSIClassCr589, &m_inserted_cdrom, ":cdrom" );
682	686
683		//SCSIAllocInstance( machine, &SCSIClassCr589, &state->m_inserted_cdrom, ":cdrom" );
	687	//machine().add_notifier(MACHINE_NOTIFY_EXIT, machine_notify_delegate(FUNC(atapi_exit), &machine));
684	688
685		//machine.add_notifier(MACHINE_NOTIFY_EXIT, machine_notify_delegate(FUNC(atapi_exit), &machine));
686
687	689	}
688	690
689	691
r22523	r22524
693	695	*
694	696	*************************************************************/
695	697
696		static WRITE_LINE_DEVICE_HANDLER( gammagic_pic8259_1_set_int_line )
	698	WRITE_LINE_MEMBER(gammagic_state::gammagic_pic8259_1_set_int_line)
697	699	{
698		gammagic_state *drvstate = device->machine().driver_data<gammagic_state>();
699		drvstate->m_maincpu->set_input_line( 0, state ? HOLD_LINE : CLEAR_LINE);
	700	m_maincpu->set_input_line(0, state ? HOLD_LINE : CLEAR_LINE);
700	701	}
701	702
702		static READ8_DEVICE_HANDLER( get_slave_ack )
	703	READ8_MEMBER(gammagic_state::get_slave_ack)
703	704	{
704		gammagic_state *state = device->machine().driver_data<gammagic_state>();
705	705	if (offset==2) {
706		return pic8259_acknowledge(state->m_pic8259_2);
	706	return pic8259_acknowledge(m_pic8259_2);
707	707	}
708	708	return 0x00;
709	709	}
710	710
711	711	static const struct pic8259_interface gammagic_pic8259_1_config =
712	712	{
713		DEVCB_LINE(gammagic_pic8259_1_set_int_line),
	713	DEVCB_DRIVER_LINE_MEMBER(gammagic_state,gammagic_pic8259_1_set_int_line),
714	714	DEVCB_LINE_VCC,
715		DEVCB_HANDLER(get_slave_ack)
	715	DEVCB_DRIVER_MEMBER(gammagic_state,get_slave_ack)
716	716	};
717	717
718	718	static const struct pic8259_interface gammagic_pic8259_2_config =
r22523	r22524
768	768	MCFG_CPU_ADD("maincpu", PENTIUM, 133000000) // Intel Pentium 133
769	769	MCFG_CPU_PROGRAM_MAP(gammagic_map)
770	770	MCFG_CPU_IO_MAP(gammagic_io)
771		MCFG_MACHINE_START(gammagic)
772		MCFG_MACHINE_RESET( gammagic )
773	771	MCFG_PIT8254_ADD( "pit8254", gammagic_pit8254_config )
774	772	MCFG_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, dma8237_1_config )
775	773	MCFG_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
r22523	r22524
791	789
792	790	DRIVER_INIT_MEMBER(gammagic_state,gammagic)
793	791	{
794		atapi_init(machine());
	792	atapi_init();
795	793	}
796	794
797	795	ROM_START( gammagic )

trunk/src/mame/drivers/vlc.c

r22523	r22524
174	174
175	175	UINT16* m_videoram;
176	176	tilemap_t *m_bg_tilemap;
	177	virtual void video_start();
	178	UINT32 screen_update_nevada(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	179	virtual void palette_init();
177	180
	181	DECLARE_WRITE_LINE_MEMBER(nevada_rtc_irq);
	182	DECLARE_READ16_MEMBER(io_board_r);
	183	DECLARE_WRITE16_MEMBER(io_board_w);
	184	DECLARE_WRITE16_MEMBER (io_board_x);
	185	DECLARE_READ16_MEMBER( nevada_sec_r );
	186	DECLARE_WRITE16_MEMBER( nevada_sec_w );
	187	virtual void machine_reset();
178	188
179	189	DECLARE_DRIVER_INIT(nevada);
180	190	};
r22523	r22524
245	255
246	256	/***************************************************************************/
247	257	/*
248		static WRITE16_HANDLER( nevada_videoram_w )
	258	WRITE16_MEMBER( nevada_state:nevada_videoram_w )
249	259	{
250	260	// Todo, Just for sample
251	261
252		nevada_state *state = space->machine().driver_data<nevada_state>();
253		state->m_videoram[offset] = data;
254		state->m_bg_tilemap->mark_tile_dirty(offset);
	262	m_videoram[offset] = data;
	263	m_bg_tilemap->mark_tile_dirty(offset);
255	264
256	265	}
257	266	*/
r22523	r22524
263	272
264	273	/***************************************************************************/
265	274	/*
266		static TILE_GET_INFO( get_bg_tile_info )
	275	static TILE_GET_INFO_MEMBER( nevada_state::get_bg_tile_info )
267	276	{
268	277	// Todo, Just for sample
269		nevada_state *state = machine.driver_data<nevada_state>();
270
271		int attr = state->m_colorram[tile_index];
272		int code = ((attr & 1) << 8) | state->m_videoram[tile_index];
	278	int attr = m_colorram[tile_index];
	279	int code = ((attr & 1) << 8) | m_videoram[tile_index];
273	280	int bank = (attr & 0x02) >> 1;
274	281	int color = (attr & 0x3c) >> 2;
275	282
276		SET_TILE_INFO(bank, code, color, 0);
	283	SET_TILE_INFO_MEMBER(bank, code, color, 0);
277	284
278	285	}
279	286	*/
280	287
281	288	/***************************************************************************/
282		static VIDEO_START( nevada )
	289	void nevada_state::video_start()
283	290	{
284	291	// todo
285	292	/*
286		nevada_state *state = machine.driver_data<nevada_state>();
287		state->m_bg_tilemap = tilemap_create(machine, get_bg_tile_info, tilemap_scan_rows, 8, 8, 32, 32);
	293	m_bg_tilemap = tilemap_create(machine(), get_bg_tile_info, tilemap_scan_rows, 8, 8, 32, 32);
288	294	*/
289	295	}
290	296
291	297	/***************************************************************************/
292		static SCREEN_UPDATE_IND16( nevada )
	298	UINT32 nevada_state::screen_update_nevada(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
293	299	{
294	300	// Todo
295	301	/*
296		nevada_state *state = screen.machine().driver_data<nevada_state>();
297		state->m_bg_tilemap->draw(bitmap, cliprect, 0, 0);
	302	m_bg_tilemap->draw(bitmap, cliprect, 0, 0);
298	303	*/
299	304	return 0;
300	305	}
301	306
302	307	/***************************************************************************/
303		static PALETTE_INIT( nevada )
	308	void nevada_state::palette_init()
304	309	{
305	310	// Palette init
306	311	}
r22523	r22524
449	454	/***************************************************************************/
450	455	/*********************    RTC SECTION       ********************************/
451	456	/***************************************************************************/
452		static WRITE_LINE_DEVICE_HANDLER(nevada_rtc_irq)
	457	WRITE_LINE_MEMBER(nevada_state::nevada_rtc_irq)
453	458	{
454		nevada_state *drvstate = device->machine().driver_data<nevada_state>();
455		drvstate->m_maincpu->set_input_line(INPUT_LINE_IRQ1, HOLD_LINE);  // rtc interrupt on INT1
	459	m_maincpu->set_input_line(INPUT_LINE_IRQ1, HOLD_LINE);  // rtc interrupt on INT1
456	460	}
457	461
458	462	/***************************************************************************/
459	463	static MSM6242_INTERFACE( nevada_rtc_intf )
460	464	{
461		DEVCB_LINE(nevada_rtc_irq)
	465	DEVCB_DRIVER_LINE_MEMBER(nevada_state,nevada_rtc_irq)
462	466	};
463	467
464	468	/***************************************************************************/
r22523	r22524
477	481	};
478	482
479	483	/***************************************************************************/
480		static READ16_HANDLER(io_board_r)
	484	READ16_MEMBER(nevada_state::io_board_r)
481	485	{
482	486	// IO board Serial communication 0xA00000
483	487	return 1;
484	488	}
485	489	/***************************************************************************/
486		static WRITE16_HANDLER(io_board_w)
	490	WRITE16_MEMBER(nevada_state::io_board_w)
487	491	{
488	492	// IO board Serial communication 0xA00000 on bit0
489	493	}
490	494	/***************************************************************************/
491		static WRITE16_HANDLER (io_board_x)
	495	WRITE16_MEMBER(nevada_state::io_board_x)
492	496	{
493	497	// IO board Serial communication 0xA80000  on bit15
494	498	}
495	499
496	500	/***************************************************************************/
497		static READ16_HANDLER( nevada_sec_r )
	501	READ16_MEMBER(nevada_state::nevada_sec_r )
498	502	{
499		nevada_state *state = space.machine().driver_data<nevada_state>();
500	503	//  D3..D0 = DOOR OPEN or Track STATE of PAL35
501	504	UINT16 res;
502	505	/* UPPER byte is use for input in PAL35 */
503	506	// 74LS173 $bits Register used LOWER bits D3..D0 for PAL35 state and DOOR LOGIC SWITCH
504		res = pal35[state->m_datA40000 >> 8];
	507	res = pal35[m_datA40000 >> 8];
505	508	res = res << 8;
506		res = res | (state->m_datA40000 & 0x00FF);
	509	res = res | (m_datA40000 & 0x00FF);
507	510
508	511	return res;
509	512	}
510	513	/***************************************************************************/
511		static WRITE16_HANDLER( nevada_sec_w )
	514	WRITE16_MEMBER(nevada_state::nevada_sec_w )
512	515	{
513		nevada_state *state = space.machine().driver_data<nevada_state>();
514	516	// 74LS173 $bits Register used LOWER bits D3..D0 for DOOR LOGIC SWITCH
515		state->m_datA40000 = data | 0x00f0;     // since D7..D4 are not used and are connected to PULLUP
	517	m_datA40000 = data | 0x00f0;     // since D7..D4 are not used and are connected to PULLUP
516	518	//  popmessage("WRITE %04x %04x  ",datA40000,data);
517	519	}
518	520
r22523	r22524
602	604	AM_RANGE(0x00010000, 0x00021fff) AM_RAM AM_SHARE("backup")
603	605	AM_RANGE(0x00900000, 0x00900001) AM_DEVWRITE8("crtc",mc6845_device, address_w,0x00ff )
604	606	AM_RANGE(0x00908000, 0x00908001) AM_DEVWRITE8("crtc",mc6845_device,register_w,0x00ff )
605		AM_RANGE(0x00a00000, 0x00a00001) AM_READWRITE_LEGACY (io_board_r,io_board_w)
606		AM_RANGE(0x00a08000, 0x00a08001) AM_WRITE_LEGACY(io_board_x)
	607	AM_RANGE(0x00a00000, 0x00a00001) AM_READWRITE(io_board_r,io_board_w)
	608	AM_RANGE(0x00a08000, 0x00a08001) AM_WRITE(io_board_x)
607	609	AM_RANGE(0x00a10000, 0x00a10001) AM_WRITE(watchdog_reset16_w )
608	610	AM_RANGE(0x00a20000, 0x00a20001) AM_DEVWRITE8_LEGACY("aysnd", ay8910_address_w,0x00ff )
609	611	AM_RANGE(0x00a28000, 0x00a28001) AM_DEVWRITE8_LEGACY("aysnd", ay8910_data_w   ,0x00ff )
610	612	AM_RANGE(0x00a30000, 0x00A300ff) AM_DEVREADWRITE8("rtc",msm6242_device, read, write, 0x00ff)
611		AM_RANGE(0x00a40000, 0x00A40001) AM_READWRITE_LEGACY( nevada_sec_r, nevada_sec_w)
	613	AM_RANGE(0x00a40000, 0x00A40001) AM_READWRITE( nevada_sec_r, nevada_sec_w)
612	614	//AM_RANGE(0x00b00000, 0x00b01fff) AM_RAM_WRITE(nevada_videoram_w) AM_BASE_MEMBER(nevada_state, m_videoram)
613	615	AM_RANGE(0x00b00000, 0x00b01fff) AM_RAM // Video
614	616	AM_RANGE(0x00b10000, 0x00b100ff) AM_DEVREADWRITE8_LEGACY( "duart40_68681", duart68681_r, duart68681_w, 0x00ff ) // Lower byte
r22523	r22524
694	696	*     Machine Reset      *
695	697	*************************/
696	698
697		static MACHINE_RESET( nevada )
	699	void nevada_state::machine_reset()
698	700	{
699		nevada_state *state = machine.driver_data<nevada_state>();
700
701		state->m_duart18_68681 = machine.device( "duart18_68681" );
702		state->m_duart39_68681 = machine.device( "duart39_68681" );
703		state->m_duart40_68681 = machine.device( "duart40_68681" );
	701	m_duart18_68681 = machine().device( "duart18_68681" );
	702	m_duart39_68681 = machine().device( "duart39_68681" );
	703	m_duart40_68681 = machine().device( "duart40_68681" );
704	704	}
705	705	/***************************************************************************/
706	706
r22523	r22524
714	714	MCFG_CPU_PROGRAM_MAP(nevada_map)
715	715	MCFG_CPU_IO_MAP(nevada_iomap)  //0x10000 0x20000
716	716
717		MCFG_MACHINE_RESET(nevada)
718		MCFG_WATCHDOG_TIME_INIT(attotime::from_msec(150))   /* 150ms Ds1232 TD to Ground */
	717	MCFG_WATCHDOG_TIME_INIT(attotime::from_msec(150))   /* 150ms Ds1232 TD to Ground */
719	718
720	719
721	720	MCFG_NVRAM_HANDLER(nevada)
r22523	r22524
726	725	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
727	726	MCFG_SCREEN_SIZE((42+1)*8, (32+1)*8)                  /* From MC6845 init, registers 00 & 04 (programmed with value-1). */
728	727	MCFG_SCREEN_VISIBLE_AREA(0*8, 31*8-1, 0*8, 31*8-1)    /* From MC6845 init, registers 01 & 06. */
729		MCFG_SCREEN_UPDATE_STATIC(nevada)
	728	MCFG_SCREEN_UPDATE_DRIVER(nevada_state, screen_update_nevada)
730	729
731	730	MCFG_GFXDECODE(nevada)
732		MCFG_PALETTE_LENGTH(256)
733		MCFG_PALETTE_INIT(nevada)
734		MCFG_VIDEO_START(nevada)
	731	MCFG_PALETTE_LENGTH(256)
735	732
736	733	MCFG_MC6845_ADD("crtc", MC6845, MC6845_CLOCK, mc6845_intf)
737	734

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