trunk/src/mess/video/s3virge.c
| r22509 | r22510 | |
|---|
| 255 | 255 | s3.cr42 = data; // bit 5 = interlace, bits 0-3 = dot clock (seems to be undocumented) |
| 256 | 256 | break; |
| 257 | 257 | case 0x43: |
| 258 | | s3.cr43 = data; |
| 258 | s3.cr43 = data; // bit 2 = bit 8 of offset register, but only if bits 4-5 of CR51 are 00h. |
| 259 | vga.crtc.offset = (vga.crtc.offset & 0x00ff) | ((data & 0x04) << 6); |
| 260 | s3_define_video_mode(); |
| 259 | 261 | break; |
| 260 | 262 | /* |
| 261 | 263 | 3d4h index 45h (R/W): CR45 Hardware Graphics Cursor Mode |
| r22509 | r22510 | |
|---|
| 360 | 362 | (801/5,928) For Hi/True color modes use the Horizontal Stretch bits |
| 361 | 363 | (3d4h index 45h bits 2 and 3). |
| 362 | 364 | */ |
| 363 | | case 0x4c: |
| 365 | case 0x4c: |
| 364 | 366 | s3.cursor_start_addr = (s3.cursor_start_addr & 0x00ff) | (data << 8); |
| 365 | 367 | break; |
| 366 | 368 | case 0x4d: |
| r22509 | r22510 | |
|---|
| 385 | 387 | vga.crtc.start_addr_latch |= ((data & 0x3) << 18); |
| 386 | 388 | svga.bank_w = (svga.bank_w & 0xcf) | ((data & 0x0c) << 2); |
| 387 | 389 | svga.bank_r = svga.bank_w; |
| 390 | if((data & 0x30) != 0x00) |
| 391 | vga.crtc.offset = (vga.crtc.offset & 0x00ff) | ((data & 0x30) << 4); |
| 392 | else |
| 393 | vga.crtc.offset = (vga.crtc.offset & 0x00ff) | ((s3.cr43 & 0x04) << 6); |
| 388 | 394 | s3_define_video_mode(); |
| 389 | 395 | break; |
| 390 | 396 | case 0x53: |
trunk/src/emu/video/pc_vga.c
| r22509 | r22510 | |
|---|
| 1430 | 1430 | recompute_params(); |
| 1431 | 1431 | break; |
| 1432 | 1432 | case 0x13: |
| 1433 | | vga.crtc.offset = data & 0xff; |
| 1433 | vga.crtc.offset &= ~0xff; |
| 1434 | vga.crtc.offset |= data & 0xff; |
| 1434 | 1435 | break; |
| 1435 | 1436 | case 0x14: |
| 1436 | 1437 | vga.crtc.dw = (data & 0x40) >> 6; |
| r22509 | r22510 | |
|---|
| 2695 | 2696 | case 0x42: // CR42 Mode Control |
| 2696 | 2697 | res = s3.cr42 & 0x0f; // bit 5 set if interlaced, leave it unset for now. |
| 2697 | 2698 | break; |
| 2699 | case 0x43: |
| 2700 | res = s3.cr43; |
| 2701 | break; |
| 2698 | 2702 | case 0x45: |
| 2699 | 2703 | res = s3.cursor_mode; |
| 2700 | 2704 | break; |
| r22509 | r22510 | |
|---|
| 2884 | 2888 | case 0x42: |
| 2885 | 2889 | s3.cr42 = data; // bit 5 = interlace, bits 0-3 = dot clock (seems to be undocumented) |
| 2886 | 2890 | break; |
| 2891 | case 0x43: |
| 2892 | s3.cr43 = data; // bit 2 = bit 8 of offset register, but only if bits 4-5 of CR51 are 00h. |
| 2893 | vga.crtc.offset = (vga.crtc.offset & 0x00ff) | ((data & 0x04) << 6); |
| 2894 | s3_define_video_mode(); |
| 2895 | break; |
| 2887 | 2896 | /* |
| 2888 | 2897 | 3d4h index 45h (R/W): CR45 Hardware Graphics Cursor Mode |
| 2889 | 2898 | bit 0 HWGC ENB. Hardware Graphics Cursor Enable. Set to enable the |
| r22509 | r22510 | |
|---|
| 3012 | 3021 | vga.crtc.start_addr_latch |= ((data & 0x3) << 18); |
| 3013 | 3022 | svga.bank_w = (svga.bank_w & 0xcf) | ((data & 0x0c) << 2); |
| 3014 | 3023 | svga.bank_r = svga.bank_w; |
| 3024 | if((data & 0x30) != 0x00) |
| 3025 | vga.crtc.offset = (vga.crtc.offset & 0x00ff) | ((data & 0x30) << 4); |
| 3026 | else |
| 3027 | vga.crtc.offset = (vga.crtc.offset & 0x00ff) | ((s3.cr43 & 0x04) << 6); |
| 3015 | 3028 | s3_define_video_mode(); |
| 3016 | 3029 | break; |
| 3017 | 3030 | case 0x53: |