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r22504 Monday 22nd April, 2013 at 13:29:58 UTC by Miodrag Milanović
rmnimbus cleanup and few smaller (nw)
[src/mess/includes]rmnimbus.h
[src/mess/machine]dgn_beta.c mbc55x.c rmnimbus.c
[src/mess/video]rmnimbus.c

trunk/src/mess/machine/mbc55x.c
r22503r22504
399399      debug_console_register_command(machine(), "mbc55x_debug", CMDFLAG_NONE, 0, 0, 1, mbc55x_debug);
400400
401401      /* set up the instruction hook */
402      machine().device(MAINCPU_TAG)->debug()->set_instruction_hook(instruction_hook);
402      m_maincpu->debug()->set_instruction_hook(instruction_hook);
403403   }
404404
405405   m_debug_machine=DEBUG_NONE;
trunk/src/mess/machine/dgn_beta.c
r22503r22504
205205
206206void dgn_beta_state::UpdateBanks(int first, int last)
207207{
208   address_space &space_0 = machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
208   address_space &space_0 = m_maincpu->space(AS_PROGRAM);
209209   address_space &space_1 = machine().device(DMACPU_TAG)->memory().space(AS_PROGRAM);
210210   int                 Page;
211211   UINT8               *readbank;
r22503r22504
645645
646646      /* CPU un-halted let it run ! */
647647      if (HALT_DMA == CLEAR_LINE)
648         machine().device(MAINCPU_TAG)->execute().yield();
648         m_maincpu->yield();
649649
650650      m_d_pia1_pa_last = data & 0x80;
651651   }
r22503r22504
677677         HALT_CPU = ASSERT_LINE;
678678
679679      LOG_HALT(("MAIN_CPU HALT=%d\n", HALT_CPU));
680      machine().device(MAINCPU_TAG)->execute().set_input_line(INPUT_LINE_HALT, HALT_CPU);
680      m_maincpu->set_input_line(INPUT_LINE_HALT, HALT_CPU);
681681
682682      m_d_pia1_pb_last = data & 0x02;
683683
r22503r22504
816816   else
817817      IRQ = CLEAR_LINE;
818818
819   machine().device(MAINCPU_TAG)->execute().set_input_line(M6809_IRQ_LINE, IRQ);
819   m_maincpu->set_input_line(M6809_IRQ_LINE, IRQ);
820820   LOG_INTS(("cpu0 IRQ : %d\n", IRQ));
821821}
822822
r22503r22504
831831   else
832832      FIRQ = CLEAR_LINE;
833833
834   machine().device(MAINCPU_TAG)->execute().set_input_line(M6809_FIRQ_LINE, FIRQ);
834   m_maincpu->set_input_line(M6809_FIRQ_LINE, FIRQ);
835835
836836   LOG_INTS(("cpu0 FIRQ : %d\n", FIRQ));
837837}
trunk/src/mess/machine/rmnimbus.c
r22503r22504
102102
103103/* Debugging */
104104
105#define DEBUG_SET(flags)    ((state->m_debug_machine & (flags))==(flags))
105#define DEBUG_SET(flags)    ((m_debug_machine & (flags))==(flags))
106#define DEBUG_SET_STATE(flags)    ((state->m_debug_machine & (flags))==(flags))
106107
107108#define DEBUG_NONE          0x0000000
108109#define DMA_BREAK           0x0000001
r22503r22504
152153/* Sound */
153154
154155
155static void drq_callback(running_machine &machine, int which);
156static void nimbus_recalculate_ints(running_machine &machine);
157
158156static void execute_debug_irq(running_machine &machine, int ref, int params, const char *param[]);
159157static void execute_debug_intmasks(running_machine &machine, int ref, int params, const char *param[]);
160158static void nimbus_debug(running_machine &machine, int ref, int params, const char *param[]);
r22503r22504
169167static void decode_dssi_f_plonk_char(device_t *device,UINT16  ds, UINT16 si, UINT8 raw_flag);
170168static void decode_dssi_f_rw_sectors(device_t *device,UINT16  ds, UINT16 si, UINT8 raw_flag);
171169
172static void nimbus_bank_memory(running_machine &machine);
173static void memory_reset(running_machine &machine);
174static void fdc_reset(running_machine &machine);
175static void set_disk_int(running_machine &machine, int state);
176static void hdc_reset(running_machine &machine);
177static void hdc_ctrl_write(running_machine &machine, UINT8 data);
178static void hdc_post_rw(running_machine &machine);
179static void hdc_drq(running_machine &machine);
180170
181static void keyboard_reset(running_machine &machine);
182171
183
184static void pc8031_reset(running_machine &machine);
185static void iou_reset(running_machine &machine);
186static void rmni_sound_reset(running_machine &machine);
187
188static void mouse_js_reset(running_machine &machine);
189
190
191
192172/*************************************
193173 *
194174 *  80186 interrupt controller
r22503r22504
260240}
261241
262242
263static void update_interrupt_state(running_machine &machine)
243void rmnimbus_state::update_interrupt_state()
264244{
265   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
266245   int new_vector = 0;
267246   int Priority;
268247   int IntNo;
269248
270249   if (LOG_INTERRUPTS)
271      logerror("update_interrupt_status: req=%04X stat=%04X serv=%04X priority_mask=%4X\n", state->m_i186.intr.request, state->m_i186.intr.status, state->m_i186.intr.in_service, state->m_i186.intr.priority_mask);
250      logerror("update_interrupt_status: req=%04X stat=%04X serv=%04X priority_mask=%4X\n", m_i186.intr.request, m_i186.intr.status, m_i186.intr.in_service, m_i186.intr.priority_mask);
272251
273252   /* loop over priorities */
274   for (Priority = 0; Priority <= state->m_i186.intr.priority_mask; Priority++)
253   for (Priority = 0; Priority <= m_i186.intr.priority_mask; Priority++)
275254   {
276255      /* note: by checking 4 bits, we also verify that the mask is off */
277      if ((state->m_i186.intr.timer & 0x0F) == Priority)
256      if ((m_i186.intr.timer & 0x0F) == Priority)
278257      {
279258         /* if we're already servicing something at this level, don't generate anything new */
280         if (state->m_i186.intr.in_service & 0x01)
259         if (m_i186.intr.in_service & 0x01)
281260            return;
282261
283262         /* if there's something pending, generate an interrupt */
284         if (state->m_i186.intr.status & 0x07)
263         if (m_i186.intr.status & 0x07)
285264         {
286            if (state->m_i186.intr.status & 1)
265            if (m_i186.intr.status & 1)
287266               new_vector = 0x08;
288            else if (state->m_i186.intr.status & 2)
267            else if (m_i186.intr.status & 2)
289268               new_vector = 0x12;
290            else if (state->m_i186.intr.status & 4)
269            else if (m_i186.intr.status & 4)
291270               new_vector = 0x13;
292271            else
293272               popmessage("Invalid timer interrupt!");
294273
295274            /* set the clear mask and generate the int */
296            state->m_i186.intr.ack_mask = 0x0001;
275            m_i186.intr.ack_mask = 0x0001;
297276            goto generate_int;
298277         }
299278      }
300279
301280      /* check DMA interrupts */
302281      for (IntNo = 0; IntNo < 2; IntNo++)
303         if ((state->m_i186.intr.dma[IntNo] & 0x0F) == Priority)
282         if ((m_i186.intr.dma[IntNo] & 0x0F) == Priority)
304283         {
305284            /* if we're already servicing something at this level, don't generate anything new */
306            if (state->m_i186.intr.in_service & (0x04 << IntNo))
285            if (m_i186.intr.in_service & (0x04 << IntNo))
307286               return;
308287
309288            /* if there's something pending, generate an interrupt */
310            if (state->m_i186.intr.request & (0x04 << IntNo))
289            if (m_i186.intr.request & (0x04 << IntNo))
311290            {
312291               new_vector = 0x0a + IntNo;
313292
314293               /* set the clear mask and generate the int */
315               state->m_i186.intr.ack_mask = 0x0004 << IntNo;
294               m_i186.intr.ack_mask = 0x0004 << IntNo;
316295               goto generate_int;
317296            }
318297         }
319298
320299      /* check external interrupts */
321300      for (IntNo = 0; IntNo < 4; IntNo++)
322         if ((state->m_i186.intr.ext[IntNo] & 0x0F) == Priority)
301         if ((m_i186.intr.ext[IntNo] & 0x0F) == Priority)
323302         {
324303            if (LOG_INTERRUPTS)
325304               logerror("Int%d priority=%d\n",IntNo,Priority);
326305
327306            /* if we're already servicing something at this level, don't generate anything new */
328            if (state->m_i186.intr.in_service & (0x10 << IntNo))
307            if (m_i186.intr.in_service & (0x10 << IntNo))
329308               return;
330309
331310            /* if there's something pending, generate an interrupt */
332            if (state->m_i186.intr.request & (0x10 << IntNo))
311            if (m_i186.intr.request & (0x10 << IntNo))
333312            {
334313               /* otherwise, generate an interrupt for this request */
335314               new_vector = 0x0c + IntNo;
336315
337316               /* set the clear mask and generate the int */
338               state->m_i186.intr.ack_mask = 0x0010 << IntNo;
317               m_i186.intr.ack_mask = 0x0010 << IntNo;
339318               goto generate_int;
340319            }
341320         }
r22503r22504
344323
345324generate_int:
346325   /* generate the appropriate interrupt */
347   state->m_i186.intr.poll_status = 0x8000 | new_vector;
348   if (!state->m_i186.intr.pending)
349      machine.device(MAINCPU_TAG)->execute().set_input_line(0, ASSERT_LINE);
350   state->m_i186.intr.pending = 1;
351   machine.scheduler().trigger(CPU_RESUME_TRIGGER);
326   m_i186.intr.poll_status = 0x8000 | new_vector;
327   if (!m_i186.intr.pending)
328      m_maincpu->set_input_line(0, ASSERT_LINE);
329   m_i186.intr.pending = 1;
330   machine().scheduler().trigger(CPU_RESUME_TRIGGER);
352331   if (LOG_OPTIMIZATION) logerror("  - trigger due to interrupt pending\n");
353   if (LOG_INTERRUPTS) logerror("(%f) **** Requesting interrupt vector %02X\n", machine.time().as_double(), new_vector);
332   if (LOG_INTERRUPTS) logerror("(%f) **** Requesting interrupt vector %02X\n", machine().time().as_double(), new_vector);
354333}
355334
356335
357static void handle_eoi(running_machine &machine,int data)
336void rmnimbus_state::handle_eoi(int data)
358337{
359   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
360338   int Priority;
361339   int IntNo;
362340   int handled=0;
r22503r22504
367345      /* turn off the appropriate in-service bit */
368346      switch (data & 0x1f)
369347      {
370         case 0x08:  state->m_i186.intr.in_service &= ~0x01; break;
371         case 0x12:  state->m_i186.intr.in_service &= ~0x01; break;
372         case 0x13:  state->m_i186.intr.in_service &= ~0x01; break;
373         case 0x0a:  state->m_i186.intr.in_service &= ~0x04; break;
374         case 0x0b:  state->m_i186.intr.in_service &= ~0x08; break;
375         case 0x0c:  state->m_i186.intr.in_service &= ~0x10; break;
376         case 0x0d:  state->m_i186.intr.in_service &= ~0x20; break;
377         case 0x0e:  state->m_i186.intr.in_service &= ~0x40; break;
378         case 0x0f:  state->m_i186.intr.in_service &= ~0x80; break;
379         default:    logerror("%05X:ERROR - 80186 EOI with unknown vector %02X\n", machine.device(MAINCPU_TAG)->safe_pc(), data & 0x1f);
348         case 0x08:  m_i186.intr.in_service &= ~0x01; break;
349         case 0x12:  m_i186.intr.in_service &= ~0x01; break;
350         case 0x13:  m_i186.intr.in_service &= ~0x01; break;
351         case 0x0a:  m_i186.intr.in_service &= ~0x04; break;
352         case 0x0b:  m_i186.intr.in_service &= ~0x08; break;
353         case 0x0c:  m_i186.intr.in_service &= ~0x10; break;
354         case 0x0d:  m_i186.intr.in_service &= ~0x20; break;
355         case 0x0e:  m_i186.intr.in_service &= ~0x40; break;
356         case 0x0f:  m_i186.intr.in_service &= ~0x80; break;
357         default:    logerror("%05X:ERROR - 80186 EOI with unknown vector %02X\n", m_maincpu->pc(), data & 0x1f);
380358      }
381      if (LOG_INTERRUPTS) logerror("(%f) **** Got EOI for vector %02X\n", machine.time().as_double(), data & 0x1f);
359      if (LOG_INTERRUPTS) logerror("(%f) **** Got EOI for vector %02X\n", machine().time().as_double(), data & 0x1f);
382360   }
383361
384362   /* non-specific case */
r22503r22504
388366      for (Priority = 0; ((Priority <= 7) && !handled); Priority++)
389367      {
390368         /* check for in-service timers */
391         if ((state->m_i186.intr.timer & 0x07) == Priority && (state->m_i186.intr.in_service & 0x01))
369         if ((m_i186.intr.timer & 0x07) == Priority && (m_i186.intr.in_service & 0x01))
392370         {
393            state->m_i186.intr.in_service &= ~0x01;
394            if (LOG_INTERRUPTS) logerror("(%f) **** Got EOI for timer\n", machine.time().as_double());
371            m_i186.intr.in_service &= ~0x01;
372            if (LOG_INTERRUPTS) logerror("(%f) **** Got EOI for timer\n", machine().time().as_double());
395373            handled=1;
396374         }
397375
398376         /* check for in-service DMA interrupts */
399377         for (IntNo = 0; ((IntNo < 2) && !handled) ; IntNo++)
400            if ((state->m_i186.intr.dma[IntNo] & 0x07) == Priority && (state->m_i186.intr.in_service & (0x04 << IntNo)))
378            if ((m_i186.intr.dma[IntNo] & 0x07) == Priority && (m_i186.intr.in_service & (0x04 << IntNo)))
401379            {
402               state->m_i186.intr.in_service &= ~(0x04 << IntNo);
403               if (LOG_INTERRUPTS) logerror("(%f) **** Got EOI for DMA%d\n", machine.time().as_double(), IntNo);
380               m_i186.intr.in_service &= ~(0x04 << IntNo);
381               if (LOG_INTERRUPTS) logerror("(%f) **** Got EOI for DMA%d\n", machine().time().as_double(), IntNo);
404382               handled=1;
405383            }
406384
407385         /* check external interrupts */
408386         for (IntNo = 0; ((IntNo < 4) && !handled) ; IntNo++)
409            if ((state->m_i186.intr.ext[IntNo] & 0x07) == Priority && (state->m_i186.intr.in_service & (0x10 << IntNo)))
387            if ((m_i186.intr.ext[IntNo] & 0x07) == Priority && (m_i186.intr.in_service & (0x10 << IntNo)))
410388            {
411               state->m_i186.intr.in_service &= ~(0x10 << IntNo);
412               if (LOG_INTERRUPTS) logerror("(%f) **** Got EOI for INT%d\n", machine.time().as_double(), IntNo);
389               m_i186.intr.in_service &= ~(0x10 << IntNo);
390               if (LOG_INTERRUPTS) logerror("(%f) **** Got EOI for INT%d\n", machine().time().as_double(), IntNo);
413391               handled=1;
414392            }
415393      }
416394   }
417   nimbus_recalculate_ints(machine);
395   nimbus_recalculate_ints();
418396}
419397
420398/* Trigger an external interupt, optionally supplying the vector to take */
421static void external_int(running_machine &machine, UINT16 intno, UINT8 vector)
399void rmnimbus_state::external_int(UINT16 intno, UINT8 vector)
422400{
423   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
424401   if (LOG_INTERRUPTS_EXT) logerror("generating external int %02X, vector %02X\n",intno,vector);
425402
426403   // Only 4 external ints
r22503r22504
434411   // int 0 & int 1
435412   if (intno<2)
436413   {
437      if(state->m_i186.intr.ext[intno] & EXTINT_CTRL_CASCADE)
438         state->m_i186.intr.ext_vector[intno]=vector;
414      if(m_i186.intr.ext[intno] & EXTINT_CTRL_CASCADE)
415         m_i186.intr.ext_vector[intno]=vector;
439416   }
440417
441418   // Turn on the requested request bit and handle interrupt
442   state->m_i186.intr.request |= (0x010 << intno);
443   update_interrupt_state(machine);
419   m_i186.intr.request |= (0x010 << intno);
420   update_interrupt_state();
444421}
445422
446static void nimbus_recalculate_ints(running_machine &machine)
423void rmnimbus_state::nimbus_recalculate_ints()
447424{
448   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
449   if((state->m_iou_reg092 & DISK_INT_ENABLE) && state->m_nimbus_drives.int_ff)
425   if((m_iou_reg092 & DISK_INT_ENABLE) && m_nimbus_drives.int_ff)
450426   {
451      state->m_nimbus_drives.int_ff=0;
452      external_int(machine,0,EXTERNAL_INT_DISK);
427      m_nimbus_drives.int_ff=0;
428      external_int(0,EXTERNAL_INT_DISK);
453429   }
454430}
455431
r22503r22504
473449   if (t->control & 0x2000)
474450   {
475451      m_i186.intr.status |= 0x01 << which;
476      update_interrupt_state(machine());
452      update_interrupt_state();
477453      if (LOG_TIMER) logerror("  Generating timer interrupt\n");
478454   }
479455
r22503r22504
489465}
490466
491467
492static void internal_timer_sync(running_machine &machine, int which)
468void rmnimbus_state::internal_timer_sync(int which)
493469{
494   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
495   struct timer_state *t = &state->m_i186.timer[which];
470   struct timer_state *t = &m_i186.timer[which];
496471
497472   /* if we have a timing timer running, adjust the count */
498473   if (t->time_timer_active)
r22503r22504
514489}
515490
516491
517static void internal_timer_update(running_machine &machine,
518                           int which,
519                           int new_count,
520                           int new_maxA,
521                           int new_maxB,
522                           int new_control)
492void rmnimbus_state::internal_timer_update(int which,int new_count,int new_maxA,int new_maxB,int new_control)
523493{
524   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
525   struct timer_state *t = &state->m_i186.timer[which];
494   struct timer_state *t = &m_i186.timer[which];
526495   int update_int_timer = 0;
527496
528497   if (LOG_TIMER)
r22503r22504
533502   {
534503      if (t->control & 0x8000)
535504      {
536         internal_timer_sync(machine, which);
505         internal_timer_sync(which);
537506         update_int_timer = 1;
538507      }
539508      t->count = new_count;
r22503r22504
544513   {
545514      if (t->control & 0x8000)
546515      {
547         internal_timer_sync(machine, which);
516         internal_timer_sync(which);
548517         update_int_timer = 1;
549518      }
550519      t->maxA = new_maxA;
r22503r22504
559528   {
560529      if (t->control & 0x8000)
561530      {
562         internal_timer_sync(machine, which);
531         internal_timer_sync(which);
563532         update_int_timer = 1;
564533      }
565534
r22503r22504
589558      diff = new_control ^ t->control;
590559      if (diff & 0x001c)
591560         logerror("%05X:ERROR! -unsupported timer mode %04X\n",
592            machine.device(MAINCPU_TAG)->safe_pc(), new_control);
561            m_maincpu->pc(), new_control);
593562
594563      /* if we have real changes, update things */
595564      if (diff != 0)
r22503r22504
598567         if ((diff & 0x8000) && !(new_control & 0x8000))
599568         {
600569            /* compute the final count */
601            internal_timer_sync(machine, which);
570            internal_timer_sync(which);
602571
603572            /* nuke the timer and force the interrupt timer to be recomputed */
604573            t->time_timer->adjust(attotime::never, which);
r22503r22504
618587         /* if something about the interrupt timer changed, force an update */
619588         if (!(diff & 0x8000) && (diff & 0x2000))
620589         {
621            internal_timer_sync(machine, which);
590            internal_timer_sync(which);
622591            update_int_timer = 1;
623592         }
624593      }
r22503r22504
668637   {
669638      if (LOG_DMA>1) logerror("DMA%d timer callback - requesting interrupt: count = %04X, source = %04X\n", which, d->count, d->source);
670639      m_i186.intr.request |= 0x04 << which;
671      update_interrupt_state(machine());
640      update_interrupt_state();
672641   }
673642}
674643
675644
676static void update_dma_control(running_machine &machine, int which, int new_control)
645void rmnimbus_state::update_dma_control(int which, int new_control)
677646{
678   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
679   struct dma_state *d = &state->m_i186.dma[which];
647   struct dma_state *d = &m_i186.dma[which];
680648   int diff;
681649
682650   /* handle the CHG bit */
r22503r22504
688656   diff = new_control ^ d->control;
689657   if ((LOG_DMA) && (diff & 0x6811))
690658      logerror("%05X:ERROR! - unsupported DMA mode %04X\n",
691         machine.device(MAINCPU_TAG)->safe_pc(), new_control);
659         m_maincpu->pc(), new_control);
692660#if 0
693661   /* if we're going live, set a timer */
694662   if ((diff & 0x0002) && (new_control & 0x0002))
r22503r22504
717685
718686   if (LOG_DMA) logerror("Initiated DMA %d - count = %04X, source = %04X, dest = %04X\n", which, d->count, d->source, d->dest);
719687   if (DEBUG_SET(DMA_BREAK))
720      debugger_break(machine);
688      debugger_break(machine());
721689
722690   /* set the new control register */
723691   d->control = new_control;
724692}
725693
726static void drq_callback(running_machine &machine, int which)
694void rmnimbus_state::drq_callback(int which)
727695{
728   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
729   struct dma_state *dma = &state->m_i186.dma[which];
730   address_space &memory_space   = machine.device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
731   address_space &io_space       = machine.device(MAINCPU_TAG)->memory().space(AS_IO);
696   struct dma_state *dma = &m_i186.dma[which];
697   address_space &memory_space   = m_maincpu->space(AS_PROGRAM);
698   address_space &io_space       = m_maincpu->space(AS_IO);
732699
733700   UINT16  dma_word;
734701   UINT8   dma_byte;
r22503r22504
740707   if(!(dma->control & ST_STOP))
741708   {
742709      logerror("%05X:ERROR! - drq%d with dma channel stopped\n",
743      machine.device(MAINCPU_TAG)->safe_pc(), which);
710      m_maincpu->pc(), which);
744711
745712      return;
746713   }
r22503r22504
789756   if((dma->control & INTERRUPT_ON_ZERO) && (dma->count==0))
790757   {
791758      if (LOG_DMA>1) logerror("DMA%d - requesting interrupt: count = %04X, source = %04X\n", which, dma->count, dma->source);
792      state->m_i186.intr.request |= 0x04 << which;
793      update_interrupt_state(machine);
759      m_i186.intr.request |= 0x04 << which;
760      update_interrupt_state();
794761   }
795762}
796763
r22503r22504
798765/* Name: rmnimbus                                                            */
799766/* Desc: CPU - Initialize the 80186 CPU                                    */
800767/*-------------------------------------------------------------------------*/
801static void nimbus_cpu_init(running_machine &machine)
768void rmnimbus_state::nimbus_cpu_init()
802769{
803   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
804770   logerror("Machine reset\n");
805771
806772   /* create timers here so they stick around */
807   state->m_i186.timer[0].int_timer = machine.scheduler().timer_alloc(timer_expired_delegate(FUNC(rmnimbus_state::internal_timer_int),state));
808   state->m_i186.timer[1].int_timer = machine.scheduler().timer_alloc(timer_expired_delegate(FUNC(rmnimbus_state::internal_timer_int),state));
809   state->m_i186.timer[2].int_timer = machine.scheduler().timer_alloc(timer_expired_delegate(FUNC(rmnimbus_state::internal_timer_int),state));
810   state->m_i186.timer[0].time_timer = machine.scheduler().timer_alloc(FUNC_NULL);
811   state->m_i186.timer[1].time_timer = machine.scheduler().timer_alloc(FUNC_NULL);
812   state->m_i186.timer[2].time_timer = machine.scheduler().timer_alloc(FUNC_NULL);
813   state->m_i186.dma[0].finish_timer = machine.scheduler().timer_alloc(timer_expired_delegate(FUNC(rmnimbus_state::dma_timer_callback),state));
814   state->m_i186.dma[1].finish_timer = machine.scheduler().timer_alloc(timer_expired_delegate(FUNC(rmnimbus_state::dma_timer_callback),state));
773   m_i186.timer[0].int_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(rmnimbus_state::internal_timer_int),this));
774   m_i186.timer[1].int_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(rmnimbus_state::internal_timer_int),this));
775   m_i186.timer[2].int_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(rmnimbus_state::internal_timer_int),this));
776   m_i186.timer[0].time_timer = machine().scheduler().timer_alloc(FUNC_NULL);
777   m_i186.timer[1].time_timer = machine().scheduler().timer_alloc(FUNC_NULL);
778   m_i186.timer[2].time_timer = machine().scheduler().timer_alloc(FUNC_NULL);
779   m_i186.dma[0].finish_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(rmnimbus_state::dma_timer_callback),this));
780   m_i186.dma[1].finish_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(rmnimbus_state::dma_timer_callback),this));
815781}
816782
817static void nimbus_cpu_reset(running_machine &machine)
783void rmnimbus_state::nimbus_cpu_reset()
818784{
819   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
820785   /* reset the interrupt state */
821   state->m_i186.intr.priority_mask        = 0x0007;
822   state->m_i186.intr.timer            = 0x000f;
823   state->m_i186.intr.dma[0]           = 0x000f;
824   state->m_i186.intr.dma[1]           = 0x000f;
825   state->m_i186.intr.ext[0]           = 0x000f;
826   state->m_i186.intr.ext[1]           = 0x000f;
827   state->m_i186.intr.ext[2]           = 0x000f;
828   state->m_i186.intr.ext[3]           = 0x000f;
829   state->m_i186.intr.in_service       = 0x0000;
786   m_i186.intr.priority_mask        = 0x0007;
787   m_i186.intr.timer            = 0x000f;
788   m_i186.intr.dma[0]           = 0x000f;
789   m_i186.intr.dma[1]           = 0x000f;
790   m_i186.intr.ext[0]           = 0x000f;
791   m_i186.intr.ext[1]           = 0x000f;
792   m_i186.intr.ext[2]           = 0x000f;
793   m_i186.intr.ext[3]           = 0x000f;
794   m_i186.intr.in_service       = 0x0000;
830795
831796   /* External vectors by default to internal int 0/1 vectors */
832   state->m_i186.intr.ext_vector[0]        = 0x000C;
833   state->m_i186.intr.ext_vector[1]        = 0x000D;
797   m_i186.intr.ext_vector[0]        = 0x000C;
798   m_i186.intr.ext_vector[1]        = 0x000D;
834799
835   state->m_i186.intr.pending           = 0x0000;
836   state->m_i186.intr.ack_mask          = 0x0000;
837   state->m_i186.intr.request           = 0x0000;
838   state->m_i186.intr.status            = 0x0000;
839   state->m_i186.intr.poll_status       = 0x0000;
800   m_i186.intr.pending           = 0x0000;
801   m_i186.intr.ack_mask          = 0x0000;
802   m_i186.intr.request           = 0x0000;
803   m_i186.intr.status            = 0x0000;
804   m_i186.intr.poll_status       = 0x0000;
840805
841806   logerror("CPU reset done\n");
842807}
r22503r22504
854819      case 0x12:
855820         if (LOG_PORTS) logerror("%05X:read 80186 interrupt poll\n", space.device().safe_pc());
856821         if (m_i186.intr.poll_status & 0x8000)
857            int_callback(*machine().device(MAINCPU_TAG), 0);
822            int_callback(*m_maincpu, 0);
858823         return m_i186.intr.poll_status;
859824
860825      case 0x13:
r22503r22504
925890         if (LOG_PORTS) logerror("%05X:read 80186 Timer %d count\n", space.device().safe_pc(), (offset - 0x28) / 4);
926891         which = (offset - 0x28) / 4;
927892         if (!(offset & 1))
928            internal_timer_sync(machine(), which);
893            internal_timer_sync(which);
929894         return m_i186.timer[which].count;
930895
931896      case 0x29:
r22503r22504
1025990   {
1026991      case 0x11:
1027992         if (LOG_PORTS) logerror("%05X:80186 EOI = %04X\n", space.device().safe_pc(), data16);
1028         handle_eoi(machine(),0x8000);
1029         update_interrupt_state(machine());
993         handle_eoi(0x8000);
994         update_interrupt_state();
1030995         break;
1031996
1032997      case 0x12:
r22503r22504
10461011         m_i186.intr.ext[1] = (m_i186.intr.ext[1] & ~0x08) | ((data16 >> 2) & 0x08);
10471012         m_i186.intr.ext[2] = (m_i186.intr.ext[2] & ~0x08) | ((data16 >> 3) & 0x08);
10481013         m_i186.intr.ext[3] = (m_i186.intr.ext[3] & ~0x08) | ((data16 >> 4) & 0x08);
1049         update_interrupt_state(machine());
1014         update_interrupt_state();
10501015         break;
10511016
10521017      case 0x15:
10531018         if (LOG_PORTS) logerror("%05X:80186 interrupt priority mask = %04X\n", space.device().safe_pc(), data16);
10541019         m_i186.intr.priority_mask = data16 & 0x0007;
1055         update_interrupt_state(machine());
1020         update_interrupt_state();
10561021         break;
10571022
10581023      case 0x16:
10591024         if (LOG_PORTS) logerror("%05X:80186 interrupt in-service = %04X\n", space.device().safe_pc(), data16);
10601025         m_i186.intr.in_service = data16 & 0x00ff;
1061         update_interrupt_state(machine());
1026         update_interrupt_state();
10621027         break;
10631028
10641029      case 0x17:
10651030         if (LOG_PORTS) logerror("%05X:80186 interrupt request = %04X\n", space.device().safe_pc(), data16);
10661031         m_i186.intr.request = (m_i186.intr.request & ~0x00c0) | (data16 & 0x00c0);
1067         update_interrupt_state(machine());
1032         update_interrupt_state();
10681033         break;
10691034
10701035      case 0x18:
10711036         if (LOG_PORTS) logerror("%05X:WARNING - wrote to 80186 interrupt status = %04X\n", space.device().safe_pc(), data16);
10721037         m_i186.intr.status = (m_i186.intr.status & ~0x8007) | (data16 & 0x8007);
1073         update_interrupt_state(machine());
1038         update_interrupt_state();
10741039         break;
10751040
10761041      case 0x19:
r22503r22504
11131078      case 0x30:
11141079         if (LOG_PORTS) logerror("%05X:80186 Timer %d count = %04X\n", space.device().safe_pc(), (offset - 0x28) / 4, data16);
11151080         which = (offset - 0x28) / 4;
1116         internal_timer_update(machine(),which, data16, -1, -1, -1);
1081         internal_timer_update(which, data16, -1, -1, -1);
11171082         break;
11181083
11191084      case 0x29:
r22503r22504
11211086      case 0x31:
11221087         if (LOG_PORTS) logerror("%05X:80186 Timer %d max A = %04X\n", space.device().safe_pc(), (offset - 0x29) / 4, data16);
11231088         which = (offset - 0x29) / 4;
1124         internal_timer_update(machine(),which, -1, data16, -1, -1);
1089         internal_timer_update(which, -1, data16, -1, -1);
11251090         break;
11261091
11271092      case 0x2a:
11281093      case 0x2e:
11291094         if (LOG_PORTS) logerror("%05X:80186 Timer %d max B = %04X\n", space.device().safe_pc(), (offset - 0x2a) / 4, data16);
11301095         which = (offset - 0x2a) / 4;
1131         internal_timer_update(machine(),which, -1, -1, data16, -1);
1096         internal_timer_update(which, -1, -1, data16, -1);
11321097         break;
11331098
11341099      case 0x2b:
r22503r22504
11361101      case 0x33:
11371102         if (LOG_PORTS) logerror("%05X:80186 Timer %d control = %04X\n", space.device().safe_pc(), (offset - 0x2b) / 4, data16);
11381103         which = (offset - 0x2b) / 4;
1139         internal_timer_update(machine(),which, -1, -1, -1, data16);
1104         internal_timer_update(which, -1, -1, -1, data16);
11401105         break;
11411106
11421107      case 0x50:
r22503r22504
12081173      case 0x6d:
12091174         if (LOG_PORTS) logerror("%05X:80186 DMA%d control = %04X\n", space.device().safe_pc(), (offset - 0x65) / 8, data16);
12101175         which = (offset - 0x65) / 8;
1211         update_dma_control(machine(), which, data16);
1176         update_dma_control(which, data16);
12121177         break;
12131178
12141179      case 0x7f:
r22503r22504
12201185         temp = (data16 & 0x0fff) << 8;
12211186         if (data16 & 0x1000)
12221187         {
1223            machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM).install_read_handler(temp, temp + 0xff, read16_delegate(FUNC(rmnimbus_state::nimbus_i186_internal_port_r),this));
1224            machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM).install_write_handler(temp, temp + 0xff, write16_delegate(FUNC(rmnimbus_state::nimbus_i186_internal_port_w),this));
1188            m_maincpu->space(AS_PROGRAM).install_read_handler(temp, temp + 0xff, read16_delegate(FUNC(rmnimbus_state::nimbus_i186_internal_port_r),this));
1189            m_maincpu->space(AS_PROGRAM).install_write_handler(temp, temp + 0xff, write16_delegate(FUNC(rmnimbus_state::nimbus_i186_internal_port_w),this));
12251190         }
12261191         else
12271192         {
12281193            temp &= 0xffff;
1229            machine().device(MAINCPU_TAG)->memory().space(AS_IO).install_read_handler(temp, temp + 0xff, read16_delegate(FUNC(rmnimbus_state::nimbus_i186_internal_port_r),this));
1230            machine().device(MAINCPU_TAG)->memory().space(AS_IO).install_write_handler(temp, temp + 0xff, write16_delegate(FUNC(rmnimbus_state::nimbus_i186_internal_port_w),this));
1194            m_maincpu->space(AS_IO).install_read_handler(temp, temp + 0xff, read16_delegate(FUNC(rmnimbus_state::nimbus_i186_internal_port_r),this));
1195            m_maincpu->space(AS_IO).install_write_handler(temp, temp + 0xff, write16_delegate(FUNC(rmnimbus_state::nimbus_i186_internal_port_w),this));
12311196         }
12321197         break;
12331198
r22503r22504
12401205void rmnimbus_state::machine_reset()
12411206{
12421207   /* CPU */
1243   nimbus_cpu_reset(machine());
1244   iou_reset(machine());
1245   fdc_reset(machine());
1246   hdc_reset(machine());
1247   keyboard_reset(machine());
1248   pc8031_reset(machine());
1249   rmni_sound_reset(machine());
1250   memory_reset(machine());
1251   mouse_js_reset(machine());
1208   nimbus_cpu_reset();
1209   iou_reset();
1210   fdc_reset();
1211   hdc_reset();
1212   keyboard_reset();
1213   pc8031_reset();
1214   rmni_sound_reset();
1215   memory_reset();
1216   mouse_js_reset();
12521217}
12531218
12541219DRIVER_INIT_MEMBER(rmnimbus_state,nimbus)
r22503r22504
12581223void rmnimbus_state::machine_start()
12591224{
12601225   /* init cpu */
1261   nimbus_cpu_init(machine());
1226   nimbus_cpu_init();
12621227
12631228   m_keyboard.keyscan_timer=machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(rmnimbus_state::keyscan_callback),this));
12641229   m_nimbus_mouse.m_mouse_timer=machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(rmnimbus_state::mouse_callback),this));
r22503r22504
12711236      debug_console_register_command(machine(), "nimbus_debug", CMDFLAG_NONE, 0, 0, 1, nimbus_debug);
12721237
12731238      /* set up the instruction hook */
1274      machine().device(MAINCPU_TAG)->debug()->set_instruction_hook(instruction_hook);
1239      m_maincpu->debug()->set_instruction_hook(instruction_hook);
12751240   }
12761241
12771242   m_debug_machine=DEBUG_NONE;
r22503r22504
12791244
12801245static void execute_debug_irq(running_machine &machine, int ref, int params, const char *param[])
12811246{
1247   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
12821248   int IntNo;
12831249   int Vector;
12841250
r22503r22504
12881254      sscanf(param[1],"%X",&Vector);
12891255
12901256      debug_console_printf(machine,"triggering IRQ%d, Vector=%02X\n",IntNo,Vector);
1291      external_int(machine,IntNo,Vector);
1257      state->external_int(IntNo,Vector);
12921258   }
12931259   else
12941260   {
r22503r22504
13411307
13421308   if ((addr_ptr !=NULL) && (addr_ptr[0]==0xCD))
13431309   {
1344      if(DEBUG_SET(DECODE_BIOS) && (addr_ptr[1]==0xF0))
1310      if(DEBUG_SET_STATE(DECODE_BIOS) && (addr_ptr[1]==0xF0))
13451311      {
1346         if(DEBUG_SET(DECODE_BIOS_RAW))
1312         if(DEBUG_SET_STATE(DECODE_BIOS_RAW))
13471313            decode_subbios(&device,curpc,1);
13481314         else
13491315            decode_subbios(&device,curpc,0);
13501316      }
13511317
1352      if(DEBUG_SET(DECODE_DOS21) && (addr_ptr[1]==0x21))
1318      if(DEBUG_SET_STATE(DECODE_DOS21) && (addr_ptr[1]==0x21))
13531319         decode_dos21(&device,curpc);
13541320   }
13551321
r22503r22504
17001666   }
17011667}
17021668
1703static void *get_dssi_ptr(address_space &space, UINT16   ds, UINT16 si)
1669void *rmnimbus_state::get_dssi_ptr(address_space &space, UINT16   ds, UINT16 si)
17041670{
17051671   int             addr;
17061672
r22503r22504
17121678
17131679static void decode_dssi_generic(device_t *device,UINT16  ds, UINT16 si, UINT8 raw_flag)
17141680{
1715   address_space &space = device->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
1681   rmnimbus_state  *state = device->machine().driver_data<rmnimbus_state>();
1682   address_space &space = state->m_maincpu->space(AS_PROGRAM);
17161683   UINT16  *params;
17171684   int     count;
17181685
17191686   if(raw_flag)
17201687      return;
17211688
1722   params=(UINT16  *)get_dssi_ptr(space,ds,si);
1689   params=(UINT16  *)state->get_dssi_ptr(space,ds,si);
17231690
17241691   for(count=0; count<10; count++)
17251692      logerror("%04X ",params[count]);
r22503r22504
17301697
17311698static void decode_dssi_f_fill_area(device_t *device,UINT16  ds, UINT16 si, UINT8 raw_flag)
17321699{
1733   address_space &space = device->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
1700   rmnimbus_state  *state = device->machine().driver_data<rmnimbus_state>();
1701   address_space &space = state->m_maincpu->space(AS_PROGRAM);
17341702
17351703   UINT16          *addr_ptr;
17361704   t_area_params   *area_params;
17371705   t_nimbus_brush  *brush;
17381706   int             cocount;
17391707
1740   area_params = (t_area_params   *)get_dssi_ptr(space,ds,si);
1708   area_params = (t_area_params   *)state->get_dssi_ptr(space,ds,si);
17411709
17421710   if (!raw_flag)
17431711      OUTPUT_SEGOFS("SegBrush:OfsBrush",area_params->seg_brush,area_params->ofs_brush);
r22503r22504
17831751
17841752static void decode_dssi_f_plot_character_string(device_t *device,UINT16  ds, UINT16 si, UINT8 raw_flag)
17851753{
1786   address_space &space = device->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
1754   rmnimbus_state  *state = device->machine().driver_data<rmnimbus_state>();
1755   address_space &space = state->m_maincpu->space(AS_PROGRAM);
17871756
17881757   UINT8                   *char_ptr;
17891758   t_plot_string_params    *plot_string_params;
r22503r22504
17921761   if(raw_flag)
17931762      return;
17941763
1795   plot_string_params=(t_plot_string_params   *)get_dssi_ptr(space,ds,si);
1764   plot_string_params=(t_plot_string_params   *)state->get_dssi_ptr(space,ds,si);
17961765
17971766   OUTPUT_SEGOFS("SegFont:OfsFont",plot_string_params->seg_font,plot_string_params->ofs_font);
17981767   OUTPUT_SEGOFS("SegData:OfsData",plot_string_params->seg_data,plot_string_params->ofs_data);
r22503r22504
18121781
18131782static void decode_dssi_f_set_new_clt(device_t *device,UINT16  ds, UINT16 si, UINT8 raw_flag)
18141783{
1815   address_space &space = device->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
1784   rmnimbus_state  *state = device->machine().driver_data<rmnimbus_state>();
1785   address_space &space = state->m_maincpu->space(AS_PROGRAM);
18161786   UINT16  *new_colours;
18171787   int     colour;
1818   new_colours=(UINT16  *)get_dssi_ptr(space,ds,si);
1788   new_colours=(UINT16  *)state->get_dssi_ptr(space,ds,si);
18191789
18201790   if(raw_flag)
18211791      return;
r22503r22504
18291799
18301800static void decode_dssi_f_plonk_char(device_t *device,UINT16  ds, UINT16 si, UINT8 raw_flag)
18311801{
1832   address_space &space = device->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
1802   rmnimbus_state  *state = device->machine().driver_data<rmnimbus_state>();
1803   address_space &space = state->m_maincpu->space(AS_PROGRAM);
18331804   UINT16  *params;
1834   params=(UINT16  *)get_dssi_ptr(space,ds,si);
1805   params=(UINT16  *)state->get_dssi_ptr(space,ds,si);
18351806
18361807   if(raw_flag)
18371808      return;
r22503r22504
18431814
18441815static void decode_dssi_f_rw_sectors(device_t *device,UINT16  ds, UINT16 si, UINT8 raw_flag)
18451816{
1846   address_space &space = device->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
1817   rmnimbus_state  *state = device->machine().driver_data<rmnimbus_state>();
1818   address_space &space = state->m_maincpu->space(AS_PROGRAM);
18471819   UINT16  *params;
18481820   int     param_no;
18491821
18501822   if(raw_flag)
18511823      return;
18521824
1853   params=(UINT16  *)get_dssi_ptr(space,ds,si);
1825   params=(UINT16  *)state->get_dssi_ptr(space,ds,si);
18541826
18551827   for(param_no=0;param_no<16;param_no++)
18561828      logerror("%04X ",params[param_no]);
r22503r22504
19761948   {{ 0, 512 },    { 512, 512 },   { 1024, 512 } }
19771949};
19781950
1979static void nimbus_bank_memory(running_machine &machine)
1951void rmnimbus_state::nimbus_bank_memory()
19801952{
1981   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
1982   address_space &space = machine.device( MAINCPU_TAG)->memory().space( AS_PROGRAM );
1983   int     ramsize = machine.device<ram_device>(RAM_TAG)->size();
1953   address_space &space = machine().device( MAINCPU_TAG)->memory().space( AS_PROGRAM );
1954   int     ramsize = machine().device<ram_device>(RAM_TAG)->size();
19841955   int     ramblock = 0;
19851956   int     blockno;
19861957   char    bank[10];
1987   UINT8   *ram    = &machine.device<ram_device>(RAM_TAG)->pointer()[0];
1958   UINT8   *ram    = &machine().device<ram_device>(RAM_TAG)->pointer()[0];
19881959   UINT8   *map_blocks[3];
19891960   UINT8   *map_base;
19901961   int     map_blockno;
19911962   int     block_ofs;
19921963
1993   UINT8   ramsel = (state->m_mcu_reg080 & 0x1F);
1964   UINT8   ramsel = (m_mcu_reg080 & 0x1F);
19941965
19951966   // Invalid ramsel, return.
19961967   if((ramsel & 0x07)!=0x07)
r22503r22504
20111982   map_blocks[1]  = (ramblocks[ramblock][1].blocksize==0) ? NULL : &ram[ramblocks[ramblock][1].blockbase*1024];
20121983   map_blocks[2]  = (ramblocks[ramblock][2].blocksize==0) ? NULL : &ram[ramblocks[ramblock][2].blockbase*1024];
20131984
2014   //if(LOG_RAM) logerror("\n\nmcu_reg080=%02X, ramblock=%d, map_blocks[0]=%X, map_blocks[1]=%X, map_blocks[2]=%X\n",state->m_mcu_reg080,ramblock,(int)map_blocks[0],(int)map_blocks[1],(int)map_blocks[2]);
1985   //if(LOG_RAM) logerror("\n\nmcu_reg080=%02X, ramblock=%d, map_blocks[0]=%X, map_blocks[1]=%X, map_blocks[2]=%X\n",m_mcu_reg080,ramblock,(int)map_blocks[0],(int)map_blocks[1],(int)map_blocks[2]);
20151986
20161987   for(blockno=0;blockno<8;blockno++)
20171988   {
r22503r22504
20352006      {
20362007         map_base=(ramsel==0x07) ? map_blocks[map_blockno] : &map_blocks[map_blockno][block_ofs*1024];
20372008
2038         state->membank(bank)->set_base(map_base);
2009         membank(bank)->set_base(map_base);
20392010         space.install_readwrite_bank(memmap[blockno].start, memmap[blockno].end, bank);
20402011         //if(LOG_RAM) logerror(", base=%X\n",(int)map_base);
20412012      }
r22503r22504
20562027{
20572028   m_mcu_reg080=data;
20582029
2059   nimbus_bank_memory(machine());
2030   nimbus_bank_memory();
20602031}
20612032
2062static void memory_reset(running_machine &machine)
2033void rmnimbus_state::memory_reset()
20632034{
2064   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2065   state->m_mcu_reg080=0x07;
2066   nimbus_bank_memory(machine);
2035   m_mcu_reg080=0x07;
2036   nimbus_bank_memory();
20672037}
20682038
20692039READ16_MEMBER(rmnimbus_state::nimbus_io_r)
r22503r22504
20972067
20982068*/
20992069
2100static void keyboard_reset(running_machine &machine)
2070void rmnimbus_state::keyboard_reset()
21012071{
2102   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2103   memset(state->m_keyboard.keyrows,0xFF,NIMBUS_KEYROWS);
2072   memset(m_keyboard.keyrows,0xFF,NIMBUS_KEYROWS);
21042073
2105   // Setup timer to scan state->m_keyboard.
2106   state->m_keyboard.keyscan_timer->adjust(attotime::zero, 0, attotime::from_hz(50));
2074   // Setup timer to scan m_keyboard.
2075   m_keyboard.keyscan_timer->adjust(attotime::zero, 0, attotime::from_hz(50));
21072076}
21082077
2109static void queue_scancode(running_machine &machine, UINT8 scancode)
2078void rmnimbus_state::queue_scancode(UINT8 scancode)
21102079{
2111   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2112   state->m_keyboard.queue[state->m_keyboard.head] = scancode;
2113   state->m_keyboard.head++;
2114   state->m_keyboard.head %= ARRAY_LENGTH(state->m_keyboard.queue);
2080   m_keyboard.queue[m_keyboard.head] = scancode;
2081   m_keyboard.head++;
2082   m_keyboard.head %= ARRAY_LENGTH(m_keyboard.queue);
21152083}
21162084
2117static int keyboard_queue_read(running_machine &machine)
2085int rmnimbus_state::keyboard_queue_read()
21182086{
2119   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
21202087   int data;
2121   if (state->m_keyboard.tail == state->m_keyboard.head)
2088   if (m_keyboard.tail == m_keyboard.head)
21222089      return -1;
21232090
2124   data = state->m_keyboard.queue[state->m_keyboard.tail];
2091   data = m_keyboard.queue[m_keyboard.tail];
21252092
21262093   if (LOG_KEYBOARD)
21272094      logerror("keyboard_queue_read(): Keyboard Read 0x%02x\n",data);
21282095
2129   state->m_keyboard.tail++;
2130   state->m_keyboard.tail %= ARRAY_LENGTH(state->m_keyboard.queue);
2096   m_keyboard.tail++;
2097   m_keyboard.tail %= ARRAY_LENGTH(m_keyboard.queue);
21312098   return data;
21322099}
21332100
2134static void scan_keyboard(running_machine &machine)
2135
2101void rmnimbus_state::scan_keyboard()
21362102{
2137   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
21382103   UINT8   keyrow;
21392104   UINT8   row;
21402105   UINT8   bitno;
r22503r22504
21472112
21482113   for(row=0;row<NIMBUS_KEYROWS;row++)
21492114   {
2150      keyrow=machine.root_device().ioport(keynames[row])->read();
2115      keyrow=machine().root_device().ioport(keynames[row])->read();
21512116
21522117      for(mask=0x80, bitno=7;mask>0;mask=mask>>1, bitno-=1)
21532118      {
2154         if(!(keyrow & mask) && (state->m_keyboard.keyrows[row] & mask))
2119         if(!(keyrow & mask) && (m_keyboard.keyrows[row] & mask))
21552120         {
21562121            if (LOG_KEYBOARD) logerror("keypress %02X\n",(row<<3)+bitno);
2157            queue_scancode(machine, (row<<3)+bitno);
2122            queue_scancode((row<<3)+bitno);
21582123         }
21592124
2160         if((keyrow & mask) && !(state->m_keyboard.keyrows[row] & mask))
2125         if((keyrow & mask) && !(m_keyboard.keyrows[row] & mask))
21612126         {
21622127            if (LOG_KEYBOARD) logerror("keyrelease %02X\n",0x80+(row<<3)+bitno);
2163            queue_scancode(machine, 0x80+(row<<3)+bitno);
2128            queue_scancode(0x80+(row<<3)+bitno);
21642129         }
21652130      }
21662131
2167      state->m_keyboard.keyrows[row]=keyrow;
2132      m_keyboard.keyrows[row]=keyrow;
21682133   }
21692134}
21702135
21712136TIMER_CALLBACK_MEMBER(rmnimbus_state::keyscan_callback)
21722137{
2173   scan_keyboard(machine());
2138   scan_keyboard();
21742139}
21752140
21762141/*
r22503r22504
21922157      m_sio_int_state=state;
21932158
21942159      if(state)
2195         external_int(machine(),0,EXTERNAL_INT_Z80SIO);
2160         external_int(0,EXTERNAL_INT_Z80SIO);
21962161   }
21972162}
21982163
r22503r22504
22132178{
22142179   if(offset==0)
22152180   {
2216      return keyboard_queue_read(machine());
2181      return keyboard_queue_read();
22172182   }
22182183   else
22192184      return -1;
r22503r22504
22212186
22222187/* Floppy disk */
22232188
2224static void fdc_reset(running_machine &machine)
2189void rmnimbus_state::fdc_reset()
22252190{
2226   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2227   device_t *fdc = machine.device(FDC_TAG);
2191   device_t *fdc = machine().device(FDC_TAG);
22282192
2229   state->m_nimbus_drives.reg400=0;
2230   state->m_nimbus_drives.reg410_in=0;
2231   state->m_nimbus_drives.reg410_out=0;
2232   state->m_nimbus_drives.int_ff=0;
2193   m_nimbus_drives.reg400=0;
2194   m_nimbus_drives.reg410_in=0;
2195   m_nimbus_drives.reg410_out=0;
2196   m_nimbus_drives.int_ff=0;
22332197   wd17xx_set_pause_time(fdc,FDC_PAUSE);
22342198}
22352199
2236static void set_disk_int(running_machine &machine, int state)
2200void rmnimbus_state::set_disk_int(int state)
22372201{
2238   rmnimbus_state *drvstate = machine.driver_data<rmnimbus_state>();
22392202   if(LOG_DISK)
22402203      logerror("nimbus_drives_intrq = %d\n",state);
22412204
2242   if(drvstate->m_iou_reg092 & DISK_INT_ENABLE)
2205   if(m_iou_reg092 & DISK_INT_ENABLE)
22432206   {
2244      drvstate->m_nimbus_drives.int_ff=state;
2207      m_nimbus_drives.int_ff=state;
22452208
22462209      if(state)
2247         external_int(machine,0,EXTERNAL_INT_DISK);
2210         external_int(0,EXTERNAL_INT_DISK);
22482211   }
22492212}
22502213
22512214WRITE_LINE_MEMBER(rmnimbus_state::nimbus_fdc_intrq_w)
22522215{
2253   set_disk_int(machine(),state);
2216   set_disk_int(state);
22542217}
22552218
22562219WRITE_LINE_MEMBER(rmnimbus_state::nimbus_fdc_drq_w)
r22503r22504
22582221   if(LOG_DISK)
22592222      logerror("nimbus_drives_drq_w(%d)\n", state);
22602223
2261   if(state && FDC_DRQ_ENABLED(this))
2262      drq_callback(machine(),1);
2224   if(state && FDC_DRQ_ENABLED())
2225      drq_callback(1);
22632226}
22642227
2265static UINT8 fdc_driveno(UINT8 drivesel)
2228UINT8 rmnimbus_state::fdc_driveno(UINT8 drivesel)
22662229{
22672230   switch (drivesel)
22682231   {
r22503r22504
22972260   device_t *fdc = machine().device(FDC_TAG);
22982261
22992262   int pc=space.device().safe_pc();
2300   rmnimbus_state *state = machine().driver_data<rmnimbus_state>();
23012263   device_t *drive = machine().device(nimbus_wd17xx_interface.floppy_drive_tags[FDC_DRIVE()]);
23022264
23032265   switch(offset*2)
r22503r22504
23262288         break;
23272289      case 0x18 :
23282290         result = m_scsibus->scsi_data_r();
2329         hdc_post_rw(machine());
2291         hdc_post_rw();
23302292      default:
23312293         break;
23322294   }
r22503r22504
23712333   if((LOG_DISK_HDD) && (((offset*2)>=0x10) || (offset==0)))
23722334      logerror("Nimbus HDCW at %05X write of %02X to %04X\n",pc,data,(offset*2)+0x400);
23732335
2374   rmnimbus_state *state = machine().driver_data<rmnimbus_state>();
23752336   switch(offset*2)
23762337   {
23772338      case 0x00 :
r22503r22504
23842345
23852346         // if we enable hdc drq with a pending condition, act on it
23862347         if((data & HDC_DRQ_MASK) && (~reg400_old & HDC_DRQ_MASK))
2387            hdc_drq(machine());
2348            hdc_drq();
23882349
23892350         break;
23902351      case 0x08 :
r22503r22504
24002361         wd17xx_data_w(fdc, space, 0, data);
24012362         break;
24022363      case 0x10 :
2403         hdc_ctrl_write(machine(),data);
2364         hdc_ctrl_write(data);
24042365         break;
24052366
24062367      case 0x18 :
24072368         m_scsibus->scsi_data_w(data);
2408         hdc_post_rw(machine());
2369         hdc_post_rw();
24092370         break;
24102371   }
24112372}
24122373
2413static void hdc_reset(running_machine &machine)
2374void rmnimbus_state::hdc_reset()
24142375{
2415   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
24162376
2417   state->m_nimbus_drives.reg410_in=0;
2418   state->m_nimbus_drives.reg410_in |= (state->m_scsibus->scsi_req_r() ? 0 : HDC_REQ_MASK);
2419   state->m_nimbus_drives.reg410_in |= (state->m_scsibus->scsi_cd_r()  ? 0 : HDC_CD_MASK);
2420   state->m_nimbus_drives.reg410_in |= (state->m_scsibus->scsi_io_r()  ? 0 : HDC_IO_MASK);
2421   state->m_nimbus_drives.reg410_in |= (state->m_scsibus->scsi_bsy_r() ? 0 : HDC_BSY_MASK);
2422   state->m_nimbus_drives.reg410_in |= (state->m_scsibus->scsi_msg_r() ? 0 : HDC_MSG_MASK);
2377   m_nimbus_drives.reg410_in=0;
2378   m_nimbus_drives.reg410_in |= (m_scsibus->scsi_req_r() ? 0 : HDC_REQ_MASK);
2379   m_nimbus_drives.reg410_in |= (m_scsibus->scsi_cd_r()  ? 0 : HDC_CD_MASK);
2380   m_nimbus_drives.reg410_in |= (m_scsibus->scsi_io_r()  ? 0 : HDC_IO_MASK);
2381   m_nimbus_drives.reg410_in |= (m_scsibus->scsi_bsy_r() ? 0 : HDC_BSY_MASK);
2382   m_nimbus_drives.reg410_in |= (m_scsibus->scsi_msg_r() ? 0 : HDC_MSG_MASK);
24232383
2424   state->m_nimbus_drives.drq_ff=0;
2384   m_nimbus_drives.drq_ff=0;
24252385}
24262386
2427static void hdc_ctrl_write(running_machine &machine, UINT8 data)
2387void rmnimbus_state::hdc_ctrl_write(UINT8 data)
24282388{
2429   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
24302389
24312390   // If we enable the HDC interupt, and an interrupt is pending, go deal with it.
2432   if(((data & HDC_IRQ_MASK) && (~state->m_nimbus_drives.reg410_out & HDC_IRQ_MASK)) &&
2433      ((~state->m_nimbus_drives.reg410_in & HDC_INT_TRIGGER)==HDC_INT_TRIGGER))
2434      set_disk_int(machine,1);
2391   if(((data & HDC_IRQ_MASK) && (~m_nimbus_drives.reg410_out & HDC_IRQ_MASK)) &&
2392      ((~m_nimbus_drives.reg410_in & HDC_INT_TRIGGER)==HDC_INT_TRIGGER))
2393      set_disk_int(1);
24352394
2436   state->m_nimbus_drives.reg410_out=data;
2395   m_nimbus_drives.reg410_out=data;
24372396
2438   state->m_scsibus->scsi_rst_w((data & HDC_RESET_MASK) ? 1 : 0);
2439   state->m_scsibus->scsi_sel_w((data & HDC_SEL_MASK) ? 1 : 0);
2397   m_scsibus->scsi_rst_w((data & HDC_RESET_MASK) ? 1 : 0);
2398   m_scsibus->scsi_sel_w((data & HDC_SEL_MASK) ? 1 : 0);
24402399}
24412400
2442static void hdc_post_rw(running_machine &machine)
2401void rmnimbus_state::hdc_post_rw()
24432402{
2444   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
24452403
2446   if((state->m_nimbus_drives.reg410_in & HDC_REQ_MASK)==0)
2447      state->m_scsibus->scsi_ack_w(1);
2404   if((m_nimbus_drives.reg410_in & HDC_REQ_MASK)==0)
2405      m_scsibus->scsi_ack_w(1);
24482406
2449   state->m_nimbus_drives.drq_ff=0;
2407   m_nimbus_drives.drq_ff=0;
24502408}
24512409
2452static void hdc_drq(running_machine &machine)
2410void rmnimbus_state::hdc_drq()
24532411{
2454   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2455   if(HDC_DRQ_ENABLED() && state->m_nimbus_drives.drq_ff)
2412   if(HDC_DRQ_ENABLED() && m_nimbus_drives.drq_ff)
24562413   {
2457      drq_callback(machine,1);
2414      drq_callback(1);
24582415   }
24592416}
24602417
r22503r22504
24962453
24972454
24982455   if(HDC_IRQ_ENABLED() && ((~m_nimbus_drives.reg410_in & HDC_INT_TRIGGER)==HDC_INT_TRIGGER))
2499      set_disk_int(machine(),1);
2456      set_disk_int(1);
25002457   else
2501      set_disk_int(machine(),0);
2458      set_disk_int(0);
25022459
25032460   switch( mask )
25042461   {
r22503r22504
25082465         if(((m_nimbus_drives.reg410_in & HDC_CD_MASK)==HDC_CD_MASK) && (last!=0))
25092466         {
25102467            m_nimbus_drives.drq_ff=1;
2511            hdc_drq(machine());
2468            hdc_drq();
25122469         }
25132470      }
25142471      else
r22503r22504
25282485
25292486/* 8031/8051 Peripheral controler 80186 side */
25302487
2531static void pc8031_reset(running_machine &machine)
2488void rmnimbus_state::pc8031_reset()
25322489{
2533   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2534   device_t *er59256 = machine.device(ER59256_TAG);
2490   device_t *er59256 = machine().device(ER59256_TAG);
25352491
25362492   logerror("peripheral controler reset\n");
25372493
2538   memset(&state->m_ipc_interface,0,sizeof(state->m_ipc_interface));
2494   memset(&m_ipc_interface,0,sizeof(m_ipc_interface));
25392495
25402496   if(!er59256_data_loaded(er59256))
25412497      er59256_preload_rom(er59256,def_config,ARRAY_LENGTH(def_config));
r22503r22504
25432499
25442500
25452501#if 0
2546static void ipc_dumpregs()
2502void rmnimbus_state::ipc_dumpregs()
25472503{
2548   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
25492504   logerror("in_data=%02X, in_status=%02X, out_data=%02X, out_status=%02X\n",
2550            state->m_ipc_interface.ipc_in, state->m_ipc_interface.status_in,
2551            state->m_ipc_interface.ipc_out, state->m_ipc_interface.status_out);
2505            m_ipc_interface.ipc_in, m_ipc_interface.status_in,
2506            m_ipc_interface.ipc_out, m_ipc_interface.status_out);
25522507
25532508}
25542509#endif
r22503r22504
26202575   }
26212576
26222577   if(((offset==2) || (offset==3)) && (m_iou_reg092 & PC8031_INT_ENABLE))
2623      external_int(machine(),0,EXTERNAL_INT_PC8031_8C);
2578      external_int(0,EXTERNAL_INT_PC8031_8C);
26242579
26252580   if(LOG_PC8031)
26262581      logerror("8031: PCIOR %04X read of %04X returns %02X\n",pc,offset,result);
r22503r22504
26542609                  m_ipc_interface.status_out  &= ~IPC_OUT_ADDR;
26552610                  m_ipc_interface.status_in   |= IPC_IN_READ_PEND;
26562611                  if(m_iou_reg092 & PC8031_INT_ENABLE)
2657                  external_int(machine(),0,EXTERNAL_INT_PC8031_8F);
2612                  external_int(0,EXTERNAL_INT_PC8031_8F);
26582613                  break;
26592614
26602615      case 0x03   : m_ipc_interface.ipc_out=data;
r22503r22504
26622617                  m_ipc_interface.status_out   |= IPC_OUT_ADDR;
26632618                  m_ipc_interface.status_in    |= IPC_IN_READ_PEND;
26642619                  if(m_iou_reg092 & PC8031_INT_ENABLE)
2665                  external_int(machine(),0,EXTERNAL_INT_PC8031_8E);
2620                  external_int(0,EXTERNAL_INT_PC8031_8E);
26662621                  break;
26672622   }
26682623}
r22503r22504
27322687   }
27332688}
27342689
2735static void iou_reset(running_machine &machine)
2690void rmnimbus_state::iou_reset()
27362691{
2737   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2738   state->m_iou_reg092=0x00;
2692   m_iou_reg092=0x00;
27392693}
27402694
27412695/*
r22503r22504
27522706
27532707*/
27542708
2755static void rmni_sound_reset(running_machine &machine)
2709void rmnimbus_state::rmni_sound_reset()
27562710{
2757   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2758   //device_t *ay8910 = machine.device(AY8910_TAG);
2759   device_t *msm5205 = machine.device(MSM5205_TAG);
2711   //device_t *ay8910 = machine().device(AY8910_TAG);
2712   device_t *msm5205 = machine().device(MSM5205_TAG);
27602713
27612714   //ay8910_reset_ym(ay8910);
27622715   msm5205_reset_w(msm5205, 1);
27632716
2764   state->m_last_playmode=MSM5205_S48_4B;
2765   msm5205_playmode_w(msm5205,state->m_last_playmode);
2717   m_last_playmode=MSM5205_S48_4B;
2718   msm5205_playmode_w(msm5205,m_last_playmode);
27662719
2767   state->m_ay8910_a=0;
2720   m_ay8910_a=0;
27682721}
27692722
27702723READ8_MEMBER(rmnimbus_state::nimbus_sound_ay8910_r)
r22503r22504
28192772{
28202773   rmnimbus_state *state = device->machine().driver_data<rmnimbus_state>();
28212774   if(state->m_iou_reg092 & MSM5205_INT_ENABLE)
2822      external_int(device->machine(),0,EXTERNAL_INT_MSM5205);
2775      state->external_int(0,EXTERNAL_INT_MSM5205);
28232776}
28242777
28252778static const int MOUSE_XYA[3][4] = { { 0, 0, 0, 0 }, { 1, 1, 0, 0 }, { 0, 1, 1, 0 } };
r22503r22504
28272780//static const int MOUSE_XYA[4] = { 1, 1, 0, 0 };
28282781//static const int MOUSE_XYB[4] = { 0, 1, 1, 0 };
28292782
2830static void mouse_js_reset(running_machine &machine)
2783void rmnimbus_state::mouse_js_reset()
28312784{
2832   rmnimbus_state *drvstate = machine.driver_data<rmnimbus_state>();
2833   mouse_joy_state *state = &drvstate->m_nimbus_mouse;
2785   mouse_joy_state *state = &m_nimbus_mouse;
28342786
28352787   state->m_mouse_px=0;
28362788   state->m_mouse_py=0;
r22503r22504
28512803{
28522804   UINT8   x = 0;
28532805   UINT8   y = 0;
2854//  int     pc=machine().device(MAINCPU_TAG)->safe_pc();
2806//  int     pc=m_maincpu->pc();
28552807
28562808   UINT8   intstate_x;
28572809   UINT8   intstate_y;
r22503r22504
29432895      {
29442896         xint=mxa ? EXTERNAL_INT_MOUSE_XR : EXTERNAL_INT_MOUSE_XL;
29452897
2946         external_int(machine(),0,xint);
2898         external_int(0,xint);
29472899
29482900//            logerror("Xint:%02X, mxb=%02X\n",xint,mxb);
29492901      }
r22503r22504
29532905      {
29542906         yint=myb ? EXTERNAL_INT_MOUSE_YU : EXTERNAL_INT_MOUSE_YD;
29552907
2956         external_int(machine(),0,yint);
2908         external_int(0,yint);
29572909//            logerror("Yint:%02X, myb=%02X\n",yint,myb);
29582910      }
29592911   }
r22503r22504
29962948
29972949   */
29982950   UINT8 result;
2999   //int pc=machine().device(MAINCPU_TAG)->safe_pc();
2951   //int pc=m_maincpu->_pc();
30002952   mouse_joy_state *state = &m_nimbus_mouse;
30012953
30022954   if (ioport("config")->read() & 0x01)
r22503r22504
30412993WRITE_LINE_MEMBER(rmnimbus_state::nimbus_via_irq_w)
30422994{
30432995   if(state)
3044      external_int(machine(),VIA_INT,0x00);
2996      external_int(VIA_INT,0x00);
30452997}
30462998
30472999const via6522_interface nimbus_via =
trunk/src/mess/video/rmnimbus.c
r22503r22504
5858#define reg02C          0x16
5959#define reg02E          0x17
6060
61#define FG_COLOUR       (state->m_vidregs[reg024]&0x0F)
62#define BG_COLOUR       ((state->m_vidregs[reg024]&0xF0)>>4)
61#define FG_COLOUR       (m_vidregs[reg024]&0x0F)
62#define BG_COLOUR       ((m_vidregs[reg024]&0xF0)>>4)
6363
64#define IS_80COL        (state->m_vidregs[reg026]&MASK_4080)
65#define IS_XOR          (state->m_vidregs[reg022]&XOR_MASK)
64#define IS_80COL        (m_vidregs[reg026]&MASK_4080)
65#define IS_XOR          (m_vidregs[reg022]&XOR_MASK)
6666
6767
6868
r22503r22504
7171#define DEBUG_DB    0x02
7272#define DEBUG_PIXEL 0x04
7373
74#define DEBUG_SET(flags)    ((state->m_debug_video & (flags))==(flags))
74#define DEBUG_SET(flags)    ((m_debug_video & (flags))==(flags))
7575
76static UINT8 get_pixel(rmnimbus_state *state, UINT16 x, UINT16 y);
77static UINT16 read_pixel_line(rmnimbus_state *state, UINT16 x, UINT16 y, UINT8 width);
78static UINT16 read_pixel_data(rmnimbus_state *state, UINT16 x, UINT16 y);
79static UINT16 read_reg_00A(rmnimbus_state *state);
80
81static void set_pixel(rmnimbus_state *state, UINT16 x, UINT16 y, UINT8 colour);
82static void write_pixel_line(rmnimbus_state *state, UINT16 x, UINT16 y, UINT16    data, UINT8 width);
83static void write_pixel_data(rmnimbus_state *state, UINT16 x, UINT16 y, UINT16    data);
84static void move_pixel_line(rmnimbus_state *state, UINT16 x, UINT16 y, UINT16    data, UINT8 width);
85static void write_reg_004(rmnimbus_state *state);
86static void write_reg_006(rmnimbus_state *state);
87static void write_reg_010(rmnimbus_state *state);
88static void write_reg_012(rmnimbus_state *state);
89static void write_reg_014(rmnimbus_state *state);
90static void write_reg_016(rmnimbus_state *state);
91static void write_reg_01A(rmnimbus_state *state);
92static void write_reg_01C(rmnimbus_state *state);
93static void write_reg_01E(rmnimbus_state *state);
94static void write_reg_026(rmnimbus_state *state);
95static void change_palette(running_machine &machine, UINT8 bank, UINT16 colours, UINT8 regno);
96
9776static void video_debug(running_machine &machine, int ref, int params, const char *param[]);
9877static void video_regdump(running_machine &machine, int ref, int params, const char *param[]);
9978
r22503r22504
10382*/
10483
10584READ16_MEMBER(rmnimbus_state::nimbus_video_io_r)
106{
107   rmnimbus_state *state = machine().driver_data<rmnimbus_state>();
85{   
10886   int     pc=space.device().safe_pc();
10987   UINT16  result;
11088
r22503r22504
11593      case    reg004  : result=m_vidregs[reg004]; break;
11694      case    reg006  : result=m_vidregs[reg006]; break;
11795      case    reg008  : result=m_vidregs[reg008]; break;
118      case    reg00A  : result=read_reg_00A(state); break;
96      case    reg00A  : result=read_reg_00A(); break;
11997      case    reg00C  : result=m_vidregs[reg00C]; break;
12098      case    reg00E  : result=m_vidregs[reg00E]; break;
12199
r22503r22504
145123   return result;
146124}
147125
148static UINT8 get_pixel(rmnimbus_state *state, UINT16 x, UINT16 y)
126UINT8 rmnimbus_state::get_pixel(UINT16 x, UINT16 y)
149127{
150128   UINT8   result = 0;
151129
152130   if((x<SCREEN_WIDTH_PIXELS) && (y<SCREEN_HEIGHT_LINES))
153131   {
154132      if(IS_80COL)
155         result=state->m_video_mem[x][y];
133         result=m_video_mem[x][y];
156134      else
157         result=state->m_video_mem[x*2][y];
135         result=m_video_mem[x*2][y];
158136   }
159137
160138   return result;
161139}
162140
163static UINT16 read_pixel_line(rmnimbus_state *state, UINT16 x, UINT16 y, UINT8 width)
141UINT16 rmnimbus_state::read_pixel_line(UINT16 x, UINT16 y, UINT8 width)
164142{
165143   UINT16  result = 0;
166144   UINT16  mask;
r22503r22504
169147   UINT8   shifts;
170148
171149   if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
172      logerror("read_pixel_line(x=%04X, y=%04X, width=%02X, bpp=%02X, pixel_mask=%02X)\n",x,y,width,state->m_bpp,state->m_pixel_mask);
150      logerror("read_pixel_line(x=%04X, y=%04X, width=%02X, bpp=%02X, pixel_mask=%02X)\n",x,y,width,m_bpp,m_pixel_mask);
173151
174   shifts=width-state->m_bpp;
152   shifts=width-m_bpp;
175153
176   for(mask=state->m_pixel_mask, pixel_x=(x*(width/state->m_bpp)); mask>0; mask=(mask>>state->m_bpp), pixel_x++)
154   for(mask=m_pixel_mask, pixel_x=(x*(width/m_bpp)); mask>0; mask=(mask>>m_bpp), pixel_x++)
177155   {
178      colour=get_pixel(state,pixel_x,y);
156      colour=get_pixel(pixel_x,y);
179157
180      if(state->m_bpp==1)
158      if(m_bpp==1)
181159         colour=((colour==FG_COLOUR) ? 1 : 0) << shifts;
182160      else
183161         colour=colour << shifts;
184162
185163      result=(result & ~mask)  | colour;
186164
187      shifts-=state->m_bpp;
165      shifts-=m_bpp;
188166   }
189167
190168   return result;
191169}
192170
193static UINT16 read_pixel_data(rmnimbus_state *state, UINT16 x, UINT16 y)
171UINT16 rmnimbus_state::read_pixel_data(UINT16 x, UINT16 y)
194172{
195173   UINT16  result=0;
196174
197175   if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
198      logerror("read_pixel_data(x=%04X, y=%04X), reg022=%04X\n",x,y,state->m_vidregs[reg022]);
176      logerror("read_pixel_data(x=%04X, y=%04X), reg022=%04X\n",x,y,m_vidregs[reg022]);
199177
200178   if(IS_80COL)
201179   {
202      switch (state->m_vidregs[reg022] & WIDTH_MASK)
180      switch (m_vidregs[reg022] & WIDTH_MASK)
203181      {
204182         case 0x00   : break;
205183
r22503r22504
213191
214192         case 0x05   : break;
215193
216         case 0x06   : state->m_bpp=2; state->m_pixel_mask=0xC000;
217                     result=read_pixel_line(state,x,y,16);
194         case 0x06   : m_bpp=2; m_pixel_mask=0xC000;
195                     result=read_pixel_line(x,y,16);
218196                     break;
219197
220198         case 0x07   : break;
r22503r22504
222200   }
223201   else /* 40 Col */
224202   {
225      switch (state->m_vidregs[reg022] & WIDTH_MASK)
203      switch (m_vidregs[reg022] & WIDTH_MASK)
226204      {
227205         case 0x00   : break;
228206
r22503r22504
236214
237215         case 0x05   : break;
238216
239         case 0x06   : state->m_bpp=4; state->m_pixel_mask=0xF000;
240                     result=read_pixel_line(state,x,y,16);
217         case 0x06   : m_bpp=4; m_pixel_mask=0xF000;
218                     result=read_pixel_line(x,y,16);
241219                     break;
242220
243221         case 0x07   : break;
r22503r22504
247225   return result;
248226}
249227
250static UINT16 read_reg_00A(rmnimbus_state *state)
228UINT16 rmnimbus_state::read_reg_00A()
251229{
252   return read_pixel_data(state, ++state->m_vidregs[reg002],state->m_vidregs[reg00C]);
230   return read_pixel_data(++m_vidregs[reg002],m_vidregs[reg00C]);
253231}
254232
255233
r22503r22504
264242*/
265243
266244WRITE16_MEMBER(rmnimbus_state::nimbus_video_io_w)
267{
268   rmnimbus_state *state = machine().driver_data<rmnimbus_state>();
245{   
269246   int pc=space.device().safe_pc();
270247
271248   if(offset<reg028)
r22503r22504
281258   {
282259      case    reg000  : m_vidregs[reg000]=data; break;
283260      case    reg002  : m_vidregs[reg002]=data; break;
284      case    reg004  : m_vidregs[reg004]=data; write_reg_004(state); break;
285      case    reg006  : m_vidregs[reg006]=data; write_reg_006(state); break;
261      case    reg004  : m_vidregs[reg004]=data; write_reg_004(); break;
262      case    reg006  : m_vidregs[reg006]=data; write_reg_006(); break;
286263      case    reg008  : m_vidregs[reg008]=data; break;
287264      case    reg00A  : m_vidregs[reg00A]=data; break;
288265      case    reg00C  : m_vidregs[reg00C]=data; break;
289266      case    reg00E  : m_vidregs[reg00E]=data; break;
290267
291      case    reg010  : m_vidregs[reg010]=data; write_reg_010(state); break;
292      case    reg012  : m_vidregs[reg012]=data; write_reg_012(state); break;
293      case    reg014  : m_vidregs[reg014]=data; write_reg_014(state); break;
294      case    reg016  : m_vidregs[reg016]=data; write_reg_016(state); break;
268      case    reg010  : m_vidregs[reg010]=data; write_reg_010(); break;
269      case    reg012  : m_vidregs[reg012]=data; write_reg_012(); break;
270      case    reg014  : m_vidregs[reg014]=data; write_reg_014(); break;
271      case    reg016  : m_vidregs[reg016]=data; write_reg_016(); break;
295272      case    reg018  : m_vidregs[reg018]=data; break;
296      case    reg01A  : m_vidregs[reg01A]=data; write_reg_01A(state); break;
297      case    reg01C  : m_vidregs[reg01C]=data; write_reg_01C(state);break;
298      case    reg01E  : m_vidregs[reg01E]=data; write_reg_01E(state);break;
273      case    reg01A  : m_vidregs[reg01A]=data; write_reg_01A(); break;
274      case    reg01C  : m_vidregs[reg01C]=data; write_reg_01C();break;
275      case    reg01E  : m_vidregs[reg01E]=data; write_reg_01E();break;
299276
300277      case    reg020  : m_vidregs[reg020]=data; break;
301278      case    reg022  : m_vidregs[reg022]=data; break;
302279      case    reg024  : m_vidregs[reg024]=data; break;
303      case    reg026  : m_vidregs[reg026]=data; write_reg_026(state); break;
304      case    reg028  : change_palette(machine(),0,data,reg028); break;
305      case    reg02A  : change_palette(machine(),1,data,reg02A); break;
306      case    reg02C  : change_palette(machine(),2,data,reg02C); break;
307      case    reg02E  : change_palette(machine(),3,data,reg02E); break;
280      case    reg026  : m_vidregs[reg026]=data; write_reg_026(); break;
281      case    reg028  : change_palette(0,data,reg028); break;
282      case    reg02A  : change_palette(1,data,reg02A); break;
283      case    reg02C  : change_palette(2,data,reg02C); break;
284      case    reg02E  : change_palette(3,data,reg02E); break;
308285
309286      default         : break;
310287   }
311288}
312289
313static void set_pixel(rmnimbus_state *state, UINT16 x, UINT16 y, UINT8 colour)
290void rmnimbus_state::set_pixel(UINT16 x, UINT16 y, UINT8 colour)
314291{
315292   if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
316293      logerror("set_pixel(x=%04X, y=%04X, colour=%04X), IS_XOR=%02X\n",x,y,colour,IS_XOR);
r22503r22504
321298   if((x<SCREEN_WIDTH_PIXELS) && (y<SCREEN_HEIGHT_LINES))
322299   {
323300      if(IS_XOR)
324         state->m_video_mem[x][y]^=colour;
301         m_video_mem[x][y]^=colour;
325302      else
326         state->m_video_mem[x][y]=colour;
303         m_video_mem[x][y]=colour;
327304   }
328305}
329306
330static void set_pixel40(rmnimbus_state *state, UINT16 x, UINT16 y, UINT8 colour)
307void rmnimbus_state::set_pixel40( UINT16 x, UINT16 y, UINT8 colour)
331308{
332   set_pixel(state, (x*2),y,colour);
333   set_pixel(state, (x*2)+1,y,colour);
309   set_pixel((x*2),y,colour);
310   set_pixel((x*2)+1,y,colour);
334311}
335312
336static void write_pixel_line(rmnimbus_state *state, UINT16 x, UINT16 y, UINT16    data, UINT8 width)
313void rmnimbus_state::write_pixel_line(UINT16 x, UINT16 y, UINT16    data, UINT8 width)
337314{
338315   UINT16  mask;
339316   UINT16  pixel_x;
r22503r22504
341318   UINT8   shifts;
342319
343320   if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
344      logerror("write_pixel_line(x=%04X, y=%04X, data=%04X, width=%02X, bpp=%02X, pixel_mask=%02X)\n",x,y,data,width,state->m_bpp,state->m_pixel_mask);
321      logerror("write_pixel_line(x=%04X, y=%04X, data=%04X, width=%02X, bpp=%02X, pixel_mask=%02X)\n",x,y,data,width,m_bpp,m_pixel_mask);
345322
346   shifts=width-state->m_bpp;
323   shifts=width-m_bpp;
347324
348   for(mask=state->m_pixel_mask, pixel_x=(x*(width/state->m_bpp)); mask>0; mask=(mask>>state->m_bpp), pixel_x++)
325   for(mask=m_pixel_mask, pixel_x=(x*(width/m_bpp)); mask>0; mask=(mask>>m_bpp), pixel_x++)
349326   {
350      if(state->m_bpp==1)
327      if(m_bpp==1)
351328         colour=(data & mask) ? FG_COLOUR : BG_COLOUR;
352329      else
353330         colour=(data & mask) >> shifts;
354331
355      //logerror("write_pixel_line: data=%04X, mask=%04X, shifts=%02X, bpp=%02X colour=%02X\n",data,mask,shifts,state->m_bpp,colour);
332      //logerror("write_pixel_line: data=%04X, mask=%04X, shifts=%02X, bpp=%02X colour=%02X\n",data,mask,shifts,m_bpp,colour);
356333
357334      if(IS_80COL)
358         set_pixel(state,pixel_x,y,colour);
335         set_pixel(pixel_x,y,colour);
359336      else
360         set_pixel40(state,pixel_x,y,colour);
337         set_pixel40(pixel_x,y,colour);
361338
362      shifts-=state->m_bpp;
339      shifts-=m_bpp;
363340   }
364341}
365342
366static void move_pixel_line(rmnimbus_state *state, UINT16 x, UINT16 y, UINT16    data, UINT8 width)
343void rmnimbus_state::move_pixel_line(UINT16 x, UINT16 y, UINT16    data, UINT8 width)
367344{
368345   UINT16  pixelno;
369346   UINT16  pixelx;
r22503r22504
376353      pixelx=(x*width)+pixelno;
377354      if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
378355         logerror("pixelx=%04X\n",pixelx);
379      state->m_video_mem[pixelx][state->m_vidregs[reg020]]=state->m_video_mem[pixelx][y];
356      m_video_mem[pixelx][m_vidregs[reg020]]=m_video_mem[pixelx][y];
380357   }
381358}
382359
r22503r22504
407384    1   pixels are xor'ed onto the screen
408385*/
409386
410static void write_pixel_data(rmnimbus_state *state, UINT16 x, UINT16 y, UINT16    data)
387void rmnimbus_state::write_pixel_data(UINT16 x, UINT16 y, UINT16    data)
411388{
412389   if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
413      logerror("write_pixel_data(x=%04X, y=%04X, data=%04X), reg022=%04X\n",x,y,data,state->m_vidregs[reg022]);
390      logerror("write_pixel_data(x=%04X, y=%04X, data=%04X), reg022=%04X\n",x,y,data,m_vidregs[reg022]);
414391
415392   if(IS_80COL)
416393   {
417      switch (state->m_vidregs[reg022] & WIDTH_MASK)
394      switch (m_vidregs[reg022] & WIDTH_MASK)
418395      {
419         case 0x00   : state->m_bpp=1; state->m_pixel_mask=0x8000;
420                     write_pixel_line(state,x,y,data,16);
396         case 0x00   : m_bpp=1; m_pixel_mask=0x8000;
397                     write_pixel_line(x,y,data,16);
421398                     break;
422399
423         case 0x01   : state->m_bpp=1; state->m_pixel_mask=0x80;
424                     write_pixel_line(state,x,y,data,8);
400         case 0x01   : m_bpp=1; m_pixel_mask=0x80;
401                     write_pixel_line(x,y,data,8);
425402                     break;
426403
427         case 0x02   : state->m_bpp=1; state->m_pixel_mask=0x0080;
428                     write_pixel_line(state,x,y,data,8);
404         case 0x02   : m_bpp=1; m_pixel_mask=0x0080;
405                     write_pixel_line(x,y,data,8);
429406                     break;
430407
431         case 0x03   : state->m_bpp=1;
432                     set_pixel(state,x,y,FG_COLOUR);
408         case 0x03   : m_bpp=1;
409                     set_pixel(x,y,FG_COLOUR);
433410                     break;
434411
435         case 0x04   : state->m_bpp=2; state->m_pixel_mask=0xC0;
436                     write_pixel_line(state,x,y,((data & 0xFF) & ((data & 0xFF00)>>8)),8);
412         case 0x04   : m_bpp=2; m_pixel_mask=0xC0;
413                     write_pixel_line(x,y,((data & 0xFF) & ((data & 0xFF00)>>8)),8);
437414                     break;
438415
439         case 0x05   : move_pixel_line(state,x,y,data,16);
416         case 0x05   : move_pixel_line(x,y,data,16);
440417                     break;
441418
442         case 0x06   : state->m_bpp=2; state->m_pixel_mask=0xC000;
443                     write_pixel_line(state,x,y,data,16);
419         case 0x06   : m_bpp=2; m_pixel_mask=0xC000;
420                     write_pixel_line(x,y,data,16);
444421                     break;
445422
446         case 0x07   : state->m_bpp=1;
447                     set_pixel(state,x,y,FG_COLOUR);
423         case 0x07   : m_bpp=1;
424                     set_pixel(x,y,FG_COLOUR);
448425                     break;
449426      }
450427   }
451428   else /* 40 Col */
452429   {
453      switch (state->m_vidregs[reg022] & WIDTH_MASK)
430      switch (m_vidregs[reg022] & WIDTH_MASK)
454431      {
455         case 0x00   : state->m_bpp=1; state->m_pixel_mask=0x0080;
456                     write_pixel_line(state,x,y,data,8);
432         case 0x00   : m_bpp=1; m_pixel_mask=0x0080;
433                     write_pixel_line(x,y,data,8);
457434                     break;
458435
459         case 0x01   : state->m_bpp=2; state->m_pixel_mask=0xC0;
460                     write_pixel_line(state,x,y,data,8);
436         case 0x01   : m_bpp=2; m_pixel_mask=0xC0;
437                     write_pixel_line(x,y,data,8);
461438                     break;
462439
463         case 0x02   : state->m_bpp=1; state->m_pixel_mask=0x0080;
464                     set_pixel40(state,x,y,FG_COLOUR);
440         case 0x02   : m_bpp=1; m_pixel_mask=0x0080;
441                     set_pixel40(x,y,FG_COLOUR);
465442                     break;
466443
467         case 0x03   : state->m_bpp=1;
468                     set_pixel(state,x,y,FG_COLOUR);
444         case 0x03   : m_bpp=1;
445                     set_pixel(x,y,FG_COLOUR);
469446                     break;
470447
471         case 0x04   : state->m_bpp=4; state->m_pixel_mask=0xF0;
472                     write_pixel_line(state,x,y,((data & 0xFF) & ((data & 0xFF00)>>8)),8);
448         case 0x04   : m_bpp=4; m_pixel_mask=0xF0;
449                     write_pixel_line(x,y,((data & 0xFF) & ((data & 0xFF00)>>8)),8);
473450                     break;
474451
475         case 0x05   : move_pixel_line(state,x,y,data,16);
452         case 0x05   : move_pixel_line(x,y,data,16);
476453                     break;
477454
478         case 0x06   : state->m_bpp=4; state->m_pixel_mask=0xF000;
479                     write_pixel_line(state,x,y,data,16);
455         case 0x06   : m_bpp=4; m_pixel_mask=0xF000;
456                     write_pixel_line(x,y,data,16);
480457                     break;
481458
482         case 0x07   : state->m_bpp=1;
483                     set_pixel(state,x,y,FG_COLOUR);
459         case 0x07   : m_bpp=1;
460                     set_pixel(x,y,FG_COLOUR);
484461                     break;
485462      }
486463   }
487464}
488465
489static void write_reg_004(rmnimbus_state *state)
466void rmnimbus_state::write_reg_004()
490467{
491   state->m_vidregs[reg002]=0;
492   state->m_vidregs[reg00C]++;
468   m_vidregs[reg002]=0;
469   m_vidregs[reg00C]++;
493470}
494471
495static void write_reg_006(rmnimbus_state *state)
472void rmnimbus_state::write_reg_006()
496473{
497   state->m_vidregs[reg00C]++;
498   state->m_vidregs[reg002]=state->m_vidregs[reg006];
474   m_vidregs[reg00C]++;
475   m_vidregs[reg002]=m_vidregs[reg006];
499476}
500477
501static void write_reg_010(rmnimbus_state *state)
478void rmnimbus_state::write_reg_010()
502479{
503   write_pixel_data(state, state->m_vidregs[reg002],state->m_vidregs[reg00C],state->m_vidregs[reg010]);
480   write_pixel_data(m_vidregs[reg002],m_vidregs[reg00C],m_vidregs[reg010]);
504481}
505482
506static void write_reg_012(rmnimbus_state *state)
483void rmnimbus_state::write_reg_012()
507484{
508485   // I dunno if this is actually what is happening as the regs seem to be write only....
509486   // doing this however does seem to make some programs (worms from the welcom disk)
510487   // work correctly.
511   state->m_vidregs[reg002]=state->m_vidregs[reg012];
488   m_vidregs[reg002]=m_vidregs[reg012];
512489
513   write_pixel_data(state, state->m_vidregs[reg012],state->m_vidregs[reg00C],FG_COLOUR);
490   write_pixel_data(m_vidregs[reg012],m_vidregs[reg00C],FG_COLOUR);
514491}
515492
516static void write_reg_014(rmnimbus_state *state)
493void rmnimbus_state::write_reg_014()
517494{
518   write_pixel_data(state, state->m_vidregs[reg002],state->m_vidregs[reg00C]++,state->m_vidregs[reg014]);
495   write_pixel_data(m_vidregs[reg002],m_vidregs[reg00C]++,m_vidregs[reg014]);
519496}
520497
521static void write_reg_016(rmnimbus_state *state)
498void rmnimbus_state::write_reg_016()
522499{
523   state->m_vidregs[reg002]=state->m_vidregs[reg016];
500   m_vidregs[reg002]=m_vidregs[reg016];
524501
525   write_pixel_data(state, state->m_vidregs[reg002],state->m_vidregs[reg00C]++,FG_COLOUR);
502   write_pixel_data(m_vidregs[reg002],m_vidregs[reg00C]++,FG_COLOUR);
526503}
527504
528505
529static void write_reg_01A(rmnimbus_state *state)
506void rmnimbus_state::write_reg_01A()
530507{
531   write_pixel_data(state, ++state->m_vidregs[reg002],state->m_vidregs[reg00C],state->m_vidregs[reg01A]);
508   write_pixel_data(++m_vidregs[reg002],m_vidregs[reg00C],m_vidregs[reg01A]);
532509}
533510
534static void write_reg_01C(rmnimbus_state *state)
511void rmnimbus_state::write_reg_01C()
535512{
536513   // I dunno if this is actually what is happening as the regs seem to be write only....
537514   // doing this however does seem to make some programs (welcome from the welcom disk,
538515   // and others using the standard RM box menus) work correctly.
539   state->m_vidregs[reg00C]=state->m_vidregs[reg01C];
516   m_vidregs[reg00C]=m_vidregs[reg01C];
540517
541   write_pixel_data(state, state->m_vidregs[reg002],state->m_vidregs[reg01C],FG_COLOUR);
518   write_pixel_data(m_vidregs[reg002],m_vidregs[reg01C],FG_COLOUR);
542519}
543520
544static void write_reg_01E(rmnimbus_state *state)
521void rmnimbus_state::write_reg_01E()
545522{
546   state->m_vidregs[reg00C]=state->m_vidregs[reg01E];
523   m_vidregs[reg00C]=m_vidregs[reg01E];
547524
548   write_pixel_data(state, ++state->m_vidregs[reg002],state->m_vidregs[reg00C],FG_COLOUR);
525   write_pixel_data(++m_vidregs[reg002],m_vidregs[reg00C],FG_COLOUR);
549526}
550527
551528/*
r22503r22504
553530    bit 5 contains the 40/80 column (320/640 pixel) flag.
554531*/
555532
556static void write_reg_026(rmnimbus_state *state)
533void rmnimbus_state::write_reg_026()
557534{
558535   if(DEBUG_SET(DEBUG_TEXT))
559      logerror("reg 026 write, border_colour=%02X\n",state->m_vidregs[reg026] & 0x0F);
536      logerror("reg 026 write, border_colour=%02X\n",m_vidregs[reg026] & 0x0F);
560537}
561538
562static void change_palette(running_machine &machine, UINT8 bank, UINT16 colours, UINT8 regno)
539void rmnimbus_state::change_palette(UINT8 bank, UINT16 colours, UINT8 regno)
563540{
564   rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
565541   UINT8   colourno;
566542   UINT16  mask;
567543   UINT8   shifts;
r22503r22504
570546   UINT8   first;
571547
572548   // for the register's data has changed update it, and then update the pallette, else do nothing.
573   if(state->m_vidregs[regno]!=colours)
574      state->m_vidregs[regno]=colours;
549   if(m_vidregs[regno]!=colours)
550      m_vidregs[regno]=colours;
575551   else
576552      return;
577553
r22503r22504
586562   for(colourno=first; colourno<(first+colourmax); colourno++)
587563   {
588564      paletteidx=(colours & mask) >> shifts;
589      palette_set_color_rgb(machine, colourno, nimbus_palette[paletteidx][RED], nimbus_palette[paletteidx][GREEN], nimbus_palette[paletteidx][BLUE]);
565      palette_set_color_rgb(machine(), colourno, nimbus_palette[paletteidx][RED], nimbus_palette[paletteidx][GREEN], nimbus_palette[paletteidx][BLUE]);
590566
591567      if(DEBUG_SET(DEBUG_TEXT))
592568         logerror("set colourno[%02X](r,g,b)=(%02X,%02X,%02X), paletteidx=%02X\n",colourno, nimbus_palette[paletteidx][RED], nimbus_palette[paletteidx][GREEN], nimbus_palette[paletteidx][BLUE],paletteidx);
trunk/src/mess/includes/rmnimbus.h
r22503r22504
275275#define FDC_DRQ_MASK    0x80
276276#define FDC_DRIVE_MASK  (FDC_DRIVE0_MASK | FDC_DRIVE1_MASK | FDC_DRIVE2_MASK | FDC_DRIVE3_MASK)
277277
278#define FDC_SIDE()          ((state->m_nimbus_drives.reg400 & FDC_SIDE_MASK) >> 4)
279#define FDC_MOTOR()         ((state->m_nimbus_drives.reg400 & FDC_MOTOR_MASKO) >> 5)
280#define FDC_DRIVE()         (fdc_driveno(state->m_nimbus_drives.reg400 & FDC_DRIVE_MASK))
281#define HDC_DRQ_ENABLED()   ((state->m_nimbus_drives.reg400 & HDC_DRQ_MASK) ? 1 : 0)
282#define FDC_DRQ_ENABLED(state)   ((state->m_nimbus_drives.reg400 & FDC_DRQ_MASK) ? 1 : 0)
278#define FDC_SIDE()          ((m_nimbus_drives.reg400 & FDC_SIDE_MASK) >> 4)
279#define FDC_MOTOR()         ((m_nimbus_drives.reg400 & FDC_MOTOR_MASKO) >> 5)
280#define FDC_DRIVE()         (fdc_driveno(m_nimbus_drives.reg400 & FDC_DRIVE_MASK))
281#define HDC_DRQ_ENABLED()   ((m_nimbus_drives.reg400 & HDC_DRQ_MASK) ? 1 : 0)
282#define FDC_DRQ_ENABLED()   ((m_nimbus_drives.reg400 & FDC_DRQ_MASK) ? 1 : 0)
283283
284284/* Masks for port 0x410 read*/
285285
r22503r22504
469469   void nimbus_scsi_linechange( UINT8 mask, UINT8 state );
470470   IRQ_CALLBACK_MEMBER(int_callback);
471471   required_device<cpu_device> m_maincpu;
472   UINT8 get_pixel(UINT16 x, UINT16 y);
473   UINT16 read_pixel_line(UINT16 x, UINT16 y, UINT8 width);
474   UINT16 read_pixel_data(UINT16 x, UINT16 y);
475   UINT16 read_reg_00A();
476   void set_pixel(UINT16 x, UINT16 y, UINT8 colour);
477   void set_pixel40(UINT16 x, UINT16 y, UINT8 colour);
478   void write_pixel_line(UINT16 x, UINT16 y, UINT16    data, UINT8 width);
479   void move_pixel_line(UINT16 x, UINT16 y, UINT16    data, UINT8 width);
480   void write_pixel_data(UINT16 x, UINT16 y, UINT16    data);
481   void write_reg_004();
482   void write_reg_006();
483   void write_reg_010();
484   void write_reg_012();
485   void write_reg_014();
486   void write_reg_016();
487   void write_reg_01A();
488   void write_reg_01C();
489   void write_reg_01E();
490   void write_reg_026();
491   void change_palette(UINT8 bank, UINT16 colours, UINT8 regno);
492   void update_interrupt_state();
493   void handle_eoi(int data);
494   void external_int(UINT16 intno, UINT8 vector);
495   void nimbus_recalculate_ints();
496   void internal_timer_sync(int which);
497   void internal_timer_update(int which,int new_count,int new_maxA,int new_maxB,int new_control);
498   void update_dma_control(int which, int new_control);
499   void drq_callback(int which);
500   void nimbus_cpu_init();
501   void nimbus_cpu_reset();
502   void *get_dssi_ptr(address_space &space, UINT16   ds, UINT16 si);
503   void nimbus_bank_memory();
504   void memory_reset();
505   void keyboard_reset();
506   void queue_scancode(UINT8 scancode);
507   int keyboard_queue_read();
508   void scan_keyboard();
509   void fdc_reset();
510   void set_disk_int(int state);
511   UINT8 fdc_driveno(UINT8 drivesel);
512   void hdc_reset();
513   void hdc_ctrl_write(UINT8 data);
514   void hdc_post_rw();
515   void hdc_drq();
516   void pc8031_reset();
517   void ipc_dumpregs();
518   void iou_reset();
519   void rmni_sound_reset();
520   void mouse_js_reset();
472521};

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