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r22049 Saturday 23rd March, 2013 at 19:12:07 UTC by Angelo Salese
Added video emulation
[src/mess/drivers]a5105.c mz3500.c

trunk/src/mess/drivers/a5105.c
r22048r22049
7171   required_shared_ptr<UINT8> m_video_ram;
7272   UINT8 *m_ram_base;
7373   UINT8 *m_rom_base;
74   UINT8 *m_char_rom;
74   UINT8 *m_char_ram;
7575   UINT16 m_pcg_addr;
7676   UINT16 m_pcg_internal_addr;
7777   UINT8 m_key_mux;
r22048r22049
117117
118118      for( yi = 0; yi < lr; yi++)
119119      {
120         tile_data = state->m_char_rom[(tile*8+yi) & 0x7ff];
120         tile_data = state->m_char_ram[(tile*8+yi) & 0x7ff];
121121
122122         if(cursor_on && cursor_addr == addr+x && device->machine().primary_screen->frame_number() & 0x10)
123123            tile_data^=0xff;
r22048r22049
163163
164164WRITE8_MEMBER( a5105_state::pcg_val_w )
165165{
166   m_char_rom[m_pcg_addr | m_pcg_internal_addr] = data;
166   m_char_ram[m_pcg_addr | m_pcg_internal_addr] = data;
167167
168168   machine().gfx[0]->mark_dirty(m_pcg_addr >> 3);
169169
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528528void a5105_state::video_start()
529529{
530530   // find memory regions
531   m_char_rom = memregion("pcg")->base();
531   m_char_ram = memregion("pcg")->base();
532532}
533533
534534static UPD7220_INTERFACE( hgdc_intf )
trunk/src/mess/drivers/mz3500.c
r22048r22049
11/***************************************************************************
22
3Template for skeleton drivers
3   MZ-3500 (c) 198? Sharp
44
5   preliminary driver by Angelo Salese
6
57***************************************************************************/
68
79
810#include "emu.h"
911#include "cpu/z80/z80.h"
1012//#include "sound/ay8910.h"
13#include "video/upd7220.h"
1114
1215#define MAIN_CLOCK XTAL_8MHz
1316
r22048r22049
1720   mz3500_state(const machine_config &mconfig, device_type type, const char *tag)
1821      : driver_device(mconfig, type, tag),
1922         m_master(*this, "master"),
20         m_slave(*this, "slave")
23         m_slave(*this, "slave"),
24         m_hgdc1(*this, "upd7220_chr"),
25         m_hgdc2(*this, "upd7220_gfx"),
26         m_video_ram(*this, "video_ram")
2127   { }
2228
2329   // devices
2430   required_device<cpu_device> m_master;
2531   required_device<cpu_device> m_slave;
32   required_device<upd7220_device> m_hgdc1;
33   required_device<upd7220_device> m_hgdc2;
34   required_shared_ptr<UINT8> m_video_ram;
2635   UINT8 *m_ipl_rom;
2736   UINT8 *m_basic_rom;
2837   UINT8 *m_work_ram;
2938   UINT8 *m_shared_ram;
39   UINT8 *m_char_rom;
3040
3141   UINT8 m_ma,m_mo,m_ms,m_me2,m_me1;
42   UINT8 m_crtc[0x10];
3243
3344   DECLARE_READ8_MEMBER(mz3500_master_mem_r);
3445   DECLARE_WRITE8_MEMBER(mz3500_master_mem_w);
r22048r22049
4051   DECLARE_WRITE8_MEMBER(mz3500_shared_ram_w);
4152   DECLARE_READ8_MEMBER(mz3500_io_r);
4253   DECLARE_WRITE8_MEMBER(mz3500_io_w);
54   DECLARE_WRITE8_MEMBER(mz3500_crtc_w);
4355
4456   // screen updates
45   UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
57   UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
4658
4759protected:
4860   // driver_device overrides
r22048r22049
5769{
5870}
5971
60UINT32 mz3500_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect )
72/*
73CRTC regs
74[0]
75---- -x-- "Choice of whether attribute or cursor be put on the frame  that displayed on CRT2" (whatever that means ...)
76---- --x- CRT2 output
77---- ---x CRT1 output
78[1]
79---- -GRB CRT1 color output
80[2]
81---- -GRB CRT2 color output
82[3]
83---- -GRB background color output
84[4]
85---- --x- border color mode in effect
86---- ---x color mode
87[5]
88---- --x- width setting (0: 40 chars, 1: 80 chars)
89---- ---x data size for graphics RAM (0: 8 bits, 1: 16 bits)
90[6]
91---- -x-- "Connection of graphic GDC"
92---- --x- "Connection of the 96K bytes VRAM"
93---- ---x "Connection of a 400 raster CRT"
94[7]
95---- ---x 0: 25 lines, 1: 20 lines display
96[d]
97(mirror of [5]?)
98*/
99
100static UPD7220_DISPLAY_PIXELS( hgdc_display_pixels )
61101{
102   // ...
103}
104
105static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
106{
107   mz3500_state *state = device->machine().driver_data<mz3500_state>();
108   const rgb_t *palette = palette_entry_list_raw(bitmap.palette());
109   int x;
110   int xi,yi;
111   int tile;
112   int attr;
113   UINT8 tile_data;
114   UINT8 width80;
115   UINT8 char_size;
116   UINT8 hires;
117
118//   popmessage("%02x",state->m_crtc[6]);
119
120   width80 = (state->m_crtc[5] & 2) >> 1;
121   hires = (state->m_crtc[6] & 1);
122   char_size = (hires) ? 16 : 8;
123
124   for( x = 0; x < pitch; x++ )
125   {
126      tile = (state->m_video_ram[((addr+x)*2) & 0x1fff] & 0xff);
127      attr = (state->m_video_ram[((addr+x)*2+1) & 0x3ffff] & 0x0f);
128
129      //if(hires)
130      //   tile <<= 1;
131
132      for( yi = 0; yi < lr; yi++)
133      {
134         tile_data = state->m_char_rom[((tile*16+yi) & 0xfff) | (hires*0x1000)];
135
136         for( xi = 0; xi < 8; xi++)
137         {
138            int res_x,res_y;
139            int pen;
140
141            /* TODO: color attribute needs double check */
142
143            if(yi >= char_size)
144               pen = -1;
145            else
146            {
147               if(state->m_crtc[4] & 1)
148                  pen = (tile_data >> (7-xi)) & 1 ? (attr >> 1) : -1;
149               else
150                  pen = (tile_data >> (7-xi)) & 1 ? 7 : -1;
151            }
152
153            res_x = x * 8 + xi;
154            res_y = y * lr + yi;
155
156            if(pen != -1)
157            {
158               if(!width80)
159               {
160                  bitmap.pix32(res_y, res_x*2+0) = palette[pen];
161                  bitmap.pix32(res_y, res_x*2+1) = palette[pen];
162               }
163               else
164                  bitmap.pix32(res_y, res_x) = palette[pen];
165            }
166         }
167      }
168   }
169
170}
171
172UINT32 mz3500_state::screen_update( screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect )
173{
174   bitmap.fill(machine().pens[(m_crtc[4] & 2) ? m_crtc[3] & 7 : 0], cliprect);
175
176   /* graphics */
177   m_hgdc2->screen_update(screen, bitmap, cliprect);
178   m_hgdc1->screen_update(screen, bitmap, cliprect);
62179   return 0;
63180}
64181
182
183
184static UPD7220_INTERFACE( hgdc_1_intf )
185{
186   "screen",
187   NULL,
188   hgdc_draw_text,
189   DEVCB_NULL,
190   DEVCB_DEVICE_LINE_MEMBER("upd7220_gfx", upd7220_device, ext_sync_w),
191   DEVCB_NULL
192};
193
194static UPD7220_INTERFACE( hgdc_2_intf )
195{
196   "screen",
197   hgdc_display_pixels,
198   NULL,
199   DEVCB_NULL,
200   DEVCB_NULL,
201   DEVCB_NULL
202};
203
65204READ8_MEMBER(mz3500_state::mz3500_ipl_r)
66205{
67206   return m_ipl_rom[offset];
r22048r22049
262401   }
263402}
264403
404WRITE8_MEMBER(mz3500_state::mz3500_crtc_w)
405{
406   if(offset & 8)
407   {
408      if(offset == 0xd)
409         m_crtc[offset & 7] = data;
410      else
411         printf("CRTC register access %02x\n",offset); // probably just a mirror, but who knows ...
412   }
413   else
414      m_crtc[offset] = data;
415}
416
265417static ADDRESS_MAP_START( mz3500_master_map, AS_PROGRAM, 8, mz3500_state )
266418   AM_RANGE(0x0000, 0xffff) AM_READWRITE(mz3500_master_mem_r,mz3500_master_mem_w)
267419ADDRESS_MAP_END
r22048r22049
273425//   AM_RANGE(0xec, 0xef) irq signal from slave to master CPU
274426//   AM_RANGE(0xf4, 0xf7) MFD upd765
275427//   AM_RANGE(0xf8, 0xfb) MFD I/O port
428   AM_RANGE(0xf8, 0xf8) AM_READNOP // TODO
276429   AM_RANGE(0xfc, 0xff) AM_READWRITE(mz3500_io_r,mz3500_io_w) // memory mapper
277430ADDRESS_MAP_END
278431
r22048r22049
289442//   AM_RANGE(0x20, 0x2f) pit8253
290443//   AM_RANGE(0x30, 0x3f) i8255
291444//   AM_RANGE(0x40, 0x4f) 8-bit input port
292//   AM_RANGE(0x50, 0x5f) CRTC
293//   AM_RANGE(0x60, 0x6f) upd7220 gfx
294//   AM_RANGE(0x70, 0x7f) upd7220 chr
445   AM_RANGE(0x50, 0x5f) AM_RAM_WRITE(mz3500_crtc_w)
446   AM_RANGE(0x60, 0x61) AM_DEVREADWRITE("upd7220_gfx", upd7220_device, read, write)
447   AM_RANGE(0x70, 0x71) AM_DEVREADWRITE("upd7220_chr", upd7220_device, read, write)
295448ADDRESS_MAP_END
296449
297450static INPUT_PORTS_START( mz3500 )
r22048r22049
350503   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
351504INPUT_PORTS_END
352505
353static const gfx_layout charlayout =
506static const gfx_layout charlayout_8x8 =
354507{
355508   8,8,
356   RGN_FRAC(1,1),
509   0x100,
357510   1,
358511   { RGN_FRAC(0,1) },
359512   { 0, 1, 2, 3, 4, 5, 6, 7 },
360513   { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8 },
361   8*8
514   8*16
362515};
363516
517
518static const gfx_layout charlayout_8x16 =
519{
520   8,16,
521   0x100,
522   1,
523   { RGN_FRAC(0,1) },
524   { 0, 1, 2, 3, 4, 5, 6, 7 },
525   { STEP16(0,8) },
526   8*16
527};
528
364529static GFXDECODE_START( mz3500 )
365   GFXDECODE_ENTRY( "gfx1", 0, charlayout,     0, 1 )
530   GFXDECODE_ENTRY( "gfx1", 0x0000, charlayout_8x8,     0, 1 )
531   GFXDECODE_ENTRY( "gfx1", 0x0008, charlayout_8x8,     0, 1 )
532   GFXDECODE_ENTRY( "gfx1", 0x1000, charlayout_8x16,     0, 1 )
366533GFXDECODE_END
367534
368535
r22048r22049
370537{
371538   m_ipl_rom = memregion("ipl")->base();
372539   m_basic_rom = memregion("basic")->base();
540   m_char_rom = memregion("gfx1")->base();
373541   m_work_ram = auto_alloc_array_clear(machine(), UINT8, 0x40000);
374542   m_shared_ram = auto_alloc_array_clear(machine(), UINT8, 0x800);
375543}
r22048r22049
382550   m_mo = 0;
383551   m_me1 = 0;
384552   m_me2 = 0;
385   m_slave->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
553   //m_slave->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
386554}
387555
388556
389557void mz3500_state::palette_init()
390558{
559   int i;
560
561   for(i=0;i<8;i++)
562      palette_set_color_rgb(machine(), i,pal1bit((i >> 1) & 1),pal1bit(i >> 2),pal1bit((i >> 0) & 1));
563
391564}
392565
566static ADDRESS_MAP_START( upd7220_1_map, AS_0, 8, mz3500_state )
567   ADDRESS_MAP_GLOBAL_MASK(0x1fff)
568   AM_RANGE(0x00000, 0x1fff) AM_RAM AM_SHARE("video_ram")
569ADDRESS_MAP_END
570
571static ADDRESS_MAP_START( upd7220_2_map, AS_0, 8, mz3500_state )
572   AM_RANGE(0x00000, 0x3ffff) AM_RAM // AM_SHARE("video_ram_2")
573ADDRESS_MAP_END
574
575/* TODO: clocks */
393576static MACHINE_CONFIG_START( mz3500, mz3500_state )
394577
395578   /* basic machine hardware */
r22048r22049
401584   MCFG_CPU_PROGRAM_MAP(mz3500_slave_map)
402585   MCFG_CPU_IO_MAP(mz3500_slave_io)
403586
587   MCFG_UPD7220_ADD("upd7220_chr", MAIN_CLOCK/5, hgdc_1_intf, upd7220_1_map)
588   MCFG_UPD7220_ADD("upd7220_gfx", MAIN_CLOCK/5, hgdc_2_intf, upd7220_2_map)
589
404590   /* video hardware */
405591   MCFG_SCREEN_ADD("screen", RASTER)
406592   MCFG_SCREEN_REFRESH_RATE(60)

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