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r22042 Saturday 23rd March, 2013 at 16:24:16 UTC by Angelo Salese
Forgot main file
[src/mess/drivers]mz3500.c*

trunk/src/mess/drivers/mz3500.c
r0r22042
1/***************************************************************************
2
3Template for skeleton drivers
4
5***************************************************************************/
6
7
8#include "emu.h"
9#include "cpu/z80/z80.h"
10//#include "sound/ay8910.h"
11
12#define MAIN_CLOCK XTAL_8MHz
13
14class mz3500_state : public driver_device
15{
16public:
17   mz3500_state(const machine_config &mconfig, device_type type, const char *tag)
18      : driver_device(mconfig, type, tag),
19         m_master(*this, "master"),
20         m_slave(*this, "slave")
21   { }
22
23   // devices
24   required_device<cpu_device> m_master;
25   required_device<cpu_device> m_slave;
26   UINT8 *m_ipl_rom;
27   UINT8 *m_basic_rom;
28   UINT8 *m_work_ram;
29   UINT8 *m_shared_ram;
30
31   DECLARE_READ8_MEMBER(mz3500_master_mem_r);
32   DECLARE_WRITE8_MEMBER(mz3500_master_mem_w);
33   DECLARE_READ8_MEMBER(mz3500_ipl_r);
34   DECLARE_READ8_MEMBER(mz3500_basic_r);
35   DECLARE_READ8_MEMBER(mz3500_work_ram_r);
36   DECLARE_WRITE8_MEMBER(mz3500_work_ram_w);
37   DECLARE_READ8_MEMBER(mz3500_shared_ram_r);
38   DECLARE_WRITE8_MEMBER(mz3500_shared_ram_w);
39
40   // screen updates
41   UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
42
43protected:
44   // driver_device overrides
45   virtual void machine_start();
46   virtual void machine_reset();
47
48   virtual void video_start();
49   virtual void palette_init();
50};
51
52void mz3500_state::video_start()
53{
54}
55
56UINT32 mz3500_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect )
57{
58   return 0;
59}
60
61READ8_MEMBER(mz3500_state::mz3500_ipl_r)
62{
63   return m_ipl_rom[offset];
64}
65
66READ8_MEMBER(mz3500_state::mz3500_basic_r)
67{
68   return m_basic_rom[offset];
69}
70
71READ8_MEMBER(mz3500_state::mz3500_work_ram_r)
72{
73   return m_work_ram[offset];
74}
75
76WRITE8_MEMBER(mz3500_state::mz3500_work_ram_w)
77{
78   m_work_ram[offset] = data;
79}
80
81
82READ8_MEMBER(mz3500_state::mz3500_master_mem_r)
83{
84   if((offset & 0xe000) == 0x0000) { return mz3500_ipl_r(space,(offset & 0xfff) | 0x1000); }
85   if((offset & 0xe000) == 0x2000) { return mz3500_basic_r(space,offset & 0x1fff); }
86   if((offset & 0xe000) == 0x4000) { return mz3500_work_ram_r(space,(offset & 0x1fff) | 0x4000); }
87   if((offset & 0xe000) == 0x6000) { return mz3500_work_ram_r(space,(offset & 0x1fff) | 0x6000); }
88   if((offset & 0xe000) == 0x8000) { return mz3500_work_ram_r(space,(offset & 0x1fff) | 0x8000); }
89   if((offset & 0xe000) == 0xa000) { return mz3500_work_ram_r(space,(offset & 0x1fff) | 0xa000); }
90   if((offset & 0xe000) == 0xc000) { return mz3500_work_ram_r(space,(offset & 0x1fff) | 0xc000); }
91   if((offset & 0xe000) == 0xe000) { return mz3500_work_ram_r(space,(offset & 0x1fff) | 0xe000); }
92
93   return 0xff;
94}
95
96WRITE8_MEMBER(mz3500_state::mz3500_master_mem_w)
97{
98   if((offset & 0xe000) == 0x4000) { mz3500_work_ram_w(space,(offset & 0x1fff) | 0x4000,data); return; }
99   if((offset & 0xe000) == 0x6000) { mz3500_work_ram_w(space,(offset & 0x1fff) | 0x6000,data); return; }
100   if((offset & 0xe000) == 0x8000) { mz3500_work_ram_w(space,(offset & 0x1fff) | 0x8000,data); return; }
101   if((offset & 0xe000) == 0xa000) { mz3500_work_ram_w(space,(offset & 0x1fff) | 0xa000,data); return; }
102   if((offset & 0xe000) == 0xc000) { mz3500_work_ram_w(space,(offset & 0x1fff) | 0xc000,data); return; }
103   if((offset & 0xe000) == 0xe000) { mz3500_work_ram_w(space,(offset & 0x1fff) | 0xe000,data); return; }
104
105}
106
107READ8_MEMBER(mz3500_state::mz3500_shared_ram_r)
108{
109   return m_shared_ram[offset];
110}
111
112WRITE8_MEMBER(mz3500_state::mz3500_shared_ram_w)
113{
114   m_shared_ram[offset] = data;
115}
116
117static ADDRESS_MAP_START( mz3500_master_map, AS_PROGRAM, 8, mz3500_state )
118   AM_RANGE(0x0000, 0xffff) AM_READWRITE(mz3500_master_mem_r,mz3500_master_mem_w)
119ADDRESS_MAP_END
120
121static ADDRESS_MAP_START( mz3500_master_io, AS_IO, 8, mz3500_state )
122   ADDRESS_MAP_GLOBAL_MASK(0xff)
123ADDRESS_MAP_END
124
125static ADDRESS_MAP_START( mz3500_slave_map, AS_PROGRAM, 8, mz3500_state )
126   AM_RANGE(0x0000, 0x1fff) AM_ROM AM_REGION("ipl", 0)
127   AM_RANGE(0x2000, 0x27ff) AM_READWRITE(mz3500_shared_ram_r, mz3500_shared_ram_w)
128   AM_RANGE(0x4000, 0x5fff) AM_RAM
129ADDRESS_MAP_END
130
131static ADDRESS_MAP_START( mz3500_slave_io, AS_IO, 8, mz3500_state )
132   ADDRESS_MAP_GLOBAL_MASK(0xff)
133ADDRESS_MAP_END
134
135static INPUT_PORTS_START( mz3500 )
136   /* dummy active high structure */
137   PORT_START("SYSA")
138   PORT_DIPNAME( 0x01, 0x00, "SYSA" )
139   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
140   PORT_DIPSETTING(    0x01, DEF_STR( On ) )
141   PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) )
142   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
143   PORT_DIPSETTING(    0x02, DEF_STR( On ) )
144   PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) )
145   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
146   PORT_DIPSETTING(    0x04, DEF_STR( On ) )
147   PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
148   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
149   PORT_DIPSETTING(    0x08, DEF_STR( On ) )
150   PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) )
151   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
152   PORT_DIPSETTING(    0x10, DEF_STR( On ) )
153   PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
154   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
155   PORT_DIPSETTING(    0x20, DEF_STR( On ) )
156   PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
157   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
158   PORT_DIPSETTING(    0x40, DEF_STR( On ) )
159   PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) )
160   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
161   PORT_DIPSETTING(    0x80, DEF_STR( On ) )
162
163   /* dummy active low structure */
164   PORT_START("DSWA")
165   PORT_DIPNAME( 0x01, 0x01, "DSWA" )
166   PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
167   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
168   PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
169   PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
170   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
171   PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
172   PORT_DIPSETTING(    0x04, DEF_STR( Off ) )
173   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
174   PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
175   PORT_DIPSETTING(    0x08, DEF_STR( Off ) )
176   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
177   PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
178   PORT_DIPSETTING(    0x10, DEF_STR( Off ) )
179   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
180   PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
181   PORT_DIPSETTING(    0x20, DEF_STR( Off ) )
182   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
183   PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
184   PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
185   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
186   PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
187   PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
188   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
189INPUT_PORTS_END
190
191static const gfx_layout charlayout =
192{
193   8,8,
194   RGN_FRAC(1,1),
195   1,
196   { RGN_FRAC(0,1) },
197   { 0, 1, 2, 3, 4, 5, 6, 7 },
198   { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8 },
199   8*8
200};
201
202static GFXDECODE_START( mz3500 )
203   GFXDECODE_ENTRY( "gfx1", 0, charlayout,     0, 1 )
204GFXDECODE_END
205
206
207void mz3500_state::machine_start()
208{
209   m_ipl_rom = memregion("ipl")->base();
210   m_basic_rom = memregion("basic")->base();
211   m_work_ram = auto_alloc_array_clear(machine(), UINT8, 0x40000);
212   m_shared_ram = auto_alloc_array_clear(machine(), UINT8, 0x800);
213}
214
215void mz3500_state::machine_reset()
216{
217}
218
219
220void mz3500_state::palette_init()
221{
222}
223
224static MACHINE_CONFIG_START( mz3500, mz3500_state )
225
226   /* basic machine hardware */
227   MCFG_CPU_ADD("master",Z80,MAIN_CLOCK/2)
228   MCFG_CPU_PROGRAM_MAP(mz3500_master_map)
229   MCFG_CPU_IO_MAP(mz3500_master_io)
230
231   MCFG_CPU_ADD("slave",Z80,MAIN_CLOCK/2)
232   MCFG_CPU_PROGRAM_MAP(mz3500_slave_map)
233   MCFG_CPU_IO_MAP(mz3500_slave_io)
234
235   /* video hardware */
236   MCFG_SCREEN_ADD("screen", RASTER)
237   MCFG_SCREEN_REFRESH_RATE(60)
238   MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
239   MCFG_SCREEN_UPDATE_DRIVER(mz3500_state, screen_update)
240   MCFG_SCREEN_SIZE(32*8, 32*8)
241   MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 0*8, 32*8-1)
242
243   MCFG_GFXDECODE(mz3500)
244
245   MCFG_PALETTE_LENGTH(8)
246
247   /* sound hardware */
248   MCFG_SPEAKER_STANDARD_MONO("mono")
249//  MCFG_SOUND_ADD("aysnd", AY8910, MAIN_CLOCK/4)
250//  MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.30)
251MACHINE_CONFIG_END
252
253
254/***************************************************************************
255
256  Game driver(s)
257
258***************************************************************************/
259
260ROM_START( mz3500 )
261   ROM_REGION( 0x2000, "ipl", ROMREGION_ERASE00 )
262   ROM_LOAD( "mz-3500_ipl-rom_2-0a_m5l2764k.bin", 0x000000, 0x002000, CRC(119708b9) SHA1(de81979608ba6ab76f09088a92bfd1a5bc42530e) )
263
264   ROM_REGION( 0x8000, "basic", ROMREGION_ERASE00 )
265   ROM_LOAD( "basic.rom", 0x00000, 0x8000, NO_DUMP )
266
267   ROM_REGION( 0x2000, "gfx1", ROMREGION_ERASE00 )
268   ROM_LOAD( "mz-3500_cg-rom_2-b_m5l2764k.bin", 0x000000, 0x002000, CRC(29f2f80a) SHA1(64b307cd9de5a3327e3ec9f3d0d6b3485706f436) )
269ROM_END
270
271GAME( 198?, mz3500,  0,   mz3500,  mz3500, driver_device,  0,       ROT0, "Sharp",      "MZ-3500", GAME_IS_SKELETON )
Property changes on: trunk/src/mess/drivers/mz3500.c
Added: svn:eol-style
   + native
Added: svn:mime-type
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