trunk/src/mame/machine/mega32x.c
| r22032 | r22033 | |
| 796 | 796 | |
| 797 | 797 | |
| 798 | 798 | |
| 799 | | void sega_32x_device::calculate_pwm_timer(running_machine &machine) |
| 799 | void sega_32x_device::calculate_pwm_timer() |
| 800 | 800 | { |
| 801 | 801 | if(m_pwm_tm_reg == 0) { m_pwm_tm_reg = 16; } // zero gives max range |
| 802 | 802 | if(m_pwm_cycle == 0) { m_pwm_cycle = 4095; } // zero gives max range |
| r22032 | r22033 | |
| 815 | 815 | } |
| 816 | 816 | |
| 817 | 817 | |
| 818 | | void sega_32x_device::handle_pwm_callback(void) |
| 818 | void sega_32x_device::handle_pwm_callback() |
| 819 | 819 | { |
| 820 | 820 | if(m_lch_index_r < PWM_FIFO_SIZE) |
| 821 | 821 | { |
| r22032 | r22033 | |
| 887 | 887 | case 0x00/2: |
| 888 | 888 | m_pwm_ctrl = data & 0xffff; |
| 889 | 889 | m_pwm_tm_reg = (m_pwm_ctrl & 0xf00) >> 8; |
| 890 | | calculate_pwm_timer(space.machine()); |
| 890 | calculate_pwm_timer(); |
| 891 | 891 | break; |
| 892 | 892 | case 0x02/2: |
| 893 | 893 | m_pwm_cycle = m_pwm_cycle_reg = data & 0xfff; |
| 894 | | calculate_pwm_timer(space.machine()); |
| 894 | calculate_pwm_timer(); |
| 895 | 895 | break; |
| 896 | 896 | case 0x04/2: |
| 897 | 897 | if(m_lch_index_w < PWM_FIFO_SIZE) |
| r22032 | r22033 | |
| 1602 | 1602 | |
| 1603 | 1603 | |
| 1604 | 1604 | |
| 1605 | | UINT32* sega_32x_device::_32x_render_videobuffer_to_screenbuffer_helper(running_machine &machine, int scanline) |
| 1605 | UINT32* sega_32x_device::_32x_render_videobuffer_to_screenbuffer_helper(int scanline) |
| 1606 | 1606 | { |
| 1607 | 1607 | int x; |
| 1608 | 1608 | |
trunk/src/mame/machine/mega32x.h
| r22032 | r22033 | |
| 104 | 104 | DECLARE_WRITE16_MEMBER( _32x_sh2_master_401e_w ); |
| 105 | 105 | DECLARE_WRITE16_MEMBER( _32x_sh2_slave_401e_w ); |
| 106 | 106 | |
| 107 | | UINT32* _32x_render_videobuffer_to_screenbuffer_helper(running_machine &machine, int scanline); |
| 107 | UINT32* _32x_render_videobuffer_to_screenbuffer_helper(int scanline); |
| 108 | 108 | int sh2_master_pwmint_enable, sh2_slave_pwmint_enable; |
| 109 | 109 | |
| 110 | 110 | void _32x_check_framebuffer_swap(bool enabled); |
| r22032 | r22033 | |
| 125 | 125 | UINT32 m_32x_linerender[320+258]; // tmp buffer (bigger than it needs to be to simplify RLE decode) |
| 126 | 126 | |
| 127 | 127 | |
| 128 | | void handle_pwm_callback(void); |
| 129 | | void calculate_pwm_timer(running_machine &machine); |
| 130 | | UINT16 m_pwm_ctrl,m_pwm_cycle,m_pwm_tm_reg; |
| 128 | void handle_pwm_callback(); |
| 129 | void calculate_pwm_timer(); |
| 130 | UINT16 m_pwm_ctrl, m_pwm_cycle, m_pwm_tm_reg; |
| 131 | 131 | UINT16 m_cur_lch[0x10],m_cur_rch[0x10]; |
| 132 | 132 | UINT16 m_pwm_cycle_reg; //used for latching |
| 133 | 133 | UINT8 m_pwm_timer_tick; |
| 134 | | UINT8 m_lch_index_r,m_rch_index_r,m_lch_index_w,m_rch_index_w; |
| 135 | | UINT16 m_lch_fifo_state,m_rch_fifo_state; |
| 134 | UINT8 m_lch_index_r, m_rch_index_r, m_lch_index_w, m_rch_index_w; |
| 135 | UINT16 m_lch_fifo_state, m_rch_fifo_state; |
| 136 | 136 | |
| 137 | 137 | |
| 138 | 138 | UINT16 get_hposition(void); |
trunk/src/mame/machine/megacd.c
| r22032 | r22033 | |
| 218 | 218 | } |
| 219 | 219 | |
| 220 | 220 | |
| 221 | | void sega_segacd_device::segacd_1meg_mode_word_write(running_machine& machine, int offset, UINT16 data, UINT16 mem_mask, int use_pm) |
| 221 | void sega_segacd_device::segacd_1meg_mode_word_write(int offset, UINT16 data, UINT16 mem_mask, int use_pm) |
| 222 | 222 | { |
| 223 | 223 | offset *= 2; |
| 224 | 224 | |
| r22032 | r22033 | |
| 316 | 316 | { |
| 317 | 317 | if (m_a12000_halt_reset_reg & 0x0100) |
| 318 | 318 | { |
| 319 | | running_machine& machine = space.machine(); |
| 320 | 319 | CHECK_SCD_LV2_INTERRUPT |
| 321 | 320 | } |
| 322 | 321 | |
| r22032 | r22033 | |
| 705 | 704 | // ret bit set by sub cpu determines which half of WorkRAM we have access to? |
| 706 | 705 | if (scd_rammode&1) |
| 707 | 706 | { |
| 708 | | segacd_1meg_mode_word_write(space.machine(), offset+0x20000/2, data, mem_mask, 0); |
| 707 | segacd_1meg_mode_word_write(offset+0x20000/2, data, mem_mask, 0); |
| 709 | 708 | } |
| 710 | 709 | else |
| 711 | 710 | { |
| 712 | | segacd_1meg_mode_word_write(space.machine(), offset+0x00000/2, data, mem_mask, 0); |
| 711 | segacd_1meg_mode_word_write(offset+0x00000/2, data, mem_mask, 0); |
| 713 | 712 | } |
| 714 | 713 | } |
| 715 | 714 | else |
| r22032 | r22033 | |
| 1172 | 1171 | |
| 1173 | 1172 | if (scd_rammode&1) |
| 1174 | 1173 | { |
| 1175 | | segacd_1meg_mode_word_write(space.machine(), offset/2+0x00000/2, data , mem_mask, 1); |
| 1174 | segacd_1meg_mode_word_write(offset/2+0x00000/2, data , mem_mask, 1); |
| 1176 | 1175 | } |
| 1177 | 1176 | else |
| 1178 | 1177 | { |
| 1179 | | segacd_1meg_mode_word_write(space.machine(), offset/2+0x20000/2, data, mem_mask, 1); |
| 1178 | segacd_1meg_mode_word_write(offset/2+0x20000/2, data, mem_mask, 1); |
| 1180 | 1179 | } |
| 1181 | 1180 | |
| 1182 | 1181 | // printf("Unspported: segacd_sub_dataram_part1_w in mode 1 (Word RAM Expander - 1 Byte Per Pixel) %04x\n", data); |
| r22032 | r22033 | |
| 1220 | 1219 | // ret bit set by sub cpu determines which half of WorkRAM we have access to? |
| 1221 | 1220 | if (scd_rammode&1) |
| 1222 | 1221 | { |
| 1223 | | segacd_1meg_mode_word_write(space.machine(),offset+0x00000/2, data, mem_mask, 0); |
| 1222 | segacd_1meg_mode_word_write(offset+0x00000/2, data, mem_mask, 0); |
| 1224 | 1223 | } |
| 1225 | 1224 | else |
| 1226 | 1225 | { |
| 1227 | | segacd_1meg_mode_word_write(space.machine(),offset+0x20000/2, data, mem_mask, 0); |
| 1226 | segacd_1meg_mode_word_write(offset+0x20000/2, data, mem_mask, 0); |
| 1228 | 1227 | } |
| 1229 | 1228 | |
| 1230 | 1229 | } |
| r22032 | r22033 | |
| 1716 | 1715 | UINT8 *dest; |
| 1717 | 1716 | int srcoffset = 0; |
| 1718 | 1717 | int dstoffset = 0; |
| 1719 | | address_space& space = machine().device(":segacd:segacd_68k")->memory().space(AS_PROGRAM); |
| 1718 | address_space& space = m_scdcpu->space(AS_PROGRAM); |
| 1720 | 1719 | |
| 1721 | 1720 | bool PCM_DMA = false; |
| 1722 | 1721 | |
| r22032 | r22033 | |
| 1779 | 1778 | |
| 1780 | 1779 | if (!(scd_rammode & 1)) |
| 1781 | 1780 | { |
| 1782 | | segacd_1meg_mode_word_write(space.machine(),(dstoffset+0x20000)/2, data, 0xffff, 0); |
| 1781 | segacd_1meg_mode_word_write((dstoffset+0x20000)/2, data, 0xffff, 0); |
| 1783 | 1782 | } |
| 1784 | 1783 | else |
| 1785 | 1784 | { |
| 1786 | | segacd_1meg_mode_word_write(space.machine(),(dstoffset+0x00000)/2, data, 0xffff, 0); |
| 1785 | segacd_1meg_mode_word_write((dstoffset+0x00000)/2, data, 0xffff, 0); |
| 1787 | 1786 | } |
| 1788 | 1787 | } |
| 1789 | 1788 | |
trunk/src/mame/machine/megacd.h
| r22032 | r22033 | |
| 15 | 15 | #define CHECK_SCD_LV3_INTERRUPT \ |
| 16 | 16 | if (lc89510_temp->get_segacd_irq_mask() & 0x08) \ |
| 17 | 17 | { \ |
| 18 | | machine().device(":segacd:segacd_68k")->execute().set_input_line(3, HOLD_LINE); \ |
| 18 | m_scdcpu->set_input_line(3, HOLD_LINE); \ |
| 19 | 19 | } |
| 20 | 20 | // from master |
| 21 | 21 | #define CHECK_SCD_LV2_INTERRUPT \ |
| 22 | 22 | if (lc89510_temp->get_segacd_irq_mask() & 0x04) \ |
| 23 | 23 | { \ |
| 24 | | machine.device(":segacd:segacd_68k")->execute().set_input_line(2, HOLD_LINE); \ |
| 24 | m_scdcpu->set_input_line(2, HOLD_LINE); \ |
| 25 | 25 | } |
| 26 | 26 | |
| 27 | 27 | // gfx convert |
| 28 | 28 | #define CHECK_SCD_LV1_INTERRUPT \ |
| 29 | 29 | if (lc89510_temp->get_segacd_irq_mask() & 0x02) \ |
| 30 | 30 | { \ |
| 31 | | machine().device(":segacd:segacd_68k")->execute().set_input_line(1, HOLD_LINE); \ |
| 31 | m_scdcpu->set_input_line(1, HOLD_LINE); \ |
| 32 | 32 | } |
| 33 | 33 | |
| 34 | 34 | #define SEGACD_IRQ3_TIMER_SPEED (attotime::from_nsec(segacd_irq3_timer_reg*30720)) |
| r22032 | r22033 | |
| 253 | 253 | |
| 254 | 254 | inline void write_pixel(running_machine& machine, UINT8 pix, int pixeloffset ); |
| 255 | 255 | UINT16 segacd_1meg_mode_word_read(int offset, UINT16 mem_mask); |
| 256 | | void segacd_1meg_mode_word_write(running_machine& machine, int offset, UINT16 data, UINT16 mem_mask, int use_pm); |
| 256 | void segacd_1meg_mode_word_write(int offset, UINT16 data, UINT16 mem_mask, int use_pm); |
| 257 | 257 | |
| 258 | 258 | DECLARE_READ16_MEMBER( segacd_dmaaddr_r ); |
| 259 | 259 | DECLARE_WRITE16_MEMBER( segacd_dmaaddr_w ); |