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r22021 Friday 22nd March, 2013 at 07:55:40 UTC by Fabio Priuli
more of the same. nw.
[src/mame/includes]megadriv.h
[src/mame/machine]mega32x.c mega32x.h megadriv.c

trunk/src/mame/machine/mega32x.c
r22020r22021
199199#include "includes/megadriv.h"
200200
201201
202
203/* the main Megadrive emulation needs to know this */
204cpu_device *_32x_master_cpu;
205cpu_device *_32x_slave_cpu;
206
207202/* need to make fifo callback part of device */
208203static UINT16 fifo_block_a[4];
209204static UINT16 fifo_block_b[4];
r22020r22021
221216
222217sega_32x_device::sega_32x_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock, device_type type)
223218   : device_t(mconfig, type, "sega_32x_device", tag, owner, clock),
219      m_master_cpu(*this, "32x_master_sh2"),
220      m_slave_cpu(*this, "32x_slave_sh2"),
224221      m_lch_pwm(*this, "lch_pwm"),
225222      m_rch_pwm(*this, "rch_pwm")
226223{
r22020r22021
567564                  current_fifo_block = fifo_block_b;
568565                  current_fifo_readblock = fifo_block_a;
569566                  // incase we have a stalled DMA in progress, let the SH2 know there is data available
570                  sh2_notify_dma_data_available(space.machine().device(_32X_MASTER_TAG));
571                  sh2_notify_dma_data_available(space.machine().device(_32X_SLAVE_TAG));
567                  sh2_notify_dma_data_available(m_master_cpu);
568                  sh2_notify_dma_data_available(m_slave_cpu);
572569
573570               }
574571               current_fifo_write_pos = 0;
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582579                  current_fifo_block = fifo_block_a;
583580                  current_fifo_readblock = fifo_block_b;
584581                  // incase we have a stalled DMA in progress, let the SH2 know there is data available
585                  sh2_notify_dma_data_available(space.machine().device(_32X_MASTER_TAG));
586                  sh2_notify_dma_data_available(space.machine().device(_32X_SLAVE_TAG));
582                  sh2_notify_dma_data_available(m_master_cpu);
583                  sh2_notify_dma_data_available(m_slave_cpu);
587584
588585               }
589586
r22020r22021
662659
663660      if (data & 0x02)
664661      {
665         _32x_master_cpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
666         _32x_slave_cpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
662         m_master_cpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
663         m_slave_cpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
667664      }
668665
669666      if (data & 0x01)
r22020r22021
723720
724721      if (data&0x1)
725722      {
726         if (m_sh2_master_cmdint_enable) _32x_master_cpu->set_input_line(SH2_CINT_IRQ_LEVEL,ASSERT_LINE);
723         if (m_sh2_master_cmdint_enable) m_master_cpu->set_input_line(SH2_CINT_IRQ_LEVEL,ASSERT_LINE);
727724         else printf("master cmdint when masked!\n");
728725      }
729726
730727      if (data&0x2)
731728      {
732         if (m_sh2_slave_cmdint_enable) _32x_slave_cpu->set_input_line(SH2_CINT_IRQ_LEVEL,ASSERT_LINE);
729         if (m_sh2_slave_cmdint_enable) m_slave_cpu->set_input_line(SH2_CINT_IRQ_LEVEL,ASSERT_LINE);
733730         else printf("slave cmdint when masked!\n");
734731      }
735732   }
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855852   if(m_pwm_timer_tick == m_pwm_tm_reg)
856853   {
857854      m_pwm_timer_tick = 0;
858      if(sh2_master_pwmint_enable) { _32x_master_cpu->set_input_line(SH2_PINT_IRQ_LEVEL,ASSERT_LINE); }
859      if(sh2_slave_pwmint_enable) { _32x_slave_cpu->set_input_line(SH2_PINT_IRQ_LEVEL,ASSERT_LINE); }
855      if(sh2_master_pwmint_enable) { m_master_cpu->set_input_line(SH2_PINT_IRQ_LEVEL,ASSERT_LINE); }
856      if(sh2_slave_pwmint_enable) { m_slave_cpu->set_input_line(SH2_PINT_IRQ_LEVEL,ASSERT_LINE); }
860857   }
861858
862859   m_32x_pwm_timer->adjust(attotime::from_hz((PWM_CLOCK) / (m_pwm_cycle - 1)));
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13141311// VRES (md reset button interrupt) clear
13151312/**********************************************************************************************/
13161313
1317WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_4014_w ){ _32x_master_cpu->set_input_line(SH2_VRES_IRQ_LEVEL,CLEAR_LINE);}
1318WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_4014_w ) { _32x_slave_cpu->set_input_line(SH2_VRES_IRQ_LEVEL,CLEAR_LINE);}
1314WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_4014_w ){ m_master_cpu->set_input_line(SH2_VRES_IRQ_LEVEL,CLEAR_LINE);}
1315WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_4014_w ) { m_slave_cpu->set_input_line(SH2_VRES_IRQ_LEVEL,CLEAR_LINE);}
13191316
13201317/**********************************************************************************************/
13211318// SH2 side 4016
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13301327// HINT (horizontal interrupt) clear
13311328/**********************************************************************************************/
13321329
1333WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_4018_w ){ _32x_master_cpu->set_input_line(SH2_HINT_IRQ_LEVEL,CLEAR_LINE);}
1334WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_4018_w ) { _32x_slave_cpu->set_input_line(SH2_HINT_IRQ_LEVEL,CLEAR_LINE);}
1330WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_4018_w ){ m_master_cpu->set_input_line(SH2_HINT_IRQ_LEVEL,CLEAR_LINE);}
1331WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_4018_w ) { m_slave_cpu->set_input_line(SH2_HINT_IRQ_LEVEL,CLEAR_LINE);}
13351332
13361333/**********************************************************************************************/
13371334// SH2 side 401A
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13391336// Note: flag cleared here is a guess, according to After Burner behaviour
13401337/**********************************************************************************************/
13411338
1342WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_401a_w ){ m_32x_68k_a15102_reg &= ~1; _32x_master_cpu->set_input_line(SH2_CINT_IRQ_LEVEL,CLEAR_LINE);}
1343WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_401a_w ) { m_32x_68k_a15102_reg &= ~2; _32x_slave_cpu->set_input_line(SH2_CINT_IRQ_LEVEL,CLEAR_LINE);}
1339WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_401a_w ){ m_32x_68k_a15102_reg &= ~1; m_master_cpu->set_input_line(SH2_CINT_IRQ_LEVEL,CLEAR_LINE);}
1340WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_401a_w ) { m_32x_68k_a15102_reg &= ~2; m_slave_cpu->set_input_line(SH2_CINT_IRQ_LEVEL,CLEAR_LINE);}
13441341
13451342/**********************************************************************************************/
13461343// SH2 side 401C
13471344// PINT (PWM timer interrupt) clear
13481345/**********************************************************************************************/
13491346
1350WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_401c_w ){ _32x_master_cpu->set_input_line(SH2_PINT_IRQ_LEVEL,CLEAR_LINE);}
1351WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_401c_w ) { _32x_slave_cpu->set_input_line(SH2_PINT_IRQ_LEVEL,CLEAR_LINE);}
1347WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_401c_w ){ m_master_cpu->set_input_line(SH2_PINT_IRQ_LEVEL,CLEAR_LINE);}
1348WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_401c_w ) { m_slave_cpu->set_input_line(SH2_PINT_IRQ_LEVEL,CLEAR_LINE);}
13521349
13531350/**********************************************************************************************/
13541351// SH2 side 401E
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15581555
15591556void sega_32x_device::_32x_check_irqs(running_machine& machine)
15601557{
1561   if (m_sh2_master_vint_enable && m_sh2_master_vint_pending) _32x_master_cpu->set_input_line(SH2_VINT_IRQ_LEVEL,ASSERT_LINE);
1562   else _32x_master_cpu->set_input_line(SH2_VINT_IRQ_LEVEL,CLEAR_LINE);
1558   if (m_sh2_master_vint_enable && m_sh2_master_vint_pending) m_master_cpu->set_input_line(SH2_VINT_IRQ_LEVEL,ASSERT_LINE);
1559   else m_master_cpu->set_input_line(SH2_VINT_IRQ_LEVEL,CLEAR_LINE);
15631560
1564   if (m_sh2_slave_vint_enable && m_sh2_slave_vint_pending) _32x_slave_cpu->set_input_line(SH2_VINT_IRQ_LEVEL,ASSERT_LINE);
1565   else _32x_slave_cpu->set_input_line(SH2_VINT_IRQ_LEVEL,CLEAR_LINE);
1561   if (m_sh2_slave_vint_enable && m_sh2_slave_vint_pending) m_slave_cpu->set_input_line(SH2_VINT_IRQ_LEVEL,ASSERT_LINE);
1562   else m_slave_cpu->set_input_line(SH2_VINT_IRQ_LEVEL,CLEAR_LINE);
15661563}
15671564
15681565void sega_32x_device::_32x_scanline_cb0(running_machine& machine)
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15831580
15841581      if(genesis_scanline_counter < 224 || m_sh2_hint_in_vbl)
15851582      {
1586         if(m_sh2_master_hint_enable) { _32x_master_cpu->set_input_line(SH2_HINT_IRQ_LEVEL,ASSERT_LINE); }
1587         if(m_sh2_slave_hint_enable) { _32x_slave_cpu->set_input_line(SH2_HINT_IRQ_LEVEL,ASSERT_LINE); }
1583         if(m_sh2_master_hint_enable) { m_master_cpu->set_input_line(SH2_HINT_IRQ_LEVEL,ASSERT_LINE); }
1584         if(m_sh2_slave_hint_enable) { m_slave_cpu->set_input_line(SH2_HINT_IRQ_LEVEL,ASSERT_LINE); }
15881585      }
15891586   }
15901587}
r22020r22021
19071904
19081905
19091906// checking if these help brutal, they don't.
1910   sh2drc_set_options(machine().device(_32X_MASTER_TAG), SH2DRC_COMPATIBLE_OPTIONS);
1911   sh2drc_set_options(machine().device(_32X_SLAVE_TAG), SH2DRC_COMPATIBLE_OPTIONS);
1907   sh2drc_set_options(m_master_cpu, SH2DRC_COMPATIBLE_OPTIONS);
1908   sh2drc_set_options(m_slave_cpu, SH2DRC_COMPATIBLE_OPTIONS);
19121909
19131910
19141911// install these now, otherwise we'll get the following (incorrect) warnings on startup..
r22020r22021
19211918   membank("masterbios")->set_entry(0);
19221919   membank("slavebios")->set_entry(0);
19231920}
1921
1922// if the system has a 32x, the extra CPUs are paused at start
1923void sega_32x_device::pause_cpu()
1924{
1925   m_master_cpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
1926   m_slave_cpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
1927}
trunk/src/mame/machine/mega32x.h
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2222
2323#include "sound/dac.h"
2424
25#define _32X_MASTER_TAG (":sega32x:32x_master_sh2")
26#define _32X_SLAVE_TAG (":sega32x:32x_slave_sh2")
27
28
2925class sega_32x_device : public device_t
3026{
3127public:
3228   sega_32x_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock, device_type type);
3329
30   required_device<cpu_device> m_master_cpu;
31   required_device<cpu_device> m_slave_cpu;
3432   required_device<dac_device> m_lch_pwm;
3533   required_device<dac_device> m_rch_pwm;
3634
35   void pause_cpu();
36
3737   DECLARE_READ32_MEMBER( _32x_sh2_master_4000_common_4002_r );
3838   DECLARE_READ32_MEMBER( _32x_sh2_slave_4000_common_4002_r );
3939   DECLARE_READ32_MEMBER( _32x_sh2_common_4004_common_4006_r );
trunk/src/mame/machine/megadriv.c
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923923   /* default state of z80 = reset, with bus */
924924   mame_printf_debug("Resetting Megadrive / Genesis\n");
925925
926   if (machine.device("genesis_snd_z80") != NULL)
926   if (state->m_z80snd)
927927   {
928928      state->m_genz80.z80_is_reset = 1;
929929      state->m_genz80.z80_has_bus = 1;
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951951   megadriv_reset_vdp(machine);
952952
953953
954
955   /* if any of these extra CPUs exist, pause them until we actually turn them on */
956   if (_32x_master_cpu != NULL)
957   {
958      _32x_master_cpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
959   }
960
961   if (_32x_slave_cpu != NULL)
962   {
963      _32x_slave_cpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
964   }
965
966
967
954   // if the system has a 32x, pause the extra CPUs until they are actually turned on
955   if (state->m_32x)
956      state->m_32x->pause_cpu();
968957}
969958
970959void megadriv_stop_scanline_timer(running_machine &machine)
r22020r22021
12231212      membank("bank1")->set_base(m_genz80.z80_prgram);
12241213   }
12251214
1226   /* Look to see if this system has the 32x Master SH2 */
1227   _32x_master_cpu = machine().device<cpu_device>(_32X_MASTER_TAG);
1228   if (_32x_master_cpu != NULL)
1229   {
1230      printf("32x MASTER SH2 cpu found '%s'\n", _32x_master_cpu->tag() );
1231   }
1232
1233   /* Look to see if this system has the 32x Slave SH2 */
1234   _32x_slave_cpu = machine().device<cpu_device>(_32X_SLAVE_TAG);
1235   if (_32x_slave_cpu != NULL)
1236   {
1237      printf("32x SLAVE SH2 cpu found '%s'\n", _32x_slave_cpu->tag() );
1238   }
1239
12401215   machine().device("maincpu")->execute().set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(md_base_state::genesis_int_callback),this));
12411216   megadriv_backupram = NULL;
12421217   megadriv_backupram_length = 0;
12431218
12441219   vdp_get_word_from_68k_mem = vdp_get_word_from_68k_mem_default;
12451220
1221   if (machine().device("sega32x"))
1222      printf("32X found 'sega32x'\n");
12461223   if (machine().device("svp"))
12471224   {
1248      printf("SVP (cpu) found '%s'\n", machine().device("svp")->tag());
1225      printf("SVP (cpu) found 'svp'\n");
12491226      vdp_get_word_from_68k_mem = vdp_get_word_from_68k_mem_delayed;
12501227   }
12511228   if (machine().device("segacd"))
12521229   {
1253      printf("SegaCD found '%s'\n", machine().device("segacd")->tag());
1230      printf("SegaCD found 'segacd'\n");
12541231      vdp_get_word_from_68k_mem = vdp_get_word_from_68k_mem_delayed;
12551232   }   
12561233
trunk/src/mame/includes/megadriv.h
r22020r22021
9393      m_maincpu(*this,"maincpu"),
9494      m_z80snd(*this,"genesis_snd_z80"),
9595      m_vdp(*this,"gen_vdp"),
96      m_32x(*this,"sega32x"),
9697      m_segacd(*this,"segacd"),
9798      m_megadrive_ram(*this,"megadrive_ram")
9899   { }
99100   optional_device<cpu_device> m_maincpu;
100101   optional_device<cpu_device> m_z80snd;
101102   required_device<sega_genesis_vdp_device> m_vdp;
103   optional_device<sega_32x_device> m_32x;
102104   optional_device<sega_segacd_device> m_segacd;
103105   optional_shared_ptr<UINT16> m_megadrive_ram;
104106
r22020r22021
393395
394396};
395397
396
397
398extern cpu_device *_32x_master_cpu;
399extern cpu_device *_32x_slave_cpu;
400
401// called from out main scanline timers...
402
403
404
405
406
407398class segacd_state : public _32x_state  // use _32x_state as base to make easier the combo 32X + SCD
408399{
409400public:

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