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r22018 Friday 22nd March, 2013 at 06:51:32 UTC by Fabio Priuli
(MESS) megadriv.c: moved z80 vars to the driver state. nw.
[src/mame/includes]megadriv.h
[src/mame/machine]megadriv.c

trunk/src/mame/machine/megadriv.c
r22017r22018
3232
3333timer_device* megadriv_scanline_timer;
3434
35struct genesis_z80_vars
36{
37   int z80_is_reset;
38   int z80_has_bus;
39   UINT32 z80_bank_addr;
40   UINT8* z80_prgram;
41};
4235
43genesis_z80_vars genz80;
44
4536void megadriv_z80_hold(running_machine &machine)
4637{
47   if ((genz80.z80_has_bus == 1) && (genz80.z80_is_reset == 0))
38   md_base_state *state = machine.driver_data<md_base_state>();
39   if ((state->m_genz80.z80_has_bus == 1) && (state->m_genz80.z80_is_reset == 0))
4840      machine.device(":genesis_snd_z80")->execute().set_input_line(0, HOLD_LINE);
4941}
5042
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5345   machine.device(":genesis_snd_z80")->execute().set_input_line(0, CLEAR_LINE);
5446}
5547
56static void megadriv_z80_bank_w(UINT16 data)
48static void megadriv_z80_bank_w(address_space &space, UINT16 data)
5749{
58   genz80.z80_bank_addr = ( ( genz80.z80_bank_addr >> 1 ) | ( data << 23 ) ) & 0xff8000;
50   md_base_state *state = space.machine().driver_data<md_base_state>();
51   state->m_genz80.z80_bank_addr = ((state->m_genz80.z80_bank_addr >> 1) | (data << 23)) & 0xff8000;
5952}
6053
6154static WRITE16_HANDLER( megadriv_68k_z80_bank_write )
6255{
6356   //logerror("%06x: 68k writing bit to bank register %01x\n", space.device().safe_pc(),data&0x01);
64   megadriv_z80_bank_w(data&0x01);
57   megadriv_z80_bank_w(space, data & 0x01);
6558}
6659
6760static WRITE8_HANDLER(megadriv_z80_z80_bank_w)
6861{
6962   //logerror("%04x: z80 writing bit to bank register %01x\n", space.device().safe_pc(),data&0x01);
70   megadriv_z80_bank_w(data&0x01);
63   megadriv_z80_bank_w(space, data & 0x01);
7164}
7265
7366
r22017r22018
8578{
8679   device_t *device = machine().device("ymsnd");
8780   //mame_printf_debug("megadriv_68k_YM2612_read %02x %04x\n",offset,mem_mask);
88   if ( (genz80.z80_has_bus==0) && (genz80.z80_is_reset==0) )
81   if ((m_genz80.z80_has_bus == 0) && (m_genz80.z80_is_reset == 0))
8982   {
9083      return ym2612_r(device, space, offset);
9184   }
r22017r22018
10396{
10497   device_t *device = machine().device("ymsnd");
10598   //mame_printf_debug("megadriv_68k_YM2612_write %02x %04x %04x\n",offset,data,mem_mask);
106   if ( (genz80.z80_has_bus==0) && (genz80.z80_is_reset==0) )
99   if ((m_genz80.z80_has_bus == 0) && (m_genz80.z80_is_reset == 0))
107100   {
108101      ym2612_w(device, space, offset, data);
109102   }
r22017r22018
570563
571564static READ16_HANDLER( megadriv_68k_read_z80_ram )
572565{
566   md_base_state *state = space.machine().driver_data<md_base_state>();
573567   //mame_printf_debug("read z80 ram %04x\n",mem_mask);
574568
575   if ( (genz80.z80_has_bus==0) && (genz80.z80_is_reset==0) )
569   if ((state->m_genz80.z80_has_bus == 0) && (state->m_genz80.z80_is_reset == 0))
576570   {
577      return genz80.z80_prgram[(offset<<1)^1] | (genz80.z80_prgram[(offset<<1)]<<8);
571      return state->m_genz80.z80_prgram[(offset<<1)^1] | (state->m_genz80.z80_prgram[(offset<<1)]<<8);
578572   }
579573   else
580574   {
r22017r22018
585579
586580static WRITE16_HANDLER( megadriv_68k_write_z80_ram )
587581{
582   md_base_state *state = space.machine().driver_data<md_base_state>();
588583   //logerror("write z80 ram\n");
589584
590   if ((genz80.z80_has_bus==0) && (genz80.z80_is_reset==0))
585   if ((state->m_genz80.z80_has_bus == 0) && (state->m_genz80.z80_is_reset == 0))
591586   {
592587      if (!ACCESSING_BITS_0_7) // byte (MSB) access
593588      {
594         genz80.z80_prgram[(offset<<1)] = (data & 0xff00) >> 8;
589         state->m_genz80.z80_prgram[(offset<<1)] = (data & 0xff00) >> 8;
595590      }
596591      else if (!ACCESSING_BITS_8_15)
597592      {
598         genz80.z80_prgram[(offset<<1)^1] = (data & 0x00ff);
593         state->m_genz80.z80_prgram[(offset<<1)^1] = (data & 0x00ff);
599594      }
600595      else // for WORD access only the MSB is used, LSB is ignored
601596      {
602         genz80.z80_prgram[(offset<<1)] = (data & 0xff00) >> 8;
597         state->m_genz80.z80_prgram[(offset<<1)] = (data & 0xff00) >> 8;
603598      }
604599   }
605600   else
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611606
612607static READ16_HANDLER( megadriv_68k_check_z80_bus )
613608{
609   md_base_state *state = space.machine().driver_data<md_base_state>();
614610   UINT16 retvalue;
615611
616612   /* Double Dragon, Shadow of the Beast, Super Off Road, and Time Killers have buggy
r22017r22018
626622   /* Check if the 68k has the z80 bus */
627623   if (!ACCESSING_BITS_0_7) // byte (MSB) access
628624   {
629      if (genz80.z80_has_bus || genz80.z80_is_reset) retvalue = nextvalue | 0x0100;
625      if (state->m_genz80.z80_has_bus || state->m_genz80.z80_is_reset) retvalue = nextvalue | 0x0100;
630626      else retvalue = (nextvalue & 0xfeff);
631627
632628      //logerror("%06x: 68000 check z80 Bus (byte MSB access) returning %04x mask %04x\n", space.device().safe_pc(),retvalue, mem_mask);
r22017r22018
636632   else if (!ACCESSING_BITS_8_15) // is this valid?
637633   {
638634      //logerror("%06x: 68000 check z80 Bus (byte LSB access) %04x\n", space.device().safe_pc(),mem_mask);
639      if (genz80.z80_has_bus || genz80.z80_is_reset) retvalue = 0x0001;
635      if (state->m_genz80.z80_has_bus || state->m_genz80.z80_is_reset) retvalue = 0x0001;
640636      else retvalue = 0x0000;
641637
642638      return retvalue;
r22017r22018
644640   else
645641   {
646642      //logerror("%06x: 68000 check z80 Bus (word access) %04x\n", space.device().safe_pc(),mem_mask);
647      if (genz80.z80_has_bus || genz80.z80_is_reset) retvalue = nextvalue | 0x0100;
643      if (state->m_genz80.z80_has_bus || state->m_genz80.z80_is_reset) retvalue = nextvalue | 0x0100;
648644      else retvalue = (nextvalue & 0xfeff);
649645
650646   //  mame_printf_debug("%06x: 68000 check z80 Bus (word access) %04x %04x\n", space.device().safe_pc(),mem_mask, retvalue);
r22017r22018
655651
656652static TIMER_CALLBACK( megadriv_z80_run_state )
657653{
654   md_base_state *state = machine.driver_data<md_base_state>();
658655   /* Is the z80 RESET line pulled? */
659   if ( genz80.z80_is_reset )
656   if (state->m_genz80.z80_is_reset)
660657   {
661658      machine.device("genesis_snd_z80" )->reset();
662659      machine.device<cpu_device>( "genesis_snd_z80" )->suspend(SUSPEND_REASON_HALT, 1 );
r22017r22018
665662   else
666663   {
667664      /* Check if z80 has the bus */
668      if ( genz80.z80_has_bus )
665      if (state->m_genz80.z80_has_bus)
669666      {
670667         machine.device<cpu_device>( "genesis_snd_z80" )->resume(SUSPEND_REASON_HALT );
671668      }
r22017r22018
679676
680677static WRITE16_HANDLER( megadriv_68k_req_z80_bus )
681678{
679   md_base_state *state = space.machine().driver_data<md_base_state>();
682680   /* Request the Z80 bus, allows 68k to read/write Z80 address space */
683681   if (!ACCESSING_BITS_0_7) // byte access
684682   {
685683      if (data & 0x0100)
686684      {
687685         //logerror("%06x: 68000 request z80 Bus (byte MSB access) %04x %04x\n", space.device().safe_pc(),data,mem_mask);
688         genz80.z80_has_bus = 0;
686         state->m_genz80.z80_has_bus = 0;
689687      }
690688      else
691689      {
692690         //logerror("%06x: 68000 return z80 Bus (byte MSB access) %04x %04x\n", space.device().safe_pc(),data,mem_mask);
693         genz80.z80_has_bus = 1;
691         state->m_genz80.z80_has_bus = 1;
694692      }
695693   }
696694   else if (!ACCESSING_BITS_8_15) // is this valid?
r22017r22018
698696      if (data & 0x0001)
699697      {
700698         //logerror("%06x: 68000 request z80 Bus (byte LSB access) %04x %04x\n", space.device().safe_pc(),data,mem_mask);
701         genz80.z80_has_bus = 0;
699         state->m_genz80.z80_has_bus = 0;
702700      }
703701      else
704702      {
705703         //logerror("%06x: 68000 return z80 Bus (byte LSB access) %04x %04x\n", space.device().safe_pc(),data,mem_mask);
706         genz80.z80_has_bus = 1;
704         state->m_genz80.z80_has_bus = 1;
707705      }
708706   }
709707   else // word access
r22017r22018
711709      if (data & 0x0100)
712710      {
713711         //logerror("%06x: 68000 request z80 Bus (word access) %04x %04x\n", space.device().safe_pc(),data,mem_mask);
714         genz80.z80_has_bus = 0;
712         state->m_genz80.z80_has_bus = 0;
715713      }
716714      else
717715      {
718716         //logerror("%06x: 68000 return z80 Bus (byte LSB access) %04x %04x\n", space.device().safe_pc(),data,mem_mask);
719         genz80.z80_has_bus = 1;
717         state->m_genz80.z80_has_bus = 1;
720718      }
721719   }
722720
723721   /* If the z80 is running, sync the z80 execution state */
724   if ( ! genz80.z80_is_reset )
725      space.machine().scheduler().timer_set( attotime::zero, FUNC(megadriv_z80_run_state ));
722   if (!state->m_genz80.z80_is_reset)
723      space.machine().scheduler().timer_set(attotime::zero, FUNC(megadriv_z80_run_state));
726724}
727725
728726static WRITE16_HANDLER ( megadriv_68k_req_z80_reset )
729727{
728   md_base_state *state = space.machine().driver_data<md_base_state>();
730729   if (!ACCESSING_BITS_0_7) // byte access
731730   {
732731      if (data & 0x0100)
733732      {
734733         //logerror("%06x: 68000 clear z80 reset (byte MSB access) %04x %04x\n", space.device().safe_pc(),data,mem_mask);
735         genz80.z80_is_reset = 0;
734         state->m_genz80.z80_is_reset = 0;
736735      }
737736      else
738737      {
739738         //logerror("%06x: 68000 start z80 reset (byte MSB access) %04x %04x\n", space.device().safe_pc(),data,mem_mask);
740         genz80.z80_is_reset = 1;
739         state->m_genz80.z80_is_reset = 1;
741740      }
742741   }
743742   else if (!ACCESSING_BITS_8_15) // is this valid?
r22017r22018
745744      if (data & 0x0001)
746745      {
747746         //logerror("%06x: 68000 clear z80 reset (byte LSB access) %04x %04x\n", space.device().safe_pc(),data,mem_mask);
748         genz80.z80_is_reset = 0;
747         state->m_genz80.z80_is_reset = 0;
749748      }
750749      else
751750      {
752751         //logerror("%06x: 68000 start z80 reset (byte LSB access) %04x %04x\n", space.device().safe_pc(),data,mem_mask);
753         genz80.z80_is_reset = 1;
752         state->m_genz80.z80_is_reset = 1;
754753      }
755754   }
756755   else // word access
r22017r22018
758757      if (data & 0x0100)
759758      {
760759         //logerror("%06x: 68000 clear z80 reset (word access) %04x %04x\n", space.device().safe_pc(),data,mem_mask);
761         genz80.z80_is_reset = 0;
760         state->m_genz80.z80_is_reset = 0;
762761      }
763762      else
764763      {
765764         //logerror("%06x: 68000 start z80 reset (byte LSB access) %04x %04x\n", space.device().safe_pc(),data,mem_mask);
766         genz80.z80_is_reset = 1;
765         state->m_genz80.z80_is_reset = 1;
767766      }
768767   }
769768   space.machine().scheduler().timer_set( attotime::zero, FUNC(megadriv_z80_run_state ));
r22017r22018
776775//   z80 area of the 68k if games misbehave
777776static READ8_HANDLER( z80_read_68k_banked_data )
778777{
778   md_base_state *state = space.machine().driver_data<md_base_state>();
779779   address_space &space68k = space.machine().device<legacy_cpu_device>("maincpu")->space();
780   UINT8 ret = space68k.read_byte(genz80.z80_bank_addr+offset);
780   UINT8 ret = space68k.read_byte(state->m_genz80.z80_bank_addr+offset);
781781   return ret;
782782}
783783
784784static WRITE8_HANDLER( z80_write_68k_banked_data )
785785{
786   md_base_state *state = space.machine().driver_data<md_base_state>();
786787   address_space &space68k = space.machine().device<legacy_cpu_device>("maincpu")->space();
787   space68k.write_byte(genz80.z80_bank_addr+offset,data);
788   space68k.write_byte(state->m_genz80.z80_bank_addr+offset,data);
788789}
789790
790791
r22017r22018
930931
931932   if (machine.device("genesis_snd_z80") != NULL)
932933   {
933      genz80.z80_is_reset = 1;
934      genz80.z80_has_bus = 1;
935      genz80.z80_bank_addr = 0;
934      state->m_genz80.z80_is_reset = 1;
935      state->m_genz80.z80_has_bus = 1;
936      state->m_genz80.z80_bank_addr = 0;
936937      genesis_scanline_counter = -1;
937      machine.scheduler().timer_set( attotime::zero, FUNC(megadriv_z80_run_state ));
938      machine.scheduler().timer_set(attotime::zero, FUNC(megadriv_z80_run_state));
938939   }
939940
940941   megadrive_reset_io(machine);
r22017r22018
12231224   if (machine().device("genesis_snd_z80"))
12241225   {
12251226      //printf("GENESIS Sound Z80 cpu found '%s'\n", machine().device("genesis_snd_z80")->tag());
1226      genz80.z80_prgram = auto_alloc_array(machine(), UINT8, 0x2000);
1227      membank("bank1")->set_base(genz80.z80_prgram);
1227      m_genz80.z80_prgram = auto_alloc_array(machine(), UINT8, 0x2000);
1228      membank("bank1")->set_base(m_genz80.z80_prgram);
12281229   }
12291230
12301231   /* Look to see if this system has the 32x Master SH2 */
r22017r22018
13661367/* sets the megadrive z80 to it's normal ports / map */
13671368void megatech_set_megadrive_z80_as_megadrive_z80(running_machine &machine, const char* tag)
13681369{
1370   md_base_state *state = machine.driver_data<md_base_state>();
13691371   device_t *ym = machine.device("ymsnd");
13701372
13711373   /* INIT THE PORTS *********************************************************************************************/
r22017r22018
13761378
13771379
13781380   machine.device(tag)->memory().space(AS_PROGRAM).install_readwrite_bank(0x0000, 0x1fff, "bank1");
1379   machine.root_device().membank("bank1")->set_base(genz80.z80_prgram );
1381   machine.root_device().membank("bank1")->set_base(state->m_genz80.z80_prgram);
13801382
1381   machine.device(tag)->memory().space(AS_PROGRAM).install_ram(0x0000, 0x1fff, genz80.z80_prgram);
1383   machine.device(tag)->memory().space(AS_PROGRAM).install_ram(0x0000, 0x1fff, state->m_genz80.z80_prgram);
13821384
13831385
13841386   machine.device(tag)->memory().space(AS_PROGRAM).install_legacy_readwrite_handler(*ym, 0x4000, 0x4003, FUNC(ym2612_r), FUNC(ym2612_w));
trunk/src/mame/includes/megadriv.h
r22017r22018
7575#define MP_ROM  0x10
7676#define MP_GAME 0
7777
78
79struct genesis_z80_vars
80{
81   int z80_is_reset;
82   int z80_has_bus;
83   UINT32 z80_bank_addr;
84   UINT8* z80_prgram;
85};
86
87
7888class md_base_state : public driver_device
7989{
8090public:
r22017r22018
92102   optional_device<sega_segacd_device> m_segacd;
93103   optional_shared_ptr<UINT16> m_megadrive_ram;
94104
105   genesis_z80_vars m_genz80;
106
95107   DECLARE_DRIVER_INIT(megadriv_c2);
96108   DECLARE_DRIVER_INIT(megadrie);
97109   DECLARE_DRIVER_INIT(megadriv);

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