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r21925 Monday 18th March, 2013 at 04:06:17 UTC by Angelo Salese
Fixed I2C for Mega Drive, NBA Jam TE is still broken due of a mem_mask issue (slot code thinks it's always a word access, but it actually isn't most of the time)
[src/mess/machine]md_eeprom.c

trunk/src/mess/machine/md_eeprom.c
r21924r21925
109109
110110static const i2cmem_interface md_24c01_i2cmem_interface =
111111{
112   I2CMEM_SLAVE_ADDRESS, 0, 0x80
112   I2CMEM_SLAVE_ADDRESS, 4, 0x80
113113};
114114
115115
116116static const i2cmem_interface md_24c02_i2cmem_interface =
117117{
118   I2CMEM_SLAVE_ADDRESS, 0, 0x100
118   I2CMEM_SLAVE_ADDRESS, 4, 0x100
119119};
120120
121121
122122static const i2cmem_interface md_24c16_i2cmem_interface =
123123{
124   I2CMEM_SLAVE_ADDRESS, 0, 0x800
124   I2CMEM_SLAVE_ADDRESS, 8, 0x800
125125};
126126
127127
128128static const i2cmem_interface md_24c64_i2cmem_interface =
129129{
130   I2CMEM_SLAVE_ADDRESS, 0, 0x2000
130   I2CMEM_SLAVE_ADDRESS, 8, 0x2000
131131};
132132
133133
r21924r21925
217217{
218218   if (offset == 0x200000/2)
219219   {
220//      m_i2c_mem = i2cmem_sda_read(m_i2cmem);
221      return ~m_i2c_mem & 1;
220      return i2cmem_sda_read(m_i2cmem);
222221   }
223222   if (offset < 0x400000/2)
224223      return m_rom[MD_ADDR(offset)];
r21924r21925
242241   if (offset == 0x200000/2)
243242   {
244243//      m_i2c_mem = i2cmem_sda_read(m_i2cmem);
245      return m_i2c_mem & 1;
244      return i2cmem_sda_read(m_i2cmem);
246245   }
247246   if (offset < 0x400000/2)
248247      return m_rom[MD_ADDR(offset)];
r21924r21925
266265   if (offset == 0x200000/2)
267266   {
268267//      m_i2c_mem = i2cmem_sda_read(m_i2cmem);
269      return m_i2c_mem & 1;
268      return i2cmem_sda_read(m_i2cmem);
270269   }
271270   if (offset < 0x400000/2)
272271      return m_rom[MD_ADDR(offset)];
r21924r21925
278277{
279278   if (offset == 0x200000/2)
280279   {
281      m_i2c_clk = BIT(data, 8);
282      m_i2c_mem = BIT(data, 0);
283      i2cmem_scl_write(m_i2cmem, m_i2c_clk);
284      i2cmem_sda_write(m_i2cmem, m_i2c_mem);
280      if(ACCESSING_BITS_8_15)
281      {
282         m_i2c_clk = BIT(data, 8);
283         i2cmem_scl_write(m_i2cmem, m_i2c_clk);
284      }
285
286      if(ACCESSING_BITS_0_7)
287      {
288         m_i2c_mem = BIT(data, 0);
289         i2cmem_sda_write(m_i2cmem, m_i2c_mem);
290      }
285291   }
286292}
287293
r21924r21925
291297   if (offset == 0x200000/2)
292298   {
293299//      m_i2c_mem = i2cmem_sda_read(m_i2cmem);
294      return m_i2c_mem & 1;
300      return i2cmem_sda_read(m_i2cmem);
295301   }
296302   if (offset < 0x400000/2)
297303      return m_rom[MD_ADDR(offset)];
r21924r21925
303309{
304310   if (offset == 0x200000/2)
305311   {
306      m_i2c_clk = BIT(data, 8);
307      m_i2c_mem = BIT(data, 0);
308      i2cmem_scl_write(m_i2cmem, m_i2c_clk);
309      i2cmem_sda_write(m_i2cmem, m_i2c_mem);
312      if(ACCESSING_BITS_8_15)
313      {
314         m_i2c_clk = BIT(data, 8);
315         i2cmem_scl_write(m_i2cmem, m_i2c_clk);
316      }
317
318      if(ACCESSING_BITS_0_7)
319      {
320         m_i2c_mem = BIT(data, 0);
321         i2cmem_sda_write(m_i2cmem, m_i2c_mem);
322      }
310323   }
311324}
312325
r21924r21925
316329   if (offset == 0x200000/2)
317330   {
318331//      m_i2c_mem = i2cmem_sda_read(m_i2cmem);
319      return m_i2c_mem & 1;
332      return i2cmem_sda_read(m_i2cmem);
320333   }
321334   if (offset < 0x400000/2)
322335      return m_rom[MD_ADDR(offset)];
r21924r21925
340353   if (offset == 0x200000/2)
341354   {
342355//      m_i2c_mem = i2cmem_sda_read(m_i2cmem);
343      return (m_i2c_mem & 1) << 7;
356      return (i2cmem_sda_read(m_i2cmem) & 1) << 7;
344357   }
345358   if (offset < 0x400000/2)
346359      return m_rom[MD_ADDR(offset)];
r21924r21925
364377   if (offset == 0x380000/2)
365378   {
366379//      m_i2c_mem = i2cmem_sda_read(m_i2cmem);
367      return (m_i2c_mem & 1) << 7;
380      return (i2cmem_sda_read(m_i2cmem) & 1) << 7;
368381   }
369382   if (offset < 0x400000/2)
370383      return m_rom[MD_ADDR(offset)];

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