MAME SVN History

199869 Revisions

r21689 Thursday 7th March, 2013 at 19:12:27 UTC by Curt Coder
Reverted MC68328 changes. (nw)

[src/emu]	emu.mak
[src/emu/machine]	~~mc68328.c~~ ~~mc68328.h~~ ~~mc68328p.h~~
[src/mess]	mess.mak
[src/mess/drivers]	palm.c
[src/mess/includes]	mc68328.h*
[src/mess/machine]	mc68328.c* mc68328.h*

trunk/src/emu/emu.mak
r21688	r21689
226	226	$(EMUMACHINE)/mc6846.o \
227	227	$(EMUMACHINE)/mc6852.o \
228	228	$(EMUMACHINE)/mc6854.o \
229		$(EMUMACHINE)/mc68328.o \
230	229	$(EMUMACHINE)/mc68901.o \
231	230	$(EMUMACHINE)/mccs1850.o \
232	231	$(EMUMACHINE)/microtch.o \

trunk/src/emu/machine/mc68328.c
r21688	r21689
1		/**********************************************************************
2
3		Motorola 68328 ("DragonBall") System-on-a-Chip implementation
4
5		By MooglyGuy
6		contact mooglyguy@gmail.com with licensing and usage questions.
7
8		**********************************************************************/
9
10		#include "emu.h"
11		#include "cpu/m68000/m68000.h"
12		#include "mc68328.h"
13		#include "mc68328p.h"
14
15		#define VERBOSE_LEVEL (0)
16
17		INLINE void verboselog(running_machine &machine, int n_level, const char *s_fmt, ...)
18		{
19		if( VERBOSE_LEVEL >= n_level )
20		{
21		va_list v;
22		char buf[ 32768 ];
23		va_start( v, s_fmt );
24		vsprintf( buf, s_fmt, v );
25		va_end( v );
26		logerror( "%s: %s", machine.describe_context(), buf );
27		}
28		}
29
30		static void mc68328_set_interrupt_line(device_t *device, UINT32 line, UINT32 active)
31		{
32		mc68328_t* mc68328 = mc68328_get_safe_token( device );
33		device_t *cpu = device->machine().device(mc68328->iface->m68k_cpu_tag);
34
35		if(active)
36		{
37		mc68328->regs.ipr \|= line;
38
39		if(!(mc68328->regs.imr & line) && !(mc68328->regs.isr & line))
40		{
41		mc68328->regs.isr \|= line;
42
43		if(mc68328->regs.isr & INT_M68K_LINE7)
44		{
45		cpu->execute().set_input_line_and_vector(M68K_IRQ_7, ASSERT_LINE, mc68328->regs.ivr \| 0x07);
46		}
47		else if(mc68328->regs.isr & INT_M68K_LINE6)
48		{
49		cpu->execute().set_input_line_and_vector(M68K_IRQ_6, ASSERT_LINE, mc68328->regs.ivr \| 0x06);
50		}
51		else if(mc68328->regs.isr & INT_M68K_LINE5)
52		{
53		cpu->execute().set_input_line_and_vector(M68K_IRQ_5, ASSERT_LINE, mc68328->regs.ivr \| 0x05);
54		}
55		else if(mc68328->regs.isr & INT_M68K_LINE4)
56		{
57		cpu->execute().set_input_line_and_vector(M68K_IRQ_4, ASSERT_LINE, mc68328->regs.ivr \| 0x04);
58		}
59		else if(mc68328->regs.isr & INT_M68K_LINE3)
60		{
61		cpu->execute().set_input_line_and_vector(M68K_IRQ_3, ASSERT_LINE, mc68328->regs.ivr \| 0x03);
62		}
63		else if(mc68328->regs.isr & INT_M68K_LINE2)
64		{
65		cpu->execute().set_input_line_and_vector(M68K_IRQ_2, ASSERT_LINE, mc68328->regs.ivr \| 0x02);
66		}
67		else if(mc68328->regs.isr & INT_M68K_LINE1)
68		{
69		cpu->execute().set_input_line_and_vector(M68K_IRQ_1, ASSERT_LINE, mc68328->regs.ivr \| 0x01);
70		}
71		}
72		}
73		else
74		{
75		mc68328->regs.isr &= ~line;
76
77		if((line & INT_M68K_LINE7) && !(mc68328->regs.isr & INT_M68K_LINE7))
78		{
79		cpu->execute().set_input_line(M68K_IRQ_7, CLEAR_LINE);
80		}
81		if((line & INT_M68K_LINE6) && !(mc68328->regs.isr & INT_M68K_LINE6))
82		{
83		cpu->execute().set_input_line(M68K_IRQ_6, CLEAR_LINE);
84		}
85		if((line & INT_M68K_LINE5) && !(mc68328->regs.isr & INT_M68K_LINE5))
86		{
87		cpu->execute().set_input_line(M68K_IRQ_5, CLEAR_LINE);
88		}
89		if((line & INT_M68K_LINE4) && !(mc68328->regs.isr & INT_M68K_LINE4))
90		{
91		cpu->execute().set_input_line(M68K_IRQ_4, CLEAR_LINE);
92		}
93		if((line & INT_M68K_LINE3) && !(mc68328->regs.isr & INT_M68K_LINE3))
94		{
95		cpu->execute().set_input_line(M68K_IRQ_3, CLEAR_LINE);
96		}
97		if((line & INT_M68K_LINE2) && !(mc68328->regs.isr & INT_M68K_LINE2))
98		{
99		cpu->execute().set_input_line(M68K_IRQ_2, CLEAR_LINE);
100		}
101		if((line & INT_M68K_LINE1) && !(mc68328->regs.isr & INT_M68K_LINE1))
102		{
103		cpu->execute().set_input_line(M68K_IRQ_1, CLEAR_LINE);
104		}
105		}
106		}
107
108		static void mc68328_poll_port_d_interrupts(device_t *device)
109		{
110		mc68328_t* mc68328 = mc68328_get_safe_token( device );
111		UINT8 line_transitions = mc68328->regs.pddataedge & mc68328->regs.pdirqedge;
112		UINT8 line_holds = mc68328->regs.pddata &~ mc68328->regs.pdirqedge;
113		UINT8 line_interrupts = (line_transitions \| line_holds) & mc68328->regs.pdirqen;
114
115		if(line_interrupts)
116		{
117		mc68328_set_interrupt_line(device, line_interrupts << 8, 1);
118		}
119		else
120		{
121		mc68328_set_interrupt_line(device, INT_KBDINTS, 0);
122		}
123		}
124
125		void mc68328_set_penirq_line(device_t *device, int state)
126		{
127		mc68328_t* mc68328 = mc68328_get_safe_token( device );
128
129		if(state)
130		{
131		mc68328_set_interrupt_line(device, INT_PEN, 1);
132		}
133		else
134		{
135		mc68328->regs.ipr &= ~INT_PEN;
136		mc68328_set_interrupt_line(device, INT_PEN, 0);
137		}
138		}
139
140		void mc68328_set_port_d_lines(device_t *device, UINT8 state, int bit)
141		{
142		mc68328_t* mc68328 = mc68328_get_safe_token( device );
143		UINT8 old_button_state = mc68328->regs.pddata;
144
145		if(state & (1 << bit))
146		{
147		mc68328->regs.pddata \|= (1 << bit);
148		}
149		else
150		{
151		mc68328->regs.pddata &= ~(1 << bit);
152		}
153
154		mc68328->regs.pddataedge \|= ~old_button_state & mc68328->regs.pddata;
155
156		mc68328_poll_port_d_interrupts(device);
157		}
158
159		static UINT32 mc68328_get_timer_frequency(device_t *device, UINT32 index)
160		{
161		mc68328_t* mc68328 = mc68328_get_safe_token( device );
162		UINT32 frequency = 0;
163
164		switch(mc68328->regs.tctl[index] & TCTL_CLKSOURCE)
165		{
166		case TCTL_CLKSOURCE_SYSCLK:
167		frequency = 32768 * 506;
168		break;
169
170		case TCTL_CLKSOURCE_SYSCLK16:
171		frequency = (32768 * 506) / 16;
172		break;
173
174		case TCTL_CLKSOURCE_32KHZ4:
175		case TCTL_CLKSOURCE_32KHZ5:
176		case TCTL_CLKSOURCE_32KHZ6:
177		case TCTL_CLKSOURCE_32KHZ7:
178		frequency = 32768;
179		break;
180		}
181		frequency /= (mc68328->regs.tprer[index] + 1);
182
183		return frequency;
184		}
185
186		static void mc68328_maybe_start_timer(device_t *device, UINT32 index, UINT32 new_enable)
187		{
188		mc68328_t* mc68328 = mc68328_get_safe_token( device );
189
190		if((mc68328->regs.tctl[index] & TCTL_TEN) == TCTL_TEN_ENABLE && (mc68328->regs.tctl[index] & TCTL_CLKSOURCE) > TCTL_CLKSOURCE_STOP)
191		{
192		if((mc68328->regs.tctl[index] & TCTL_CLKSOURCE) == TCTL_CLKSOURCE_TIN)
193		{
194		mc68328->gptimer[index]->adjust(attotime::never);
195		}
196		else if(mc68328->regs.tcmp[index] == 0)
197		{
198		mc68328->gptimer[index]->adjust(attotime::never);
199		}
200		else
201		{
202		UINT32 frequency = mc68328_get_timer_frequency(device, index);
203		attotime period = (attotime::from_hz(frequency) * mc68328->regs.tcmp[index]);
204
205		if(new_enable)
206		{
207		mc68328->regs.tcn[index] = 0x0000;
208		}
209
210		mc68328->gptimer[index]->adjust(period);
211		}
212		}
213		else
214		{
215		mc68328->gptimer[index]->adjust(attotime::never);
216		}
217		}
218
219		static void mc68328_timer_compare_event(device_t *device, UINT32 index)
220		{
221		mc68328_t* mc68328 = mc68328_get_safe_token( device );
222
223		mc68328->regs.tcn[index] = mc68328->regs.tcmp[index];
224		mc68328->regs.tstat[index] \|= TSTAT_COMP;
225
226		if((mc68328->regs.tctl[index] & TCTL_FRR) == TCTL_FRR_RESTART)
227		{
228		UINT32 frequency = mc68328_get_timer_frequency(device, index);
229
230		if(frequency > 0)
231		{
232		attotime period = attotime::from_hz(frequency) * mc68328->regs.tcmp[index];
233
234		mc68328->regs.tcn[index] = 0x0000;
235
236		mc68328->gptimer[index]->adjust(period);
237		}
238		else
239		{
240		mc68328->gptimer[index]->adjust(attotime::never);
241		}
242		}
243		else
244		{
245		UINT32 frequency = mc68328_get_timer_frequency(device, index);
246
247		if(frequency > 0)
248		{
249		attotime period = attotime::from_hz(frequency) * 0x10000;
250
251		mc68328->gptimer[index]->adjust(period);
252		}
253		else
254		{
255		mc68328->gptimer[index]->adjust(attotime::never);
256		}
257		}
258		if((mc68328->regs.tctl[index] & TCTL_IRQEN) == TCTL_IRQEN_ENABLE)
259		{
260		mc68328_set_interrupt_line(device, (index == 0) ? INT_TIMER1 : INT_TIMER2, 1);
261		}
262		}
263
264		static TIMER_CALLBACK( mc68328_timer1_hit )
265		{
266		device_t *device = machine.device(MC68328_TAG);
267
268		mc68328_timer_compare_event(device, 0);
269		}
270
271		static TIMER_CALLBACK( mc68328_timer2_hit )
272		{
273		device_t *device = machine.device(MC68328_TAG);
274
275		mc68328_timer_compare_event(device, 1);
276		}
277
278		static TIMER_CALLBACK( mc68328_pwm_transition )
279		{
280		device_t *device = machine.device(MC68328_TAG);
281		mc68328_t* mc68328 = mc68328_get_safe_token( device );
282
283		if(mc68328->regs.pwmw >= mc68328->regs.pwmp \|\| mc68328->regs.pwmw == 0 \|\| mc68328->regs.pwmp == 0)
284		{
285		mc68328->pwm->adjust(attotime::never);
286		return;
287		}
288
289		if(((mc68328->regs.pwmc & PWMC_POL) == 0 && (mc68328->regs.pwmc & PWMC_PIN) != 0) \|\|
290		((mc68328->regs.pwmc & PWMC_POL) != 0 && (mc68328->regs.pwmc & PWMC_PIN) == 0))
291		{
292		UINT32 frequency = 32768 * 506;
293		UINT32 divisor = 4 << (mc68328->regs.pwmc & PWMC_CLKSEL); // ?? Datasheet says 2 <<, but then we're an octave higher than CoPilot.
294		attotime period;
295
296		frequency /= divisor;
297		period = attotime::from_hz(frequency) * (mc68328->regs.pwmp - mc68328->regs.pwmw);
298
299		mc68328->pwm->adjust(period);
300
301		if(mc68328->regs.pwmc & PWMC_IRQEN)
302		{
303		mc68328_set_interrupt_line(device, INT_PWM, 1);
304		}
305		}
306		else
307		{
308		UINT32 frequency = 32768 * 506;
309		UINT32 divisor = 4 << (mc68328->regs.pwmc & PWMC_CLKSEL); // ?? Datasheet says 2 <<, but then we're an octave higher than CoPilot.
310		attotime period;
311
312		frequency /= divisor;
313		period = attotime::from_hz(frequency) * mc68328->regs.pwmw;
314
315		mc68328->pwm->adjust(period);
316		}
317
318		mc68328->regs.pwmc ^= PWMC_PIN;
319
320		if( !mc68328->out_pwm.isnull() )
321		{
322		mc68328->out_pwm( 0, (mc68328->regs.pwmc & PWMC_PIN) ? 1 : 0 );
323		}
324		}
325
326		static TIMER_CALLBACK( mc68328_rtc_tick )
327		{
328		device_t *device = machine.device(MC68328_TAG);
329		mc68328_t* mc68328 = mc68328_get_safe_token( device );
330
331		if(mc68328->regs.rtcctl & RTCCTL_ENABLE)
332		{
333		UINT32 set_int = 0;
334
335		mc68328->regs.hmsr++;
336
337		if(mc68328->regs.rtcienr & RTCINT_SECOND)
338		{
339		set_int = 1;
340		mc68328->regs.rtcisr \|= RTCINT_SECOND;
341		}
342
343		if((mc68328->regs.hmsr & 0x0000003f) == 0x0000003c)
344		{
345		mc68328->regs.hmsr &= 0xffffffc0;
346		mc68328->regs.hmsr += 0x00010000;
347
348		if(mc68328->regs.rtcienr & RTCINT_MINUTE)
349		{
350		set_int = 1;
351		mc68328->regs.rtcisr \|= RTCINT_MINUTE;
352		}
353
354		if((mc68328->regs.hmsr & 0x003f0000) == 0x003c0000)
355		{
356		mc68328->regs.hmsr &= 0xffc0ffff;
357		mc68328->regs.hmsr += 0x0100000;
358
359		if((mc68328->regs.hmsr & 0x1f000000) == 0x18000000)
360		{
361		mc68328->regs.hmsr &= 0xe0ffffff;
362
363		if(mc68328->regs.rtcienr & RTCINT_DAY)
364		{
365		set_int = 1;
366		mc68328->regs.rtcisr \|= RTCINT_DAY;
367		}
368		}
369		}
370
371		if(mc68328->regs.stpwtch != 0x003f)
372		{
373		mc68328->regs.stpwtch--;
374		mc68328->regs.stpwtch &= 0x003f;
375
376		if(mc68328->regs.stpwtch == 0x003f)
377		{
378		if(mc68328->regs.rtcienr & RTCINT_STOPWATCH)
379		{
380		set_int = 1;
381		mc68328->regs.rtcisr \|= RTCINT_STOPWATCH;
382		}
383		}
384		}
385		}
386
387		if(mc68328->regs.hmsr == mc68328->regs.alarm)
388		{
389		if(mc68328->regs.rtcienr & RTCINT_ALARM)
390		{
391		set_int = 1;
392		mc68328->regs.rtcisr \|= RTCINT_STOPWATCH;
393		}
394		}
395
396		if(set_int)
397		{
398		mc68328_set_interrupt_line(device, INT_RTC, 1);
399		}
400		else
401		{
402		mc68328_set_interrupt_line(device, INT_RTC, 0);
403		}
404		}
405		}
406
407		WRITE16_DEVICE_HANDLER( mc68328_w )
408		{
409		mc68328_t* mc68328 = mc68328_get_safe_token( device );
410		UINT32 address = offset << 1;
411		UINT16 temp16[4] = { 0 };
412		UINT32 imr_old = mc68328->regs.imr, imr_diff;
413
414		switch(address)
415		{
416		case 0x000:
417		if( mem_mask & 0x00ff )
418		{
419		verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfff001) = %02x\n", data & 0x00ff);
420		}
421		else
422		{
423		verboselog(space.machine(), 2, "mc68328_w: SCR = %02x\n", (data >> 8) & 0x00ff);
424		}
425		break;
426
427		case 0x100:
428		verboselog(space.machine(), 2, "mc68328_w: GRPBASEA = %04x\n", data);
429		mc68328->regs.grpbasea = data;
430		break;
431
432		case 0x102:
433		verboselog(space.machine(), 2, "mc68328_w: GRPBASEB = %04x\n", data);
434		mc68328->regs.grpbaseb = data;
435		break;
436
437		case 0x104:
438		verboselog(space.machine(), 2, "mc68328_w: GRPBASEC = %04x\n", data);
439		mc68328->regs.grpbasec = data;
440		break;
441
442		case 0x106:
443		verboselog(space.machine(), 2, "mc68328_w: GRPBASED = %04x\n", data);
444		mc68328->regs.grpbased = data;
445		break;
446
447		case 0x108:
448		verboselog(space.machine(), 2, "mc68328_w: GRPMASKA = %04x\n", data);
449		mc68328->regs.grpmaska = data;
450		break;
451
452		case 0x10a:
453		verboselog(space.machine(), 2, "mc68328_w: GRPMASKB = %04x\n", data);
454		mc68328->regs.grpmaskb = data;
455		break;
456
457		case 0x10c:
458		verboselog(space.machine(), 2, "mc68328_w: GRPMASKC = %04x\n", data);
459		mc68328->regs.grpmaskc = data;
460		break;
461
462		case 0x10e:
463		verboselog(space.machine(), 2, "mc68328_w: GRPMASKD = %04x\n", data);
464		mc68328->regs.grpmaskd = data;
465		break;
466
467		case 0x110:
468		verboselog(space.machine(), 5, "mc68328_w: CSA0(0) = %04x\n", data);
469		mc68328->regs.csa0 &= 0xffff0000 \| (~mem_mask);
470		mc68328->regs.csa0 \|= data & mem_mask;
471		break;
472
473		case 0x112:
474		verboselog(space.machine(), 5, "mc68328_w: CSA0(16) = %04x\n", data);
475		mc68328->regs.csa0 &= ~(mem_mask << 16);
476		mc68328->regs.csa0 \|= (data & mem_mask) << 16;
477		break;
478
479		case 0x114:
480		verboselog(space.machine(), 5, "mc68328_w: CSA1(0) = %04x\n", data);
481		mc68328->regs.csa1 &= 0xffff0000 \| (~mem_mask);
482		mc68328->regs.csa1 \|= data & mem_mask;
483		break;
484
485		case 0x116:
486		verboselog(space.machine(), 5, "mc68328_w: CSA1(16) = %04x\n", data);
487		mc68328->regs.csa1 &= ~(mem_mask << 16);
488		mc68328->regs.csa1 \|= (data & mem_mask) << 16;
489		break;
490
491		case 0x118:
492		verboselog(space.machine(), 5, "mc68328_w: CSA2(0) = %04x\n", data);
493		mc68328->regs.csa2 &= 0xffff0000 \| (~mem_mask);
494		mc68328->regs.csa2 \|= data & mem_mask;
495		break;
496
497		case 0x11a:
498		verboselog(space.machine(), 5, "mc68328_w: CSA2(16) = %04x\n", data);
499		mc68328->regs.csa2 &= ~(mem_mask << 16);
500		mc68328->regs.csa2 \|= (data & mem_mask) << 16;
501		break;
502
503		case 0x11c:
504		verboselog(space.machine(), 5, "mc68328_w: CSA3(0) = %04x\n", data);
505		mc68328->regs.csa3 &= 0xffff0000 \| (~mem_mask);
506		mc68328->regs.csa3 \|= data & mem_mask;
507		break;
508
509		case 0x11e:
510		verboselog(space.machine(), 5, "mc68328_w: CSA3(16) = %04x\n", data);
511		mc68328->regs.csa3 &= ~(mem_mask << 16);
512		mc68328->regs.csa3 \|= (data & mem_mask) << 16;
513		break;
514
515		case 0x120:
516		verboselog(space.machine(), 5, "mc68328_w: CSB0(0) = %04x\n", data);
517		mc68328->regs.csb0 &= 0xffff0000 \| (~mem_mask);
518		mc68328->regs.csb0 \|= data & mem_mask;
519		break;
520
521		case 0x122:
522		verboselog(space.machine(), 5, "mc68328_w: CSB0(16) = %04x\n", data);
523		mc68328->regs.csb0 &= ~(mem_mask << 16);
524		mc68328->regs.csb0 \|= (data & mem_mask) << 16;
525		break;
526
527		case 0x124:
528		verboselog(space.machine(), 5, "mc68328_w: CSB1(0) = %04x\n", data);
529		mc68328->regs.csb1 &= 0xffff0000 \| (~mem_mask);
530		mc68328->regs.csb1 \|= data & mem_mask;
531		break;
532
533		case 0x126:
534		verboselog(space.machine(), 5, "mc68328_w: CSB1(16) = %04x\n", data);
535		mc68328->regs.csb1 &= ~(mem_mask << 16);
536		mc68328->regs.csb1 \|= (data & mem_mask) << 16;
537		break;
538
539		case 0x128:
540		verboselog(space.machine(), 5, "mc68328_w: CSB2(0) = %04x\n", data);
541		mc68328->regs.csb2 &= 0xffff0000 \| (~mem_mask);
542		mc68328->regs.csb2 \|= data & mem_mask;
543		break;
544
545		case 0x12a:
546		verboselog(space.machine(), 5, "mc68328_w: CSB2(16) = %04x\n", data);
547		mc68328->regs.csb2 &= ~(mem_mask << 16);
548		mc68328->regs.csb2 \|= (data & mem_mask) << 16;
549		break;
550
551		case 0x12c:
552		verboselog(space.machine(), 5, "mc68328_w: CSB3(0) = %04x\n", data);
553		mc68328->regs.csb3 &= 0xffff0000 \| (~mem_mask);
554		mc68328->regs.csb3 \|= data & mem_mask;
555		break;
556
557		case 0x12e:
558		verboselog(space.machine(), 5, "mc68328_w: CSB3(16) = %04x\n", data);
559		mc68328->regs.csb3 &= ~(mem_mask << 16);
560		mc68328->regs.csb3 \|= (data & mem_mask) << 16;
561		break;
562
563		case 0x130:
564		verboselog(space.machine(), 5, "mc68328_w: CSC0(0) = %04x\n", data);
565		mc68328->regs.csc0 &= 0xffff0000 \| (~mem_mask);
566		mc68328->regs.csc0 \|= data & mem_mask;
567		break;
568
569		case 0x132:
570		verboselog(space.machine(), 5, "mc68328_w: CSC0(16) = %04x\n", data);
571		mc68328->regs.csc0 &= ~(mem_mask << 16);
572		mc68328->regs.csc0 \|= (data & mem_mask) << 16;
573		break;
574
575		case 0x134:
576		verboselog(space.machine(), 5, "mc68328_w: CSC1(0) = %04x\n", data);
577		mc68328->regs.csc1 &= 0xffff0000 \| (~mem_mask);
578		mc68328->regs.csc1 \|= data & mem_mask;
579		break;
580
581		case 0x136:
582		verboselog(space.machine(), 5, "mc68328_w: CSC1(16) = %04x\n", data);
583		mc68328->regs.csc1 &= ~(mem_mask << 16);
584		mc68328->regs.csc1 \|= (data & mem_mask) << 16;
585		break;
586
587		case 0x138:
588		verboselog(space.machine(), 5, "mc68328_w: CSC2(0) = %04x\n", data);
589		mc68328->regs.csc2 &= 0xffff0000 \| (~mem_mask);
590		mc68328->regs.csc2 \|= data & mem_mask;
591		break;
592
593		case 0x13a:
594		verboselog(space.machine(), 5, "mc68328_w: CSC2(16) = %04x\n", data);
595		mc68328->regs.csc2 &= ~(mem_mask << 16);
596		mc68328->regs.csc2 \|= (data & mem_mask) << 16;
597		break;
598
599		case 0x13c:
600		verboselog(space.machine(), 5, "mc68328_w: CSC3(0) = %04x\n", data);
601		mc68328->regs.csc3 &= 0xffff0000 \| (~mem_mask);
602		mc68328->regs.csc3 \|= data & mem_mask;
603		break;
604
605		case 0x13e:
606		verboselog(space.machine(), 5, "mc68328_w: CSC3(16) = %04x\n", data);
607		mc68328->regs.csc3 &= ~(mem_mask << 16);
608		mc68328->regs.csc3 \|= (data & mem_mask) << 16;
609		break;
610
611		case 0x140:
612		verboselog(space.machine(), 5, "mc68328_w: CSD0(0) = %04x\n", data);
613		mc68328->regs.csd0 &= 0xffff0000 \| (~mem_mask);
614		mc68328->regs.csd0 \|= data & mem_mask;
615		break;
616
617		case 0x142:
618		verboselog(space.machine(), 5, "mc68328_w: CSD0(16) = %04x\n", data);
619		mc68328->regs.csd0 &= ~(mem_mask << 16);
620		mc68328->regs.csd0 \|= (data & mem_mask) << 16;
621		break;
622
623		case 0x144:
624		verboselog(space.machine(), 5, "mc68328_w: CSD1(0) = %04x\n", data);
625		mc68328->regs.csd1 &= 0xffff0000 \| (~mem_mask);
626		mc68328->regs.csd1 \|= data & mem_mask;
627		break;
628
629		case 0x146:
630		verboselog(space.machine(), 5, "mc68328_w: CSD1(16) = %04x\n", data);
631		mc68328->regs.csd1 &= ~(mem_mask << 16);
632		mc68328->regs.csd1 \|= (data & mem_mask) << 16;
633		break;
634
635		case 0x148:
636		verboselog(space.machine(), 5, "mc68328_w: CSD2(0) = %04x\n", data);
637		mc68328->regs.csd2 &= 0xffff0000 \| (~mem_mask);
638		mc68328->regs.csd2 \|= data & mem_mask;
639		break;
640
641		case 0x14a:
642		verboselog(space.machine(), 5, "mc68328_w: CSD2(16) = %04x\n", data);
643		mc68328->regs.csd2 &= ~(mem_mask << 16);
644		mc68328->regs.csd2 \|= (data & mem_mask) << 16;
645		break;
646
647		case 0x14c:
648		verboselog(space.machine(), 5, "mc68328_w: CSD3(0) = %04x\n", data);
649		mc68328->regs.csd3 &= 0xffff0000 \| (~mem_mask);
650		mc68328->regs.csd3 \|= data & mem_mask;
651		break;
652
653		case 0x14e:
654		verboselog(space.machine(), 5, "mc68328_w: CSD3(16) = %04x\n", data);
655		mc68328->regs.csd3 &= ~(mem_mask << 16);
656		mc68328->regs.csd3 \|= (data & mem_mask) << 16;
657		break;
658
659		case 0x200:
660		verboselog(space.machine(), 2, "mc68328_w: PLLCR = %04x\n", data);
661		mc68328->regs.pllcr = data;
662		break;
663
664		case 0x202:
665		verboselog(space.machine(), 2, "mc68328_w: PLLFSR = %04x\n", data);
666		mc68328->regs.pllfsr = data;
667		break;
668
669		case 0x206:
670		if( mem_mask & 0x00ff )
671		{
672		verboselog(space.machine(), 2, "mc68328_w: PCTLR = %02x\n", data & 0x00ff);
673		mc68328->regs.pctlr = data & 0x00ff;
674		}
675		else
676		{
677		verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfff206) = %02x\n", (data >> 8) & 0x00ff);
678		}
679		break;
680
681		case 0x300:
682		if( mem_mask & 0x00ff )
683		{
684		verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfff301) = %02x\n", data & 0x00ff);
685		}
686		else
687		{
688		verboselog(space.machine(), 2, "mc68328_w: IVR = %02x\n", (data >> 8) & 0x00ff);
689		mc68328->regs.ivr = (data >> 8) & 0x00ff;
690		}
691		break;
692
693		case 0x302:
694		verboselog(space.machine(), 2, "mc68328_w: ICR = %04x\n", data);
695		mc68328->regs.icr = data;
696		break;
697
698		case 0x304:
699		verboselog(space.machine(), 2, "mc68328_w: IMR(16) = %04x\n", data);
700		mc68328->regs.imr &= ~(mem_mask << 16);
701		mc68328->regs.imr \|= (data & mem_mask) << 16;
702		mc68328->regs.isr &= ~((data & mem_mask) << 16);
703
704		imr_diff = imr_old ^ mc68328->regs.imr;
705		mc68328_set_interrupt_line(device, imr_diff, 0);
706		break;
707
708		case 0x306:
709		verboselog(space.machine(), 2, "mc68328_w: IMR(0) = %04x\n", data);
710		mc68328->regs.imr &= 0xffff0000 \| (~mem_mask);
711		mc68328->regs.imr \|= data & mem_mask;
712		mc68328->regs.isr &= ~(data & mem_mask);
713
714		imr_diff = imr_old ^ mc68328->regs.imr;
715		mc68328_set_interrupt_line(device, imr_diff, 0);
716		break;
717
718		case 0x308:
719		{
720		verboselog(space.machine(), 2, "mc68328_w: IWR(16) = %04x\n", data);
721		mc68328->regs.iwr &= ~(mem_mask << 16);
722		mc68328->regs.iwr \|= (data & mem_mask) << 16;
723		}
724		break;
725
726		case 0x30a:
727		verboselog(space.machine(), 2, "mc68328_w: IWR(0) = %04x\n", data);
728		mc68328->regs.iwr &= 0xffff0000 \| (~mem_mask);
729		mc68328->regs.iwr \|= data & mem_mask;
730		break;
731
732		case 0x30c:
733		verboselog(space.machine(), 2, "mc68328_w: ISR(16) = %04x\n", data);
734		// Clear edge-triggered IRQ1
735		if((mc68328->regs.icr & ICR_ET1) == ICR_ET1 && (data & INT_IRQ1_SHIFT) == INT_IRQ1_SHIFT)
736		{
737		mc68328->regs.isr &= ~INT_IRQ1;
738		}
739
740		// Clear edge-triggered IRQ2
741		if((mc68328->regs.icr & ICR_ET2) == ICR_ET2 && (data & INT_IRQ2_SHIFT) == INT_IRQ2_SHIFT)
742		{
743		mc68328->regs.isr &= ~INT_IRQ2;
744		}
745
746		// Clear edge-triggered IRQ3
747		if((mc68328->regs.icr & ICR_ET3) == ICR_ET3 && (data & INT_IRQ3_SHIFT) == INT_IRQ3_SHIFT)
748		{
749		mc68328->regs.isr &= ~INT_IRQ3;
750		}
751
752		// Clear edge-triggered IRQ6
753		if((mc68328->regs.icr & ICR_ET6) == ICR_ET6 && (data & INT_IRQ6_SHIFT) == INT_IRQ6_SHIFT)
754		{
755		mc68328->regs.isr &= ~INT_IRQ6;
756		}
757
758		// Clear edge-triggered IRQ7
759		if((data & INT_IRQ7_SHIFT) == INT_IRQ7_SHIFT)
760		{
761		mc68328->regs.isr &= ~INT_IRQ7;
762		}
763		break;
764
765		case 0x30e:
766		verboselog(space.machine(), 2, "mc68328_w: ISR(0) = %04x (Ignored)\n", data);
767		break;
768
769		case 0x310:
770		verboselog(space.machine(), 2, "mc68328_w: IPR(16) = %04x (Ignored)\n");
771		break;
772
773		case 0x312:
774		verboselog(space.machine(), 2, "mc68328_w: IPR(0) = %04x (Ignored)\n");
775		break;
776
777		case 0x400:
778		if( mem_mask & 0x00ff )
779		{
780		verboselog(space.machine(), 2, "mc68328_w: PADATA = %02x\n", data & 0x00ff);
781		mc68328->regs.padata = data & 0x00ff;
782		if(!mc68328->out_port_a.isnull())
783		{
784		mc68328->out_port_a( 0, data & 0x00ff );
785		}
786		}
787		else
788		{
789		verboselog(space.machine(), 2, "mc68328_w: PADIR = %02x\n", (data >> 8) & 0x00ff);
790		mc68328->regs.padir = (data >> 8) & 0x00ff;
791		}
792		break;
793
794		case 0x402:
795		if( mem_mask & 0x00ff )
796		{
797		verboselog(space.machine(), 2, "mc68328_w: PASEL = %02x\n", data & 0x00ff);
798		mc68328->regs.pasel = data & 0x00ff;
799		}
800		else
801		{
802		verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfff402) = %02x\n", (data >> 8) & 0x00ff);
803		}
804		break;
805
806		case 0x408:
807		if( mem_mask & 0x00ff )
808		{
809		verboselog(space.machine(), 2, "mc68328_w: PBDATA = %02x\n", data & 0x00ff);
810		mc68328->regs.pbdata = data & 0x00ff;
811		if(!mc68328->out_port_b.isnull())
812		{
813		mc68328->out_port_b( 0, data & 0x00ff );
814		}
815		}
816		else
817		{
818		verboselog(space.machine(), 2, "mc68328_w: PBDIR = %02x\n", (data >> 8) & 0x00ff);
819		mc68328->regs.pbdir = (data >> 8) & 0x00ff;
820		}
821		break;
822
823		case 0x40a:
824		if( mem_mask & 0x00ff )
825		{
826		verboselog(space.machine(), 2, "mc68328_w: PBSEL = %02x\n", data & 0x00ff);
827		mc68328->regs.pbsel = data & 0x00ff;
828		}
829		else
830		{
831		verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfff40a) = %02x\n", (data >> 8) & 0x00ff);
832		}
833		break;
834
835		case 0x410:
836		if( mem_mask & 0x00ff )
837		{
838		verboselog(space.machine(), 2, "mc68328_w: PCDATA = %02x\n", data & 0x00ff);
839		mc68328->regs.pcdata = data & 0x00ff;
840		if(!mc68328->out_port_c.isnull())
841		{
842		mc68328->out_port_c( 0, data & 0x00ff );
843		}
844		}
845		else
846		{
847		verboselog(space.machine(), 2, "mc68328_w: PCDIR = %02x\n", (data >> 8) & 0x00ff);
848		mc68328->regs.pcdir = (data >> 8) & 0x00ff;
849		}
850		break;
851
852		case 0x412:
853		if( mem_mask & 0x00ff )
854		{
855		verboselog(space.machine(), 2, "mc68328_w: PCSEL = %02x\n", data & 0x00ff);
856		mc68328->regs.pcsel = data & 0x00ff;
857		}
858		else
859		{
860		verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfff412) = %02x\n", (data >> 8) & 0x00ff);
861		}
862		break;
863
864		case 0x418:
865		if( mem_mask & 0x00ff )
866		{
867		verboselog(space.machine(), 2, "mc68328_w: PDDATA = %02x\n", data & 0x00ff);
868
869		mc68328->regs.pddataedge &= ~(data & 0x00ff);
870		mc68328_poll_port_d_interrupts(device);
871		}
872		else
873		{
874		verboselog(space.machine(), 2, "mc68328_w: PDDIR = %02x\n", (data >> 8) & 0x00ff);
875		mc68328->regs.pddir = (data >> 8) & 0x00ff;
876		}
877		break;
878
879		case 0x41a:
880		if( mem_mask & 0x00ff )
881		{
882		verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfff41b) = %02x\n", data & 0x00ff);
883		}
884		else
885		{
886		verboselog(space.machine(), 2, "mc68328_w: PDPUEN = %02x\n", (data >> 8) & 0x00ff);
887		mc68328->regs.pdpuen = (data >> 8) & 0x00ff;
888		}
889		break;
890
891		case 0x41c:
892		if( mem_mask & 0x00ff )
893		{
894		verboselog(space.machine(), 2, "mc68328_w: PDIRQEN = %02x\n", data & 0x00ff);
895		mc68328->regs.pdirqen = data & 0x00ff;
896
897		mc68328_poll_port_d_interrupts(device);
898		}
899		else
900		{
901		verboselog(space.machine(), 2, "mc68328_w: PDPOL = %02x\n", (data >> 8) & 0x00ff);
902		mc68328->regs.pdpol = (data >> 8) & 0x00ff;
903		}
904		break;
905
906		case 0x41e:
907		if( mem_mask & 0x00ff )
908		{
909		verboselog(space.machine(), 2, "mc68328_w: PDIRQEDGE = %02x\n", data & 0x00ff);
910		mc68328->regs.pdirqedge = data & 0x00ff;
911		}
912		else
913		{
914		verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfff41e) = %02x\n", (data >> 8) & 0x00ff);
915		}
916		break;
917
918		case 0x420:
919		if( mem_mask & 0x00ff )
920		{
921		verboselog(space.machine(), 2, "mc68328_w: PEDATA = %02x\n", data & 0x00ff);
922		mc68328->regs.pedata = data & 0x00ff;
923		if(!mc68328->out_port_e.isnull())
924		{
925		mc68328->out_port_e( 0, data & 0x00ff );
926		}
927		}
928		else
929		{
930		verboselog(space.machine(), 2, "mc68328_w: PEDIR = %02x\n", (data >> 8) & 0x00ff);
931		mc68328->regs.pedir = (data >> 8) & 0x00ff;
932		}
933		break;
934
935		case 0x422:
936		if( mem_mask & 0x00ff )
937		{
938		verboselog(space.machine(), 2, "mc68328_w: PESEL = %02x\n", data & 0x00ff);
939		mc68328->regs.pesel = data & 0x00ff;
940		}
941		else
942		{
943		verboselog(space.machine(), 2, "mc68328_w: PEPUEN = %02x\n", (data >> 8) & 0x00ff);
944		mc68328->regs.pepuen = (data >> 8) & 0x00ff;
945		mc68328->regs.pedata \|= mc68328->regs.pepuen;
946		}
947		break;
948
949		case 0x428:
950		if( mem_mask & 0x00ff )
951		{
952		verboselog(space.machine(), 2, "mc68328_w: PFDATA = %02x\n", data & 0x00ff);
953		mc68328->regs.pfdata = data & 0x00ff;
954		if(!mc68328->out_port_f.isnull())
955		{
956		mc68328->out_port_f( 0, data & 0x00ff );
957		}
958		}
959		else
960		{
961		verboselog(space.machine(), 2, "mc68328_w: PFDIR = %02x\n", (data >> 8) & 0x00ff);
962		mc68328->regs.pfdir = (data >> 8) & 0x00ff;
963		}
964		break;
965
966		case 0x42a:
967		if( mem_mask & 0x00ff )
968		{
969		verboselog(space.machine(), 2, "mc68328_w: PFSEL = %02x\n", data & 0x00ff);
970		mc68328->regs.pfsel = data & 0x00ff;
971		}
972		else
973		{
974		verboselog(space.machine(), 2, "mc68328_w: PFPUEN = %02x\n", (data >> 8) & 0x00ff);
975		mc68328->regs.pfpuen = (data >> 8) & 0x00ff;
976		}
977		break;
978
979		case 0x430:
980		if( mem_mask & 0x00ff )
981		{
982		verboselog(space.machine(), 2, "mc68328_w: PGDATA = %02x\n", data & 0x00ff);
983		mc68328->regs.pgdata = data & 0x00ff;
984		if(!mc68328->out_port_g.isnull())
985		{
986		mc68328->out_port_g( 0, data & 0x00ff );
987		}
988		}
989		else
990		{
991		verboselog(space.machine(), 2, "mc68328_w: PGDIR = %02x\n", (data >> 8) & 0x00ff);
992		mc68328->regs.pgdir = (data >> 8) & 0x00ff;
993		}
994		break;
995
996		case 0x432:
997		if( mem_mask & 0x00ff )
998		{
999		verboselog(space.machine(), 2, "mc68328_w: PGSEL = %02x\n", data & 0x00ff);
1000		mc68328->regs.pgsel = data & 0x00ff;
1001		}
1002		else
1003		{
1004		verboselog(space.machine(), 2, "mc68328_w: PGPUEN = %02x\n", (data >> 8) & 0x00ff);
1005		mc68328->regs.pgpuen = (data >> 8) & 0x00ff;
1006		}
1007		break;
1008
1009		case 0x438:
1010		if( mem_mask & 0x00ff )
1011		{
1012		verboselog(space.machine(), 2, "mc68328_w: PJDATA = %02x\n", data & 0x00ff);
1013		mc68328->regs.pjdata = data & 0x00ff;
1014		if(!mc68328->out_port_j.isnull())
1015		{
1016		mc68328->out_port_j( 0, data & 0x00ff );
1017		}
1018		}
1019		else
1020		{
1021		verboselog(space.machine(), 2, "mc68328_w: PJDIR = %02x\n", (data >> 8) & 0x00ff);
1022		mc68328->regs.pjdir = (data >> 8) & 0x00ff;
1023		}
1024		break;
1025
1026		case 0x43a:
1027		if( mem_mask & 0x00ff )
1028		{
1029		verboselog(space.machine(), 2, "mc68328_w: PJSEL = %02x\n", data & 0x00ff);
1030		mc68328->regs.pjsel = data & 0x00ff;
1031		}
1032		else
1033		{
1034		verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfff43a) = %02x\n", (data >> 8) & 0x00ff);
1035		}
1036		break;
1037
1038		case 0x440:
1039		if( mem_mask & 0x00ff )
1040		{
1041		verboselog(space.machine(), 2, "mc68328_w: PKDATA = %02x\n", data & 0x00ff);
1042		mc68328->regs.pkdata = data & 0x00ff;
1043		if(!mc68328->out_port_k.isnull())
1044		{
1045		mc68328->out_port_k( 0, data & 0x00ff );
1046		}
1047		}
1048		else
1049		{
1050		verboselog(space.machine(), 2, "mc68328_w: PKDIR = %02x\n", (data >> 8) & 0x00ff);
1051		mc68328->regs.pkdir = (data >> 8) & 0x00ff;
1052		}
1053		break;
1054
1055		case 0x442:
1056		if( mem_mask & 0x00ff )
1057		{
1058		verboselog(space.machine(), 2, "mc68328_w: PKSEL = %02x\n", data & 0x00ff);
1059		mc68328->regs.pksel = data & 0x00ff;
1060		}
1061		else
1062		{
1063		verboselog(space.machine(), 2, "mc68328_w: PKPUEN = %02x\n", (data >> 8) & 0x00ff);
1064		mc68328->regs.pgpuen = (data >> 8) & 0x00ff;
1065		}
1066		break;
1067
1068		case 0x448:
1069		if( mem_mask & 0x00ff )
1070		{
1071		verboselog(space.machine(), 2, "mc68328_w: PMDATA = %02x\n", data & 0x00ff);
1072		mc68328->regs.pmdata = data & 0x00ff;
1073		if(!mc68328->out_port_m.isnull())
1074		{
1075		mc68328->out_port_m( 0, data & 0x00ff );
1076		}
1077		}
1078		else
1079		{
1080		verboselog(space.machine(), 2, "mc68328_w: PMDIR = %02x\n", (data >> 8) & 0x00ff);
1081		mc68328->regs.pmdir = (data >> 8) & 0x00ff;
1082		}
1083		break;
1084
1085		case 0x44a:
1086		if( mem_mask & 0x00ff )
1087		{
1088		verboselog(space.machine(), 2, "mc68328_w: PMSEL = %02x\n", data & 0x00ff);
1089		mc68328->regs.pmsel = data & 0x00ff;
1090		}
1091		else
1092		{
1093		verboselog(space.machine(), 2, "mc68328_w: PMPUEN = %02x\n", (data >> 8) & 0x00ff);
1094		mc68328->regs.pmpuen = (data >> 8) & 0x00ff;
1095		}
1096		break;
1097
1098		case 0x500:
1099		verboselog(space.machine(), 2, "mc68328_w: PWMC = %04x\n", data);
1100
1101		mc68328->regs.pwmc = data;
1102
1103		if(mc68328->regs.pwmc & PWMC_PWMIRQ)
1104		{
1105		mc68328_set_interrupt_line(device, INT_PWM, 1);
1106		}
1107
1108		mc68328->regs.pwmc &= ~PWMC_LOAD;
1109
1110		if((mc68328->regs.pwmc & PWMC_PWMEN) != 0 && mc68328->regs.pwmw != 0 && mc68328->regs.pwmp != 0)
1111		{
1112		UINT32 frequency = 32768 * 506;
1113		UINT32 divisor = 4 << (mc68328->regs.pwmc & PWMC_CLKSEL); // ?? Datasheet says 2 <<, but then we're an octave higher than CoPilot.
1114		attotime period;
1115		frequency /= divisor;
1116		period = attotime::from_hz(frequency) * mc68328->regs.pwmw;
1117		mc68328->pwm->adjust(period);
1118		if(mc68328->regs.pwmc & PWMC_IRQEN)
1119		{
1120		mc68328_set_interrupt_line(device, INT_PWM, 1);
1121		}
1122		mc68328->regs.pwmc ^= PWMC_PIN;
1123		}
1124		else
1125		{
1126		mc68328->pwm->adjust(attotime::never);
1127		}
1128		break;
1129
1130		case 0x502:
1131		verboselog(space.machine(), 2, "mc68328_w: PWMP = %04x\n", data);
1132		mc68328->regs.pwmp = data;
1133		break;
1134
1135		case 0x504:
1136		verboselog(space.machine(), 2, "mc68328_w: PWMW = %04x\n", data);
1137		mc68328->regs.pwmw = data;
1138		break;
1139
1140		case 0x506:
1141		verboselog(space.machine(), 2, "mc68328_w: PWMCNT = %04x\n", data);
1142		mc68328->regs.pwmcnt = 0;
1143		break;
1144
1145		case 0x600:
1146		verboselog(space.machine(), 2, "mc68328_w: TCTL1 = %04x\n", data);
1147		temp16[0] = mc68328->regs.tctl[0];
1148		mc68328->regs.tctl[0] = data;
1149		if((temp16[0] & TCTL_TEN) == (mc68328->regs.tctl[0] & TCTL_TEN))
1150		{
1151		mc68328_maybe_start_timer(device, 0, 0);
1152		}
1153		else if((temp16[0] & TCTL_TEN) != TCTL_TEN_ENABLE && (mc68328->regs.tctl[0] & TCTL_TEN) == TCTL_TEN_ENABLE)
1154		{
1155		mc68328_maybe_start_timer(device, 0, 1);
1156		}
1157		break;
1158
1159		case 0x602:
1160		verboselog(space.machine(), 2, "mc68328_w: TPRER1 = %04x\n", data);
1161		mc68328->regs.tprer[0] = data;
1162		mc68328_maybe_start_timer(device, 0, 0);
1163		break;
1164
1165		case 0x604:
1166		verboselog(space.machine(), 2, "mc68328_w: TCMP1 = %04x\n", data);
1167		mc68328->regs.tcmp[0] = data;
1168		mc68328_maybe_start_timer(device, 0, 0);
1169		break;
1170
1171		case 0x606:
1172		verboselog(space.machine(), 2, "mc68328_w: TCR1 = %04x (Ignored)\n", data);
1173		break;
1174
1175		case 0x608:
1176		verboselog(space.machine(), 2, "mc68328_w: TCN1 = %04x (Ignored)\n", data);
1177		break;
1178
1179		case 0x60a:
1180		verboselog(space.machine(), 5, "mc68328_w: TSTAT1 = %04x\n", data);
1181		mc68328->regs.tstat[0] &= ~mc68328->regs.tclear[0];
1182		if(!(mc68328->regs.tstat[0] & TSTAT_COMP))
1183		{
1184		mc68328_set_interrupt_line(device, INT_TIMER1, 0);
1185		}
1186		break;
1187
1188		case 0x60c:
1189		verboselog(space.machine(), 2, "mc68328_w: TCTL2 = %04x\n", data);
1190		temp16[0] = mc68328->regs.tctl[1];
1191		mc68328->regs.tctl[1] = data;
1192		if((temp16[0] & TCTL_TEN) == (mc68328->regs.tctl[1] & TCTL_TEN))
1193		{
1194		mc68328_maybe_start_timer(device, 1, 0);
1195		}
1196		else if((temp16[0] & TCTL_TEN) != TCTL_TEN_ENABLE && (mc68328->regs.tctl[1] & TCTL_TEN) == TCTL_TEN_ENABLE)
1197		{
1198		mc68328_maybe_start_timer(device, 1, 1);
1199		}
1200		break;
1201
1202		case 0x60e:
1203		verboselog(space.machine(), 2, "mc68328_w: TPRER2 = %04x\n", data);
1204		mc68328->regs.tprer[1] = data;
1205		mc68328_maybe_start_timer(device, 1, 0);
1206		break;
1207
1208		case 0x610:
1209		verboselog(space.machine(), 2, "mc68328_w: TCMP2 = %04x\n", data);
1210		mc68328->regs.tcmp[1] = data;
1211		mc68328_maybe_start_timer(device, 1, 0);
1212		break;
1213
1214		case 0x612:
1215		verboselog(space.machine(), 2, "mc68328_w: TCR2 = %04x (Ignored)\n", data);
1216		break;
1217
1218		case 0x614:
1219		verboselog(space.machine(), 2, "mc68328_w: TCN2 = %04x (Ignored)\n", data);
1220		break;
1221
1222		case 0x616:
1223		verboselog(space.machine(), 2, "mc68328_w: TSTAT2 = %04x\n", data);
1224		mc68328->regs.tstat[1] &= ~mc68328->regs.tclear[1];
1225		if(!(mc68328->regs.tstat[1] & TSTAT_COMP))
1226		{
1227		mc68328_set_interrupt_line(device, INT_TIMER2, 0);
1228		}
1229		break;
1230
1231		case 0x618:
1232		verboselog(space.machine(), 2, "mc68328_w: WCTLR = %04x\n", data);
1233		mc68328->regs.wctlr = data;
1234		break;
1235
1236		case 0x61a:
1237		verboselog(space.machine(), 2, "mc68328_w: WCMPR = %04x\n", data);
1238		mc68328->regs.wcmpr = data;
1239		break;
1240
1241		case 0x61c:
1242		verboselog(space.machine(), 2, "mc68328_w: WCN = %04x (Ignored)\n", data);
1243		break;
1244
1245		case 0x700:
1246		verboselog(space.machine(), 2, "mc68328_w: SPISR = %04x\n", data);
1247		mc68328->regs.spisr = data;
1248		break;
1249
1250		case 0x800:
1251		verboselog(space.machine(), 2, "mc68328_w: SPIMDATA = %04x\n", data);
1252		if(!mc68328->out_spim.isnull())
1253		{
1254		mc68328->out_spim( 0, data, 0xffff );
1255		}
1256		else
1257		{
1258		mc68328->regs.spimdata = data;
1259		}
1260		break;
1261
1262		case 0x802:
1263		verboselog(space.machine(), 2, "mc68328_w: SPIMCONT = %04x\n", data);
1264		verboselog(space.machine(), 3, " Count = %d\n", data & SPIM_CLOCK_COUNT);
1265		verboselog(space.machine(), 3, " Polarity = %s\n", (data & SPIM_POL) ? "Inverted" : "Active-high");
1266		verboselog(space.machine(), 3, " Phase = %s\n", (data & SPIM_PHA) ? "Opposite" : "Normal");
1267		verboselog(space.machine(), 3, " IRQ Enable = %s\n", (data & SPIM_IRQEN) ? "Enable" : "Disable");
1268		verboselog(space.machine(), 3, " IRQ Pending = %s\n", (data & SPIM_SPIMIRQ) ? "Yes" : "No");
1269		verboselog(space.machine(), 3, " Exchange = %s\n", (data & SPIM_XCH) ? "Initiate" : "Idle");
1270		verboselog(space.machine(), 3, " SPIM Enable = %s\n", (data & SPIM_SPMEN) ? "Enable" : "Disable");
1271		verboselog(space.machine(), 3, " Data Rate = Divide By %d\n", 1 << ((((data & SPIM_RATE) >> 13) & 0x0007) + 2) );
1272		mc68328->regs.spimcont = data;
1273		// $$HACK$$ We should probably emulate the ADS7843 A/D device properly.
1274		if(data & SPIM_XCH)
1275		{
1276		mc68328->regs.spimcont &= ~SPIM_XCH;
1277		if(mc68328->iface->spim_xch_trigger)
1278		{
1279		(mc68328->iface->spim_xch_trigger)( device );
1280		}
1281		if(data & SPIM_IRQEN)
1282		{
1283		mc68328->regs.spimcont \|= SPIM_SPIMIRQ;
1284		verboselog(space.machine(), 3, "Triggering SPIM Interrupt\n" );
1285		mc68328_set_interrupt_line(device, INT_SPIM, 1);
1286		}
1287		}
1288		if(!(data & SPIM_IRQEN))
1289		{
1290		mc68328_set_interrupt_line(device, INT_SPIM, 0);
1291		}
1292		break;
1293
1294		case 0x900:
1295		verboselog(space.machine(), 2, "mc68328_w: USTCNT = %04x\n", data);
1296		mc68328->regs.ustcnt = data;
1297		break;
1298
1299		case 0x902:
1300		verboselog(space.machine(), 2, "mc68328_w: UBAUD = %04x\n", data);
1301		mc68328->regs.ubaud = data;
1302		break;
1303
1304		case 0x904:
1305		verboselog(space.machine(), 2, "mc68328_w: URX = %04x\n", data);
1306		break;
1307
1308		case 0x906:
1309		verboselog(space.machine(), 2, "mc68328_w: UTX = %04x\n", data);
1310		break;
1311
1312		case 0x908:
1313		verboselog(space.machine(), 2, "mc68328_w: UMISC = %04x\n", data);
1314		mc68328->regs.umisc = data;
1315		break;
1316
1317		case 0xa00:
1318		verboselog(space.machine(), 2, "mc68328_w: LSSA(16) = %04x\n", data);
1319		mc68328->regs.lssa &= ~(mem_mask << 16);
1320		mc68328->regs.lssa \|= (data & mem_mask) << 16;
1321		verboselog(space.machine(), 3, " Address: %08x\n", mc68328->regs.lssa);
1322		break;
1323
1324		case 0xa02:
1325		verboselog(space.machine(), 2, "mc68328_w: LSSA(0) = %04x\n", data);
1326		mc68328->regs.lssa &= 0xffff0000 \| (~mem_mask);
1327		mc68328->regs.lssa \|= data & mem_mask;
1328		verboselog(space.machine(), 3, " Address: %08x\n", mc68328->regs.lssa);
1329		break;
1330
1331		case 0xa04:
1332		if( mem_mask & 0x00ff )
1333		{
1334		verboselog(space.machine(), 2, "mc68328_w: LVPW = %02x\n", data & 0x00ff);
1335		mc68328->regs.lvpw = data & 0x00ff;
1336		verboselog(space.machine(), 3, " Page Width: %d or %d\n", (mc68328->regs.lvpw + 1) * ((mc68328->regs.lpicf & 0x01) ? 8 : 16));
1337		}
1338		else
1339		{
1340		verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfffa04) = %02x\n", (data >> 8) & 0x00ff);
1341		}
1342		break;
1343
1344		case 0xa08:
1345		verboselog(space.machine(), 2, "mc68328_w: LXMAX = %04x\n", data);
1346		mc68328->regs.lxmax = data;
1347		verboselog(space.machine(), 3, " Width: %d\n", (data & 0x03ff) + 1);
1348		break;
1349
1350		case 0xa0a:
1351		verboselog(space.machine(), 2, "mc68328_w: LYMAX = %04x\n", data);
1352		mc68328->regs.lymax = data;
1353		verboselog(space.machine(), 3, " Height: %d\n", (data & 0x03ff) + 1);
1354		break;
1355
1356		case 0xa18:
1357		verboselog(space.machine(), 2, "mc68328_w: LCXP = %04x\n", data);
1358		mc68328->regs.lcxp = data;
1359		verboselog(space.machine(), 3, " X Position: %d\n", data & 0x03ff);
1360		switch(mc68328->regs.lcxp >> 14)
1361		{
1362		case 0:
1363		verboselog(space.machine(), 3, " Cursor Control: Transparent\n");
1364		break;
1365
1366		case 1:
1367		verboselog(space.machine(), 3, " Cursor Control: Black\n");
1368		break;
1369
1370		case 2:
1371		verboselog(space.machine(), 3, " Cursor Control: Reverse\n");
1372		break;
1373
1374		case 3:
1375		verboselog(space.machine(), 3, " Cursor Control: Invalid\n");
1376		break;
1377		}
1378		break;
1379
1380		case 0xa1a:
1381		verboselog(space.machine(), 2, "mc68328_w: LCYP = %04x\n", data);
1382		mc68328->regs.lcyp = data;
1383		verboselog(space.machine(), 3, " Y Position: %d\n", data & 0x01ff);
1384		break;
1385
1386		case 0xa1c:
1387		verboselog(space.machine(), 2, "mc68328_w: LCWCH = %04x\n", data);
1388		mc68328->regs.lcwch = data;
1389		verboselog(space.machine(), 3, " Width: %d\n", (data >> 8) & 0x1f);
1390		verboselog(space.machine(), 3, " Height: %d\n", data & 0x1f);
1391		break;
1392
1393		case 0xa1e:
1394		if( mem_mask & 0x00ff )
1395		{
1396		verboselog(space.machine(), 2, "mc68328_w: LBLKC = %02x\n", data & 0x00ff);
1397		mc68328->regs.lblkc = data & 0x00ff;
1398		verboselog(space.machine(), 3, " Blink Enable: %d\n", mc68328->regs.lblkc >> 7);
1399		verboselog(space.machine(), 3, " Blink Divisor: %d\n", mc68328->regs.lblkc & 0x7f);
1400		}
1401		else
1402		{
1403		verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfffa1e) = %02x\n", (data >> 8) & 0x00ff);
1404		}
1405		break;
1406
1407		case 0xa20:
1408		if( mem_mask & 0x00ff )
1409		{
1410		verboselog(space.machine(), 2, "mc68328_w: LPOLCF = %02x\n", data & 0x00ff);
1411		mc68328->regs.lpolcf = data & 0x00ff;
1412		verboselog(space.machine(), 3, " LCD Shift Clock Polarity: %s\n", (mc68328->regs.lpicf & 0x08) ? "Active positive edge of LCLK" : "Active negative edge of LCLK");
1413		verboselog(space.machine(), 3, " First-line marker polarity: %s\n", (mc68328->regs.lpicf & 0x04) ? "Active Low" : "Active High");
1414		verboselog(space.machine(), 3, " Line-pulse polarity: %s\n", (mc68328->regs.lpicf & 0x02) ? "Active Low" : "Active High");
1415		verboselog(space.machine(), 3, " Pixel polarity: %s\n", (mc68328->regs.lpicf & 0x01) ? "Active Low" : "Active High");
1416		}
1417		else
1418		{
1419		verboselog(space.machine(), 2, "mc68328_w: LPICF = %02x\n", (data >> 8) & 0x00ff);
1420		mc68328->regs.lpicf = (data >> 8) & 0x00ff;
1421		switch((mc68328->regs.lpicf >> 1) & 0x03)
1422		{
1423		case 0:
1424		verboselog(space.machine(), 3, " Bus Size: 1-bit\n");
1425		break;
1426
1427		case 1:
1428		verboselog(space.machine(), 3, " Bus Size: 2-bit\n");
1429		break;
1430
1431		case 2:
1432		verboselog(space.machine(), 3, " Bus Size: 4-bit\n");
1433		break;
1434
1435		case 3:
1436		verboselog(space.machine(), 3, " Bus Size: unused\n");
1437		break;
1438		}
1439		verboselog(space.machine(), 3, " Gray scale enable: %d\n", mc68328->regs.lpicf & 0x01);
1440		}
1441		break;
1442
1443		case 0xa22:
1444		if( mem_mask & 0x00ff )
1445		{
1446		verboselog(space.machine(), 2, "mc68328_w: LACDRC = %02x\n", data & 0x00ff);
1447		mc68328->regs.lacdrc = data & 0x00ff;
1448		}
1449		else
1450		{
1451		verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfffa22) = %02x\n", (data >> 8) & 0x00ff);
1452		}
1453		break;
1454
1455		case 0xa24:
1456		if( mem_mask & 0x00ff )
1457		{
1458		verboselog(space.machine(), 2, "mc68328_w: LPXCD = %02x\n", data & 0x00ff);
1459		mc68328->regs.lpxcd = data & 0x00ff;
1460		verboselog(space.machine(), 3, " Clock Divisor: %d\n", mc68328->regs.lpxcd + 1);
1461		}
1462		else
1463		{
1464		verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfffa24) = %02x\n", (data >> 8) & 0x00ff);
1465		}
1466		break;
1467
1468		case 0xa26:
1469		if( mem_mask & 0x00ff )
1470		{
1471		verboselog(space.machine(), 2, "mc68328_w: LCKCON = %02x\n", data & 0x00ff);
1472		mc68328->regs.lckcon = data & 0x00ff;
1473		verboselog(space.machine(), 3, " LCDC Enable: %d\n", (mc68328->regs.lckcon >> 7) & 0x01);
1474		verboselog(space.machine(), 3, " DMA Burst Length: %d\n", ((mc68328->regs.lckcon >> 6) & 0x01) ? 16 : 8);
1475		verboselog(space.machine(), 3, " DMA Bursting Clock Control: %d\n", ((mc68328->regs.lckcon >> 4) & 0x03) + 1);
1476		verboselog(space.machine(), 3, " Bus Width: %d\n", ((mc68328->regs.lckcon >> 1) & 0x01) ? 8 : 16);
1477		verboselog(space.machine(), 3, " Pixel Clock Divider Source: %s\n", (mc68328->regs.lckcon & 0x01) ? "PIX" : "SYS");
1478		}
1479		else
1480		{
1481		verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfffa26) = %02x\n", (data >> 8) & 0x00ff);
1482		}
1483		break;
1484
1485		case 0xa28:
1486		if( mem_mask & 0x00ff )
1487		{
1488		verboselog(space.machine(), 2, "mc68328_w: LLBAR = %02x\n", data & 0x00ff);
1489		mc68328->regs.llbar = data & 0x00ff;
1490		verboselog(space.machine(), 3, " Address: %d\n", (mc68328->regs.llbar & 0x7f) * ((mc68328->regs.lpicf & 0x01) ? 8 : 16));
1491		}
1492		else
1493		{
1494		verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfffa28) = %02x\n", (data >> 8) & 0x00ff);
1495		}
1496		break;
1497
1498		case 0xa2a:
1499		if( mem_mask & 0x00ff )
1500		{
1501		verboselog(space.machine(), 2, "mc68328_w: LOTCR = %02x\n", data & 0x00ff);
1502		}
1503		else
1504		{
1505		verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfffa2a) = %02x\n", (data >> 8) & 0x00ff);
1506		}
1507		break;
1508
1509		case 0xa2c:
1510		if( mem_mask & 0x00ff )
1511		{
1512		verboselog(space.machine(), 2, "mc68328_w: LPOSR = %02x\n", data & 0x00ff);
1513		mc68328->regs.lposr = data & 0x00ff;
1514		verboselog(space.machine(), 3, " Byte Offset: %d\n", (mc68328->regs.lposr >> 3) & 0x01);
1515		verboselog(space.machine(), 3, " Pixel Offset: %d\n", mc68328->regs.lposr & 0x07);
1516		}
1517		else
1518		{
1519		verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfffa2c) = %02x\n", (data >> 8) & 0x00ff);
1520		}
1521		break;
1522
1523		case 0xa30:
1524		if( mem_mask & 0x00ff )
1525		{
1526		verboselog(space.machine(), 2, "mc68328_w: LFRCM = %02x\n", data & 0x00ff);
1527		mc68328->regs.lfrcm = data & 0x00ff;
1528		verboselog(space.machine(), 3, " X Modulation: %d\n", (mc68328->regs.lfrcm >> 4) & 0x0f);
1529		verboselog(space.machine(), 3, " Y Modulation: %d\n", mc68328->regs.lfrcm & 0x0f);
1530		}
1531		else
1532		{
1533		verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfffa30) = %02x\n", (data >> 8) & 0x00ff);
1534		}
1535		break;
1536
1537		case 0xa32:
1538		verboselog(space.machine(), 2, "mc68328_w: LGPMR = %04x\n", data);
1539		mc68328->regs.lgpmr = data;
1540		verboselog(space.machine(), 3, " Palette 0: %d\n", (mc68328->regs.lgpmr >> 8) & 0x07);
1541		verboselog(space.machine(), 3, " Palette 1: %d\n", (mc68328->regs.lgpmr >> 12) & 0x07);
1542		verboselog(space.machine(), 3, " Palette 2: %d\n", (mc68328->regs.lgpmr >> 0) & 0x07);
1543		verboselog(space.machine(), 3, " Palette 3: %d\n", (mc68328->regs.lgpmr >> 4) & 0x07);
1544		break;
1545
1546		case 0xb00:
1547		verboselog(space.machine(), 2, "mc68328_w: HMSR(0) = %04x\n", data);
1548		mc68328->regs.hmsr &= ~(mem_mask << 16);
1549		mc68328->regs.hmsr \|= (data & mem_mask) << 16;
1550		mc68328->regs.hmsr &= 0x1f3f003f;
1551		break;
1552
1553		case 0xb02:
1554		verboselog(space.machine(), 2, "mc68328_w: HMSR(16) = %04x\n", data);
1555		mc68328->regs.hmsr &= 0xffff0000 \| (~mem_mask);
1556		mc68328->regs.hmsr \|= data & mem_mask;
1557		mc68328->regs.hmsr &= 0x1f3f003f;
1558		break;
1559
1560		case 0xb04:
1561		verboselog(space.machine(), 2, "mc68328_w: ALARM(0) = %04x\n", data);
1562		mc68328->regs.alarm &= ~(mem_mask << 16);
1563		mc68328->regs.alarm \|= (data & mem_mask) << 16;
1564		mc68328->regs.alarm &= 0x1f3f003f;
1565		break;
1566
1567		case 0xb06:
1568		verboselog(space.machine(), 2, "mc68328_w: ALARM(16) = %04x\n", data);
1569		mc68328->regs.alarm &= 0xffff0000 \| (~mem_mask);
1570		mc68328->regs.alarm \|= data & mem_mask;
1571		mc68328->regs.alarm &= 0x1f3f003f;
1572		break;
1573
1574		case 0xb0c:
1575		verboselog(space.machine(), 2, "mc68328_w: RTCCTL = %04x\n", data);
1576		mc68328->regs.rtcctl = data & 0x00a0;
1577		break;
1578
1579		case 0xb0e:
1580		verboselog(space.machine(), 2, "mc68328_w: RTCISR = %04x\n", data);
1581		mc68328->regs.rtcisr &= ~data;
1582		if(mc68328->regs.rtcisr == 0)
1583		{
1584		mc68328_set_interrupt_line(device, INT_RTC, 0);
1585		}
1586		break;
1587
1588		case 0xb10:
1589		verboselog(space.machine(), 2, "mc68328_w: RTCIENR = %04x\n", data);
1590		mc68328->regs.rtcienr = data & 0x001f;
1591		break;
1592
1593		case 0xb12:
1594		verboselog(space.machine(), 2, "mc68328_w: STPWTCH = %04x\n", data);
1595		mc68328->regs.stpwtch = data & 0x003f;
1596		break;
1597
1598		default:
1599		verboselog(space.machine(), 0, "mc68328_w: Unknown address (0x%06x) = %04x (%04x)\n", 0xfff000 + address, data, mem_mask);
1600		break;
1601		}
1602		}
1603
1604		READ16_DEVICE_HANDLER( mc68328_r )
1605		{
1606		mc68328_t* mc68328 = mc68328_get_safe_token( device );
1607		UINT16 temp16 = 0;
1608		UINT32 address = offset << 1;
1609
1610		switch(address)
1611		{
1612		case 0x000:
1613		if( mem_mask & 0x00ff )
1614		{
1615		verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfff001)\n", mem_mask);
1616		}
1617		else
1618		{
1619		verboselog(space.machine(), 2, "mc68328_r (%04x): SCR = %02x\n", mem_mask, mc68328->regs.scr);
1620		return mc68328->regs.scr << 8;
1621		}
1622		break;
1623
1624		case 0x100:
1625		verboselog(space.machine(), 2, "mc68328_r (%04x): GRPBASEA = %04x\n", mem_mask, mc68328->regs.grpbasea);
1626		return mc68328->regs.grpbasea;
1627
1628		case 0x102:
1629		verboselog(space.machine(), 2, "mc68328_r (%04x): GRPBASEB = %04x\n", mem_mask, mc68328->regs.grpbaseb);
1630		return mc68328->regs.grpbaseb;
1631
1632		case 0x104:
1633		verboselog(space.machine(), 2, "mc68328_r (%04x): GRPBASEC = %04x\n", mem_mask, mc68328->regs.grpbasec);
1634		return mc68328->regs.grpbasec;
1635
1636		case 0x106:
1637		verboselog(space.machine(), 2, "mc68328_r (%04x): GRPBASED = %04x\n", mem_mask, mc68328->regs.grpbased);
1638		return mc68328->regs.grpbased;
1639
1640		case 0x108:
1641		verboselog(space.machine(), 2, "mc68328_r (%04x): GRPMASKA = %04x\n", mem_mask, mc68328->regs.grpmaska);
1642		return mc68328->regs.grpmaska;
1643
1644		case 0x10a:
1645		verboselog(space.machine(), 2, "mc68328_r (%04x): GRPMASKB = %04x\n", mem_mask, mc68328->regs.grpmaskb);
1646		return mc68328->regs.grpmaskb;
1647
1648		case 0x10c:
1649		verboselog(space.machine(), 2, "mc68328_r (%04x): GRPMASKC = %04x\n", mem_mask, mc68328->regs.grpmaskc);
1650		return mc68328->regs.grpmaskc;
1651
1652		case 0x10e:
1653		verboselog(space.machine(), 2, "mc68328_r (%04x): GRPMASKD = %04x\n", mem_mask, mc68328->regs.grpmaskd);
1654		return mc68328->regs.grpmaskd;
1655
1656		case 0x110:
1657		verboselog(space.machine(), 5, "mc68328_r (%04x): CSA0(0) = %04x\n", mem_mask, mc68328->regs.csa0 & 0x0000ffff);
1658		return mc68328->regs.csa0 & 0x0000ffff;
1659
1660		case 0x112:
1661		verboselog(space.machine(), 5, "mc68328_r (%04x): CSA0(16) = %04x\n", mem_mask, mc68328->regs.csa0 >> 16);
1662		return mc68328->regs.csa0 >> 16;
1663
1664		case 0x114:
1665		verboselog(space.machine(), 5, "mc68328_r (%04x): CSA1(0) = %04x\n", mem_mask, mc68328->regs.csa1 & 0x0000ffff);
1666		return mc68328->regs.csa1 & 0x0000ffff;
1667
1668		case 0x116:
1669		verboselog(space.machine(), 5, "mc68328_r (%04x): CSA1(16) = %04x\n", mem_mask, mc68328->regs.csa1 >> 16);
1670		return mc68328->regs.csa1 >> 16;
1671
1672		case 0x118:
1673		verboselog(space.machine(), 5, "mc68328_r (%04x): CSA2(0) = %04x\n", mem_mask, mc68328->regs.csa2 & 0x0000ffff);
1674		return mc68328->regs.csa2 & 0x0000ffff;
1675
1676		case 0x11a:
1677		verboselog(space.machine(), 5, "mc68328_r (%04x): CSA2(16) = %04x\n", mem_mask, mc68328->regs.csa2 >> 16);
1678		return mc68328->regs.csa2 >> 16;
1679
1680		case 0x11c:
1681		verboselog(space.machine(), 5, "mc68328_r (%04x): CSA3(0) = %04x\n", mem_mask, mc68328->regs.csa3 & 0x0000ffff);
1682		return mc68328->regs.csa3 & 0x0000ffff;
1683
1684		case 0x11e:
1685		verboselog(space.machine(), 5, "mc68328_r (%04x): CSA3(16) = %04x\n", mem_mask, mc68328->regs.csa3 >> 16);
1686		return mc68328->regs.csa3 >> 16;
1687
1688		case 0x120:
1689		verboselog(space.machine(), 5, "mc68328_r (%04x): CSB0(0) = %04x\n", mem_mask, mc68328->regs.csb0 & 0x0000ffff);
1690		return mc68328->regs.csb0 & 0x0000ffff;
1691
1692		case 0x122:
1693		verboselog(space.machine(), 5, "mc68328_r (%04x): CSB0(16) = %04x\n", mem_mask, mc68328->regs.csb0 >> 16);
1694		return mc68328->regs.csb0 >> 16;
1695
1696		case 0x124:
1697		verboselog(space.machine(), 5, "mc68328_r (%04x): CSB1(0) = %04x\n", mem_mask, mc68328->regs.csb1 & 0x0000ffff);
1698		return mc68328->regs.csb1 & 0x0000ffff;
1699
1700		case 0x126:
1701		verboselog(space.machine(), 5, "mc68328_r (%04x): CSB1(16) = %04x\n", mem_mask, mc68328->regs.csb1 >> 16);
1702		return mc68328->regs.csb1 >> 16;
1703
1704		case 0x128:
1705		verboselog(space.machine(), 5, "mc68328_r (%04x): CSB2(0) = %04x\n", mem_mask, mc68328->regs.csb2 & 0x0000ffff);
1706		return mc68328->regs.csb2 & 0x0000ffff;
1707
1708		case 0x12a:
1709		verboselog(space.machine(), 5, "mc68328_r (%04x): CSB2(16) = %04x\n", mem_mask, mc68328->regs.csb2 >> 16);
1710		return mc68328->regs.csb2 >> 16;
1711
1712		case 0x12c:
1713		verboselog(space.machine(), 5, "mc68328_r (%04x): CSB3(0) = %04x\n", mem_mask, mc68328->regs.csb3 & 0x0000ffff);
1714		return mc68328->regs.csb3 & 0x0000ffff;
1715
1716		case 0x12e:
1717		verboselog(space.machine(), 5, "mc68328_r (%04x): CSB3(16) = %04x\n", mem_mask, mc68328->regs.csb3 >> 16);
1718		return mc68328->regs.csb3 >> 16;
1719
1720		case 0x130:
1721		verboselog(space.machine(), 5, "mc68328_r (%04x): CSC0(0) = %04x\n", mem_mask, mc68328->regs.csc0 & 0x0000ffff);
1722		return mc68328->regs.csc0 & 0x0000ffff;
1723
1724		case 0x132:
1725		verboselog(space.machine(), 5, "mc68328_r (%04x): CSC0(16) = %04x\n", mem_mask, mc68328->regs.csc0 >> 16);
1726		return mc68328->regs.csc0 >> 16;
1727
1728		case 0x134:
1729		verboselog(space.machine(), 5, "mc68328_r (%04x): CSC1(0) = %04x\n", mem_mask, mc68328->regs.csc1 & 0x0000ffff);
1730		return mc68328->regs.csc1 & 0x0000ffff;
1731
1732		case 0x136:
1733		verboselog(space.machine(), 5, "mc68328_r (%04x): CSC1(16) = %04x\n", mem_mask, mc68328->regs.csc1 >> 16);
1734		return mc68328->regs.csc1 >> 16;
1735
1736		case 0x138:
1737		verboselog(space.machine(), 5, "mc68328_r (%04x): CSC2(0) = %04x\n", mem_mask, mc68328->regs.csc2 & 0x0000ffff);
1738		return mc68328->regs.csc2 & 0x0000ffff;
1739
1740		case 0x13a:
1741		verboselog(space.machine(), 5, "mc68328_r (%04x): CSC2(16) = %04x\n", mem_mask, mc68328->regs.csc2 >> 16);
1742		return mc68328->regs.csc2 >> 16;
1743
1744		case 0x13c:
1745		verboselog(space.machine(), 5, "mc68328_r (%04x): CSC3(0) = %04x\n", mem_mask, mc68328->regs.csc3 & 0x0000ffff);
1746		return mc68328->regs.csc3 & 0x0000ffff;
1747
1748		case 0x13e:
1749		verboselog(space.machine(), 5, "mc68328_r (%04x): CSC3(16) = %04x\n", mem_mask, mc68328->regs.csc3 >> 16);
1750		return mc68328->regs.csc3 >> 16;
1751
1752		case 0x140:
1753		verboselog(space.machine(), 5, "mc68328_r (%04x): CSD0(0) = %04x\n", mem_mask, mc68328->regs.csd0 & 0x0000ffff);
1754		return mc68328->regs.csd0 & 0x0000ffff;
1755
1756		case 0x142:
1757		verboselog(space.machine(), 5, "mc68328_r (%04x): CSD0(16) = %04x\n", mem_mask, mc68328->regs.csd0 >> 16);
1758		return mc68328->regs.csd0 >> 16;
1759
1760		case 0x144:
1761		verboselog(space.machine(), 5, "mc68328_r (%04x): CSD1(0) = %04x\n", mem_mask, mc68328->regs.csd1 & 0x0000ffff);
1762		return mc68328->regs.csd1 & 0x0000ffff;
1763
1764		case 0x146:
1765		verboselog(space.machine(), 5, "mc68328_r (%04x): CSD1(16) = %04x\n", mem_mask, mc68328->regs.csd1 >> 16);
1766		return mc68328->regs.csd1 >> 16;
1767
1768		case 0x148:
1769		verboselog(space.machine(), 5, "mc68328_r (%04x): CSD2(0) = %04x\n", mem_mask, mc68328->regs.csd2 & 0x0000ffff);
1770		return mc68328->regs.csd2 & 0x0000ffff;
1771
1772		case 0x14a:
1773		verboselog(space.machine(), 5, "mc68328_r (%04x): CSD2(16) = %04x\n", mem_mask, mc68328->regs.csd2 >> 16);
1774		return mc68328->regs.csd2 >> 16;
1775
1776		case 0x14c:
1777		verboselog(space.machine(), 5, "mc68328_r (%04x): CSD3(0) = %04x\n", mem_mask, mc68328->regs.csd3 & 0x0000ffff);
1778		return mc68328->regs.csd3 & 0x0000ffff;
1779
1780		case 0x14e:
1781		verboselog(space.machine(), 5, "mc68328_r (%04x): CSD3(16) = %04x\n", mem_mask, mc68328->regs.csd3 >> 16);
1782		return mc68328->regs.csd3 >> 16;
1783
1784		case 0x200:
1785		verboselog(space.machine(), 2, "mc68328_r (%04x): PLLCR = %04x\n", mem_mask, mc68328->regs.pllcr);
1786		return mc68328->regs.pllcr;
1787
1788		case 0x202:
1789		verboselog(space.machine(), 2, "mc68328_r (%04x): PLLFSR = %04x\n", mem_mask, mc68328->regs.pllfsr);
1790		mc68328->regs.pllfsr ^= 0x8000;
1791		return mc68328->regs.pllfsr;
1792
1793		case 0x206:
1794		if( mem_mask & 0x00ff )
1795		{
1796		verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfff206)\n", mem_mask);
1797		}
1798		else
1799		{
1800		verboselog(space.machine(), 2, "mc68328_r (%04x): PCTLR = %02x\n", mem_mask, mc68328->regs.pctlr);
1801		return mc68328->regs.pctlr << 8;
1802		}
1803		break;
1804
1805		case 0x300:
1806		if( mem_mask & 0x00ff )
1807		{
1808		verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfff301)\n", mem_mask);
1809		}
1810		else
1811		{
1812		verboselog(space.machine(), 2, "mc68328_r (%04x): IVR = %02x\n", mem_mask, mc68328->regs.ivr);
1813		return mc68328->regs.ivr << 8;
1814		}
1815		break;
1816
1817		case 0x302:
1818		verboselog(space.machine(), 2, "mc68328_r (%04x): ICR = %04x\n", mem_mask, mc68328->regs.icr);
1819		return mc68328->regs.icr;
1820
1821		case 0x304:
1822		verboselog(space.machine(), 2, "mc68328_r (%04x): IMR(16) = %04x\n", mem_mask, mc68328->regs.imr >> 16);
1823		return mc68328->regs.imr >> 16;
1824
1825		case 0x306:
1826		verboselog(space.machine(), 2, "mc68328_r (%04x): IMR(0) = %04x\n", mem_mask, mc68328->regs.imr & 0x0000ffff);
1827		return mc68328->regs.imr & 0x0000ffff;
1828
1829		case 0x308:
1830		verboselog(space.machine(), 2, "mc68328_r (%04x): IWR(16) = %04x\n", mem_mask, mc68328->regs.iwr >> 16);
1831		return mc68328->regs.iwr >> 16;
1832
1833		case 0x30a:
1834		verboselog(space.machine(), 2, "mc68328_r (%04x): IWR(0) = %04x\n", mem_mask, mc68328->regs.iwr & 0x0000ffff);
1835		return mc68328->regs.iwr & 0x0000ffff;
1836
1837		case 0x30c:
1838		verboselog(space.machine(), 2, "mc68328_r (%04x): ISR(16) = %04x\n", mem_mask, mc68328->regs.isr >> 16);
1839		return mc68328->regs.isr >> 16;
1840
1841		case 0x30e:
1842		verboselog(space.machine(), 2, "mc68328_r (%04x): ISR(0) = %04x\n", mem_mask, mc68328->regs.isr & 0x0000ffff);
1843		return mc68328->regs.isr & 0x0000ffff;
1844
1845		case 0x310:
1846		verboselog(space.machine(), 2, "mc68328_r (%04x): IPR(16) = %04x\n", mem_mask, mc68328->regs.ipr >> 16);
1847		return mc68328->regs.ipr >> 16;
1848
1849		case 0x312:
1850		verboselog(space.machine(), 2, "mc68328_r (%04x): IPR(0) = %04x\n", mem_mask, mc68328->regs.ipr & 0x0000ffff);
1851		return mc68328->regs.ipr & 0x0000ffff;
1852
1853		case 0x400:
1854		if( mem_mask & 0x00ff )
1855		{
1856		verboselog(space.machine(), 2, "mc68328_r (%04x): PADATA = %02x\n", mem_mask, mc68328->regs.padata);
1857		if(!mc68328->in_port_a.isnull())
1858		{
1859		return mc68328->in_port_a( 0 );
1860		}
1861		else
1862		{
1863		return mc68328->regs.padata;
1864		}
1865		}
1866		else
1867		{
1868		verboselog(space.machine(), 2, "mc68328_r (%04x): PADIR = %02x\n", mem_mask, mc68328->regs.padir);
1869		return mc68328->regs.padir << 8;
1870		}
1871		break;
1872
1873		case 0x402:
1874		if( mem_mask & 0x00ff )
1875		{
1876		verboselog(space.machine(), 2, "mc68328_r (%04x): PASEL = %02x\n", mem_mask, mc68328->regs.pasel);
1877		return mc68328->regs.pasel;
1878		}
1879		else
1880		{
1881		verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfff402)\n", mem_mask);
1882		}
1883		break;
1884
1885		case 0x408:
1886		if( mem_mask & 0x00ff )
1887		{
1888		verboselog(space.machine(), 2, "mc68328_r (%04x): PBDATA = %02x\n", mem_mask, mc68328->regs.pbdata);
1889		if(!mc68328->in_port_b.isnull())
1890		{
1891		return mc68328->in_port_b( 0 );
1892		}
1893		else
1894		{
1895		return mc68328->regs.pbdata;
1896		}
1897		}
1898		else
1899		{
1900		verboselog(space.machine(), 2, "mc68328_r (%04x): PBDIR = %02x\n", mem_mask, mc68328->regs.pbdir);
1901		return mc68328->regs.pbdir << 8;
1902		}
1903		break;
1904
1905		case 0x40a:
1906		if( mem_mask & 0x00ff )
1907		{
1908		verboselog(space.machine(), 2, "mc68328_r (%04x): PBSEL = %02x\n", mem_mask, mc68328->regs.pbsel);
1909		return mc68328->regs.pbsel;
1910		}
1911		else
1912		{
1913		verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfff40a)\n", mem_mask);
1914		}
1915		break;
1916
1917		case 0x410:
1918		if( mem_mask & 0x00ff )
1919		{
1920		verboselog(space.machine(), 2, "mc68328_r (%04x): PCDATA = %02x\n", mem_mask, mc68328->regs.pcdata);
1921		if(!mc68328->in_port_c.isnull())
1922		{
1923		return mc68328->in_port_c( 0 );
1924		}
1925		else
1926		{
1927		return mc68328->regs.pcdata;
1928		}
1929		}
1930		else
1931		{
1932		verboselog(space.machine(), 2, "mc68328_r (%04x): PCDIR = %02x\n", mem_mask, mc68328->regs.pcdir);
1933		return mc68328->regs.pcdir << 8;
1934		}
1935		break;
1936
1937		case 0x412:
1938		if( mem_mask & 0x00ff )
1939		{
1940		verboselog(space.machine(), 2, "mc68328_r (%04x): PCSEL = %02x\n", mem_mask, mc68328->regs.pcsel);
1941		return mc68328->regs.pcsel;
1942		}
1943		else
1944		{
1945		verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfff412)\n", mem_mask);
1946		}
1947		break;
1948
1949		case 0x418:
1950		if( mem_mask & 0x00ff )
1951		{
1952		verboselog(space.machine(), 2, "mc68328_r (%04x): PDDATA = %02x\n", mem_mask, mc68328->regs.pddata);
1953		if(!mc68328->in_port_d.isnull())
1954		{
1955		return mc68328->in_port_d( 0 );
1956		}
1957		else
1958		{
1959		return mc68328->regs.pddata;
1960		}
1961		}
1962		else
1963		{
1964		verboselog(space.machine(), 2, "mc68328_r (%04x): PDDIR = %02x\n", mem_mask, mc68328->regs.pddir);
1965		return mc68328->regs.pddir << 8;
1966		}
1967		break;
1968
1969		case 0x41a:
1970		if( mem_mask & 0x00ff )
1971		{
1972		verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfff41b)\n", mem_mask);
1973		}
1974		else
1975		{
1976		verboselog(space.machine(), 2, "mc68328_r (%04x): PDPUEN = %02x\n", mem_mask, mc68328->regs.pdpuen);
1977		return mc68328->regs.pdpuen << 8;
1978		}
1979		break;
1980
1981		case 0x41c:
1982		if( mem_mask & 0x00ff )
1983		{
1984		verboselog(space.machine(), 2, "mc68328_r (%04x): PDIRQEN = %02x\n", mem_mask, mc68328->regs.pdirqen);
1985		return mc68328->regs.pdirqen;
1986		}
1987		else
1988		{
1989		verboselog(space.machine(), 2, "mc68328_r (%04x): PDPOL = %02x\n", mem_mask, mc68328->regs.pdpol);
1990		return mc68328->regs.pdpol << 8;
1991		}
1992		break;
1993
1994		case 0x41e:
1995		if( mem_mask & 0x00ff )
1996		{
1997		verboselog(space.machine(), 2, "mc68328_r (%04x): PDIRQEDGE = %02x\n", mem_mask, mc68328->regs.pdirqedge);
1998		return mc68328->regs.pdirqedge;
1999		}
2000		else
2001		{
2002		verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfff41e)\n", mem_mask);
2003		}
2004		break;
2005
2006		case 0x420:
2007		if( mem_mask & 0x00ff )
2008		{
2009		verboselog(space.machine(), 2, "mc68328_r (%04x): PEDATA = %02x\n", mem_mask, mc68328->regs.pedata);
2010		if(!mc68328->in_port_e.isnull())
2011		{
2012		return mc68328->in_port_e( 0 );
2013		}
2014		else
2015		{
2016		return mc68328->regs.pedata;
2017		}
2018		}
2019		else
2020		{
2021		verboselog(space.machine(), 2, "mc68328_r (%04x): PEDIR = %02x\n", mem_mask, mc68328->regs.pedir);
2022		return mc68328->regs.pedir << 8;
2023		}
2024		break;
2025
2026		case 0x422:
2027		if( mem_mask & 0x00ff )
2028		{
2029		verboselog(space.machine(), 2, "mc68328_r (%04x): PESEL = %02x\n", mem_mask, mc68328->regs.pesel);
2030		return mc68328->regs.pesel;
2031		}
2032		else
2033		{
2034		verboselog(space.machine(), 2, "mc68328_r (%04x): PEPUEN = %02x\n", mem_mask, mc68328->regs.pepuen);
2035		return mc68328->regs.pepuen << 8;
2036		}
2037		break;
2038
2039		case 0x428:
2040		if( mem_mask & 0x00ff )
2041		{
2042		verboselog(space.machine(), 2, "mc68328_r (%04x): PFDATA = %02x\n", mem_mask, mc68328->regs.pfdata);
2043		if(!mc68328->in_port_f.isnull())
2044		{
2045		return mc68328->in_port_f( 0 );
2046		}
2047		else
2048		{
2049		return mc68328->regs.pfdata;
2050		}
2051		}
2052		else
2053		{
2054		verboselog(space.machine(), 2, "mc68328_r (%04x): PFDIR = %02x\n", mem_mask, mc68328->regs.pfdir);
2055		return mc68328->regs.pfdir << 8;
2056		}
2057		break;
2058
2059		case 0x42a:
2060		if( mem_mask & 0x00ff )
2061		{
2062		verboselog(space.machine(), 2, "mc68328_r (%04x): PFSEL = %02x\n", mem_mask, mc68328->regs.pfsel);
2063		return mc68328->regs.pfsel;
2064		}
2065		else
2066		{
2067		verboselog(space.machine(), 2, "mc68328_r (%04x): PFPUEN = %02x\n", mem_mask, mc68328->regs.pfpuen);
2068		return mc68328->regs.pfpuen << 8;
2069		}
2070		break;
2071
2072		case 0x430:
2073		if( mem_mask & 0x00ff )
2074		{
2075		verboselog(space.machine(), 2, "mc68328_r (%04x): PGDATA = %02x\n", mem_mask, mc68328->regs.pgdata);
2076		if(!mc68328->in_port_g.isnull())
2077		{
2078		return mc68328->in_port_g( 0 );
2079		}
2080		else
2081		{
2082		return mc68328->regs.pgdata;
2083		}
2084		}
2085		else
2086		{
2087		verboselog(space.machine(), 2, "mc68328_r (%04x): PGDIR = %02x\n", mem_mask, mc68328->regs.pgdir);
2088		return mc68328->regs.pgdir << 8;
2089		}
2090		break;
2091
2092		case 0x432:
2093		if( mem_mask & 0x00ff )
2094		{
2095		verboselog(space.machine(), 2, "mc68328_r (%04x): PGSEL = %02x\n", mem_mask, mc68328->regs.pgsel);
2096		return mc68328->regs.pgsel;
2097		}
2098		else
2099		{
2100		verboselog(space.machine(), 2, "mc68328_r (%04x): PGPUEN = %02x\n", mem_mask, mc68328->regs.pgpuen);
2101		return mc68328->regs.pgpuen << 8;
2102		}
2103		break;
2104
2105		case 0x438:
2106		if( mem_mask & 0x00ff )
2107		{
2108		verboselog(space.machine(), 2, "mc68328_r (%04x): PJDATA = %02x\n", mem_mask, mc68328->regs.pjdata);
2109		if(!mc68328->in_port_j.isnull())
2110		{
2111		return mc68328->in_port_j( 0 );
2112		}
2113		else
2114		{
2115		return mc68328->regs.pjdata;
2116		}
2117		}
2118		else
2119		{
2120		verboselog(space.machine(), 2, "mc68328_r (%04x): PJDIR = %02x\n", mem_mask, mc68328->regs.pjdir);
2121		return mc68328->regs.pjdir << 8;
2122		}
2123		break;
2124
2125		case 0x43a:
2126		if( mem_mask & 0x00ff )
2127		{
2128		verboselog(space.machine(), 2, "mc68328_r (%04x): PJSEL = %02x\n", mem_mask, mc68328->regs.pjsel);
2129		return mc68328->regs.pjsel;
2130		}
2131		else
2132		{
2133		verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfff43a)\n", mem_mask);
2134		}
2135		break;
2136
2137		case 0x440:
2138		if( mem_mask & 0x00ff )
2139		{
2140		verboselog(space.machine(), 2, "mc68328_r (%04x): PKDATA = %02x\n", mem_mask, mc68328->regs.pkdata);
2141		if(!mc68328->in_port_k.isnull())
2142		{
2143		return mc68328->in_port_k( 0 );
2144		}
2145		else
2146		{
2147		return mc68328->regs.pkdata;
2148		}
2149		}
2150		else
2151		{
2152		verboselog(space.machine(), 2, "mc68328_r (%04x): PKDIR = %02x\n", mem_mask, mc68328->regs.pkdir);
2153		return mc68328->regs.pkdir << 8;
2154		}
2155		break;
2156
2157		case 0x442:
2158		if( mem_mask & 0x00ff )
2159		{
2160		verboselog(space.machine(), 2, "mc68328_r (%04x): PKSEL = %02x\n", mem_mask, mc68328->regs.pksel);
2161		return mc68328->regs.pksel;
2162		}
2163		else
2164		{
2165		verboselog(space.machine(), 2, "mc68328_r (%04x): PKPUEN = %02x\n", mem_mask, mc68328->regs.pkpuen);
2166		return mc68328->regs.pkpuen << 8;
2167		}
2168		break;
2169
2170		case 0x448:
2171		if( mem_mask & 0x00ff )
2172		{
2173		verboselog(space.machine(), 2, "mc68328_r (%04x): PMDATA = %02x\n", mem_mask, mc68328->regs.pmdata);
2174		if(!mc68328->in_port_m.isnull())
2175		{
2176		return mc68328->in_port_m( 0 );
2177		}
2178		else
2179		{
2180		return mc68328->regs.pmdata;
2181		}
2182		}
2183		else
2184		{
2185		verboselog(space.machine(), 2, "mc68328_r (%04x): PMDIR = %02x\n", mem_mask, mc68328->regs.pmdir);
2186		return mc68328->regs.pmdir << 8;
2187		}
2188		break;
2189
2190		case 0x44a:
2191		if( mem_mask & 0x00ff )
2192		{
2193		verboselog(space.machine(), 2, "mc68328_r (%04x): PMSEL = %02x\n", mem_mask, mc68328->regs.pmsel);
2194		return mc68328->regs.pmsel;
2195		}
2196		else
2197		{
2198		verboselog(space.machine(), 2, "mc68328_r (%04x): PMPUEN = %02x\n", mem_mask, mc68328->regs.pmpuen);
2199		return mc68328->regs.pmpuen << 8;
2200		}
2201		break;
2202
2203		case 0x500:
2204		verboselog(space.machine(), 2, "mc68328_r (%04x): PWMC = %04x\n", mem_mask, mc68328->regs.pwmc);
2205		temp16 = mc68328->regs.pwmc;
2206		if(mc68328->regs.pwmc & PWMC_PWMIRQ)
2207		{
2208		mc68328->regs.pwmc &= ~PWMC_PWMIRQ;
2209		mc68328_set_interrupt_line(device, INT_PWM, 0);
2210		}
2211		return temp16;
2212
2213		case 0x502:
2214		verboselog(space.machine(), 2, "mc68328_r (%04x): PWMP = %04x\n", mem_mask, mc68328->regs.pwmp);
2215		return mc68328->regs.pwmp;
2216
2217		case 0x504:
2218		verboselog(space.machine(), 2, "mc68328_r (%04x): PWMW = %04x\n", mem_mask, mc68328->regs.pwmw);
2219		return mc68328->regs.pwmw;
2220
2221		case 0x506:
2222		verboselog(space.machine(), 2, "mc68328_r (%04x): PWMCNT = %04x\n", mem_mask, mc68328->regs.pwmcnt);
2223		return mc68328->regs.pwmcnt;
2224
2225		case 0x600:
2226		verboselog(space.machine(), 2, "mc68328_r (%04x): TCTL1 = %04x\n", mem_mask, mc68328->regs.tctl[0]);
2227		return mc68328->regs.tctl[0];
2228
2229		case 0x602:
2230		verboselog(space.machine(), 2, "mc68328_r (%04x): TPRER1 = %04x\n", mem_mask, mc68328->regs.tprer[0]);
2231		return mc68328->regs.tprer[0];
2232
2233		case 0x604:
2234		verboselog(space.machine(), 2, "mc68328_r (%04x): TCMP1 = %04x\n", mem_mask, mc68328->regs.tcmp[0]);
2235		return mc68328->regs.tcmp[0];
2236
2237		case 0x606:
2238		verboselog(space.machine(), 2, "mc68328_r (%04x): TCR1 = %04x\n", mem_mask, mc68328->regs.tcr[0]);
2239		return mc68328->regs.tcr[0];
2240
2241		case 0x608:
2242		verboselog(space.machine(), 2, "mc68328_r (%04x): TCN1 = %04x\n", mem_mask, mc68328->regs.tcn[0]);
2243		return mc68328->regs.tcn[0];
2244
2245		case 0x60a:
2246		verboselog(space.machine(), 5, "mc68328_r (%04x): TSTAT1 = %04x\n", mem_mask, mc68328->regs.tstat[0]);
2247		mc68328->regs.tclear[0] \|= mc68328->regs.tstat[0];
2248		return mc68328->regs.tstat[0];
2249
2250		case 0x60c:
2251		verboselog(space.machine(), 2, "mc68328_r (%04x): TCTL2 = %04x\n", mem_mask, mc68328->regs.tctl[1]);
2252		return mc68328->regs.tctl[1];
2253
2254		case 0x60e:
2255		verboselog(space.machine(), 2, "mc68328_r (%04x): TPREP2 = %04x\n", mem_mask, mc68328->regs.tprer[1]);
2256		return mc68328->regs.tprer[1];
2257
2258		case 0x610:
2259		verboselog(space.machine(), 2, "mc68328_r (%04x): TCMP2 = %04x\n", mem_mask, mc68328->regs.tcmp[1]);
2260		return mc68328->regs.tcmp[1];
2261
2262		case 0x612:
2263		verboselog(space.machine(), 2, "mc68328_r (%04x): TCR2 = %04x\n", mem_mask, mc68328->regs.tcr[1]);
2264		return mc68328->regs.tcr[1];
2265
2266		case 0x614:
2267		verboselog(space.machine(), 2, "mc68328_r (%04x): TCN2 = %04x\n", mem_mask, mc68328->regs.tcn[1]);
2268		return mc68328->regs.tcn[1];
2269
2270		case 0x616:
2271		verboselog(space.machine(), 2, "mc68328_r (%04x): TSTAT2 = %04x\n", mem_mask, mc68328->regs.tstat[1]);
2272		mc68328->regs.tclear[1] \|= mc68328->regs.tstat[1];
2273		return mc68328->regs.tstat[1];
2274
2275		case 0x618:
2276		verboselog(space.machine(), 2, "mc68328_r (%04x): WCTLR = %04x\n", mem_mask, mc68328->regs.wctlr);
2277		return mc68328->regs.wctlr;
2278
2279		case 0x61a:
2280		verboselog(space.machine(), 2, "mc68328_r (%04x): WCMPR = %04x\n", mem_mask, mc68328->regs.wcmpr);
2281		return mc68328->regs.wcmpr;
2282
2283		case 0x61c:
2284		verboselog(space.machine(), 2, "mc68328_r (%04x): WCN = %04x\n", mem_mask, mc68328->regs.wcn);
2285		return mc68328->regs.wcn;
2286
2287		case 0x700:
2288		verboselog(space.machine(), 2, "mc68328_r (%04x): SPISR = %04x\n", mem_mask, mc68328->regs.spisr);
2289		return mc68328->regs.spisr;
2290
2291		case 0x800:
2292		verboselog(space.machine(), 2, "mc68328_r (%04x): SPIMDATA = %04x\n", mem_mask, mc68328->regs.spimdata);
2293		if(!mc68328->in_spim.isnull())
2294		{
2295		return mc68328->in_spim( 0, 0xffff );
2296		}
2297		return mc68328->regs.spimdata;
2298
2299		case 0x802:
2300		verboselog(space.machine(), 2, "mc68328_r (%04x): SPIMCONT = %04x\n", mem_mask, mc68328->regs.spimcont);
2301		if(mc68328->regs.spimcont & SPIM_XCH)
2302		{
2303		mc68328->regs.spimcont &= ~SPIM_XCH;
2304		mc68328->regs.spimcont \|= SPIM_SPIMIRQ;
2305		return ((mc68328->regs.spimcont \| SPIM_XCH) &~ SPIM_SPIMIRQ);
2306		}
2307		return mc68328->regs.spimcont;
2308
2309		case 0x900:
2310		verboselog(space.machine(), 2, "mc68328_r (%04x): USTCNT = %04x\n", mem_mask, mc68328->regs.ustcnt);
2311		return mc68328->regs.ustcnt;
2312
2313		case 0x902:
2314		verboselog(space.machine(), 2, "mc68328_r (%04x): UBAUD = %04x\n", mem_mask, mc68328->regs.ubaud);
2315		return mc68328->regs.ubaud;
2316
2317		case 0x904:
2318		verboselog(space.machine(), 5, "mc68328_r (%04x): URX = %04x\n", mem_mask, mc68328->regs.urx);
2319		return mc68328->regs.urx;
2320
2321		case 0x906:
2322		verboselog(space.machine(), 5, "mc68328_r (%04x): UTX = %04x\n", mem_mask, mc68328->regs.utx);
2323		return mc68328->regs.utx \| UTX_FIFO_EMPTY \| UTX_FIFO_HALF \| UTX_TX_AVAIL;
2324
2325		case 0x908:
2326		verboselog(space.machine(), 2, "mc68328_r (%04x): UMISC = %04x\n", mem_mask, mc68328->regs.umisc);
2327		return mc68328->regs.umisc;
2328
2329		case 0xa00:
2330		verboselog(space.machine(), 2, "mc68328_r (%04x): LSSA(16) = %04x\n", mem_mask, mc68328->regs.lssa >> 16);
2331		return mc68328->regs.lssa >> 16;
2332
2333		case 0xa02:
2334		verboselog(space.machine(), 2, "mc68328_r (%04x): LSSA(0) = %04x\n", mem_mask, mc68328->regs.lssa & 0x0000ffff);
2335		return mc68328->regs.lssa & 0x0000ffff;
2336
2337		case 0xa04:
2338		if( mem_mask & 0x00ff )
2339		{
2340		verboselog(space.machine(), 2, "mc68328_r (%04x): LVPW = %02x\n", mem_mask, mc68328->regs.lvpw);
2341		return mc68328->regs.lvpw;
2342		}
2343		else
2344		{
2345		verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa04)\n", mem_mask);
2346		}
2347		break;
2348
2349		case 0xa08:
2350		verboselog(space.machine(), 2, "mc68328_r (%04x): LXMAX = %04x\n", mem_mask, mc68328->regs.lxmax);
2351		return mc68328->regs.lxmax;
2352
2353		case 0xa0a:
2354		verboselog(space.machine(), 2, "mc68328_r (%04x): LYMAX = %04x\n", mem_mask, mc68328->regs.lymax);
2355		return mc68328->regs.lymax;
2356
2357		case 0xa18:
2358		verboselog(space.machine(), 2, "mc68328_r (%04x): LCXP = %04x\n", mem_mask, mc68328->regs.lcxp);
2359		return mc68328->regs.lcxp;
2360
2361		case 0xa1a:
2362		verboselog(space.machine(), 2, "mc68328_r (%04x): LCYP = %04x\n", mem_mask, mc68328->regs.lcyp);
2363		return mc68328->regs.lcyp;
2364
2365		case 0xa1c:
2366		verboselog(space.machine(), 2, "mc68328_r (%04x): LCWCH = %04x\n", mem_mask, mc68328->regs.lcwch);
2367		return mc68328->regs.lcwch;
2368
2369		case 0xa1e:
2370		if( mem_mask & 0x00ff )
2371		{
2372		verboselog(space.machine(), 2, "mc68328_r (%04x): LBLKC = %02x\n", mem_mask, mc68328->regs.lblkc);
2373		return mc68328->regs.lblkc;
2374		}
2375		else
2376		{
2377		verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa1e)\n", mem_mask);
2378		}
2379		break;
2380
2381		case 0xa20:
2382		if( mem_mask & 0x00ff )
2383		{
2384		verboselog(space.machine(), 2, "mc68328_r (%04x): LPOLCF = %02x\n", mem_mask, mc68328->regs.lpolcf);
2385		return mc68328->regs.lpolcf;
2386		}
2387		else
2388		{
2389		verboselog(space.machine(), 2, "mc68328_r (%04x): LPICF = %02x\n", mem_mask, mc68328->regs.lpicf);
2390		return mc68328->regs.lpicf << 8;
2391		}
2392		break;
2393
2394		case 0xa22:
2395		if( mem_mask & 0x00ff )
2396		{
2397		verboselog(space.machine(), 2, "mc68328_r (%04x): LACDRC = %02x\n", mem_mask, mc68328->regs.lacdrc);
2398		return mc68328->regs.lacdrc;
2399		}
2400		else
2401		{
2402		verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa22)\n", mem_mask);
2403		}
2404		break;
2405
2406		case 0xa24:
2407		if( mem_mask & 0x00ff )
2408		{
2409		verboselog(space.machine(), 2, "mc68328_r (%04x): LPXCD = %02x\n", mem_mask, mc68328->regs.lpxcd);
2410		return mc68328->regs.lpxcd;
2411		}
2412		else
2413		{
2414		verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa24)\n", mem_mask);
2415		}
2416		break;
2417
2418		case 0xa26:
2419		if( mem_mask & 0x00ff )
2420		{
2421		verboselog(space.machine(), 2, "mc68328_r (%04x): LCKCON = %02x\n", mem_mask, mc68328->regs.lckcon);
2422		return mc68328->regs.lckcon;
2423		}
2424		else
2425		{
2426		verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa26)\n", mem_mask);
2427		}
2428		break;
2429
2430		case 0xa28:
2431		if( mem_mask & 0x00ff )
2432		{
2433		verboselog(space.machine(), 2, "mc68328_r (%04x): LLBAR = %02x\n", mem_mask, mc68328->regs.llbar);
2434		return mc68328->regs.llbar;
2435		}
2436		else
2437		{
2438		verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa28)\n", mem_mask);
2439		}
2440		break;
2441
2442		case 0xa2a:
2443		if( mem_mask & 0x00ff )
2444		{
2445		verboselog(space.machine(), 2, "mc68328_r (%04x): LOTCR = %02x\n", mem_mask, mc68328->regs.lotcr);
2446		return mc68328->regs.lotcr;
2447		}
2448		else
2449		{
2450		verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa2a)\n", mem_mask);
2451		}
2452		break;
2453
2454		case 0xa2c:
2455		if( mem_mask & 0x00ff )
2456		{
2457		verboselog(space.machine(), 2, "mc68328_r (%04x): LPOSR = %02x\n", mem_mask, mc68328->regs.lposr);
2458		return mc68328->regs.lposr;
2459		}
2460		else
2461		{
2462		verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa2c)\n", mem_mask);
2463		}
2464		break;
2465
2466		case 0xa30:
2467		if( mem_mask & 0x00ff )
2468		{
2469		verboselog(space.machine(), 2, "mc68328_r (%04x): LFRCM = %02x\n", mem_mask, mc68328->regs.lfrcm);
2470		return mc68328->regs.lfrcm;
2471		}
2472		else
2473		{
2474		verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa30)\n", mem_mask);
2475		}
2476		break;
2477
2478		case 0xa32:
2479		verboselog(space.machine(), 2, "mc68328_r (%04x): LGPMR = %04x\n", mem_mask, mc68328->regs.lgpmr);
2480		return mc68328->regs.lgpmr;
2481
2482		case 0xb00:
2483		verboselog(space.machine(), 2, "mc68328_r (%04x): HMSR(0) = %04x\n", mem_mask, mc68328->regs.hmsr & 0x0000ffff);
2484		return mc68328->regs.hmsr & 0x0000ffff;
2485
2486		case 0xb02:
2487		verboselog(space.machine(), 2, "mc68328_r (%04x): HMSR(16) = %04x\n", mem_mask, mc68328->regs.hmsr >> 16);
2488		return mc68328->regs.hmsr >> 16;
2489
2490		case 0xb04:
2491		verboselog(space.machine(), 2, "mc68328_r (%04x): ALARM(0) = %04x\n", mem_mask, mc68328->regs.alarm & 0x0000ffff);
2492		return mc68328->regs.alarm & 0x0000ffff;
2493
2494		case 0xb06:
2495		verboselog(space.machine(), 2, "mc68328_r (%04x): ALARM(16) = %04x\n", mem_mask, mc68328->regs.alarm >> 16);
2496		return mc68328->regs.alarm >> 16;
2497
2498		case 0xb0c:
2499		verboselog(space.machine(), 2, "mc68328_r (%04x): RTCCTL = %04x\n", mem_mask, mc68328->regs.rtcctl);
2500		return mc68328->regs.rtcctl;
2501
2502		case 0xb0e:
2503		verboselog(space.machine(), 2, "mc68328_r (%04x): RTCISR = %04x\n", mem_mask, mc68328->regs.rtcisr);
2504		return mc68328->regs.rtcisr;
2505
2506		case 0xb10:
2507		verboselog(space.machine(), 2, "mc68328_r (%04x): RTCIENR = %04x\n", mem_mask, mc68328->regs.rtcienr);
2508		return mc68328->regs.rtcienr;
2509
2510		case 0xb12:
2511		verboselog(space.machine(), 2, "mc68328_r (%04x): STPWTCH = %04x\n", mem_mask, mc68328->regs.stpwtch);
2512		return mc68328->regs.stpwtch;
2513
2514		default:
2515		verboselog(space.machine(), 0, "mc68328_r (%04x): Unknown address (0x%06x)\n", mem_mask, 0xfff000 + address);
2516		break;
2517		}
2518		return 0;
2519		}
2520
2521		static DEVICE_RESET( mc68328 )
2522		{
2523		mc68328_t* mc68328 = mc68328_get_safe_token( device );
2524
2525		mc68328->regs.scr = 0x0c;
2526		mc68328->regs.grpbasea = 0x0000;
2527		mc68328->regs.grpbaseb = 0x0000;
2528		mc68328->regs.grpbasec = 0x0000;
2529		mc68328->regs.grpbased = 0x0000;
2530		mc68328->regs.grpmaska = 0x0000;
2531		mc68328->regs.grpmaskb = 0x0000;
2532		mc68328->regs.grpmaskc = 0x0000;
2533		mc68328->regs.grpmaskd = 0x0000;
2534		mc68328->regs.csa0 = 0x00010006;
2535		mc68328->regs.csa1 = 0x00010006;
2536		mc68328->regs.csa2 = 0x00010006;
2537		mc68328->regs.csa3 = 0x00010006;
2538		mc68328->regs.csb0 = 0x00010006;
2539		mc68328->regs.csb1 = 0x00010006;
2540		mc68328->regs.csb2 = 0x00010006;
2541		mc68328->regs.csb3 = 0x00010006;
2542		mc68328->regs.csc0 = 0x00010006;
2543		mc68328->regs.csc1 = 0x00010006;
2544		mc68328->regs.csc2 = 0x00010006;
2545		mc68328->regs.csc3 = 0x00010006;
2546		mc68328->regs.csd0 = 0x00010006;
2547		mc68328->regs.csd1 = 0x00010006;
2548		mc68328->regs.csd2 = 0x00010006;
2549		mc68328->regs.csd3 = 0x00010006;
2550
2551		mc68328->regs.pllcr = 0x2400;
2552		mc68328->regs.pllfsr = 0x0123;
2553		mc68328->regs.pctlr = 0x1f;
2554
2555		mc68328->regs.ivr = 0x00;
2556		mc68328->regs.icr = 0x0000;
2557		mc68328->regs.imr = 0x00ffffff;
2558		mc68328->regs.iwr = 0x00ffffff;
2559		mc68328->regs.isr = 0x00000000;
2560		mc68328->regs.ipr = 0x00000000;
2561
2562		mc68328->regs.padir = 0x00;
2563		mc68328->regs.padata = 0x00;
2564		mc68328->regs.pasel = 0x00;
2565		mc68328->regs.pbdir = 0x00;
2566		mc68328->regs.pbdata = 0x00;
2567		mc68328->regs.pbsel = 0x00;
2568		mc68328->regs.pcdir = 0x00;
2569		mc68328->regs.pcdata = 0x00;
2570		mc68328->regs.pcsel = 0x00;
2571		mc68328->regs.pddir = 0x00;
2572		mc68328->regs.pddata = 0x00;
2573		mc68328->regs.pdpuen = 0xff;
2574		mc68328->regs.pdpol = 0x00;
2575		mc68328->regs.pdirqen = 0x00;
2576		mc68328->regs.pddataedge = 0x00;
2577		mc68328->regs.pdirqedge = 0x00;
2578		mc68328->regs.pedir = 0x00;
2579		mc68328->regs.pedata = 0x00;
2580		mc68328->regs.pepuen = 0x80;
2581		mc68328->regs.pesel = 0x80;
2582		mc68328->regs.pfdir = 0x00;
2583		mc68328->regs.pfdata = 0x00;
2584		mc68328->regs.pfpuen = 0xff;
2585		mc68328->regs.pfsel = 0xff;
2586		mc68328->regs.pgdir = 0x00;
2587		mc68328->regs.pgdata = 0x00;
2588		mc68328->regs.pgpuen = 0xff;
2589		mc68328->regs.pgsel = 0xff;
2590		mc68328->regs.pjdir = 0x00;
2591		mc68328->regs.pjdata = 0x00;
2592		mc68328->regs.pjsel = 0x00;
2593		mc68328->regs.pkdir = 0x00;
2594		mc68328->regs.pkdata = 0x00;
2595		mc68328->regs.pkpuen = 0xff;
2596		mc68328->regs.pksel = 0xff;
2597		mc68328->regs.pmdir = 0x00;
2598		mc68328->regs.pmdata = 0x00;
2599		mc68328->regs.pmpuen = 0xff;
2600		mc68328->regs.pmsel = 0xff;
2601
2602		mc68328->regs.pwmc = 0x0000;
2603		mc68328->regs.pwmp = 0x0000;
2604		mc68328->regs.pwmw = 0x0000;
2605		mc68328->regs.pwmcnt = 0x0000;
2606
2607		mc68328->regs.tctl[0] = mc68328->regs.tctl[1] = 0x0000;
2608		mc68328->regs.tprer[0] = mc68328->regs.tprer[1] = 0x0000;
2609		mc68328->regs.tcmp[0] = mc68328->regs.tcmp[1] = 0xffff;
2610		mc68328->regs.tcr[0] = mc68328->regs.tcr[1] = 0x0000;
2611		mc68328->regs.tcn[0] = mc68328->regs.tcn[1] = 0x0000;
2612		mc68328->regs.tstat[0] = mc68328->regs.tstat[1] = 0x0000;
2613		mc68328->regs.wctlr = 0x0000;
2614		mc68328->regs.wcmpr = 0xffff;
2615		mc68328->regs.wcn = 0x0000;
2616
2617		mc68328->regs.spisr = 0x0000;
2618
2619		mc68328->regs.spimdata = 0x0000;
2620		mc68328->regs.spimcont = 0x0000;
2621
2622		mc68328->regs.ustcnt = 0x0000;
2623		mc68328->regs.ubaud = 0x003f;
2624		mc68328->regs.urx = 0x0000;
2625		mc68328->regs.utx = 0x0000;
2626		mc68328->regs.umisc = 0x0000;
2627
2628		mc68328->regs.lssa = 0x00000000;
2629		mc68328->regs.lvpw = 0xff;
2630		mc68328->regs.lxmax = 0x03ff;
2631		mc68328->regs.lymax = 0x01ff;
2632		mc68328->regs.lcxp = 0x0000;
2633		mc68328->regs.lcyp = 0x0000;
2634		mc68328->regs.lcwch = 0x0101;
2635		mc68328->regs.lblkc = 0x7f;
2636		mc68328->regs.lpicf = 0x00;
2637		mc68328->regs.lpolcf = 0x00;
2638		mc68328->regs.lacdrc = 0x00;
2639		mc68328->regs.lpxcd = 0x00;
2640		mc68328->regs.lckcon = 0x40;
2641		mc68328->regs.llbar = 0x3e;
2642		mc68328->regs.lotcr = 0x3f;
2643		mc68328->regs.lposr = 0x00;
2644		mc68328->regs.lfrcm = 0xb9;
2645		mc68328->regs.lgpmr = 0x1073;
2646
2647		mc68328->regs.hmsr = 0x00000000;
2648		mc68328->regs.alarm = 0x00000000;
2649		mc68328->regs.rtcctl = 0x00;
2650		mc68328->regs.rtcisr = 0x00;
2651		mc68328->regs.rtcienr = 0x00;
2652		mc68328->regs.stpwtch = 0x00;
2653
2654		mc68328->rtc->adjust(attotime::from_hz(1), 0, attotime::from_hz(1));
2655		}
2656
2657		static void mc68328_register_state_save(device_t *device)
2658		{
2659		mc68328_t* mc68328 = mc68328_get_safe_token( device );
2660
2661		state_save_register_global(device->machine(), mc68328->regs.scr);
2662		state_save_register_global(device->machine(), mc68328->regs.grpbasea);
2663		state_save_register_global(device->machine(), mc68328->regs.grpbaseb);
2664		state_save_register_global(device->machine(), mc68328->regs.grpbasec);
2665		state_save_register_global(device->machine(), mc68328->regs.grpbased);
2666		state_save_register_global(device->machine(), mc68328->regs.grpmaska);
2667		state_save_register_global(device->machine(), mc68328->regs.grpmaskb);
2668		state_save_register_global(device->machine(), mc68328->regs.grpmaskc);
2669		state_save_register_global(device->machine(), mc68328->regs.grpmaskd);
2670		state_save_register_global(device->machine(), mc68328->regs.csa0);
2671		state_save_register_global(device->machine(), mc68328->regs.csa1);
2672		state_save_register_global(device->machine(), mc68328->regs.csa2);
2673		state_save_register_global(device->machine(), mc68328->regs.csa3);
2674		state_save_register_global(device->machine(), mc68328->regs.csb0);
2675		state_save_register_global(device->machine(), mc68328->regs.csb1);
2676		state_save_register_global(device->machine(), mc68328->regs.csb2);
2677		state_save_register_global(device->machine(), mc68328->regs.csb3);
2678		state_save_register_global(device->machine(), mc68328->regs.csc0);
2679		state_save_register_global(device->machine(), mc68328->regs.csc1);
2680		state_save_register_global(device->machine(), mc68328->regs.csc2);
2681		state_save_register_global(device->machine(), mc68328->regs.csc3);
2682		state_save_register_global(device->machine(), mc68328->regs.csd0);
2683		state_save_register_global(device->machine(), mc68328->regs.csd1);
2684		state_save_register_global(device->machine(), mc68328->regs.csd2);
2685		state_save_register_global(device->machine(), mc68328->regs.csd3);
2686
2687		state_save_register_global(device->machine(), mc68328->regs.pllcr);
2688		state_save_register_global(device->machine(), mc68328->regs.pllfsr);
2689		state_save_register_global(device->machine(), mc68328->regs.pctlr);
2690
2691		state_save_register_global(device->machine(), mc68328->regs.ivr);
2692		state_save_register_global(device->machine(), mc68328->regs.icr);
2693		state_save_register_global(device->machine(), mc68328->regs.imr);
2694		state_save_register_global(device->machine(), mc68328->regs.iwr);
2695		state_save_register_global(device->machine(), mc68328->regs.isr);
2696		state_save_register_global(device->machine(), mc68328->regs.ipr);
2697
2698		state_save_register_global(device->machine(), mc68328->regs.padir);
2699		state_save_register_global(device->machine(), mc68328->regs.padata);
2700		state_save_register_global(device->machine(), mc68328->regs.pasel);
2701		state_save_register_global(device->machine(), mc68328->regs.pbdir);
2702		state_save_register_global(device->machine(), mc68328->regs.pbdata);
2703		state_save_register_global(device->machine(), mc68328->regs.pbsel);
2704		state_save_register_global(device->machine(), mc68328->regs.pcdir);
2705		state_save_register_global(device->machine(), mc68328->regs.pcdata);
2706		state_save_register_global(device->machine(), mc68328->regs.pcsel);
2707		state_save_register_global(device->machine(), mc68328->regs.pddir);
2708		state_save_register_global(device->machine(), mc68328->regs.pddata);
2709		state_save_register_global(device->machine(), mc68328->regs.pdpuen);
2710		state_save_register_global(device->machine(), mc68328->regs.pdpol);
2711		state_save_register_global(device->machine(), mc68328->regs.pdirqen);
2712		state_save_register_global(device->machine(), mc68328->regs.pddataedge);
2713		state_save_register_global(device->machine(), mc68328->regs.pdirqedge);
2714		state_save_register_global(device->machine(), mc68328->regs.pedir);
2715		state_save_register_global(device->machine(), mc68328->regs.pedata);
2716		state_save_register_global(device->machine(), mc68328->regs.pepuen);
2717		state_save_register_global(device->machine(), mc68328->regs.pesel);
2718		state_save_register_global(device->machine(), mc68328->regs.pfdir);
2719		state_save_register_global(device->machine(), mc68328->regs.pfdata);
2720		state_save_register_global(device->machine(), mc68328->regs.pfpuen);
2721		state_save_register_global(device->machine(), mc68328->regs.pfsel);
2722		state_save_register_global(device->machine(), mc68328->regs.pgdir);
2723		state_save_register_global(device->machine(), mc68328->regs.pgdata);
2724		state_save_register_global(device->machine(), mc68328->regs.pgpuen);
2725		state_save_register_global(device->machine(), mc68328->regs.pgsel);
2726		state_save_register_global(device->machine(), mc68328->regs.pjdir);
2727		state_save_register_global(device->machine(), mc68328->regs.pjdata);
2728		state_save_register_global(device->machine(), mc68328->regs.pjsel);
2729		state_save_register_global(device->machine(), mc68328->regs.pkdir);
2730		state_save_register_global(device->machine(), mc68328->regs.pkdata);
2731		state_save_register_global(device->machine(), mc68328->regs.pkpuen);
2732		state_save_register_global(device->machine(), mc68328->regs.pksel);
2733		state_save_register_global(device->machine(), mc68328->regs.pmdir);
2734		state_save_register_global(device->machine(), mc68328->regs.pmdata);
2735		state_save_register_global(device->machine(), mc68328->regs.pmpuen);
2736		state_save_register_global(device->machine(), mc68328->regs.pmsel);
2737
2738		state_save_register_global(device->machine(), mc68328->regs.pwmc);
2739		state_save_register_global(device->machine(), mc68328->regs.pwmp);
2740		state_save_register_global(device->machine(), mc68328->regs.pwmw);
2741		state_save_register_global(device->machine(), mc68328->regs.pwmcnt);
2742
2743		state_save_register_global(device->machine(), mc68328->regs.tctl[0]);
2744		state_save_register_global(device->machine(), mc68328->regs.tctl[1]);
2745		state_save_register_global(device->machine(), mc68328->regs.tprer[0]);
2746		state_save_register_global(device->machine(), mc68328->regs.tprer[1]);
2747		state_save_register_global(device->machine(), mc68328->regs.tcmp[0]);
2748		state_save_register_global(device->machine(), mc68328->regs.tcmp[1]);
2749		state_save_register_global(device->machine(), mc68328->regs.tcr[0]);
2750		state_save_register_global(device->machine(), mc68328->regs.tcr[1]);
2751		state_save_register_global(device->machine(), mc68328->regs.tcn[0]);
2752		state_save_register_global(device->machine(), mc68328->regs.tcn[1]);
2753		state_save_register_global(device->machine(), mc68328->regs.tstat[0]);
2754		state_save_register_global(device->machine(), mc68328->regs.tstat[1]);
2755		state_save_register_global(device->machine(), mc68328->regs.wctlr);
2756		state_save_register_global(device->machine(), mc68328->regs.wcmpr);
2757		state_save_register_global(device->machine(), mc68328->regs.wcn);
2758
2759		state_save_register_global(device->machine(), mc68328->regs.spisr);
2760
2761		state_save_register_global(device->machine(), mc68328->regs.spimdata);
2762		state_save_register_global(device->machine(), mc68328->regs.spimcont);
2763
2764		state_save_register_global(device->machine(), mc68328->regs.ustcnt);
2765		state_save_register_global(device->machine(), mc68328->regs.ubaud);
2766		state_save_register_global(device->machine(), mc68328->regs.urx);
2767		state_save_register_global(device->machine(), mc68328->regs.utx);
2768		state_save_register_global(device->machine(), mc68328->regs.umisc);
2769
2770		state_save_register_global(device->machine(), mc68328->regs.lssa);
2771		state_save_register_global(device->machine(), mc68328->regs.lvpw);
2772		state_save_register_global(device->machine(), mc68328->regs.lxmax);
2773		state_save_register_global(device->machine(), mc68328->regs.lymax);
2774		state_save_register_global(device->machine(), mc68328->regs.lcxp);
2775		state_save_register_global(device->machine(), mc68328->regs.lcyp);
2776		state_save_register_global(device->machine(), mc68328->regs.lcwch);
2777		state_save_register_global(device->machine(), mc68328->regs.lblkc);
2778		state_save_register_global(device->machine(), mc68328->regs.lpicf);
2779		state_save_register_global(device->machine(), mc68328->regs.lpolcf);
2780		state_save_register_global(device->machine(), mc68328->regs.lacdrc);
2781		state_save_register_global(device->machine(), mc68328->regs.lpxcd);
2782		state_save_register_global(device->machine(), mc68328->regs.lckcon);
2783		state_save_register_global(device->machine(), mc68328->regs.llbar);
2784		state_save_register_global(device->machine(), mc68328->regs.lotcr);
2785		state_save_register_global(device->machine(), mc68328->regs.lposr);
2786		state_save_register_global(device->machine(), mc68328->regs.lfrcm);
2787		state_save_register_global(device->machine(), mc68328->regs.lgpmr);
2788
2789		state_save_register_global(device->machine(), mc68328->regs.hmsr);
2790		state_save_register_global(device->machine(), mc68328->regs.alarm);
2791		state_save_register_global(device->machine(), mc68328->regs.rtcctl);
2792		state_save_register_global(device->machine(), mc68328->regs.rtcisr);
2793		state_save_register_global(device->machine(), mc68328->regs.rtcienr);
2794		state_save_register_global(device->machine(), mc68328->regs.stpwtch);
2795		}
2796
2797		static DEVICE_START( mc68328 )
2798		{
2799		mc68328_t* mc68328 = mc68328_get_safe_token( device );
2800
2801		mc68328->iface = (const mc68328_interface*)device->static_config();
2802
2803		mc68328->out_port_a.resolve(mc68328->iface->out_port_a_func, *device);
2804		mc68328->out_port_b.resolve(mc68328->iface->out_port_b_func, *device);
2805		mc68328->out_port_c.resolve(mc68328->iface->out_port_c_func, *device);
2806		mc68328->out_port_d.resolve(mc68328->iface->out_port_d_func, *device);
2807		mc68328->out_port_e.resolve(mc68328->iface->out_port_e_func, *device);
2808		mc68328->out_port_f.resolve(mc68328->iface->out_port_f_func, *device);
2809		mc68328->out_port_g.resolve(mc68328->iface->out_port_g_func, *device);
2810		mc68328->out_port_j.resolve(mc68328->iface->out_port_j_func, *device);
2811		mc68328->out_port_k.resolve(mc68328->iface->out_port_k_func, *device);
2812		mc68328->out_port_m.resolve(mc68328->iface->out_port_m_func, *device);
2813
2814		mc68328->in_port_a.resolve(mc68328->iface->in_port_a_func, *device);
2815		mc68328->in_port_b.resolve(mc68328->iface->in_port_b_func, *device);
2816		mc68328->in_port_c.resolve(mc68328->iface->in_port_c_func, *device);
2817		mc68328->in_port_d.resolve(mc68328->iface->in_port_d_func, *device);
2818		mc68328->in_port_e.resolve(mc68328->iface->in_port_e_func, *device);
2819		mc68328->in_port_f.resolve(mc68328->iface->in_port_f_func, *device);
2820		mc68328->in_port_g.resolve(mc68328->iface->in_port_g_func, *device);
2821		mc68328->in_port_j.resolve(mc68328->iface->in_port_j_func, *device);
2822		mc68328->in_port_k.resolve(mc68328->iface->in_port_k_func, *device);
2823		mc68328->in_port_m.resolve(mc68328->iface->in_port_m_func, *device);
2824
2825		mc68328->out_pwm.resolve(mc68328->iface->out_pwm_func, *device);
2826
2827		mc68328->out_spim.resolve(mc68328->iface->out_spim_func, *device);
2828		mc68328->in_spim.resolve(mc68328->iface->in_spim_func, *device);
2829
2830		mc68328->gptimer[0] = device->machine().scheduler().timer_alloc(FUNC(mc68328_timer1_hit));
2831		mc68328->gptimer[1] = device->machine().scheduler().timer_alloc(FUNC(mc68328_timer2_hit));
2832		mc68328->rtc = device->machine().scheduler().timer_alloc(FUNC(mc68328_rtc_tick));
2833		mc68328->pwm = device->machine().scheduler().timer_alloc(FUNC(mc68328_pwm_transition));
2834
2835		mc68328_register_state_save(device);
2836		}
2837
2838		const device_type MC68328 = &device_creator<mc68328_device>;
2839
2840		mc68328_device::mc68328_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
2841		: device_t(mconfig, MC68328, "Motorola MC68328 (DragonBall) Integrated Processor", tag, owner, clock)
2842		{
2843		m_token = global_alloc_clear(mc68328_t);
2844		}
2845
2846		//-------------------------------------------------
2847		// device_config_complete - perform any
2848		// operations now that the configuration is
2849		// complete
2850		//-------------------------------------------------
2851
2852		void mc68328_device::device_config_complete()
2853		{
2854		}
2855
2856		//-------------------------------------------------
2857		// device_start - device-specific startup
2858		//-------------------------------------------------
2859
2860		void mc68328_device::device_start()
2861		{
2862		DEVICE_START_NAME( mc68328 )(this);
2863		}
2864
2865		//-------------------------------------------------
2866		// device_reset - device-specific reset
2867		//-------------------------------------------------
2868
2869		void mc68328_device::device_reset()
2870		{
2871		DEVICE_RESET_NAME( mc68328 )(this);
2872		}

trunk/src/emu/machine/mc68328.h
r21688	r21689
1		/**********************************************************************
2
3		Motorola 68328 ("DragonBall") System-on-a-Chip implementation
4
5		By MooglyGuy
6		contact mooglyguy@gmail.com with licensing and usage questions.
7
8		**********************************************************************/
9
10		/*****************************************************************************************************************
11
12		P P P P P P P P P P P P P P
13		E E E E E E E J J J J J J J
14		1 2 3 4 5 6 7 0 1 2 3 4 5 6
15		D D D D D / / / / / / / / / / / / / /
16		3 4 5 6 7 ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
17		/ / / / / ! ! C C C C C C C C C C C C C C C
18		P V P P P P D D G D D D D T T L U V S S S S S S S S G S S S S S S S
19		B C B B B B D D 1 1 N 1 1 1 1 M C W W C A A A A B B B B N C C C C D D D
20		3 C 4 5 6 7 8 9 0 1 D 2 3 4 5 S K E E C 0 1 2 3 0 1 2 3 D 0 1 2 3 0 1 2
21		\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|
22		+-------------------------------------------------------------------------------+
23		\| \|
24		\| \|
25		\| \|
26		\| \|
27		\| \|
28		D2/PB2--\| \|--PJ7/!CSD3
29		D1/PB1--\| \|--VCC
30		D0/PB0--\| \|--PD0/!KBD0/!INT0
31		TDO--\| \|--PD1/!KBD1/!INT1
32		TDI--\| \|--PD2/!KBD2/!INT2
33		GND--\| \|--PD3/!KBD3/!INT3
34		!OE--\| \|--PD4/!KBD4/!INT4
35		!UDS/PC1--\| \|--PD5/!KBD5/!INT5
36		!AS--\| \|--PD6/!KBD6/!INT6
37		A0--\| \|--PD7/!KBD7/!INT7
38		!LDS--\| \|--GND
39		R/!W--\| \|--LD0
40		!DTACK/PC5--\| \|--LD1
41		!RESET--\| \|--LD2
42		VCC--\| \|--LD3
43		!WE/PC6--\| \|--LFRM
44		!JTAGRST--\| \|--LLP
45		BBUSW--\| MC68328PV \|--LCLK
46		A1--\| TOP VIEW \|--LACD
47		A2--\| \|--VCC
48		A3--\| \|--PK0/SPMTXD0
49		A4--\| \|--PK1/SPMRXD0
50		A5--\| \|--PK2/SPMCLK0
51		A6--\| \|--PK3/SPSEN
52		GND--\| \|--PK4/SPSRXD1
53		A7--\| \|--PK5/SPSCLK1
54		A8--\| \|--PK6/!CE2
55		A9--\| \|--PK7/!CE1
56		A10--\| \|--GND
57		A11--\| \|--PM0/!CTS
58		A12--\| \|--PM1/!RTS
59		A13--\| \|--PM2/!IRQ6
60		A14--\| \|--PM3/!IRQ3
61		VCC--\| \|--PM4/!IRQ2
62		A15--\| \|--PM5/!IRQ1
63		A16/PA0--\| \|--PM6/!PENIRQ
64		\| \|
65		\| _ \|
66		\| (_) \|
67		\|\ \|
68		\| \ \|
69		+-------------------------------------------------------------------------------+
70		\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|
71		P P P P P G P P P P P P P P V P P P P P P P P G P P P V C G P P P E X P
72		A A A A A N A A F F F F F F C F F G G G G G G N G G C C L N C M L X T L
73		1 2 3 4 5 D 6 7 0 1 2 3 4 5 C 6 7 7 6 5 4 3 2 D 1 0 0 C K D 4 7 L T A L
74		/ / / / / / / / / / / / / / / / / / / / / / / / O / / G A L V
75		A A A A A A A A A A A A A A A R T ! T ! P R T M ! U N L C
76		1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 T I T I T W X X O I A D C
77		7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 C N O N O M D D C R R
78		O 1 U 2 U O L Q T
79		T T K 7 G
80		1 2 P
81		I
82		O
83
84		Figure 12-1. MC68328 144-Lead Plastic Thin-Quad Flat Pack Pin Assignment
85
86		Source: MC68328 (DragonBall)(tm) Integrated Processor User's Manual
87
88		*****************************************************************************************************************/
89
90		#ifndef __MC68328_H_
91		#define __MC68328_H_
92
93		/***************************************************************************
94		TYPE DEFINITIONS
95		***************************************************************************/
96
97		struct mc68328_interface
98		{
99		const char *m68k_cpu_tag;
100
101		devcb_write8 out_port_a_func; /* 8-bit output */
102		devcb_write8 out_port_b_func; /* 8-bit output */
103		devcb_write8 out_port_c_func; /* 8-bit output */
104		devcb_write8 out_port_d_func; /* 8-bit output */
105		devcb_write8 out_port_e_func; /* 8-bit output */
106		devcb_write8 out_port_f_func; /* 8-bit output */
107		devcb_write8 out_port_g_func; /* 8-bit output */
108		devcb_write8 out_port_j_func; /* 8-bit output */
109		devcb_write8 out_port_k_func; /* 8-bit output */
110		devcb_write8 out_port_m_func; /* 8-bit output */
111
112		devcb_read8 in_port_a_func; /* 8-bit input */
113		devcb_read8 in_port_b_func; /* 8-bit input */
114		devcb_read8 in_port_c_func; /* 8-bit input */
115		devcb_read8 in_port_d_func; /* 8-bit input */
116		devcb_read8 in_port_e_func; /* 8-bit input */
117		devcb_read8 in_port_f_func; /* 8-bit input */
118		devcb_read8 in_port_g_func; /* 8-bit input */
119		devcb_read8 in_port_j_func; /* 8-bit input */
120		devcb_read8 in_port_k_func; /* 8-bit input */
121		devcb_read8 in_port_m_func; /* 8-bit input */
122
123		devcb_write8 out_pwm_func; /* 1-bit output */
124
125		devcb_write16 out_spim_func; /* 16-bit output */
126		devcb_read16 in_spim_func; /* 16-bit input */
127		void (spim_xch_trigger)( device_t device ); /* SPIM exchange trigger */
128		};
129		#define MC68328_INTERFACE(name) const mc68328_interface (name)=
130
131		#define MC68328_TAG "dragonball"
132
133		/***************************************************************************
134		DEVICE CONFIGURATION MACROS
135		***************************************************************************/
136
137		#define MCFG_MC68328_ADD(_intrf) \
138		MCFG_DEVICE_ADD("dragonball", MC68328, 0) \
139		MCFG_DEVICE_CONFIG(_intrf)
140
141		/----------- defined in machine/mc68328.c -----------/
142
143		/***************************************************************************
144		READ/WRITE HANDLERS
145		***************************************************************************/
146
147		DECLARE_WRITE16_DEVICE_HANDLER( mc68328_w );
148		DECLARE_READ16_DEVICE_HANDLER( mc68328_r );
149
150
151		/***************************************************************************
152		EXTERNAL I/O LINES
153		***************************************************************************/
154
155		void mc68328_set_penirq_line(device_t *device, int state);
156		void mc68328_set_port_d_lines(device_t *device, UINT8 state, int bit);
157
158		/***************************************************************************
159		DEVICE INTERFACE
160		***************************************************************************/
161
162		class mc68328_device : public device_t
163		{
164		public:
165		mc68328_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
166		~mc68328_device() { global_free(m_token); }
167
168		// access to legacy token
169		void *token() const { assert(m_token != NULL); return m_token; }
170		protected:
171		// device-level overrides
172		virtual void device_config_complete();
173		virtual void device_start();
174		virtual void device_reset();
175		private:
176		// internal state
177		void *m_token;
178		};
179
180		extern const device_type MC68328;
181
182
183		/----------- defined in video/mc68328.c -----------/
184
185		/***************************************************************************
186		VIDEO INTERFACE
187		***************************************************************************/
188
189		PALETTE_INIT( mc68328 );
190		VIDEO_START( mc68328 );
191		SCREEN_UPDATE_IND16( mc68328 );
192
193		#endif // __MC68328_H_

trunk/src/emu/machine/mc68328p.h
r21688	r21689
1		/**********************************************************************
2
3		Motorola 68328 ("DragonBall") System-on-a-Chip private data
4
5		By MooglyGuy
6		contact mooglyguy@gmail.com with licensing and usage questions.
7
8		**********************************************************************/
9
10		#ifndef __MC68328_PRIVATE_H_
11		#define __MC68328_PRIVATE_H_
12
13		struct mc68328_regs_t
14		{
15		// $(FF)FFF000
16		UINT8 scr; // System Control Register
17		UINT8 unused0[255];
18
19		// $(FF)FFF100
20		UINT16 grpbasea; // Chip Select Group A Base Register
21		UINT16 grpbaseb; // Chip Select Group B Base Register
22		UINT16 grpbasec; // Chip Select Group C Base Register
23		UINT16 grpbased; // Chip Select Group D Base Register
24		UINT16 grpmaska; // Chip Select Group A Mask Register
25		UINT16 grpmaskb; // Chip Select Group B Mask Register
26		UINT16 grpmaskc; // Chip Select Group C Mask Register
27		UINT16 grpmaskd; // Chip Select Group D Mask Register
28		UINT32 csa0; // Group A Chip Select 0 Register
29		UINT32 csa1; // Group A Chip Select 1 Register
30		UINT32 csa2; // Group A Chip Select 2 Register
31		UINT32 csa3; // Group A Chip Select 3 Register
32		UINT32 csb0; // Group B Chip Select 0 Register
33		UINT32 csb1; // Group B Chip Select 1 Register
34		UINT32 csb2; // Group B Chip Select 2 Register
35		UINT32 csb3; // Group B Chip Select 3 Register
36		UINT32 csc0; // Group C Chip Select 0 Register
37		UINT32 csc1; // Group C Chip Select 1 Register
38		UINT32 csc2; // Group C Chip Select 2 Register
39		UINT32 csc3; // Group C Chip Select 3 Register
40		UINT32 csd0; // Group D Chip Select 0 Register
41		UINT32 csd1; // Group D Chip Select 1 Register
42		UINT32 csd2; // Group D Chip Select 2 Register
43		UINT32 csd3; // Group D Chip Select 3 Register
44		UINT8 unused1[176];
45
46		// $(FF)FFF200
47		UINT16 pllcr; // PLL Control Register
48		UINT16 pllfsr; // PLL Frequency Select Register
49		UINT8 pad2[3];
50		UINT8 pctlr; // Power Control Register
51		UINT8 unused3[248];
52
53		// $(FF)FFF300
54		UINT8 ivr; // Interrupt Vector Register
55		UINT8 unused4[1];
56		UINT16 icr; // Interrupt Control Register
57		UINT32 imr; // Interrupt Mask Register
58		UINT32 iwr; // Interrupt Wakeup Enable Register
59		UINT32 isr; // Interrupt Status Register
60		UINT32 ipr; // Interrupt Pending Register
61		UINT8 unused5[236];
62
63		// $(FF)FFF400
64		UINT8 padir; // Port A Direction Register
65		UINT8 padata; // Port A Data Register
66		UINT8 unused6[1];
67		UINT8 pasel; // Port A Select Register
68		UINT8 unused7[4];
69
70		UINT8 pbdir; // Port B Direction Register
71		UINT8 pbdata; // Port B Data Register
72		UINT8 unused8[1];
73		UINT8 pbsel; // Port B Select Register
74		UINT8 unused9[4];
75
76		UINT8 pcdir; // Port C Direction Register
77		UINT8 pcdata; // Port C Data Register
78		UINT8 unused10[1];
79		UINT8 pcsel; // Port C Select Register
80		UINT8 unused11[4];
81
82		UINT8 pddir; // Port D Direction Register
83		UINT8 pddata; // Port D Data Register
84		UINT8 pdpuen; // Port D Pullup Enable Register
85		UINT8 unused12[1];
86		UINT8 pdpol; // Port D Polarity Register
87		UINT8 pdirqen; // Port D IRQ Enable Register
88		UINT8 pddataedge; // Port D Data Edge Level
89		UINT8 pdirqedge; // Port D IRQ Edge Register
90
91		UINT8 pedir; // Port E Direction Register
92		UINT8 pedata; // Port E Data Register
93		UINT8 pepuen; // Port E Pullup Enable Register
94		UINT8 pesel; // Port E Select Register
95		UINT8 unused14[4];
96
97		UINT8 pfdir; // Port F Direction Register
98		UINT8 pfdata; // Port F Data Register
99		UINT8 pfpuen; // Port F Pullup Enable Register
100		UINT8 pfsel; // Port F Select Register
101		UINT8 unused15[4];
102
103		UINT8 pgdir; // Port G Direction Register
104		UINT8 pgdata; // Port G Data Register
105		UINT8 pgpuen; // Port G Pullup Enable Register
106		UINT8 pgsel; // Port G Select Register
107		UINT8 unused16[4];
108
109		UINT8 pjdir; // Port J Direction Register
110		UINT8 pjdata; // Port J Data Register
111		UINT8 unused17[1];
112		UINT8 pjsel; // Port J Select Register
113		UINT8 unused18[4];
114		UINT8 pkdir; // Port K Direction Register
115		UINT8 pkdata; // Port K Data Register
116		UINT8 pkpuen; // Port K Pullup Enable Register
117		UINT8 pksel; // Port K Select Register
118		UINT8 unused19[4];
119
120		UINT8 pmdir; // Port M Direction Register
121		UINT8 pmdata; // Port M Data Register
122		UINT8 pmpuen; // Port M Pullup Enable Register
123		UINT8 pmsel; // Port M Select Register
124		UINT8 unused20[180];
125
126		// $(FF)FFF500
127		UINT16 pwmc; // PWM Control Register
128		UINT16 pwmp; // PWM Period Register
129		UINT16 pwmw; // PWM Width Register
130		UINT16 pwmcnt; // PWN Counter
131		UINT8 unused21[248];
132
133		// $(FF)FFF600
134		UINT16 tctl[2]; // Timer Control Register
135		UINT16 tprer[2]; // Timer Prescaler Register
136		UINT16 tcmp[2]; // Timer Compare Register
137		UINT16 tcr[2]; // Timer Capture Register
138		UINT16 tcn[2]; // Timer Counter
139		UINT16 tstat[2]; // Timer Status
140		UINT16 wctlr; // Watchdog Control Register
141		UINT16 wcmpr; // Watchdog Compare Register
142		UINT16 wcn; // Watchdog Counter
143		UINT8 tclear[2]; // Timer Clearable Status
144		UINT8 unused22[224];
145
146		// $(FF)FFF700
147		UINT16 spisr; // SPIS Register
148		UINT8 unused23[254];
149
150		// $(FF)FFF800
151		UINT16 spimdata; // SPIM Data Register
152		UINT16 spimcont; // SPIM Control/Status Register
153		UINT8 unused24[252];
154
155		// $(FF)FFF900
156		UINT16 ustcnt; // UART Status/Control Register
157		UINT16 ubaud; // UART Baud Control Register
158		UINT16 urx; // UART RX Register
159		UINT16 utx; // UART TX Register
160		UINT16 umisc; // UART Misc Register
161		UINT8 unused25[246];
162
163		// $(FF)FFFA00
164		UINT32 lssa; // Screen Starting Address Register
165		UINT8 unused26[1];
166		UINT8 lvpw; // Virtual Page Width Register
167		UINT8 unused27[2];
168		UINT16 lxmax; // Screen Width Register
169		UINT16 lymax; // Screen Height Register
170		UINT8 unused28[12];
171		UINT16 lcxp; // Cursor X Position
172		UINT16 lcyp; // Cursor Y Position
173		UINT16 lcwch; // Cursor Width & Height Register
174		UINT8 unused29[1];
175		UINT8 lblkc; // Blink Control Register
176		UINT8 lpicf; // Panel Interface Config Register
177		UINT8 lpolcf; // Polarity Config Register
178		UINT8 unused30[1];
179		UINT8 lacdrc; // ACD (M) Rate Control Register
180		UINT8 unused31[1];
181		UINT8 lpxcd; // Pixel Clock Divider Register
182		UINT8 unused32[1];
183		UINT8 lckcon; // Clocking Control Register
184		UINT8 unused33[1];
185		UINT8 llbar; // Last Buffer Address Register
186		UINT8 unused34[1];
187		UINT8 lotcr; // Octet Terminal Count Register
188		UINT8 unused35[1];
189		UINT8 lposr; // Panning Offset Register
190		UINT8 unused36[3];
191		UINT8 lfrcm; // Frame Rate Control Modulation Register
192		UINT16 lgpmr; // Gray Palette Mapping Register
193		UINT8 unused37[204];
194
195		// $(FF)FFFB00
196		UINT32 hmsr; // RTC Hours Minutes Seconds Register
197		UINT32 alarm; // RTC Alarm Register
198		UINT8 unused38[4];
199		UINT16 rtcctl; // RTC Control Register
200		UINT16 rtcisr; // RTC Interrupt Status Register
201		UINT16 rtcienr; // RTC Interrupt Enable Register
202		UINT16 stpwtch; // Stopwatch Minutes
203		UINT8 unused42[1260];
204		};
205
206		struct mc68328_t
207		{
208		const mc68328_interface* iface;
209
210		mc68328_regs_t regs;
211
212		emu_timer *gptimer[2];
213		emu_timer *rtc;
214		emu_timer *pwm;
215
216		devcb_resolved_write8 out_port_a; /* 8-bit output */
217		devcb_resolved_write8 out_port_b; /* 8-bit output */
218		devcb_resolved_write8 out_port_c; /* 8-bit output */
219		devcb_resolved_write8 out_port_d; /* 8-bit output */
220		devcb_resolved_write8 out_port_e; /* 8-bit output */
221		devcb_resolved_write8 out_port_f; /* 8-bit output */
222		devcb_resolved_write8 out_port_g; /* 8-bit output */
223		devcb_resolved_write8 out_port_j; /* 8-bit output */
224		devcb_resolved_write8 out_port_k; /* 8-bit output */
225		devcb_resolved_write8 out_port_m; /* 8-bit output */
226
227		devcb_resolved_read8 in_port_a; /* 8-bit input */
228		devcb_resolved_read8 in_port_b; /* 8-bit input */
229		devcb_resolved_read8 in_port_c; /* 8-bit input */
230		devcb_resolved_read8 in_port_d; /* 8-bit input */
231		devcb_resolved_read8 in_port_e; /* 8-bit input */
232		devcb_resolved_read8 in_port_f; /* 8-bit input */
233		devcb_resolved_read8 in_port_g; /* 8-bit input */
234		devcb_resolved_read8 in_port_j; /* 8-bit input */
235		devcb_resolved_read8 in_port_k; /* 8-bit input */
236		devcb_resolved_read8 in_port_m; /* 8-bit input */
237
238		devcb_resolved_write8 out_pwm; /* 1-bit output */
239
240		devcb_resolved_write16 out_spim; /* 16-bit output */
241		devcb_resolved_read16 in_spim; /* 16-bit input */
242		};
243
244		#define SCR_BETO 0x80
245		#define SCR_WPV 0x40
246		#define SCR_PRV 0x20
247		#define SCR_BETEN 0x10
248		#define SCR_SO 0x08
249		#define SCR_DMAP 0x04
250		#define SCR_WDTH8 0x01
251
252		#define ICR_POL6 0x0100
253		#define ICR_POL3 0x0200
254		#define ICR_POL2 0x0400
255		#define ICR_POL1 0x0800
256		#define ICR_ET6 0x1000
257		#define ICR_ET3 0x2000
258		#define ICR_ET2 0x4000
259		#define ICR_ET1 0x8000
260
261		#define INT_SPIM 0x000001
262		#define INT_TIMER2 0x000002
263		#define INT_UART 0x000004
264		#define INT_WDT 0x000008
265		#define INT_RTC 0x000010
266		#define INT_RESERVED 0x000020
267		#define INT_KB 0x000040
268		#define INT_PWM 0x000080
269		#define INT_INT0 0x000100
270		#define INT_INT1 0x000200
271		#define INT_INT2 0x000400
272		#define INT_INT3 0x000800
273		#define INT_INT4 0x001000
274		#define INT_INT5 0x002000
275		#define INT_INT6 0x004000
276		#define INT_INT7 0x008000
277		#define INT_KBDINTS 0x00ff00
278		#define INT_IRQ1 0x010000
279		#define INT_IRQ2 0x020000
280		#define INT_IRQ3 0x040000
281		#define INT_IRQ6 0x080000
282		#define INT_PEN 0x100000
283		#define INT_SPIS 0x200000
284		#define INT_TIMER1 0x400000
285		#define INT_IRQ7 0x800000
286
287		#define INT_M68K_LINE1 (INT_IRQ1)
288		#define INT_M68K_LINE2 (INT_IRQ2)
289		#define INT_M68K_LINE3 (INT_IRQ3)
290		#define INT_M68K_LINE4 (INT_INT0 \| INT_INT1 \| INT_INT2 \| INT_INT3 \| INT_INT4 \| INT_INT5 \| INT_INT6 \| INT_INT7 \| \
291		INT_PWM \| INT_KB \| INT_RTC \| INT_WDT \| INT_UART \| INT_TIMER2 \| INT_SPIM)
292		#define INT_M68K_LINE5 (INT_PEN)
293		#define INT_M68K_LINE6 (INT_IRQ6 \| INT_TIMER1 \| INT_SPIS)
294		#define INT_M68K_LINE7 (INT_IRQ7)
295		#define INT_M68K_LINE67 (INT_M68K_LINE6 \| INT_M68K_LINE7)
296		#define INT_M68K_LINE567 (INT_M68K_LINE5 \| INT_M68K_LINE6 \| INT_M68K_LINE7)
297		#define INT_M68K_LINE4567 (INT_M68K_LINE4 \| INT_M68K_LINE5 \| INT_M68K_LINE6 \| INT_M68K_LINE7)
298		#define INT_M68K_LINE34567 (INT_M68K_LINE3 \| INT_M68K_LINE4 \| INT_M68K_LINE5 \| INT_M68K_LINE6 \| INT_M68K_LINE7)
299		#define INT_M68K_LINE234567 (INT_M68K_LINE2 \| INT_M68K_LINE3 \| INT_M68K_LINE4 \| INT_M68K_LINE5 \| INT_M68K_LINE6 \| INT_M68K_LINE7)
300
301		#define INT_IRQ1_SHIFT 0x000001
302		#define INT_IRQ2_SHIFT 0x000002
303		#define INT_IRQ3_SHIFT 0x000004
304		#define INT_IRQ6_SHIFT 0x000008
305		#define INT_PEN_SHIFT 0x000010
306		#define INT_SPIS_SHIFT 0x000020
307		#define INT_TIMER1_SHIFT 0x000040
308		#define INT_IRQ7_SHIFT 0x000080
309
310		#define INT_ACTIVE 1
311		#define INT_INACTIVE 0
312
313		#define GRPBASE_BASE_ADDR 0xfff0
314		#define GRPBASE_VALID 0x0001
315
316		#define GRPMASK_BASE_MASK 0xfff0
317
318		#define CSAB_COMPARE 0xff000000
319		#define CSAB_BSW 0x00010000
320		#define CSAB_MASK 0x0000ff00
321		#define CSAB_RO 0x00000008
322		#define CSAB_WAIT 0x00000007
323
324		#define CSCD_COMPARE 0xfff00000
325		#define CSCD_BSW 0x00010000
326		#define CSCD_MASK 0x0000fff0
327		#define CSCD_RO 0x00000008
328		#define CSCD_WAIT 0x00000007
329
330		#define PLLCR_PIXCLK_SEL 0x3800
331		#define PLLCR_PIXCLK_SEL_DIV2 0x0000
332		#define PLLCR_PIXCLK_SEL_DIV4 0x0800
333		#define PLLCR_PIXCLK_SEL_DIV8 0x1000
334		#define PLLCR_PIXCLK_SEL_DIV16 0x1800
335		#define PLLCR_PIXCLK_SEL_DIV1_0 0x2000
336		#define PLLCR_PIXCLK_SEL_DIV1_1 0x2800
337		#define PLLCR_PIXCLK_SEL_DIV1_2 0x3000
338		#define PLLCR_PIXCLK_SEL_DIV1_3 0x3800
339		#define PLLCR_SYSCLK_SEL 0x0700
340		#define PLLCR_SYSCLK_SEL_DIV2 0x0000
341		#define PLLCR_SYSCLK_SEL_DIV4 0x0100
342		#define PLLCR_SYSCLK_SEL_DIV8 0x0200
343		#define PLLCR_SYSCLK_SEL_DIV16 0x0300
344		#define PLLCR_SYSCLK_SEL_DIV1_0 0x0400
345		#define PLLCR_SYSCLK_SEL_DIV1_1 0x0500
346		#define PLLCR_SYSCLK_SEL_DIV1_2 0x0600
347		#define PLLCR_SYSCLK_SEL_DIV1_3 0x0700
348		#define PLLCR_CLKEN 0x0010
349		#define PLLCR_DISPLL 0x0008
350
351		#define PLLFSR_CLK32 0x8000
352		#define PLLFSR_PROT 0x4000
353		#define PLLFSR_QCNT 0x0f00
354		#define PLLFSR_PCNT 0x00ff
355
356		#define PCTLR_PC_EN 0x80
357		#define PCTLR_STOP 0x40
358		#define PCTLR_WIDTH 0x1f
359
360		#define CXP_CC 0xc000
361		#define CXP_CC_XLU 0x0000
362		#define CXP_CC_BLACK 0x4000
363		#define CXP_CC_INVERSE 0x8000
364		#define CXP_CC_INVALID 0xc000
365		#define CXP_MASK 0x03ff
366
367		#define CYP_MASK 0x01ff
368
369		#define CWCH_CW 0x1f00
370		#define CWCH_CH 0x001f
371
372		#define BLKC_BKEN 0x80
373		#define BLKC_BD 0x7f
374
375		#define LPICF_PBSIZ 0x06
376		#define LPICF_PBSIZ_1 0x00
377		#define LPICF_PBSIZ_2 0x02
378		#define LPICF_PBSIZ_4 0x04
379		#define LPICF_PBSIZ_INVALID 0x06
380
381		#define LPOLCF_LCKPOL 0x08
382		#define LPOLCF_FLMPOL 0x04
383		#define LPOLCF_LPPOL 0x02
384		#define LPOLCF_PIXPOL 0x01
385
386		#define LACDRC_MASK 0x0f
387
388		#define LPXCD_MASK 0x3f
389
390		#define LCKCON_LCDC_EN 0x80
391		#define LCKCON_LCDON 0x80
392		#define LCKCON_DMA16 0x40
393		#define LCKCON_WS 0x30
394		#define LCKCON_WS_1 0x00
395		#define LCKCON_WS_2 0x10
396		#define LCKCON_WS_3 0x20
397		#define LCKCON_WS_4 0x30
398		#define LCKCON_DWIDTH 0x02
399		#define LCKCON_PCDS 0x01
400
401		#define LBAR_MASK 0x7f
402
403		#define LPOSR_BOS 0x08
404		#define LPOSR_POS 0x07
405
406		#define LFRCM_XMOD 0xf0
407		#define LFRCM_YMOD 0x0f
408
409		#define LGPMR_PAL1 0x7000
410		#define LGPMR_PAL0 0x0700
411		#define LGPMR_PAL3 0x0070
412		#define LGPMR_PAL2 0x0007
413
414		#define RTCHMSR_HOURS 0x1f000000
415		#define RTCHMSR_MINUTES 0x003f0000
416		#define RTCHMSR_SECONDS 0x0000003f
417
418		#define RTCCTL_38_4 0x0020
419		#define RTCCTL_ENABLE 0x0080
420
421		#define RTCINT_STOPWATCH 0x0001
422		#define RTCINT_MINUTE 0x0002
423		#define RTCINT_ALARM 0x0004
424		#define RTCINT_DAY 0x0008
425		#define RTCINT_SECOND 0x0010
426
427		#define RTCSTPWTCH_MASK 0x003f
428
429		#define TCTL_TEN 0x0001
430		#define TCTL_TEN_ENABLE 0x0001
431		#define TCTL_CLKSOURCE 0x000e
432		#define TCTL_CLKSOURCE_STOP 0x0000
433		#define TCTL_CLKSOURCE_SYSCLK 0x0002
434		#define TCTL_CLKSOURCE_SYSCLK16 0x0004
435		#define TCTL_CLKSOURCE_TIN 0x0006
436		#define TCTL_CLKSOURCE_32KHZ4 0x0008
437		#define TCTL_CLKSOURCE_32KHZ5 0x000a
438		#define TCTL_CLKSOURCE_32KHZ6 0x000c
439		#define TCTL_CLKSOURCE_32KHZ7 0x000e
440		#define TCTL_IRQEN 0x0010
441		#define TCTL_IRQEN_ENABLE 0x0010
442		#define TCTL_OM 0x0020
443		#define TCTL_OM_ACTIVELOW 0x0000
444		#define TCTL_OM_TOGGLE 0x0020
445		#define TCTL_CAPTURE 0x00c0
446		#define TCTL_CAPTURE_NOINT 0x0000
447		#define TCTL_CAPTURE_RISING 0x0040
448		#define TCTL_CAPTURE_FALLING 0x0080
449		#define TCTL_CAPTURE_BOTH 0x00c0
450		#define TCTL_FRR 0x0100
451		#define TCTL_FRR_RESTART 0x0000
452		#define TCTL_FRR_FREERUN 0x0100
453
454		#define TSTAT_COMP 0x0001
455		#define TSTAT_CAPT 0x0002
456
457		#define WCTLR_WDRST 0x0008
458		#define WCTLR_LOCK 0x0004
459		#define WCTLR_FI 0x0002
460		#define WCTLR_WDEN 0x0001
461
462		#define USTCNT_UART_EN 0x8000
463		#define USTCNT_RX_EN 0x4000
464		#define USTCNT_TX_EN 0x2000
465		#define USTCNT_RX_CLK_CONT 0x1000
466		#define USTCNT_PARITY_EN 0x0800
467		#define USTCNT_ODD_EVEN 0x0400
468		#define USTCNT_STOP_BITS 0x0200
469		#define USTCNT_8_7 0x0100
470		#define USTCNT_GPIO_DELTA_EN 0x0080
471		#define USTCNT_CTS_DELTA_EN 0x0040
472		#define USTCNT_RX_FULL_EN 0x0020
473		#define USTCNT_RX_HALF_EN 0x0010
474		#define USTCNT_RX_RDY_EN 0x0008
475		#define USTCNT_TX_EMPTY_EN 0x0004
476		#define USTCNT_TX_HALF_EN 0x0002
477		#define USTCNT_TX_AVAIL_EN 0x0001
478
479		#define UBAUD_GPIO_DELTA 0x8000
480		#define UBAUD_GPIO 0x4000
481		#define UBAUD_GPIO_DIR 0x2000
482		#define UBAUD_GPIO_SRC 0x1000
483		#define UBAUD_BAUD_SRC 0x0800
484		#define UBAUD_DIVIDE 0x0700
485		#define UBAUD_DIVIDE_1 0x0000
486		#define UBAUD_DIVIDE_2 0x0100
487		#define UBAUD_DIVIDE_4 0x0200
488		#define UBAUD_DIVIDE_8 0x0300
489		#define UBAUD_DIVIDE_16 0x0400
490		#define UBAUD_DIVIDE_32 0x0500
491		#define UBAUD_DIVIDE_64 0x0600
492		#define UBAUD_DIVIDE_128 0x0700
493		#define UBAUD_PRESCALER 0x00ff
494
495		#define URX_FIFO_FULL 0x8000
496		#define URX_FIFO_HALF 0x4000
497		#define URX_DATA_READY 0x2000
498		#define URX_OVRUN 0x0800
499		#define URX_FRAME_ERROR 0x0400
500		#define URX_BREAK 0x0200
501		#define URX_PARITY_ERROR 0x0100
502
503		#define UTX_FIFO_EMPTY 0x8000
504		#define UTX_FIFO_HALF 0x4000
505		#define UTX_TX_AVAIL 0x2000
506		#define UTX_SEND_BREAK 0x1000
507		#define UTX_IGNORE_CTS 0x0800
508		#define UTX_CTS_STATUS 0x0200
509		#define UTX_CTS_DELTA 0x0100
510
511		#define UMISC_CLK_SRC 0x4000
512		#define UMISC_FORCE_PERR 0x2000
513		#define UMISC_LOOP 0x1000
514		#define UMISC_RTS_CONT 0x0080
515		#define UMISC_RTS 0x0040
516		#define UMISC_IRDA_ENABLE 0x0020
517		#define UMISC_IRDA_LOOP 0x0010
518
519		#define SPIS_SPIS_IRQ 0x8000
520		#define SPIS_IRQEN 0x4000
521		#define SPIS_ENPOL 0x2000
522		#define SPIS_DATA_RDY 0x1000
523		#define SPIS_OVRWR 0x0800
524		#define SPIS_PHA 0x0400
525		#define SPIS_POL 0x0200
526		#define SPIS_SPISEN 0x0100
527
528		#define SPIM_CLOCK_COUNT 0x000f
529		#define SPIM_POL 0x0010
530		#define SPIM_POL_HIGH 0x0000
531		#define SPIM_POL_LOW 0x0010
532		#define SPIM_PHA 0x0020
533		#define SPIM_PHA_NORMAL 0x0000
534		#define SPIM_PHA_OPPOSITE 0x0020
535		#define SPIM_IRQEN 0x0040
536		#define SPIM_SPIMIRQ 0x0080
537		#define SPIM_XCH 0x0100
538		#define SPIM_XCH_IDLE 0x0000
539		#define SPIM_XCH_INIT 0x0100
540		#define SPIM_SPMEN 0x0200
541		#define SPIM_SPMEN_DISABLE 0x0000
542		#define SPIM_SPMEN_ENABLE 0x0200
543		#define SPIM_RATE 0xe000
544		#define SPIM_RATE_4 0x0000
545		#define SPIM_RATE_8 0x2000
546		#define SPIM_RATE_16 0x4000
547		#define SPIM_RATE_32 0x6000
548		#define SPIM_RATE_64 0x8000
549		#define SPIM_RATE_128 0xa000
550		#define SPIM_RATE_256 0xc000
551		#define SPIM_RATE_512 0xe000
552
553		#define PWMC_PWMIRQ 0x8000
554		#define PWMC_IRQEN 0x4000
555		#define PWMC_LOAD 0x0100
556		#define PWMC_PIN 0x0080
557		#define PWMC_POL 0x0040
558		#define PWMC_PWMEN 0x0010
559		#define PWMC_CLKSEL 0x0007
560
561		INLINE mc68328_t* mc68328_get_safe_token( device_t *device )
562		{
563		assert( device != NULL );
564		assert( device->type() == MC68328 );
565		return (mc68328_t) downcast<mc68328_device >(device)->token();
566		}
567
568		#endif // __MC68328_PRIVATE_H_

trunk/src/mess/mess.mak
r21688	r21689
1461	1461
1462	1462	$(MESSOBJ)/palm.a: \
1463	1463	$(MESS_DRIVERS)/palm.o \
	1464	$(MESS_MACHINE)/mc68328.o \
1464	1465	$(MESS_VIDEO)/mc68328.o \
1465	1466	$(MESS_DRIVERS)/palmz22.o \
1466	1467

trunk/src/mess/drivers/palm.c
r21688	r21689
11	11
12	12	#include "emu.h"
13	13	#include "cpu/m68000/m68000.h"
14		#include "~~mach~~ine/mc68328.h"
	14	#include "includes/mc68328.h"
15	15	#include "sound/dac.h"
16	16	#include "debugger.h"
17	17	#include "machine/ram.h"

trunk/src/mess/machine/mc68328.c
r0	r21689
	1	/**********************************************************************
	2
	3	Motorola 68328 ("DragonBall") System-on-a-Chip implementation
	4
	5	By MooglyGuy
	6	contact mooglyguy@gmail.com with licensing and usage questions.
	7
	8	**********************************************************************/
	9
	10	#include "emu.h"
	11	#include "cpu/m68000/m68000.h"
	12	#include "includes/mc68328.h"
	13	#include "mc68328.h"
	14
	15	#define VERBOSE_LEVEL (0)
	16
	17	INLINE void verboselog(running_machine &machine, int n_level, const char *s_fmt, ...)
	18	{
	19	if( VERBOSE_LEVEL >= n_level )
	20	{
	21	va_list v;
	22	char buf[ 32768 ];
	23	va_start( v, s_fmt );
	24	vsprintf( buf, s_fmt, v );
	25	va_end( v );
	26	logerror( "%s: %s", machine.describe_context(), buf );
	27	}
	28	}
	29
	30	static void mc68328_set_interrupt_line(device_t *device, UINT32 line, UINT32 active)
	31	{
	32	mc68328_t* mc68328 = mc68328_get_safe_token( device );
	33	device_t *cpu = device->machine().device(mc68328->iface->m68k_cpu_tag);
	34
	35	if(active)
	36	{
	37	mc68328->regs.ipr \|= line;
	38
	39	if(!(mc68328->regs.imr & line) && !(mc68328->regs.isr & line))
	40	{
	41	mc68328->regs.isr \|= line;
	42
	43	if(mc68328->regs.isr & INT_M68K_LINE7)
	44	{
	45	cpu->execute().set_input_line_and_vector(M68K_IRQ_7, ASSERT_LINE, mc68328->regs.ivr \| 0x07);
	46	}
	47	else if(mc68328->regs.isr & INT_M68K_LINE6)
	48	{
	49	cpu->execute().set_input_line_and_vector(M68K_IRQ_6, ASSERT_LINE, mc68328->regs.ivr \| 0x06);
	50	}
	51	else if(mc68328->regs.isr & INT_M68K_LINE5)
	52	{
	53	cpu->execute().set_input_line_and_vector(M68K_IRQ_5, ASSERT_LINE, mc68328->regs.ivr \| 0x05);
	54	}
	55	else if(mc68328->regs.isr & INT_M68K_LINE4)
	56	{
	57	cpu->execute().set_input_line_and_vector(M68K_IRQ_4, ASSERT_LINE, mc68328->regs.ivr \| 0x04);
	58	}
	59	else if(mc68328->regs.isr & INT_M68K_LINE3)
	60	{
	61	cpu->execute().set_input_line_and_vector(M68K_IRQ_3, ASSERT_LINE, mc68328->regs.ivr \| 0x03);
	62	}
	63	else if(mc68328->regs.isr & INT_M68K_LINE2)
	64	{
	65	cpu->execute().set_input_line_and_vector(M68K_IRQ_2, ASSERT_LINE, mc68328->regs.ivr \| 0x02);
	66	}
	67	else if(mc68328->regs.isr & INT_M68K_LINE1)
	68	{
	69	cpu->execute().set_input_line_and_vector(M68K_IRQ_1, ASSERT_LINE, mc68328->regs.ivr \| 0x01);
	70	}
	71	}
	72	}
	73	else
	74	{
	75	mc68328->regs.isr &= ~line;
	76
	77	if((line & INT_M68K_LINE7) && !(mc68328->regs.isr & INT_M68K_LINE7))
	78	{
	79	cpu->execute().set_input_line(M68K_IRQ_7, CLEAR_LINE);
	80	}
	81	if((line & INT_M68K_LINE6) && !(mc68328->regs.isr & INT_M68K_LINE6))
	82	{
	83	cpu->execute().set_input_line(M68K_IRQ_6, CLEAR_LINE);
	84	}
	85	if((line & INT_M68K_LINE5) && !(mc68328->regs.isr & INT_M68K_LINE5))
	86	{
	87	cpu->execute().set_input_line(M68K_IRQ_5, CLEAR_LINE);
	88	}
	89	if((line & INT_M68K_LINE4) && !(mc68328->regs.isr & INT_M68K_LINE4))
	90	{
	91	cpu->execute().set_input_line(M68K_IRQ_4, CLEAR_LINE);
	92	}
	93	if((line & INT_M68K_LINE3) && !(mc68328->regs.isr & INT_M68K_LINE3))
	94	{
	95	cpu->execute().set_input_line(M68K_IRQ_3, CLEAR_LINE);
	96	}
	97	if((line & INT_M68K_LINE2) && !(mc68328->regs.isr & INT_M68K_LINE2))
	98	{
	99	cpu->execute().set_input_line(M68K_IRQ_2, CLEAR_LINE);
	100	}
	101	if((line & INT_M68K_LINE1) && !(mc68328->regs.isr & INT_M68K_LINE1))
	102	{
	103	cpu->execute().set_input_line(M68K_IRQ_1, CLEAR_LINE);
	104	}
	105	}
	106	}
	107
	108	static void mc68328_poll_port_d_interrupts(device_t *device)
	109	{
	110	mc68328_t* mc68328 = mc68328_get_safe_token( device );
	111	UINT8 line_transitions = mc68328->regs.pddataedge & mc68328->regs.pdirqedge;
	112	UINT8 line_holds = mc68328->regs.pddata &~ mc68328->regs.pdirqedge;
	113	UINT8 line_interrupts = (line_transitions \| line_holds) & mc68328->regs.pdirqen;
	114
	115	if(line_interrupts)
	116	{
	117	mc68328_set_interrupt_line(device, line_interrupts << 8, 1);
	118	}
	119	else
	120	{
	121	mc68328_set_interrupt_line(device, INT_KBDINTS, 0);
	122	}
	123	}
	124
	125	void mc68328_set_penirq_line(device_t *device, int state)
	126	{
	127	mc68328_t* mc68328 = mc68328_get_safe_token( device );
	128
	129	if(state)
	130	{
	131	mc68328_set_interrupt_line(device, INT_PEN, 1);
	132	}
	133	else
	134	{
	135	mc68328->regs.ipr &= ~INT_PEN;
	136	mc68328_set_interrupt_line(device, INT_PEN, 0);
	137	}
	138	}
	139
	140	void mc68328_set_port_d_lines(device_t *device, UINT8 state, int bit)
	141	{
	142	mc68328_t* mc68328 = mc68328_get_safe_token( device );
	143	UINT8 old_button_state = mc68328->regs.pddata;
	144
	145	if(state & (1 << bit))
	146	{
	147	mc68328->regs.pddata \|= (1 << bit);
	148	}
	149	else
	150	{
	151	mc68328->regs.pddata &= ~(1 << bit);
	152	}
	153
	154	mc68328->regs.pddataedge \|= ~old_button_state & mc68328->regs.pddata;
	155
	156	mc68328_poll_port_d_interrupts(device);
	157	}
	158
	159	static UINT32 mc68328_get_timer_frequency(device_t *device, UINT32 index)
	160	{
	161	mc68328_t* mc68328 = mc68328_get_safe_token( device );
	162	UINT32 frequency = 0;
	163
	164	switch(mc68328->regs.tctl[index] & TCTL_CLKSOURCE)
	165	{
	166	case TCTL_CLKSOURCE_SYSCLK:
	167	frequency = 32768 * 506;
	168	break;
	169
	170	case TCTL_CLKSOURCE_SYSCLK16:
	171	frequency = (32768 * 506) / 16;
	172	break;
	173
	174	case TCTL_CLKSOURCE_32KHZ4:
	175	case TCTL_CLKSOURCE_32KHZ5:
	176	case TCTL_CLKSOURCE_32KHZ6:
	177	case TCTL_CLKSOURCE_32KHZ7:
	178	frequency = 32768;
	179	break;
	180	}
	181	frequency /= (mc68328->regs.tprer[index] + 1);
	182
	183	return frequency;
	184	}
	185
	186	static void mc68328_maybe_start_timer(device_t *device, UINT32 index, UINT32 new_enable)
	187	{
	188	mc68328_t* mc68328 = mc68328_get_safe_token( device );
	189
	190	if((mc68328->regs.tctl[index] & TCTL_TEN) == TCTL_TEN_ENABLE && (mc68328->regs.tctl[index] & TCTL_CLKSOURCE) > TCTL_CLKSOURCE_STOP)
	191	{
	192	if((mc68328->regs.tctl[index] & TCTL_CLKSOURCE) == TCTL_CLKSOURCE_TIN)
	193	{
	194	mc68328->gptimer[index]->adjust(attotime::never);
	195	}
	196	else if(mc68328->regs.tcmp[index] == 0)
	197	{
	198	mc68328->gptimer[index]->adjust(attotime::never);
	199	}
	200	else
	201	{
	202	UINT32 frequency = mc68328_get_timer_frequency(device, index);
	203	attotime period = (attotime::from_hz(frequency) * mc68328->regs.tcmp[index]);
	204
	205	if(new_enable)
	206	{
	207	mc68328->regs.tcn[index] = 0x0000;
	208	}
	209
	210	mc68328->gptimer[index]->adjust(period);
	211	}
	212	}
	213	else
	214	{
	215	mc68328->gptimer[index]->adjust(attotime::never);
	216	}
	217	}
	218
	219	static void mc68328_timer_compare_event(device_t *device, UINT32 index)
	220	{
	221	mc68328_t* mc68328 = mc68328_get_safe_token( device );
	222
	223	mc68328->regs.tcn[index] = mc68328->regs.tcmp[index];
	224	mc68328->regs.tstat[index] \|= TSTAT_COMP;
	225
	226	if((mc68328->regs.tctl[index] & TCTL_FRR) == TCTL_FRR_RESTART)
	227	{
	228	UINT32 frequency = mc68328_get_timer_frequency(device, index);
	229
	230	if(frequency > 0)
	231	{
	232	attotime period = attotime::from_hz(frequency) * mc68328->regs.tcmp[index];
	233
	234	mc68328->regs.tcn[index] = 0x0000;
	235
	236	mc68328->gptimer[index]->adjust(period);
	237	}
	238	else
	239	{
	240	mc68328->gptimer[index]->adjust(attotime::never);
	241	}
	242	}
	243	else
	244	{
	245	UINT32 frequency = mc68328_get_timer_frequency(device, index);
	246
	247	if(frequency > 0)
	248	{
	249	attotime period = attotime::from_hz(frequency) * 0x10000;
	250
	251	mc68328->gptimer[index]->adjust(period);
	252	}
	253	else
	254	{
	255	mc68328->gptimer[index]->adjust(attotime::never);
	256	}
	257	}
	258	if((mc68328->regs.tctl[index] & TCTL_IRQEN) == TCTL_IRQEN_ENABLE)
	259	{
	260	mc68328_set_interrupt_line(device, (index == 0) ? INT_TIMER1 : INT_TIMER2, 1);
	261	}
	262	}
	263
	264	static TIMER_CALLBACK( mc68328_timer1_hit )
	265	{
	266	device_t *device = machine.device(MC68328_TAG);
	267
	268	mc68328_timer_compare_event(device, 0);
	269	}
	270
	271	static TIMER_CALLBACK( mc68328_timer2_hit )
	272	{
	273	device_t *device = machine.device(MC68328_TAG);
	274
	275	mc68328_timer_compare_event(device, 1);
	276	}
	277
	278	static TIMER_CALLBACK( mc68328_pwm_transition )
	279	{
	280	device_t *device = machine.device(MC68328_TAG);
	281	mc68328_t* mc68328 = mc68328_get_safe_token( device );
	282
	283	if(mc68328->regs.pwmw >= mc68328->regs.pwmp \|\| mc68328->regs.pwmw == 0 \|\| mc68328->regs.pwmp == 0)
	284	{
	285	mc68328->pwm->adjust(attotime::never);
	286	return;
	287	}
	288
	289	if(((mc68328->regs.pwmc & PWMC_POL) == 0 && (mc68328->regs.pwmc & PWMC_PIN) != 0) \|\|
	290	((mc68328->regs.pwmc & PWMC_POL) != 0 && (mc68328->regs.pwmc & PWMC_PIN) == 0))
	291	{
	292	UINT32 frequency = 32768 * 506;
	293	UINT32 divisor = 4 << (mc68328->regs.pwmc & PWMC_CLKSEL); // ?? Datasheet says 2 <<, but then we're an octave higher than CoPilot.
	294	attotime period;
	295
	296	frequency /= divisor;
	297	period = attotime::from_hz(frequency) * (mc68328->regs.pwmp - mc68328->regs.pwmw);
	298
	299	mc68328->pwm->adjust(period);
	300
	301	if(mc68328->regs.pwmc & PWMC_IRQEN)
	302	{
	303	mc68328_set_interrupt_line(device, INT_PWM, 1);
	304	}
	305	}
	306	else
	307	{
	308	UINT32 frequency = 32768 * 506;
	309	UINT32 divisor = 4 << (mc68328->regs.pwmc & PWMC_CLKSEL); // ?? Datasheet says 2 <<, but then we're an octave higher than CoPilot.
	310	attotime period;
	311
	312	frequency /= divisor;
	313	period = attotime::from_hz(frequency) * mc68328->regs.pwmw;
	314
	315	mc68328->pwm->adjust(period);
	316	}
	317
	318	mc68328->regs.pwmc ^= PWMC_PIN;
	319
	320	if( !mc68328->out_pwm.isnull() )
	321	{
	322	mc68328->out_pwm( 0, (mc68328->regs.pwmc & PWMC_PIN) ? 1 : 0 );
	323	}
	324	}
	325
	326	static TIMER_CALLBACK( mc68328_rtc_tick )
	327	{
	328	device_t *device = machine.device(MC68328_TAG);
	329	mc68328_t* mc68328 = mc68328_get_safe_token( device );
	330
	331	if(mc68328->regs.rtcctl & RTCCTL_ENABLE)
	332	{
	333	UINT32 set_int = 0;
	334
	335	mc68328->regs.hmsr++;
	336
	337	if(mc68328->regs.rtcienr & RTCINT_SECOND)
	338	{
	339	set_int = 1;
	340	mc68328->regs.rtcisr \|= RTCINT_SECOND;
	341	}
	342
	343	if((mc68328->regs.hmsr & 0x0000003f) == 0x0000003c)
	344	{
	345	mc68328->regs.hmsr &= 0xffffffc0;
	346	mc68328->regs.hmsr += 0x00010000;
	347
	348	if(mc68328->regs.rtcienr & RTCINT_MINUTE)
	349	{
	350	set_int = 1;
	351	mc68328->regs.rtcisr \|= RTCINT_MINUTE;
	352	}
	353
	354	if((mc68328->regs.hmsr & 0x003f0000) == 0x003c0000)
	355	{
	356	mc68328->regs.hmsr &= 0xffc0ffff;
	357	mc68328->regs.hmsr += 0x0100000;
	358
	359	if((mc68328->regs.hmsr & 0x1f000000) == 0x18000000)
	360	{
	361	mc68328->regs.hmsr &= 0xe0ffffff;
	362
	363	if(mc68328->regs.rtcienr & RTCINT_DAY)
	364	{
	365	set_int = 1;
	366	mc68328->regs.rtcisr \|= RTCINT_DAY;
	367	}
	368	}
	369	}
	370
	371	if(mc68328->regs.stpwtch != 0x003f)
	372	{
	373	mc68328->regs.stpwtch--;
	374	mc68328->regs.stpwtch &= 0x003f;
	375
	376	if(mc68328->regs.stpwtch == 0x003f)
	377	{
	378	if(mc68328->regs.rtcienr & RTCINT_STOPWATCH)
	379	{
	380	set_int = 1;
	381	mc68328->regs.rtcisr \|= RTCINT_STOPWATCH;
	382	}
	383	}
	384	}
	385	}
	386
	387	if(mc68328->regs.hmsr == mc68328->regs.alarm)
	388	{
	389	if(mc68328->regs.rtcienr & RTCINT_ALARM)
	390	{
	391	set_int = 1;
	392	mc68328->regs.rtcisr \|= RTCINT_STOPWATCH;
	393	}
	394	}
	395
	396	if(set_int)
	397	{
	398	mc68328_set_interrupt_line(device, INT_RTC, 1);
	399	}
	400	else
	401	{
	402	mc68328_set_interrupt_line(device, INT_RTC, 0);
	403	}
	404	}
	405	}
	406
	407	WRITE16_DEVICE_HANDLER( mc68328_w )
	408	{
	409	mc68328_t* mc68328 = mc68328_get_safe_token( device );
	410	UINT32 address = offset << 1;
	411	UINT16 temp16[4] = { 0 };
	412	UINT32 imr_old = mc68328->regs.imr, imr_diff;
	413
	414	switch(address)
	415	{
	416	case 0x000:
	417	if( mem_mask & 0x00ff )
	418	{
	419	verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfff001) = %02x\n", data & 0x00ff);
	420	}
	421	else
	422	{
	423	verboselog(space.machine(), 2, "mc68328_w: SCR = %02x\n", (data >> 8) & 0x00ff);
	424	}
	425	break;
	426
	427	case 0x100:
	428	verboselog(space.machine(), 2, "mc68328_w: GRPBASEA = %04x\n", data);
	429	mc68328->regs.grpbasea = data;
	430	break;
	431
	432	case 0x102:
	433	verboselog(space.machine(), 2, "mc68328_w: GRPBASEB = %04x\n", data);
	434	mc68328->regs.grpbaseb = data;
	435	break;
	436
	437	case 0x104:
	438	verboselog(space.machine(), 2, "mc68328_w: GRPBASEC = %04x\n", data);
	439	mc68328->regs.grpbasec = data;
	440	break;
	441
	442	case 0x106:
	443	verboselog(space.machine(), 2, "mc68328_w: GRPBASED = %04x\n", data);
	444	mc68328->regs.grpbased = data;
	445	break;
	446
	447	case 0x108:
	448	verboselog(space.machine(), 2, "mc68328_w: GRPMASKA = %04x\n", data);
	449	mc68328->regs.grpmaska = data;
	450	break;
	451
	452	case 0x10a:
	453	verboselog(space.machine(), 2, "mc68328_w: GRPMASKB = %04x\n", data);
	454	mc68328->regs.grpmaskb = data;
	455	break;
	456
	457	case 0x10c:
	458	verboselog(space.machine(), 2, "mc68328_w: GRPMASKC = %04x\n", data);
	459	mc68328->regs.grpmaskc = data;
	460	break;
	461
	462	case 0x10e:
	463	verboselog(space.machine(), 2, "mc68328_w: GRPMASKD = %04x\n", data);
	464	mc68328->regs.grpmaskd = data;
	465	break;
	466
	467	case 0x110:
	468	verboselog(space.machine(), 5, "mc68328_w: CSA0(0) = %04x\n", data);
	469	mc68328->regs.csa0 &= 0xffff0000 \| (~mem_mask);
	470	mc68328->regs.csa0 \|= data & mem_mask;
	471	break;
	472
	473	case 0x112:
	474	verboselog(space.machine(), 5, "mc68328_w: CSA0(16) = %04x\n", data);
	475	mc68328->regs.csa0 &= ~(mem_mask << 16);
	476	mc68328->regs.csa0 \|= (data & mem_mask) << 16;
	477	break;
	478
	479	case 0x114:
	480	verboselog(space.machine(), 5, "mc68328_w: CSA1(0) = %04x\n", data);
	481	mc68328->regs.csa1 &= 0xffff0000 \| (~mem_mask);
	482	mc68328->regs.csa1 \|= data & mem_mask;
	483	break;
	484
	485	case 0x116:
	486	verboselog(space.machine(), 5, "mc68328_w: CSA1(16) = %04x\n", data);
	487	mc68328->regs.csa1 &= ~(mem_mask << 16);
	488	mc68328->regs.csa1 \|= (data & mem_mask) << 16;
	489	break;
	490
	491	case 0x118:
	492	verboselog(space.machine(), 5, "mc68328_w: CSA2(0) = %04x\n", data);
	493	mc68328->regs.csa2 &= 0xffff0000 \| (~mem_mask);
	494	mc68328->regs.csa2 \|= data & mem_mask;
	495	break;
	496
	497	case 0x11a:
	498	verboselog(space.machine(), 5, "mc68328_w: CSA2(16) = %04x\n", data);
	499	mc68328->regs.csa2 &= ~(mem_mask << 16);
	500	mc68328->regs.csa2 \|= (data & mem_mask) << 16;
	501	break;
	502
	503	case 0x11c:
	504	verboselog(space.machine(), 5, "mc68328_w: CSA3(0) = %04x\n", data);
	505	mc68328->regs.csa3 &= 0xffff0000 \| (~mem_mask);
	506	mc68328->regs.csa3 \|= data & mem_mask;
	507	break;
	508
	509	case 0x11e:
	510	verboselog(space.machine(), 5, "mc68328_w: CSA3(16) = %04x\n", data);
	511	mc68328->regs.csa3 &= ~(mem_mask << 16);
	512	mc68328->regs.csa3 \|= (data & mem_mask) << 16;
	513	break;
	514
	515	case 0x120:
	516	verboselog(space.machine(), 5, "mc68328_w: CSB0(0) = %04x\n", data);
	517	mc68328->regs.csb0 &= 0xffff0000 \| (~mem_mask);
	518	mc68328->regs.csb0 \|= data & mem_mask;
	519	break;
	520
	521	case 0x122:
	522	verboselog(space.machine(), 5, "mc68328_w: CSB0(16) = %04x\n", data);
	523	mc68328->regs.csb0 &= ~(mem_mask << 16);
	524	mc68328->regs.csb0 \|= (data & mem_mask) << 16;
	525	break;
	526
	527	case 0x124:
	528	verboselog(space.machine(), 5, "mc68328_w: CSB1(0) = %04x\n", data);
	529	mc68328->regs.csb1 &= 0xffff0000 \| (~mem_mask);
	530	mc68328->regs.csb1 \|= data & mem_mask;
	531	break;
	532
	533	case 0x126:
	534	verboselog(space.machine(), 5, "mc68328_w: CSB1(16) = %04x\n", data);
	535	mc68328->regs.csb1 &= ~(mem_mask << 16);
	536	mc68328->regs.csb1 \|= (data & mem_mask) << 16;
	537	break;
	538
	539	case 0x128:
	540	verboselog(space.machine(), 5, "mc68328_w: CSB2(0) = %04x\n", data);
	541	mc68328->regs.csb2 &= 0xffff0000 \| (~mem_mask);
	542	mc68328->regs.csb2 \|= data & mem_mask;
	543	break;
	544
	545	case 0x12a:
	546	verboselog(space.machine(), 5, "mc68328_w: CSB2(16) = %04x\n", data);
	547	mc68328->regs.csb2 &= ~(mem_mask << 16);
	548	mc68328->regs.csb2 \|= (data & mem_mask) << 16;
	549	break;
	550
	551	case 0x12c:
	552	verboselog(space.machine(), 5, "mc68328_w: CSB3(0) = %04x\n", data);
	553	mc68328->regs.csb3 &= 0xffff0000 \| (~mem_mask);
	554	mc68328->regs.csb3 \|= data & mem_mask;
	555	break;
	556
	557	case 0x12e:
	558	verboselog(space.machine(), 5, "mc68328_w: CSB3(16) = %04x\n", data);
	559	mc68328->regs.csb3 &= ~(mem_mask << 16);
	560	mc68328->regs.csb3 \|= (data & mem_mask) << 16;
	561	break;
	562
	563	case 0x130:
	564	verboselog(space.machine(), 5, "mc68328_w: CSC0(0) = %04x\n", data);
	565	mc68328->regs.csc0 &= 0xffff0000 \| (~mem_mask);
	566	mc68328->regs.csc0 \|= data & mem_mask;
	567	break;
	568
	569	case 0x132:
	570	verboselog(space.machine(), 5, "mc68328_w: CSC0(16) = %04x\n", data);
	571	mc68328->regs.csc0 &= ~(mem_mask << 16);
	572	mc68328->regs.csc0 \|= (data & mem_mask) << 16;
	573	break;
	574
	575	case 0x134:
	576	verboselog(space.machine(), 5, "mc68328_w: CSC1(0) = %04x\n", data);
	577	mc68328->regs.csc1 &= 0xffff0000 \| (~mem_mask);
	578	mc68328->regs.csc1 \|= data & mem_mask;
	579	break;
	580
	581	case 0x136:
	582	verboselog(space.machine(), 5, "mc68328_w: CSC1(16) = %04x\n", data);
	583	mc68328->regs.csc1 &= ~(mem_mask << 16);
	584	mc68328->regs.csc1 \|= (data & mem_mask) << 16;
	585	break;
	586
	587	case 0x138:
	588	verboselog(space.machine(), 5, "mc68328_w: CSC2(0) = %04x\n", data);
	589	mc68328->regs.csc2 &= 0xffff0000 \| (~mem_mask);
	590	mc68328->regs.csc2 \|= data & mem_mask;
	591	break;
	592
	593	case 0x13a:
	594	verboselog(space.machine(), 5, "mc68328_w: CSC2(16) = %04x\n", data);
	595	mc68328->regs.csc2 &= ~(mem_mask << 16);
	596	mc68328->regs.csc2 \|= (data & mem_mask) << 16;
	597	break;
	598
	599	case 0x13c:
	600	verboselog(space.machine(), 5, "mc68328_w: CSC3(0) = %04x\n", data);
	601	mc68328->regs.csc3 &= 0xffff0000 \| (~mem_mask);
	602	mc68328->regs.csc3 \|= data & mem_mask;
	603	break;
	604
	605	case 0x13e:
	606	verboselog(space.machine(), 5, "mc68328_w: CSC3(16) = %04x\n", data);
	607	mc68328->regs.csc3 &= ~(mem_mask << 16);
	608	mc68328->regs.csc3 \|= (data & mem_mask) << 16;
	609	break;
	610
	611	case 0x140:
	612	verboselog(space.machine(), 5, "mc68328_w: CSD0(0) = %04x\n", data);
	613	mc68328->regs.csd0 &= 0xffff0000 \| (~mem_mask);
	614	mc68328->regs.csd0 \|= data & mem_mask;
	615	break;
	616
	617	case 0x142:
	618	verboselog(space.machine(), 5, "mc68328_w: CSD0(16) = %04x\n", data);
	619	mc68328->regs.csd0 &= ~(mem_mask << 16);
	620	mc68328->regs.csd0 \|= (data & mem_mask) << 16;
	621	break;
	622
	623	case 0x144:
	624	verboselog(space.machine(), 5, "mc68328_w: CSD1(0) = %04x\n", data);
	625	mc68328->regs.csd1 &= 0xffff0000 \| (~mem_mask);
	626	mc68328->regs.csd1 \|= data & mem_mask;
	627	break;
	628
	629	case 0x146:
	630	verboselog(space.machine(), 5, "mc68328_w: CSD1(16) = %04x\n", data);
	631	mc68328->regs.csd1 &= ~(mem_mask << 16);
	632	mc68328->regs.csd1 \|= (data & mem_mask) << 16;
	633	break;
	634
	635	case 0x148:
	636	verboselog(space.machine(), 5, "mc68328_w: CSD2(0) = %04x\n", data);
	637	mc68328->regs.csd2 &= 0xffff0000 \| (~mem_mask);
	638	mc68328->regs.csd2 \|= data & mem_mask;
	639	break;
	640
	641	case 0x14a:
	642	verboselog(space.machine(), 5, "mc68328_w: CSD2(16) = %04x\n", data);
	643	mc68328->regs.csd2 &= ~(mem_mask << 16);
	644	mc68328->regs.csd2 \|= (data & mem_mask) << 16;
	645	break;
	646
	647	case 0x14c:
	648	verboselog(space.machine(), 5, "mc68328_w: CSD3(0) = %04x\n", data);
	649	mc68328->regs.csd3 &= 0xffff0000 \| (~mem_mask);
	650	mc68328->regs.csd3 \|= data & mem_mask;
	651	break;
	652
	653	case 0x14e:
	654	verboselog(space.machine(), 5, "mc68328_w: CSD3(16) = %04x\n", data);
	655	mc68328->regs.csd3 &= ~(mem_mask << 16);
	656	mc68328->regs.csd3 \|= (data & mem_mask) << 16;
	657	break;
	658
	659	case 0x200:
	660	verboselog(space.machine(), 2, "mc68328_w: PLLCR = %04x\n", data);
	661	mc68328->regs.pllcr = data;
	662	break;
	663
	664	case 0x202:
	665	verboselog(space.machine(), 2, "mc68328_w: PLLFSR = %04x\n", data);
	666	mc68328->regs.pllfsr = data;
	667	break;
	668
	669	case 0x206:
	670	if( mem_mask & 0x00ff )
	671	{
	672	verboselog(space.machine(), 2, "mc68328_w: PCTLR = %02x\n", data & 0x00ff);
	673	mc68328->regs.pctlr = data & 0x00ff;
	674	}
	675	else
	676	{
	677	verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfff206) = %02x\n", (data >> 8) & 0x00ff);
	678	}
	679	break;
	680
	681	case 0x300:
	682	if( mem_mask & 0x00ff )
	683	{
	684	verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfff301) = %02x\n", data & 0x00ff);
	685	}
	686	else
	687	{
	688	verboselog(space.machine(), 2, "mc68328_w: IVR = %02x\n", (data >> 8) & 0x00ff);
	689	mc68328->regs.ivr = (data >> 8) & 0x00ff;
	690	}
	691	break;
	692
	693	case 0x302:
	694	verboselog(space.machine(), 2, "mc68328_w: ICR = %04x\n", data);
	695	mc68328->regs.icr = data;
	696	break;
	697
	698	case 0x304:
	699	verboselog(space.machine(), 2, "mc68328_w: IMR(16) = %04x\n", data);
	700	mc68328->regs.imr &= ~(mem_mask << 16);
	701	mc68328->regs.imr \|= (data & mem_mask) << 16;
	702	mc68328->regs.isr &= ~((data & mem_mask) << 16);
	703
	704	imr_diff = imr_old ^ mc68328->regs.imr;
	705	mc68328_set_interrupt_line(device, imr_diff, 0);
	706	break;
	707
	708	case 0x306:
	709	verboselog(space.machine(), 2, "mc68328_w: IMR(0) = %04x\n", data);
	710	mc68328->regs.imr &= 0xffff0000 \| (~mem_mask);
	711	mc68328->regs.imr \|= data & mem_mask;
	712	mc68328->regs.isr &= ~(data & mem_mask);
	713
	714	imr_diff = imr_old ^ mc68328->regs.imr;
	715	mc68328_set_interrupt_line(device, imr_diff, 0);
	716	break;
	717
	718	case 0x308:
	719	{
	720	verboselog(space.machine(), 2, "mc68328_w: IWR(16) = %04x\n", data);
	721	mc68328->regs.iwr &= ~(mem_mask << 16);
	722	mc68328->regs.iwr \|= (data & mem_mask) << 16;
	723	}
	724	break;
	725
	726	case 0x30a:
	727	verboselog(space.machine(), 2, "mc68328_w: IWR(0) = %04x\n", data);
	728	mc68328->regs.iwr &= 0xffff0000 \| (~mem_mask);
	729	mc68328->regs.iwr \|= data & mem_mask;
	730	break;
	731
	732	case 0x30c:
	733	verboselog(space.machine(), 2, "mc68328_w: ISR(16) = %04x\n", data);
	734	// Clear edge-triggered IRQ1
	735	if((mc68328->regs.icr & ICR_ET1) == ICR_ET1 && (data & INT_IRQ1_SHIFT) == INT_IRQ1_SHIFT)
	736	{
	737	mc68328->regs.isr &= ~INT_IRQ1;
	738	}
	739
	740	// Clear edge-triggered IRQ2
	741	if((mc68328->regs.icr & ICR_ET2) == ICR_ET2 && (data & INT_IRQ2_SHIFT) == INT_IRQ2_SHIFT)
	742	{
	743	mc68328->regs.isr &= ~INT_IRQ2;
	744	}
	745
	746	// Clear edge-triggered IRQ3
	747	if((mc68328->regs.icr & ICR_ET3) == ICR_ET3 && (data & INT_IRQ3_SHIFT) == INT_IRQ3_SHIFT)
	748	{
	749	mc68328->regs.isr &= ~INT_IRQ3;
	750	}
	751
	752	// Clear edge-triggered IRQ6
	753	if((mc68328->regs.icr & ICR_ET6) == ICR_ET6 && (data & INT_IRQ6_SHIFT) == INT_IRQ6_SHIFT)
	754	{
	755	mc68328->regs.isr &= ~INT_IRQ6;
	756	}
	757
	758	// Clear edge-triggered IRQ7
	759	if((data & INT_IRQ7_SHIFT) == INT_IRQ7_SHIFT)
	760	{
	761	mc68328->regs.isr &= ~INT_IRQ7;
	762	}
	763	break;
	764
	765	case 0x30e:
	766	verboselog(space.machine(), 2, "mc68328_w: ISR(0) = %04x (Ignored)\n", data);
	767	break;
	768
	769	case 0x310:
	770	verboselog(space.machine(), 2, "mc68328_w: IPR(16) = %04x (Ignored)\n");
	771	break;
	772
	773	case 0x312:
	774	verboselog(space.machine(), 2, "mc68328_w: IPR(0) = %04x (Ignored)\n");
	775	break;
	776
	777	case 0x400:
	778	if( mem_mask & 0x00ff )
	779	{
	780	verboselog(space.machine(), 2, "mc68328_w: PADATA = %02x\n", data & 0x00ff);
	781	mc68328->regs.padata = data & 0x00ff;
	782	if(!mc68328->out_port_a.isnull())
	783	{
	784	mc68328->out_port_a( 0, data & 0x00ff );
	785	}
	786	}
	787	else
	788	{
	789	verboselog(space.machine(), 2, "mc68328_w: PADIR = %02x\n", (data >> 8) & 0x00ff);
	790	mc68328->regs.padir = (data >> 8) & 0x00ff;
	791	}
	792	break;
	793
	794	case 0x402:
	795	if( mem_mask & 0x00ff )
	796	{
	797	verboselog(space.machine(), 2, "mc68328_w: PASEL = %02x\n", data & 0x00ff);
	798	mc68328->regs.pasel = data & 0x00ff;
	799	}
	800	else
	801	{
	802	verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfff402) = %02x\n", (data >> 8) & 0x00ff);
	803	}
	804	break;
	805
	806	case 0x408:
	807	if( mem_mask & 0x00ff )
	808	{
	809	verboselog(space.machine(), 2, "mc68328_w: PBDATA = %02x\n", data & 0x00ff);
	810	mc68328->regs.pbdata = data & 0x00ff;
	811	if(!mc68328->out_port_b.isnull())
	812	{
	813	mc68328->out_port_b( 0, data & 0x00ff );
	814	}
	815	}
	816	else
	817	{
	818	verboselog(space.machine(), 2, "mc68328_w: PBDIR = %02x\n", (data >> 8) & 0x00ff);
	819	mc68328->regs.pbdir = (data >> 8) & 0x00ff;
	820	}
	821	break;
	822
	823	case 0x40a:
	824	if( mem_mask & 0x00ff )
	825	{
	826	verboselog(space.machine(), 2, "mc68328_w: PBSEL = %02x\n", data & 0x00ff);
	827	mc68328->regs.pbsel = data & 0x00ff;
	828	}
	829	else
	830	{
	831	verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfff40a) = %02x\n", (data >> 8) & 0x00ff);
	832	}
	833	break;
	834
	835	case 0x410:
	836	if( mem_mask & 0x00ff )
	837	{
	838	verboselog(space.machine(), 2, "mc68328_w: PCDATA = %02x\n", data & 0x00ff);
	839	mc68328->regs.pcdata = data & 0x00ff;
	840	if(!mc68328->out_port_c.isnull())
	841	{
	842	mc68328->out_port_c( 0, data & 0x00ff );
	843	}
	844	}
	845	else
	846	{
	847	verboselog(space.machine(), 2, "mc68328_w: PCDIR = %02x\n", (data >> 8) & 0x00ff);
	848	mc68328->regs.pcdir = (data >> 8) & 0x00ff;
	849	}
	850	break;
	851
	852	case 0x412:
	853	if( mem_mask & 0x00ff )
	854	{
	855	verboselog(space.machine(), 2, "mc68328_w: PCSEL = %02x\n", data & 0x00ff);
	856	mc68328->regs.pcsel = data & 0x00ff;
	857	}
	858	else
	859	{
	860	verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfff412) = %02x\n", (data >> 8) & 0x00ff);
	861	}
	862	break;
	863
	864	case 0x418:
	865	if( mem_mask & 0x00ff )
	866	{
	867	verboselog(space.machine(), 2, "mc68328_w: PDDATA = %02x\n", data & 0x00ff);
	868
	869	mc68328->regs.pddataedge &= ~(data & 0x00ff);
	870	mc68328_poll_port_d_interrupts(device);
	871	}
	872	else
	873	{
	874	verboselog(space.machine(), 2, "mc68328_w: PDDIR = %02x\n", (data >> 8) & 0x00ff);
	875	mc68328->regs.pddir = (data >> 8) & 0x00ff;
	876	}
	877	break;
	878
	879	case 0x41a:
	880	if( mem_mask & 0x00ff )
	881	{
	882	verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfff41b) = %02x\n", data & 0x00ff);
	883	}
	884	else
	885	{
	886	verboselog(space.machine(), 2, "mc68328_w: PDPUEN = %02x\n", (data >> 8) & 0x00ff);
	887	mc68328->regs.pdpuen = (data >> 8) & 0x00ff;
	888	}
	889	break;
	890
	891	case 0x41c:
	892	if( mem_mask & 0x00ff )
	893	{
	894	verboselog(space.machine(), 2, "mc68328_w: PDIRQEN = %02x\n", data & 0x00ff);
	895	mc68328->regs.pdirqen = data & 0x00ff;
	896
	897	mc68328_poll_port_d_interrupts(device);
	898	}
	899	else
	900	{
	901	verboselog(space.machine(), 2, "mc68328_w: PDPOL = %02x\n", (data >> 8) & 0x00ff);
	902	mc68328->regs.pdpol = (data >> 8) & 0x00ff;
	903	}
	904	break;
	905
	906	case 0x41e:
	907	if( mem_mask & 0x00ff )
	908	{
	909	verboselog(space.machine(), 2, "mc68328_w: PDIRQEDGE = %02x\n", data & 0x00ff);
	910	mc68328->regs.pdirqedge = data & 0x00ff;
	911	}
	912	else
	913	{
	914	verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfff41e) = %02x\n", (data >> 8) & 0x00ff);
	915	}
	916	break;
	917
	918	case 0x420:
	919	if( mem_mask & 0x00ff )
	920	{
	921	verboselog(space.machine(), 2, "mc68328_w: PEDATA = %02x\n", data & 0x00ff);
	922	mc68328->regs.pedata = data & 0x00ff;
	923	if(!mc68328->out_port_e.isnull())
	924	{
	925	mc68328->out_port_e( 0, data & 0x00ff );
	926	}
	927	}
	928	else
	929	{
	930	verboselog(space.machine(), 2, "mc68328_w: PEDIR = %02x\n", (data >> 8) & 0x00ff);
	931	mc68328->regs.pedir = (data >> 8) & 0x00ff;
	932	}
	933	break;
	934
	935	case 0x422:
	936	if( mem_mask & 0x00ff )
	937	{
	938	verboselog(space.machine(), 2, "mc68328_w: PESEL = %02x\n", data & 0x00ff);
	939	mc68328->regs.pesel = data & 0x00ff;
	940	}
	941	else
	942	{
	943	verboselog(space.machine(), 2, "mc68328_w: PEPUEN = %02x\n", (data >> 8) & 0x00ff);
	944	mc68328->regs.pepuen = (data >> 8) & 0x00ff;
	945	mc68328->regs.pedata \|= mc68328->regs.pepuen;
	946	}
	947	break;
	948
	949	case 0x428:
	950	if( mem_mask & 0x00ff )
	951	{
	952	verboselog(space.machine(), 2, "mc68328_w: PFDATA = %02x\n", data & 0x00ff);
	953	mc68328->regs.pfdata = data & 0x00ff;
	954	if(!mc68328->out_port_f.isnull())
	955	{
	956	mc68328->out_port_f( 0, data & 0x00ff );
	957	}
	958	}
	959	else
	960	{
	961	verboselog(space.machine(), 2, "mc68328_w: PFDIR = %02x\n", (data >> 8) & 0x00ff);
	962	mc68328->regs.pfdir = (data >> 8) & 0x00ff;
	963	}
	964	break;
	965
	966	case 0x42a:
	967	if( mem_mask & 0x00ff )
	968	{
	969	verboselog(space.machine(), 2, "mc68328_w: PFSEL = %02x\n", data & 0x00ff);
	970	mc68328->regs.pfsel = data & 0x00ff;
	971	}
	972	else
	973	{
	974	verboselog(space.machine(), 2, "mc68328_w: PFPUEN = %02x\n", (data >> 8) & 0x00ff);
	975	mc68328->regs.pfpuen = (data >> 8) & 0x00ff;
	976	}
	977	break;
	978
	979	case 0x430:
	980	if( mem_mask & 0x00ff )
	981	{
	982	verboselog(space.machine(), 2, "mc68328_w: PGDATA = %02x\n", data & 0x00ff);
	983	mc68328->regs.pgdata = data & 0x00ff;
	984	if(!mc68328->out_port_g.isnull())
	985	{
	986	mc68328->out_port_g( 0, data & 0x00ff );
	987	}
	988	}
	989	else
	990	{
	991	verboselog(space.machine(), 2, "mc68328_w: PGDIR = %02x\n", (data >> 8) & 0x00ff);
	992	mc68328->regs.pgdir = (data >> 8) & 0x00ff;
	993	}
	994	break;
	995
	996	case 0x432:
	997	if( mem_mask & 0x00ff )
	998	{
	999	verboselog(space.machine(), 2, "mc68328_w: PGSEL = %02x\n", data & 0x00ff);
	1000	mc68328->regs.pgsel = data & 0x00ff;
	1001	}
	1002	else
	1003	{
	1004	verboselog(space.machine(), 2, "mc68328_w: PGPUEN = %02x\n", (data >> 8) & 0x00ff);
	1005	mc68328->regs.pgpuen = (data >> 8) & 0x00ff;
	1006	}
	1007	break;
	1008
	1009	case 0x438:
	1010	if( mem_mask & 0x00ff )
	1011	{
	1012	verboselog(space.machine(), 2, "mc68328_w: PJDATA = %02x\n", data & 0x00ff);
	1013	mc68328->regs.pjdata = data & 0x00ff;
	1014	if(!mc68328->out_port_j.isnull())
	1015	{
	1016	mc68328->out_port_j( 0, data & 0x00ff );
	1017	}
	1018	}
	1019	else
	1020	{
	1021	verboselog(space.machine(), 2, "mc68328_w: PJDIR = %02x\n", (data >> 8) & 0x00ff);
	1022	mc68328->regs.pjdir = (data >> 8) & 0x00ff;
	1023	}
	1024	break;
	1025
	1026	case 0x43a:
	1027	if( mem_mask & 0x00ff )
	1028	{
	1029	verboselog(space.machine(), 2, "mc68328_w: PJSEL = %02x\n", data & 0x00ff);
	1030	mc68328->regs.pjsel = data & 0x00ff;
	1031	}
	1032	else
	1033	{
	1034	verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfff43a) = %02x\n", (data >> 8) & 0x00ff);
	1035	}
	1036	break;
	1037
	1038	case 0x440:
	1039	if( mem_mask & 0x00ff )
	1040	{
	1041	verboselog(space.machine(), 2, "mc68328_w: PKDATA = %02x\n", data & 0x00ff);
	1042	mc68328->regs.pkdata = data & 0x00ff;
	1043	if(!mc68328->out_port_k.isnull())
	1044	{
	1045	mc68328->out_port_k( 0, data & 0x00ff );
	1046	}
	1047	}
	1048	else
	1049	{
	1050	verboselog(space.machine(), 2, "mc68328_w: PKDIR = %02x\n", (data >> 8) & 0x00ff);
	1051	mc68328->regs.pkdir = (data >> 8) & 0x00ff;
	1052	}
	1053	break;
	1054
	1055	case 0x442:
	1056	if( mem_mask & 0x00ff )
	1057	{
	1058	verboselog(space.machine(), 2, "mc68328_w: PKSEL = %02x\n", data & 0x00ff);
	1059	mc68328->regs.pksel = data & 0x00ff;
	1060	}
	1061	else
	1062	{
	1063	verboselog(space.machine(), 2, "mc68328_w: PKPUEN = %02x\n", (data >> 8) & 0x00ff);
	1064	mc68328->regs.pgpuen = (data >> 8) & 0x00ff;
	1065	}
	1066	break;
	1067
	1068	case 0x448:
	1069	if( mem_mask & 0x00ff )
	1070	{
	1071	verboselog(space.machine(), 2, "mc68328_w: PMDATA = %02x\n", data & 0x00ff);
	1072	mc68328->regs.pmdata = data & 0x00ff;
	1073	if(!mc68328->out_port_m.isnull())
	1074	{
	1075	mc68328->out_port_m( 0, data & 0x00ff );
	1076	}
	1077	}
	1078	else
	1079	{
	1080	verboselog(space.machine(), 2, "mc68328_w: PMDIR = %02x\n", (data >> 8) & 0x00ff);
	1081	mc68328->regs.pmdir = (data >> 8) & 0x00ff;
	1082	}
	1083	break;
	1084
	1085	case 0x44a:
	1086	if( mem_mask & 0x00ff )
	1087	{
	1088	verboselog(space.machine(), 2, "mc68328_w: PMSEL = %02x\n", data & 0x00ff);
	1089	mc68328->regs.pmsel = data & 0x00ff;
	1090	}
	1091	else
	1092	{
	1093	verboselog(space.machine(), 2, "mc68328_w: PMPUEN = %02x\n", (data >> 8) & 0x00ff);
	1094	mc68328->regs.pmpuen = (data >> 8) & 0x00ff;
	1095	}
	1096	break;
	1097
	1098	case 0x500:
	1099	verboselog(space.machine(), 2, "mc68328_w: PWMC = %04x\n", data);
	1100
	1101	mc68328->regs.pwmc = data;
	1102
	1103	if(mc68328->regs.pwmc & PWMC_PWMIRQ)
	1104	{
	1105	mc68328_set_interrupt_line(device, INT_PWM, 1);
	1106	}
	1107
	1108	mc68328->regs.pwmc &= ~PWMC_LOAD;
	1109
	1110	if((mc68328->regs.pwmc & PWMC_PWMEN) != 0 && mc68328->regs.pwmw != 0 && mc68328->regs.pwmp != 0)
	1111	{
	1112	UINT32 frequency = 32768 * 506;
	1113	UINT32 divisor = 4 << (mc68328->regs.pwmc & PWMC_CLKSEL); // ?? Datasheet says 2 <<, but then we're an octave higher than CoPilot.
	1114	attotime period;
	1115	frequency /= divisor;
	1116	period = attotime::from_hz(frequency) * mc68328->regs.pwmw;
	1117	mc68328->pwm->adjust(period);
	1118	if(mc68328->regs.pwmc & PWMC_IRQEN)
	1119	{
	1120	mc68328_set_interrupt_line(device, INT_PWM, 1);
	1121	}
	1122	mc68328->regs.pwmc ^= PWMC_PIN;
	1123	}
	1124	else
	1125	{
	1126	mc68328->pwm->adjust(attotime::never);
	1127	}
	1128	break;
	1129
	1130	case 0x502:
	1131	verboselog(space.machine(), 2, "mc68328_w: PWMP = %04x\n", data);
	1132	mc68328->regs.pwmp = data;
	1133	break;
	1134
	1135	case 0x504:
	1136	verboselog(space.machine(), 2, "mc68328_w: PWMW = %04x\n", data);
	1137	mc68328->regs.pwmw = data;
	1138	break;
	1139
	1140	case 0x506:
	1141	verboselog(space.machine(), 2, "mc68328_w: PWMCNT = %04x\n", data);
	1142	mc68328->regs.pwmcnt = 0;
	1143	break;
	1144
	1145	case 0x600:
	1146	verboselog(space.machine(), 2, "mc68328_w: TCTL1 = %04x\n", data);
	1147	temp16[0] = mc68328->regs.tctl[0];
	1148	mc68328->regs.tctl[0] = data;
	1149	if((temp16[0] & TCTL_TEN) == (mc68328->regs.tctl[0] & TCTL_TEN))
	1150	{
	1151	mc68328_maybe_start_timer(device, 0, 0);
	1152	}
	1153	else if((temp16[0] & TCTL_TEN) != TCTL_TEN_ENABLE && (mc68328->regs.tctl[0] & TCTL_TEN) == TCTL_TEN_ENABLE)
	1154	{
	1155	mc68328_maybe_start_timer(device, 0, 1);
	1156	}
	1157	break;
	1158
	1159	case 0x602:
	1160	verboselog(space.machine(), 2, "mc68328_w: TPRER1 = %04x\n", data);
	1161	mc68328->regs.tprer[0] = data;
	1162	mc68328_maybe_start_timer(device, 0, 0);
	1163	break;
	1164
	1165	case 0x604:
	1166	verboselog(space.machine(), 2, "mc68328_w: TCMP1 = %04x\n", data);
	1167	mc68328->regs.tcmp[0] = data;
	1168	mc68328_maybe_start_timer(device, 0, 0);
	1169	break;
	1170
	1171	case 0x606:
	1172	verboselog(space.machine(), 2, "mc68328_w: TCR1 = %04x (Ignored)\n", data);
	1173	break;
	1174
	1175	case 0x608:
	1176	verboselog(space.machine(), 2, "mc68328_w: TCN1 = %04x (Ignored)\n", data);
	1177	break;
	1178
	1179	case 0x60a:
	1180	verboselog(space.machine(), 5, "mc68328_w: TSTAT1 = %04x\n", data);
	1181	mc68328->regs.tstat[0] &= ~mc68328->regs.tclear[0];
	1182	if(!(mc68328->regs.tstat[0] & TSTAT_COMP))
	1183	{
	1184	mc68328_set_interrupt_line(device, INT_TIMER1, 0);
	1185	}
	1186	break;
	1187
	1188	case 0x60c:
	1189	verboselog(space.machine(), 2, "mc68328_w: TCTL2 = %04x\n", data);
	1190	temp16[0] = mc68328->regs.tctl[1];
	1191	mc68328->regs.tctl[1] = data;
	1192	if((temp16[0] & TCTL_TEN) == (mc68328->regs.tctl[1] & TCTL_TEN))
	1193	{
	1194	mc68328_maybe_start_timer(device, 1, 0);
	1195	}
	1196	else if((temp16[0] & TCTL_TEN) != TCTL_TEN_ENABLE && (mc68328->regs.tctl[1] & TCTL_TEN) == TCTL_TEN_ENABLE)
	1197	{
	1198	mc68328_maybe_start_timer(device, 1, 1);
	1199	}
	1200	break;
	1201
	1202	case 0x60e:
	1203	verboselog(space.machine(), 2, "mc68328_w: TPRER2 = %04x\n", data);
	1204	mc68328->regs.tprer[1] = data;
	1205	mc68328_maybe_start_timer(device, 1, 0);
	1206	break;
	1207
	1208	case 0x610:
	1209	verboselog(space.machine(), 2, "mc68328_w: TCMP2 = %04x\n", data);
	1210	mc68328->regs.tcmp[1] = data;
	1211	mc68328_maybe_start_timer(device, 1, 0);
	1212	break;
	1213
	1214	case 0x612:
	1215	verboselog(space.machine(), 2, "mc68328_w: TCR2 = %04x (Ignored)\n", data);
	1216	break;
	1217
	1218	case 0x614:
	1219	verboselog(space.machine(), 2, "mc68328_w: TCN2 = %04x (Ignored)\n", data);
	1220	break;
	1221
	1222	case 0x616:
	1223	verboselog(space.machine(), 2, "mc68328_w: TSTAT2 = %04x\n", data);
	1224	mc68328->regs.tstat[1] &= ~mc68328->regs.tclear[1];
	1225	if(!(mc68328->regs.tstat[1] & TSTAT_COMP))
	1226	{
	1227	mc68328_set_interrupt_line(device, INT_TIMER2, 0);
	1228	}
	1229	break;
	1230
	1231	case 0x618:
	1232	verboselog(space.machine(), 2, "mc68328_w: WCTLR = %04x\n", data);
	1233	mc68328->regs.wctlr = data;
	1234	break;
	1235
	1236	case 0x61a:
	1237	verboselog(space.machine(), 2, "mc68328_w: WCMPR = %04x\n", data);
	1238	mc68328->regs.wcmpr = data;
	1239	break;
	1240
	1241	case 0x61c:
	1242	verboselog(space.machine(), 2, "mc68328_w: WCN = %04x (Ignored)\n", data);
	1243	break;
	1244
	1245	case 0x700:
	1246	verboselog(space.machine(), 2, "mc68328_w: SPISR = %04x\n", data);
	1247	mc68328->regs.spisr = data;
	1248	break;
	1249
	1250	case 0x800:
	1251	verboselog(space.machine(), 2, "mc68328_w: SPIMDATA = %04x\n", data);
	1252	if(!mc68328->out_spim.isnull())
	1253	{
	1254	mc68328->out_spim( 0, data, 0xffff );
	1255	}
	1256	else
	1257	{
	1258	mc68328->regs.spimdata = data;
	1259	}
	1260	break;
	1261
	1262	case 0x802:
	1263	verboselog(space.machine(), 2, "mc68328_w: SPIMCONT = %04x\n", data);
	1264	verboselog(space.machine(), 3, " Count = %d\n", data & SPIM_CLOCK_COUNT);
	1265	verboselog(space.machine(), 3, " Polarity = %s\n", (data & SPIM_POL) ? "Inverted" : "Active-high");
	1266	verboselog(space.machine(), 3, " Phase = %s\n", (data & SPIM_PHA) ? "Opposite" : "Normal");
	1267	verboselog(space.machine(), 3, " IRQ Enable = %s\n", (data & SPIM_IRQEN) ? "Enable" : "Disable");
	1268	verboselog(space.machine(), 3, " IRQ Pending = %s\n", (data & SPIM_SPIMIRQ) ? "Yes" : "No");
	1269	verboselog(space.machine(), 3, " Exchange = %s\n", (data & SPIM_XCH) ? "Initiate" : "Idle");
	1270	verboselog(space.machine(), 3, " SPIM Enable = %s\n", (data & SPIM_SPMEN) ? "Enable" : "Disable");
	1271	verboselog(space.machine(), 3, " Data Rate = Divide By %d\n", 1 << ((((data & SPIM_RATE) >> 13) & 0x0007) + 2) );
	1272	mc68328->regs.spimcont = data;
	1273	// $$HACK$$ We should probably emulate the ADS7843 A/D device properly.
	1274	if(data & SPIM_XCH)
	1275	{
	1276	mc68328->regs.spimcont &= ~SPIM_XCH;
	1277	if(mc68328->iface->spim_xch_trigger)
	1278	{
	1279	(mc68328->iface->spim_xch_trigger)( device );
	1280	}
	1281	if(data & SPIM_IRQEN)
	1282	{
	1283	mc68328->regs.spimcont \|= SPIM_SPIMIRQ;
	1284	verboselog(space.machine(), 3, "Triggering SPIM Interrupt\n" );
	1285	mc68328_set_interrupt_line(device, INT_SPIM, 1);
	1286	}
	1287	}
	1288	if(!(data & SPIM_IRQEN))
	1289	{
	1290	mc68328_set_interrupt_line(device, INT_SPIM, 0);
	1291	}
	1292	break;
	1293
	1294	case 0x900:
	1295	verboselog(space.machine(), 2, "mc68328_w: USTCNT = %04x\n", data);
	1296	mc68328->regs.ustcnt = data;
	1297	break;
	1298
	1299	case 0x902:
	1300	verboselog(space.machine(), 2, "mc68328_w: UBAUD = %04x\n", data);
	1301	mc68328->regs.ubaud = data;
	1302	break;
	1303
	1304	case 0x904:
	1305	verboselog(space.machine(), 2, "mc68328_w: URX = %04x\n", data);
	1306	break;
	1307
	1308	case 0x906:
	1309	verboselog(space.machine(), 2, "mc68328_w: UTX = %04x\n", data);
	1310	break;
	1311
	1312	case 0x908:
	1313	verboselog(space.machine(), 2, "mc68328_w: UMISC = %04x\n", data);
	1314	mc68328->regs.umisc = data;
	1315	break;
	1316
	1317	case 0xa00:
	1318	verboselog(space.machine(), 2, "mc68328_w: LSSA(16) = %04x\n", data);
	1319	mc68328->regs.lssa &= ~(mem_mask << 16);
	1320	mc68328->regs.lssa \|= (data & mem_mask) << 16;
	1321	verboselog(space.machine(), 3, " Address: %08x\n", mc68328->regs.lssa);
	1322	break;
	1323
	1324	case 0xa02:
	1325	verboselog(space.machine(), 2, "mc68328_w: LSSA(0) = %04x\n", data);
	1326	mc68328->regs.lssa &= 0xffff0000 \| (~mem_mask);
	1327	mc68328->regs.lssa \|= data & mem_mask;
	1328	verboselog(space.machine(), 3, " Address: %08x\n", mc68328->regs.lssa);
	1329	break;
	1330
	1331	case 0xa04:
	1332	if( mem_mask & 0x00ff )
	1333	{
	1334	verboselog(space.machine(), 2, "mc68328_w: LVPW = %02x\n", data & 0x00ff);
	1335	mc68328->regs.lvpw = data & 0x00ff;
	1336	verboselog(space.machine(), 3, " Page Width: %d or %d\n", (mc68328->regs.lvpw + 1) * ((mc68328->regs.lpicf & 0x01) ? 8 : 16));
	1337	}
	1338	else
	1339	{
	1340	verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfffa04) = %02x\n", (data >> 8) & 0x00ff);
	1341	}
	1342	break;
	1343
	1344	case 0xa08:
	1345	verboselog(space.machine(), 2, "mc68328_w: LXMAX = %04x\n", data);
	1346	mc68328->regs.lxmax = data;
	1347	verboselog(space.machine(), 3, " Width: %d\n", (data & 0x03ff) + 1);
	1348	break;
	1349
	1350	case 0xa0a:
	1351	verboselog(space.machine(), 2, "mc68328_w: LYMAX = %04x\n", data);
	1352	mc68328->regs.lymax = data;
	1353	verboselog(space.machine(), 3, " Height: %d\n", (data & 0x03ff) + 1);
	1354	break;
	1355
	1356	case 0xa18:
	1357	verboselog(space.machine(), 2, "mc68328_w: LCXP = %04x\n", data);
	1358	mc68328->regs.lcxp = data;
	1359	verboselog(space.machine(), 3, " X Position: %d\n", data & 0x03ff);
	1360	switch(mc68328->regs.lcxp >> 14)
	1361	{
	1362	case 0:
	1363	verboselog(space.machine(), 3, " Cursor Control: Transparent\n");
	1364	break;
	1365
	1366	case 1:
	1367	verboselog(space.machine(), 3, " Cursor Control: Black\n");
	1368	break;
	1369
	1370	case 2:
	1371	verboselog(space.machine(), 3, " Cursor Control: Reverse\n");
	1372	break;
	1373
	1374	case 3:
	1375	verboselog(space.machine(), 3, " Cursor Control: Invalid\n");
	1376	break;
	1377	}
	1378	break;
	1379
	1380	case 0xa1a:
	1381	verboselog(space.machine(), 2, "mc68328_w: LCYP = %04x\n", data);
	1382	mc68328->regs.lcyp = data;
	1383	verboselog(space.machine(), 3, " Y Position: %d\n", data & 0x01ff);
	1384	break;
	1385
	1386	case 0xa1c:
	1387	verboselog(space.machine(), 2, "mc68328_w: LCWCH = %04x\n", data);
	1388	mc68328->regs.lcwch = data;
	1389	verboselog(space.machine(), 3, " Width: %d\n", (data >> 8) & 0x1f);
	1390	verboselog(space.machine(), 3, " Height: %d\n", data & 0x1f);
	1391	break;
	1392
	1393	case 0xa1e:
	1394	if( mem_mask & 0x00ff )
	1395	{
	1396	verboselog(space.machine(), 2, "mc68328_w: LBLKC = %02x\n", data & 0x00ff);
	1397	mc68328->regs.lblkc = data & 0x00ff;
	1398	verboselog(space.machine(), 3, " Blink Enable: %d\n", mc68328->regs.lblkc >> 7);
	1399	verboselog(space.machine(), 3, " Blink Divisor: %d\n", mc68328->regs.lblkc & 0x7f);
	1400	}
	1401	else
	1402	{
	1403	verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfffa1e) = %02x\n", (data >> 8) & 0x00ff);
	1404	}
	1405	break;
	1406
	1407	case 0xa20:
	1408	if( mem_mask & 0x00ff )
	1409	{
	1410	verboselog(space.machine(), 2, "mc68328_w: LPOLCF = %02x\n", data & 0x00ff);
	1411	mc68328->regs.lpolcf = data & 0x00ff;
	1412	verboselog(space.machine(), 3, " LCD Shift Clock Polarity: %s\n", (mc68328->regs.lpicf & 0x08) ? "Active positive edge of LCLK" : "Active negative edge of LCLK");
	1413	verboselog(space.machine(), 3, " First-line marker polarity: %s\n", (mc68328->regs.lpicf & 0x04) ? "Active Low" : "Active High");
	1414	verboselog(space.machine(), 3, " Line-pulse polarity: %s\n", (mc68328->regs.lpicf & 0x02) ? "Active Low" : "Active High");
	1415	verboselog(space.machine(), 3, " Pixel polarity: %s\n", (mc68328->regs.lpicf & 0x01) ? "Active Low" : "Active High");
	1416	}
	1417	else
	1418	{
	1419	verboselog(space.machine(), 2, "mc68328_w: LPICF = %02x\n", (data >> 8) & 0x00ff);
	1420	mc68328->regs.lpicf = (data >> 8) & 0x00ff;
	1421	switch((mc68328->regs.lpicf >> 1) & 0x03)
	1422	{
	1423	case 0:
	1424	verboselog(space.machine(), 3, " Bus Size: 1-bit\n");
	1425	break;
	1426
	1427	case 1:
	1428	verboselog(space.machine(), 3, " Bus Size: 2-bit\n");
	1429	break;
	1430
	1431	case 2:
	1432	verboselog(space.machine(), 3, " Bus Size: 4-bit\n");
	1433	break;
	1434
	1435	case 3:
	1436	verboselog(space.machine(), 3, " Bus Size: unused\n");
	1437	break;
	1438	}
	1439	verboselog(space.machine(), 3, " Gray scale enable: %d\n", mc68328->regs.lpicf & 0x01);
	1440	}
	1441	break;
	1442
	1443	case 0xa22:
	1444	if( mem_mask & 0x00ff )
	1445	{
	1446	verboselog(space.machine(), 2, "mc68328_w: LACDRC = %02x\n", data & 0x00ff);
	1447	mc68328->regs.lacdrc = data & 0x00ff;
	1448	}
	1449	else
	1450	{
	1451	verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfffa22) = %02x\n", (data >> 8) & 0x00ff);
	1452	}
	1453	break;
	1454
	1455	case 0xa24:
	1456	if( mem_mask & 0x00ff )
	1457	{
	1458	verboselog(space.machine(), 2, "mc68328_w: LPXCD = %02x\n", data & 0x00ff);
	1459	mc68328->regs.lpxcd = data & 0x00ff;
	1460	verboselog(space.machine(), 3, " Clock Divisor: %d\n", mc68328->regs.lpxcd + 1);
	1461	}
	1462	else
	1463	{
	1464	verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfffa24) = %02x\n", (data >> 8) & 0x00ff);
	1465	}
	1466	break;
	1467
	1468	case 0xa26:
	1469	if( mem_mask & 0x00ff )
	1470	{
	1471	verboselog(space.machine(), 2, "mc68328_w: LCKCON = %02x\n", data & 0x00ff);
	1472	mc68328->regs.lckcon = data & 0x00ff;
	1473	verboselog(space.machine(), 3, " LCDC Enable: %d\n", (mc68328->regs.lckcon >> 7) & 0x01);
	1474	verboselog(space.machine(), 3, " DMA Burst Length: %d\n", ((mc68328->regs.lckcon >> 6) & 0x01) ? 16 : 8);
	1475	verboselog(space.machine(), 3, " DMA Bursting Clock Control: %d\n", ((mc68328->regs.lckcon >> 4) & 0x03) + 1);
	1476	verboselog(space.machine(), 3, " Bus Width: %d\n", ((mc68328->regs.lckcon >> 1) & 0x01) ? 8 : 16);
	1477	verboselog(space.machine(), 3, " Pixel Clock Divider Source: %s\n", (mc68328->regs.lckcon & 0x01) ? "PIX" : "SYS");
	1478	}
	1479	else
	1480	{
	1481	verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfffa26) = %02x\n", (data >> 8) & 0x00ff);
	1482	}
	1483	break;
	1484
	1485	case 0xa28:
	1486	if( mem_mask & 0x00ff )
	1487	{
	1488	verboselog(space.machine(), 2, "mc68328_w: LLBAR = %02x\n", data & 0x00ff);
	1489	mc68328->regs.llbar = data & 0x00ff;
	1490	verboselog(space.machine(), 3, " Address: %d\n", (mc68328->regs.llbar & 0x7f) * ((mc68328->regs.lpicf & 0x01) ? 8 : 16));
	1491	}
	1492	else
	1493	{
	1494	verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfffa28) = %02x\n", (data >> 8) & 0x00ff);
	1495	}
	1496	break;
	1497
	1498	case 0xa2a:
	1499	if( mem_mask & 0x00ff )
	1500	{
	1501	verboselog(space.machine(), 2, "mc68328_w: LOTCR = %02x\n", data & 0x00ff);
	1502	}
	1503	else
	1504	{
	1505	verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfffa2a) = %02x\n", (data >> 8) & 0x00ff);
	1506	}
	1507	break;
	1508
	1509	case 0xa2c:
	1510	if( mem_mask & 0x00ff )
	1511	{
	1512	verboselog(space.machine(), 2, "mc68328_w: LPOSR = %02x\n", data & 0x00ff);
	1513	mc68328->regs.lposr = data & 0x00ff;
	1514	verboselog(space.machine(), 3, " Byte Offset: %d\n", (mc68328->regs.lposr >> 3) & 0x01);
	1515	verboselog(space.machine(), 3, " Pixel Offset: %d\n", mc68328->regs.lposr & 0x07);
	1516	}
	1517	else
	1518	{
	1519	verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfffa2c) = %02x\n", (data >> 8) & 0x00ff);
	1520	}
	1521	break;
	1522
	1523	case 0xa30:
	1524	if( mem_mask & 0x00ff )
	1525	{
	1526	verboselog(space.machine(), 2, "mc68328_w: LFRCM = %02x\n", data & 0x00ff);
	1527	mc68328->regs.lfrcm = data & 0x00ff;
	1528	verboselog(space.machine(), 3, " X Modulation: %d\n", (mc68328->regs.lfrcm >> 4) & 0x0f);
	1529	verboselog(space.machine(), 3, " Y Modulation: %d\n", mc68328->regs.lfrcm & 0x0f);
	1530	}
	1531	else
	1532	{
	1533	verboselog(space.machine(), 2, "mc68328_w: Unknown address (0xfffa30) = %02x\n", (data >> 8) & 0x00ff);
	1534	}
	1535	break;
	1536
	1537	case 0xa32:
	1538	verboselog(space.machine(), 2, "mc68328_w: LGPMR = %04x\n", data);
	1539	mc68328->regs.lgpmr = data;
	1540	verboselog(space.machine(), 3, " Palette 0: %d\n", (mc68328->regs.lgpmr >> 8) & 0x07);
	1541	verboselog(space.machine(), 3, " Palette 1: %d\n", (mc68328->regs.lgpmr >> 12) & 0x07);
	1542	verboselog(space.machine(), 3, " Palette 2: %d\n", (mc68328->regs.lgpmr >> 0) & 0x07);
	1543	verboselog(space.machine(), 3, " Palette 3: %d\n", (mc68328->regs.lgpmr >> 4) & 0x07);
	1544	break;
	1545
	1546	case 0xb00:
	1547	verboselog(space.machine(), 2, "mc68328_w: HMSR(0) = %04x\n", data);
	1548	mc68328->regs.hmsr &= ~(mem_mask << 16);
	1549	mc68328->regs.hmsr \|= (data & mem_mask) << 16;
	1550	mc68328->regs.hmsr &= 0x1f3f003f;
	1551	break;
	1552
	1553	case 0xb02:
	1554	verboselog(space.machine(), 2, "mc68328_w: HMSR(16) = %04x\n", data);
	1555	mc68328->regs.hmsr &= 0xffff0000 \| (~mem_mask);
	1556	mc68328->regs.hmsr \|= data & mem_mask;
	1557	mc68328->regs.hmsr &= 0x1f3f003f;
	1558	break;
	1559
	1560	case 0xb04:
	1561	verboselog(space.machine(), 2, "mc68328_w: ALARM(0) = %04x\n", data);
	1562	mc68328->regs.alarm &= ~(mem_mask << 16);
	1563	mc68328->regs.alarm \|= (data & mem_mask) << 16;
	1564	mc68328->regs.alarm &= 0x1f3f003f;
	1565	break;
	1566
	1567	case 0xb06:
	1568	verboselog(space.machine(), 2, "mc68328_w: ALARM(16) = %04x\n", data);
	1569	mc68328->regs.alarm &= 0xffff0000 \| (~mem_mask);
	1570	mc68328->regs.alarm \|= data & mem_mask;
	1571	mc68328->regs.alarm &= 0x1f3f003f;
	1572	break;
	1573
	1574	case 0xb0c:
	1575	verboselog(space.machine(), 2, "mc68328_w: RTCCTL = %04x\n", data);
	1576	mc68328->regs.rtcctl = data & 0x00a0;
	1577	break;
	1578
	1579	case 0xb0e:
	1580	verboselog(space.machine(), 2, "mc68328_w: RTCISR = %04x\n", data);
	1581	mc68328->regs.rtcisr &= ~data;
	1582	if(mc68328->regs.rtcisr == 0)
	1583	{
	1584	mc68328_set_interrupt_line(device, INT_RTC, 0);
	1585	}
	1586	break;
	1587
	1588	case 0xb10:
	1589	verboselog(space.machine(), 2, "mc68328_w: RTCIENR = %04x\n", data);
	1590	mc68328->regs.rtcienr = data & 0x001f;
	1591	break;
	1592
	1593	case 0xb12:
	1594	verboselog(space.machine(), 2, "mc68328_w: STPWTCH = %04x\n", data);
	1595	mc68328->regs.stpwtch = data & 0x003f;
	1596	break;
	1597
	1598	default:
	1599	verboselog(space.machine(), 0, "mc68328_w: Unknown address (0x%06x) = %04x (%04x)\n", 0xfff000 + address, data, mem_mask);
	1600	break;
	1601	}
	1602	}
	1603
	1604	READ16_DEVICE_HANDLER( mc68328_r )
	1605	{
	1606	mc68328_t* mc68328 = mc68328_get_safe_token( device );
	1607	UINT16 temp16 = 0;
	1608	UINT32 address = offset << 1;
	1609
	1610	switch(address)
	1611	{
	1612	case 0x000:
	1613	if( mem_mask & 0x00ff )
	1614	{
	1615	verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfff001)\n", mem_mask);
	1616	}
	1617	else
	1618	{
	1619	verboselog(space.machine(), 2, "mc68328_r (%04x): SCR = %02x\n", mem_mask, mc68328->regs.scr);
	1620	return mc68328->regs.scr << 8;
	1621	}
	1622	break;
	1623
	1624	case 0x100:
	1625	verboselog(space.machine(), 2, "mc68328_r (%04x): GRPBASEA = %04x\n", mem_mask, mc68328->regs.grpbasea);
	1626	return mc68328->regs.grpbasea;
	1627
	1628	case 0x102:
	1629	verboselog(space.machine(), 2, "mc68328_r (%04x): GRPBASEB = %04x\n", mem_mask, mc68328->regs.grpbaseb);
	1630	return mc68328->regs.grpbaseb;
	1631
	1632	case 0x104:
	1633	verboselog(space.machine(), 2, "mc68328_r (%04x): GRPBASEC = %04x\n", mem_mask, mc68328->regs.grpbasec);
	1634	return mc68328->regs.grpbasec;
	1635
	1636	case 0x106:
	1637	verboselog(space.machine(), 2, "mc68328_r (%04x): GRPBASED = %04x\n", mem_mask, mc68328->regs.grpbased);
	1638	return mc68328->regs.grpbased;
	1639
	1640	case 0x108:
	1641	verboselog(space.machine(), 2, "mc68328_r (%04x): GRPMASKA = %04x\n", mem_mask, mc68328->regs.grpmaska);
	1642	return mc68328->regs.grpmaska;
	1643
	1644	case 0x10a:
	1645	verboselog(space.machine(), 2, "mc68328_r (%04x): GRPMASKB = %04x\n", mem_mask, mc68328->regs.grpmaskb);
	1646	return mc68328->regs.grpmaskb;
	1647
	1648	case 0x10c:
	1649	verboselog(space.machine(), 2, "mc68328_r (%04x): GRPMASKC = %04x\n", mem_mask, mc68328->regs.grpmaskc);
	1650	return mc68328->regs.grpmaskc;
	1651
	1652	case 0x10e:
	1653	verboselog(space.machine(), 2, "mc68328_r (%04x): GRPMASKD = %04x\n", mem_mask, mc68328->regs.grpmaskd);
	1654	return mc68328->regs.grpmaskd;
	1655
	1656	case 0x110:
	1657	verboselog(space.machine(), 5, "mc68328_r (%04x): CSA0(0) = %04x\n", mem_mask, mc68328->regs.csa0 & 0x0000ffff);
	1658	return mc68328->regs.csa0 & 0x0000ffff;
	1659
	1660	case 0x112:
	1661	verboselog(space.machine(), 5, "mc68328_r (%04x): CSA0(16) = %04x\n", mem_mask, mc68328->regs.csa0 >> 16);
	1662	return mc68328->regs.csa0 >> 16;
	1663
	1664	case 0x114:
	1665	verboselog(space.machine(), 5, "mc68328_r (%04x): CSA1(0) = %04x\n", mem_mask, mc68328->regs.csa1 & 0x0000ffff);
	1666	return mc68328->regs.csa1 & 0x0000ffff;
	1667
	1668	case 0x116:
	1669	verboselog(space.machine(), 5, "mc68328_r (%04x): CSA1(16) = %04x\n", mem_mask, mc68328->regs.csa1 >> 16);
	1670	return mc68328->regs.csa1 >> 16;
	1671
	1672	case 0x118:
	1673	verboselog(space.machine(), 5, "mc68328_r (%04x): CSA2(0) = %04x\n", mem_mask, mc68328->regs.csa2 & 0x0000ffff);
	1674	return mc68328->regs.csa2 & 0x0000ffff;
	1675
	1676	case 0x11a:
	1677	verboselog(space.machine(), 5, "mc68328_r (%04x): CSA2(16) = %04x\n", mem_mask, mc68328->regs.csa2 >> 16);
	1678	return mc68328->regs.csa2 >> 16;
	1679
	1680	case 0x11c:
	1681	verboselog(space.machine(), 5, "mc68328_r (%04x): CSA3(0) = %04x\n", mem_mask, mc68328->regs.csa3 & 0x0000ffff);
	1682	return mc68328->regs.csa3 & 0x0000ffff;
	1683
	1684	case 0x11e:
	1685	verboselog(space.machine(), 5, "mc68328_r (%04x): CSA3(16) = %04x\n", mem_mask, mc68328->regs.csa3 >> 16);
	1686	return mc68328->regs.csa3 >> 16;
	1687
	1688	case 0x120:
	1689	verboselog(space.machine(), 5, "mc68328_r (%04x): CSB0(0) = %04x\n", mem_mask, mc68328->regs.csb0 & 0x0000ffff);
	1690	return mc68328->regs.csb0 & 0x0000ffff;
	1691
	1692	case 0x122:
	1693	verboselog(space.machine(), 5, "mc68328_r (%04x): CSB0(16) = %04x\n", mem_mask, mc68328->regs.csb0 >> 16);
	1694	return mc68328->regs.csb0 >> 16;
	1695
	1696	case 0x124:
	1697	verboselog(space.machine(), 5, "mc68328_r (%04x): CSB1(0) = %04x\n", mem_mask, mc68328->regs.csb1 & 0x0000ffff);
	1698	return mc68328->regs.csb1 & 0x0000ffff;
	1699
	1700	case 0x126:
	1701	verboselog(space.machine(), 5, "mc68328_r (%04x): CSB1(16) = %04x\n", mem_mask, mc68328->regs.csb1 >> 16);
	1702	return mc68328->regs.csb1 >> 16;
	1703
	1704	case 0x128:
	1705	verboselog(space.machine(), 5, "mc68328_r (%04x): CSB2(0) = %04x\n", mem_mask, mc68328->regs.csb2 & 0x0000ffff);
	1706	return mc68328->regs.csb2 & 0x0000ffff;
	1707
	1708	case 0x12a:
	1709	verboselog(space.machine(), 5, "mc68328_r (%04x): CSB2(16) = %04x\n", mem_mask, mc68328->regs.csb2 >> 16);
	1710	return mc68328->regs.csb2 >> 16;
	1711
	1712	case 0x12c:
	1713	verboselog(space.machine(), 5, "mc68328_r (%04x): CSB3(0) = %04x\n", mem_mask, mc68328->regs.csb3 & 0x0000ffff);
	1714	return mc68328->regs.csb3 & 0x0000ffff;
	1715
	1716	case 0x12e:
	1717	verboselog(space.machine(), 5, "mc68328_r (%04x): CSB3(16) = %04x\n", mem_mask, mc68328->regs.csb3 >> 16);
	1718	return mc68328->regs.csb3 >> 16;
	1719
	1720	case 0x130:
	1721	verboselog(space.machine(), 5, "mc68328_r (%04x): CSC0(0) = %04x\n", mem_mask, mc68328->regs.csc0 & 0x0000ffff);
	1722	return mc68328->regs.csc0 & 0x0000ffff;
	1723
	1724	case 0x132:
	1725	verboselog(space.machine(), 5, "mc68328_r (%04x): CSC0(16) = %04x\n", mem_mask, mc68328->regs.csc0 >> 16);
	1726	return mc68328->regs.csc0 >> 16;
	1727
	1728	case 0x134:
	1729	verboselog(space.machine(), 5, "mc68328_r (%04x): CSC1(0) = %04x\n", mem_mask, mc68328->regs.csc1 & 0x0000ffff);
	1730	return mc68328->regs.csc1 & 0x0000ffff;
	1731
	1732	case 0x136:
	1733	verboselog(space.machine(), 5, "mc68328_r (%04x): CSC1(16) = %04x\n", mem_mask, mc68328->regs.csc1 >> 16);
	1734	return mc68328->regs.csc1 >> 16;
	1735
	1736	case 0x138:
	1737	verboselog(space.machine(), 5, "mc68328_r (%04x): CSC2(0) = %04x\n", mem_mask, mc68328->regs.csc2 & 0x0000ffff);
	1738	return mc68328->regs.csc2 & 0x0000ffff;
	1739
	1740	case 0x13a:
	1741	verboselog(space.machine(), 5, "mc68328_r (%04x): CSC2(16) = %04x\n", mem_mask, mc68328->regs.csc2 >> 16);
	1742	return mc68328->regs.csc2 >> 16;
	1743
	1744	case 0x13c:
	1745	verboselog(space.machine(), 5, "mc68328_r (%04x): CSC3(0) = %04x\n", mem_mask, mc68328->regs.csc3 & 0x0000ffff);
	1746	return mc68328->regs.csc3 & 0x0000ffff;
	1747
	1748	case 0x13e:
	1749	verboselog(space.machine(), 5, "mc68328_r (%04x): CSC3(16) = %04x\n", mem_mask, mc68328->regs.csc3 >> 16);
	1750	return mc68328->regs.csc3 >> 16;
	1751
	1752	case 0x140:
	1753	verboselog(space.machine(), 5, "mc68328_r (%04x): CSD0(0) = %04x\n", mem_mask, mc68328->regs.csd0 & 0x0000ffff);
	1754	return mc68328->regs.csd0 & 0x0000ffff;
	1755
	1756	case 0x142:
	1757	verboselog(space.machine(), 5, "mc68328_r (%04x): CSD0(16) = %04x\n", mem_mask, mc68328->regs.csd0 >> 16);
	1758	return mc68328->regs.csd0 >> 16;
	1759
	1760	case 0x144:
	1761	verboselog(space.machine(), 5, "mc68328_r (%04x): CSD1(0) = %04x\n", mem_mask, mc68328->regs.csd1 & 0x0000ffff);
	1762	return mc68328->regs.csd1 & 0x0000ffff;
	1763
	1764	case 0x146:
	1765	verboselog(space.machine(), 5, "mc68328_r (%04x): CSD1(16) = %04x\n", mem_mask, mc68328->regs.csd1 >> 16);
	1766	return mc68328->regs.csd1 >> 16;
	1767
	1768	case 0x148:
	1769	verboselog(space.machine(), 5, "mc68328_r (%04x): CSD2(0) = %04x\n", mem_mask, mc68328->regs.csd2 & 0x0000ffff);
	1770	return mc68328->regs.csd2 & 0x0000ffff;
	1771
	1772	case 0x14a:
	1773	verboselog(space.machine(), 5, "mc68328_r (%04x): CSD2(16) = %04x\n", mem_mask, mc68328->regs.csd2 >> 16);
	1774	return mc68328->regs.csd2 >> 16;
	1775
	1776	case 0x14c:
	1777	verboselog(space.machine(), 5, "mc68328_r (%04x): CSD3(0) = %04x\n", mem_mask, mc68328->regs.csd3 & 0x0000ffff);
	1778	return mc68328->regs.csd3 & 0x0000ffff;
	1779
	1780	case 0x14e:
	1781	verboselog(space.machine(), 5, "mc68328_r (%04x): CSD3(16) = %04x\n", mem_mask, mc68328->regs.csd3 >> 16);
	1782	return mc68328->regs.csd3 >> 16;
	1783
	1784	case 0x200:
	1785	verboselog(space.machine(), 2, "mc68328_r (%04x): PLLCR = %04x\n", mem_mask, mc68328->regs.pllcr);
	1786	return mc68328->regs.pllcr;
	1787
	1788	case 0x202:
	1789	verboselog(space.machine(), 2, "mc68328_r (%04x): PLLFSR = %04x\n", mem_mask, mc68328->regs.pllfsr);
	1790	mc68328->regs.pllfsr ^= 0x8000;
	1791	return mc68328->regs.pllfsr;
	1792
	1793	case 0x206:
	1794	if( mem_mask & 0x00ff )
	1795	{
	1796	verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfff206)\n", mem_mask);
	1797	}
	1798	else
	1799	{
	1800	verboselog(space.machine(), 2, "mc68328_r (%04x): PCTLR = %02x\n", mem_mask, mc68328->regs.pctlr);
	1801	return mc68328->regs.pctlr << 8;
	1802	}
	1803	break;
	1804
	1805	case 0x300:
	1806	if( mem_mask & 0x00ff )
	1807	{
	1808	verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfff301)\n", mem_mask);
	1809	}
	1810	else
	1811	{
	1812	verboselog(space.machine(), 2, "mc68328_r (%04x): IVR = %02x\n", mem_mask, mc68328->regs.ivr);
	1813	return mc68328->regs.ivr << 8;
	1814	}
	1815	break;
	1816
	1817	case 0x302:
	1818	verboselog(space.machine(), 2, "mc68328_r (%04x): ICR = %04x\n", mem_mask, mc68328->regs.icr);
	1819	return mc68328->regs.icr;
	1820
	1821	case 0x304:
	1822	verboselog(space.machine(), 2, "mc68328_r (%04x): IMR(16) = %04x\n", mem_mask, mc68328->regs.imr >> 16);
	1823	return mc68328->regs.imr >> 16;
	1824
	1825	case 0x306:
	1826	verboselog(space.machine(), 2, "mc68328_r (%04x): IMR(0) = %04x\n", mem_mask, mc68328->regs.imr & 0x0000ffff);
	1827	return mc68328->regs.imr & 0x0000ffff;
	1828
	1829	case 0x308:
	1830	verboselog(space.machine(), 2, "mc68328_r (%04x): IWR(16) = %04x\n", mem_mask, mc68328->regs.iwr >> 16);
	1831	return mc68328->regs.iwr >> 16;
	1832
	1833	case 0x30a:
	1834	verboselog(space.machine(), 2, "mc68328_r (%04x): IWR(0) = %04x\n", mem_mask, mc68328->regs.iwr & 0x0000ffff);
	1835	return mc68328->regs.iwr & 0x0000ffff;
	1836
	1837	case 0x30c:
	1838	verboselog(space.machine(), 2, "mc68328_r (%04x): ISR(16) = %04x\n", mem_mask, mc68328->regs.isr >> 16);
	1839	return mc68328->regs.isr >> 16;
	1840
	1841	case 0x30e:
	1842	verboselog(space.machine(), 2, "mc68328_r (%04x): ISR(0) = %04x\n", mem_mask, mc68328->regs.isr & 0x0000ffff);
	1843	return mc68328->regs.isr & 0x0000ffff;
	1844
	1845	case 0x310:
	1846	verboselog(space.machine(), 2, "mc68328_r (%04x): IPR(16) = %04x\n", mem_mask, mc68328->regs.ipr >> 16);
	1847	return mc68328->regs.ipr >> 16;
	1848
	1849	case 0x312:
	1850	verboselog(space.machine(), 2, "mc68328_r (%04x): IPR(0) = %04x\n", mem_mask, mc68328->regs.ipr & 0x0000ffff);
	1851	return mc68328->regs.ipr & 0x0000ffff;
	1852
	1853	case 0x400:
	1854	if( mem_mask & 0x00ff )
	1855	{
	1856	verboselog(space.machine(), 2, "mc68328_r (%04x): PADATA = %02x\n", mem_mask, mc68328->regs.padata);
	1857	if(!mc68328->in_port_a.isnull())
	1858	{
	1859	return mc68328->in_port_a( 0 );
	1860	}
	1861	else
	1862	{
	1863	return mc68328->regs.padata;
	1864	}
	1865	}
	1866	else
	1867	{
	1868	verboselog(space.machine(), 2, "mc68328_r (%04x): PADIR = %02x\n", mem_mask, mc68328->regs.padir);
	1869	return mc68328->regs.padir << 8;
	1870	}
	1871	break;
	1872
	1873	case 0x402:
	1874	if( mem_mask & 0x00ff )
	1875	{
	1876	verboselog(space.machine(), 2, "mc68328_r (%04x): PASEL = %02x\n", mem_mask, mc68328->regs.pasel);
	1877	return mc68328->regs.pasel;
	1878	}
	1879	else
	1880	{
	1881	verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfff402)\n", mem_mask);
	1882	}
	1883	break;
	1884
	1885	case 0x408:
	1886	if( mem_mask & 0x00ff )
	1887	{
	1888	verboselog(space.machine(), 2, "mc68328_r (%04x): PBDATA = %02x\n", mem_mask, mc68328->regs.pbdata);
	1889	if(!mc68328->in_port_b.isnull())
	1890	{
	1891	return mc68328->in_port_b( 0 );
	1892	}
	1893	else
	1894	{
	1895	return mc68328->regs.pbdata;
	1896	}
	1897	}
	1898	else
	1899	{
	1900	verboselog(space.machine(), 2, "mc68328_r (%04x): PBDIR = %02x\n", mem_mask, mc68328->regs.pbdir);
	1901	return mc68328->regs.pbdir << 8;
	1902	}
	1903	break;
	1904
	1905	case 0x40a:
	1906	if( mem_mask & 0x00ff )
	1907	{
	1908	verboselog(space.machine(), 2, "mc68328_r (%04x): PBSEL = %02x\n", mem_mask, mc68328->regs.pbsel);
	1909	return mc68328->regs.pbsel;
	1910	}
	1911	else
	1912	{
	1913	verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfff40a)\n", mem_mask);
	1914	}
	1915	break;
	1916
	1917	case 0x410:
	1918	if( mem_mask & 0x00ff )
	1919	{
	1920	verboselog(space.machine(), 2, "mc68328_r (%04x): PCDATA = %02x\n", mem_mask, mc68328->regs.pcdata);
	1921	if(!mc68328->in_port_c.isnull())
	1922	{
	1923	return mc68328->in_port_c( 0 );
	1924	}
	1925	else
	1926	{
	1927	return mc68328->regs.pcdata;
	1928	}
	1929	}
	1930	else
	1931	{
	1932	verboselog(space.machine(), 2, "mc68328_r (%04x): PCDIR = %02x\n", mem_mask, mc68328->regs.pcdir);
	1933	return mc68328->regs.pcdir << 8;
	1934	}
	1935	break;
	1936
	1937	case 0x412:
	1938	if( mem_mask & 0x00ff )
	1939	{
	1940	verboselog(space.machine(), 2, "mc68328_r (%04x): PCSEL = %02x\n", mem_mask, mc68328->regs.pcsel);
	1941	return mc68328->regs.pcsel;
	1942	}
	1943	else
	1944	{
	1945	verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfff412)\n", mem_mask);
	1946	}
	1947	break;
	1948
	1949	case 0x418:
	1950	if( mem_mask & 0x00ff )
	1951	{
	1952	verboselog(space.machine(), 2, "mc68328_r (%04x): PDDATA = %02x\n", mem_mask, mc68328->regs.pddata);
	1953	if(!mc68328->in_port_d.isnull())
	1954	{
	1955	return mc68328->in_port_d( 0 );
	1956	}
	1957	else
	1958	{
	1959	return mc68328->regs.pddata;
	1960	}
	1961	}
	1962	else
	1963	{
	1964	verboselog(space.machine(), 2, "mc68328_r (%04x): PDDIR = %02x\n", mem_mask, mc68328->regs.pddir);
	1965	return mc68328->regs.pddir << 8;
	1966	}
	1967	break;
	1968
	1969	case 0x41a:
	1970	if( mem_mask & 0x00ff )
	1971	{
	1972	verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfff41b)\n", mem_mask);
	1973	}
	1974	else
	1975	{
	1976	verboselog(space.machine(), 2, "mc68328_r (%04x): PDPUEN = %02x\n", mem_mask, mc68328->regs.pdpuen);
	1977	return mc68328->regs.pdpuen << 8;
	1978	}
	1979	break;
	1980
	1981	case 0x41c:
	1982	if( mem_mask & 0x00ff )
	1983	{
	1984	verboselog(space.machine(), 2, "mc68328_r (%04x): PDIRQEN = %02x\n", mem_mask, mc68328->regs.pdirqen);
	1985	return mc68328->regs.pdirqen;
	1986	}
	1987	else
	1988	{
	1989	verboselog(space.machine(), 2, "mc68328_r (%04x): PDPOL = %02x\n", mem_mask, mc68328->regs.pdpol);
	1990	return mc68328->regs.pdpol << 8;
	1991	}
	1992	break;
	1993
	1994	case 0x41e:
	1995	if( mem_mask & 0x00ff )
	1996	{
	1997	verboselog(space.machine(), 2, "mc68328_r (%04x): PDIRQEDGE = %02x\n", mem_mask, mc68328->regs.pdirqedge);
	1998	return mc68328->regs.pdirqedge;
	1999	}
	2000	else
	2001	{
	2002	verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfff41e)\n", mem_mask);
	2003	}
	2004	break;
	2005
	2006	case 0x420:
	2007	if( mem_mask & 0x00ff )
	2008	{
	2009	verboselog(space.machine(), 2, "mc68328_r (%04x): PEDATA = %02x\n", mem_mask, mc68328->regs.pedata);
	2010	if(!mc68328->in_port_e.isnull())
	2011	{
	2012	return mc68328->in_port_e( 0 );
	2013	}
	2014	else
	2015	{
	2016	return mc68328->regs.pedata;
	2017	}
	2018	}
	2019	else
	2020	{
	2021	verboselog(space.machine(), 2, "mc68328_r (%04x): PEDIR = %02x\n", mem_mask, mc68328->regs.pedir);
	2022	return mc68328->regs.pedir << 8;
	2023	}
	2024	break;
	2025
	2026	case 0x422:
	2027	if( mem_mask & 0x00ff )
	2028	{
	2029	verboselog(space.machine(), 2, "mc68328_r (%04x): PESEL = %02x\n", mem_mask, mc68328->regs.pesel);
	2030	return mc68328->regs.pesel;
	2031	}
	2032	else
	2033	{
	2034	verboselog(space.machine(), 2, "mc68328_r (%04x): PEPUEN = %02x\n", mem_mask, mc68328->regs.pepuen);
	2035	return mc68328->regs.pepuen << 8;
	2036	}
	2037	break;
	2038
	2039	case 0x428:
	2040	if( mem_mask & 0x00ff )
	2041	{
	2042	verboselog(space.machine(), 2, "mc68328_r (%04x): PFDATA = %02x\n", mem_mask, mc68328->regs.pfdata);
	2043	if(!mc68328->in_port_f.isnull())
	2044	{
	2045	return mc68328->in_port_f( 0 );
	2046	}
	2047	else
	2048	{
	2049	return mc68328->regs.pfdata;
	2050	}
	2051	}
	2052	else
	2053	{
	2054	verboselog(space.machine(), 2, "mc68328_r (%04x): PFDIR = %02x\n", mem_mask, mc68328->regs.pfdir);
	2055	return mc68328->regs.pfdir << 8;
	2056	}
	2057	break;
	2058
	2059	case 0x42a:
	2060	if( mem_mask & 0x00ff )
	2061	{
	2062	verboselog(space.machine(), 2, "mc68328_r (%04x): PFSEL = %02x\n", mem_mask, mc68328->regs.pfsel);
	2063	return mc68328->regs.pfsel;
	2064	}
	2065	else
	2066	{
	2067	verboselog(space.machine(), 2, "mc68328_r (%04x): PFPUEN = %02x\n", mem_mask, mc68328->regs.pfpuen);
	2068	return mc68328->regs.pfpuen << 8;
	2069	}
	2070	break;
	2071
	2072	case 0x430:
	2073	if( mem_mask & 0x00ff )
	2074	{
	2075	verboselog(space.machine(), 2, "mc68328_r (%04x): PGDATA = %02x\n", mem_mask, mc68328->regs.pgdata);
	2076	if(!mc68328->in_port_g.isnull())
	2077	{
	2078	return mc68328->in_port_g( 0 );
	2079	}
	2080	else
	2081	{
	2082	return mc68328->regs.pgdata;
	2083	}
	2084	}
	2085	else
	2086	{
	2087	verboselog(space.machine(), 2, "mc68328_r (%04x): PGDIR = %02x\n", mem_mask, mc68328->regs.pgdir);
	2088	return mc68328->regs.pgdir << 8;
	2089	}
	2090	break;
	2091
	2092	case 0x432:
	2093	if( mem_mask & 0x00ff )
	2094	{
	2095	verboselog(space.machine(), 2, "mc68328_r (%04x): PGSEL = %02x\n", mem_mask, mc68328->regs.pgsel);
	2096	return mc68328->regs.pgsel;
	2097	}
	2098	else
	2099	{
	2100	verboselog(space.machine(), 2, "mc68328_r (%04x): PGPUEN = %02x\n", mem_mask, mc68328->regs.pgpuen);
	2101	return mc68328->regs.pgpuen << 8;
	2102	}
	2103	break;
	2104
	2105	case 0x438:
	2106	if( mem_mask & 0x00ff )
	2107	{
	2108	verboselog(space.machine(), 2, "mc68328_r (%04x): PJDATA = %02x\n", mem_mask, mc68328->regs.pjdata);
	2109	if(!mc68328->in_port_j.isnull())
	2110	{
	2111	return mc68328->in_port_j( 0 );
	2112	}
	2113	else
	2114	{
	2115	return mc68328->regs.pjdata;
	2116	}
	2117	}
	2118	else
	2119	{
	2120	verboselog(space.machine(), 2, "mc68328_r (%04x): PJDIR = %02x\n", mem_mask, mc68328->regs.pjdir);
	2121	return mc68328->regs.pjdir << 8;
	2122	}
	2123	break;
	2124
	2125	case 0x43a:
	2126	if( mem_mask & 0x00ff )
	2127	{
	2128	verboselog(space.machine(), 2, "mc68328_r (%04x): PJSEL = %02x\n", mem_mask, mc68328->regs.pjsel);
	2129	return mc68328->regs.pjsel;
	2130	}
	2131	else
	2132	{
	2133	verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfff43a)\n", mem_mask);
	2134	}
	2135	break;
	2136
	2137	case 0x440:
	2138	if( mem_mask & 0x00ff )
	2139	{
	2140	verboselog(space.machine(), 2, "mc68328_r (%04x): PKDATA = %02x\n", mem_mask, mc68328->regs.pkdata);
	2141	if(!mc68328->in_port_k.isnull())
	2142	{
	2143	return mc68328->in_port_k( 0 );
	2144	}
	2145	else
	2146	{
	2147	return mc68328->regs.pkdata;
	2148	}
	2149	}
	2150	else
	2151	{
	2152	verboselog(space.machine(), 2, "mc68328_r (%04x): PKDIR = %02x\n", mem_mask, mc68328->regs.pkdir);
	2153	return mc68328->regs.pkdir << 8;
	2154	}
	2155	break;
	2156
	2157	case 0x442:
	2158	if( mem_mask & 0x00ff )
	2159	{
	2160	verboselog(space.machine(), 2, "mc68328_r (%04x): PKSEL = %02x\n", mem_mask, mc68328->regs.pksel);
	2161	return mc68328->regs.pksel;
	2162	}
	2163	else
	2164	{
	2165	verboselog(space.machine(), 2, "mc68328_r (%04x): PKPUEN = %02x\n", mem_mask, mc68328->regs.pkpuen);
	2166	return mc68328->regs.pkpuen << 8;
	2167	}
	2168	break;
	2169
	2170	case 0x448:
	2171	if( mem_mask & 0x00ff )
	2172	{
	2173	verboselog(space.machine(), 2, "mc68328_r (%04x): PMDATA = %02x\n", mem_mask, mc68328->regs.pmdata);
	2174	if(!mc68328->in_port_m.isnull())
	2175	{
	2176	return mc68328->in_port_m( 0 );
	2177	}
	2178	else
	2179	{
	2180	return mc68328->regs.pmdata;
	2181	}
	2182	}
	2183	else
	2184	{
	2185	verboselog(space.machine(), 2, "mc68328_r (%04x): PMDIR = %02x\n", mem_mask, mc68328->regs.pmdir);
	2186	return mc68328->regs.pmdir << 8;
	2187	}
	2188	break;
	2189
	2190	case 0x44a:
	2191	if( mem_mask & 0x00ff )
	2192	{
	2193	verboselog(space.machine(), 2, "mc68328_r (%04x): PMSEL = %02x\n", mem_mask, mc68328->regs.pmsel);
	2194	return mc68328->regs.pmsel;
	2195	}
	2196	else
	2197	{
	2198	verboselog(space.machine(), 2, "mc68328_r (%04x): PMPUEN = %02x\n", mem_mask, mc68328->regs.pmpuen);
	2199	return mc68328->regs.pmpuen << 8;
	2200	}
	2201	break;
	2202
	2203	case 0x500:
	2204	verboselog(space.machine(), 2, "mc68328_r (%04x): PWMC = %04x\n", mem_mask, mc68328->regs.pwmc);
	2205	temp16 = mc68328->regs.pwmc;
	2206	if(mc68328->regs.pwmc & PWMC_PWMIRQ)
	2207	{
	2208	mc68328->regs.pwmc &= ~PWMC_PWMIRQ;
	2209	mc68328_set_interrupt_line(device, INT_PWM, 0);
	2210	}
	2211	return temp16;
	2212
	2213	case 0x502:
	2214	verboselog(space.machine(), 2, "mc68328_r (%04x): PWMP = %04x\n", mem_mask, mc68328->regs.pwmp);
	2215	return mc68328->regs.pwmp;
	2216
	2217	case 0x504:
	2218	verboselog(space.machine(), 2, "mc68328_r (%04x): PWMW = %04x\n", mem_mask, mc68328->regs.pwmw);
	2219	return mc68328->regs.pwmw;
	2220
	2221	case 0x506:
	2222	verboselog(space.machine(), 2, "mc68328_r (%04x): PWMCNT = %04x\n", mem_mask, mc68328->regs.pwmcnt);
	2223	return mc68328->regs.pwmcnt;
	2224
	2225	case 0x600:
	2226	verboselog(space.machine(), 2, "mc68328_r (%04x): TCTL1 = %04x\n", mem_mask, mc68328->regs.tctl[0]);
	2227	return mc68328->regs.tctl[0];
	2228
	2229	case 0x602:
	2230	verboselog(space.machine(), 2, "mc68328_r (%04x): TPRER1 = %04x\n", mem_mask, mc68328->regs.tprer[0]);
	2231	return mc68328->regs.tprer[0];
	2232
	2233	case 0x604:
	2234	verboselog(space.machine(), 2, "mc68328_r (%04x): TCMP1 = %04x\n", mem_mask, mc68328->regs.tcmp[0]);
	2235	return mc68328->regs.tcmp[0];
	2236
	2237	case 0x606:
	2238	verboselog(space.machine(), 2, "mc68328_r (%04x): TCR1 = %04x\n", mem_mask, mc68328->regs.tcr[0]);
	2239	return mc68328->regs.tcr[0];
	2240
	2241	case 0x608:
	2242	verboselog(space.machine(), 2, "mc68328_r (%04x): TCN1 = %04x\n", mem_mask, mc68328->regs.tcn[0]);
	2243	return mc68328->regs.tcn[0];
	2244
	2245	case 0x60a:
	2246	verboselog(space.machine(), 5, "mc68328_r (%04x): TSTAT1 = %04x\n", mem_mask, mc68328->regs.tstat[0]);
	2247	mc68328->regs.tclear[0] \|= mc68328->regs.tstat[0];
	2248	return mc68328->regs.tstat[0];
	2249
	2250	case 0x60c:
	2251	verboselog(space.machine(), 2, "mc68328_r (%04x): TCTL2 = %04x\n", mem_mask, mc68328->regs.tctl[1]);
	2252	return mc68328->regs.tctl[1];
	2253
	2254	case 0x60e:
	2255	verboselog(space.machine(), 2, "mc68328_r (%04x): TPREP2 = %04x\n", mem_mask, mc68328->regs.tprer[1]);
	2256	return mc68328->regs.tprer[1];
	2257
	2258	case 0x610:
	2259	verboselog(space.machine(), 2, "mc68328_r (%04x): TCMP2 = %04x\n", mem_mask, mc68328->regs.tcmp[1]);
	2260	return mc68328->regs.tcmp[1];
	2261
	2262	case 0x612:
	2263	verboselog(space.machine(), 2, "mc68328_r (%04x): TCR2 = %04x\n", mem_mask, mc68328->regs.tcr[1]);
	2264	return mc68328->regs.tcr[1];
	2265
	2266	case 0x614:
	2267	verboselog(space.machine(), 2, "mc68328_r (%04x): TCN2 = %04x\n", mem_mask, mc68328->regs.tcn[1]);
	2268	return mc68328->regs.tcn[1];
	2269
	2270	case 0x616:
	2271	verboselog(space.machine(), 2, "mc68328_r (%04x): TSTAT2 = %04x\n", mem_mask, mc68328->regs.tstat[1]);
	2272	mc68328->regs.tclear[1] \|= mc68328->regs.tstat[1];
	2273	return mc68328->regs.tstat[1];
	2274
	2275	case 0x618:
	2276	verboselog(space.machine(), 2, "mc68328_r (%04x): WCTLR = %04x\n", mem_mask, mc68328->regs.wctlr);
	2277	return mc68328->regs.wctlr;
	2278
	2279	case 0x61a:
	2280	verboselog(space.machine(), 2, "mc68328_r (%04x): WCMPR = %04x\n", mem_mask, mc68328->regs.wcmpr);
	2281	return mc68328->regs.wcmpr;
	2282
	2283	case 0x61c:
	2284	verboselog(space.machine(), 2, "mc68328_r (%04x): WCN = %04x\n", mem_mask, mc68328->regs.wcn);
	2285	return mc68328->regs.wcn;
	2286
	2287	case 0x700:
	2288	verboselog(space.machine(), 2, "mc68328_r (%04x): SPISR = %04x\n", mem_mask, mc68328->regs.spisr);
	2289	return mc68328->regs.spisr;
	2290
	2291	case 0x800:
	2292	verboselog(space.machine(), 2, "mc68328_r (%04x): SPIMDATA = %04x\n", mem_mask, mc68328->regs.spimdata);
	2293	if(!mc68328->in_spim.isnull())
	2294	{
	2295	return mc68328->in_spim( 0, 0xffff );
	2296	}
	2297	return mc68328->regs.spimdata;
	2298
	2299	case 0x802:
	2300	verboselog(space.machine(), 2, "mc68328_r (%04x): SPIMCONT = %04x\n", mem_mask, mc68328->regs.spimcont);
	2301	if(mc68328->regs.spimcont & SPIM_XCH)
	2302	{
	2303	mc68328->regs.spimcont &= ~SPIM_XCH;
	2304	mc68328->regs.spimcont \|= SPIM_SPIMIRQ;
	2305	return ((mc68328->regs.spimcont \| SPIM_XCH) &~ SPIM_SPIMIRQ);
	2306	}
	2307	return mc68328->regs.spimcont;
	2308
	2309	case 0x900:
	2310	verboselog(space.machine(), 2, "mc68328_r (%04x): USTCNT = %04x\n", mem_mask, mc68328->regs.ustcnt);
	2311	return mc68328->regs.ustcnt;
	2312
	2313	case 0x902:
	2314	verboselog(space.machine(), 2, "mc68328_r (%04x): UBAUD = %04x\n", mem_mask, mc68328->regs.ubaud);
	2315	return mc68328->regs.ubaud;
	2316
	2317	case 0x904:
	2318	verboselog(space.machine(), 5, "mc68328_r (%04x): URX = %04x\n", mem_mask, mc68328->regs.urx);
	2319	return mc68328->regs.urx;
	2320
	2321	case 0x906:
	2322	verboselog(space.machine(), 5, "mc68328_r (%04x): UTX = %04x\n", mem_mask, mc68328->regs.utx);
	2323	return mc68328->regs.utx \| UTX_FIFO_EMPTY \| UTX_FIFO_HALF \| UTX_TX_AVAIL;
	2324
	2325	case 0x908:
	2326	verboselog(space.machine(), 2, "mc68328_r (%04x): UMISC = %04x\n", mem_mask, mc68328->regs.umisc);
	2327	return mc68328->regs.umisc;
	2328
	2329	case 0xa00:
	2330	verboselog(space.machine(), 2, "mc68328_r (%04x): LSSA(16) = %04x\n", mem_mask, mc68328->regs.lssa >> 16);
	2331	return mc68328->regs.lssa >> 16;
	2332
	2333	case 0xa02:
	2334	verboselog(space.machine(), 2, "mc68328_r (%04x): LSSA(0) = %04x\n", mem_mask, mc68328->regs.lssa & 0x0000ffff);
	2335	return mc68328->regs.lssa & 0x0000ffff;
	2336
	2337	case 0xa04:
	2338	if( mem_mask & 0x00ff )
	2339	{
	2340	verboselog(space.machine(), 2, "mc68328_r (%04x): LVPW = %02x\n", mem_mask, mc68328->regs.lvpw);
	2341	return mc68328->regs.lvpw;
	2342	}
	2343	else
	2344	{
	2345	verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa04)\n", mem_mask);
	2346	}
	2347	break;
	2348
	2349	case 0xa08:
	2350	verboselog(space.machine(), 2, "mc68328_r (%04x): LXMAX = %04x\n", mem_mask, mc68328->regs.lxmax);
	2351	return mc68328->regs.lxmax;
	2352
	2353	case 0xa0a:
	2354	verboselog(space.machine(), 2, "mc68328_r (%04x): LYMAX = %04x\n", mem_mask, mc68328->regs.lymax);
	2355	return mc68328->regs.lymax;
	2356
	2357	case 0xa18:
	2358	verboselog(space.machine(), 2, "mc68328_r (%04x): LCXP = %04x\n", mem_mask, mc68328->regs.lcxp);
	2359	return mc68328->regs.lcxp;
	2360
	2361	case 0xa1a:
	2362	verboselog(space.machine(), 2, "mc68328_r (%04x): LCYP = %04x\n", mem_mask, mc68328->regs.lcyp);
	2363	return mc68328->regs.lcyp;
	2364
	2365	case 0xa1c:
	2366	verboselog(space.machine(), 2, "mc68328_r (%04x): LCWCH = %04x\n", mem_mask, mc68328->regs.lcwch);
	2367	return mc68328->regs.lcwch;
	2368
	2369	case 0xa1e:
	2370	if( mem_mask & 0x00ff )
	2371	{
	2372	verboselog(space.machine(), 2, "mc68328_r (%04x): LBLKC = %02x\n", mem_mask, mc68328->regs.lblkc);
	2373	return mc68328->regs.lblkc;
	2374	}
	2375	else
	2376	{
	2377	verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa1e)\n", mem_mask);
	2378	}
	2379	break;
	2380
	2381	case 0xa20:
	2382	if( mem_mask & 0x00ff )
	2383	{
	2384	verboselog(space.machine(), 2, "mc68328_r (%04x): LPOLCF = %02x\n", mem_mask, mc68328->regs.lpolcf);
	2385	return mc68328->regs.lpolcf;
	2386	}
	2387	else
	2388	{
	2389	verboselog(space.machine(), 2, "mc68328_r (%04x): LPICF = %02x\n", mem_mask, mc68328->regs.lpicf);
	2390	return mc68328->regs.lpicf << 8;
	2391	}
	2392	break;
	2393
	2394	case 0xa22:
	2395	if( mem_mask & 0x00ff )
	2396	{
	2397	verboselog(space.machine(), 2, "mc68328_r (%04x): LACDRC = %02x\n", mem_mask, mc68328->regs.lacdrc);
	2398	return mc68328->regs.lacdrc;
	2399	}
	2400	else
	2401	{
	2402	verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa22)\n", mem_mask);
	2403	}
	2404	break;
	2405
	2406	case 0xa24:
	2407	if( mem_mask & 0x00ff )
	2408	{
	2409	verboselog(space.machine(), 2, "mc68328_r (%04x): LPXCD = %02x\n", mem_mask, mc68328->regs.lpxcd);
	2410	return mc68328->regs.lpxcd;
	2411	}
	2412	else
	2413	{
	2414	verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa24)\n", mem_mask);
	2415	}
	2416	break;
	2417
	2418	case 0xa26:
	2419	if( mem_mask & 0x00ff )
	2420	{
	2421	verboselog(space.machine(), 2, "mc68328_r (%04x): LCKCON = %02x\n", mem_mask, mc68328->regs.lckcon);
	2422	return mc68328->regs.lckcon;
	2423	}
	2424	else
	2425	{
	2426	verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa26)\n", mem_mask);
	2427	}
	2428	break;
	2429
	2430	case 0xa28:
	2431	if( mem_mask & 0x00ff )
	2432	{
	2433	verboselog(space.machine(), 2, "mc68328_r (%04x): LLBAR = %02x\n", mem_mask, mc68328->regs.llbar);
	2434	return mc68328->regs.llbar;
	2435	}
	2436	else
	2437	{
	2438	verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa28)\n", mem_mask);
	2439	}
	2440	break;
	2441
	2442	case 0xa2a:
	2443	if( mem_mask & 0x00ff )
	2444	{
	2445	verboselog(space.machine(), 2, "mc68328_r (%04x): LOTCR = %02x\n", mem_mask, mc68328->regs.lotcr);
	2446	return mc68328->regs.lotcr;
	2447	}
	2448	else
	2449	{
	2450	verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa2a)\n", mem_mask);
	2451	}
	2452	break;
	2453
	2454	case 0xa2c:
	2455	if( mem_mask & 0x00ff )
	2456	{
	2457	verboselog(space.machine(), 2, "mc68328_r (%04x): LPOSR = %02x\n", mem_mask, mc68328->regs.lposr);
	2458	return mc68328->regs.lposr;
	2459	}
	2460	else
	2461	{
	2462	verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa2c)\n", mem_mask);
	2463	}
	2464	break;
	2465
	2466	case 0xa30:
	2467	if( mem_mask & 0x00ff )
	2468	{
	2469	verboselog(space.machine(), 2, "mc68328_r (%04x): LFRCM = %02x\n", mem_mask, mc68328->regs.lfrcm);
	2470	return mc68328->regs.lfrcm;
	2471	}
	2472	else
	2473	{
	2474	verboselog(space.machine(), 2, "mc68328_r (%04x): Unknown address (0xfffa30)\n", mem_mask);
	2475	}
	2476	break;
	2477
	2478	case 0xa32:
	2479	verboselog(space.machine(), 2, "mc68328_r (%04x): LGPMR = %04x\n", mem_mask, mc68328->regs.lgpmr);
	2480	return mc68328->regs.lgpmr;
	2481
	2482	case 0xb00:
	2483	verboselog(space.machine(), 2, "mc68328_r (%04x): HMSR(0) = %04x\n", mem_mask, mc68328->regs.hmsr & 0x0000ffff);
	2484	return mc68328->regs.hmsr & 0x0000ffff;
	2485
	2486	case 0xb02:
	2487	verboselog(space.machine(), 2, "mc68328_r (%04x): HMSR(16) = %04x\n", mem_mask, mc68328->regs.hmsr >> 16);
	2488	return mc68328->regs.hmsr >> 16;
	2489
	2490	case 0xb04:
	2491	verboselog(space.machine(), 2, "mc68328_r (%04x): ALARM(0) = %04x\n", mem_mask, mc68328->regs.alarm & 0x0000ffff);
	2492	return mc68328->regs.alarm & 0x0000ffff;
	2493
	2494	case 0xb06:
	2495	verboselog(space.machine(), 2, "mc68328_r (%04x): ALARM(16) = %04x\n", mem_mask, mc68328->regs.alarm >> 16);
	2496	return mc68328->regs.alarm >> 16;
	2497
	2498	case 0xb0c:
	2499	verboselog(space.machine(), 2, "mc68328_r (%04x): RTCCTL = %04x\n", mem_mask, mc68328->regs.rtcctl);
	2500	return mc68328->regs.rtcctl;
	2501
	2502	case 0xb0e:
	2503	verboselog(space.machine(), 2, "mc68328_r (%04x): RTCISR = %04x\n", mem_mask, mc68328->regs.rtcisr);
	2504	return mc68328->regs.rtcisr;
	2505
	2506	case 0xb10:
	2507	verboselog(space.machine(), 2, "mc68328_r (%04x): RTCIENR = %04x\n", mem_mask, mc68328->regs.rtcienr);
	2508	return mc68328->regs.rtcienr;
	2509
	2510	case 0xb12:
	2511	verboselog(space.machine(), 2, "mc68328_r (%04x): STPWTCH = %04x\n", mem_mask, mc68328->regs.stpwtch);
	2512	return mc68328->regs.stpwtch;
	2513
	2514	default:
	2515	verboselog(space.machine(), 0, "mc68328_r (%04x): Unknown address (0x%06x)\n", mem_mask, 0xfff000 + address);
	2516	break;
	2517	}
	2518	return 0;
	2519	}
	2520
	2521	static DEVICE_RESET( mc68328 )
	2522	{
	2523	mc68328_t* mc68328 = mc68328_get_safe_token( device );
	2524
	2525	mc68328->regs.scr = 0x0c;
	2526	mc68328->regs.grpbasea = 0x0000;
	2527	mc68328->regs.grpbaseb = 0x0000;
	2528	mc68328->regs.grpbasec = 0x0000;
	2529	mc68328->regs.grpbased = 0x0000;
	2530	mc68328->regs.grpmaska = 0x0000;
	2531	mc68328->regs.grpmaskb = 0x0000;
	2532	mc68328->regs.grpmaskc = 0x0000;
	2533	mc68328->regs.grpmaskd = 0x0000;
	2534	mc68328->regs.csa0 = 0x00010006;
	2535	mc68328->regs.csa1 = 0x00010006;
	2536	mc68328->regs.csa2 = 0x00010006;
	2537	mc68328->regs.csa3 = 0x00010006;
	2538	mc68328->regs.csb0 = 0x00010006;
	2539	mc68328->regs.csb1 = 0x00010006;
	2540	mc68328->regs.csb2 = 0x00010006;
	2541	mc68328->regs.csb3 = 0x00010006;
	2542	mc68328->regs.csc0 = 0x00010006;
	2543	mc68328->regs.csc1 = 0x00010006;
	2544	mc68328->regs.csc2 = 0x00010006;
	2545	mc68328->regs.csc3 = 0x00010006;
	2546	mc68328->regs.csd0 = 0x00010006;
	2547	mc68328->regs.csd1 = 0x00010006;
	2548	mc68328->regs.csd2 = 0x00010006;
	2549	mc68328->regs.csd3 = 0x00010006;
	2550
	2551	mc68328->regs.pllcr = 0x2400;
	2552	mc68328->regs.pllfsr = 0x0123;
	2553	mc68328->regs.pctlr = 0x1f;
	2554
	2555	mc68328->regs.ivr = 0x00;
	2556	mc68328->regs.icr = 0x0000;
	2557	mc68328->regs.imr = 0x00ffffff;
	2558	mc68328->regs.iwr = 0x00ffffff;
	2559	mc68328->regs.isr = 0x00000000;
	2560	mc68328->regs.ipr = 0x00000000;
	2561
	2562	mc68328->regs.padir = 0x00;
	2563	mc68328->regs.padata = 0x00;
	2564	mc68328->regs.pasel = 0x00;
	2565	mc68328->regs.pbdir = 0x00;
	2566	mc68328->regs.pbdata = 0x00;
	2567	mc68328->regs.pbsel = 0x00;
	2568	mc68328->regs.pcdir = 0x00;
	2569	mc68328->regs.pcdata = 0x00;
	2570	mc68328->regs.pcsel = 0x00;
	2571	mc68328->regs.pddir = 0x00;
	2572	mc68328->regs.pddata = 0x00;
	2573	mc68328->regs.pdpuen = 0xff;
	2574	mc68328->regs.pdpol = 0x00;
	2575	mc68328->regs.pdirqen = 0x00;
	2576	mc68328->regs.pddataedge = 0x00;
	2577	mc68328->regs.pdirqedge = 0x00;
	2578	mc68328->regs.pedir = 0x00;
	2579	mc68328->regs.pedata = 0x00;
	2580	mc68328->regs.pepuen = 0x80;
	2581	mc68328->regs.pesel = 0x80;
	2582	mc68328->regs.pfdir = 0x00;
	2583	mc68328->regs.pfdata = 0x00;
	2584	mc68328->regs.pfpuen = 0xff;
	2585	mc68328->regs.pfsel = 0xff;
	2586	mc68328->regs.pgdir = 0x00;
	2587	mc68328->regs.pgdata = 0x00;
	2588	mc68328->regs.pgpuen = 0xff;
	2589	mc68328->regs.pgsel = 0xff;
	2590	mc68328->regs.pjdir = 0x00;
	2591	mc68328->regs.pjdata = 0x00;
	2592	mc68328->regs.pjsel = 0x00;
	2593	mc68328->regs.pkdir = 0x00;
	2594	mc68328->regs.pkdata = 0x00;
	2595	mc68328->regs.pkpuen = 0xff;
	2596	mc68328->regs.pksel = 0xff;
	2597	mc68328->regs.pmdir = 0x00;
	2598	mc68328->regs.pmdata = 0x00;
	2599	mc68328->regs.pmpuen = 0xff;
	2600	mc68328->regs.pmsel = 0xff;
	2601
	2602	mc68328->regs.pwmc = 0x0000;
	2603	mc68328->regs.pwmp = 0x0000;
	2604	mc68328->regs.pwmw = 0x0000;
	2605	mc68328->regs.pwmcnt = 0x0000;
	2606
	2607	mc68328->regs.tctl[0] = mc68328->regs.tctl[1] = 0x0000;
	2608	mc68328->regs.tprer[0] = mc68328->regs.tprer[1] = 0x0000;
	2609	mc68328->regs.tcmp[0] = mc68328->regs.tcmp[1] = 0xffff;
	2610	mc68328->regs.tcr[0] = mc68328->regs.tcr[1] = 0x0000;
	2611	mc68328->regs.tcn[0] = mc68328->regs.tcn[1] = 0x0000;
	2612	mc68328->regs.tstat[0] = mc68328->regs.tstat[1] = 0x0000;
	2613	mc68328->regs.wctlr = 0x0000;
	2614	mc68328->regs.wcmpr = 0xffff;
	2615	mc68328->regs.wcn = 0x0000;
	2616
	2617	mc68328->regs.spisr = 0x0000;
	2618
	2619	mc68328->regs.spimdata = 0x0000;
	2620	mc68328->regs.spimcont = 0x0000;
	2621
	2622	mc68328->regs.ustcnt = 0x0000;
	2623	mc68328->regs.ubaud = 0x003f;
	2624	mc68328->regs.urx = 0x0000;
	2625	mc68328->regs.utx = 0x0000;
	2626	mc68328->regs.umisc = 0x0000;
	2627
	2628	mc68328->regs.lssa = 0x00000000;
	2629	mc68328->regs.lvpw = 0xff;
	2630	mc68328->regs.lxmax = 0x03ff;
	2631	mc68328->regs.lymax = 0x01ff;
	2632	mc68328->regs.lcxp = 0x0000;
	2633	mc68328->regs.lcyp = 0x0000;
	2634	mc68328->regs.lcwch = 0x0101;
	2635	mc68328->regs.lblkc = 0x7f;
	2636	mc68328->regs.lpicf = 0x00;
	2637	mc68328->regs.lpolcf = 0x00;
	2638	mc68328->regs.lacdrc = 0x00;
	2639	mc68328->regs.lpxcd = 0x00;
	2640	mc68328->regs.lckcon = 0x40;
	2641	mc68328->regs.llbar = 0x3e;
	2642	mc68328->regs.lotcr = 0x3f;
	2643	mc68328->regs.lposr = 0x00;
	2644	mc68328->regs.lfrcm = 0xb9;
	2645	mc68328->regs.lgpmr = 0x1073;
	2646
	2647	mc68328->regs.hmsr = 0x00000000;
	2648	mc68328->regs.alarm = 0x00000000;
	2649	mc68328->regs.rtcctl = 0x00;
	2650	mc68328->regs.rtcisr = 0x00;
	2651	mc68328->regs.rtcienr = 0x00;
	2652	mc68328->regs.stpwtch = 0x00;
	2653
	2654	mc68328->rtc->adjust(attotime::from_hz(1), 0, attotime::from_hz(1));
	2655	}
	2656
	2657	static void mc68328_register_state_save(device_t *device)
	2658	{
	2659	mc68328_t* mc68328 = mc68328_get_safe_token( device );
	2660
	2661	state_save_register_global(device->machine(), mc68328->regs.scr);
	2662	state_save_register_global(device->machine(), mc68328->regs.grpbasea);
	2663	state_save_register_global(device->machine(), mc68328->regs.grpbaseb);
	2664	state_save_register_global(device->machine(), mc68328->regs.grpbasec);
	2665	state_save_register_global(device->machine(), mc68328->regs.grpbased);
	2666	state_save_register_global(device->machine(), mc68328->regs.grpmaska);
	2667	state_save_register_global(device->machine(), mc68328->regs.grpmaskb);
	2668	state_save_register_global(device->machine(), mc68328->regs.grpmaskc);
	2669	state_save_register_global(device->machine(), mc68328->regs.grpmaskd);
	2670	state_save_register_global(device->machine(), mc68328->regs.csa0);
	2671	state_save_register_global(device->machine(), mc68328->regs.csa1);
	2672	state_save_register_global(device->machine(), mc68328->regs.csa2);
	2673	state_save_register_global(device->machine(), mc68328->regs.csa3);
	2674	state_save_register_global(device->machine(), mc68328->regs.csb0);
	2675	state_save_register_global(device->machine(), mc68328->regs.csb1);
	2676	state_save_register_global(device->machine(), mc68328->regs.csb2);
	2677	state_save_register_global(device->machine(), mc68328->regs.csb3);
	2678	state_save_register_global(device->machine(), mc68328->regs.csc0);
	2679	state_save_register_global(device->machine(), mc68328->regs.csc1);
	2680	state_save_register_global(device->machine(), mc68328->regs.csc2);
	2681	state_save_register_global(device->machine(), mc68328->regs.csc3);
	2682	state_save_register_global(device->machine(), mc68328->regs.csd0);
	2683	state_save_register_global(device->machine(), mc68328->regs.csd1);
	2684	state_save_register_global(device->machine(), mc68328->regs.csd2);
	2685	state_save_register_global(device->machine(), mc68328->regs.csd3);
	2686
	2687	state_save_register_global(device->machine(), mc68328->regs.pllcr);
	2688	state_save_register_global(device->machine(), mc68328->regs.pllfsr);
	2689	state_save_register_global(device->machine(), mc68328->regs.pctlr);
	2690
	2691	state_save_register_global(device->machine(), mc68328->regs.ivr);
	2692	state_save_register_global(device->machine(), mc68328->regs.icr);
	2693	state_save_register_global(device->machine(), mc68328->regs.imr);
	2694	state_save_register_global(device->machine(), mc68328->regs.iwr);
	2695	state_save_register_global(device->machine(), mc68328->regs.isr);
	2696	state_save_register_global(device->machine(), mc68328->regs.ipr);
	2697
	2698	state_save_register_global(device->machine(), mc68328->regs.padir);
	2699	state_save_register_global(device->machine(), mc68328->regs.padata);
	2700	state_save_register_global(device->machine(), mc68328->regs.pasel);
	2701	state_save_register_global(device->machine(), mc68328->regs.pbdir);
	2702	state_save_register_global(device->machine(), mc68328->regs.pbdata);
	2703	state_save_register_global(device->machine(), mc68328->regs.pbsel);
	2704	state_save_register_global(device->machine(), mc68328->regs.pcdir);
	2705	state_save_register_global(device->machine(), mc68328->regs.pcdata);
	2706	state_save_register_global(device->machine(), mc68328->regs.pcsel);
	2707	state_save_register_global(device->machine(), mc68328->regs.pddir);
	2708	state_save_register_global(device->machine(), mc68328->regs.pddata);
	2709	state_save_register_global(device->machine(), mc68328->regs.pdpuen);
	2710	state_save_register_global(device->machine(), mc68328->regs.pdpol);
	2711	state_save_register_global(device->machine(), mc68328->regs.pdirqen);
	2712	state_save_register_global(device->machine(), mc68328->regs.pddataedge);
	2713	state_save_register_global(device->machine(), mc68328->regs.pdirqedge);
	2714	state_save_register_global(device->machine(), mc68328->regs.pedir);
	2715	state_save_register_global(device->machine(), mc68328->regs.pedata);
	2716	state_save_register_global(device->machine(), mc68328->regs.pepuen);
	2717	state_save_register_global(device->machine(), mc68328->regs.pesel);
	2718	state_save_register_global(device->machine(), mc68328->regs.pfdir);
	2719	state_save_register_global(device->machine(), mc68328->regs.pfdata);
	2720	state_save_register_global(device->machine(), mc68328->regs.pfpuen);
	2721	state_save_register_global(device->machine(), mc68328->regs.pfsel);
	2722	state_save_register_global(device->machine(), mc68328->regs.pgdir);
	2723	state_save_register_global(device->machine(), mc68328->regs.pgdata);
	2724	state_save_register_global(device->machine(), mc68328->regs.pgpuen);
	2725	state_save_register_global(device->machine(), mc68328->regs.pgsel);
	2726	state_save_register_global(device->machine(), mc68328->regs.pjdir);
	2727	state_save_register_global(device->machine(), mc68328->regs.pjdata);
	2728	state_save_register_global(device->machine(), mc68328->regs.pjsel);
	2729	state_save_register_global(device->machine(), mc68328->regs.pkdir);
	2730	state_save_register_global(device->machine(), mc68328->regs.pkdata);
	2731	state_save_register_global(device->machine(), mc68328->regs.pkpuen);
	2732	state_save_register_global(device->machine(), mc68328->regs.pksel);
	2733	state_save_register_global(device->machine(), mc68328->regs.pmdir);
	2734	state_save_register_global(device->machine(), mc68328->regs.pmdata);
	2735	state_save_register_global(device->machine(), mc68328->regs.pmpuen);
	2736	state_save_register_global(device->machine(), mc68328->regs.pmsel);
	2737
	2738	state_save_register_global(device->machine(), mc68328->regs.pwmc);
	2739	state_save_register_global(device->machine(), mc68328->regs.pwmp);
	2740	state_save_register_global(device->machine(), mc68328->regs.pwmw);
	2741	state_save_register_global(device->machine(), mc68328->regs.pwmcnt);
	2742
	2743	state_save_register_global(device->machine(), mc68328->regs.tctl[0]);
	2744	state_save_register_global(device->machine(), mc68328->regs.tctl[1]);
	2745	state_save_register_global(device->machine(), mc68328->regs.tprer[0]);
	2746	state_save_register_global(device->machine(), mc68328->regs.tprer[1]);
	2747	state_save_register_global(device->machine(), mc68328->regs.tcmp[0]);
	2748	state_save_register_global(device->machine(), mc68328->regs.tcmp[1]);
	2749	state_save_register_global(device->machine(), mc68328->regs.tcr[0]);
	2750	state_save_register_global(device->machine(), mc68328->regs.tcr[1]);
	2751	state_save_register_global(device->machine(), mc68328->regs.tcn[0]);
	2752	state_save_register_global(device->machine(), mc68328->regs.tcn[1]);
	2753	state_save_register_global(device->machine(), mc68328->regs.tstat[0]);
	2754	state_save_register_global(device->machine(), mc68328->regs.tstat[1]);
	2755	state_save_register_global(device->machine(), mc68328->regs.wctlr);
	2756	state_save_register_global(device->machine(), mc68328->regs.wcmpr);
	2757	state_save_register_global(device->machine(), mc68328->regs.wcn);
	2758
	2759	state_save_register_global(device->machine(), mc68328->regs.spisr);
	2760
	2761	state_save_register_global(device->machine(), mc68328->regs.spimdata);
	2762	state_save_register_global(device->machine(), mc68328->regs.spimcont);
	2763
	2764	state_save_register_global(device->machine(), mc68328->regs.ustcnt);
	2765	state_save_register_global(device->machine(), mc68328->regs.ubaud);
	2766	state_save_register_global(device->machine(), mc68328->regs.urx);
	2767	state_save_register_global(device->machine(), mc68328->regs.utx);
	2768	state_save_register_global(device->machine(), mc68328->regs.umisc);
	2769
	2770	state_save_register_global(device->machine(), mc68328->regs.lssa);
	2771	state_save_register_global(device->machine(), mc68328->regs.lvpw);
	2772	state_save_register_global(device->machine(), mc68328->regs.lxmax);
	2773	state_save_register_global(device->machine(), mc68328->regs.lymax);
	2774	state_save_register_global(device->machine(), mc68328->regs.lcxp);
	2775	state_save_register_global(device->machine(), mc68328->regs.lcyp);
	2776	state_save_register_global(device->machine(), mc68328->regs.lcwch);
	2777	state_save_register_global(device->machine(), mc68328->regs.lblkc);
	2778	state_save_register_global(device->machine(), mc68328->regs.lpicf);
	2779	state_save_register_global(device->machine(), mc68328->regs.lpolcf);
	2780	state_save_register_global(device->machine(), mc68328->regs.lacdrc);
	2781	state_save_register_global(device->machine(), mc68328->regs.lpxcd);
	2782	state_save_register_global(device->machine(), mc68328->regs.lckcon);
	2783	state_save_register_global(device->machine(), mc68328->regs.llbar);
	2784	state_save_register_global(device->machine(), mc68328->regs.lotcr);
	2785	state_save_register_global(device->machine(), mc68328->regs.lposr);
	2786	state_save_register_global(device->machine(), mc68328->regs.lfrcm);
	2787	state_save_register_global(device->machine(), mc68328->regs.lgpmr);
	2788
	2789	state_save_register_global(device->machine(), mc68328->regs.hmsr);
	2790	state_save_register_global(device->machine(), mc68328->regs.alarm);
	2791	state_save_register_global(device->machine(), mc68328->regs.rtcctl);
	2792	state_save_register_global(device->machine(), mc68328->regs.rtcisr);
	2793	state_save_register_global(device->machine(), mc68328->regs.rtcienr);
	2794	state_save_register_global(device->machine(), mc68328->regs.stpwtch);
	2795	}
	2796
	2797	static DEVICE_START( mc68328 )
	2798	{
	2799	mc68328_t* mc68328 = mc68328_get_safe_token( device );
	2800
	2801	mc68328->iface = (const mc68328_interface*)device->static_config();
	2802
	2803	mc68328->out_port_a.resolve(mc68328->iface->out_port_a_func, *device);
	2804	mc68328->out_port_b.resolve(mc68328->iface->out_port_b_func, *device);
	2805	mc68328->out_port_c.resolve(mc68328->iface->out_port_c_func, *device);
	2806	mc68328->out_port_d.resolve(mc68328->iface->out_port_d_func, *device);
	2807	mc68328->out_port_e.resolve(mc68328->iface->out_port_e_func, *device);
	2808	mc68328->out_port_f.resolve(mc68328->iface->out_port_f_func, *device);
	2809	mc68328->out_port_g.resolve(mc68328->iface->out_port_g_func, *device);
	2810	mc68328->out_port_j.resolve(mc68328->iface->out_port_j_func, *device);
	2811	mc68328->out_port_k.resolve(mc68328->iface->out_port_k_func, *device);
	2812	mc68328->out_port_m.resolve(mc68328->iface->out_port_m_func, *device);
	2813
	2814	mc68328->in_port_a.resolve(mc68328->iface->in_port_a_func, *device);
	2815	mc68328->in_port_b.resolve(mc68328->iface->in_port_b_func, *device);
	2816	mc68328->in_port_c.resolve(mc68328->iface->in_port_c_func, *device);
	2817	mc68328->in_port_d.resolve(mc68328->iface->in_port_d_func, *device);
	2818	mc68328->in_port_e.resolve(mc68328->iface->in_port_e_func, *device);
	2819	mc68328->in_port_f.resolve(mc68328->iface->in_port_f_func, *device);
	2820	mc68328->in_port_g.resolve(mc68328->iface->in_port_g_func, *device);
	2821	mc68328->in_port_j.resolve(mc68328->iface->in_port_j_func, *device);
	2822	mc68328->in_port_k.resolve(mc68328->iface->in_port_k_func, *device);
	2823	mc68328->in_port_m.resolve(mc68328->iface->in_port_m_func, *device);
	2824
	2825	mc68328->out_pwm.resolve(mc68328->iface->out_pwm_func, *device);
	2826
	2827	mc68328->out_spim.resolve(mc68328->iface->out_spim_func, *device);
	2828	mc68328->in_spim.resolve(mc68328->iface->in_spim_func, *device);
	2829
	2830	mc68328->gptimer[0] = device->machine().scheduler().timer_alloc(FUNC(mc68328_timer1_hit));
	2831	mc68328->gptimer[1] = device->machine().scheduler().timer_alloc(FUNC(mc68328_timer2_hit));
	2832	mc68328->rtc = device->machine().scheduler().timer_alloc(FUNC(mc68328_rtc_tick));
	2833	mc68328->pwm = device->machine().scheduler().timer_alloc(FUNC(mc68328_pwm_transition));
	2834
	2835	mc68328_register_state_save(device);
	2836	}
	2837
	2838	const device_type MC68328 = &device_creator<mc68328_device>;
	2839
	2840	mc68328_device::mc68328_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	2841	: device_t(mconfig, MC68328, "Motorola MC68328 (DragonBall) Integrated Processor", tag, owner, clock)
	2842	{
	2843	m_token = global_alloc_clear(mc68328_t);
	2844	}
	2845
	2846	//-------------------------------------------------
	2847	// device_config_complete - perform any
	2848	// operations now that the configuration is
	2849	// complete
	2850	//-------------------------------------------------
	2851
	2852	void mc68328_device::device_config_complete()
	2853	{
	2854	}
	2855
	2856	//-------------------------------------------------
	2857	// device_start - device-specific startup
	2858	//-------------------------------------------------
	2859
	2860	void mc68328_device::device_start()
	2861	{
	2862	DEVICE_START_NAME( mc68328 )(this);
	2863	}
	2864
	2865	//-------------------------------------------------
	2866	// device_reset - device-specific reset
	2867	//-------------------------------------------------
	2868
	2869	void mc68328_device::device_reset()
	2870	{
	2871	DEVICE_RESET_NAME( mc68328 )(this);
	2872	}

Property changes on: trunk/src/mess/machine/mc68328.c
Added: svn:eol-style + native Added: svn:mime-type + text/plain

trunk/src/mess/machine/mc68328.h
r0	r21689
	1	/**********************************************************************
	2
	3	Motorola 68328 ("DragonBall") System-on-a-Chip private data
	4
	5	By MooglyGuy
	6	contact mooglyguy@gmail.com with licensing and usage questions.
	7
	8	**********************************************************************/
	9
	10	#ifndef __MC68328_PRIVATE_H_
	11	#define __MC68328_PRIVATE_H_
	12
	13	struct mc68328_regs_t
	14	{
	15	// $(FF)FFF000
	16	UINT8 scr; // System Control Register
	17	UINT8 unused0[255];
	18
	19	// $(FF)FFF100
	20	UINT16 grpbasea; // Chip Select Group A Base Register
	21	UINT16 grpbaseb; // Chip Select Group B Base Register
	22	UINT16 grpbasec; // Chip Select Group C Base Register
	23	UINT16 grpbased; // Chip Select Group D Base Register
	24	UINT16 grpmaska; // Chip Select Group A Mask Register
	25	UINT16 grpmaskb; // Chip Select Group B Mask Register
	26	UINT16 grpmaskc; // Chip Select Group C Mask Register
	27	UINT16 grpmaskd; // Chip Select Group D Mask Register
	28	UINT32 csa0; // Group A Chip Select 0 Register
	29	UINT32 csa1; // Group A Chip Select 1 Register
	30	UINT32 csa2; // Group A Chip Select 2 Register
	31	UINT32 csa3; // Group A Chip Select 3 Register
	32	UINT32 csb0; // Group B Chip Select 0 Register
	33	UINT32 csb1; // Group B Chip Select 1 Register
	34	UINT32 csb2; // Group B Chip Select 2 Register
	35	UINT32 csb3; // Group B Chip Select 3 Register
	36	UINT32 csc0; // Group C Chip Select 0 Register
	37	UINT32 csc1; // Group C Chip Select 1 Register
	38	UINT32 csc2; // Group C Chip Select 2 Register
	39	UINT32 csc3; // Group C Chip Select 3 Register
	40	UINT32 csd0; // Group D Chip Select 0 Register
	41	UINT32 csd1; // Group D Chip Select 1 Register
	42	UINT32 csd2; // Group D Chip Select 2 Register
	43	UINT32 csd3; // Group D Chip Select 3 Register
	44	UINT8 unused1[176];
	45
	46	// $(FF)FFF200
	47	UINT16 pllcr; // PLL Control Register
	48	UINT16 pllfsr; // PLL Frequency Select Register
	49	UINT8 pad2[3];
	50	UINT8 pctlr; // Power Control Register
	51	UINT8 unused3[248];
	52
	53	// $(FF)FFF300
	54	UINT8 ivr; // Interrupt Vector Register
	55	UINT8 unused4[1];
	56	UINT16 icr; // Interrupt Control Register
	57	UINT32 imr; // Interrupt Mask Register
	58	UINT32 iwr; // Interrupt Wakeup Enable Register
	59	UINT32 isr; // Interrupt Status Register
	60	UINT32 ipr; // Interrupt Pending Register
	61	UINT8 unused5[236];
	62
	63	// $(FF)FFF400
	64	UINT8 padir; // Port A Direction Register
	65	UINT8 padata; // Port A Data Register
	66	UINT8 unused6[1];
	67	UINT8 pasel; // Port A Select Register
	68	UINT8 unused7[4];
	69
	70	UINT8 pbdir; // Port B Direction Register
	71	UINT8 pbdata; // Port B Data Register
	72	UINT8 unused8[1];
	73	UINT8 pbsel; // Port B Select Register
	74	UINT8 unused9[4];
	75
	76	UINT8 pcdir; // Port C Direction Register
	77	UINT8 pcdata; // Port C Data Register
	78	UINT8 unused10[1];
	79	UINT8 pcsel; // Port C Select Register
	80	UINT8 unused11[4];
	81
	82	UINT8 pddir; // Port D Direction Register
	83	UINT8 pddata; // Port D Data Register
	84	UINT8 pdpuen; // Port D Pullup Enable Register
	85	UINT8 unused12[1];
	86	UINT8 pdpol; // Port D Polarity Register
	87	UINT8 pdirqen; // Port D IRQ Enable Register
	88	UINT8 pddataedge; // Port D Data Edge Level
	89	UINT8 pdirqedge; // Port D IRQ Edge Register
	90
	91	UINT8 pedir; // Port E Direction Register
	92	UINT8 pedata; // Port E Data Register
	93	UINT8 pepuen; // Port E Pullup Enable Register
	94	UINT8 pesel; // Port E Select Register
	95	UINT8 unused14[4];
	96
	97	UINT8 pfdir; // Port F Direction Register
	98	UINT8 pfdata; // Port F Data Register
	99	UINT8 pfpuen; // Port F Pullup Enable Register
	100	UINT8 pfsel; // Port F Select Register
	101	UINT8 unused15[4];
	102
	103	UINT8 pgdir; // Port G Direction Register
	104	UINT8 pgdata; // Port G Data Register
	105	UINT8 pgpuen; // Port G Pullup Enable Register
	106	UINT8 pgsel; // Port G Select Register
	107	UINT8 unused16[4];
	108
	109	UINT8 pjdir; // Port J Direction Register
	110	UINT8 pjdata; // Port J Data Register
	111	UINT8 unused17[1];
	112	UINT8 pjsel; // Port J Select Register
	113	UINT8 unused18[4];
	114	UINT8 pkdir; // Port K Direction Register
	115	UINT8 pkdata; // Port K Data Register
	116	UINT8 pkpuen; // Port K Pullup Enable Register
	117	UINT8 pksel; // Port K Select Register
	118	UINT8 unused19[4];
	119
	120	UINT8 pmdir; // Port M Direction Register
	121	UINT8 pmdata; // Port M Data Register
	122	UINT8 pmpuen; // Port M Pullup Enable Register
	123	UINT8 pmsel; // Port M Select Register
	124	UINT8 unused20[180];
	125
	126	// $(FF)FFF500
	127	UINT16 pwmc; // PWM Control Register
	128	UINT16 pwmp; // PWM Period Register
	129	UINT16 pwmw; // PWM Width Register
	130	UINT16 pwmcnt; // PWN Counter
	131	UINT8 unused21[248];
	132
	133	// $(FF)FFF600
	134	UINT16 tctl[2]; // Timer Control Register
	135	UINT16 tprer[2]; // Timer Prescaler Register
	136	UINT16 tcmp[2]; // Timer Compare Register
	137	UINT16 tcr[2]; // Timer Capture Register
	138	UINT16 tcn[2]; // Timer Counter
	139	UINT16 tstat[2]; // Timer Status
	140	UINT16 wctlr; // Watchdog Control Register
	141	UINT16 wcmpr; // Watchdog Compare Register
	142	UINT16 wcn; // Watchdog Counter
	143	UINT8 tclear[2]; // Timer Clearable Status
	144	UINT8 unused22[224];
	145
	146	// $(FF)FFF700
	147	UINT16 spisr; // SPIS Register
	148	UINT8 unused23[254];
	149
	150	// $(FF)FFF800
	151	UINT16 spimdata; // SPIM Data Register
	152	UINT16 spimcont; // SPIM Control/Status Register
	153	UINT8 unused24[252];
	154
	155	// $(FF)FFF900
	156	UINT16 ustcnt; // UART Status/Control Register
	157	UINT16 ubaud; // UART Baud Control Register
	158	UINT16 urx; // UART RX Register
	159	UINT16 utx; // UART TX Register
	160	UINT16 umisc; // UART Misc Register
	161	UINT8 unused25[246];
	162
	163	// $(FF)FFFA00
	164	UINT32 lssa; // Screen Starting Address Register
	165	UINT8 unused26[1];
	166	UINT8 lvpw; // Virtual Page Width Register
	167	UINT8 unused27[2];
	168	UINT16 lxmax; // Screen Width Register
	169	UINT16 lymax; // Screen Height Register
	170	UINT8 unused28[12];
	171	UINT16 lcxp; // Cursor X Position
	172	UINT16 lcyp; // Cursor Y Position
	173	UINT16 lcwch; // Cursor Width & Height Register
	174	UINT8 unused29[1];
	175	UINT8 lblkc; // Blink Control Register
	176	UINT8 lpicf; // Panel Interface Config Register
	177	UINT8 lpolcf; // Polarity Config Register
	178	UINT8 unused30[1];
	179	UINT8 lacdrc; // ACD (M) Rate Control Register
	180	UINT8 unused31[1];
	181	UINT8 lpxcd; // Pixel Clock Divider Register
	182	UINT8 unused32[1];
	183	UINT8 lckcon; // Clocking Control Register
	184	UINT8 unused33[1];
	185	UINT8 llbar; // Last Buffer Address Register
	186	UINT8 unused34[1];
	187	UINT8 lotcr; // Octet Terminal Count Register
	188	UINT8 unused35[1];
	189	UINT8 lposr; // Panning Offset Register
	190	UINT8 unused36[3];
	191	UINT8 lfrcm; // Frame Rate Control Modulation Register
	192	UINT16 lgpmr; // Gray Palette Mapping Register
	193	UINT8 unused37[204];
	194
	195	// $(FF)FFFB00
	196	UINT32 hmsr; // RTC Hours Minutes Seconds Register
	197	UINT32 alarm; // RTC Alarm Register
	198	UINT8 unused38[4];
	199	UINT16 rtcctl; // RTC Control Register
	200	UINT16 rtcisr; // RTC Interrupt Status Register
	201	UINT16 rtcienr; // RTC Interrupt Enable Register
	202	UINT16 stpwtch; // Stopwatch Minutes
	203	UINT8 unused42[1260];
	204	};
	205
	206	struct mc68328_t
	207	{
	208	const mc68328_interface* iface;
	209
	210	mc68328_regs_t regs;
	211
	212	emu_timer *gptimer[2];
	213	emu_timer *rtc;
	214	emu_timer *pwm;
	215
	216	devcb_resolved_write8 out_port_a; /* 8-bit output */
	217	devcb_resolved_write8 out_port_b; /* 8-bit output */
	218	devcb_resolved_write8 out_port_c; /* 8-bit output */
	219	devcb_resolved_write8 out_port_d; /* 8-bit output */
	220	devcb_resolved_write8 out_port_e; /* 8-bit output */
	221	devcb_resolved_write8 out_port_f; /* 8-bit output */
	222	devcb_resolved_write8 out_port_g; /* 8-bit output */
	223	devcb_resolved_write8 out_port_j; /* 8-bit output */
	224	devcb_resolved_write8 out_port_k; /* 8-bit output */
	225	devcb_resolved_write8 out_port_m; /* 8-bit output */
	226
	227	devcb_resolved_read8 in_port_a; /* 8-bit input */
	228	devcb_resolved_read8 in_port_b; /* 8-bit input */
	229	devcb_resolved_read8 in_port_c; /* 8-bit input */
	230	devcb_resolved_read8 in_port_d; /* 8-bit input */
	231	devcb_resolved_read8 in_port_e; /* 8-bit input */
	232	devcb_resolved_read8 in_port_f; /* 8-bit input */
	233	devcb_resolved_read8 in_port_g; /* 8-bit input */
	234	devcb_resolved_read8 in_port_j; /* 8-bit input */
	235	devcb_resolved_read8 in_port_k; /* 8-bit input */
	236	devcb_resolved_read8 in_port_m; /* 8-bit input */
	237
	238	devcb_resolved_write8 out_pwm; /* 1-bit output */
	239
	240	devcb_resolved_write16 out_spim; /* 16-bit output */
	241	devcb_resolved_read16 in_spim; /* 16-bit input */
	242	};
	243
	244	#define SCR_BETO 0x80
	245	#define SCR_WPV 0x40
	246	#define SCR_PRV 0x20
	247	#define SCR_BETEN 0x10
	248	#define SCR_SO 0x08
	249	#define SCR_DMAP 0x04
	250	#define SCR_WDTH8 0x01
	251
	252	#define ICR_POL6 0x0100
	253	#define ICR_POL3 0x0200
	254	#define ICR_POL2 0x0400
	255	#define ICR_POL1 0x0800
	256	#define ICR_ET6 0x1000
	257	#define ICR_ET3 0x2000
	258	#define ICR_ET2 0x4000
	259	#define ICR_ET1 0x8000
	260
	261	#define INT_SPIM 0x000001
	262	#define INT_TIMER2 0x000002
	263	#define INT_UART 0x000004
	264	#define INT_WDT 0x000008
	265	#define INT_RTC 0x000010
	266	#define INT_RESERVED 0x000020
	267	#define INT_KB 0x000040
	268	#define INT_PWM 0x000080
	269	#define INT_INT0 0x000100
	270	#define INT_INT1 0x000200
	271	#define INT_INT2 0x000400
	272	#define INT_INT3 0x000800
	273	#define INT_INT4 0x001000
	274	#define INT_INT5 0x002000
	275	#define INT_INT6 0x004000
	276	#define INT_INT7 0x008000
	277	#define INT_KBDINTS 0x00ff00
	278	#define INT_IRQ1 0x010000
	279	#define INT_IRQ2 0x020000
	280	#define INT_IRQ3 0x040000
	281	#define INT_IRQ6 0x080000
	282	#define INT_PEN 0x100000
	283	#define INT_SPIS 0x200000
	284	#define INT_TIMER1 0x400000
	285	#define INT_IRQ7 0x800000
	286
	287	#define INT_M68K_LINE1 (INT_IRQ1)
	288	#define INT_M68K_LINE2 (INT_IRQ2)
	289	#define INT_M68K_LINE3 (INT_IRQ3)
	290	#define INT_M68K_LINE4 (INT_INT0 \| INT_INT1 \| INT_INT2 \| INT_INT3 \| INT_INT4 \| INT_INT5 \| INT_INT6 \| INT_INT7 \| \
	291	INT_PWM \| INT_KB \| INT_RTC \| INT_WDT \| INT_UART \| INT_TIMER2 \| INT_SPIM)
	292	#define INT_M68K_LINE5 (INT_PEN)
	293	#define INT_M68K_LINE6 (INT_IRQ6 \| INT_TIMER1 \| INT_SPIS)
	294	#define INT_M68K_LINE7 (INT_IRQ7)
	295	#define INT_M68K_LINE67 (INT_M68K_LINE6 \| INT_M68K_LINE7)
	296	#define INT_M68K_LINE567 (INT_M68K_LINE5 \| INT_M68K_LINE6 \| INT_M68K_LINE7)
	297	#define INT_M68K_LINE4567 (INT_M68K_LINE4 \| INT_M68K_LINE5 \| INT_M68K_LINE6 \| INT_M68K_LINE7)
	298	#define INT_M68K_LINE34567 (INT_M68K_LINE3 \| INT_M68K_LINE4 \| INT_M68K_LINE5 \| INT_M68K_LINE6 \| INT_M68K_LINE7)
	299	#define INT_M68K_LINE234567 (INT_M68K_LINE2 \| INT_M68K_LINE3 \| INT_M68K_LINE4 \| INT_M68K_LINE5 \| INT_M68K_LINE6 \| INT_M68K_LINE7)
	300
	301	#define INT_IRQ1_SHIFT 0x000001
	302	#define INT_IRQ2_SHIFT 0x000002
	303	#define INT_IRQ3_SHIFT 0x000004
	304	#define INT_IRQ6_SHIFT 0x000008
	305	#define INT_PEN_SHIFT 0x000010
	306	#define INT_SPIS_SHIFT 0x000020
	307	#define INT_TIMER1_SHIFT 0x000040
	308	#define INT_IRQ7_SHIFT 0x000080
	309
	310	#define INT_ACTIVE 1
	311	#define INT_INACTIVE 0
	312
	313	#define GRPBASE_BASE_ADDR 0xfff0
	314	#define GRPBASE_VALID 0x0001
	315
	316	#define GRPMASK_BASE_MASK 0xfff0
	317
	318	#define CSAB_COMPARE 0xff000000
	319	#define CSAB_BSW 0x00010000
	320	#define CSAB_MASK 0x0000ff00
	321	#define CSAB_RO 0x00000008
	322	#define CSAB_WAIT 0x00000007
	323
	324	#define CSCD_COMPARE 0xfff00000
	325	#define CSCD_BSW 0x00010000
	326	#define CSCD_MASK 0x0000fff0
	327	#define CSCD_RO 0x00000008
	328	#define CSCD_WAIT 0x00000007
	329
	330	#define PLLCR_PIXCLK_SEL 0x3800
	331	#define PLLCR_PIXCLK_SEL_DIV2 0x0000
	332	#define PLLCR_PIXCLK_SEL_DIV4 0x0800
	333	#define PLLCR_PIXCLK_SEL_DIV8 0x1000
	334	#define PLLCR_PIXCLK_SEL_DIV16 0x1800
	335	#define PLLCR_PIXCLK_SEL_DIV1_0 0x2000
	336	#define PLLCR_PIXCLK_SEL_DIV1_1 0x2800
	337	#define PLLCR_PIXCLK_SEL_DIV1_2 0x3000
	338	#define PLLCR_PIXCLK_SEL_DIV1_3 0x3800
	339	#define PLLCR_SYSCLK_SEL 0x0700
	340	#define PLLCR_SYSCLK_SEL_DIV2 0x0000
	341	#define PLLCR_SYSCLK_SEL_DIV4 0x0100
	342	#define PLLCR_SYSCLK_SEL_DIV8 0x0200
	343	#define PLLCR_SYSCLK_SEL_DIV16 0x0300
	344	#define PLLCR_SYSCLK_SEL_DIV1_0 0x0400
	345	#define PLLCR_SYSCLK_SEL_DIV1_1 0x0500
	346	#define PLLCR_SYSCLK_SEL_DIV1_2 0x0600
	347	#define PLLCR_SYSCLK_SEL_DIV1_3 0x0700
	348	#define PLLCR_CLKEN 0x0010
	349	#define PLLCR_DISPLL 0x0008
	350
	351	#define PLLFSR_CLK32 0x8000
	352	#define PLLFSR_PROT 0x4000
	353	#define PLLFSR_QCNT 0x0f00
	354	#define PLLFSR_PCNT 0x00ff
	355
	356	#define PCTLR_PC_EN 0x80
	357	#define PCTLR_STOP 0x40
	358	#define PCTLR_WIDTH 0x1f
	359
	360	#define CXP_CC 0xc000
	361	#define CXP_CC_XLU 0x0000
	362	#define CXP_CC_BLACK 0x4000
	363	#define CXP_CC_INVERSE 0x8000
	364	#define CXP_CC_INVALID 0xc000
	365	#define CXP_MASK 0x03ff
	366
	367	#define CYP_MASK 0x01ff
	368
	369	#define CWCH_CW 0x1f00
	370	#define CWCH_CH 0x001f
	371
	372	#define BLKC_BKEN 0x80
	373	#define BLKC_BD 0x7f
	374
	375	#define LPICF_PBSIZ 0x06
	376	#define LPICF_PBSIZ_1 0x00
	377	#define LPICF_PBSIZ_2 0x02
	378	#define LPICF_PBSIZ_4 0x04
	379	#define LPICF_PBSIZ_INVALID 0x06
	380
	381	#define LPOLCF_LCKPOL 0x08
	382	#define LPOLCF_FLMPOL 0x04
	383	#define LPOLCF_LPPOL 0x02
	384	#define LPOLCF_PIXPOL 0x01
	385
	386	#define LACDRC_MASK 0x0f
	387
	388	#define LPXCD_MASK 0x3f
	389
	390	#define LCKCON_LCDC_EN 0x80
	391	#define LCKCON_LCDON 0x80
	392	#define LCKCON_DMA16 0x40
	393	#define LCKCON_WS 0x30
	394	#define LCKCON_WS_1 0x00
	395	#define LCKCON_WS_2 0x10
	396	#define LCKCON_WS_3 0x20
	397	#define LCKCON_WS_4 0x30
	398	#define LCKCON_DWIDTH 0x02
	399	#define LCKCON_PCDS 0x01
	400
	401	#define LBAR_MASK 0x7f
	402
	403	#define LPOSR_BOS 0x08
	404	#define LPOSR_POS 0x07
	405
	406	#define LFRCM_XMOD 0xf0
	407	#define LFRCM_YMOD 0x0f
	408
	409	#define LGPMR_PAL1 0x7000
	410	#define LGPMR_PAL0 0x0700
	411	#define LGPMR_PAL3 0x0070
	412	#define LGPMR_PAL2 0x0007
	413
	414	#define RTCHMSR_HOURS 0x1f000000
	415	#define RTCHMSR_MINUTES 0x003f0000
	416	#define RTCHMSR_SECONDS 0x0000003f
	417
	418	#define RTCCTL_38_4 0x0020
	419	#define RTCCTL_ENABLE 0x0080
	420
	421	#define RTCINT_STOPWATCH 0x0001
	422	#define RTCINT_MINUTE 0x0002
	423	#define RTCINT_ALARM 0x0004
	424	#define RTCINT_DAY 0x0008
	425	#define RTCINT_SECOND 0x0010
	426
	427	#define RTCSTPWTCH_MASK 0x003f
	428
	429	#define TCTL_TEN 0x0001
	430	#define TCTL_TEN_ENABLE 0x0001
	431	#define TCTL_CLKSOURCE 0x000e
	432	#define TCTL_CLKSOURCE_STOP 0x0000
	433	#define TCTL_CLKSOURCE_SYSCLK 0x0002
	434	#define TCTL_CLKSOURCE_SYSCLK16 0x0004
	435	#define TCTL_CLKSOURCE_TIN 0x0006
	436	#define TCTL_CLKSOURCE_32KHZ4 0x0008
	437	#define TCTL_CLKSOURCE_32KHZ5 0x000a
	438	#define TCTL_CLKSOURCE_32KHZ6 0x000c
	439	#define TCTL_CLKSOURCE_32KHZ7 0x000e
	440	#define TCTL_IRQEN 0x0010
	441	#define TCTL_IRQEN_ENABLE 0x0010
	442	#define TCTL_OM 0x0020
	443	#define TCTL_OM_ACTIVELOW 0x0000
	444	#define TCTL_OM_TOGGLE 0x0020
	445	#define TCTL_CAPTURE 0x00c0
	446	#define TCTL_CAPTURE_NOINT 0x0000
	447	#define TCTL_CAPTURE_RISING 0x0040
	448	#define TCTL_CAPTURE_FALLING 0x0080
	449	#define TCTL_CAPTURE_BOTH 0x00c0
	450	#define TCTL_FRR 0x0100
	451	#define TCTL_FRR_RESTART 0x0000
	452	#define TCTL_FRR_FREERUN 0x0100
	453
	454	#define TSTAT_COMP 0x0001
	455	#define TSTAT_CAPT 0x0002
	456
	457	#define WCTLR_WDRST 0x0008
	458	#define WCTLR_LOCK 0x0004
	459	#define WCTLR_FI 0x0002
	460	#define WCTLR_WDEN 0x0001
	461
	462	#define USTCNT_UART_EN 0x8000
	463	#define USTCNT_RX_EN 0x4000
	464	#define USTCNT_TX_EN 0x2000
	465	#define USTCNT_RX_CLK_CONT 0x1000
	466	#define USTCNT_PARITY_EN 0x0800
	467	#define USTCNT_ODD_EVEN 0x0400
	468	#define USTCNT_STOP_BITS 0x0200
	469	#define USTCNT_8_7 0x0100
	470	#define USTCNT_GPIO_DELTA_EN 0x0080
	471	#define USTCNT_CTS_DELTA_EN 0x0040
	472	#define USTCNT_RX_FULL_EN 0x0020
	473	#define USTCNT_RX_HALF_EN 0x0010
	474	#define USTCNT_RX_RDY_EN 0x0008
	475	#define USTCNT_TX_EMPTY_EN 0x0004
	476	#define USTCNT_TX_HALF_EN 0x0002
	477	#define USTCNT_TX_AVAIL_EN 0x0001
	478
	479	#define UBAUD_GPIO_DELTA 0x8000
	480	#define UBAUD_GPIO 0x4000
	481	#define UBAUD_GPIO_DIR 0x2000
	482	#define UBAUD_GPIO_SRC 0x1000
	483	#define UBAUD_BAUD_SRC 0x0800
	484	#define UBAUD_DIVIDE 0x0700
	485	#define UBAUD_DIVIDE_1 0x0000
	486	#define UBAUD_DIVIDE_2 0x0100
	487	#define UBAUD_DIVIDE_4 0x0200
	488	#define UBAUD_DIVIDE_8 0x0300
	489	#define UBAUD_DIVIDE_16 0x0400
	490	#define UBAUD_DIVIDE_32 0x0500
	491	#define UBAUD_DIVIDE_64 0x0600
	492	#define UBAUD_DIVIDE_128 0x0700
	493	#define UBAUD_PRESCALER 0x00ff
	494
	495	#define URX_FIFO_FULL 0x8000
	496	#define URX_FIFO_HALF 0x4000
	497	#define URX_DATA_READY 0x2000
	498	#define URX_OVRUN 0x0800
	499	#define URX_FRAME_ERROR 0x0400
	500	#define URX_BREAK 0x0200
	501	#define URX_PARITY_ERROR 0x0100
	502
	503	#define UTX_FIFO_EMPTY 0x8000
	504	#define UTX_FIFO_HALF 0x4000
	505	#define UTX_TX_AVAIL 0x2000
	506	#define UTX_SEND_BREAK 0x1000
	507	#define UTX_IGNORE_CTS 0x0800
	508	#define UTX_CTS_STATUS 0x0200
	509	#define UTX_CTS_DELTA 0x0100
	510
	511	#define UMISC_CLK_SRC 0x4000
	512	#define UMISC_FORCE_PERR 0x2000
	513	#define UMISC_LOOP 0x1000
	514	#define UMISC_RTS_CONT 0x0080
	515	#define UMISC_RTS 0x0040
	516	#define UMISC_IRDA_ENABLE 0x0020
	517	#define UMISC_IRDA_LOOP 0x0010
	518
	519	#define SPIS_SPIS_IRQ 0x8000
	520	#define SPIS_IRQEN 0x4000
	521	#define SPIS_ENPOL 0x2000
	522	#define SPIS_DATA_RDY 0x1000
	523	#define SPIS_OVRWR 0x0800
	524	#define SPIS_PHA 0x0400
	525	#define SPIS_POL 0x0200
	526	#define SPIS_SPISEN 0x0100
	527
	528	#define SPIM_CLOCK_COUNT 0x000f
	529	#define SPIM_POL 0x0010
	530	#define SPIM_POL_HIGH 0x0000
	531	#define SPIM_POL_LOW 0x0010
	532	#define SPIM_PHA 0x0020
	533	#define SPIM_PHA_NORMAL 0x0000
	534	#define SPIM_PHA_OPPOSITE 0x0020
	535	#define SPIM_IRQEN 0x0040
	536	#define SPIM_SPIMIRQ 0x0080
	537	#define SPIM_XCH 0x0100
	538	#define SPIM_XCH_IDLE 0x0000
	539	#define SPIM_XCH_INIT 0x0100
	540	#define SPIM_SPMEN 0x0200
	541	#define SPIM_SPMEN_DISABLE 0x0000
	542	#define SPIM_SPMEN_ENABLE 0x0200
	543	#define SPIM_RATE 0xe000
	544	#define SPIM_RATE_4 0x0000
	545	#define SPIM_RATE_8 0x2000
	546	#define SPIM_RATE_16 0x4000
	547	#define SPIM_RATE_32 0x6000
	548	#define SPIM_RATE_64 0x8000
	549	#define SPIM_RATE_128 0xa000
	550	#define SPIM_RATE_256 0xc000
	551	#define SPIM_RATE_512 0xe000
	552
	553	#define PWMC_PWMIRQ 0x8000
	554	#define PWMC_IRQEN 0x4000
	555	#define PWMC_LOAD 0x0100
	556	#define PWMC_PIN 0x0080
	557	#define PWMC_POL 0x0040
	558	#define PWMC_PWMEN 0x0010
	559	#define PWMC_CLKSEL 0x0007
	560
	561	INLINE mc68328_t* mc68328_get_safe_token( device_t *device )
	562	{
	563	assert( device != NULL );
	564	assert( device->type() == MC68328 );
	565	return (mc68328_t) downcast<mc68328_device >(device)->token();
	566	}
	567
	568	#endif // __MC68328_PRIVATE_H_

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trunk/src/mess/includes/mc68328.h
r0	r21689
	1	/**********************************************************************
	2
	3	Motorola 68328 ("DragonBall") System-on-a-Chip implementation
	4
	5	By MooglyGuy
	6	contact mooglyguy@gmail.com with licensing and usage questions.
	7
	8	**********************************************************************/
	9
	10	/*****************************************************************************************************************
	11
	12	P P P P P P P P P P P P P P
	13	E E E E E E E J J J J J J J
	14	1 2 3 4 5 6 7 0 1 2 3 4 5 6
	15	D D D D D / / / / / / / / / / / / / /
	16	3 4 5 6 7 ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
	17	/ / / / / ! ! C C C C C C C C C C C C C C C
	18	P V P P P P D D G D D D D T T L U V S S S S S S S S G S S S S S S S
	19	B C B B B B D D 1 1 N 1 1 1 1 M C W W C A A A A B B B B N C C C C D D D
	20	3 C 4 5 6 7 8 9 0 1 D 2 3 4 5 S K E E C 0 1 2 3 0 1 2 3 D 0 1 2 3 0 1 2
	21	\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|
	22	+-------------------------------------------------------------------------------+
	23	\| \|
	24	\| \|
	25	\| \|
	26	\| \|
	27	\| \|
	28	D2/PB2--\| \|--PJ7/!CSD3
	29	D1/PB1--\| \|--VCC
	30	D0/PB0--\| \|--PD0/!KBD0/!INT0
	31	TDO--\| \|--PD1/!KBD1/!INT1
	32	TDI--\| \|--PD2/!KBD2/!INT2
	33	GND--\| \|--PD3/!KBD3/!INT3
	34	!OE--\| \|--PD4/!KBD4/!INT4
	35	!UDS/PC1--\| \|--PD5/!KBD5/!INT5
	36	!AS--\| \|--PD6/!KBD6/!INT6
	37	A0--\| \|--PD7/!KBD7/!INT7
	38	!LDS--\| \|--GND
	39	R/!W--\| \|--LD0
	40	!DTACK/PC5--\| \|--LD1
	41	!RESET--\| \|--LD2
	42	VCC--\| \|--LD3
	43	!WE/PC6--\| \|--LFRM
	44	!JTAGRST--\| \|--LLP
	45	BBUSW--\| MC68328PV \|--LCLK
	46	A1--\| TOP VIEW \|--LACD
	47	A2--\| \|--VCC
	48	A3--\| \|--PK0/SPMTXD0
	49	A4--\| \|--PK1/SPMRXD0
	50	A5--\| \|--PK2/SPMCLK0
	51	A6--\| \|--PK3/SPSEN
	52	GND--\| \|--PK4/SPSRXD1
	53	A7--\| \|--PK5/SPSCLK1
	54	A8--\| \|--PK6/!CE2
	55	A9--\| \|--PK7/!CE1
	56	A10--\| \|--GND
	57	A11--\| \|--PM0/!CTS
	58	A12--\| \|--PM1/!RTS
	59	A13--\| \|--PM2/!IRQ6
	60	A14--\| \|--PM3/!IRQ3
	61	VCC--\| \|--PM4/!IRQ2
	62	A15--\| \|--PM5/!IRQ1
	63	A16/PA0--\| \|--PM6/!PENIRQ
	64	\| \|
	65	\| _ \|
	66	\| (_) \|
	67	\|\ \|
	68	\| \ \|
	69	+-------------------------------------------------------------------------------+
	70	\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|
	71	P P P P P G P P P P P P P P V P P P P P P P P G P P P V C G P P P E X P
	72	A A A A A N A A F F F F F F C F F G G G G G G N G G C C L N C M L X T L
	73	1 2 3 4 5 D 6 7 0 1 2 3 4 5 C 6 7 7 6 5 4 3 2 D 1 0 0 C K D 4 7 L T A L
	74	/ / / / / / / / / / / / / / / / / / / / / / / / O / / G A L V
	75	A A A A A A A A A A A A A A A R T ! T ! P R T M ! U N L C
	76	1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 T I T I T W X X O I A D C
	77	7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 C N O N O M D D C R R
	78	O 1 U 2 U O L Q T
	79	T T K 7 G
	80	1 2 P
	81	I
	82	O
	83
	84	Figure 12-1. MC68328 144-Lead Plastic Thin-Quad Flat Pack Pin Assignment
	85
	86	Source: MC68328 (DragonBall)(tm) Integrated Processor User's Manual
	87
	88	*****************************************************************************************************************/
	89
	90	#ifndef __MC68328_H_
	91	#define __MC68328_H_
	92
	93	/***************************************************************************
	94	TYPE DEFINITIONS
	95	***************************************************************************/
	96
	97	struct mc68328_interface
	98	{
	99	const char *m68k_cpu_tag;
	100
	101	devcb_write8 out_port_a_func; /* 8-bit output */
	102	devcb_write8 out_port_b_func; /* 8-bit output */
	103	devcb_write8 out_port_c_func; /* 8-bit output */
	104	devcb_write8 out_port_d_func; /* 8-bit output */
	105	devcb_write8 out_port_e_func; /* 8-bit output */
	106	devcb_write8 out_port_f_func; /* 8-bit output */
	107	devcb_write8 out_port_g_func; /* 8-bit output */
	108	devcb_write8 out_port_j_func; /* 8-bit output */
	109	devcb_write8 out_port_k_func; /* 8-bit output */
	110	devcb_write8 out_port_m_func; /* 8-bit output */
	111
	112	devcb_read8 in_port_a_func; /* 8-bit input */
	113	devcb_read8 in_port_b_func; /* 8-bit input */
	114	devcb_read8 in_port_c_func; /* 8-bit input */
	115	devcb_read8 in_port_d_func; /* 8-bit input */
	116	devcb_read8 in_port_e_func; /* 8-bit input */
	117	devcb_read8 in_port_f_func; /* 8-bit input */
	118	devcb_read8 in_port_g_func; /* 8-bit input */
	119	devcb_read8 in_port_j_func; /* 8-bit input */
	120	devcb_read8 in_port_k_func; /* 8-bit input */
	121	devcb_read8 in_port_m_func; /* 8-bit input */
	122
	123	devcb_write8 out_pwm_func; /* 1-bit output */
	124
	125	devcb_write16 out_spim_func; /* 16-bit output */
	126	devcb_read16 in_spim_func; /* 16-bit input */
	127	void (spim_xch_trigger)( device_t device ); /* SPIM exchange trigger */
	128	};
	129	#define MC68328_INTERFACE(name) const mc68328_interface (name)=
	130
	131	#define MC68328_TAG "dragonball"
	132
	133	/***************************************************************************
	134	DEVICE CONFIGURATION MACROS
	135	***************************************************************************/
	136
	137	#define MCFG_MC68328_ADD(_intrf) \
	138	MCFG_DEVICE_ADD("dragonball", MC68328, 0) \
	139	MCFG_DEVICE_CONFIG(_intrf)
	140
	141	/----------- defined in machine/mc68328.c -----------/
	142
	143	/***************************************************************************
	144	READ/WRITE HANDLERS
	145	***************************************************************************/
	146
	147	DECLARE_WRITE16_DEVICE_HANDLER( mc68328_w );
	148	DECLARE_READ16_DEVICE_HANDLER( mc68328_r );
	149
	150
	151	/***************************************************************************
	152	EXTERNAL I/O LINES
	153	***************************************************************************/
	154
	155	void mc68328_set_penirq_line(device_t *device, int state);
	156	void mc68328_set_port_d_lines(device_t *device, UINT8 state, int bit);
	157
	158	/***************************************************************************
	159	DEVICE INTERFACE
	160	***************************************************************************/
	161
	162	class mc68328_device : public device_t
	163	{
	164	public:
	165	mc68328_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	166	~mc68328_device() { global_free(m_token); }
	167
	168	// access to legacy token
	169	void *token() const { assert(m_token != NULL); return m_token; }
	170	protected:
	171	// device-level overrides
	172	virtual void device_config_complete();
	173	virtual void device_start();
	174	virtual void device_reset();
	175	private:
	176	// internal state
	177	void *m_token;
	178	};
	179
	180	extern const device_type MC68328;
	181
	182
	183	/----------- defined in video/mc68328.c -----------/
	184
	185	/***************************************************************************
	186	VIDEO INTERFACE
	187	***************************************************************************/
	188
	189	PALETTE_INIT( mc68328 );
	190	VIDEO_START( mc68328 );
	191	SCREEN_UPDATE_IND16( mc68328 );
	192
	193	#endif // __MC68328_H_

Property changes on: trunk/src/mess/includes/mc68328.h
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