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r21653 Wednesday 6th March, 2013 at 19:12:40 UTC by David Haywood
current, need to fix eeprom hookup.
[src/mame/drivers]dreambal.c

trunk/src/mame/drivers/dreambal.c
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1818#include "sound/okim6295.h"
1919#include "video/deco16ic.h"
2020#include "video/decospr.h"
21#include "machine/eeprom.h"
2122
2223class dreambal_state : public driver_device
2324{
2425public:
2526   dreambal_state(const machine_config &mconfig, device_type type, const char *tag)
26      : driver_device(mconfig, type, tag)/* ,
27      : driver_device(mconfig, type, tag),
28         m_eeprom(*this, "eeprom")
2729
30      /* ,
31
2832      m_pf1_rowscroll(*this, "pf1_rowscroll"),
2933      m_pf2_rowscroll(*this, "pf2_rowscroll"),
3034*/
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3640   required_shared_ptr<UINT16> m_pf2_rowscroll;
3741   required_shared_ptr<UINT16> m_spriteram;
3842   */
43   required_device<eeprom_device> m_eeprom;
3944
4045   /* devices */
4146   cpu_device *m_maincpu;
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4550   virtual void machine_start();
4651   virtual void machine_reset();
4752   UINT32 screen_update_dreambal(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
53
54   DECLARE_WRITE16_HANDLER( dreambal_eeprom_w )
55   {
56      if (data&0xfff8)
57      {
58         logerror("dreambal_eeprom_w unhandled data %04x %04x\n",data&0x0fff8, mem_mask);
59      }
60
61      if (mem_mask&0x00ff)
62      {
63         m_eeprom->set_clock_line(data &0x1 ? ASSERT_LINE : CLEAR_LINE);
64         m_eeprom->write_bit(data &0x2);
65         m_eeprom->set_cs_line(data&0x4 ? CLEAR_LINE : ASSERT_LINE);
66      }
67   }
4868};
4969
5070
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6787
6888
6989static ADDRESS_MAP_START( dreambal_map, AS_PROGRAM, 16, dreambal_state )
90//ADDRESS_MAP_UNMAP_HIGH
7091   AM_RANGE(0x000000, 0x07ffff) AM_ROM
7192   AM_RANGE(0x100000, 0x100fff) AM_DEVREADWRITE_LEGACY("tilegen1", deco16ic_pf1_data_r, deco16ic_pf1_data_w)
7293   AM_RANGE(0x101000, 0x101fff) AM_RAM
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7697   AM_RANGE(0x120000, 0x123fff) AM_RAM
7798   AM_RANGE(0x140000, 0x1403ff) AM_RAM_WRITE(paletteram_xxxxBBBBGGGGRRRR_word_w) AM_SHARE("paletteram")
7899   AM_RANGE(0x161000, 0x16100f) AM_DEVWRITE_LEGACY("tilegen1", deco16ic_pf_control_w)
100
101   AM_RANGE(0x160088, 0x160089) AM_READ_PORT("UNK1")
102   AM_RANGE(0x160292, 0x160293) AM_READ_PORT("UNK2")
103   AM_RANGE(0x16036C, 0x16036D) AM_READ_PORT("UNK3")
104   AM_RANGE(0x180000, 0x180001) AM_NOP // OKI?
105   
106   AM_RANGE(0x165000, 0x165001) AM_WRITE( dreambal_eeprom_w ) // EEP Write?
107
79108ADDRESS_MAP_END
80109
81110
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108137GFXDECODE_END
109138
110139static INPUT_PORTS_START( dreambal )
111   PORT_START("UNK")
140   PORT_START("UNK1")
112141   PORT_DIPNAME( 0x0001, 0x0001, "2" )
113142   PORT_DIPSETTING(      0x0001, DEF_STR( Off ) )
114143   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
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157186   PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Unknown ) )
158187   PORT_DIPSETTING(      0x8000, DEF_STR( Off ) )
159188   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
189
190   PORT_START("UNK2")
191   PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_READ_LINE_DEVICE_MEMBER("eeprom", eeprom_device, read_bit)
192   //PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_VBLANK("screen")
193   PORT_DIPNAME( 0x0002, 0x0002, DEF_STR( Unknown ) )
194   PORT_DIPSETTING(      0x0002, DEF_STR( Off ) )
195   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
196   PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) )
197   PORT_DIPSETTING(      0x0004, DEF_STR( Off ) )
198   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
199   PORT_DIPNAME( 0x0008, 0x0000, DEF_STR( Unknown ) )
200   PORT_DIPSETTING(      0x0008, DEF_STR( Off ) )
201   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
202   PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) )
203   PORT_DIPSETTING(      0x0010, DEF_STR( Off ) )
204   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
205   PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Unknown ) )
206   PORT_DIPSETTING(      0x0020, DEF_STR( Off ) )
207   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
208   PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Unknown ) )
209   PORT_DIPSETTING(      0x0040, DEF_STR( Off ) )
210   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
211   PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Unknown ) )
212   PORT_DIPSETTING(      0x0080, DEF_STR( Off ) )
213   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
214   PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Unknown ) )
215   PORT_DIPSETTING(      0x0100, DEF_STR( Off ) )
216   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
217   PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Unknown ) )
218   PORT_DIPSETTING(      0x0200, DEF_STR( Off ) )
219   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
220   PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Unknown ) )
221   PORT_DIPSETTING(      0x0400, DEF_STR( Off ) )
222   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
223   PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Unknown ) )
224   PORT_DIPSETTING(      0x0800, DEF_STR( Off ) )
225   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
226   PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unknown ) )
227   PORT_DIPSETTING(      0x1000, DEF_STR( Off ) )
228   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
229   PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unknown ) )
230   PORT_DIPSETTING(      0x2000, DEF_STR( Off ) )
231   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
232   PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) )
233   PORT_DIPSETTING(      0x4000, DEF_STR( Off ) )
234   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
235   PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Unknown ) )
236   PORT_DIPSETTING(      0x8000, DEF_STR( Off ) )
237   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
238
239   PORT_START("UNK3")
240   PORT_DIPNAME( 0x0001, 0x0001, "2" )
241   PORT_DIPSETTING(      0x0001, DEF_STR( Off ) )
242   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
243   PORT_DIPNAME( 0x0002, 0x0002, DEF_STR( Unknown ) )
244   PORT_DIPSETTING(      0x0002, DEF_STR( Off ) )
245   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
246   PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) )
247   PORT_DIPSETTING(      0x0004, DEF_STR( Off ) )
248   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
249   PORT_DIPNAME( 0x0008, 0x0000, DEF_STR( Unknown ) )
250   PORT_DIPSETTING(      0x0008, DEF_STR( Off ) )
251   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
252   PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) )
253   PORT_DIPSETTING(      0x0010, DEF_STR( Off ) )
254   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
255   PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Unknown ) )
256   PORT_DIPSETTING(      0x0020, DEF_STR( Off ) )
257   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
258   PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Unknown ) )
259   PORT_DIPSETTING(      0x0040, DEF_STR( Off ) )
260   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
261   PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Unknown ) )
262   PORT_DIPSETTING(      0x0080, DEF_STR( Off ) )
263   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
264   PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Unknown ) )
265   PORT_DIPSETTING(      0x0100, DEF_STR( Off ) )
266   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
267   PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Unknown ) )
268   PORT_DIPSETTING(      0x0200, DEF_STR( Off ) )
269   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
270   PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Unknown ) )
271   PORT_DIPSETTING(      0x0400, DEF_STR( Off ) )
272   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
273   PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Unknown ) )
274   PORT_DIPSETTING(      0x0800, DEF_STR( Off ) )
275   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
276   PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unknown ) )
277   PORT_DIPSETTING(      0x1000, DEF_STR( Off ) )
278   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
279   PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unknown ) )
280   PORT_DIPSETTING(      0x2000, DEF_STR( Off ) )
281   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
282   PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) )
283   PORT_DIPSETTING(      0x4000, DEF_STR( Off ) )
284   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
285   PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Unknown ) )
286   PORT_DIPSETTING(      0x8000, DEF_STR( Off ) )
287   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
288
289   PORT_START("UNK4")
290   PORT_DIPNAME( 0x0001, 0x0001, "2" )
291   PORT_DIPSETTING(      0x0001, DEF_STR( Off ) )
292   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
293   PORT_DIPNAME( 0x0002, 0x0002, DEF_STR( Unknown ) )
294   PORT_DIPSETTING(      0x0002, DEF_STR( Off ) )
295   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
296   PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) )
297   PORT_DIPSETTING(      0x0004, DEF_STR( Off ) )
298   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
299   PORT_DIPNAME( 0x0008, 0x0000, DEF_STR( Unknown ) )
300   PORT_DIPSETTING(      0x0008, DEF_STR( Off ) )
301   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
302   PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) )
303   PORT_DIPSETTING(      0x0010, DEF_STR( Off ) )
304   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
305   PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Unknown ) )
306   PORT_DIPSETTING(      0x0020, DEF_STR( Off ) )
307   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
308   PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Unknown ) )
309   PORT_DIPSETTING(      0x0040, DEF_STR( Off ) )
310   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
311   PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Unknown ) )
312   PORT_DIPSETTING(      0x0080, DEF_STR( Off ) )
313   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
314   PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Unknown ) )
315   PORT_DIPSETTING(      0x0100, DEF_STR( Off ) )
316   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
317   PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Unknown ) )
318   PORT_DIPSETTING(      0x0200, DEF_STR( Off ) )
319   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
320   PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Unknown ) )
321   PORT_DIPSETTING(      0x0400, DEF_STR( Off ) )
322   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
323   PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Unknown ) )
324   PORT_DIPSETTING(      0x0800, DEF_STR( Off ) )
325   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
326   PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unknown ) )
327   PORT_DIPSETTING(      0x1000, DEF_STR( Off ) )
328   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
329   PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unknown ) )
330   PORT_DIPSETTING(      0x2000, DEF_STR( Off ) )
331   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
332   PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) )
333   PORT_DIPSETTING(      0x4000, DEF_STR( Off ) )
334   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
335   PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Unknown ) )
336   PORT_DIPSETTING(      0x8000, DEF_STR( Off ) )
337   PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
160338INPUT_PORTS_END
161339
162340static int dreambal_bank_callback( const int bank )
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208386   MCFG_PALETTE_LENGTH(0x400/2)
209387   MCFG_GFXDECODE(dreambal)
210388
389   MCFG_EEPROM_93C46_ADD("eeprom")  // 93lc46b
390
211391   MCFG_DECO16IC_ADD("tilegen1", dreambal_deco16ic_tilegen1_intf)
212392
213393   /* sound hardware */
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230410   ROM_REGION( 0x80000, "oki", 0 ) /* Oki samples */
231411   ROM_LOAD( "mm_01-1.12f",    0x00000, 0x20000, CRC(4f134be7) SHA1(b83230cc62bde55be736fd604af23f927706a770) )
232412
233   ROM_REGION( 0x80000, "eeprom", 0 ) /* EEPROM */
234   ROM_LOAD( "93lc46b.8f",    0x00000, 0x80, CRC(5ba5403f) SHA1(cad63d704d81db5c45826d485c5e3a0679fba152) )
413   ROM_REGION( 0x80, "eeprom", 0 ) /* EEPROM */
414   ROM_LOAD16_WORD_SWAP( "93lc46b.8f",    0x00, 0x80, CRC(5ba5403f) SHA1(cad63d704d81db5c45826d485c5e3a0679fba152) )
235415   
236416ROM_END
237417

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