MAME SVN History

199869 Revisions

r21592 Tuesday 5th March, 2013 at 12:01:47 UTC by Fabio Priuli
srccleaned + minor fixes. nw.

[src/mess/drivers]	snes.c
[src/mess/machine]	snescart.c sns_bsx.c sns_bsx.h sns_rom.c sns_rom.h sns_rom21.c sns_rom21.h sns_sdd1.c sns_sdd1.h sns_sfx.c sns_sfx.h sns_slot.c sns_slot.h sns_spc7110.c sns_spc7110.h sns_sufami.c sns_sufami.h sns_upd.c sns_upd.h

trunk/src/mess/drivers/snes.c
r21591	r21592
73	73	{
74	74	UINT16 temp = state->m_upd96050->dataram_r(addr/2);
75	75	UINT8 res;
76
	76
77	77	if (addr & 1)
78	78	{
79	79	res = temp>>8;
r21591	r21592
82	82	{
83	83	res = temp & 0xff;
84	84	}
85
	85
86	86	return res;
87	87	}
88	88
89	89	void st010_write_ram(snes_state *state, UINT16 addr, UINT8 data)
90	90	{
91	91	UINT16 temp = state->m_upd96050->dataram_r(addr/2);
92
	92
93	93	if (addr & 1)
94	94	{
95	95	temp &= 0xff;
r21591	r21592
100	100	temp &= 0xff00;
101	101	temp \|= data;
102	102	}
103
	103
104	104	state->m_upd96050->dataram_w(addr/2, temp);
105	105	}
106	106
r21591	r21592
111	111	UINT16 address = offset & 0xffff;
112	112
113	113	// take care of add-on chip access
114		if (state->m_has_addon_chip == HAS_OBC1
	114	if (state->m_has_addon_chip == HAS_OBC1
115	115	&& (offset < 0x400000 && address >= 0x6000 && address < 0x8000))
116	116	return obc1_read(space, offset, mem_mask);
117		if (state->m_has_addon_chip == HAS_CX4
	117	if (state->m_has_addon_chip == HAS_CX4
118	118	&& (offset < 0x400000 && address >= 0x6000 && address < 0x8000))
119	119	return CX4_read(address - 0x6000);
120	120	if (state->m_has_addon_chip == HAS_RTC
r21591	r21592
127	127	if (offset == 0x600000 \|\| offset == 0x600001)
128	128	return (offset & 1) ? st010_get_sr() : st010_get_dr();
129	129	}
130		if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1
	130	if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1
131	131	&& (offset < 0x200000 && address >= 0x6000 && address < 0x8000))
132	132	return (address < 0x7000) ? dsp_get_dr() : dsp_get_sr();
133	133	if (state->m_cart[0].mode == SNES_MODE_20 && state->m_has_addon_chip == HAS_DSP1)
r21591	r21592
136	136	return (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
137	137	if (offset >= 0x600000 && offset < 0x700000 && (offset & 0x8000) == 0x0000)
138	138	return (address < 0x4000) ? dsp_get_dr() : dsp_get_sr();
139		}
	139	}
140	140	if ((state->m_has_addon_chip == HAS_DSP2 \|\| state->m_has_addon_chip == HAS_DSP3)
141	141	&& (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
142	142	return (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
143		if (state->m_has_addon_chip == HAS_DSP4
	143	if (state->m_has_addon_chip == HAS_DSP4
144	144	&& (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
145	145	return (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
146	146	if (state->m_has_addon_chip == HAS_SDD1
r21591	r21592
148	148	return sdd1_mmio_read(space, (UINT32)address);
149	149	if ((state->m_has_addon_chip == HAS_SPC7110 \|\| state->m_has_addon_chip == HAS_SPC7110_RTC)
150	150	&& offset < 0x400000)
151		{
	151	{
152	152	UINT16 limit = (state->m_has_addon_chip == HAS_SPC7110_RTC) ? 0x4842 : 0x483f;
153	153	if (address >= 0x4800 && address <= limit)
154	154	return spc7110_mmio_read(space, (UINT32)address);
r21591	r21592
162	162	return spc7110_mmio_read(space, 0x4800);
163	163	if (state->m_has_addon_chip == HAS_SUPERFX && state->m_superfx != NULL
164	164	&& offset < 0x400000)
165		{
	165	{
166	166	if (address >= 0x3000 && address < 0x3300)
167	167	return superfx_mmio_read(state->m_superfx, address);
168		if (address >= 0x6000 && address < 0x8000) // here it should be snes_ram[0xe00000+...] but there are mirroring issues
	168	if (address >= 0x6000 && address < 0x8000) // here it should be snes_ram[0xe00000+...] but there are mirroring issues
169	169	return superfx_access_ram(state->m_superfx) ? snes_ram[0xf00000 + (offset & 0x1fff)] : snes_open_bus_r(space, 0);
170	170	}
171	171	if (state->m_has_addon_chip == HAS_SUPERFX && state->m_superfx != NULL
r21591	r21592
185	185	if (state->m_has_addon_chip == HAS_SUPERFX && state->m_superfx != NULL
186	186	&& offset >= 0x600000)
187	187	return superfx_access_ram(state->m_superfx) ? snes_ram[0x800000 + offset] : snes_open_bus_r(space, 0);
188
	188
189	189	// base cart access
190	190	if (offset < 0x300000)
191	191	return snes_r_bank1(space, offset, 0xff);
r21591	r21592
197	197	return snes_r_bank4(space, offset - 0x600000, 0xff);
198	198	else
199	199	return snes_r_bank5(space, offset - 0x700000, 0xff);
200		}
	200	}
201	201
202	202	static READ8_HANDLER( snes_hi_r )
203	203	{
204	204	snes_state *state = space.machine().driver_data<snes_state>();
205	205	UINT16 address = offset & 0xffff;
206
	206
207	207	// take care of add-on chip access
208		if (state->m_has_addon_chip == HAS_OBC1
	208	if (state->m_has_addon_chip == HAS_OBC1
209	209	&& (offset < 0x400000 && address >= 0x6000 && address < 0x8000))
210	210	return obc1_read(space, offset, mem_mask);
211		if (state->m_has_addon_chip == HAS_CX4
	211	if (state->m_has_addon_chip == HAS_CX4
212	212	&& (offset < 0x400000 && address >= 0x6000 && address < 0x8000))
213	213	return CX4_read(address - 0x6000);
214	214	if (state->m_has_addon_chip == HAS_RTC
r21591	r21592
221	221	if (offset == 0x600000 \|\| offset == 0x600001)
222	222	return (offset & 1) ? st010_get_sr() : st010_get_dr();
223	223	}
224		if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1
	224	if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1
225	225	&& (offset < 0x200000 && address >= 0x6000 && address < 0x8000))
226	226	return (address < 0x7000) ? dsp_get_dr() : dsp_get_sr();
227	227	if (state->m_cart[0].mode == SNES_MODE_20 && state->m_has_addon_chip == HAS_DSP1)
r21591	r21592
234	234	if ((state->m_has_addon_chip == HAS_DSP2 \|\| state->m_has_addon_chip == HAS_DSP3)
235	235	&& (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
236	236	return (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
237		if (state->m_has_addon_chip == HAS_DSP4
	237	if (state->m_has_addon_chip == HAS_DSP4
238	238	&& (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
239	239	return (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
240	240	if (state->m_has_addon_chip == HAS_SDD1
r21591	r21592
244	244	return sdd1_read(space.machine(), offset - 0x400000);
245	245	if ((state->m_has_addon_chip == HAS_SPC7110 \|\| state->m_has_addon_chip == HAS_SPC7110_RTC)
246	246	&& offset < 0x400000)
247		{
	247	{
248	248	UINT16 limit = (state->m_has_addon_chip == HAS_SPC7110_RTC) ? 0x4842 : 0x483f;
249	249	if (address >= 0x4800 && address <= limit)
250	250	return spc7110_mmio_read(space, (UINT32)address);
r21591	r21592
253	253	if (offset >= 0x300000 && offset < 0x310000 && address >= 0x6000 && address < 0x8000)
254	254	return snes_ram[0x306000 + (address & 0x1fff)];
255	255	}
256		if ((state->m_has_addon_chip == HAS_SPC7110 \|\| state->m_has_addon_chip == HAS_SPC7110_RTC)
	256	if ((state->m_has_addon_chip == HAS_SPC7110 \|\| state->m_has_addon_chip == HAS_SPC7110_RTC)
257	257	&& offset >= 0x500000)
258	258	return spc7110_bank7_read(space, offset - 0x400000);
259	259	if (state->m_has_addon_chip == HAS_SUPERFX && state->m_superfx != NULL)
260		return space.read_byte(offset); // [80-ff] same as [00-7f]
261
	260	return space.read_byte(offset); // [80-ff] same as [00-7f]
	261
262	262	// base cart access
263	263	if (offset < 0x400000)
264	264	return snes_r_bank6(space, offset, 0xff);
265	265	else
266	266	return snes_r_bank7(space, offset - 0x400000, 0xff);
267		}
	267	}
268	268
269	269	static WRITE8_HANDLER( snes_lo_w )
270	270	{
271	271	snes_state *state = space.machine().driver_data<snes_state>();
272	272	UINT16 address = offset & 0xffff;
273
	273
274	274	// take care of add-on chip access
275		if (state->m_has_addon_chip == HAS_OBC1
	275	if (state->m_has_addon_chip == HAS_OBC1
276	276	&& (offset < 0x400000 && address >= 0x6000 && address < 0x8000))
277		{ obc1_write(space, offset, data, mem_mask); return; }
278		if (state->m_has_addon_chip == HAS_CX4
	277	{ obc1_write(space, offset, data, mem_mask); return; }
	278	if (state->m_has_addon_chip == HAS_CX4
279	279	&& (offset < 0x400000 && address >= 0x6000 && address < 0x8000))
280		{ CX4_write(space.machine(), address - 0x6000, data); return; }
	280	{ CX4_write(space.machine(), address - 0x6000, data); return; }
281	281	if (state->m_has_addon_chip == HAS_RTC
282	282	&& (offset < 0x400000 && (address == 0x2800 \|\| address == 0x2801)))
283		{ srtc_write(space.machine(), offset, data); return; }
	283	{ srtc_write(space.machine(), offset, data); return; }
284	284	if (state->m_has_addon_chip == HAS_ST010 \|\| state->m_has_addon_chip == HAS_ST011)
285	285	{
286	286	if (offset >= 0x680000 && offset < 0x700000 && address < 0x1000)
287		{ st010_write_ram(state, address, data); return; }
	287	{ st010_write_ram(state, address, data); return; }
288	288	if (offset == 0x600000)
289		{ st010_set_dr(data); return; }
	289	{ st010_set_dr(data); return; }
290	290	if (offset == 0x600001)
291		{ st010_set_sr(data); return; }
	291	{ st010_set_sr(data); return; }
292	292	}
293		if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1
	293	if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1
294	294	&& (offset < 0x200000 && address >= 0x6000 && address < 0x8000))
295		{ dsp_set_dr(data); return; }
	295	{ dsp_set_dr(data); return; }
296	296	if (state->m_cart[0].mode == SNES_MODE_20 && state->m_has_addon_chip == HAS_DSP1)
297	297	{
298	298	if (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)
299		{ dsp_set_dr(data); return; }
	299	{ dsp_set_dr(data); return; }
300	300	if (offset >= 0x600000 && offset < 0x700000 && (offset & 0x8000) == 0x0000)
301		{ dsp_set_dr(data); return; }
	301	{ dsp_set_dr(data); return; }
302	302	}
303	303	if ((state->m_has_addon_chip == HAS_DSP2 \|\| state->m_has_addon_chip == HAS_DSP3)
304	304	&& (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
305	305	{
306	306	if (address < 0xc000)
307		{ dsp_set_dr(data); return; }
	307	{ dsp_set_dr(data); return; }
308	308	else
309		{ dsp_set_sr(data); return; }
	309	{ dsp_set_sr(data); return; }
310	310	}
311		if (state->m_has_addon_chip == HAS_DSP4
	311	if (state->m_has_addon_chip == HAS_DSP4
312	312	&& (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
313	313	{
314	314	if (address < 0xc000)
315		{ dsp_set_dr(data); return; }
	315	{ dsp_set_dr(data); return; }
316	316	else
317		{ dsp_set_sr(data); return; }
	317	{ dsp_set_sr(data); return; }
318	318	}
319	319	if (state->m_has_addon_chip == HAS_SDD1 && offset < 0x400000)
320	320	{
r21591	r21592
325	325	}
326	326	}
327	327	if ((state->m_has_addon_chip == HAS_SPC7110 \|\| state->m_has_addon_chip == HAS_SPC7110_RTC) && offset < 0x400000)
328		{
	328	{
329	329	UINT16 limit = (state->m_has_addon_chip == HAS_SPC7110_RTC) ? 0x4842 : 0x483f;
330	330	if (address >= 0x4800 && address <= limit)
331		{ spc7110_mmio_write(space.machine(), (UINT32)address, data); return; }
	331	{ spc7110_mmio_write(space.machine(), (UINT32)address, data); return; }
332	332	if (offset < 0x10000 && address >= 0x6000 && address < 0x8000)
333		{ snes_ram[0x306000 + (address & 0x1fff)] = data; return; }
	333	{ snes_ram[0x306000 + (address & 0x1fff)] = data; return; }
334	334	if (offset >= 0x300000 && offset < 0x310000 && address >= 0x6000 && address < 0x8000)
335		{ snes_ram[0x306000 + (address & 0x1fff)] = data; return; }
	335	{ snes_ram[0x306000 + (address & 0x1fff)] = data; return; }
336	336	}
337	337	if (state->m_has_addon_chip == HAS_SUPERFX && state->m_superfx != NULL
338		&& offset < 0x400000)
339		{
	338	&& offset < 0x400000)
	339	{
340	340	if (address >= 0x3000 && address < 0x3300)
341		{ superfx_mmio_write(state->m_superfx, address, data); return; }
342		if (address >= 0x6000 && address < 0x8000) // here it should be snes_ram[0xe00000+...] but there are mirroring issues
343		{ snes_ram[0xf00000 + (offset & 0x1fff)] = data; return; }
	341	{ superfx_mmio_write(state->m_superfx, address, data); return; }
	342	if (address >= 0x6000 && address < 0x8000) // here it should be snes_ram[0xe00000+...] but there are mirroring issues
	343	{ snes_ram[0xf00000 + (offset & 0x1fff)] = data; return; }
344	344	}
345	345	if (state->m_has_addon_chip == HAS_SUPERFX && state->m_superfx != NULL
346	346	&& offset >= 0x600000)
347		{ snes_ram[0x800000 + offset] = data; return; }
348
	347	{ snes_ram[0x800000 + offset] = data; return; }
	348
349	349	// base cart access
350	350	if (offset < 0x300000)
351	351	snes_w_bank1(space, offset, data, 0xff);
r21591	r21592
357	357	snes_w_bank4(space, offset - 0x600000, data, 0xff);
358	358	else
359	359	snes_w_bank5(space, offset - 0x700000, data, 0xff);
360		}
	360	}
361	361
362	362	static WRITE8_HANDLER( snes_hi_w )
363	363	{
364	364	snes_state *state = space.machine().driver_data<snes_state>();
365	365	UINT16 address = offset & 0xffff;
366
	366
367	367	// take care of add-on chip access
368		if (state->m_has_addon_chip == HAS_OBC1
	368	if (state->m_has_addon_chip == HAS_OBC1
369	369	&& (offset < 0x400000 && address >= 0x6000 && address < 0x8000))
370		{ obc1_write(space, offset, data, mem_mask); return; }
371		if (state->m_has_addon_chip == HAS_CX4
	370	{ obc1_write(space, offset, data, mem_mask); return; }
	371	if (state->m_has_addon_chip == HAS_CX4
372	372	&& (offset < 0x400000 && address >= 0x6000 && address < 0x8000))
373		{ CX4_write(space.machine(), address - 0x6000, data); return; }
	373	{ CX4_write(space.machine(), address - 0x6000, data); return; }
374	374	if (state->m_has_addon_chip == HAS_RTC
375	375	&& (offset < 0x400000 && (address == 0x2800 \|\| address == 0x2801)))
376		{ srtc_write(space.machine(), offset, data); return; }
	376	{ srtc_write(space.machine(), offset, data); return; }
377	377	if (state->m_has_addon_chip == HAS_ST010 \|\| state->m_has_addon_chip == HAS_ST011)
378	378	{
379	379	if (offset >= 0x680000 && offset < 0x700000 && address < 0x1000)
380		{ st010_write_ram(state, address, data); return; }
	380	{ st010_write_ram(state, address, data); return; }
381	381	if (offset == 0x600000)
382		{ st010_set_dr(data); return; }
	382	{ st010_set_dr(data); return; }
383	383	if (offset == 0x600001)
384		{ st010_set_sr(data); return; }
	384	{ st010_set_sr(data); return; }
385	385	}
386		if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1
	386	if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1
387	387	&& (offset < 0x200000 && address >= 0x6000 && address < 0x8000))
388		{ dsp_set_dr(data); return; }
	388	{ dsp_set_dr(data); return; }
389	389	if (state->m_cart[0].mode == SNES_MODE_20 && state->m_has_addon_chip == HAS_DSP1)
390	390	{
391	391	if (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)
392		{ dsp_set_dr(data); return; }
	392	{ dsp_set_dr(data); return; }
393	393	if (offset >= 0x600000 && offset < 0x700000 && (offset & 0x8000) == 0x0000)
394		{ dsp_set_dr(data); return; }
395		}
	394	{ dsp_set_dr(data); return; }
	395	}
396	396	if ((state->m_has_addon_chip == HAS_DSP2 \|\| state->m_has_addon_chip == HAS_DSP3)
397	397	&& (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
398	398	{
399	399	if (address < 0xc000)
400		{ dsp_set_dr(data); return; }
	400	{ dsp_set_dr(data); return; }
401	401	else
402		{ dsp_set_sr(data); return; }
	402	{ dsp_set_sr(data); return; }
403	403	}
404		if (state->m_has_addon_chip == HAS_DSP4
	404	if (state->m_has_addon_chip == HAS_DSP4
405	405	&& (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
406	406	{
407	407	if (address < 0xc000)
408		{ dsp_set_dr(data); return; }
	408	{ dsp_set_dr(data); return; }
409	409	else
410		{ dsp_set_sr(data); return; }
	410	{ dsp_set_sr(data); return; }
411	411	}
412	412	if (state->m_has_addon_chip == HAS_SDD1 && offset < 0x400000)
413	413	{
r21591	r21592
418	418	}
419	419	}
420	420	if ((state->m_has_addon_chip == HAS_SPC7110 \|\| state->m_has_addon_chip == HAS_SPC7110_RTC) && offset < 0x400000)
421		{
	421	{
422	422	UINT16 limit = (state->m_has_addon_chip == HAS_SPC7110_RTC) ? 0x4842 : 0x483f;
423	423	if (address >= 0x4800 && address <= limit)
424		{ spc7110_mmio_write(space.machine(), (UINT32)address, data); return; }
	424	{ spc7110_mmio_write(space.machine(), (UINT32)address, data); return; }
425	425	if (offset < 0x10000 && address >= 0x6000 && address < 0x8000)
426		{ snes_ram[0x306000 + (address & 0x1fff)] = data; return; }
	426	{ snes_ram[0x306000 + (address & 0x1fff)] = data; return; }
427	427	if (offset >= 0x300000 && offset < 0x310000 && address >= 0x6000 && address < 0x8000)
428		{ snes_ram[0x306000 + (address & 0x1fff)] = data; return; }
	428	{ snes_ram[0x306000 + (address & 0x1fff)] = data; return; }
429	429	}
430	430	if (state->m_has_addon_chip == HAS_SUPERFX && state->m_superfx != NULL)
431		{ space.write_byte(offset, data); return; } // [80-ff] same as [00-7f]
432
	431	{ space.write_byte(offset, data); return; } // [80-ff] same as [00-7f]
	432
433	433	// base cart access
434	434	if (offset < 0x400000)
435	435	snes_w_bank6(space, offset, data, 0xff);
436	436	else
437	437	snes_w_bank7(space, offset, data - 0x400000, 0xff);
438		}
	438	}
439	439
440	440	static READ8_HANDLER( superfx_r_bank1 )
441	441	{
r21591	r21592
1100	1100
1101	1101	machine.add_notifier(MACHINE_NOTIFY_EXIT, machine_notify_delegate(FUNC(snes_machine_stop),&machine));
1102	1102	MACHINE_START_CALL(snes);
1103
	1103
1104	1104	switch (state->m_has_addon_chip)
1105	1105	{
1106	1106	case HAS_SDD1:
r21591	r21592
1133	1133
1134	1134	// see if there's a uPD7725 DSP in the machine config
1135	1135	state->m_upd7725 = machine.device<upd7725_device>("dsp");
1136
	1136
1137	1137	// if we have a DSP, halt it for the moment
1138	1138	if (state->m_upd7725)
1139	1139	machine.device("dsp")->execute().set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
1140
	1140
1141	1141	// ditto for a uPD96050 (Seta ST-010 or ST-011)
1142	1142	state->m_upd96050 = machine.device<upd96050_device>("setadsp");
1143	1143	if (state->m_upd96050)
1144	1144	machine.device("setadsp")->execute().set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
1145
	1145
1146	1146	switch (state->m_has_addon_chip)
1147	1147	{
1148	1148	case HAS_DSP1:
r21591	r21592
1158	1158	state->m_has_addon_chip = HAS_NONE; // prevent crash trying to access NULL device
1159	1159	}
1160	1160	break;
1161
	1161
1162	1162	case HAS_RTC:
1163	1163	srtc_init(machine);
1164	1164	break;
1165
	1165
1166	1166	case HAS_OBC1:
1167	1167	obc1_init(machine);
1168	1168	break;
1169
	1169
1170	1170	case HAS_ST010:
1171	1171	case HAS_ST011:
1172	1172	// cartridge uses the DSP, let 'er rip
r21591	r21592
1178	1178	state->m_has_addon_chip = HAS_NONE; // prevent crash trying to access NULL device
1179	1179	}
1180	1180	break;
1181
	1181
1182	1182	default:
1183	1183	break;
1184	1184	}
r21591	r21592
1470	1470	snsnew_state(const machine_config &mconfig, device_type type, const char *tag)
1471	1471	: snes_state(mconfig, type, tag),
1472	1472	m_slotcart(*this, "snsslot")
1473		{ }
1474
	1473	{ }
	1474
1475	1475	optional_device<sns_cart_slot_device> m_slotcart;
1476	1476	int m_type;
1477	1477	};
r21591	r21592
1489	1489	{
1490	1490	snsnew_state *state = space.machine().driver_data<snsnew_state>();
1491	1491	UINT16 address = offset & 0xffff;
1492
	1492
1493	1493	if (offset < 0x400000)
1494	1494	{
1495	1495	if (address < 0x2000)
r21591	r21592
1498	1498	return snes_r_io(space, address);
1499	1499	if (address >= 0x6000 && address < 0x8000)
1500	1500	return snes_open_bus_r(space, 0);
1501		if (address >= 0x8000)
	1501	if (address >= 0x8000)
1502	1502	return state->m_slotcart->m_cart->read_h(space, offset);
1503	1503	}
1504	1504	else if (offset < 0x700000)
r21591	r21592
1508	1508	else
1509	1509	return state->m_slotcart->m_cart->read_h(space, offset);
1510	1510	}
1511
	1511
1512	1512	// ROM & NVRAM access
1513	1513	return state->m_slotcart->m_cart->read_h(space, offset);
1514		}
	1514	}
1515	1515
1516	1516	static WRITE8_HANDLER( snes20_hi_w )
1517	1517	{
r21591	r21592
1524	1524	if (address >= 0x2000 && address < 0x6000)
1525	1525	snes_w_io(space, address, data);
1526	1526	}
1527		else if (offset >= 0x700000) // NVRAM access
	1527	else if (offset >= 0x700000) // NVRAM access
1528	1528	{
1529	1529	state->m_slotcart->m_cart->write_h(space, offset, data);
1530	1530	}
1531		}
	1531	}
1532	1532
1533	1533	static READ8_HANDLER( snes20_lo_r )
1534	1534	{
1535	1535	snsnew_state *state = space.machine().driver_data<snsnew_state>();
1536	1536	UINT16 address = offset & 0xffff;
1537
	1537
1538	1538	if (offset < 0x400000)
1539	1539	{
1540	1540	if (address < 0x2000)
r21591	r21592
1543	1543	return snes_r_io(space, address);
1544	1544	if (address >= 0x6000 && address < 0x8000)
1545	1545	return snes_open_bus_r(space, 0);
1546		if (address >= 0x8000)
	1546	if (address >= 0x8000)
1547	1547	return state->m_slotcart->m_cart->read_l(space, offset);
1548	1548	}
1549	1549	else if (offset < 0x700000)
r21591	r21592
1553	1553	else
1554	1554	return state->m_slotcart->m_cart->read_l(space, offset);
1555	1555	}
1556
	1556
1557	1557	// ROM & NVRAM access
1558	1558	return state->m_slotcart->m_cart->read_l(space, offset);
1559		}
	1559	}
1560	1560
1561	1561	static WRITE8_HANDLER( snes20_lo_w )
1562	1562	{
1563	1563	snes20_hi_w(space, offset, data, 0xff);
1564		}
	1564	}
1565	1565
1566	1566
1567	1567	// HiROM
r21591	r21592
1570	1570	{
1571	1571	snsnew_state *state = space.machine().driver_data<snsnew_state>();
1572	1572	UINT16 address = offset & 0xffff;
1573
	1573
1574	1574	if (offset < 0x400000)
1575	1575	{
1576	1576	if (address < 0x2000)
r21591	r21592
1590	1590	if (address >= 0x8000)
1591	1591	return state->m_slotcart->m_cart->read_l(space, offset);
1592	1592	}
1593
	1593
1594	1594	// ROM & NVRAM access
1595	1595	return state->m_slotcart->m_cart->read_l(space, offset);
1596		}
	1596	}
1597	1597
1598	1598	static WRITE8_HANDLER( snes21_lo_w )
1599	1599	{
r21591	r21592
1615	1615	}
1616	1616	}
1617	1617	}
1618		else if (offset >= 0x700000) // NVRAM access
	1618	else if (offset >= 0x700000) // NVRAM access
1619	1619	state->m_slotcart->m_cart->write_l(space, offset, data);
1620		}
	1620	}
1621	1621
1622	1622	static READ8_HANDLER( snes21_hi_r )
1623	1623	{
1624	1624	snsnew_state *state = space.machine().driver_data<snsnew_state>();
1625	1625	UINT16 address = offset & 0xffff;
1626
	1626
1627	1627	if (offset < 0x400000)
1628	1628	{
1629	1629	if (address < 0x2000)
r21591	r21592
1643	1643	if (address >= 0x8000)
1644	1644	return state->m_slotcart->m_cart->read_h(space, offset);
1645	1645	}
1646
	1646
1647	1647	// ROM & NVRAM access
1648	1648	return state->m_slotcart->m_cart->read_h(space, offset);
1649		}
	1649	}
1650	1650
1651	1651	static WRITE8_HANDLER( snes21_hi_w )
1652	1652	{
r21591	r21592
1668	1668	}
1669	1669	}
1670	1670	}
1671		else if (offset >= 0x700000) // NVRAM access
	1671	else if (offset >= 0x700000) // NVRAM access
1672	1672	state->m_slotcart->m_cart->write_h(space, offset, data);
1673		}
	1673	}
1674	1674
1675	1675	// SuperFX / GSU
1676	1676
r21591	r21592
1678	1678	{
1679	1679	snsnew_state *state = space.machine().driver_data<snsnew_state>();
1680	1680	UINT16 address = offset & 0xffff;
1681
	1681
1682	1682	if (offset < 0x400000)
1683	1683	{
1684	1684	if (address < 0x2000)
r21591	r21592
1692	1692	}
1693	1693	if (address >= 0x6000 && address < 0x8000)
1694	1694	{
1695		return state->m_slotcart->m_cart->read_h(space, offset); //RAM
	1695	return state->m_slotcart->m_cart->read_h(space, offset); //RAM
1696	1696	}
1697	1697	if (address >= 0x8000)
1698		return state->m_slotcart->m_cart->read_h(space, offset); //ROM
	1698	return state->m_slotcart->m_cart->read_h(space, offset); //ROM
1699	1699	}
1700	1700	else if (offset < 0x600000)
1701		return state->m_slotcart->m_cart->read_h(space, offset); //ROM
1702
1703		return state->m_slotcart->m_cart->read_h(space, offset); //RAM
1704		}
	1701	return state->m_slotcart->m_cart->read_h(space, offset); //ROM
1705	1702
	1703	return state->m_slotcart->m_cart->read_h(space, offset); //RAM
	1704	}
	1705
1706	1706	static READ8_HANDLER( snesfx_lo_r )
1707	1707	{
1708	1708	snsnew_state *state = space.machine().driver_data<snsnew_state>();
1709	1709	UINT16 address = offset & 0xffff;
1710
	1710
1711	1711	if (offset < 0x400000)
1712	1712	{
1713	1713	if (address < 0x2000)
r21591	r21592
1721	1721	}
1722	1722	if (address >= 0x6000 && address < 0x8000)
1723	1723	{
1724		return state->m_slotcart->m_cart->read_l(space, offset); //RAM
	1724	return state->m_slotcart->m_cart->read_l(space, offset); //RAM
1725	1725	}
1726	1726	if (address >= 0x8000)
1727		return state->m_slotcart->m_cart->read_l(space, offset); //ROM
	1727	return state->m_slotcart->m_cart->read_l(space, offset); //ROM
1728	1728	}
1729	1729	else if (offset < 0x600000)
1730		return state->m_slotcart->m_cart->read_l(space, offset); //ROM
1731
1732		return state->m_slotcart->m_cart->read_l(space, offset); //RAM
1733		}
	1730	return state->m_slotcart->m_cart->read_l(space, offset); //ROM
1734	1731
	1732	return state->m_slotcart->m_cart->read_l(space, offset); //RAM
	1733	}
	1734
1735	1735	static WRITE8_HANDLER( snesfx_hi_w )
1736	1736	{
1737	1737	snsnew_state *state = space.machine().driver_data<snsnew_state>();
r21591	r21592
1752	1752	}
1753	1753	else
1754	1754	state->m_slotcart->m_cart->write_h(space, offset, data);
1755		}
	1755	}
1756	1756
1757	1757	static WRITE8_HANDLER( snesfx_lo_w )
1758	1758	{
r21591	r21592
1774	1774	}
1775	1775	else
1776	1776	state->m_slotcart->m_cart->write_l(space, offset, data);
1777		}
	1777	}
1778	1778
1779	1779	// SPC-7110
1780	1780
r21591	r21592
1782	1782	{
1783	1783	snsnew_state *state = space.machine().driver_data<snsnew_state>();
1784	1784	UINT16 address = offset & 0xffff;
1785
	1785
1786	1786	if (offset < 0x400000)
1787	1787	{
1788	1788	if (address < 0x2000)
r21591	r21592
1792	1792	UINT16 limit = (state->m_slotcart->get_type() == SNES_SPC7110_RTC) ? 0x4843 : 0x4840;
1793	1793	if (address >= 0x4800 && address < limit)
1794	1794	return state->m_slotcart->m_cart->chip_read(space, address);
1795
	1795
1796	1796	return snes_r_io(space, address);
1797	1797	}
1798	1798	if (address >= 0x6000 && address < 0x8000)
r21591	r21592
1806	1806	return state->m_slotcart->m_cart->read_h(space, offset);
1807	1807	}
1808	1808	return state->m_slotcart->m_cart->read_h(space, offset);
1809		}
	1809	}
1810	1810
1811	1811	static READ8_HANDLER( snespc7110_lo_r )
1812	1812	{
1813	1813	snsnew_state *state = space.machine().driver_data<snsnew_state>();
1814	1814	UINT16 address = offset & 0xffff;
1815
	1815
1816	1816	if (offset < 0x400000)
1817	1817	{
1818	1818	if (address < 0x2000)
r21591	r21592
1822	1822	UINT16 limit = (state->m_slotcart->get_type() == SNES_SPC7110_RTC) ? 0x4843 : 0x4840;
1823	1823	if (address >= 0x4800 && address < limit)
1824	1824	return state->m_slotcart->m_cart->chip_read(space, address);
1825
	1825
1826	1826	return snes_r_io(space, address);
1827	1827	}
1828	1828	if (address >= 0x6000 && address < 0x8000)
r21591	r21592
1839	1839	return state->m_slotcart->m_cart->chip_read(space, 0x4800);
1840	1840
1841	1841	return snes_open_bus_r(space, 0);
1842		}
	1842	}
1843	1843
1844	1844	static WRITE8_HANDLER( snespc7110_hi_w )
1845	1845	{
r21591	r21592
1867	1867	state->m_slotcart->m_cart->write_l(space, offset, data);
1868	1868	}
1869	1869	}
1870		}
	1870	}
1871	1871
1872	1872	static WRITE8_HANDLER( snespc7110_lo_w )
1873	1873	{
r21591	r21592
1895	1895	state->m_slotcart->m_cart->write_l(space, offset, data);
1896	1896	}
1897	1897	}
1898		}
	1898	}
1899	1899
1900	1900
1901	1901	// S-DD1
r21591	r21592
1904	1904	{
1905	1905	snsnew_state *state = space.machine().driver_data<snsnew_state>();
1906	1906	UINT16 address = offset & 0xffff;
1907
	1907
1908	1908	if (offset < 0x400000)
1909	1909	{
1910	1910	if (address < 0x2000)
r21591	r21592
1913	1913	{
1914	1914	if (address >= 0x4800 && address < 0x4808)
1915	1915	return state->m_slotcart->m_cart->chip_read(space, address);
1916
	1916
1917	1917	return snes_r_io(space, address);
1918	1918	}
1919	1919	if (address >= 0x6000 && address < 0x8000)
r21591	r21592
1921	1921	if (address >= 0x8000)
1922	1922	return state->m_slotcart->m_cart->read_l(space, offset);
1923	1923	}
1924
	1924
1925	1925	// ROM & NVRAM access
1926	1926	return state->m_slotcart->m_cart->read_l(space, offset);
1927		}
	1927	}
1928	1928
1929	1929	static WRITE8_HANDLER( snesdd1_lo_w )
1930	1930	{
r21591	r21592
1951	1951	}
1952	1952	if (offset >= 0x700000 && address < 0x8000 && state->m_slotcart->m_cart->get_nvram_size())
1953	1953	return state->m_slotcart->m_cart->write_l(space, offset, data);
1954		}
	1954	}
1955	1955
1956	1956	static READ8_HANDLER( snesdd1_hi_r )
1957	1957	{
1958	1958	snsnew_state *state = space.machine().driver_data<snsnew_state>();
1959
	1959
1960	1960	if (offset >= 0x400000)
1961	1961	return state->m_slotcart->m_cart->read_h(space, offset);
1962		else
	1962	else
1963	1963	return snesdd1_lo_r(space, offset, 0xff);
1964		}
	1964	}
1965	1965
1966	1966	static WRITE8_HANDLER( snesdd1_hi_w )
1967	1967	{
1968	1968	snesdd1_lo_w(space, offset, data, 0xff);
1969		}
	1969	}
1970	1970
1971	1971
1972	1972	// BS-X
r21591	r21592
1975	1975	{
1976	1976	snsnew_state *state = space.machine().driver_data<snsnew_state>();
1977	1977	UINT16 address = offset & 0xffff;
1978
	1978
1979	1979	if (offset < 0x400000)
1980	1980	{
1981	1981	if (address < 0x2000)
r21591	r21592
1990	1990	}
1991	1991	if (address >= 0x6000 && address < 0x8000)
1992	1992	{
1993		if (offset >= 0x200000)
	1993	if (offset >= 0x200000)
1994	1994	return state->m_slotcart->m_cart->read_l(space, offset);
1995	1995	else
1996	1996	return snes_open_bus_r(space, 0);
1997	1997	}
1998		if (address >= 0x8000)
	1998	if (address >= 0x8000)
1999	1999	return state->m_slotcart->m_cart->read_l(space, offset);
2000	2000	}
2001	2001	return state->m_slotcart->m_cart->read_l(space, offset);
2002		}
	2002	}
2003	2003
2004	2004	static WRITE8_HANDLER( snesbsx_hi_w )
2005	2005	{
r21591	r21592
2025	2025	}
2026	2026	if (address >= 0x6000 && address < 0x8000)
2027	2027	{
2028		if (offset >= 0x200000)
	2028	if (offset >= 0x200000)
2029	2029	return state->m_slotcart->m_cart->write_l(space, offset, data);
2030	2030	}
2031		if (address >= 0x8000)
	2031	if (address >= 0x8000)
2032	2032	return state->m_slotcart->m_cart->write_l(space, offset, data);
2033	2033	}
2034	2034	return state->m_slotcart->m_cart->write_l(space, offset, data);
2035		}
	2035	}
2036	2036
2037	2037	static READ8_HANDLER( snesbsx_lo_r )
2038	2038	{
2039	2039	return snesbsx_hi_r(space, offset, 0xff);
2040		}
	2040	}
2041	2041
2042	2042	static WRITE8_HANDLER( snesbsx_lo_w )
2043	2043	{
2044	2044	snesbsx_hi_w(space, offset, data, 0xff);
2045		}
	2045	}
2046	2046
2047	2047
2048	2048	static READ8_HANDLER( snesnew_lo_r )
r21591	r21592
2050	2050	snsnew_state *state = space.machine().driver_data<snsnew_state>();
2051	2051
2052	2052	// take care of add-on IO
2053		if (state->m_slotcart->get_type() == SNES_DSP
	2053	if (state->m_slotcart->get_type() == SNES_DSP
2054	2054	&& (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
2055	2055	return state->m_slotcart->m_cart->chip_read(space, offset & 0x7fff);
2056		else if (state->m_slotcart->get_type() == SNES_DSP_MODE21
2057		&& (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	2056	else if (state->m_slotcart->get_type() == SNES_DSP_MODE21
	2057	&& (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
2058	2058	return state->m_slotcart->m_cart->chip_read(space, offset & 0x1fff);
2059		else if (state->m_slotcart->get_type() == SNES_DSP4
2060		&& (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
	2059	else if (state->m_slotcart->get_type() == SNES_DSP4
	2060	&& (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
2061	2061	return state->m_slotcart->m_cart->chip_read(space, offset & 0x7fff);
2062		else if (state->m_slotcart->get_type() == SNES_OBC1
2063		&& (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	2062	else if (state->m_slotcart->get_type() == SNES_OBC1
	2063	&& (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
2064	2064	return state->m_slotcart->m_cart->chip_read(space, offset);
2065		else if ((state->m_slotcart->get_type() == SNES_ST010 \|\| state->m_slotcart->get_type() == SNES_ST011)
2066		&& (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000))
	2065	else if ((state->m_slotcart->get_type() == SNES_ST010 \|\| state->m_slotcart->get_type() == SNES_ST011)
	2066	&& (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000))
2067	2067	return state->m_slotcart->m_cart->chip_read(space, offset);
2068	2068	else if (state->m_slotcart->get_type() == SNES_SRTC
2069		&& (offset < 0x400000 && (offset & 0xffff) == 0x2800))
	2069	&& (offset < 0x400000 && (offset & 0xffff) == 0x2800))
2070	2070	return state->m_slotcart->m_cart->chip_read(space, offset & 0xffff);
2071	2071	else
2072	2072	{
r21591	r21592
2084	2084	case SNES_POKEMON:
2085	2085	case SNES_BANANA:
2086	2086	return snes20_lo_r(space, offset, 0xff);
2087
	2087
2088	2088	case SNES_MODE21:
2089	2089	case SNES_DSP_MODE21:
2090	2090	case SNES_SRTC:
2091	2091	case SNES_BSXHI:
2092	2092	return snes21_lo_r(space, offset, 0xff);
2093
	2093
2094	2094	case SNES_SFX:
2095	2095	return snesfx_lo_r(space, offset, 0xff);
2096
	2096
2097	2097	case SNES_SPC7110:
2098	2098	case SNES_SPC7110_RTC:
2099	2099	return snespc7110_lo_r(space, offset, 0xff);
2100
	2100
2101	2101	case SNES_SDD1:
2102	2102	return snesdd1_lo_r(space, offset, 0xff);
2103
	2103
2104	2104	case SNES_BSX:
2105	2105	return snesbsx_lo_r(space, offset, 0xff);
2106	2106	}
2107	2107	}
2108	2108	return snes_open_bus_r(space, 0);
2109		}
	2109	}
2110	2110
2111	2111	static READ8_HANDLER( snesnew_hi_r )
2112	2112	{
2113	2113	snsnew_state *state = space.machine().driver_data<snsnew_state>();
2114
	2114
2115	2115	// take care of add-on IO
2116	2116	if (state->m_slotcart->get_type() == SNES_DSP
2117	2117	&& (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
2118	2118	return state->m_slotcart->m_cart->chip_read(space, offset & 0x7fff);
2119		else if (state->m_slotcart->get_type() == SNES_DSP_MODE21
2120		&& (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	2119	else if (state->m_slotcart->get_type() == SNES_DSP_MODE21
	2120	&& (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
2121	2121	return state->m_slotcart->m_cart->chip_read(space, offset & 0x1fff);
2122		else if (state->m_slotcart->get_type() == SNES_DSP4
2123		&& (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
	2122	else if (state->m_slotcart->get_type() == SNES_DSP4
	2123	&& (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
2124	2124	return state->m_slotcart->m_cart->chip_read(space, offset & 0x7fff);
2125		else if (state->m_slotcart->get_type() == SNES_OBC1
2126		&& (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	2125	else if (state->m_slotcart->get_type() == SNES_OBC1
	2126	&& (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
2127	2127	return state->m_slotcart->m_cart->chip_read(space, offset);
2128		else if ((state->m_slotcart->get_type() == SNES_ST010 \|\| state->m_slotcart->get_type() == SNES_ST011)
2129		&& (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000))
	2128	else if ((state->m_slotcart->get_type() == SNES_ST010 \|\| state->m_slotcart->get_type() == SNES_ST011)
	2129	&& (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000))
2130	2130	return state->m_slotcart->m_cart->chip_read(space, offset);
2131		else if (state->m_slotcart->get_type() == SNES_SRTC
2132		&& (offset < 0x400000 && (offset & 0xffff) == 0x2800))
	2131	else if ((state->m_slotcart->get_type() == SNES_ST010 \|\| state->m_slotcart->get_type() == SNES_ST011)
	2132	&& (offset == 0x600000 \|\| offset == 0x600001))
	2133	return state->m_slotcart->m_cart->chip_read(space, offset);
	2134	else if (state->m_slotcart->get_type() == SNES_SRTC
	2135	&& (offset < 0x400000 && (offset & 0xffff) == 0x2800))
2133	2136	return state->m_slotcart->m_cart->chip_read(space, offset & 0xffff);
2134	2137	else if ((state->m_slotcart->get_type() == SNES_POKEMON \|\| state->m_slotcart->get_type() == SNES_BANANA)
2135		&& (offset & 0x70000) == 0x0000)
	2138	&& (offset & 0x70000) == 0x0000)
2136	2139	{
2137		// printf("hi read %x\n", offset);
	2140	// printf("hi read %x\n", offset);
2138	2141	return state->m_slotcart->m_cart->chip_read(space, offset);
2139	2142	}
2140	2143	else
r21591	r21592
2153	2156	case SNES_POKEMON:
2154	2157	case SNES_BANANA:
2155	2158	return snes20_hi_r(space, offset, 0xff);
2156
	2159
2157	2160	case SNES_MODE21:
2158	2161	case SNES_DSP_MODE21:
2159	2162	case SNES_SRTC:
2160	2163	case SNES_BSXHI:
2161	2164	return snes21_hi_r(space, offset, 0xff);
2162
	2165
2163	2166	case SNES_SFX:
2164	2167	return snesfx_hi_r(space, offset, 0xff);
2165
	2168
2166	2169	case SNES_SPC7110:
2167	2170	case SNES_SPC7110_RTC:
2168	2171	return snespc7110_hi_r(space, offset, 0xff);
2169
	2172
2170	2173	case SNES_SDD1:
2171	2174	return snesdd1_hi_r(space, offset, 0xff);
2172
	2175
2173	2176	case SNES_BSX:
2174	2177	return snesbsx_hi_r(space, offset, 0xff);
2175	2178	}
2176	2179	}
2177	2180	return snes_open_bus_r(space, 0);
2178		}
	2181	}
2179	2182
2180	2183	static WRITE8_HANDLER( snesnew_lo_w )
2181	2184	{
2182	2185	snsnew_state *state = space.machine().driver_data<snsnew_state>();
2183
	2186
2184	2187	// take care of add-on IO
2185	2188	if (state->m_slotcart->get_type() == SNES_DSP
2186	2189	&& (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
2187	2190	state->m_slotcart->m_cart->chip_write(space, offset & 0x7fff, data);
2188		else if (state->m_slotcart->get_type() == SNES_DSP_MODE21
2189		&& (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	2191	else if (state->m_slotcart->get_type() == SNES_DSP_MODE21
	2192	&& (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
2190	2193	state->m_slotcart->m_cart->chip_write(space, offset & 0x1fff, data);
2191		else if (state->m_slotcart->get_type() == SNES_DSP4
2192		&& (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
	2194	else if (state->m_slotcart->get_type() == SNES_DSP4
	2195	&& (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
2193	2196	state->m_slotcart->m_cart->chip_write(space, offset & 0x7fff, data);
2194		else if (state->m_slotcart->get_type() == SNES_OBC1
2195		&& (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	2197	else if (state->m_slotcart->get_type() == SNES_OBC1
	2198	&& (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
2196	2199	state->m_slotcart->m_cart->chip_write(space, offset, data);
2197		else if ((state->m_slotcart->get_type() == SNES_ST010 \|\| state->m_slotcart->get_type() == SNES_ST011)
2198		&& (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000))
	2200	else if ((state->m_slotcart->get_type() == SNES_ST010 \|\| state->m_slotcart->get_type() == SNES_ST011)
	2201	&& (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000))
2199	2202	state->m_slotcart->m_cart->chip_write(space, offset, data);
	2203	else if ((state->m_slotcart->get_type() == SNES_ST010 \|\| state->m_slotcart->get_type() == SNES_ST011)
	2204	&& (offset == 0x600000 \|\| offset == 0x600001))
	2205	state->m_slotcart->m_cart->chip_write(space, offset, data);
2200	2206	else if (state->m_slotcart->get_type() == SNES_SRTC
2201		&& (offset < 0x400000 && (offset & 0xffff) == 0x2801))
	2207	&& (offset < 0x400000 && (offset & 0xffff) == 0x2801))
2202	2208	state->m_slotcart->m_cart->chip_write(space, offset & 0xffff, data);
2203	2209	else if (state->m_slotcart->get_type() == SNES_BANANA
2204		&& (offset & 0x78000) == 0x8000)
2205		{
2206		// printf("lo write %x\n", offset);
	2210	&& (offset & 0x78000) == 0x8000)
	2211	{
	2212	// printf("lo write %x\n", offset);
2207	2213	state->m_slotcart->m_cart->chip_write(space, offset, data);
2208	2214	}
2209	2215	else
r21591	r21592
2223	2229	case SNES_BANANA:
2224	2230	snes20_lo_w(space, offset, data, 0xff);
2225	2231	break;
2226
	2232
2227	2233	case SNES_MODE21:
2228	2234	case SNES_DSP_MODE21:
2229	2235	case SNES_SRTC:
2230	2236	case SNES_BSXHI:
2231	2237	snes21_lo_w(space, offset, data, 0xff);
2232	2238	break;
2233
	2239
2234	2240	case SNES_SFX:
2235	2241	snesfx_lo_w(space, offset, data, 0xff);
2236	2242	break;
2237
	2243
2238	2244	case SNES_SPC7110:
2239	2245	case SNES_SPC7110_RTC:
2240	2246	snespc7110_lo_w(space, offset, data, 0xff);
2241	2247	break;
2242
	2248
2243	2249	case SNES_SDD1:
2244	2250	snesdd1_lo_w(space, offset, data, 0xff);
2245	2251	break;
2246
	2252
2247	2253	case SNES_BSX:
2248	2254	snesbsx_lo_w(space, offset, data, 0xff);
2249	2255	break;
2250	2256	}
2251	2257	}
2252		}
	2258	}
2253	2259
2254	2260	static WRITE8_HANDLER( snesnew_hi_w )
2255	2261	{
2256	2262	snsnew_state *state = space.machine().driver_data<snsnew_state>();
2257
	2263
2258	2264	// take care of add-on IO
2259	2265	if (state->m_slotcart->get_type() == SNES_DSP
2260	2266	&& (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
2261	2267	state->m_slotcart->m_cart->chip_write(space, offset & 0x7fff, data);
2262		else if (state->m_slotcart->get_type() == SNES_DSP_MODE21
2263		&& (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	2268	else if (state->m_slotcart->get_type() == SNES_DSP_MODE21
	2269	&& (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
2264	2270	state->m_slotcart->m_cart->chip_write(space, offset & 0x1fff, data);
2265		else if (state->m_slotcart->get_type() == SNES_DSP4
2266		&& (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
	2271	else if (state->m_slotcart->get_type() == SNES_DSP4
	2272	&& (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
2267	2273	state->m_slotcart->m_cart->chip_write(space, offset & 0x7fff, data);
2268		else if (state->m_slotcart->get_type() == SNES_OBC1
2269		&& (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	2274	else if (state->m_slotcart->get_type() == SNES_OBC1
	2275	&& (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
2270	2276	return state->m_slotcart->m_cart->chip_write(space, offset, data);
2271		else if ((state->m_slotcart->get_type() == SNES_ST010 \|\| state->m_slotcart->get_type() == SNES_ST011)
2272		&& (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000))
	2277	else if ((state->m_slotcart->get_type() == SNES_ST010 \|\| state->m_slotcart->get_type() == SNES_ST011)
	2278	&& (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000))
2273	2279	state->m_slotcart->m_cart->chip_write(space, offset, data);
	2280	else if ((state->m_slotcart->get_type() == SNES_ST010 \|\| state->m_slotcart->get_type() == SNES_ST011)
	2281	&& (offset == 0x600000 \|\| offset == 0x600001))
	2282	state->m_slotcart->m_cart->chip_write(space, offset, data);
2274	2283	else if (state->m_slotcart->get_type() == SNES_SRTC
2275		&& (offset < 0x400000 && (offset & 0xffff) == 0x2801))
	2284	&& (offset < 0x400000 && (offset & 0xffff) == 0x2801))
2276	2285	state->m_slotcart->m_cart->chip_write(space, offset & 0xffff, data);
2277	2286	else if ((state->m_slotcart->get_type() == SNES_POKEMON)
2278		&& (offset & 0x70000) == 0x0000)
2279		{
2280		// printf("hi write %x\n", offset);
	2287	&& (offset & 0x70000) == 0x0000)
	2288	{
	2289	// printf("hi write %x\n", offset);
2281	2290	state->m_slotcart->m_cart->chip_write(space, offset, data);
2282	2291	}
2283	2292	else
r21591	r21592
2297	2306	case SNES_BANANA:
2298	2307	snes20_hi_w(space, offset, data, 0xff);
2299	2308	break;
2300
	2309
2301	2310	case SNES_MODE21:
2302	2311	case SNES_DSP_MODE21:
2303	2312	case SNES_SRTC:
2304	2313	case SNES_BSXHI:
2305	2314	snes21_hi_w(space, offset, data, 0xff);
2306	2315	break;
2307
	2316
2308	2317	case SNES_SFX:
2309	2318	snesfx_hi_w(space, offset, data, 0xff);
2310	2319	break;
2311
	2320
2312	2321	case SNES_SPC7110:
2313	2322	case SNES_SPC7110_RTC:
2314	2323	snespc7110_hi_w(space, offset, data, 0xff);
2315	2324	break;
2316
	2325
2317	2326	case SNES_SDD1:
2318	2327	snesdd1_hi_w(space, offset, data, 0xff);
2319	2328	break;
2320
	2329
2321	2330	case SNES_BSX:
2322	2331	snesbsx_hi_w(space, offset, data, 0xff);
2323	2332	break;
2324	2333	}
2325	2334	}
2326		}
	2335	}
2327	2336
2328	2337
2329	2338	static ADDRESS_MAP_START( snesnew_map, AS_PROGRAM, 8, snsnew_state )
r21591	r21592
2334	2343
2335	2344	static SLOT_INTERFACE_START(snes_cart)
2336	2345	SLOT_INTERFACE_INTERNAL("lorom", SNS_LOROM)
2337		SLOT_INTERFACE_INTERNAL("lorom_bsx", SNS_LOROM_BSX) // LoROM + BS-X slot - unsupported
2338		SLOT_INTERFACE_INTERNAL("lorom_cx4", SNS_LOROM) // Cart + CX4 - unsupported
	2346	SLOT_INTERFACE_INTERNAL("lorom_bsx", SNS_LOROM_BSX) // LoROM + BS-X slot - unsupported
	2347	SLOT_INTERFACE_INTERNAL("lorom_cx4", SNS_LOROM) // Cart + CX4 - unsupported
2339	2348	SLOT_INTERFACE_INTERNAL("lorom_dsp", SNS_LOROM_NECDSP)
2340	2349	SLOT_INTERFACE_INTERNAL("lorom_dsp4", SNS_LOROM_NECDSP)
2341	2350	SLOT_INTERFACE_INTERNAL("lorom_obc1", SNS_LOROM_OBC1)
2342		SLOT_INTERFACE_INTERNAL("lorom_sa1", SNS_LOROM) // Cart + SA1 - unsupported
	2351	SLOT_INTERFACE_INTERNAL("lorom_sa1", SNS_LOROM) // Cart + SA1 - unsupported
2343	2352	SLOT_INTERFACE_INTERNAL("lorom_sdd1", SNS_LOROM_SDD1)
2344	2353	SLOT_INTERFACE_INTERNAL("lorom_sfx", SNS_LOROM_SUPERFX)
2345		SLOT_INTERFACE_INTERNAL("lorom_sgb", SNS_LOROM) // SuperGB base cart - unsupported
	2354	SLOT_INTERFACE_INTERNAL("lorom_sgb", SNS_LOROM) // SuperGB base cart - unsupported
2346	2355	SLOT_INTERFACE_INTERNAL("lorom_st010", SNS_LOROM_SETA10)
2347	2356	SLOT_INTERFACE_INTERNAL("lorom_st011", SNS_LOROM_SETA11)
2348		SLOT_INTERFACE_INTERNAL("lorom_st018", SNS_LOROM) // Cart + ST018 - unsupported
2349		SLOT_INTERFACE_INTERNAL("lorom_sufami", SNS_LOROM_SUFAMI) // Sufami Turbo base cart
	2357	SLOT_INTERFACE_INTERNAL("lorom_st018", SNS_LOROM) // Cart + ST018 - unsupported
	2358	SLOT_INTERFACE_INTERNAL("lorom_sufami", SNS_LOROM_SUFAMI) // Sufami Turbo base cart
2350	2359	SLOT_INTERFACE_INTERNAL("hirom", SNS_HIROM)
2351		SLOT_INTERFACE_INTERNAL("hirom_bsx", SNS_HIROM_BSX) // HiROM + BS-X slot - unsupported
	2360	SLOT_INTERFACE_INTERNAL("hirom_bsx", SNS_HIROM_BSX) // HiROM + BS-X slot - unsupported
2352	2361	SLOT_INTERFACE_INTERNAL("hirom_dsp", SNS_HIROM_NECDSP)
2353	2362	SLOT_INTERFACE_INTERNAL("hirom_spc7110", SNS_HIROM_SPC7110)
2354	2363	SLOT_INTERFACE_INTERNAL("hirom_spcrtc", SNS_HIROM_SPC7110_RTC)
2355	2364	SLOT_INTERFACE_INTERNAL("hirom_srtc", SNS_HIROM_SRTC)
2356		SLOT_INTERFACE_INTERNAL("bsxrom", SNS_ROM_BSX) // BS-X base cart - partial support only
	2365	SLOT_INTERFACE_INTERNAL("bsxrom", SNS_ROM_BSX) // BS-X base cart - partial support only
2357	2366	// pirate carts
2358	2367	SLOT_INTERFACE_INTERNAL("lorom_poke", SNS_LOROM_POKEMON)
2359	2368	SLOT_INTERFACE_END
r21591	r21592
2365	2374
2366	2375	state->m_type = state->m_slotcart->get_type();
2367	2376
2368		MACHINE_START_CALL(snes);
	2377	MACHINE_START_CALL(snes_mess);
2369	2378
2370		// ~~FIXME: why~~ in~~stalling~~ ~~handle~~r~~s here d~~o~~es not wo~~r~~k? it would allow to cl~~e~~an up handler~~s ~~above~~...
	2379	// in progress...
2371	2380	switch (state->m_type)
2372	2381	{
2373	2382	case SNES_MODE21:
2374		case SNES_MODE25:
2375		case SNES_DSP_MODE21:
2376	2383	machine.device("maincpu")->memory().space(AS_PROGRAM).install_legacy_readwrite_handler(0x000000, 0x7dffff, FUNC(snes21_lo_r), FUNC(snes21_lo_w));
2377	2384	machine.device("maincpu")->memory().space(AS_PROGRAM).install_legacy_readwrite_handler(0x800000, 0xffffff, FUNC(snes21_hi_r), FUNC(snes21_hi_w));
2378	2385	set_5a22_map(*state->m_maincpu);
2379	2386	break;
	2387	case SNES_DSP_MODE21:
	2388	// machine.device("maincpu")->memory().space(AS_PROGRAM).install_legacy_readwrite_handler(0x000000, 0x7dffff, FUNC(snes21_lo_r), FUNC(snes21_lo_w));
	2389	// machine.device("maincpu")->memory().space(AS_PROGRAM).install_legacy_readwrite_handler(0x800000, 0xffffff, FUNC(snes21_hi_r), FUNC(snes21_hi_w));
	2390	// machine.device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0x006000, 0x007fff, 0x1f0000, 0, read8_delegate(FUNC(device_sns_cart_interface::chip_read),state->m_slotcart->m_cart));
	2391	// machine.device("maincpu")->memory().space(AS_PROGRAM).install_write_handler(0x006000, 0x007fff, 0x1f0000, 0, write8_delegate(FUNC(device_sns_cart_interface::chip_write),state->m_slotcart->m_cart));
	2392	// set_5a22_map(*state->m_maincpu);
	2393	break;
	2394	case SNES_SRTC:
	2395	// machine.device("maincpu")->memory().space(AS_PROGRAM).install_legacy_readwrite_handler(0x000000, 0x7dffff, FUNC(snes21_lo_r), FUNC(snes21_lo_w));
	2396	// machine.device("maincpu")->memory().space(AS_PROGRAM).install_legacy_readwrite_handler(0x800000, 0xffffff, FUNC(snes21_hi_r), FUNC(snes21_hi_w));
	2397	// machine.device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0x002800, 0x002800, 0x3f0000, 0, read8_delegate(FUNC(device_sns_cart_interface::chip_read),state->m_slotcart->m_cart));
	2398	// machine.device("maincpu")->memory().space(AS_PROGRAM).install_write_handler(0x002801, 0x002801, 0x3f0000, 0, write8_delegate(FUNC(device_sns_cart_interface::chip_write),state->m_slotcart->m_cart));
	2399	// set_5a22_map(*state->m_maincpu);
	2400	break;
2380	2401	}
2381	2402	}
2382	2403

trunk/src/mess/machine/sns_upd.c
r21591	r21592
1	1	/***********************************************************************************************************
2
	2
3	3	UPD7725 / UPD96050 add-on chip emulation (for SNES/SFC)
4	4	used in carts with DSP-1, DSP-1A, DSP-1B, DSP-2, DSP-3, DSP-4, ST-010 & ST-011 add-on chips
5
	5
6	6	Copyright MESS Team.
7	7	Visit http://mamedev.org for licensing and usage restrictions.
8
	8
9	9	***********************************************************************************************************/
10	10
11	11
r21591	r21592
24	24
25	25	sns_rom20_necdsp_device::sns_rom20_necdsp_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
26	26	: sns_rom_device(mconfig, SNS_LOROM_NECDSP, "SNES Cart (LoROM) + NEC DSP", tag, owner, clock),
27		m_upd7725(*this, "dsp")
	27	m_upd7725(*this, "dsp")
28	28	{
29	29	}
30	30
31	31	sns_rom21_necdsp_device::sns_rom21_necdsp_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
32	32	: sns_rom21_device(mconfig, SNS_HIROM_NECDSP, "SNES Cart (HiROM) + NEC DSP", tag, owner, clock),
33		m_upd7725(*this, "dsp")
	33	m_upd7725(*this, "dsp")
34	34	{
35	35	}
36	36
37	37	sns_rom_setadsp_device::sns_rom_setadsp_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock)
38	38	: sns_rom_device(mconfig, type, name, tag, owner, clock),
39		m_upd96050(*this, "dsp")
	39	m_upd96050(*this, "dsp")
40	40	{
41	41	}
42	42
r21591	r21592
223	223	else
224	224	return temp & 0xff;
225	225	}
	226	if (offset == 0x600000 \|\| offset == 0x600001)
	227	return (offset & 1) ? m_upd96050->snesdsp_read(FALSE) : m_upd96050->snesdsp_read(TRUE);
	228
226	229	return 0xff;
227	230	}
228	231
r21591	r21592
233	236	{
234	237	UINT16 address = offset & 0xffff;
235	238	UINT16 temp = m_upd96050->dataram_r(address/2);
236
	239
237	240	if (offset & 1)
238	241	{
239	242	temp &= 0xff;
r21591	r21592
244	247	temp &= 0xff00;
245	248	temp \|= data;
246	249	}
247
	250
248	251	m_upd96050->dataram_w(address/2, temp);
249	252	return;
250	253	}
	254	if (offset == 0x600000)
	255	m_upd96050->snesdsp_write(TRUE, data);
	256	if (offset == 0x600001)
	257	m_upd96050->snesdsp_write(FALSE, data);
251	258	}
252	259
253	260
r21591	r21592
316	323	{
317	324	return MACHINE_CONFIG_NAME( snes_st011 );
318	325	}
319

trunk/src/mess/machine/sns_upd.h
r21591	r21592
13	13	public:
14	14	// construction/destruction
15	15	sns_rom20_necdsp_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
16
	16
17	17	// device-level overrides
18	18	virtual void device_start();
19	19	virtual void device_config_complete() { m_shortname = "sns_rom_necdsp"; }
20	20	virtual machine_config_constructor device_mconfig_additions() const;
21
	21
22	22	required_device<upd7725_device> m_upd7725;
23
	23
24	24	// additional reading and writing
25	25	virtual DECLARE_READ8_MEMBER(chip_read);
26	26	virtual DECLARE_WRITE8_MEMBER(chip_write);
27
	27
28	28	virtual DECLARE_READ32_MEMBER(necdsp_prg_r);
29	29	virtual DECLARE_READ16_MEMBER(necdsp_data_r);
30	30	};
r21591	r21592
36	36	public:
37	37	// construction/destruction
38	38	sns_rom21_necdsp_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
39
	39
40	40	// device-level overrides
41	41	virtual void device_start();
42	42	virtual void device_config_complete() { m_shortname = "sns_rom21_necdsp"; }
43	43	virtual machine_config_constructor device_mconfig_additions() const;
44
	44
45	45	required_device<upd7725_device> m_upd7725;
46
	46
47	47	// additional reading and writing
48	48	virtual DECLARE_READ8_MEMBER(chip_read);
49	49	virtual DECLARE_WRITE8_MEMBER(chip_write);
50
	50
51	51	virtual DECLARE_READ32_MEMBER(necdsp_prg_r);
52	52	virtual DECLARE_READ16_MEMBER(necdsp_data_r);
53	53	};
r21591	r21592
59	59	public:
60	60	// construction/destruction
61	61	sns_rom_setadsp_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock);
62
	62
63	63	// device-level overrides
64	64	virtual void device_start();
65	65	virtual void device_config_complete() { m_shortname = "sns_rom_setadsp"; }
66
	66
67	67	required_device<upd96050_device> m_upd96050;
68
	68
69	69	// additional reading and writing
70	70	virtual DECLARE_READ8_MEMBER(chip_read);
71	71	virtual DECLARE_WRITE8_MEMBER(chip_write);
72
	72
73	73	virtual DECLARE_READ32_MEMBER(setadsp_prg_r);
74	74	virtual DECLARE_READ16_MEMBER(setadsp_data_r);
75	75	};
r21591	r21592
81	81	public:
82	82	// construction/destruction
83	83	sns_rom_seta10dsp_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
84
	84
85	85	// device-level overrides
86	86	virtual void device_config_complete() { m_shortname = "sns_rom_seta10"; }
87	87	virtual machine_config_constructor device_mconfig_additions() const;
r21591	r21592
94	94	public:
95	95	// construction/destruction
96	96	sns_rom_seta11dsp_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
97
	97
98	98	// device-level overrides
99	99	virtual void device_config_complete() { m_shortname = "sns_rom_seta11"; }
100	100	virtual machine_config_constructor device_mconfig_additions() const;

trunk/src/mess/machine/sns_sfx.c
r21591	r21592
1	1	/***********************************************************************************************************
2
	2
3	3	SuperFX add-on chip emulation (for SNES/SFC)
4
	4
5	5	Copyright MESS Team.
6	6	Visit http://mamedev.org for licensing and usage restrictions.
7
	7
8	8	***********************************************************************************************************/
9	9
10	10
r21591	r21592
110	110	READ8_MEMBER( sns_rom_superfx_device::read_l )
111	111	{
112	112	UINT16 address = offset & 0xffff;
113
	113
114	114	if (offset < 0x400000)
115	115	{
116	116	if (address >= 0x6000 && address < 0x8000)
117	117	{
118	118	if (superfx_access_ram(m_superfx))
119		return sfx_ram[offset & 0x1fff];
	119	return sfx_ram[offset & 0x1fff];
120	120	}
121	121	if (address >= 0x8000)
122	122	return m_rom[rom_bank_map[offset / 0x10000] * 0x8000 + (offset & 0x7fff)];
r21591	r21592
139	139	else
140	140	{
141	141	if (superfx_access_ram(m_superfx))
142		return sfx_ram[offset & 0xfffff];
	142	return sfx_ram[offset & 0xfffff];
143	143	}
144
145		return 0xff; // should be open bus...
	144
	145	return 0xff; // should be open bus...
146	146	}
147	147
148	148
r21591	r21592
167	167	READ8_MEMBER(sns_rom_superfx_device::read_h)
168	168	{
169	169	UINT16 address = offset & 0xffff;
170
	170
171	171	if (offset < 0x400000)
172	172	{
173	173	if (address >= 0x6000 && address < 0x8000)
174	174	{
175	175	if (superfx_access_ram(m_superfx))
176		return sfx_ram[offset & 0x1fff];
	176	return sfx_ram[offset & 0x1fff];
177	177	}
178	178	if (address >= 0x8000)
179	179	return m_rom[rom_bank_map[offset / 0x10000] * 0x8000 + (offset & 0x7fff)];
r21591	r21592
196	196	else
197	197	{
198	198	if (superfx_access_ram(m_superfx))
199		return sfx_ram[offset & 0xfffff];
	199	return sfx_ram[offset & 0xfffff];
200	200	}
201
202		return 0xff; // should be open bus...
	201
	202	return 0xff; // should be open bus...
203	203	}
204	204
205	205	WRITE8_MEMBER( sns_rom_superfx_device::write_h )
r21591	r21592
219	219	sfx_ram[offset & 0xfffff] = data;
220	220	}
221	221	}
222

trunk/src/mess/machine/sns_sfx.h
r21591	r21592
13	13	public:
14	14	// construction/destruction
15	15	sns_rom_superfx_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
16
	16
17	17	// device-level overrides
18	18	virtual void device_start();
19	19	virtual void device_config_complete() { m_shortname = "sns_rom_superfx"; }
20	20	virtual machine_config_constructor device_mconfig_additions() const;
21
	21
22	22	required_device<device_t> m_superfx;
23
	23
24	24	// additional reading and writing
25	25	virtual DECLARE_READ8_MEMBER(read_l);
26	26	virtual DECLARE_WRITE8_MEMBER(write_l);
r21591	r21592
28	28	virtual DECLARE_WRITE8_MEMBER(write_h);
29	29	virtual DECLARE_READ8_MEMBER(chip_read);
30	30	virtual DECLARE_WRITE8_MEMBER(chip_write);
31
	31
32	32	virtual DECLARE_READ8_MEMBER(superfx_r_bank1);
33	33	virtual DECLARE_READ8_MEMBER(superfx_r_bank2);
34	34	virtual DECLARE_READ8_MEMBER(superfx_r_bank3);
r21591	r21592
36	36	virtual DECLARE_WRITE8_MEMBER(superfx_w_bank2);
37	37	virtual DECLARE_WRITE8_MEMBER(superfx_w_bank3);
38	38	virtual DECLARE_WRITE_LINE_MEMBER(snes_extern_irq_w);
39
40
	39
	40
41	41	UINT8 sfx_ram[0x200000];
42	42	};
43	43

trunk/src/mess/machine/sns_rom.c
r21591	r21592
1	1	/***********************************************************************************************************
2
	2
3	3	Super NES/Famicom (LoROM) cartridge emulation (for SNES/SFC)
4
	4
5	5	Copyright MESS Team.
6	6	Visit http://mamedev.org for licensing and usage restrictions.
7
	7
8	8	***********************************************************************************************************/
9	9
10	10
r21591	r21592
62	62	// or from rom?
63	63	m_offset = (m_ram[0x1ff5] & 0x01) ? 0x1800 : 0x1c00;
64	64	m_address = (m_ram[0x1ff6] & 0x7f);
65		m_shift = (m_ram[0x1ff6] & 0x03) << 1;
	65	m_shift = (m_ram[0x1ff6] & 0x03) << 1;
66	66
67	67	save_item(NAME(m_ram));
68	68	save_item(NAME(m_address));
r21591	r21592
84	84	{
85	85	UINT8 value = 0xff;
86	86	UINT16 address = offset & 0xffff;
87
	87
88	88	if (offset < 0x700000)
89	89	{
90	90	int bank = offset / 0x10000;
r21591	r21592
107	107	value = m_nvram[offset & mask];
108	108	}
109	109	else
110		value = 0xff; // this should never happened...
	110	value = 0xff; // this should never happened...
111	111	}
112	112	else
113	113	{
r21591	r21592
125	125
126	126	WRITE8_MEMBER(sns_rom_device::write_h)
127	127	{
128		if (offset >= 0x700000) // SRAM
	128	if (offset >= 0x700000) // SRAM
129	129	{
130	130	if (m_nvram_size > 0x8000)
131	131	{
r21591	r21592
161	161	// same as above but additional read/write handling for the add-on chip
162	162
163	163	/***************************************************************************
164
	164
165	165	Based on C++ implementation by Byuu in BSNES.
166
	166
167	167	Byuu's code is released under GNU General Public License
168	168	version 2 as published by the Free Software Foundation.
169
	169
170	170	The implementation below is released under the MAME license
171	171	for use in MAME, MESS and derivatives by permission of Byuu
172
	172
173	173	Copyright (for the implementation below) MESS Team.
174	174	Visit http://mamedev.org for licensing and usage restrictions.
175
	175
176	176	***********************************************************************************************************/
177	177
178	178
r21591	r21592
180	180	{
181	181	UINT16 address = offset & 0x1fff;
182	182	UINT8 value;
183
	183
184	184	switch (address)
185	185	{
186	186	case 0x1ff0:
187	187	value = m_ram[m_offset + (m_address << 2) + 0];
188	188	break;
189
	189
190	190	case 0x1ff1:
191	191	value = m_ram[m_offset + (m_address << 2) + 1];
192	192	break;
193
	193
194	194	case 0x1ff2:
195	195	value = m_ram[m_offset + (m_address << 2) + 2];
196	196	break;
197
	197
198	198	case 0x1ff3:
199	199	value = m_ram[m_offset + (m_address << 2) + 3];
200	200	break;
201
	201
202	202	case 0x1ff4:
203	203	value = m_ram[m_offset + (m_address >> 2) + 0x200];
204	204	break;
205
	205
206	206	default:
207	207	value = m_ram[address];
208	208	break;
209	209	}
210
	210
211	211	return value;
212	212	}
213	213
r21591	r21592
216	216	{
217	217	UINT16 address = offset & 0x1fff;
218	218	UINT8 temp;
219
	219
220	220	switch(address)
221	221	{
222	222	case 0x1ff0:
223	223	m_ram[m_offset + (m_address << 2) + 0] = data;
224	224	break;
225
	225
226	226	case 0x1ff1:
227	227	m_ram[m_offset + (m_address << 2) + 1] = data;
228	228	break;
229
	229
230	230	case 0x1ff2:
231	231	m_ram[m_offset + (m_address << 2) + 2] = data;
232	232	break;
233
	233
234	234	case 0x1ff3:
235	235	m_ram[m_offset + (m_address << 2) + 3] = data;
236	236	break;
237
	237
238	238	case 0x1ff4:
239	239	temp = m_ram[m_offset + (m_address >> 2) + 0x200];
240	240	temp = (temp & ~(3 << m_shift)) \| ((data & 0x03) << m_shift);
241	241	m_ram[m_offset + (m_address >> 2) + 0x200] = temp;
242	242	break;
243
	243
244	244	case 0x1ff5:
245	245	m_offset = (data & 0x01) ? 0x1800 : 0x1c00;
246	246	m_ram[address & 0x1fff] = data;
247	247	break;
248
	248
249	249	case 0x1ff6:
250	250	m_address = data & 0x7f;
251	251	m_shift = (data & 0x03) << 1;
252	252	m_ram[address & 0x1fff] = data;
253	253	break;
254
	254
255	255	default:
256	256	m_ram[address & 0x1fff] = data;
257	257	break;
258	258	}
259	259	}
260

trunk/src/mess/machine/sns_rom.h
r21591	r21592
7	7	// ======================> sns_rom_device
8	8
9	9	class sns_rom_device : public device_t,
10		public device_sns_cart_interface
	10	public device_sns_cart_interface
11	11	{
12	12	public:
13	13	// construction/destruction
14	14	sns_rom_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock);
15	15	sns_rom_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
16
	16
17	17	// device-level overrides
18	18	virtual void device_start();
19	19	virtual void device_config_complete() { m_shortname = "sns_rom"; }
r21591	r21592
32	32	public:
33	33	// construction/destruction
34	34	sns_rom_pokemon_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
35
	35
36	36	// device-level overrides
37	37	virtual void device_start();
38	38	virtual void device_config_complete() { m_shortname = "sns_rom_pokemon"; }
39
	39
40	40	// reading and writing
41		virtual DECLARE_READ8_MEMBER(chip_read); // protection device
42		virtual DECLARE_WRITE8_MEMBER(chip_write); // protection device
	41	virtual DECLARE_READ8_MEMBER(chip_read); // protection device
	42	virtual DECLARE_WRITE8_MEMBER(chip_write); // protection device
43	43	UINT8 m_latch;
44	44	};
45	45
r21591	r21592
50	50	public:
51	51	// construction/destruction
52	52	sns_rom_obc1_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
53
	53
54	54	// device-level overrides
55	55	virtual void device_start();
56	56	virtual void device_config_complete() { m_shortname = "sns_rom_obc1"; }
57
	57
58	58	// additional reading and writing
59	59	virtual DECLARE_READ8_MEMBER(chip_read);
60	60	virtual DECLARE_WRITE8_MEMBER(chip_write);
61
	61
62	62	int m_address;
63	63	int m_offset;
64	64	int m_shift;

trunk/src/mess/machine/sns_bsx.c
r21591	r21592
1	1	/***********************************************************************************************************
2
	2
3	3	BS-X Satellaview cartridge emulation (for SNES/SFC)
4
	4
5	5	Copyright MESS Team.
6	6	Visit http://mamedev.org for licensing and usage restrictions.
7	7
r21591	r21592
89	89	m_command = 0;
90	90	m_write_old = 0;
91	91	m_write_new = 0;
92
	92
93	93	m_flash_enable = 0;
94	94	m_read_enable = 0;
95	95	m_write_enable = 0;
r21591	r21592
129	129	mame_printf_debug("BS-X Base Unit reg read outside correct range!\n");
130	130	return 0x00;
131	131	}
132
133		switch (offset)
134		{
	132
	133	switch (offset)
	134	{
135	135	// no 218b? no 218d? no 2191? no 2195? no 219a-219f?
136		case 0x2192:
	136	case 0x2192:
137	137	{
138	138	UINT8 counter = r2192_counter++;
139		if (r2192_counter >= 18)
	139	if (r2192_counter >= 18)
140	140	r2192_counter = 0;
141
142		if (counter == 0)
	141
	142	if (counter == 0)
143	143	{
144	144	system_time curtime, *systime = &curtime;
145		m_machine.current_datetime(curtime);
	145	m_machine.current_datetime(curtime);
146	146	r2192_hour = systime->local_time.hour;
147	147	r2192_minute = systime->local_time.minute;
148	148	r2192_second = systime->local_time.second;
149	149	}
150
151		switch (counter)
	150
	151	switch (counter)
152	152	{
153	153	case 0: return 0x00; //???
154	154	case 1: return 0x00; //???
r21591	r21592
169	169	case 16: return 0x00; //???
170	170	case 17: return 0x00; //???
171	171	}
172		}
	172	}
173	173	break;
174	174
175	175	case 0x2193:
r21591	r21592
191	191	mame_printf_debug("BS-X Base Unit reg write outside correct range!\n");
192	192	return;
193	193	}
194
195		switch(offset)
	194
	195	switch(offset)
196	196	{
197	197	// no 218d? no 2190? no 2195? no 2196? no 2198? no 219a-219f?
198	198	case 0x218f:
199		regs[6] >>= 1; // 0x218e
200		regs[6] = regs[7] - regs[6]; // 0x218f - 0x218e
201		regs[7] >>= 1; // 0x218f
	199	regs[6] >>= 1; // 0x218e
	200	regs[6] = regs[7] - regs[6]; // 0x218f - 0x218e
	201	regs[7] >>= 1; // 0x218f
202	202	break;
203
	203
204	204	case 0x2191:
205	205	regs[offset - 0x2188] = data;
206	206	r2192_counter = 0;
207	207	break;
208
	208
209	209	case 0x2192:
210		regs[8] = data; // sets 0x2190
	210	regs[8] = data; // sets 0x2190
211	211	break;
212
	212
213	213	default:
214	214	regs[offset - 0x2188] = data;
215	215	break;
r21591	r21592
266	266	rom_access = 0;
267	267	else
268	268	{
269		// rom_access = BIT(m_cart_regs[0x02], 7) + 1;
270		rom_access = 1; // for whatever reason bsxsore changes access mode here and then fails to read the ROM properly!
	269	// rom_access = BIT(m_cart_regs[0x02], 7) + 1;
	270	rom_access = 1; // for whatever reason bsxsore changes access mode here and then fails to read the ROM properly!
271	271	printf("rom_access %s\n", !BIT(m_cart_regs[0x02], 7) ? "Lo" : "Hi");
272	272	}
273	273	}
r21591	r21592
317	317	int bank = (rom_access == 1) ? (offset / 0x10000) : (offset / 0x8000);
318	318	return m_rom[rom_bank_map[bank] * 0x8000 + (offset & 0x7fff)];
319	319	}
320
	320
321	321	return 0x00;
322	322	}
323	323
r21591	r21592
330	330	if (m_slot->m_cart && m_slot->m_cart->get_rom_size())
331	331	return m_slot->m_cart->read_l(space, offset);
332	332	}
333
	333
334	334	// if not in any of the cases above...
335	335	//$00-3f\|80-bf:8000-ffff
336	336	//$40-7f\|c0-ff:0000-ffff
r21591	r21592
341	341	int bank = (rom_access == 1) ? (offset / 0x10000) : (offset / 0x8000);
342	342	return m_rom[rom_bank_map[bank] * 0x8000 + (offset & 0x7fff)];
343	343	}
344
	344
345	345	return 0x00;
346	346	}
347	347
r21591	r21592
378	378	// 0x70-0x77:0x0000-0xffff -> PRAM
379	379	m_pram[offset & 0x7ffff] = data;
380	380	}
381
	381
382	382	// if not in any of the cases above...
383	383	//$00-3f\|80-bf:8000-ffff
384	384	//$40-7f\|c0-ff:0000-ffff
r21591	r21592
394	394	// write to cart...
395	395	return;
396	396	}
397
	397
398	398	// if not in any of the cases above...
399	399	//$00-3f\|80-bf:8000-ffff
400	400	//$40-7f\|c0-ff:0000-ffff
r21591	r21592
407	407	{
408	408	if ((offset & 0xffff) >= 0x2188 && (offset & 0xffff) < 0x21a0)
409	409	return m_base_unit->read(offset & 0xffff);
410
411		if ((offset & 0xf0ffff) == 0x005000) //$[00-0f]:5000 reg access
	410
	411	if ((offset & 0xf0ffff) == 0x005000) //$[00-0f]:5000 reg access
412	412	{
413	413	UINT8 n = (offset >> 16) & 0x0f;
414	414	return m_cart_regs[n];
415	415	}
416
417		if ((offset & 0xf8f000) == 0x105000) //$[10-17]:[5000-5fff] SRAM access
	416
	417	if ((offset & 0xf8f000) == 0x105000) //$[10-17]:[5000-5fff] SRAM access
418	418	{
419	419	return m_nvram[((offset >> 16) & 7) * 0x1000 + (offset & 0xfff)];
420	420	}
421
	421
422	422	return 0x00;
423	423	}
424	424
r21591	r21592
426	426	{
427	427	if ((offset & 0xffff) >= 0x2188 && (offset & 0xffff) < 0x21a0)
428	428	m_base_unit->write(offset & 0xffff, data);
429
430		if ((offset & 0xf0ffff) == 0x005000) //$[00-0f]:5000 reg access
	429
	430	if ((offset & 0xf0ffff) == 0x005000) //$[00-0f]:5000 reg access
431	431	{
432	432	UINT8 n = (offset >> 16) & 0x0f;
433	433	m_cart_regs[n] = data;
434	434	if (n == 0x0e && data & 0x80)
435	435	access_update();
436	436	}
437
438		if ((offset & 0xf8f000) == 0x105000) //$[10-17]:[5000-5fff] SRAM access
	437
	438	if ((offset & 0xf8f000) == 0x105000) //$[10-17]:[5000-5fff] SRAM access
439	439	{
440	440	m_nvram[((offset >> 16) & 7) * 0x1000 + (offset & 0xfff)] = data;
441	441	}
r21591	r21592
583	583	WRITE8_MEMBER(sns_rom_bsmempak_device::write_l)
584	584	{
585	585	}
586

trunk/src/mess/machine/sns_bsx.h
r21591	r21592
17	17
18	18	private:
19	19	// regs
20		UINT8 regs[0x18]; // 0x2188-0x219f
	20	UINT8 regs[0x18]; // 0x2188-0x219f
21	21
22	22	// counter + clock
23	23	UINT8 r2192_counter;
r21591	r21592
34	34	// construction/destruction
35	35	sns_rom_bsx_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock);
36	36	sns_rom_bsx_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
37
	37
38	38	// device-level overrides
39	39	virtual void device_start();
40	40	virtual void device_config_complete() { m_shortname = "sns_rom_bsx"; }
41	41	virtual machine_config_constructor device_mconfig_additions() const;
42
	42
43	43	// additional reading and writing
44	44	virtual DECLARE_READ8_MEMBER(read_l);
45	45	virtual DECLARE_READ8_MEMBER(read_h);
r21591	r21592
47	47	virtual DECLARE_WRITE8_MEMBER(write_h);
48	48	virtual DECLARE_READ8_MEMBER(chip_read);
49	49	virtual DECLARE_WRITE8_MEMBER(chip_write);
50
	50
51	51	// base regs
52	52	BSX_base *m_base_unit;
53
	53
54	54	// cart regs
55	55	UINT8 m_cart_regs[16];
56		UINT8 access_00_1f; // 1 = CART, 0 = NOTHING
57		UINT8 access_80_9f; // 1 = CART, 0 = NOTHING
58		UINT8 access_40_4f; // 1 = NOTHING, 0 = PRAM
59		UINT8 access_50_5f; // 1 = NOTHING, 0 = PRAM
60		UINT8 access_60_6f; // 1 = PRAM, 0 = NOTHING
61		UINT8 rom_access; // 2 = HiROM, 1 = LoROM, 0 = PRAM
	56	UINT8 access_00_1f; // 1 = CART, 0 = NOTHING
	57	UINT8 access_80_9f; // 1 = CART, 0 = NOTHING
	58	UINT8 access_40_4f; // 1 = NOTHING, 0 = PRAM
	59	UINT8 access_50_5f; // 1 = NOTHING, 0 = PRAM
	60	UINT8 access_60_6f; // 1 = PRAM, 0 = NOTHING
	61	UINT8 rom_access; // 2 = HiROM, 1 = LoROM, 0 = PRAM
62	62	void access_update();
63
64
	63
	64
65	65	UINT8 m_pram[0x80000];
66
	66
67	67	private:
68	68	required_device<sns_bsx_cart_slot_device> m_slot;
69	69	};
r21591	r21592
75	75	public:
76	76	// construction/destruction
77	77	sns_rom_bsxlo_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
78
	78
79	79	// device-level overrides
80	80	virtual void device_start();
81	81	virtual void device_config_complete() { m_shortname = "sns_rom_bsxlo"; }
82	82	virtual machine_config_constructor device_mconfig_additions() const;
83
	83
84	84	// additional reading and writing
85	85	virtual DECLARE_READ8_MEMBER(read_l);
86	86	virtual DECLARE_READ8_MEMBER(read_h);
87		// virtual DECLARE_WRITE8_MEMBER(write_l);
88		// virtual DECLARE_WRITE8_MEMBER(write_h);
89		// virtual DECLARE_READ8_MEMBER(chip_read);
90		// virtual DECLARE_WRITE8_MEMBER(chip_write);
91
	87	// virtual DECLARE_WRITE8_MEMBER(write_l);
	88	// virtual DECLARE_WRITE8_MEMBER(write_h);
	89	// virtual DECLARE_READ8_MEMBER(chip_read);
	90	// virtual DECLARE_WRITE8_MEMBER(chip_write);
	91
92	92	private:
93	93	required_device<sns_bsx_cart_slot_device> m_slot;
94	94	};
r21591	r21592
100	100	public:
101	101	// construction/destruction
102	102	sns_rom_bsxhi_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
103
	103
104	104	// device-level overrides
105	105	virtual void device_start();
106	106	virtual void device_config_complete() { m_shortname = "sns_rom_bsxhi"; }
107	107	virtual machine_config_constructor device_mconfig_additions() const;
108
	108
109	109	// additional reading and writing
110	110	virtual DECLARE_READ8_MEMBER(read_l);
111	111	virtual DECLARE_READ8_MEMBER(read_h);
112	112	virtual DECLARE_WRITE8_MEMBER(write_l);
113	113	virtual DECLARE_WRITE8_MEMBER(write_h);
114		// virtual DECLARE_READ8_MEMBER(chip_read);
115		// virtual DECLARE_WRITE8_MEMBER(chip_write);
116
	114	// virtual DECLARE_READ8_MEMBER(chip_read);
	115	// virtual DECLARE_WRITE8_MEMBER(chip_write);
	116
117	117	private:
118	118	required_device<sns_bsx_cart_slot_device> m_slot;
119	119	};
r21591	r21592
126	126	public:
127	127	// construction/destruction
128	128	sns_rom_bsmempak_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
129
	129
130	130	// device-level overrides
131	131	virtual void device_start();
132	132	virtual void device_config_complete() { m_shortname = "sns_bsmempak"; }
133
	133
134	134	// additional reading and writing
135	135	virtual DECLARE_READ8_MEMBER(read_l);
136	136	virtual DECLARE_READ8_MEMBER(read_h);
137	137	virtual DECLARE_WRITE8_MEMBER(write_l);
138		// virtual DECLARE_WRITE8_MEMBER(write_h);
139		// virtual DECLARE_READ8_MEMBER(chip_read);
140		// virtual DECLARE_WRITE8_MEMBER(chip_write);
141
	138	// virtual DECLARE_WRITE8_MEMBER(write_h);
	139	// virtual DECLARE_READ8_MEMBER(chip_read);
	140	// virtual DECLARE_WRITE8_MEMBER(chip_write);
	141
142	142	// flash regs
143	143	UINT32 m_command;
144	144	UINT8 m_write_old;
145	145	UINT8 m_write_new;
146
	146
147	147	int m_flash_enable;
148	148	int m_read_enable;
149	149	int m_write_enable;

trunk/src/mess/machine/sns_spc7110.c
r21591	r21592
1	1	/***********************************************************************************************************
2
	2
3	3	SPC-7110 add-on chip emulation (for SNES/SFC)
4
	4
5	5	Based on C++ implementation by Byuu in BSNES.
6
	6
7	7	Byuu's code is released under GNU General Public License
8	8	version 2 as published by the Free Software Foundation.
9	9
10	10	The implementation below is released under the MAME license
11	11	for use in MAME, MESS and derivatives by permission of Byuu
12
	12
13	13	Copyright (for the implementation below) MESS Team.
14	14	Visit http://mamedev.org for licensing and usage restrictions.
15
	15
16	16	***********************************************************************************************************/
17	17
18	18
r21591	r21592
59	59	m_r480a = 0x00;
60	60	m_r480b = 0x00;
61	61	m_r480c = 0x00;
62
	62
63	63	m_r4811 = 0x00;
64	64	m_r4812 = 0x00;
65	65	m_r4813 = 0x00;
r21591	r21592
68	68	m_r4816 = 0x00;
69	69	m_r4817 = 0x00;
70	70	m_r4818 = 0x00;
71
	71
72	72	m_r481x = 0x00;
73	73	m_r4814_latch = 0;
74	74	m_r4815_latch = 0;
75
	75
76	76	m_r4820 = 0x00;
77	77	m_r4821 = 0x00;
78	78	m_r4822 = 0x00;
r21591	r21592
89	89	m_r482d = 0x00;
90	90	m_r482e = 0x00;
91	91	m_r482f = 0x00;
92
	92
93	93	m_r4830 = 0x00;
94	94	m_r4831 = 0;
95		m_dx_offset = spc7110_datarom_addr(0 * 0x100000, 0x200000); // we would need the rom length here...
	95	m_dx_offset = spc7110_datarom_addr(0 * 0x100000, 0x200000); // we would need the rom length here...
96	96	m_r4832 = 1;
97		m_ex_offset = spc7110_datarom_addr(1 * 0x100000, 0x200000); // we would need the rom length here...
	97	m_ex_offset = spc7110_datarom_addr(1 * 0x100000, 0x200000); // we would need the rom length here...
98	98	m_r4833 = 2;
99		m_fx_offset = spc7110_datarom_addr(2 * 0x100000, 0x200000); // we would need the rom length here...
	99	m_fx_offset = spc7110_datarom_addr(2 * 0x100000, 0x200000); // we would need the rom length here...
100	100	m_r4834 = 0x00;
101
	101
102	102	m_r4840 = 0x00;
103	103	m_r4841 = 0x00;
104	104	m_r4842 = 0x00;
105
	105
106	106	m_decomp = auto_alloc(machine(), SPC7110_Decomp(machine()));
107	107
108	108	save_item(NAME(m_ram));
r21591	r21592
169	169	void sns_rom_spc7110rtc_device::device_start()
170	170	{
171	171	memset(rom_bank_map, 0, sizeof(rom_bank_map));
172
	172
173	173	spc7110_start();
174	174
175	175	// RTC
r21591	r21592
179	179	m_rtc_offset = 0;
180	180
181	181	// at this stage, rtc_ram is not yet allocated. this will be fixed when converting RTC to be a separate device.
182		// spc7110_update_time(0);
183
	182	// spc7110_update_time(0);
	183
184	184	save_item(NAME(m_rtc_state));
185	185	save_item(NAME(m_rtc_mode));
186	186	save_item(NAME(m_rtc_index));
r21591	r21592
202	202	{ 0x08, 10, 4, 0 },
203	203	{ 0x03, 12, 5, 0 },
204	204	{ 0x01, 15, 5, 0 },
205
	205
206	206	{ 0x5a, 7, 7, 1 },
207	207	{ 0x3f, 19, 8, 0 },
208	208	{ 0x2c, 21, 9, 0 },
r21591	r21592
216	216	{ 0x04, 32, 17, 0 },
217	217	{ 0x03, 34, 18, 0 },
218	218	{ 0x02, 35, 5, 0 },
219
	219
220	220	{ 0x5a, 20, 20, 1 },
221	221	{ 0x48, 39, 21, 0 },
222	222	{ 0x3a, 40, 22, 0 },
r21591	r21592
237	237	{ 0x03, 34, 37, 0 },
238	238	{ 0x02, 35, 38, 0 },
239	239	{ 0x02, 36, 5, 0 },
240
	240
241	241	{ 0x58, 39, 40, 1 },
242	242	{ 0x4d, 47, 41, 0 },
243	243	{ 0x43, 48, 42, 0 },
r21591	r21592
246	246	{ 0x2e, 51, 45, 0 },
247	247	{ 0x29, 44, 46, 0 },
248	248	{ 0x25, 45, 24, 0 },
249
	249
250	250	{ 0x56, 47, 48, 1 },
251	251	{ 0x4f, 47, 49, 0 },
252	252	{ 0x47, 48, 50, 0 },
r21591	r21592
258	258	static const UINT8 spc7110_mode2_context_table[32][2] =
259	259	{
260	260	{ 1, 2 },
261
	261
262	262	{ 3, 8 },
263	263	{ 13, 14 },
264
	264
265	265	{ 15, 16 },
266	266	{ 17, 18 },
267	267	{ 19, 20 },
r21591	r21592
274	274	{ 25, 26 },
275	275	{ 27, 28 },
276	276	{ 29, 30 },
277
	277
278	278	{ 31, 31 },
279	279	{ 31, 31 },
280	280	{ 31, 31 },
r21591	r21592
291	291	{ 31, 31 },
292	292	{ 31, 31 },
293	293	{ 31, 31 },
294
	294
295	295	{ 31, 31 },
296	296	};
297	297
r21591	r21592
300	300	{
301	301	m_decomp_buffer = (UINT8*)auto_alloc_array(machine, UINT8, SPC7110_DECOMP_BUFFER_SIZE);
302	302	reset();
303
	303
304	304	for (int i = 0; i < 256; i++)
305	305	{
306	306	#define map(x, y) (((i >> x) & 1) << y)
r21591	r21592
327	327	//mode 3 is invalid; this is treated as a special case to always return 0x00
328	328	//set to mode 3 so that reading decomp port before starting first decomp will return 0x00
329	329	m_decomp_mode = 3;
330
	330
331	331	m_decomp_buffer_rdoffset = 0;
332	332	m_decomp_buffer_wroffset = 0;
333	333	m_decomp_buffer_length = 0;
r21591	r21592
337	337	{
338	338	m_decomp_mode = mode;
339	339	m_decomp_offset = offset;
340
	340
341	341	m_decomp_buffer_rdoffset = 0;
342	342	m_decomp_buffer_wroffset = 0;
343	343	m_decomp_buffer_length = 0;
344
	344
345	345	//reset context states
346	346	for (int i = 0; i < 32; i++)
347	347	{
348	348	m_context[i].index = 0;
349	349	m_context[i].invert = 0;
350	350	}
351
	351
352	352	switch (m_decomp_mode)
353	353	{
354	354	case 0: mode0(1, ROM, len); break;
355	355	case 1: mode1(1, ROM, len); break;
356	356	case 2: mode2(1, ROM, len); break;
357	357	}
358
	358
359	359	//decompress up to requested output data index
360	360	while (index--)
361	361	{
r21591	r21592
366	366	UINT8 SPC7110_Decomp::read(UINT8 *ROM, UINT32 len)
367	367	{
368	368	UINT8 data;
369
	369
370	370	if (m_decomp_buffer_length == 0)
371	371	{
372	372	//decompress at least (SPC7110_DECOMP_BUFFER_SIZE / 2) bytes to the buffer
r21591	r21592
375	375	case 0:
376	376	mode0(0, ROM, len);
377	377	break;
378
	378
379	379	case 1:
380	380	mode1(0, ROM, len);
381	381	break;
382
	382
383	383	case 2:
384	384	mode2(0, ROM, len);
385	385	break;
386
	386
387	387	default:
388	388	return 0x00;
389	389	}
390	390	}
391
	391
392	392	data = m_decomp_buffer[m_decomp_buffer_rdoffset++];
393	393	m_decomp_buffer_rdoffset &= SPC7110_DECOMP_BUFFER_SIZE - 1;
394	394	m_decomp_buffer_length--;
r21591	r21592
416	416	{
417	417	static UINT8 val, in, span;
418	418	static INT32 out, inverts, lps, in_count;
419
	419
420	420	if (init == 1)
421	421	{
422	422	out = inverts = lps = 0;
r21591	r21592
426	426	in_count = 8;
427	427	return;
428	428	}
429
	429
430	430	while (m_decomp_buffer_length < (SPC7110_DECOMP_BUFFER_SIZE >> 1))
431	431	{
432	432	for (int bit = 0; bit < 8; bit++)
r21591	r21592
440	440	{
441	441	con += 15;
442	442	}
443
	443
444	444	//get prob and mps
445	445	prob = probability(con);
446	446	mps = (((out >> 15) & 1) ^ m_context[con].invert);
447
	447
448	448	//get bit
449	449	if (val <= span - prob) //mps
450	450	{
r21591	r21592
459	459	out = (out << 1) + 1 - mps;
460	460	flag_lps = 1;
461	461	}
462
	462
463	463	//renormalize
464	464	while (span < 0x7f)
465	465	{
466	466	shift++;
467
	467
468	468	span = (span << 1) + 1;
469	469	val = (val << 1) + (in >> 7);
470
	470
471	471	in <<= 1;
472	472	if (--in_count == 0)
473	473	{
r21591	r21592
475	475	in_count = 8;
476	476	}
477	477	}
478
	478
479	479	//update processing info
480	480	lps = (lps << 1) + flag_lps;
481	481	inverts = (inverts << 1) + m_context[con].invert;
482
	482
483	483	//update context state
484	484	if (flag_lps & toggle_invert(con))
485	485	{
r21591	r21592
494	494	m_context[con].index = next_mps(con);
495	495	}
496	496	}
497
	497
498	498	//save byte
499	499	write(out);
500	500	}
r21591	r21592
505	505	static INT32 pixelorder[4], realorder[4];
506	506	static UINT8 in, val, span;
507	507	static INT32 out, inverts, lps, in_count;
508
	508
509	509	if (init == 1)
510	510	{
511	511	for (int i = 0; i < 4; i++)
r21591	r21592
519	519	in_count = 8;
520	520	return;
521	521	}
522
	522
523	523	while (m_decomp_buffer_length < (SPC7110_DECOMP_BUFFER_SIZE >> 1))
524	524	{
525	525	UINT16 data;
r21591	r21592
530	530	UINT32 b = ((out >> (7 * 2)) & 3);
531	531	UINT32 c = ((out >> (8 * 2)) & 3);
532	532	UINT32 con = (a == b) ? (b != c) : (b == c) ? 2 : 4 - (a == c);
533
	533
534	534	//update pixel order
535	535	UINT32 m, n;
536	536	for (m = 0; m < 4; m++)
r21591	r21592
545	545	pixelorder[n] = pixelorder[n - 1];
546	546	}
547	547	pixelorder[0] = a;
548
	548
549	549	//calculate the real pixel order
550	550	for (m = 0; m < 4; m++)
551	551	{
552	552	realorder[m] = pixelorder[m];
553	553	}
554
	554
555	555	//rotate reference pixel c value to top
556	556	for (m = 0; m < 4; m++)
557	557	{
r21591	r21592
565	565	realorder[n] = realorder[n - 1];
566	566	}
567	567	realorder[0] = c;
568
	568
569	569	//rotate reference pixel b value to top
570	570	for (m = 0; m < 4; m++)
571	571	{
r21591	r21592
579	579	realorder[n] = realorder[n - 1];
580	580	}
581	581	realorder[0] = b;
582
	582
583	583	//rotate reference pixel a value to top
584	584	for (m = 0; m < 4; m++)
585	585	{
r21591	r21592
593	593	realorder[n] = realorder[n - 1];
594	594	}
595	595	realorder[0] = a;
596
	596
597	597	//get 2 symbols
598	598	for (int bit = 0; bit < 2; bit++)
599	599	{
600	600	//get prob
601	601	UINT32 prob = probability(con);
602	602	UINT32 shift = 0;
603
	603
604	604	//get symbol
605	605	UINT32 flag_lps;
606	606	if (val <= span - prob) //mps
r21591	r21592
614	614	span = prob - 1;
615	615	flag_lps = 1;
616	616	}
617
	617
618	618	//renormalize
619	619	while (span < 0x7f)
620	620	{
621	621	shift++;
622
	622
623	623	span = (span << 1) + 1;
624	624	val = (val << 1) + (in >> 7);
625
	625
626	626	in <<= 1;
627	627	if (--in_count == 0)
628	628	{
r21591	r21592
630	630	in_count = 8;
631	631	}
632	632	}
633
	633
634	634	//update processing info
635	635	lps = (lps << 1) + flag_lps;
636	636	inverts = (inverts << 1) + m_context[con].invert;
637
	637
638	638	//update context state
639	639	if (flag_lps & toggle_invert(con))
640	640	{
r21591	r21592
648	648	{
649	649	m_context[con].index = next_mps(con);
650	650	}
651
	651
652	652	//get next context
653	653	con = 5 + (con << 1) + ((lps ^ inverts) & 1);
654	654	}
655
	655
656	656	//get pixel
657	657	b = realorder[(lps ^ inverts) & 3];
658	658	out = (out << 2) + b;
659	659	}
660
	660
661	661	//turn pixel data into bitplanes
662	662	data = morton_2x8(out);
663	663	write(data >> 8);
r21591	r21592
671	671	static UINT8 bitplanebuffer[16], buffer_index;
672	672	static UINT8 in, val, span;
673	673	static INT32 out0, out1, inverts, lps, in_count;
674
	674
675	675	if (init == 1)
676	676	{
677	677	for (int i = 0; i < 16; i++)
r21591	r21592
686	686	in_count = 8;
687	687	return;
688	688	}
689
	689
690	690	while (m_decomp_buffer_length < (SPC7110_DECOMP_BUFFER_SIZE >> 1))
691	691	{
692	692	UINT32 data;
r21591	r21592
698	698	UINT32 c = ((out1 >> (0 * 4)) & 15);
699	699	UINT32 con = 0;
700	700	UINT32 refcon = (a == b) ? (b != c) : (b == c) ? 2 : 4 - (a == c);
701
	701
702	702	//update pixel order
703	703	UINT32 m, n;
704	704	for (m = 0; m < 16; m++)
r21591	r21592
713	713	pixelorder[n] = pixelorder[n - 1];
714	714	}
715	715	pixelorder[0] = a;
716
	716
717	717	//calculate the real pixel order
718	718	for (m = 0; m < 16; m++)
719	719	{
720	720	realorder[m] = pixelorder[m];
721	721	}
722
	722
723	723	//rotate reference pixel c value to top
724	724	for (m = 0; m < 16; m++)
725	725	{
r21591	r21592
733	733	realorder[n] = realorder[n - 1];
734	734	}
735	735	realorder[0] = c;
736
	736
737	737	//rotate reference pixel b value to top
738	738	for (m = 0; m < 16; m++)
739	739	{
r21591	r21592
747	747	realorder[n] = realorder[n - 1];
748	748	}
749	749	realorder[0] = b;
750
	750
751	751	//rotate reference pixel a value to top
752	752	for (m = 0; m < 16; m++)
753	753	{
r21591	r21592
761	761	realorder[n] = realorder[n - 1];
762	762	}
763	763	realorder[0] = a;
764
	764
765	765	//get 4 symbols
766	766	for (int bit = 0; bit < 4; bit++)
767	767	{
768	768	UINT32 invertbit, shift;
769
	769
770	770	//get prob
771	771	UINT32 prob = probability(con);
772
	772
773	773	//get symbol
774	774	UINT32 flag_lps;
775	775	if (val <= span - prob) //mps
r21591	r21592
783	783	span = prob - 1;
784	784	flag_lps = 1;
785	785	}
786
	786
787	787	//renormalize
788	788	shift = 0;
789	789	while (span < 0x7f)
790	790	{
791	791	shift++;
792
	792
793	793	span = (span << 1) + 1;
794	794	val = (val << 1) + (in >> 7);
795
	795
796	796	in <<= 1;
797	797	if (--in_count == 0)
798	798	{
r21591	r21592
800	800	in_count = 8;
801	801	}
802	802	}
803
	803
804	804	//update processing info
805	805	lps = (lps << 1) + flag_lps;
806	806	invertbit = m_context[con].invert;
807	807	inverts = (inverts << 1) + invertbit;
808
	808
809	809	//update context state
810	810	if (flag_lps & toggle_invert(con))
811	811	{
r21591	r21592
819	819	{
820	820	m_context[con].index = next_mps(con);
821	821	}
822
	822
823	823	//get next context
824	824	con = spc7110_mode2_context_table[con][flag_lps ^ invertbit] + (con == 1 ? refcon : 0);
825	825	}
826
	826
827	827	//get pixel
828	828	b = realorder[(lps ^ inverts) & 0x0f];
829	829	out1 = (out1 << 4) + ((out0 >> 28) & 0x0f);
830	830	out0 = (out0 << 4) + b;
831	831	}
832
	832
833	833	//convert pixel data into bitplanes
834	834	data = morton_4x8(out0);
835	835	write(data >> 24);
836	836	write(data >> 16);
837	837	bitplanebuffer[buffer_index++] = data >> 8;
838	838	bitplanebuffer[buffer_index++] = data >> 0;
839
	839
840	840	if (buffer_index == 16)
841	841	{
842	842	for (int i = 0; i < 16; i++)
r21591	r21592
937	937	system_time curtime, *systime = &curtime;
938	938	machine().current_datetime(curtime);
939	939	int update = 1;
940
	940
941	941	m_rtc_offset += offset;
942
	942
943	943	// TEST: can we go beyond 24hrs of rounding?!? I doubt it will ever go beyond 3600, but I could be wrong...
944	944	assert(m_rtc_offset < 86400);
945
	945
946	946	/* do not update if CR0 or CR2 timer disable flags are set */
947	947	if ((m_rtc_ram[13] & 0x01) \|\| (m_rtc_ram[15] & 0x03))
948	948	update = 0;
949
	949
950	950	if (update)
951	951	{
952	952	/* update time with offset, assuming offset < 3600s */
r21591	r21592
954	954	UINT8 minute = systime->local_time.minute;
955	955	UINT8 hour = systime->local_time.hour;
956	956	UINT8 mday = systime->local_time.mday;
957
	957
958	958	while (m_rtc_offset >= 3600)
959	959	{
960	960	m_rtc_offset -= 3600;
961	961	hour++;
962
	962
963	963	if (hour == 24)
964	964	{
965	965	mday++;
966	966	hour = 0;
967	967	}
968	968	}
969
	969
970	970	while (m_rtc_offset >= 60)
971	971	{
972	972	m_rtc_offset -= 60;
973	973	minute++;
974
	974
975	975	if (minute == 60)
976	976	{
977	977	hour++;
978	978	minute = 0;
979	979	}
980	980	}
981
	981
982	982	while (m_rtc_offset)
983	983	{
984	984	m_rtc_offset -= 1;
985	985	second++;
986
	986
987	987	if (second == 60)
988	988	{
989	989	minute++;
990	990	second = 0;
991	991	}
992	992	}
993
	993
994	994	m_rtc_ram[0] = second % 10;
995	995	m_rtc_ram[1] = second / 10;
996	996	m_rtc_ram[2] = minute % 10;
r21591	r21592
1023	1023	if (address >= 0x8000)
1024	1024	return m_rom[rom_bank_map[offset / 0x8000] * 0x8000 + (offset & 0x7fff)];
1025	1025	}
1026
	1026
1027	1027	return 0xff;
1028	1028	}
1029	1029
1030	1030	READ8_MEMBER(sns_rom_spc7110_device::read_h)
1031	1031	{
1032	1032	UINT16 address = offset & 0xfffff;
1033
	1033
1034	1034	if (offset < 0x400000)
1035	1035	{
1036	1036	if (address >= 0x6000 && address < 0x8000)
r21591	r21592
1074	1074	UINT8 *ROM = get_rom_base();
1075	1075	UINT32 len = get_rom_size();
1076	1076	UINT16 addr = offset & 0xffff;
1077
	1077
1078	1078	switch (addr)
1079	1079	{
1080	1080	//==================
1081	1081	//decompression unit
1082	1082	//==================
1083
	1083
1084	1084	case 0x4800:
1085	1085	{
1086	1086	UINT16 counter = (m_r4809 + (m_r480a << 8));
r21591	r21592
1106	1106	m_r480c &= 0x7f;
1107	1107	return status;
1108	1108	}
1109
	1109
1110	1110	//==============
1111	1111	//data port unit
1112	1112	//==============
1113
	1113
1114	1114	case 0x4810:
1115	1115	{
1116	1116	UINT8 data;
1117	1117	UINT32 address, adjust, adjustaddr;
1118
	1118
1119	1119	if (m_r481x != 0x07) return 0x00;
1120
	1120
1121	1121	address = spc7110_data_pointer();
1122	1122	adjust = spc7110_data_adjust();
1123	1123	if (m_r4818 & 8)
1124	1124	{
1125	1125	adjust = (INT16)adjust; //16-bit sign extend
1126	1126	}
1127
	1127
1128	1128	adjustaddr = address;
1129	1129	if (m_r4818 & 2)
1130	1130	{
1131	1131	adjustaddr += adjust;
1132	1132	spc7110_set_data_adjust(adjust + 1);
1133	1133	}
1134
	1134
1135	1135	data = ROM[spc7110_datarom_addr(adjustaddr, len)];
1136	1136	if (!(m_r4818 & 2))
1137	1137	{
r21591	r21592
1140	1140	{
1141	1141	increment = (INT16)increment; //16-bit sign extend
1142	1142	}
1143
	1143
1144	1144	if ((m_r4818 & 16) == 0)
1145	1145	{
1146	1146	spc7110_set_data_pointer(address + increment);
r21591	r21592
1150	1150	spc7110_set_data_adjust(adjust + increment);
1151	1151	}
1152	1152	}
1153
	1153
1154	1154	return data;
1155	1155	}
1156	1156	case 0x4811: return m_r4811;
r21591	r21592
1169	1169	{
1170	1170	return 0x00;
1171	1171	}
1172
	1172
1173	1173	address = spc7110_data_pointer();
1174	1174	adjust = spc7110_data_adjust();
1175	1175	if (m_r4818 & 8)
1176	1176	{
1177	1177	adjust = (INT16)adjust; //16-bit sign extend
1178	1178	}
1179
	1179
1180	1180	data = ROM[spc7110_datarom_addr(address + adjust, len)];
1181	1181	if ((m_r4818 & 0x60) == 0x60)
1182	1182	{
r21591	r21592
1189	1189	spc7110_set_data_adjust(adjust + adjust);
1190	1190	}
1191	1191	}
1192
	1192
1193	1193	return data;
1194	1194	}
1195
	1195
1196	1196	//=========
1197	1197	//math unit
1198	1198	//=========
1199
	1199
1200	1200	case 0x4820: return m_r4820;
1201	1201	case 0x4821: return m_r4821;
1202	1202	case 0x4822: return m_r4822;
r21591	r21592
1218	1218	m_r482f &= 0x7f;
1219	1219	return status;
1220	1220	}
1221
	1221
1222	1222	//===================
1223	1223	//memory mapping unit
1224	1224	//===================
1225
	1225
1226	1226	case 0x4830: return m_r4830;
1227	1227	case 0x4831: return m_r4831;
1228	1228	case 0x4832: return m_r4832;
1229	1229	case 0x4833: return m_r4833;
1230	1230	case 0x4834: return m_r4834;
1231
	1231
1232	1232	//====================
1233	1233	//real-time clock unit
1234	1234	//====================
r21591	r21592
1238	1238	UINT8 data = 0;
1239	1239	if (m_rtc_state == RTCS_Inactive \|\| m_rtc_state == RTCS_ModeSelect)
1240	1240	return 0x00;
1241
	1241
1242	1242	m_r4842 = 0x80;
1243	1243	data = m_rtc_ram[m_rtc_index];
1244	1244	m_rtc_index = (m_rtc_index + 1) & 15;
r21591	r21592
1260	1260	UINT8 *ROM = get_rom_base();
1261	1261	UINT32 len = get_rom_size();
1262	1262	UINT16 addr = offset & 0xffff;
1263
	1263
1264	1264	switch (addr)
1265	1265	{
1266	1266	//==================
1267	1267	//decompression unit
1268	1268	//==================
1269
	1269
1270	1270	case 0x4801: m_r4801 = data; break;
1271	1271	case 0x4802: m_r4802 = data; break;
1272	1272	case 0x4803: m_r4803 = data; break;
r21591	r21592
1276	1276	{
1277	1277	UINT32 table, index, address, mode, offset;
1278	1278	m_r4806 = data;
1279
	1279
1280	1280	table = (m_r4801 + (m_r4802 << 8) + (m_r4803 << 16));
1281	1281	index = (m_r4804 << 2);
1282	1282	//length = (m_r4809 + (m_r480a << 8));
r21591	r21592
1285	1285	offset = (ROM[address + 1] << 16)
1286	1286	+ (ROM[address + 2] << 8)
1287	1287	+ (ROM[address + 3] << 0);
1288
	1288
1289	1289	m_decomp->init(machine(), ROM, len, mode, offset, (m_r4805 + (m_r4806 << 8)) << mode);
1290	1290	m_r480c = 0x80;
1291	1291	}
1292	1292	break;
1293
	1293
1294	1294	case 0x4807: m_r4807 = data; break;
1295	1295	case 0x4808: m_r4808 = data; break;
1296	1296	case 0x4809: m_r4809 = data; break;
1297	1297	case 0x480a: m_r480a = data; break;
1298	1298	case 0x480b: m_r480b = data; break;
1299
	1299
1300	1300	//==============
1301	1301	//data port unit
1302	1302	//==============
1303
	1303
1304	1304	case 0x4811: m_r4811 = data; m_r481x \|= 0x01; break;
1305	1305	case 0x4812: m_r4812 = data; m_r481x \|= 0x02; break;
1306	1306	case 0x4813: m_r4813 = data; m_r481x \|= 0x04; break;
r21591	r21592
1320	1320	{
1321	1321	break;
1322	1322	}
1323
	1323
1324	1324	if ((m_r4818 & 0x60) == 0x20)
1325	1325	{
1326	1326	UINT32 increment = spc7110_data_adjust() & 0xff;
r21591	r21592
1341	1341	}
1342	1342	break;
1343	1343	}
1344
	1344
1345	1345	case 0x4815:
1346	1346	{
1347	1347	m_r4815 = data;
r21591	r21592
1358	1358	{
1359	1359	break;
1360	1360	}
1361
	1361
1362	1362	if ((m_r4818 & 0x60) == 0x20)
1363	1363	{
1364	1364	UINT32 increment = spc7110_data_adjust() & 0xff;
r21591	r21592
1379	1379	}
1380	1380	break;
1381	1381	}
1382
	1382
1383	1383	case 0x4816: m_r4816 = data; break;
1384	1384	case 0x4817: m_r4817 = data; break;
1385	1385	case 0x4818:
1386	1386	{
1387	1387	if (m_r481x != 0x07)
1388	1388	break;
1389
	1389
1390	1390	m_r4818 = data;
1391	1391	m_r4814_latch = m_r4815_latch = 0;
1392	1392	break;
1393	1393	}
1394
	1394
1395	1395	//=========
1396	1396	//math unit
1397	1397	//=========
1398
	1398
1399	1399	case 0x4820: m_r4820 = data; break;
1400	1400	case 0x4821: m_r4821 = data; break;
1401	1401	case 0x4822: m_r4822 = data; break;
r21591	r21592
1404	1404	case 0x4825:
1405	1405	{
1406	1406	m_r4825 = data;
1407
	1407
1408	1408	if (m_r482e & 1)
1409	1409	{
1410	1410	//signed 16-bit x 16-bit multiplication
1411	1411	INT16 r0 = (INT16)(m_r4824 + (m_r4825 << 8));
1412	1412	INT16 r1 = (INT16)(m_r4820 + (m_r4821 << 8));
1413
	1413
1414	1414	INT32 result = r0 * r1;
1415	1415	m_r4828 = result;
1416	1416	m_r4829 = result >> 8;
r21591	r21592
1422	1422	//unsigned 16-bit x 16-bit multiplication
1423	1423	UINT16 r0 = (UINT16)(m_r4824 + (m_r4825 << 8));
1424	1424	UINT16 r1 = (UINT16)(m_r4820 + (m_r4821 << 8));
1425
	1425
1426	1426	UINT32 result = r0 * r1;
1427	1427	m_r4828 = result;
1428	1428	m_r4829 = result >> 8;
1429	1429	m_r482a = result >> 16;
1430	1430	m_r482b = result >> 24;
1431	1431	}
1432
	1432
1433	1433	m_r482f = 0x80;
1434	1434	break;
1435	1435	}
1436
	1436
1437	1437	case 0x4826: m_r4826 = data; break;
1438	1438	case 0x4827:
1439	1439	{
1440	1440	m_r4827 = data;
1441
	1441
1442	1442	if (m_r482e & 1)
1443	1443	{
1444	1444	//signed 32-bit x 16-bit division
1445	1445	INT32 dividend = (INT32)(m_r4820 + (m_r4821 << 8) + (m_r4822 << 16) + (m_r4823 << 24));
1446	1446	INT16 divisor = (INT16)(m_r4826 + (m_r4827 << 8));
1447
	1447
1448	1448	INT32 quotient;
1449	1449	INT16 remainder;
1450
	1450
1451	1451	if (divisor)
1452	1452	{
1453	1453	quotient = (INT32)(dividend / divisor);
r21591	r21592
1459	1459	quotient = 0;
1460	1460	remainder = dividend & 0xffff;
1461	1461	}
1462
	1462
1463	1463	m_r4828 = quotient;
1464	1464	m_r4829 = quotient >> 8;
1465	1465	m_r482a = quotient >> 16;
1466	1466	m_r482b = quotient >> 24;
1467
	1467
1468	1468	m_r482c = remainder;
1469	1469	m_r482d = remainder >> 8;
1470	1470	}
r21591	r21592
1473	1473	//unsigned 32-bit x 16-bit division
1474	1474	UINT32 dividend = (UINT32)(m_r4820 + (m_r4821 << 8) + (m_r4822 << 16) + (m_r4823 << 24));
1475	1475	UINT16 divisor = (UINT16)(m_r4826 + (m_r4827 << 8));
1476
	1476
1477	1477	UINT32 quotient;
1478	1478	UINT16 remainder;
1479
	1479
1480	1480	if (divisor)
1481	1481	{
1482	1482	quotient = (UINT32)(dividend / divisor);
r21591	r21592
1488	1488	quotient = 0;
1489	1489	remainder = dividend & 0xffff;
1490	1490	}
1491
	1491
1492	1492	m_r4828 = quotient;
1493	1493	m_r4829 = quotient >> 8;
1494	1494	m_r482a = quotient >> 16;
1495	1495	m_r482b = quotient >> 24;
1496
	1496
1497	1497	m_r482c = remainder;
1498	1498	m_r482d = remainder >> 8;
1499	1499	}
1500
	1500
1501	1501	m_r482f = 0x80;
1502	1502	break;
1503	1503	}
1504
	1504
1505	1505	case 0x482e:
1506	1506	{
1507	1507	//reset math unit
r21591	r21592
1509	1509	m_r4824 = m_r4825 = m_r4826 = m_r4827 = 0;
1510	1510	m_r4828 = m_r4829 = m_r482a = m_r482b = 0;
1511	1511	m_r482c = m_r482d = 0;
1512
	1512
1513	1513	m_r482e = data;
1514	1514	break;
1515	1515	}
1516
	1516
1517	1517	//===================
1518	1518	//memory mapping unit
1519	1519	//===================
1520
	1520
1521	1521	case 0x4830: m_r4830 = data; break;
1522
	1522
1523	1523	case 0x4831:
1524	1524	{
1525	1525	m_r4831 = data;
1526	1526	m_dx_offset = spc7110_datarom_addr(data * 0x100000, len);
1527	1527	break;
1528	1528	}
1529
	1529
1530	1530	case 0x4832:
1531	1531	{
1532	1532	m_r4832 = data;
1533	1533	m_ex_offset = spc7110_datarom_addr(data * 0x100000, len);
1534	1534	break;
1535	1535	}
1536
	1536
1537	1537	case 0x4833:
1538	1538	{
1539	1539	m_r4833 = data;
1540	1540	m_fx_offset = spc7110_datarom_addr(data * 0x100000, len);
1541	1541	break;
1542	1542	}
1543
	1543
1544	1544	case 0x4834: m_r4834 = data; break;
1545
	1545
1546	1546	//====================
1547	1547	//real-time clock unit
1548	1548	//====================
1549
	1549
1550	1550	case 0x4840:
1551	1551	{
1552	1552	m_r4840 = data;
1553
	1553
1554	1554	if (!(m_r4840 & 1))
1555	1555	{
1556	1556	//disable RTC
r21591	r21592
1565	1565	}
1566	1566	}
1567	1567	break;
1568
	1568
1569	1569	case 0x4841:
1570	1570	{
1571	1571	m_r4841 = data;
1572
	1572
1573	1573	switch (m_rtc_state)
1574	1574	{
1575	1575	case RTCS_ModeSelect:
r21591	r21592
1581	1581	m_rtc_index = 0;
1582	1582	}
1583	1583	break;
1584
	1584
1585	1585	case RTCS_IndexSelect:
1586	1586	m_r4842 = 0x80;
1587	1587	m_rtc_index = data & 15;
1588	1588	if (m_rtc_mode == RTCM_Linear)
1589	1589	m_rtc_state = RTCS_Write;
1590	1590	break;
1591
	1591
1592	1592	case RTCS_Write:
1593	1593	m_r4842 = 0x80;
1594
	1594
1595	1595	//control register 0
1596	1596	if (m_rtc_index == 13)
1597	1597	{
1598	1598	//increment second counter
1599	1599	if (data & 2)
1600	1600	spc7110_update_time(1);
1601
	1601
1602	1602	//round minute counter
1603	1603	if (data & 8)
1604	1604	{
1605	1605	spc7110_update_time(0);
1606
	1606
1607	1607	UINT8 second = m_rtc_ram[0] + m_rtc_ram[1] * 10;
1608	1608	//clear seconds
1609	1609	m_rtc_ram[0] = 0;
1610	1610	m_rtc_ram[1] = 0;
1611
	1611
1612	1612	if (second >= 30)
1613	1613	spc7110_update_time(60);
1614	1614	}
1615	1615	}
1616
	1616
1617	1617	//control register 2
1618	1618	if (m_rtc_index == 15)
1619	1619	{
r21591	r21592
1621	1621	if ((data & 1) && !(m_rtc_ram[15] & 1))
1622	1622	{
1623	1623	spc7110_update_time(0);
1624
	1624
1625	1625	//clear seconds
1626	1626	m_rtc_ram[0] = 0;
1627	1627	m_rtc_ram[1] = 0;
1628	1628	}
1629
	1629
1630	1630	//disable timer
1631	1631	if ((data & 2) && !(m_rtc_ram[15] & 2))
1632	1632	spc7110_update_time(0);
1633	1633	}
1634
	1634
1635	1635	m_rtc_ram[m_rtc_index] = data & 15;
1636	1636	m_rtc_index = (m_rtc_index + 1) & 15;
1637	1637	break;
r21591	r21592
1640	1640	break;
1641	1641	}
1642	1642	}
1643

trunk/src/mess/machine/sns_spc7110.h
r21591	r21592
23	23	{
24	24	public:
25	25	SPC7110_Decomp(running_machine &machine);
26
	26
27	27	running_machine &machine() const { return m_machine; }
28
	28
29	29	void init(running_machine &machine, UINT8 *ROM, UINT32 len, UINT32 mode, UINT32 offset, UINT32 index);
30	30	void reset();
31
	31
32	32	UINT8 read(UINT8 *ROM, UINT32 len);
33	33	void write(UINT8 data);
34	34	void mode0(UINT8 init, UINT8 *ROM, UINT32 len);
35	35	void mode1(UINT8 init, UINT8 *ROM, UINT32 len);
36	36	void mode2(UINT8 init, UINT8 *ROM, UINT32 len);
37
	37
38	38	UINT8 dataread(UINT8 *ROM, UINT32 len);
39	39	UINT8 probability(UINT32 n);
40	40	UINT8 next_lps(UINT32 n);
r21591	r21592
42	42	UINT8 toggle_invert(UINT32 n);
43	43	UINT32 morton_2x8(UINT32 data);
44	44	UINT32 morton_4x8(UINT32 data);
45
	45
46	46	UINT32 m_decomp_mode;
47	47	UINT32 m_decomp_offset;
48
	48
49	49	UINT8 *m_decomp_buffer;
50	50	UINT32 m_decomp_buffer_rdoffset;
51	51	UINT32 m_decomp_buffer_wroffset;
52	52	UINT32 m_decomp_buffer_length;
53
	53
54	54	struct ContextState
55	55	{
56	56	UINT8 index;
57	57	UINT8 invert;
58	58	} m_context[32];
59
	59
60	60	UINT32 m_morton16[2][256];
61	61	UINT32 m_morton32[4][256];
62
63
	62
	63
64	64	private:
65	65	running_machine& m_machine;
66	66	UINT32 m_rom_size;
r21591	r21592
74	74	// construction/destruction
75	75	sns_rom_spc7110_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock);
76	76	sns_rom_spc7110_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
77
	77
78	78	// device-level overrides
79	79	virtual void device_start();
80	80	virtual void device_config_complete() { m_shortname = "sns_rom_spc7110"; }
r21591	r21592
95	95	void spc7110_set_data_pointer(UINT32 addr);
96	96	void spc7110_set_data_adjust(UINT32 addr);
97	97	void spc7110_update_time(UINT8 offset);
98
99	98
	99
100	100	//==================
101	101	//decompression unit
102	102	//==================
r21591	r21592
112	112	UINT8 m_r480a; // compression length high
113	113	UINT8 m_r480b; // decompression control register
114	114	UINT8 m_r480c; // decompression status
115
	115
116	116	SPC7110_Decomp* m_decomp;
117
	117
118	118	UINT8 m_r4811; // data pointer low
119	119	UINT8 m_r4812; // data pointer high
120	120	UINT8 m_r4813; // data pointer bank
r21591	r21592
123	123	UINT8 m_r4816; // data increment low
124	124	UINT8 m_r4817; // data increment high
125	125	UINT8 m_r4818; // data port control register
126
	126
127	127	UINT8 m_r481x;
128
	128
129	129	UINT8 m_r4814_latch;
130	130	UINT8 m_r4815_latch;
131
	131
132	132	//=========
133	133	//math unit
134	134	//=========
r21591	r21592
148	148	UINT8 m_r482d; // 16-bit remainder B1
149	149	UINT8 m_r482e; // math control register
150	150	UINT8 m_r482f; // math status
151
	151
152	152	//===================
153	153	//memory mapping unit
154	154	//===================
r21591	r21592
157	157	UINT8 m_r4832; // $[e0-ef]:[0000-ffff] mapping
158	158	UINT8 m_r4833; // $[f0-ff]:[0000-ffff] mapping
159	159	UINT8 m_r4834; // ???
160
	160
161	161	UINT32 m_dx_offset;
162	162	UINT32 m_ex_offset;
163	163	UINT32 m_fx_offset;
164
	164
165	165	//====================
166	166	//real-time clock unit
167	167	//====================
168	168	UINT8 m_r4840; // RTC latch
169	169	UINT8 m_r4841; // RTC index/data port
170	170	UINT8 m_r4842; // RTC status
171
	171
172	172	UINT32 m_rtc_state;
173	173	UINT32 m_rtc_mode;
174	174	UINT32 m_rtc_index;
175
	175
176	176	UINT64 m_rtc_offset;
177	177
178	178	//this is now allocated in the main snes cart class, to allow saving to nvram
179	179	//UINT8 m_rtc_ram[16]; // 0-12 secs, min, hrs, etc.; 13-14-15 control registers
180
	180
181	181	UINT8 m_ram[0x2000];
182	182	};
183	183
r21591	r21592
188	188	public:
189	189	// construction/destruction
190	190	sns_rom_spc7110rtc_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
191
	191
192	192	// device-level overrides
193	193	virtual void device_start();
194	194	virtual void device_config_complete() { m_shortname = "sns_rom_spc7110rtc"; }
195
	195
196	196	// reading and writing
197	197
198	198	// we just use the spc7110 ones for the moment, pending the split of regs 0x4840-0x4842 (RTC) from the base add-on
199		// virtual DECLARE_READ8_MEMBER(read_l);
200		// virtual DECLARE_READ8_MEMBER(read_h);
201		// virtual DECLARE_WRITE8_MEMBER(write_l);
202
203		// virtual DECLARE_READ8_MEMBER(chip_read);
204		// virtual DECLARE_WRITE8_MEMBER(chip_write);
	199	// virtual DECLARE_READ8_MEMBER(read_l);
	200	// virtual DECLARE_READ8_MEMBER(read_h);
	201	// virtual DECLARE_WRITE8_MEMBER(write_l);
	202
	203	// virtual DECLARE_READ8_MEMBER(chip_read);
	204	// virtual DECLARE_WRITE8_MEMBER(chip_write);
205	205	};
206
	206
207	207	// device type definition
208	208	extern const device_type SNS_HIROM_SPC7110;
209	209	extern const device_type SNS_HIROM_SPC7110_RTC;

trunk/src/mess/machine/sns_sufami.c
r21591	r21592
1	1	/***********************************************************************************************************
2
	2
3	3	Bandai Sufami Turbo cartridge emulation (for SNES/SFC)
4
	4
5	5	Copyright MESS Team.
6	6	Visit http://mamedev.org for licensing and usage restrictions.
7
	7
8	8	This is basically a standard LoROM cart with two slots for ST minicarts
9	9	The content of each slot (with ROM and RAM) is mapped to a separate memory range
10	10	Slot 1: ROM [20-3f][8000-ffff], RAM [60-63][8000-ffff]
11	11	Slot 2: ROM [40-5f][8000-ffff], RAM [70-73][8000-ffff]
12
	12
13	13	***********************************************************************************************************/
14	14
15	15
r21591	r21592
81	81
82	82	READ8_MEMBER(sns_rom_sufami_device::read_h)
83	83	{
84		if (offset < 0x200000) // SUFAMI TURBO ROM
	84	if (offset < 0x200000) // SUFAMI TURBO ROM
85	85	{
86	86	int bank = offset / 0x10000;
87	87	return m_rom[rom_bank_map[bank] * 0x8000 + (offset & 0x7fff)];
88	88	}
89		if (offset >= 0x200000 && offset < 0x400000) // SLOT1 STROM
	89	if (offset >= 0x200000 && offset < 0x400000) // SLOT1 STROM
90	90	{
91	91	if (m_slot1->m_cart)
92	92	return m_slot1->m_cart->read_l(space, offset - 0x200000);
93	93	}
94		if (offset >= 0x400000 && offset < 0x600000) // SLOT2 STROM
	94	if (offset >= 0x400000 && offset < 0x600000) // SLOT2 STROM
95	95	{
96	96	if (m_slot2->m_cart)
97	97	return m_slot2->m_cart->read_l(space, offset - 0x400000);
98	98	}
99		if (offset >= 0x600000 && offset < 0x640000) // SLOT1 RAM
	99	if (offset >= 0x600000 && offset < 0x640000) // SLOT1 RAM
100	100	{
101	101	if (m_slot1->m_cart && (offset & 0xffff) > 0x8000)
102	102	return m_slot1->m_cart->read_h(space, offset - 0x600000);
103	103	}
104		if (offset >= 0x700000 && offset < 0x740000) // SLOT2 RAM
	104	if (offset >= 0x700000 && offset < 0x740000) // SLOT2 RAM
105	105	{
106	106	if (m_slot2->m_cart && (offset & 0xffff) > 0x8000)
107	107	return m_slot2->m_cart->read_h(space, offset - 0x700000);
108	108	}
109
	109
110	110	return 0xff;
111	111	}
112	112
r21591	r21592
117	117
118	118	WRITE8_MEMBER(sns_rom_sufami_device::write_h)
119	119	{
120		if (offset >= 0x600000 && offset < 0x640000) // SLOT1 RAM
	120	if (offset >= 0x600000 && offset < 0x640000) // SLOT1 RAM
121	121	{
122	122	if (m_slot1->m_cart && (offset & 0xffff) > 0x8000)
123	123	return m_slot1->m_cart->write_h(space, offset - 0x600000, data);
124	124	}
125
126		if (offset >= 0x700000 && offset < 0x740000) // SLOT2 RAM
	125
	126	if (offset >= 0x700000 && offset < 0x740000) // SLOT2 RAM
127	127	{
128	128	if (m_slot2->m_cart && (offset & 0xffff) > 0x8000)
129	129	return m_slot2->m_cart->write_h(space, offset - 0x700000, data);
130	130	}
131
	131
132	132	}
133	133
134	134	/*-------------------------------------------------
r21591	r21592
172	172	m_nvram[bank * 0x8000 + (offset & 0x7fff)] = data;
173	173	}
174	174	}
175
176

trunk/src/mess/machine/sns_sufami.h
r21591	r21592
12	12	public:
13	13	// construction/destruction
14	14	sns_rom_sufami_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
15
	15
16	16	// device-level overrides
17	17	virtual void device_start();
18	18	virtual void device_config_complete() { m_shortname = "sns_rom_sufami"; }
19	19	virtual machine_config_constructor device_mconfig_additions() const;
20
	20
21	21	// additional reading and writing
22	22	virtual DECLARE_READ8_MEMBER(read_l);
23	23	virtual DECLARE_READ8_MEMBER(read_h);
r21591	r21592
36	36	public:
37	37	// construction/destruction
38	38	sns_rom_strom_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
39
	39
40	40	// device-level overrides
41	41	virtual void device_start();
42	42	virtual void device_config_complete() { m_shortname = "sns_strom"; }
43
	43
44	44	// additional reading and writing
45		virtual DECLARE_READ8_MEMBER(read_l); // used for ROM
46		virtual DECLARE_READ8_MEMBER(read_h); // used for ROM
47		virtual DECLARE_WRITE8_MEMBER(write_l); // used for RAM
48		virtual DECLARE_WRITE8_MEMBER(write_h); // used for RAM
	45	virtual DECLARE_READ8_MEMBER(read_l); // used for ROM
	46	virtual DECLARE_READ8_MEMBER(read_h); // used for ROM
	47	virtual DECLARE_WRITE8_MEMBER(write_l); // used for RAM
	48	virtual DECLARE_WRITE8_MEMBER(write_h); // used for RAM
49	49	};
50	50
51	51

trunk/src/mess/machine/sns_sdd1.c
r21591	r21592
1	1	/***********************************************************************************************************
2
	2
3	3	S-DD1 add-on chip emulation (for SNES/SFC)
4
	4
5	5	Based on Andreas Naive Public Domain code.
6	6	Code ported by MooglyGuy and updated to slots by Fabio Priuli.
7
	7
8	8	Copyright MESS Team.
9	9	Visit http://mamedev.org for licensing and usage restrictions.
10
	10
11	11	***********************************************************************************************************/
12	12
13	13
r21591	r21592
30	30	UINT8 SDD1__IM::IM_getCodeword(UINT8 ROM, UINT32 mmc, const UINT8 code_len)
31	31	{
32	32	UINT8 codeword = ROM[SSD1_ADD(m_byte_ptr)] << m_bit_count;
33
	33
34	34	++m_bit_count;
35
	35
36	36	if (codeword & 0x80)
37	37	{
38	38	codeword \|= ROM[SSD1_ADD((m_byte_ptr + 1))] >> (9 - m_bit_count);
39	39	m_bit_count += code_len;
40	40	}
41
	41
42	42	if (m_bit_count & 0x08)
43	43	{
44	44	m_byte_ptr++;
45	45	m_bit_count &= 0x07;
46	46	}
47
	47
48	48	return codeword;
49	49	}
50	50
r21591	r21592
87	87	0x78, 0x38, 0x58, 0x18, 0x68, 0x28, 0x48, 0x08,
88	88	0x70, 0x30, 0x50, 0x10, 0x60, 0x20, 0x40, 0x00,
89	89	};
90
	90
91	91	UINT8 codeword = m_IM->IM_getCodeword(ROM, mmc, code_num);
92
	92
93	93	if (codeword & 0x80)
94	94	{
95	95	*LPSind = 1;
r21591	r21592
112	112	UINT8 SDD1__BG::BG_getBit(UINT8 ROM, UINT32 mmc, UINT8* endOfRun)
113	113	{
114	114	UINT8 bit;
115
	115
116	116	if (!(m_MPScount \|\| m_LPSind))
117	117	{
118	118	m_GCD->GCD_getRunCount(ROM, mmc, m_code_num, &(m_MPScount), &(m_LPSind));
119	119	}
120
	120
121	121	if (m_MPScount)
122	122	{
123	123	bit = 0;
r21591	r21592
128	128	bit = 1;
129	129	m_LPSind = 0;
130	130	}
131
	131
132	132	if (m_MPScount \|\| m_LPSind)
133	133	{
134	134	(*endOfRun) = 0;
r21591	r21592
137	137	{
138	138	(*endOfRun) = 1;
139	139	}
140
	140
141	141	return bit;
142	142	}
143	143
r21591	r21592
200	200	{
201	201	UINT8 endOfRun;
202	202	UINT8 bit;
203
	203
204	204	SDD1__PEM_ContextInfo *pContInfo = &(m_contextInfo)[context];
205	205	UINT8 currStatus = pContInfo->status;
206	206	const SDD1__PEM_state* pState = &(PEM_evolution_table[currStatus]);
207	207	UINT8 currentMPS = pContInfo->MPS;
208
	208
209	209	bit = m_BG[pState->code_num]->BG_getBit(ROM, mmc, &endOfRun);
210
	210
211	211	if (endOfRun)
212	212	{
213	213	if (bit)
r21591	r21592
223	223	pContInfo->status = pState->nextIfMPS;
224	224	}
225	225	}
226
	226
227	227	return bit ^ currentMPS;
228	228	}
229	229
r21591	r21592
258	258	UINT8 currContext;
259	259	UINT16 *context_bits;
260	260	UINT8 bit = 0;
261
	261
262	262	switch (m_bitplanesInfo)
263	263	{
264	264	case 0x00:
r21591	r21592
278	278	m_currBitplane = m_bit_number & 0x07;
279	279	break;
280	280	}
281
	281
282	282	context_bits = &(m_prevBitplaneBits)[m_currBitplane];
283
	283
284	284	currContext = (m_currBitplane & 0x01) << 4;
285	285	switch (m_contextBitsInfo)
286	286	{
r21591	r21592
297	297	currContext \|= ((context_bits & 0x0180) >> 5) \| (context_bits & 0x0003);
298	298	break;
299	299	}
300
	300
301	301	bit = m_PEM->PEM_getBit(ROM, mmc, currContext);
302
	302
303	303	*context_bits <<= 1;
304	304	*context_bits \|= bit;
305
	305
306	306	m_bit_number++;
307
	307
308	308	return bit;
309	309	}
310	310
r21591	r21592
321	321	{
322	322	UINT8 i;
323	323	UINT8 register1 = 0, register2 = 0;
324
	324
325	325	switch (m_bitplanesInfo)
326	326	{
327	327	case 0x00:
r21591	r21592
341	341	{
342	342	if (m_CM->CM_getBit(ROM, mmc))
343	343	register1 \|= i;
344
	344
345	345	if (m_CM->CM_getBit(ROM, mmc))
346	346	register2 \|= i;
347	347	}
r21591	r21592
381	381	m_BG6 = auto_alloc(machine, SDD1__BG(m_GCD, 6));
382	382	m_BG7 = auto_alloc(machine, SDD1__BG(m_GCD, 7));
383	383	m_PEM = auto_alloc(machine, SDD1__PEM(m_BG0, m_BG1, m_BG2, m_BG3,
384		m_BG4, m_BG5, m_BG6, m_BG7));
	384	m_BG4, m_BG5, m_BG6, m_BG7));
385	385	m_CM = auto_alloc(machine, SDD1__CM(m_PEM));
386	386	m_OL = auto_alloc(machine, SDD1__OL(m_CM));
387	387	}
r21591	r21592
400	400	m_PEM->PEM_prepareDecomp();
401	401	m_CM->CM_prepareDecomp(ROM, mmc, in_buf);
402	402	m_OL->OL_prepareDecomp(ROM, mmc, in_buf, out_len, out_buf);
403
	403
404	404	m_OL->OL_launch(ROM, mmc);
405	405	}
406	406
r21591	r21592
428	428	void sns_rom_sdd1_device::device_start()
429	429	{
430	430	UINT8 i;
431
	431
432	432	m_sdd1_enable = 0x00;
433	433	m_xfer_enable = 0x00;
434
	434
435	435	m_mmc[0] = 0 << 20;
436	436	m_mmc[1] = 1 << 20;
437	437	m_mmc[2] = 2 << 20;
438	438	m_mmc[3] = 3 << 20;
439
	439
440	440	for(i = 0; i < 8; i++)
441	441	{
442	442	m_dma[i].addr = 0;
443	443	m_dma[i].size = 0;
444	444	}
445
	445
446	446	m_sdd1emu = auto_alloc(machine(), SDD1__emu(machine()));
447
	447
448	448	m_buffer.data = (UINT8*)auto_alloc_array(machine(), UINT8, 0x10000);
449	449	m_buffer.ready = 0;
450	450
r21591	r21592
461	461	READ8_MEMBER( sns_rom_sdd1_device::chip_read )
462	462	{
463	463	UINT16 addr = offset & 0xffff;
464
	464
465	465	switch (addr)
466	466	{
467	467	case 0x4804:
r21591	r21592
473	473	case 0x4807:
474	474	return (m_mmc[3] >> 20) & 7;
475	475	}
476
477		// we should never get here, but...
	476
	477	// we should never get here, but...
478	478	return 0;
479	479	}
480	480
r21591	r21592
482	482	WRITE8_MEMBER( sns_rom_sdd1_device::chip_write )
483	483	{
484	484	UINT16 addr = offset & 0xffff;
485
	485
486	486	if ((addr & 0x4380) == 0x4300)
487	487	{
488	488	UINT8 channel = (addr >> 4) & 7;
r21591	r21592
507	507	}
508	508	return;
509	509	}
510
	510
511	511	switch(addr)
512	512	{
513	513	case 0x4800:
r21591	r21592
516	516	case 0x4801:
517	517	m_xfer_enable = data;
518	518	break;
519
	519
520	520	case 0x4804:
521	521	m_mmc[0] = (data & 7) << 20;
522	522	break;
r21591	r21592
530	530	m_mmc[3] = (data & 7) << 20;
531	531	break;
532	532	}
533
	533
534	534	}
535	535
536	536	UINT8 sns_rom_sdd1_device::read_helper(UINT32 addr)
r21591	r21592
552	552	// this really should stream byte-by-byte, but it's not necessary since the size is known
553	553	m_buffer.offset = 0;
554	554	m_buffer.size = m_dma[i].size ? m_dma[i].size : 65536;
555
	555
556	556	// SDD1_emu calls this function; it needs to access uncompressed data;
557	557	// so temporarily disable decompression mode for decompress() call.
558	558	m_sdd1emu->SDD1emu_decompress(m_rom, m_mmc, addr, m_buffer.size, m_buffer.data);
559
	559
560	560	m_buffer.ready = 1;
561	561	}
562
	562
563	563	// fetch a decompressed byte; once buffer is depleted, disable channel and invalidate buffer
564	564	data = m_buffer.data[(UINT16)m_buffer.offset++];
565	565	if (m_buffer.offset >= m_buffer.size)
r21591	r21592
567	567	m_buffer.ready = 0;
568	568	m_xfer_enable &= ~(1 << i);
569	569	}
570
	570
571	571	return data;
572	572	}
573	573	}
r21591	r21592
597	597
598	598	WRITE8_MEMBER(sns_rom_sdd1_device::write_l)
599	599	{
600		if (offset >= 0x700000 && (offset & 0xffff) < 0x8000 && m_nvram_size > 0) // SRAM
	600	if (offset >= 0x700000 && (offset & 0xffff) < 0x8000 && m_nvram_size > 0) // SRAM
601	601	m_nvram[offset & 0x1fff] = data;
602	602	}

trunk/src/mess/machine/sns_sdd1.h
r21591	r21592
9	9	{
10	10	public:
11	11	SDD1__IM() {}
12
	12
13	13	UINT32 m_byte_ptr;
14	14	UINT8 m_bit_count;
15
	15
16	16	void IM_prepareDecomp(UINT32 in_buf);
17	17	UINT8 IM_getCodeword(UINT8 ROM, UINT32 mmc, const UINT8 code_len);
18	18	};
r21591	r21592
22	22	public:
23	23	SDD1__GCD(SDD1__IM* associatedIM)
24	24	: m_IM(associatedIM) { }
25
	25
26	26	SDD1__IM* m_IM;
27
	27
28	28	void GCD_getRunCount(UINT8 ROM, UINT32 mmc, UINT8 code_num, UINT8* MPScount, UINT8* LPSind);
29	29	};
30	30
r21591	r21592
34	34	SDD1__BG(SDD1__GCD* associatedGCD, UINT8 code)
35	35	: m_code_num(code),
36	36	m_GCD(associatedGCD) { }
37
	37
38	38	UINT8 m_code_num;
39	39	UINT8 m_MPScount;
40	40	UINT8 m_LPSind;
41	41	SDD1__GCD* m_GCD;
42
	42
43	43	void BG_prepareDecomp();
44	44	UINT8 BG_getBit(UINT8 ROM, UINT32 mmc, UINT8* endOfRun);
45	45	} ;
r21591	r21592
54	54	{
55	55	public:
56	56	SDD1__PEM(
57		SDD1__BG* associatedBG0, SDD1__BG* associatedBG1,
58		SDD1__BG* associatedBG2, SDD1__BG* associatedBG3,
59		SDD1__BG* associatedBG4, SDD1__BG* associatedBG5,
60		SDD1__BG* associatedBG6, SDD1__BG* associatedBG7)
	57	SDD1__BG* associatedBG0, SDD1__BG* associatedBG1,
	58	SDD1__BG* associatedBG2, SDD1__BG* associatedBG3,
	59	SDD1__BG* associatedBG4, SDD1__BG* associatedBG5,
	60	SDD1__BG* associatedBG6, SDD1__BG* associatedBG7)
61	61	{
62	62	m_BG[0] = associatedBG0;
63	63	m_BG[1] = associatedBG1;
r21591	r21592
68	68	m_BG[6] = associatedBG6;
69	69	m_BG[7] = associatedBG7;
70	70	}
71
	71
72	72	SDD1__PEM_ContextInfo m_contextInfo[32];
73	73	SDD1__BG* m_BG[8];
74
	74
75	75	void PEM_prepareDecomp();
76	76	UINT8 PEM_getBit(UINT8 ROM, UINT32 mmc, UINT8 context);
77	77	} ;
r21591	r21592
82	82	public:
83	83	SDD1__CM(SDD1__PEM* associatedPEM)
84	84	: m_PEM(associatedPEM) { }
85
	85
86	86	UINT8 m_bitplanesInfo;
87	87	UINT8 m_contextBitsInfo;
88	88	UINT8 m_bit_number;
89	89	UINT8 m_currBitplane;
90	90	UINT16 m_prevBitplaneBits[8];
91	91	SDD1__PEM* m_PEM;
92
	92
93	93	void CM_prepareDecomp(UINT8 ROM, UINT32 mmc, UINT32 first_byte);
94	94	UINT8 CM_getBit(UINT8 ROM, UINT32 mmc);
95	95	} ;
r21591	r21592
100	100	public:
101	101	SDD1__OL(SDD1__CM* associatedCM)
102	102	: m_CM(associatedCM) { }
103
	103
104	104	UINT8 m_bitplanesInfo;
105	105	UINT16 m_length;
106	106	UINT8* m_buffer;
107	107	SDD1__CM* m_CM;
108
	108
109	109	void OL_prepareDecomp(UINT8 ROM, UINT32 mmc, UINT32 first_byte, UINT16 out_len, UINT8 *out_buf);
110	110	void OL_launch(UINT8 ROM, UINT32 mmc);
111	111	} ;
r21591	r21592
114	114	{
115	115	public:
116	116	SDD1__emu(running_machine &machine);
117
	117
118	118	running_machine &machine() const { return m_machine; }
119
	119
120	120	SDD1__IM* m_IM;
121	121	SDD1__GCD* m_GCD;
122	122	SDD1__BG* m_BG0; SDD1__BG* m_BG1; SDD1__BG* m_BG2; SDD1__BG* m_BG3;
r21591	r21592
124	124	SDD1__PEM* m_PEM;
125	125	SDD1__CM* m_CM;
126	126	SDD1__OL* m_OL;
127
	127
128	128	void SDD1emu_decompress(UINT8 ROM, UINT32 mmc, UINT32 in_buf, UINT16 out_len, UINT8 *out_buf);
129
	129
130	130	private:
131	131	running_machine& m_machine;
132	132	};
r21591	r21592
136	136	// ======================> sns_rom_sdd1_device
137	137
138	138	class sns_rom_sdd1_device : public device_t,
139		public device_sns_cart_interface
	139	public device_sns_cart_interface
140	140	{
141	141	public:
142	142	// construction/destruction
143	143	sns_rom_sdd1_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock);
144	144	sns_rom_sdd1_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
145
	145
146	146	// device-level overrides
147	147	virtual void device_start();
148	148	virtual void device_config_complete() { m_shortname = "sns_rom_sdd1"; }
r21591	r21592
159	159	UINT8 m_sdd1_enable; // channel bit-mask
160	160	UINT8 m_xfer_enable; // channel bit-mask
161	161	UINT32 m_mmc[4]; // memory map controller ROM indices
162
	162
163	163	struct
164	164	{
165	165	UINT32 addr; // $43x2-$43x4 -- DMA transfer address
166	166	UINT16 size; // $43x5-$43x6 -- DMA transfer size
167	167	} m_dma[8];
168
	168
169	169	SDD1__emu* m_sdd1emu;
170	170
171	171	struct

trunk/src/mess/machine/sns_rom21.c
r21591	r21592
1	1	/***********************************************************************************************************
2
	2
3	3	Super NES/Famicom (HiROM) cartridge emulation (for SNES/SFC)
4
	4
5	5	Copyright MESS Team.
6	6	Visit http://mamedev.org for licensing and usage restrictions.
7
	7
8	8	***********************************************************************************************************/
9	9
10	10
r21591	r21592
51	51	m_index = -1;
52	52
53	53	// at this stage, rtc_ram is not yet allocated. this will be fixed when converting RTC to be a separate device.
54		// update_time();
	54	// update_time();
55	55
56	56	save_item(NAME(m_mode));
57	57	save_item(NAME(m_index));
r21591	r21592
66	66	READ8_MEMBER(sns_rom21_device::read_l)
67	67	{
68	68	UINT16 address = offset & 0xffff;
69
	69
70	70	if (offset >= 0x300000 && offset < 0x400000 && address < 0x8000)
71	71	{
72	72	if (m_nvram_size > 0)
r21591	r21592
77	77	return m_nvram[(offset - 0x6000) & mask];
78	78	}
79	79	}
80
	80
81	81	// here ROM banks from 128 to 255, mirrored twice
82	82	int bank = (offset & 0x3fffff) / 0x8000;
83	83	return m_rom[rom_bank_map[bank + 0x80] * 0x8000 + (offset & 0x7fff)];
r21591	r21592
86	86	READ8_MEMBER(sns_rom21_device::read_h)
87	87	{
88	88	UINT16 address = offset & 0xffff;
89
	89
90	90	if (offset >= 0x300000 && offset < 0x400000 && address < 0x8000)
91	91	{
92	92	if (m_nvram_size > 0)
r21591	r21592
97	97	return m_nvram[(offset - 0x6000) & mask];
98	98	}
99	99	}
100
	100
101	101	// here ROM banks from 0 to 127, mirrored twice
102	102	int bank = (offset & 0x3fffff) / 0x8000;
103	103	return m_rom[rom_bank_map[bank] * 0x8000 + (offset & 0x7fff)];
r21591	r21592
111	111	WRITE8_MEMBER(sns_rom21_device::write_h)
112	112	{
113	113	UINT16 address = offset & 0xffff;
114
	114
115	115	if (offset >= 0x300000 && offset < 0x400000 && address < 0x8000)
116	116	{
117	117	if (m_nvram_size > 0)
r21591	r21592
127	127	// Hi-ROM + S-RTC (used by Daikaijuu Monogatari II)
128	128	// same as above but additional read/write handling for the RTC
129	129	/***************************************************************************
130
	130
131	131	Based on C++ implementation by Byuu in BSNES.
132
	132
133	133	Byuu's code is released under GNU General Public License
134	134	version 2 as published by the Free Software Foundation.
135
	135
136	136	The implementation below is released under the MAME license
137	137	for use in MAME, MESS and derivatives by permission of Byuu
138
	138
139	139	Copyright (for the implementation below) MESS Team.
140	140	Visit http://mamedev.org for licensing and usage restrictions.
141
	141
142	142	***************************************************************************/
143	143
144	144	static const UINT8 srtc_months[12] =
r21591	r21592
175	175	{
176	176	UINT32 y = 1900, m = 1; // Epoch is 1900-01-01
177	177	UINT32 sum = 0; // Number of days passed since epoch
178
	178
179	179	year = MAX(1900, year);
180	180	month = MAX(1, MIN(12, month));
181	181	day = MAX(1, MIN(31, day));
182
	182
183	183	while (y < year)
184	184	{
185	185	UINT8 leapyear = 0;
r21591	r21592
194	194	sum += leapyear ? 366 : 365;
195	195	y++;
196	196	}
197
	197
198	198	while (m < month)
199	199	{
200	200	UINT32 days = srtc_months[m - 1];
r21591	r21592
214	214	sum += days;
215	215	m++;
216	216	}
217
	217
218	218	sum += day - 1;
219	219	return (sum + 1) % 7; // 1900-01-01 was a Monday
220	220	}
221	221
222	222
223	223	// this gets called only for accesses at 0x2800,
224		// because for 0x2801 open bus gets returned...
	224	// because for 0x2801 open bus gets returned...
225	225	READ8_MEMBER(sns_rom21_srtc_device::chip_read)
226	226	{
227	227	if (m_mode != RTCM_Read)
228	228	return 0x00;
229
	229
230	230	if (m_index < 0)
231	231	{
232	232	update_time();
r21591	r21592
246	246	WRITE8_MEMBER(sns_rom21_srtc_device::chip_write)
247	247	{
248	248	data &= 0x0f; // Only the low four bits are used
249
	249
250	250	if (data == 0x0d)
251	251	{
252	252	m_mode = RTCM_Read;
253	253	m_index = -1;
254	254	return;
255	255	}
256
	256
257	257	if (data == 0x0e)
258	258	{
259	259	m_mode = RTCM_Command;
260	260	return;
261	261	}
262
	262
263	263	if (data == 0x0f)
264	264	return; // Unknown behaviour
265
	265
266	266	if (m_mode == RTCM_Write)
267	267	{
268	268	if (m_index >= 0 && m_index < 12)
269	269	{
270	270	m_rtc_ram[m_index++] = data;
271
	271
272	272	if (m_index == 12)
273	273	{
274	274	// Day of week is automatically calculated and written
r21591	r21592
276	276	UINT32 month = m_rtc_ram[8];
277	277	UINT32 year = m_rtc_ram[9] + m_rtc_ram[10] * 10 + m_rtc_ram[11] * 100;
278	278	year += 1000;
279
	279
280	280	m_rtc_ram[m_index++] = srtc_weekday(year, month, day);
281	281	}
282	282	}
r21591	r21592
303	303	}
304	304	}
305	305	}
306

trunk/src/mess/machine/sns_rom21.h
r21591	r21592
7	7	// ======================> sns_rom21_device
8	8
9	9	class sns_rom21_device : public device_t,
10		public device_sns_cart_interface
	10	public device_sns_cart_interface
11	11	{
12	12	public:
13	13	// construction/destruction
14	14	sns_rom21_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock);
15	15	sns_rom21_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
16
	16
17	17	// device-level overrides
18	18	virtual void device_start();
19	19	virtual void device_config_complete() { m_shortname = "sns_rom21"; }
r21591	r21592
32	32	public:
33	33	// construction/destruction
34	34	sns_rom21_srtc_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
35
	35
36	36	// device-level overrides
37	37	virtual void device_start();
38	38	virtual void device_config_complete() { m_shortname = "sns_rom21_srtc"; }
39
	39
40	40	// reading and writing
41	41	virtual DECLARE_READ8_MEMBER(chip_read);
42	42	virtual DECLARE_WRITE8_MEMBER(chip_write);
r21591	r21592
49	49	RTCM_Read,
50	50	RTCM_Write
51	51	};
52
	52
53	53	void update_time();
54	54	UINT8 srtc_weekday(UINT32 year, UINT32 month, UINT32 day);
55
	55
56	56	//this is now allocated in the main snes cart class, to allow saving to nvram
57	57	//UINT8 m_rtc_ram[13];
58	58	INT32 m_mode;

trunk/src/mess/machine/sns_slot.c
r21591	r21592
1	1	/***********************************************************************************************************
2
3	2
	3
4	4	SNES cart emulation
5	5	(through slot devices)
6	6
7	7
8
	8
9	9	***********************************************************************************************************/
10	10
11	11
r21591	r21592
96	96
97	97
98	98	//-------------------------------------------------
99		// addon_bios_alloc - alloc the space for the
	99	// addon_bios_alloc - alloc the space for the
100	100	// (optional) add-on CPU bios
101	101	//-------------------------------------------------
102	102
r21591	r21592
111	111
112	112
113	113	//-------------------------------------------------
114		// rom_map_setup - setup map of rom banks in 32K
	114	// rom_map_setup - setup map of rom banks in 32K
115	115	// blocks, so to simplify ROM access
116	116	//-------------------------------------------------
117	117
118	118	void device_sns_cart_interface::rom_map_setup(UINT32 size)
119	119	{
120	120	int i;
121		// setup the rom_bank_map array to faster ROM read
	121	// setup the rom_bank_map array to faster ROM read
122	122	for (i = 0; i < size / 0x8000; i++)
123	123	rom_bank_map[i] = i;
124
	124
125	125	// fill up remaining blocks with mirrors
126	126	while (i % 256)
127	127	{
r21591	r21592
135	135	}
136	136
137	137	// check bank map!
138		// for (i = 0; i < 256; i++)
139		// {
140		// printf("bank %3d = %3d\t", i, rom_bank_map[i]);
141		// if ((i%8) == 7)
142		// printf("\n");
143		// }
	138	// for (i = 0; i < 256; i++)
	139	// {
	140	// printf("bank %3d = %3d\t", i, rom_bank_map[i]);
	141	// if ((i%8) == 7)
	142	// printf("\n");
	143	// }
144	144	}
145	145
146	146	//**************************************************************************
r21591	r21592
244	244	{ SNES_STROM, "strom"},
245	245	// pirate carts
246	246	{ SNES_POKEMON, "lorom_poke"},
247		{ SNES_BANANA, "lorom_paja"}, // wip
248		{ SNES_SOULBLAD, "lorom_sbld"} // wip
	247	{ SNES_BANANA, "lorom_paja"}, // wip
	248	{ SNES_SOULBLAD, "lorom_sbld"} // wip
249	249	};
250	250
251	251	static int sns_get_pcb_id(const char *slot)
r21591	r21592
255	255	if (!mame_stricmp(slot_list[i].slot_option, slot))
256	256	return slot_list[i].pcb_id;
257	257	}
258
	258
259	259	return 0;
260	260	}
261	261
r21591	r21592
266	266	if (slot_list[i].pcb_id == type)
267	267	return slot_list[i].slot_option;
268	268	}
269
	269
270	270	return "lorom";
271	271	}
272	272
r21591	r21592
285	285	{
286	286	UINT8 header[512];
287	287	UINT32 offset = 512;
288
	288
289	289	/* Check for a header (512 bytes) */
290	290	memcpy(header, ROM, 512);
291
	291
292	292	if ((header[8] == 0xaa) && (header[9] == 0xbb) && (header[10] == 0x04))
293	293	{
294	294	/* Found an SWC identifier */
r21591	r21592
310	310	logerror("No header found.\n");
311	311	offset = 0;
312	312	}
313
	313
314	314	return offset;
315	315	}
316	316
r21591	r21592
326	326	UINT16 ichecksum = infoblock[offset + 0x1c] \| (infoblock[offset + 0x1d] << 8);
327	327	UINT8 reset_opcode = infoblock[(offset & ~0x7fff) \| (reset_vector & 0x7fff)]; //first opcode executed upon reset
328	328	UINT8 mapper = infoblock[offset + 0x15] & ~0x10; //mask off irrelevant FastROM-capable bit
329
	329
330	330	/* $00:[000-7fff] contains uninitialized RAM and MMIO.
331	331	reset vector must point to ROM at $00:[8000-ffff] to be considered valid. */
332	332	if (reset_vector < 0x8000)
333	333	return 0;
334
	334
335	335	/* some images duplicate the header in multiple locations, and others have completely
336	336	invalid header information that cannot be relied upon. The code below will analyze
337	337	the first opcode executed at the specified reset vector to determine the probability
338	338	that this is the correct header. Score is assigned accordingly. */
339
	339
340	340	/* most likely opcodes */
341	341	if (reset_opcode == 0x78 //sei
342	342	\|\| reset_opcode == 0x18 //clc (clc; xce)
r21591	r21592
346	346	\|\| reset_opcode == 0x5c //jml $nnnnnn
347	347	)
348	348	score += 8;
349
	349
350	350	/* plausible opcodes */
351	351	if (reset_opcode == 0xc2 //rep #$nn
352	352	\|\| reset_opcode == 0xe2 //sep #$nn
r21591	r21592
361	361	\|\| reset_opcode == 0x22 //jsl $nnnnnn
362	362	)
363	363	score += 4;
364
	364
365	365	/* implausible opcodes */
366	366	if (reset_opcode == 0x40 //rti
367	367	\|\| reset_opcode == 0x60 //rts
r21591	r21592
371	371	\|\| reset_opcode == 0xcc //cpy $nnnn
372	372	)
373	373	score -= 4;
374
	374
375	375	/* least likely opcodes */
376	376	if (reset_opcode == 0x00 //brk #$nn
377	377	\|\| reset_opcode == 0x02 //cop #$nn
r21591	r21592
380	380	\|\| reset_opcode == 0xff //sbc $nnnnnn,x
381	381	)
382	382	score -= 8;
383
	383
384	384	/* Sometimes, both the header and reset vector's first opcode will match ...
385	385	fallback and rely on info validity in these cases to determine more likely header. */
386
	386
387	387	/* a valid checksum is the biggest indicator of a valid header. */
388	388	if ((checksum + ichecksum) == 0xffff && (checksum != 0) && (ichecksum != 0))
389	389	score += 4;
390
	390
391	391	/* then there are the expected mapper values */
392	392	if (offset == 0x007fc0 && mapper == 0x20) // 0x20 is usually LoROM
393	393	score += 2;
394
	394
395	395	if (offset == 0x00ffc0 && mapper == 0x21) // 0x21 is usually HiROM
396	396	score += 2;
397
	397
398	398	if (offset == 0x007fc0 && mapper == 0x22) // 0x22 is usually ExLoROM
399	399	score += 2;
400
	400
401	401	if (offset == 0x40ffc0 && mapper == 0x25) // 0x25 is usually ExHiROM
402	402	score += 2;
403
	403
404	404	/* finally, there are valid values in the Company, Region etc. fields */
405	405	if (infoblock[offset + 0x1a] == 0x33) // Company field: 0x33 indicates extended header
406	406	score += 2;
407
	407
408	408	if (infoblock[offset + 0x16] < 0x08) // ROM Type field
409	409	score++;
410
	410
411	411	if (infoblock[offset + 0x17] < 0x10) // ROM Size field
412	412	score++;
413
	413
414	414	if (infoblock[offset + 0x18] < 0x08) // SRAM Size field
415	415	score++;
416
	416
417	417	if (infoblock[offset + 0x19] < 14) // Region field
418	418	score++;
419
	419
420	420	/* do we still have a positive score? */
421	421	if (score < 0)
422	422	score = 0;
423
	423
424	424	return score;
425	425	}
426	426
r21591	r21592
445	445	/* Images larger than 32mbits are likely ExHiRom */
446	446	if (valid_mode25)
447	447	valid_mode25 += 4;
448
	448
449	449	if ((valid_mode20 >= valid_mode21) && (valid_mode20 >= valid_mode25))
450		retvalue = 0x007fc0;
	450	retvalue = 0x007fc0;
451	451	else if (valid_mode21 >= valid_mode25)
452	452	retvalue = 0x00ffc0;
453	453	else
454	454	retvalue = 0x40ffc0;
455
	455
456	456	logerror( "\t HiROM/LoROM id: %s (LoROM: %d , HiROM: %d, ExHiROM: %d)\n",
457		(retvalue == 0x007fc0) ? "LoROM" :
458		(retvalue == 0x00ffc0) ? "HiROM" :
459		(retvalue == 0x40ffc0) ? "ExHiROM" : "Other",
460		valid_mode20, valid_mode21, valid_mode25);
461
	457	(retvalue == 0x007fc0) ? "LoROM" :
	458	(retvalue == 0x00ffc0) ? "HiROM" :
	459	(retvalue == 0x40ffc0) ? "ExHiROM" : "Other",
	460	valid_mode20, valid_mode21, valid_mode25);
	461
462	462	return retvalue;
463	463	}
464	464
r21591	r21592
472	472	case 0x01:
473	473	case 0x02:
474	474	break;
475
	475
476	476	case 0x03:
477	477	if (buffer[start_offs + 0x15] == 0x30)
478	478	return SNES_DSP4;
479	479	else
480	480	return SNES_DSP;
481
	481
482	482	case 0x04:
483	483	return SNES_DSP;
484
	484
485	485	case 0x05:
486	486	// DSP2 can be detected by (buffer[start_offs + 0x15] == 0x20)
487		// DSP3 is harder to detect, and one has to rely on the manufacturer (Bandai)
	487	// DSP3 is harder to detect, and one has to rely on the manufacturer (Bandai)
488	488	// by checking (buffer[start_offs + 0x15] == 0x30) && (buffer[start_offs + 0x1a] == 0xb2)
489	489	// in other cases is DSP1, but we do treat all these together...
490	490	return SNES_DSP;
491
	491
492	492	case 0x13: // Mario Chip 1
493	493	case 0x14: // GSU-x
494	494	case 0x15: // GSU-x
r21591	r21592
496	496	if (buffer[start_offs + 0x15] == 0x20)
497	497	return SNES_SFX;
498	498	break;
499
	499
500	500	case 0x25:
501	501	return SNES_OBC1;
502
	502
503	503	case 0x32: // needed by a Sample game (according to ZSNES)
504	504	case 0x34:
505	505	case 0x35:
506	506	if (buffer[start_offs + 0x15] == 0x23)
507	507	return SNES_SA1;
508	508	break;
509
	509
510	510	case 0x43:
511	511	case 0x45:
512	512	if (buffer[start_offs + 0x15] == 0x32)
513	513	return SNES_SDD1;
514	514	break;
515
	515
516	516	case 0x55:
517	517	if (buffer[start_offs + 0x15] == 0x35)
518	518	return SNES_SRTC;
519	519	break;
520
	520
521	521	case 0xe3:
522	522	return SNES_Z80GB;
523
	523
524	524	case 0xf3:
525	525	return SNES_CX4;
526
	526
527	527	case 0xf5:
528	528	if (buffer[start_offs + 0x15] == 0x30)
529	529	return SNES_ST018;
530	530	else if (buffer[start_offs + 0x15] == 0x3a)
531	531	return SNES_SPC7110;
532	532	break;
533
	533
534	534	case 0xf6:
535	535	/* These Seta ST-01X chips have both 0x30 at 0xffd5,
536	536	they only differ for the 'size' at 0xffd7 */
r21591	r21592
538	538	return SNES_ST011;
539	539	else
540	540	return SNES_ST010;
541
	541
542	542	case 0xf9:
543	543	if (buffer[start_offs + 0x15] == 0x3a)
544	544	return SNES_SPC7110_RTC;
545	545	break;
546
	546
547	547	default:
548	548	break;
549	549	}
r21591	r21592
585	585
586	586	m_cart->rom_map_setup(len);
587	587
588		// check for on-cart CPU bios
	588	// check for on-cart CPU bios
589	589	if (software_entry() != NULL)
590	590	{
591	591	if (get_software_region("addon"))
r21591	r21592
605	605	else
606	606	m_type = sns_get_pcb_id(slot_name);
607	607	}
608
609	608
	609
610	610	setup_custom_mappers();
611
	611
612	612	setup_nvram();
613	613
614	614	if (m_cart->get_nvram_size() \|\| m_cart->get_rtc_ram_size())
r21591	r21592
620	620	memcpy(m_cart->get_nvram_base(), temp_nvram, m_cart->get_nvram_size());
621	621	if (m_cart->get_rtc_ram_size())
622	622	memcpy(m_cart->get_rtc_ram_base(), temp_nvram + m_cart->get_nvram_size(), m_cart->get_rtc_ram_size());
623
	623
624	624	if (temp_nvram)
625	625	auto_free(machine(), temp_nvram);
626	626	}
627
	627
628	628	printf("Type %d\n", m_type);
629	629
630	630	internal_header_logging(ROM, len);
631	631
632	632	return IMAGE_INIT_PASS;
633	633	}
634
	634
635	635	return IMAGE_INIT_PASS;
636	636	}
637	637
r21591	r21592
652	652	memcpy(temp_nvram, m_cart->get_nvram_base(), m_cart->get_nvram_size());
653	653	if (m_cart->get_rtc_ram_size())
654	654	memcpy(temp_nvram + m_cart->get_nvram_size(), m_cart->get_rtc_ram_base(), m_cart->get_rtc_ram_size());
655
	655
656	656	battery_save(temp_nvram, tot_size);
657	657	if (temp_nvram)
658	658	auto_free(machine(), temp_nvram);
r21591	r21592
676	676	UINT8 sram_size = (m_type == SNES_SFX) ? (ROM[0x00ffbd] & 0x07) : (ROM[hilo_mode + 0x18] & 0x07);
677	677	if (sram_size)
678	678	{
679		UINT32 max = (hilo_mode == 0x007fc0) ? 0x80000 : 0x20000; // MODE20 vs MODE21
	679	UINT32 max = (hilo_mode == 0x007fc0) ? 0x80000 : 0x20000; // MODE20 vs MODE21
680	680	size = 1024 << (ROM[0x00ffbd] & 0x07);
681	681	if (size > max)
682	682	size = max;
r21591	r21592
729	729	break;
730	730	case 0x00ffc0: // HiRom
731	731	case 0x40ffc0: // ExHiRom
732		type = SNES_MODE21;
	732	type = SNES_MODE21;
733	733	break;
734	734	default:
735	735	break;
736	736	}
737
	737
738	738	// detect Sufami Turbo...
739	739	if (type == SNES_MODE20 && !memcmp(ROM, "BANDAI SFC-ADX", 14))
740	740	{
r21591	r21592
757	757	type = SNES_BSMEMPAK;
758	758	}
759	759	}
760
	760
761	761	// check for add-on chips...
762	762	if (len >= hilo_mode + 0x1a)
763	763	{
r21591	r21592
808	808	int type;
809	809
810	810	core_fread(m_file, ROM, len);
811
	811
812	812	type = get_cart_type(ROM, len);
813	813	slot_string = sns_get_slot(type);
814
	814
815	815	global_free(ROM);
816	816	clear();
817
	817
818	818	return slot_string;
819	819	}
820	820
r21591	r21592
882	882	static int char_to_int_conv( char id )
883	883	{
884	884	int value;
885
	885
886	886	if (id == '1') value = 0x01;
887	887	else if (id == '2') value = 0x02;
888	888	else if (id == '3') value = 0x03;
r21591	r21592
899	899	else if (id == 'E') value = 0x0e;
900	900	else if (id == 'F') value = 0x0f;
901	901	else value = 0x00;
902
	902
903	903	return value;
904	904	}
905	905
r21591	r21592
939	939	UNK,
940	940	UNK
941	941	};
942
	942
943	943	/* Some known countries */
944	944	static const char *const countries[] =
945	945	{
r21591	r21592
948	948	/* 8*/ "Spain (PAL)", "Germany, Austria & Switzerland (PAL)", "Italy (PAL)", "Hong Kong & China (PAL)",
949	949	/* c*/ "Indonesia (PAL)", "South Korea (NTSC)", UNK, UNK,
950	950	};
951
	951
952	952	/* Some known companies (integrations to the list from Snes9x) */
953	953	static const char *const companies[] =
954	954	{
r21591	r21592
1007	1007	default:
1008	1008	break;
1009	1009	}
1010
	1010
1011	1011	// detect Sufami Turbo...
1012	1012	if (type == SNES_MODE20 && !memcmp(ROM, "BANDAI SFC-ADX", 14))
1013	1013	{
r21591	r21592
1016	1016	else
1017	1017	type = SNES_STROM;
1018	1018	}
1019
	1019
1020	1020	// detect BS-X Base Cart
1021	1021	if (!memcmp(ROM + hilo_mode, "Satellaview BS-X ", 21))
1022	1022	type = SNES_BSX;
r21591	r21592
1030	1030	type = SNES_BSMEMPAK;
1031	1031	}
1032	1032	}
1033
	1033
1034	1034	addon = snes_find_addon_chip(ROM, hilo_mode);
1035	1035	if (addon != -1)
1036	1036	{
r21591	r21592
1041	1041	else
1042	1042	type = addon;
1043	1043	}
1044
	1044
1045	1045	/* Company */
1046	1046	for (int i = 0; i < 2; i++)
1047	1047	company_id[i] = ROM[hilo_mode - 0x10 + i];
1048	1048	company = (char_to_int_conv(company_id[0]) << 4) + char_to_int_conv(company_id[1]);
1049	1049	if (company == 0)
1050	1050	company = ROM[hilo_mode + 0x1a];
1051
	1051
1052	1052	/* ROM ID */
1053	1053	for(int i = 0; i < 4; i++ )
1054	1054	rom_id[i] = ROM[hilo_mode - 0x0d + i];
1055
	1055
1056	1056	/* Title */
1057	1057	for(int i = 0; i < 21; i++ )
1058	1058	title[i] = ROM[hilo_mode + i];
1059
	1059
1060	1060	/* RAM */
1061	1061	if (((ROM[hilo_mode + 0x16] & 0xf) == 1) \|\|
1062	1062	((ROM[hilo_mode + 0x16] & 0xf) == 2) \|\|
1063	1063	((ROM[hilo_mode + 0x16] & 0xf) == 4) \|\|
1064	1064	((ROM[hilo_mode + 0x16] & 0xf) == 5))
1065	1065	has_ram = 1;
1066
	1066
1067	1067	/* SRAM */
1068	1068	if (((ROM[hilo_mode + 0x16] & 0xf) == 2) \|\|
1069	1069	((ROM[hilo_mode + 0x16] & 0xf) == 5) \|\|
1070	1070	((ROM[hilo_mode + 0x16] & 0xf) == 6))
1071	1071	has_sram = 1;
1072
	1072
1073	1073	logerror( "ROM DETAILS\n" );
1074	1074	logerror( "===========\n\n" );
1075	1075	logerror( "\tTotal blocks: 0x%x\n", len);
1076	1076	logerror( "\tROM bank size: %s \n",
1077		(type == SNES_MODE20) ? "LoROM" :
1078		(type == SNES_MODE21) ? "HiROM" :
1079		(type == SNES_MODE22) ? "ExLoROM" :
1080		(type == SNES_MODE25) ? "ExHiROM" : "Other (BSX or ST)" );
	1077	(type == SNES_MODE20) ? "LoROM" :
	1078	(type == SNES_MODE21) ? "HiROM" :
	1079	(type == SNES_MODE22) ? "ExLoROM" :
	1080	(type == SNES_MODE25) ? "ExHiROM" : "Other (BSX or ST)" );
1081	1081	logerror( "\tCompany: %s [%.2s]\n", companies[company], company_id );
1082	1082	logerror( "\tROM ID: %.4s\n\n", rom_id );
1083
	1083
1084	1084	logerror( "HEADER DETAILS\n" );
1085	1085	logerror( "==============\n\n" );
1086	1086	logerror( "\tName: %.21s\n", title );
1087	1087	logerror( "\tSpeed: %s [%d]\n", (ROM[hilo_mode + 0x15] & 0xf0) ? "FastROM" : "SlowROM", (ROM[hilo_mode + 0x15] & 0xf0) >> 4);
1088	1088	logerror( "\tBank size: %s [%d]\n", (ROM[hilo_mode + 0x15] & 0xf) ? "HiROM" : "LoROM", ROM[hilo_mode + 0x15] & 0xf);
1089
	1089
1090	1090	logerror( "\tType: %s", cart_types[type]);
1091	1091	if (has_ram)
1092	1092	logerror( ", RAM");
1093	1093	if (has_sram)
1094	1094	logerror( ", SRAM");
1095	1095	logerror( " [%d]\n", ROM[hilo_mode + 0x16]);
1096
	1096
1097	1097	logerror( "\tSize: %d megabits [%d]\n", 1 << (ROM[hilo_mode + 0x17] - 7), ROM[hilo_mode + 0x17]);
1098	1098	logerror( "\tSRAM: %d kilobits [%d]\n", ROM[hilo_mode + 0x18] * 8, ROM[hilo_mode + 0x18] );
1099	1099	logerror( "\tCountry: %s [%d]\n", countries[ROM[hilo_mode + 0x19]], ROM[hilo_mode + 0x19]);
r21591	r21592
1103	1103	logerror( "\tChecksum: %X %X\n", ROM[hilo_mode + 0x1f], ROM[hilo_mode + 0x1e]);
1104	1104	logerror( "\tNMI Address: %2X%2Xh\n", ROM[hilo_mode + 0x2b], ROM[hilo_mode + 0x2a]);
1105	1105	logerror( "\tStart Address: %2X%2Xh\n\n", ROM[hilo_mode + 0x2d], ROM[hilo_mode + 0x2c]);
1106
	1106
1107	1107	logerror( "\tMode: %d\n", type);
1108	1108	}

trunk/src/mess/machine/sns_slot.h
r21591	r21592
11	11	{
12	12	SNES_MODE20 = 0,
13	13	SNES_MODE21,
14		SNES_MODE22, // ExLoROM - not used anymore in emulation (only to log info), will be removed
15		SNES_MODE25, // ExHiROM - not used anymore in emulation (only to log info), will be removed
	14	SNES_MODE22, // ExLoROM - not used anymore in emulation (only to log info), will be removed
	15	SNES_MODE25, // ExHiROM - not used anymore in emulation (only to log info), will be removed
16	16	SNES_CX4,
17	17	SNES_DSP,
18	18	SNES_DSP_MODE21,
r21591	r21592
36	36	SNES_STROM,
37	37	// pirate carts
38	38	SNES_POKEMON,
39		SNES_BANANA, // wip
40		SNES_SOULBLAD // wip
	39	SNES_BANANA, // wip
	40	SNES_SOULBLAD // wip
41	41	};
42	42
43	43
r21591	r21592
79	79	virtual UINT32 get_rtc_ram_size() { return m_rtc_ram_size; };
80	80
81	81	virtual void rom_map_setup(UINT32 size);
82
	82
83	83	// internal state
84	84	UINT8 *m_rom;
85	85	UINT8 *m_nvram;
86	86	UINT8 *m_bios;
87		UINT8 *m_rtc_ram; // temp pointer to save RTC ram to nvram (will disappear when RTCs become devices)
	87	UINT8 *m_rtc_ram; // temp pointer to save RTC ram to nvram (will disappear when RTCs become devices)
88	88	UINT32 m_rom_size;
89	89	UINT32 m_nvram_size;
90	90	UINT32 m_bios_size;
91		UINT32 m_rtc_ram_size; // temp
	91	UINT32 m_rtc_ram_size; // temp
92	92
93		UINT8 rom_bank_map[256]; // 32K chunks of rom
	93	UINT8 rom_bank_map[256]; // 32K chunks of rom
94	94	};
95	95
96	96
r21591	r21592
105	105	// construction/destruction
106	106	base_sns_cart_slot_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock);
107	107	virtual ~base_sns_cart_slot_device();
108
	108
109	109	// device-level overrides
110	110	virtual void device_start();
111	111	virtual void device_config_complete();
112
	112
113	113	// image-level overrides
114	114	virtual bool call_load();
115	115	virtual void call_unload();
r21591	r21592
146	146	// this should be private, but then there is some problem installing delegates in the driver...
147	147	//private:
148	148
149		device_sns_cart_interface* m_cart;
150
	149	device_sns_cart_interface* m_cart;
	150
151	151	int m_type;
152	152	};
153	153

trunk/src/mess/machine/snescart.c
r21591	r21592
1312	1312	#include "machine/snesrtc.c"
1313	1313	#include "machine/snessdd1.c"
1314	1314	#include "machine/snes7110.c"
1315

199869 Revisions