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r21587 Tuesday 5th March, 2013 at 08:18:31 UTC by Fabio Priuli
other two statics gone. nw.
[src/mame/includes]snes.h
[src/mame/machine]snes.c

trunk/src/mame/machine/snes.c
r21586r21587
3131/* -- Globals -- */
3232UINT8  *snes_ram = NULL;        /* 65816 ram */
3333
34static DECLARE_READ8_HANDLER(snes_io_dma_r);
35static DECLARE_WRITE8_HANDLER(snes_io_dma_w);
36
3734struct snes_cart_info snes_cart;
3835
39#define DMA_REG(a) state->m_dma_regs[a - 0x4300]   // regs 0x4300-0x437f
36#define DMA_REG(a) m_dma_regs[a - 0x4300]   // regs 0x4300-0x437f
4037
4138// add-on chip emulators
4239#include "machine/snesobc1.c"
r21586r21587
272269}
273270
274271/* read & write to DMA addresses are defined separately, to be called by snessdd1 handlers */
275static READ8_HANDLER( snes_io_dma_r )
272READ8_MEMBER( snes_state::snes_io_dma_r )
276273{
277   snes_state *state = space.machine().driver_data<snes_state>();
278
279274   switch (offset)
280275   {
281276      case DMAP0: case DMAP1: case DMAP2: case DMAP3: /*0x43n0*/
282277      case DMAP4: case DMAP5: case DMAP6: case DMAP7:
283         return state->m_dma_channel[(offset >> 4) & 0x07].dmap;
278         return m_dma_channel[(offset >> 4) & 0x07].dmap;
284279      case BBAD0: case BBAD1: case BBAD2: case BBAD3: /*0x43n1*/
285280      case BBAD4: case BBAD5: case BBAD6: case BBAD7:
286         return state->m_dma_channel[(offset >> 4) & 0x07].dest_addr;
281         return m_dma_channel[(offset >> 4) & 0x07].dest_addr;
287282      case A1T0L: case A1T1L: case A1T2L: case A1T3L: /*0x43n2*/
288283      case A1T4L: case A1T5L: case A1T6L: case A1T7L:
289         return state->m_dma_channel[(offset >> 4) & 0x07].src_addr & 0xff;
284         return m_dma_channel[(offset >> 4) & 0x07].src_addr & 0xff;
290285      case A1T0H: case A1T1H: case A1T2H: case A1T3H: /*0x43n3*/
291286      case A1T4H: case A1T5H: case A1T6H: case A1T7H:
292         return (state->m_dma_channel[(offset >> 4) & 0x07].src_addr >> 8) & 0xff;
287         return (m_dma_channel[(offset >> 4) & 0x07].src_addr >> 8) & 0xff;
293288      case A1B0: case A1B1: case A1B2: case A1B3:     /*0x43n4*/
294289      case A1B4: case A1B5: case A1B6: case A1B7:
295         return state->m_dma_channel[(offset >> 4) & 0x07].bank;
290         return m_dma_channel[(offset >> 4) & 0x07].bank;
296291      case DAS0L: case DAS1L: case DAS2L: case DAS3L: /*0x43n5*/
297292      case DAS4L: case DAS5L: case DAS6L: case DAS7L:
298         return state->m_dma_channel[(offset >> 4) & 0x07].trans_size & 0xff;
293         return m_dma_channel[(offset >> 4) & 0x07].trans_size & 0xff;
299294      case DAS0H: case DAS1H: case DAS2H: case DAS3H: /*0x43n6*/
300295      case DAS4H: case DAS5H: case DAS6H: case DAS7H:
301         return (state->m_dma_channel[(offset >> 4) & 0x07].trans_size >> 8) & 0xff;
296         return (m_dma_channel[(offset >> 4) & 0x07].trans_size >> 8) & 0xff;
302297      case DSAB0: case DSAB1: case DSAB2: case DSAB3: /*0x43n7*/
303298      case DSAB4: case DSAB5: case DSAB6: case DSAB7:
304         return state->m_dma_channel[(offset >> 4) & 0x07].ibank;
299         return m_dma_channel[(offset >> 4) & 0x07].ibank;
305300      case A2A0L: case A2A1L: case A2A2L: case A2A3L: /*0x43n8*/
306301      case A2A4L: case A2A5L: case A2A6L: case A2A7L:
307         return state->m_dma_channel[(offset >> 4) & 0x07].hdma_addr & 0xff;
302         return m_dma_channel[(offset >> 4) & 0x07].hdma_addr & 0xff;
308303      case A2A0H: case A2A1H: case A2A2H: case A2A3H: /*0x43n9*/
309304      case A2A4H: case A2A5H: case A2A6H: case A2A7H:
310         return (state->m_dma_channel[(offset >> 4) & 0x07].hdma_addr >> 8) & 0xff;
305         return (m_dma_channel[(offset >> 4) & 0x07].hdma_addr >> 8) & 0xff;
311306      case NTRL0: case NTRL1: case NTRL2: case NTRL3: /*0x43na*/
312307      case NTRL4: case NTRL5: case NTRL6: case NTRL7:
313         return state->m_dma_channel[(offset >> 4) & 0x07].hdma_line_counter;
308         return m_dma_channel[(offset >> 4) & 0x07].hdma_line_counter;
314309      case 0x430b: case 0x431b: case 0x432b: case 0x433b: /* according to bsnes, this does not return open_bus (even if its precise effect is unknown) */
315310      case 0x434b: case 0x435b: case 0x436b: case 0x437b:
316         return state->m_dma_channel[(offset >> 4) & 0x07].unk;
311         return m_dma_channel[(offset >> 4) & 0x07].unk;
317312   }
318313
319314   /* we should never arrive here */
320315   return snes_open_bus_r(space, 0);
321316}
322317
323static WRITE8_HANDLER( snes_io_dma_w )
318WRITE8_HANDLER( snes_state::snes_io_dma_w )
324319{
325   snes_state *state = space.machine().driver_data<snes_state>();
326
327320   switch (offset)
328321   {
329322         /* Below is all DMA related */
330323      case DMAP0: case DMAP1: case DMAP2: case DMAP3: /*0x43n0*/
331324      case DMAP4: case DMAP5: case DMAP6: case DMAP7:
332         state->m_dma_channel[(offset >> 4) & 0x07].dmap = data;
325         m_dma_channel[(offset >> 4) & 0x07].dmap = data;
333326         break;
334327      case BBAD0: case BBAD1: case BBAD2: case BBAD3: /*0x43n1*/
335328      case BBAD4: case BBAD5: case BBAD6: case BBAD7:
336         state->m_dma_channel[(offset >> 4) & 0x07].dest_addr = data;
329         m_dma_channel[(offset >> 4) & 0x07].dest_addr = data;
337330         break;
338331      case A1T0L: case A1T1L: case A1T2L: case A1T3L: /*0x43n2*/
339332      case A1T4L: case A1T5L: case A1T6L: case A1T7L:
340         state->m_dma_channel[(offset >> 4) & 0x07].src_addr = (state->m_dma_channel[(offset >> 4) & 0x07].src_addr & 0xff00) | (data << 0);
333         m_dma_channel[(offset >> 4) & 0x07].src_addr = (m_dma_channel[(offset >> 4) & 0x07].src_addr & 0xff00) | (data << 0);
341334         break;
342335      case A1T0H: case A1T1H: case A1T2H: case A1T3H: /*0x43n3*/
343336      case A1T4H: case A1T5H: case A1T6H: case A1T7H:
344         state->m_dma_channel[(offset >> 4) & 0x07].src_addr = (state->m_dma_channel[(offset >> 4) & 0x07].src_addr & 0x00ff) | (data << 8);
337         m_dma_channel[(offset >> 4) & 0x07].src_addr = (m_dma_channel[(offset >> 4) & 0x07].src_addr & 0x00ff) | (data << 8);
345338         break;
346339      case A1B0: case A1B1: case A1B2: case A1B3:     /*0x43n4*/
347340      case A1B4: case A1B5: case A1B6: case A1B7:
348         state->m_dma_channel[(offset >> 4) & 0x07].bank = data;
341         m_dma_channel[(offset >> 4) & 0x07].bank = data;
349342         break;
350343      case DAS0L: case DAS1L: case DAS2L: case DAS3L: /*0x43n5*/
351344      case DAS4L: case DAS5L: case DAS6L: case DAS7L:
352         state->m_dma_channel[(offset >> 4) & 0x07].trans_size = (state->m_dma_channel[(offset >> 4) & 0x07].trans_size & 0xff00) | (data << 0);
345         m_dma_channel[(offset >> 4) & 0x07].trans_size = (m_dma_channel[(offset >> 4) & 0x07].trans_size & 0xff00) | (data << 0);
353346         break;
354347      case DAS0H: case DAS1H: case DAS2H: case DAS3H: /*0x43n6*/
355348      case DAS4H: case DAS5H: case DAS6H: case DAS7H:
356         state->m_dma_channel[(offset >> 4) & 0x07].trans_size = (state->m_dma_channel[(offset >> 4) & 0x07].trans_size & 0x00ff) | (data << 8);
349         m_dma_channel[(offset >> 4) & 0x07].trans_size = (m_dma_channel[(offset >> 4) & 0x07].trans_size & 0x00ff) | (data << 8);
357350         break;
358351      case DSAB0: case DSAB1: case DSAB2: case DSAB3: /*0x43n7*/
359352      case DSAB4: case DSAB5: case DSAB6: case DSAB7:
360         state->m_dma_channel[(offset >> 4) & 0x07].ibank = data;
353         m_dma_channel[(offset >> 4) & 0x07].ibank = data;
361354         break;
362355      case A2A0L: case A2A1L: case A2A2L: case A2A3L: /*0x43n8*/
363356      case A2A4L: case A2A5L: case A2A6L: case A2A7L:
364         state->m_dma_channel[(offset >> 4) & 0x07].hdma_addr = (state->m_dma_channel[(offset >> 4) & 0x07].hdma_addr & 0xff00) | (data << 0);
357         m_dma_channel[(offset >> 4) & 0x07].hdma_addr = (m_dma_channel[(offset >> 4) & 0x07].hdma_addr & 0xff00) | (data << 0);
365358         break;
366359      case A2A0H: case A2A1H: case A2A2H: case A2A3H: /*0x43n9*/
367360      case A2A4H: case A2A5H: case A2A6H: case A2A7H:
368         state->m_dma_channel[(offset >> 4) & 0x07].hdma_addr = (state->m_dma_channel[(offset >> 4) & 0x07].hdma_addr & 0x00ff) | (data << 8);
361         m_dma_channel[(offset >> 4) & 0x07].hdma_addr = (m_dma_channel[(offset >> 4) & 0x07].hdma_addr & 0x00ff) | (data << 8);
369362         break;
370363      case NTRL0: case NTRL1: case NTRL2: case NTRL3: /*0x43na*/
371364      case NTRL4: case NTRL5: case NTRL6: case NTRL7:
372         state->m_dma_channel[(offset >> 4) & 0x07].hdma_line_counter = data;
365         m_dma_channel[(offset >> 4) & 0x07].hdma_line_counter = data;
373366         break;
374367      case 0x430b: case 0x431b: case 0x432b: case 0x433b:
375368      case 0x434b: case 0x435b: case 0x436b: case 0x437b:
376         state->m_dma_channel[(offset >> 4) & 0x07].unk = data;
369         m_dma_channel[(offset >> 4) & 0x07].unk = data;
377370         break;
378371   }
379372
r21586r21587
406399   // DMA accesses are from 4300 to 437f
407400   if (offset >= DMAP0 && offset < 0x4380)
408401   {
409      return snes_io_dma_r(space, offset);
402      return state->snes_io_dma_r(space, offset);
410403   }
411404
412405   /* offset is from 0x000000 */
r21586r21587
509502   // DMA accesses are from 4300 to 437f
510503   if (offset >= DMAP0 && offset < 0x4380)
511504   {
512      snes_io_dma_w(space, offset, data);
505      state->snes_io_dma_w(space, offset, data);
513506      return;
514507   }
515508
trunk/src/mame/includes/snes.h
r21586r21587
682682   void hdma_update(address_space &space, int dma);
683683   void hirq_tick();
684684
685   DECLARE_READ8_MEMBER(snes_io_dma_r);
686   DECLARE_WRITE8_MEMBER(snes_io_dma_w);
685687   TIMER_CALLBACK_MEMBER(snes_nmi_tick);
686688   TIMER_CALLBACK_MEMBER(snes_hirq_tick_callback);
687689   TIMER_CALLBACK_MEMBER(snes_reset_oam_address);

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