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r21584 Tuesday 5th March, 2013 at 06:50:37 UTC by Fabio Priuli
cleanups. nw.
[src/mess/drivers]snes.c

trunk/src/mess/drivers/snes.c
r21583r21584
108108static READ8_HANDLER( snes_lo_r )
109109{
110110   snes_state *state = space.machine().driver_data<snes_state>();
111   UINT16 address = offset & 0xffff;
112
111113   // take care of add-on chip access
112114   if (state->m_has_addon_chip == HAS_OBC1
113      && (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
115      && (offset < 0x400000 && address >= 0x6000 && address < 0x8000))
114116      return obc1_read(space, offset, mem_mask);
115117   if (state->m_has_addon_chip == HAS_CX4
116      && (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
117      return CX4_read((offset & 0xffff) - 0x6000);
118      && (offset < 0x400000 && address >= 0x6000 && address < 0x8000))
119      return CX4_read(address - 0x6000);
118120   if (state->m_has_addon_chip == HAS_RTC
119      && (offset < 0x400000 && ((offset & 0xffff) == 0x2800 || (offset & 0xffff) == 0x2801)))
121      && (offset < 0x400000 && (address == 0x2800 || address == 0x2801)))
120122      return srtc_read(space, offset);
121123   if (state->m_has_addon_chip == HAS_ST010 || state->m_has_addon_chip == HAS_ST011)
122124   {
123      if (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000)
124         return st010_read_ram(state, (offset & 0xffff));
125      if (offset >= 0x680000 && offset < 0x700000 && address < 0x1000)
126         return st010_read_ram(state, address);
125127      if (offset == 0x600000 || offset == 0x600001)
126128         return (offset & 1) ? st010_get_sr() : st010_get_dr();
127129   }
128130   if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1
129      && (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
130      return ((offset & 0xffff) < 0x7000) ? dsp_get_dr() : dsp_get_sr();
131      && (offset < 0x200000 && address >= 0x6000 && address < 0x8000))
132      return (address < 0x7000) ? dsp_get_dr() : dsp_get_sr();
131133   if (state->m_cart[0].mode == SNES_MODE_20 && state->m_has_addon_chip == HAS_DSP1)
132134   {
133135      if (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)
134         return ((offset & 0xffff) < 0xc000) ? dsp_get_dr() : dsp_get_sr();
136         return (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
135137      if (offset >= 0x600000 && offset < 0x700000 && (offset & 0x8000) == 0x0000)
136         return ((offset & 0xffff) < 0x4000) ? dsp_get_dr() : dsp_get_sr();
138         return (address < 0x4000) ? dsp_get_dr() : dsp_get_sr();
137139   }   
138140   if ((state->m_has_addon_chip == HAS_DSP2 || state->m_has_addon_chip == HAS_DSP3)
139141      && (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
140      return ((offset & 0xffff) < 0xc000) ? dsp_get_dr() : dsp_get_sr();
142      return (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
141143   if (state->m_has_addon_chip == HAS_DSP4
142144      && (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
143      return ((offset & 0xffff) < 0xc000) ? dsp_get_dr() : dsp_get_sr();
145      return (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
144146   if (state->m_has_addon_chip == HAS_SDD1
145      && (offset < 0x400000 && (offset & 0xffff) >= 0x4800 && (offset & 0xffff) < 0x4808))
146      return sdd1_mmio_read(space, (UINT32)(offset & 0xffff));
147      && (offset < 0x400000 && address >= 0x4800 && address < 0x4808))
148      return sdd1_mmio_read(space, (UINT32)address);
147149   if ((state->m_has_addon_chip == HAS_SPC7110 || state->m_has_addon_chip == HAS_SPC7110_RTC)
148150      && offset < 0x400000)
149151   {   
150152      UINT16 limit = (state->m_has_addon_chip == HAS_SPC7110_RTC) ? 0x4842 : 0x483f;
151      if ((offset & 0xffff) >= 0x4800 && (offset & 0xffff) <= limit)
152         return spc7110_mmio_read(space, (UINT32)(offset & 0xffff));
153      if (offset < 0x10000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)
154         return snes_ram[0x306000 + (offset & 0x1fff)];
155      if (offset >= 0x300000 && offset < 0x310000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)
156         return snes_ram[0x306000 + (offset & 0x1fff)];
153      if (address >= 0x4800 && address <= limit)
154         return spc7110_mmio_read(space, (UINT32)address);
155      if (offset < 0x10000 && address >= 0x6000 && address < 0x8000)
156         return snes_ram[0x306000 + (address & 0x1fff)];
157      if (offset >= 0x300000 && offset < 0x310000 && address >= 0x6000 && address < 0x8000)
158         return snes_ram[0x306000 + (address & 0x1fff)];
157159   }
158160   if ((state->m_has_addon_chip == HAS_SPC7110 || state->m_has_addon_chip == HAS_SPC7110_RTC)
159161      && offset >= 0x500000 && offset < 0x510000)
r21583r21584
175177static READ8_HANDLER( snes_hi_r )
176178{
177179   snes_state *state = space.machine().driver_data<snes_state>();
180   UINT16 address = offset & 0xffff;
181   
178182   // take care of add-on chip access
179183   if (state->m_has_addon_chip == HAS_OBC1
180      && (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
184      && (offset < 0x400000 && address >= 0x6000 && address < 0x8000))
181185      return obc1_read(space, offset, mem_mask);
182186   if (state->m_has_addon_chip == HAS_CX4
183      && (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
184      return CX4_read((offset & 0xffff) - 0x6000);
187      && (offset < 0x400000 && address >= 0x6000 && address < 0x8000))
188      return CX4_read(address - 0x6000);
185189   if (state->m_has_addon_chip == HAS_RTC
186      && (offset < 0x400000 && ((offset & 0xffff) == 0x2800 || (offset & 0xffff) == 0x2801)))
190      && (offset < 0x400000 && (address == 0x2800 || address == 0x2801)))
187191      return srtc_read(space, offset);
188192   if (state->m_has_addon_chip == HAS_ST010 || state->m_has_addon_chip == HAS_ST011)
189193   {
190      if (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000)
191         return st010_read_ram(state, (offset & 0xffff));
194      if (offset >= 0x680000 && offset < 0x700000 && address < 0x1000)
195         return st010_read_ram(state, address);
192196      if (offset == 0x600000 || offset == 0x600001)
193197         return (offset & 1) ? st010_get_sr() : st010_get_dr();
194198   }
195199   if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1
196      && (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
197      return ((offset & 0xffff) < 0x7000) ? dsp_get_dr() : dsp_get_sr();
200      && (offset < 0x200000 && address >= 0x6000 && address < 0x8000))
201      return (address < 0x7000) ? dsp_get_dr() : dsp_get_sr();
198202   if (state->m_cart[0].mode == SNES_MODE_20 && state->m_has_addon_chip == HAS_DSP1)
199203   {
200204      if (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)
201         return ((offset & 0xffff) < 0xc000) ? dsp_get_dr() : dsp_get_sr();
205         return (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
202206      if (offset >= 0x600000 && offset < 0x700000 && (offset & 0x8000) == 0x0000)
203         return ((offset & 0xffff) < 0x4000) ? dsp_get_dr() : dsp_get_sr();
207         return (address < 0x4000) ? dsp_get_dr() : dsp_get_sr();
204208   }
205209   if ((state->m_has_addon_chip == HAS_DSP2 || state->m_has_addon_chip == HAS_DSP3)
206210      && (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
207      return ((offset & 0xffff) < 0xc000) ? dsp_get_dr() : dsp_get_sr();
211      return (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
208212   if (state->m_has_addon_chip == HAS_DSP4
209213      && (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
210      return ((offset & 0xffff) < 0xc000) ? dsp_get_dr() : dsp_get_sr();
214      return (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
211215   if (state->m_has_addon_chip == HAS_SDD1
212      && (offset < 0x400000 && (offset & 0xffff) >= 0x4800 && (offset & 0xffff) < 0x4808))
213      return sdd1_mmio_read(space, (UINT32)(offset & 0xffff));
216      && (offset < 0x400000 && address >= 0x4800 && address < 0x4808))
217      return sdd1_mmio_read(space, (UINT32)address);
214218   if (state->m_has_addon_chip == HAS_SDD1 && offset >= 0x400000)
215219      return sdd1_read(space.machine(), offset - 0x400000);
216220   if ((state->m_has_addon_chip == HAS_SPC7110 || state->m_has_addon_chip == HAS_SPC7110_RTC)
217221      && offset < 0x400000)
218222   {   
219223      UINT16 limit = (state->m_has_addon_chip == HAS_SPC7110_RTC) ? 0x4842 : 0x483f;
220      if ((offset & 0xffff) >= 0x4800 && (offset & 0xffff) <= limit)
221         return spc7110_mmio_read(space, (UINT32)(offset & 0xffff));
222      if (offset < 0x10000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)
223         return snes_ram[0x306000 + (offset & 0x1fff)];
224      if (offset >= 0x300000 && offset < 0x310000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)
225         return snes_ram[0x306000 + (offset & 0x1fff)];
224      if (address >= 0x4800 && address <= limit)
225         return spc7110_mmio_read(space, (UINT32)address);
226      if (offset < 0x10000 && address >= 0x6000 && address < 0x8000)
227         return snes_ram[0x306000 + (address & 0x1fff)];
228      if (offset >= 0x300000 && offset < 0x310000 && address >= 0x6000 && address < 0x8000)
229         return snes_ram[0x306000 + (address & 0x1fff)];
226230   }
227231   if ((state->m_has_addon_chip == HAS_SPC7110 || state->m_has_addon_chip == HAS_SPC7110_RTC)
228232      && offset >= 0x500000)
r21583r21584
238242static WRITE8_HANDLER( snes_lo_w )
239243{
240244   snes_state *state = space.machine().driver_data<snes_state>();
245   UINT16 address = offset & 0xffff;
246   
241247   // take care of add-on chip access
242248   if (state->m_has_addon_chip == HAS_OBC1
243      && (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
244   {
245      obc1_write(space, offset, data, mem_mask);
246      return;
247   }
249      && (offset < 0x400000 && address >= 0x6000 && address < 0x8000))
250   {   obc1_write(space, offset, data, mem_mask);   return;   }
248251   if (state->m_has_addon_chip == HAS_CX4
249      && (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
250   {
251      CX4_write(space.machine(), (offset & 0xffff) - 0x6000, data);
252      return;
253   }
252      && (offset < 0x400000 && address >= 0x6000 && address < 0x8000))
253   {   CX4_write(space.machine(), address - 0x6000, data);   return;   }
254254   if (state->m_has_addon_chip == HAS_RTC
255      && (offset < 0x400000 && ((offset & 0xffff) == 0x2800 || (offset & 0xffff) == 0x2801)))
256   {
257      srtc_write(space.machine(), offset, data);
258      return;
259   }
255      && (offset < 0x400000 && (address == 0x2800 || address == 0x2801)))
256   {   srtc_write(space.machine(), offset, data);   return;   }
260257   if (state->m_has_addon_chip == HAS_ST010 || state->m_has_addon_chip == HAS_ST011)
261258   {
262      if (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000)
263      {   st010_write_ram(state, (offset & 0xffff), data);   return;   }
259      if (offset >= 0x680000 && offset < 0x700000 && address < 0x1000)
260      {   st010_write_ram(state, address, data);   return;   }
264261      if (offset == 0x600000)
265262      {   st010_set_dr(data);   return;   }
266263      if (offset == 0x600001)
267264      {   st010_set_sr(data);   return;   }
268265   }
269266   if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1
270      && (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
271   {   
272      dsp_set_dr(data);
273      return;
274   }
267      && (offset < 0x200000 && address >= 0x6000 && address < 0x8000))
268   {   dsp_set_dr(data);   return;   }
275269   if (state->m_cart[0].mode == SNES_MODE_20 && state->m_has_addon_chip == HAS_DSP1)
276270   {
277271      if (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)
r21583r21584
282276   if ((state->m_has_addon_chip == HAS_DSP2 || state->m_has_addon_chip == HAS_DSP3)
283277      && (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
284278   {
285      if ((offset & 0xffff) < 0xc000)
279      if (address < 0xc000)
286280      {   dsp_set_dr(data);   return;   }
287281      else
288282      {   dsp_set_sr(data);   return;   }
r21583r21584
290284   if (state->m_has_addon_chip == HAS_DSP4
291285      && (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
292286   {
293      if ((offset & 0xffff) < 0xc000)
287      if (address < 0xc000)
294288      {   dsp_set_dr(data);   return;   }
295289      else
296290      {   dsp_set_sr(data);   return;   }
297291   }
298292   if (state->m_has_addon_chip == HAS_SDD1 && offset < 0x400000)
299293   {
300      if (((offset & 0xffff) >= 0x4300 && (offset & 0xffff) < 0x4380) ||
301         ((offset & 0xffff) >= 0x4800 && (offset & 0xffff) < 0x4808))
294      if ((address >= 0x4300 && address < 0x4380) || (address >= 0x4800 && address < 0x4808))
302295      {
303            sdd1_mmio_write(space, (UINT32)(offset & 0xffff), data);
296            sdd1_mmio_write(space, (UINT32)address, data);
304297            // here we don't return, but we let the w_io happen...
305298      }
306299   }
307300   if ((state->m_has_addon_chip == HAS_SPC7110 || state->m_has_addon_chip == HAS_SPC7110_RTC) && offset < 0x400000)
308301   {   
309302      UINT16 limit = (state->m_has_addon_chip == HAS_SPC7110_RTC) ? 0x4842 : 0x483f;
310      if ((offset & 0xffff) >= 0x4800 && (offset & 0xffff) <= limit)
311      {   spc7110_mmio_write(space.machine(), (UINT32)(offset & 0xffff), data);   return;   }
312      if (offset < 0x10000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)
313      {   snes_ram[0x306000 + (offset & 0x1fff)] = data;   return;   }
314      if (offset >= 0x300000 && offset < 0x310000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)
315      {   snes_ram[0x306000 + (offset & 0x1fff)] = data;   return;   }
303      if (address >= 0x4800 && address <= limit)
304      {   spc7110_mmio_write(space.machine(), (UINT32)address, data);   return;   }
305      if (offset < 0x10000 && address >= 0x6000 && address < 0x8000)
306      {   snes_ram[0x306000 + (address & 0x1fff)] = data;   return;   }
307      if (offset >= 0x300000 && offset < 0x310000 && address >= 0x6000 && address < 0x8000)
308      {   snes_ram[0x306000 + (address & 0x1fff)] = data;   return;   }
316309   }
317310   
318311   // base cart access
r21583r21584
331324static WRITE8_HANDLER( snes_hi_w )
332325{
333326   snes_state *state = space.machine().driver_data<snes_state>();
327   UINT16 address = offset & 0xffff;
328   
334329   // take care of add-on chip access
335330   if (state->m_has_addon_chip == HAS_OBC1
336      && (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
337   {
338      obc1_write(space, offset, data, mem_mask);
339      return;
340   }
331      && (offset < 0x400000 && address >= 0x6000 && address < 0x8000))
332   {   obc1_write(space, offset, data, mem_mask);   return;   }
341333   if (state->m_has_addon_chip == HAS_CX4
342      && (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
343   {
344      CX4_write(space.machine(), (offset & 0xffff) - 0x6000, data);
345      return;
346   }
334      && (offset < 0x400000 && address >= 0x6000 && address < 0x8000))
335   {   CX4_write(space.machine(), address - 0x6000, data);   return;   }
347336   if (state->m_has_addon_chip == HAS_RTC
348      && (offset < 0x400000 && ((offset & 0xffff) == 0x2800 || (offset & 0xffff) == 0x2801)))
349   {
350      srtc_write(space.machine(), offset, data);
351      return;
352   }
337      && (offset < 0x400000 && (address == 0x2800 || address == 0x2801)))
338   {   srtc_write(space.machine(), offset, data);   return;   }
353339   if (state->m_has_addon_chip == HAS_ST010 || state->m_has_addon_chip == HAS_ST011)
354340   {
355      if (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000)
356      {   st010_write_ram(state, (offset & 0xffff), data);   return;   }
341      if (offset >= 0x680000 && offset < 0x700000 && address < 0x1000)
342      {   st010_write_ram(state, address, data);   return;   }
357343      if (offset == 0x600000)
358344      {   st010_set_dr(data);   return;   }
359345      if (offset == 0x600001)
360346      {   st010_set_sr(data);   return;   }
361347   }
362348   if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1
363      && (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
364   {   
365      dsp_set_dr(data);
366      return;
367   }
349      && (offset < 0x200000 && address >= 0x6000 && address < 0x8000))
350   {   dsp_set_dr(data);   return;   }
368351   if (state->m_cart[0].mode == SNES_MODE_20 && state->m_has_addon_chip == HAS_DSP1)
369352   {
370353      if (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)
r21583r21584
375358   if ((state->m_has_addon_chip == HAS_DSP2 || state->m_has_addon_chip == HAS_DSP3)
376359      && (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
377360   {
378      if ((offset & 0xffff) < 0xc000)
361      if (address < 0xc000)
379362      {   dsp_set_dr(data);   return;   }
380363      else
381364      {   dsp_set_sr(data);   return;   }
r21583r21584
383366   if (state->m_has_addon_chip == HAS_DSP4
384367      && (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
385368   {
386      if ((offset & 0xffff) < 0xc000)
369      if (address < 0xc000)
387370      {   dsp_set_dr(data);   return;   }
388371      else
389372      {   dsp_set_sr(data);   return;   }
390373   }
391374   if (state->m_has_addon_chip == HAS_SDD1 && offset < 0x400000)
392375   {
393      if (((offset & 0xffff) >= 0x4300 && (offset & 0xffff) < 0x4380) ||
394         ((offset & 0xffff) >= 0x4800 && (offset & 0xffff) < 0x4808))
376      if ((address >= 0x4300 && address < 0x4380) || (address >= 0x4800 && address < 0x4808))
395377      {
396         sdd1_mmio_write(space, (UINT32)(offset & 0xffff), data);
378         sdd1_mmio_write(space, (UINT32)address, data);
397379         // here we don't return, but we let the w_io happen...
398380      }
399381   }
400382   if ((state->m_has_addon_chip == HAS_SPC7110 || state->m_has_addon_chip == HAS_SPC7110_RTC) && offset < 0x400000)
401383   {   
402384      UINT16 limit = (state->m_has_addon_chip == HAS_SPC7110_RTC) ? 0x4842 : 0x483f;
403      if ((offset & 0xffff) >= 0x4800 && (offset & 0xffff) <= limit)
404      {   spc7110_mmio_write(space.machine(), (UINT32)(offset & 0xffff), data);   return;   }
405      if (offset < 0x10000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)
406      {   snes_ram[0x306000 + (offset & 0x1fff)] = data;   return;   }
407      if (offset >= 0x300000 && offset < 0x310000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000)
408      {   snes_ram[0x306000 + (offset & 0x1fff)] = data;   return;   }
385      if (address >= 0x4800 && address <= limit)
386      {   spc7110_mmio_write(space.machine(), (UINT32)address, data);   return;   }
387      if (offset < 0x10000 && address >= 0x6000 && address < 0x8000)
388      {   snes_ram[0x306000 + (address & 0x1fff)] = data;   return;   }
389      if (offset >= 0x300000 && offset < 0x310000 && address >= 0x6000 && address < 0x8000)
390      {   snes_ram[0x306000 + (address & 0x1fff)] = data;   return;   }
409391   }
410392   
411393   // base cart access

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