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r21575 Monday 4th March, 2013 at 21:45:21 UTC by Fabio Priuli
snes: shuffling some code around (part 2). nw.

[src/mame/includes]	snes.h
[src/mame/machine]	snes.c snescx4.c snesobc1.c snesrtc.c
[src/mess/drivers]	snes.c

trunk/src/mess/drivers/snes.c

r21574	r21575
57	57	spc_ram_w(device, space, offset + 0x100, data);
58	58	}
59	59
	60	// DSP accessors
	61	#define dsp_get_sr() state->m_upd7725->snesdsp_read(false)
	62	#define dsp_get_dr() state->m_upd7725->snesdsp_read(true)
	63	#define dsp_set_sr(data) state->m_upd7725->snesdsp_write(false, data)
	64	#define dsp_set_dr(data) state->m_upd7725->snesdsp_write(true, data)
60	65
	66	#define st010_get_sr() state->m_upd96050->snesdsp_read(false)
	67	#define st010_get_dr() state->m_upd96050->snesdsp_read(true)
	68	#define st010_set_sr(data) state->m_upd96050->snesdsp_write(false, data)
	69	#define st010_set_dr(data) state->m_upd96050->snesdsp_write(true, data)
	70
	71	// ST-010 and ST-011 RAM interface
	72	UINT8 st010_read_ram(snes_state *state, UINT16 addr)
	73	{
	74	UINT16 temp = state->m_upd96050->dataram_r(addr/2);
	75	UINT8 res;
	76
	77	if (addr & 1)
	78	{
	79	res = temp>>8;
	80	}
	81	else
	82	{
	83	res = temp & 0xff;
	84	}
	85
	86	return res;
	87	}
	88
	89	void st010_write_ram(snes_state *state, UINT16 addr, UINT8 data)
	90	{
	91	UINT16 temp = state->m_upd96050->dataram_r(addr/2);
	92
	93	if (addr & 1)
	94	{
	95	temp &= 0xff;
	96	temp |= data<<8;
	97	}
	98	else
	99	{
	100	temp &= 0xff00;
	101	temp |= data;
	102	}
	103
	104	state->m_upd96050->dataram_w(addr/2, temp);
	105	}
	106
	107
61	108	static READ8_HANDLER( snes_lo_r )
62	109	{
	110	snes_state *state = space.machine().driver_data<snes_state>();
	111	// take care of add-on chip access
	112	if (state->m_has_addon_chip == HAS_OBC1
	113	&& (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	114	return obc1_read(space, offset, mem_mask);
	115	if (state->m_has_addon_chip == HAS_CX4
	116	&& (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	117	return CX4_read((offset & 0xffff) - 0x6000);
	118	if (state->m_has_addon_chip == HAS_RTC
	119	&& (offset < 0x400000 && ((offset & 0xffff) == 0x2800 || (offset & 0xffff) == 0x2801)))
	120	return srtc_read(space, offset);
	121	if (state->m_has_addon_chip == HAS_ST010 || state->m_has_addon_chip == HAS_ST011)
	122	{
	123	if (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000)
	124	return st010_read_ram(state, (offset & 0xffff));
	125	if (offset == 0x600000 || offset == 0x600001)
	126	return (offset & 1) ? st010_get_sr() : st010_get_dr();
	127	}
	128	if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1
	129	&& (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	130	return ((offset & 0xffff) < 0x7000) ? dsp_get_dr() : dsp_get_sr();
	131	if (state->m_cart[0].mode == SNES_MODE_20 && state->m_has_addon_chip == HAS_DSP1)
	132	{
	133	if (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)
	134	return ((offset & 0xffff) < 0xc000) ? dsp_get_dr() : dsp_get_sr();
	135	if (offset >= 0x600000 && offset < 0x700000 && (offset & 0x8000) == 0x0000)
	136	return ((offset & 0xffff) < 0x4000) ? dsp_get_dr() : dsp_get_sr();
	137	}
	138	if ((state->m_has_addon_chip == HAS_DSP2 || state->m_has_addon_chip == HAS_DSP3)
	139	&& (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
	140	return ((offset & 0xffff) < 0xc000) ? dsp_get_dr() : dsp_get_sr();
	141	if (state->m_has_addon_chip == HAS_DSP4
	142	&& (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
	143	return ((offset & 0xffff) < 0xc000) ? dsp_get_dr() : dsp_get_sr();
	144
	145	// base cart access
63	146	if (offset < 0x300000)
64	147	return snes_r_bank1(space, offset, 0xff);
65	148	else if (offset < 0x400000)
r21574	r21575
74	157
75	158	static READ8_HANDLER( snes_hi_r )
76	159	{
	160	snes_state *state = space.machine().driver_data<snes_state>();
	161	// take care of add-on chip access
	162	if (state->m_has_addon_chip == HAS_OBC1
	163	&& (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	164	return obc1_read(space, offset, mem_mask);
	165	if (state->m_has_addon_chip == HAS_CX4
	166	&& (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	167	return CX4_read((offset & 0xffff) - 0x6000);
	168	if (state->m_has_addon_chip == HAS_RTC
	169	&& (offset < 0x400000 && ((offset & 0xffff) == 0x2800 || (offset & 0xffff) == 0x2801)))
	170	return srtc_read(space, offset);
	171	if (state->m_has_addon_chip == HAS_ST010 || state->m_has_addon_chip == HAS_ST011)
	172	{
	173	if (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000)
	174	return st010_read_ram(state, (offset & 0xffff));
	175	if (offset == 0x600000 || offset == 0x600001)
	176	return (offset & 1) ? st010_get_sr() : st010_get_dr();
	177	}
	178	if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1
	179	&& (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	180	return ((offset & 0xffff) < 0x7000) ? dsp_get_dr() : dsp_get_sr();
	181	if (state->m_cart[0].mode == SNES_MODE_20 && state->m_has_addon_chip == HAS_DSP1)
	182	{
	183	if (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)
	184	return ((offset & 0xffff) < 0xc000) ? dsp_get_dr() : dsp_get_sr();
	185	if (offset >= 0x600000 && offset < 0x700000 && (offset & 0x8000) == 0x0000)
	186	return ((offset & 0xffff) < 0x4000) ? dsp_get_dr() : dsp_get_sr();
	187	}
	188	if ((state->m_has_addon_chip == HAS_DSP2 || state->m_has_addon_chip == HAS_DSP3)
	189	&& (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
	190	return ((offset & 0xffff) < 0xc000) ? dsp_get_dr() : dsp_get_sr();
	191	if (state->m_has_addon_chip == HAS_DSP4
	192	&& (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
	193	return ((offset & 0xffff) < 0xc000) ? dsp_get_dr() : dsp_get_sr();
	194
	195	// base cart access
77	196	if (offset < 0x400000)
78	197	return snes_r_bank6(space, offset, 0xff);
79	198	else
r21574	r21575
82	201
83	202	static WRITE8_HANDLER( snes_lo_w )
84	203	{
	204	snes_state *state = space.machine().driver_data<snes_state>();
	205	// take care of add-on chip access
	206	if (state->m_has_addon_chip == HAS_OBC1
	207	&& (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	208	{
	209	obc1_write(space, offset, data, mem_mask);
	210	return;
	211	}
	212	if (state->m_has_addon_chip == HAS_CX4
	213	&& (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	214	{
	215	CX4_write(space.machine(), (offset & 0xffff) - 0x6000, data);
	216	return;
	217	}
	218	if (state->m_has_addon_chip == HAS_RTC
	219	&& (offset < 0x400000 && ((offset & 0xffff) == 0x2800 || (offset & 0xffff) == 0x2801)))
	220	{
	221	srtc_write(space.machine(), offset, data);
	222	return;
	223	}
	224	if (state->m_has_addon_chip == HAS_ST010 || state->m_has_addon_chip == HAS_ST011)
	225	{
	226	if (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000)
	227	{   st010_write_ram(state, (offset & 0xffff), data);   return;   }
	228	if (offset == 0x600000)
	229	{   st010_set_dr(data);   return;   }
	230	if (offset == 0x600001)
	231	{   st010_set_sr(data);   return;   }
	232	}
	233	if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1
	234	&& (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	235	{
	236	dsp_set_dr(data);
	237	return;
	238	}
	239	if (state->m_cart[0].mode == SNES_MODE_20 && state->m_has_addon_chip == HAS_DSP1)
	240	{
	241	if (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)
	242	{   dsp_set_dr(data);   return;   }
	243	if (offset >= 0x600000 && offset < 0x700000 && (offset & 0x8000) == 0x0000)
	244	{   dsp_set_dr(data);   return;   }
	245	}
	246	if ((state->m_has_addon_chip == HAS_DSP2 || state->m_has_addon_chip == HAS_DSP3)
	247	&& (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
	248	{
	249	if ((offset & 0xffff) < 0xc000)
	250	{   dsp_set_dr(data);   return;   }
	251	else
	252	{   dsp_set_sr(data);   return;   }
	253	}
	254	if (state->m_has_addon_chip == HAS_DSP4
	255	&& (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
	256	{
	257	if ((offset & 0xffff) < 0xc000)
	258	{   dsp_set_dr(data);   return;   }
	259	else
	260	{   dsp_set_sr(data);   return;   }
	261	}
	262
	263	// base cart access
85	264	if (offset < 0x300000)
86	265	snes_w_bank1(space, offset, data, 0xff);
87	266	else if (offset < 0x400000)
r21574	r21575
96	275
97	276	static WRITE8_HANDLER( snes_hi_w )
98	277	{
	278	snes_state *state = space.machine().driver_data<snes_state>();
	279	// take care of add-on chip access
	280	if (state->m_has_addon_chip == HAS_OBC1
	281	&& (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	282	{
	283	obc1_write(space, offset, data, mem_mask);
	284	return;
	285	}
	286	if (state->m_has_addon_chip == HAS_CX4
	287	&& (offset < 0x400000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	288	{
	289	CX4_write(space.machine(), (offset & 0xffff) - 0x6000, data);
	290	return;
	291	}
	292	if (state->m_has_addon_chip == HAS_RTC
	293	&& (offset < 0x400000 && ((offset & 0xffff) == 0x2800 || (offset & 0xffff) == 0x2801)))
	294	{
	295	srtc_write(space.machine(), offset, data);
	296	return;
	297	}
	298	if (state->m_has_addon_chip == HAS_ST010 || state->m_has_addon_chip == HAS_ST011)
	299	{
	300	if (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x1000)
	301	{   st010_write_ram(state, (offset & 0xffff), data);   return;   }
	302	if (offset == 0x600000)
	303	{   st010_set_dr(data);   return;   }
	304	if (offset == 0x600001)
	305	{   st010_set_sr(data);   return;   }
	306	}
	307	if (state->m_cart[0].mode == SNES_MODE_21 && state->m_has_addon_chip == HAS_DSP1
	308	&& (offset < 0x200000 && (offset & 0xffff) >= 0x6000 && (offset & 0xffff) < 0x8000))
	309	{
	310	dsp_set_dr(data);
	311	return;
	312	}
	313	if (state->m_cart[0].mode == SNES_MODE_20 && state->m_has_addon_chip == HAS_DSP1)
	314	{
	315	if (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000)
	316	{   dsp_set_dr(data);   return;   }
	317	if (offset >= 0x600000 && offset < 0x700000 && (offset & 0x8000) == 0x0000)
	318	{   dsp_set_dr(data);   return;   }
	319	}
	320	if ((state->m_has_addon_chip == HAS_DSP2 || state->m_has_addon_chip == HAS_DSP3)
	321	&& (offset >= 0x200000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
	322	{
	323	if ((offset & 0xffff) < 0xc000)
	324	{   dsp_set_dr(data);   return;   }
	325	else
	326	{   dsp_set_sr(data);   return;   }
	327	}
	328	if (state->m_has_addon_chip == HAS_DSP4
	329	&& (offset >= 0x300000 && offset < 0x400000 && (offset & 0x8000) == 0x8000))
	330	{
	331	if ((offset & 0xffff) < 0xc000)
	332	{   dsp_set_dr(data);   return;   }
	333	else
	334	{   dsp_set_sr(data);   return;   }
	335	}
	336
	337	// base cart access
99	338	if (offset < 0x400000)
100	339	snes_w_bank6(space, offset, data, 0xff);
101	340	else
r21574	r21575
121	360	return snes_ram[0xe00000 + offset];
122	361	}
123	362
124		static WRITE8_HANDLER( superfx_w_bank1 )
125		{
126		printf("Attempting to write to cart ROM: %08x = %02x\n", offset, data);
127		// Do nothing; can't write to cart ROM.
128		}
129
130		static WRITE8_HANDLER( superfx_w_bank2 )
131		{
132		printf("Attempting to write to cart ROM: %08x = %02x\n", 0x400000 + offset, data);
133		// Do nothing; can't write to cart ROM.
134		}
135
136	363	static WRITE8_HANDLER( superfx_w_bank3 )
137	364	{
138	365	/* IMPORTANT: SFX RAM sits in 0x600000-0x7fffff, and it's mirrored in 0xe00000-0xffffff. However, SNES
r21574	r21575
155	382	ADDRESS_MAP_END
156	383
157	384	static ADDRESS_MAP_START( superfx_map, AS_PROGRAM, 8, snes_state )
158		AM_RANGE(0x000000, 0x3fffff) AM_READWRITE_LEGACY(superfx_r_bank1, superfx_w_bank1)
159		AM_RANGE(0x400000, 0x5fffff) AM_READWRITE_LEGACY(superfx_r_bank2, superfx_w_bank2)
	385	AM_RANGE(0x000000, 0x3fffff) AM_READ_LEGACY(superfx_r_bank1)
	386	AM_RANGE(0x400000, 0x5fffff) AM_READ_LEGACY(superfx_r_bank2)
160	387	AM_RANGE(0x600000, 0x7dffff) AM_READWRITE_LEGACY(superfx_r_bank3, superfx_w_bank3)
161		AM_RANGE(0x800000, 0xbfffff) AM_READWRITE_LEGACY(superfx_r_bank1, superfx_w_bank1)
162		AM_RANGE(0xc00000, 0xdfffff) AM_READWRITE_LEGACY(superfx_r_bank2, superfx_w_bank2)
	388	AM_RANGE(0x800000, 0xbfffff) AM_READ_LEGACY(superfx_r_bank1)
	389	AM_RANGE(0xc00000, 0xdfffff) AM_READ_LEGACY(superfx_r_bank2)
163	390	AM_RANGE(0xe00000, 0xffffff) AM_READWRITE_LEGACY(superfx_r_bank3, superfx_w_bank3)
164	391	ADDRESS_MAP_END
165	392

trunk/src/mame/includes/snes.h

r21574	r21575
766	766
767	767	extern UINT8  *snes_ram;            /* Main memory */
768	768
	769	// add-on chips IO
	770	void srtc_write(running_machine &machine, UINT16 addr, UINT8 data);
	771	UINT8 srtc_read(address_space &space, UINT16 addr);
	772	extern DECLARE_READ8_HANDLER(obc1_read);
	773	extern DECLARE_WRITE8_HANDLER(obc1_write);
	774	UINT8 CX4_read(UINT32 addr);
	775	void CX4_write(running_machine &machine, UINT32 addr, UINT8 data);
769	776
770	777
771	778	extern struct snes_cart_info snes_cart;

trunk/src/mame/machine/snesobc1.c

r21574	r21575
22	22	static snes_obc1_state obc1_state;
23	23
24	24
25		static READ8_HANDLER( obc1_read )
	25	READ8_HANDLER( obc1_read )
26	26	{
27	27	UINT16 address = offset & 0x1fff;
28	28	UINT8 value;
r21574	r21575
58	58	}
59	59
60	60
61		static WRITE8_HANDLER( obc1_write )
	61	WRITE8_HANDLER( obc1_write )
62	62	{
63	63	UINT16 address = offset & 0x1fff;
64	64	UINT8 temp;

trunk/src/mame/machine/snesrtc.c

r21574	r21575
109	109	return (sum + 1) % 7; // 1900-01-01 was a Monday
110	110	}
111	111
112		static UINT8 srtc_read( address_space &space, UINT16 addr )
	112	UINT8 srtc_read( address_space &space, UINT16 addr )
113	113	{
114	114	addr &= 0xffff;
115	115
r21574	r21575
140	140	return snes_open_bus_r(space, 0);
141	141	}
142	142
143		static void srtc_write( running_machine &machine, UINT16 addr, UINT8 data )
	143	void srtc_write( running_machine &machine, UINT16 addr, UINT8 data )
144	144	{
145	145	addr &= 0xffff;
146	146

trunk/src/mame/machine/snescx4.c

r21574	r21575
15	15
16	16	static CX4 cx4;
17	17
18		static UINT8 CX4_read(UINT32 addr);
19	18	static UINT16 CX4_readw(UINT16 addr);
20	19	static UINT32 CX4_readl(UINT16 addr);
21	20
22		static void CX4_write(running_machine &machine, UINT32 addr, UINT8 data);
23	21	static void CX4_writew(running_machine &machine, UINT16 addr, UINT16 data);
24	22	//static void CX4_writel(running_machine &machine, UINT16 addr, UINT32 data);
25	23
r21574	r21575
118	116	#include "cx4oam.c"
119	117	#include "cx4ops.c"
120	118
121		static void CX4_write(running_machine &machine, UINT32 addr, UINT8 data)
	119	void CX4_write(running_machine &machine, UINT32 addr, UINT8 data)
122	120	{
123	121	addr &= 0x1fff;
124	122
r21574	r21575
214	212	}
215	213	#endif
216	214
217		static UINT8 CX4_read(UINT32 addr)
	215	UINT8 CX4_read(UINT32 addr)
218	216	{
219	217	addr &= 0x1fff;
220	218

trunk/src/mame/machine/snes.c

r21574	r21575
38	38
39	39	#define DMA_REG(a) state->m_dma_regs[a - 0x4300]   // regs 0x4300-0x437f
40	40
41		// DSP accessors
42		#define dsp_get_sr() state->m_upd7725->snesdsp_read(false)
43		#define dsp_get_dr() state->m_upd7725->snesdsp_read(true)
44		#define dsp_set_sr(data) state->m_upd7725->snesdsp_write(false, data)
45		#define dsp_set_dr(data) state->m_upd7725->snesdsp_write(true, data)
46
47		#define st010_get_sr() state->m_upd96050->snesdsp_read(false)
48		#define st010_get_dr() state->m_upd96050->snesdsp_read(true)
49		#define st010_set_sr(data) state->m_upd96050->snesdsp_write(false, data)
50		#define st010_set_dr(data) state->m_upd96050->snesdsp_write(true, data)
51
52	41	// add-on chip emulators
53	42	#include "machine/snesobc1.c"
54	43	#include "machine/snescx4.c"
r21574	r21575
57	46	#include "machine/snes7110.c"
58	47	#include "machine/snesbsx.c"
59	48
60		// ST-010 and ST-011 RAM interface
61		UINT8 st010_read_ram(snes_state *state, UINT16 addr)
62		{
63		UINT16 temp = state->m_upd96050->dataram_r(addr/2);
64		UINT8 res;
65	49
66		if (addr & 1)
67		{
68		res = temp>>8;
69		}
70		else
71		{
72		res = temp & 0xff;
73		}
74
75		return res;
76		}
77
78		void st010_write_ram(snes_state *state, UINT16 addr, UINT8 data)
79		{
80		UINT16 temp = state->m_upd96050->dataram_r(addr/2);
81
82		if (addr & 1)
83		{
84		temp &= 0xff;
85		temp |= data<<8;
86		}
87		else
88		{
89		temp &= 0xff00;
90		temp |= data;
91		}
92
93		state->m_upd96050->dataram_w(addr/2, temp);
94		}
95
96
97	50	VIDEO_START( snes )
98	51	{
99	52	snes_state *state = machine.driver_data<snes_state>();
r21574	r21575
457	410	return superfx_mmio_read(state->m_superfx, offset);
458	411	}
459	412	}
460		else if (state->m_has_addon_chip == HAS_RTC)
461		{
462		if (offset == 0x2800 || offset == 0x2801)
463		{
464		return srtc_read(space, offset);
465		}
466		}
467	413	else if (state->m_has_addon_chip == HAS_SDD1)
468	414	{
469	415	if (offset >= 0x4800 && offset < 0x4808)
r21574	r21575
594	540	return;
595	541	}
596	542	}
597		else if (state->m_has_addon_chip == HAS_RTC)
598		{
599		if (offset == 0x2800 || offset == 0x2801)
600		{
601		srtc_write(space.machine(), offset, data);
602		return;
603		}
604		}
605	543	else if (state->m_has_addon_chip == HAS_SDD1)
606	544	{
607	545	if ((offset >= 0x4300 && offset < 0x4380) ||
r21574	r21575
841	779	else
842	780	value = snes_open_bus_r(space, 0);
843	781	}
844		else if (state->m_has_addon_chip == HAS_OBC1)
845		value = obc1_read(space, offset, mem_mask);
846		else if ((state->m_cart[0].mode == SNES_MODE_21) && (state->m_has_addon_chip == HAS_DSP1) && (offset < 0x100000))
847		value = (address < 0x7000) ? dsp_get_dr() : dsp_get_sr();
848		else if (state->m_has_addon_chip == HAS_CX4)
849		value = CX4_read(address - 0x6000);
850	782	else if (state->m_has_addon_chip == HAS_SPC7110 || state->m_has_addon_chip == HAS_SPC7110_RTC)
851	783	{
852	784	if (offset < 0x10000)
r21574	r21575
858	790	value = snes_open_bus_r(space, 0);                              /* Reserved */
859	791	}
860	792	}
861		else if ((state->m_cart[0].mode == SNES_MODE_20) && (state->m_has_addon_chip == HAS_DSP1) && (offset >= 0x200000))
862		value = (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
863		else if ((state->m_cart[0].mode == SNES_MODE_20) && (state->m_has_addon_chip == HAS_DSP2) && (offset >= 0x200000))
864		value = (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
865		else if ((state->m_has_addon_chip == HAS_DSP3) && (offset >= 0x200000))
866		value = (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
867	793	else
868	794	value = snes_ram[offset];
869	795
r21574	r21575
895	821	else
896	822	value = snes_open_bus_r(space, 0);
897	823	}
898		else if (state->m_has_addon_chip == HAS_OBC1)
899		value = obc1_read (space, offset, mem_mask);
900		else if (state->m_has_addon_chip == HAS_CX4)
901		value = CX4_read(address - 0x6000);
902	824	else if (state->m_has_addon_chip == HAS_SPC7110 || state->m_has_addon_chip == HAS_SPC7110_RTC)
903	825	{
904	826	if (offset < 0x10000)
r21574	r21575
917	839	value = snes_open_bus_r(space, 0);
918	840	}
919	841	}
920		/* some dsp1 games use these banks 0x30 to 0x3f at address 0x8000 */
921		else if ((state->m_cart[0].mode == SNES_MODE_20) && (state->m_has_addon_chip == HAS_DSP1))
922		value = (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
923		else if ((state->m_cart[0].mode == SNES_MODE_20) && (state->m_has_addon_chip == HAS_DSP2))
924		value = (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
925		else if (state->m_has_addon_chip == HAS_DSP3)
926		value = (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
927		else if (state->m_has_addon_chip == HAS_DSP4)
928		value = (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
929	842	else
930	843	value = snes_ram[0x300000 + offset];
931	844
r21574	r21575
984	897	else
985	898	value = snes_open_bus_r(space, 0);
986	899	}
987		else if (state->m_has_addon_chip == HAS_ST010 || state->m_has_addon_chip == HAS_ST011)
988		{
989		if (offset >= 0x80000 && address < 0x1000)
990		{
991		value = st010_read_ram(state, address);
992		}
993		else if (offset <= 1)
994		{
995		value = (address & 1) ? st010_get_sr() : st010_get_dr();
996		}
997		}
998	900	else if (state->m_cart[0].mode & 5)                         /* Mode 20 & 22 */
999	901	{
1000	902	if (address >= 0x8000)
1001	903	value = snes_ram[0x600000 + offset];
1002		/* some other dsp1 games use these banks 0x60 to 0x6f at address 0x0000 */
1003		else if (state->m_has_addon_chip == HAS_DSP1)
1004		value = (address >= 0x4000) ? dsp_get_sr() : dsp_get_dr();
1005	904	else
1006	905	{
1007	906	logerror("(PC=%06x) snes_r_bank4: Unmapped external chip read: %04x\n",space.device().safe_pc(),address);
r21574	r21575
1067	966	{
1068	967	if (state->m_cart[0].mode != SNES_MODE_25)
1069	968	value = space.read_byte(offset);
1070		else if ((state->m_has_addon_chip == HAS_CX4) && (address >= 0x6000))
1071		value = CX4_read(address - 0x6000);
1072	969	else                            /* Mode 25 has SRAM not mirrored from lower banks */
1073	970	{
1074	971	if (address < 0x6000)
r21574	r21575
1085	982	}
1086	983	}
1087	984	}
1088		else if ((state->m_cart[0].mode == SNES_MODE_20) && (state->m_has_addon_chip == HAS_DSP1) && (offset >= 0x200000))
1089		value = (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
1090		else if ((state->m_cart[0].mode == SNES_MODE_20) && (state->m_has_addon_chip == HAS_DSP2) && (offset >= 0x200000))
1091		value = (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
1092		else if ((state->m_has_addon_chip == HAS_DSP3) && (offset >= 0x200000))
1093		value = (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
1094		else if ((state->m_has_addon_chip == HAS_DSP4) && (offset >= 0x300000))
1095		value = (address < 0xc000) ? dsp_get_dr() : dsp_get_sr();
1096	985	else
1097	986	value = snes_ram[0x800000 + offset];
1098	987
r21574	r21575
1134	1023	value = spc7110_bank7_read(space, offset);
1135	1024	else if (state->m_has_addon_chip == HAS_SDD1)
1136	1025	value = sdd1_read(space.machine(), offset);
1137		else if (state->m_has_addon_chip == HAS_ST010 || state->m_has_addon_chip == HAS_ST011)
1138		{
1139		if (offset >= 0x280000 && offset < 0x300000 && address < 0x1000)
1140		{
1141		value = st010_read_ram(state, address);
1142		}
1143		else if (offset >= 0x200000 && offset <= 0x200001)
1144		{
1145		value = (address & 1) ? st010_get_sr() : st010_get_dr();
1146		}
1147		}
1148	1026	else if ((state->m_cart[0].mode & 5) && !(state->m_has_addon_chip == HAS_SUPERFX))      /* Mode 20 & 22 */
1149	1027	{
1150	1028	if (address < 0x8000)
r21574	r21575
1178	1056	{
1179	1057	if (state->m_has_addon_chip == HAS_SUPERFX)
1180	1058	snes_ram[0xf00000 + (offset & 0x1fff)] = data;  // here it should be 0xe00000 but there are mirroring issues
1181		else if (state->m_has_addon_chip == HAS_OBC1)
1182		obc1_write(space, offset, data, mem_mask);
1183		else if ((state->m_cart[0].mode == SNES_MODE_21) && (state->m_has_addon_chip == HAS_DSP1) && (offset < 0x100000))
1184		dsp_set_dr(data);
1185		else if (state->m_has_addon_chip == HAS_CX4)
1186		CX4_write(space.machine(), address - 0x6000, data);
1187	1059	else if (state->m_has_addon_chip == HAS_SPC7110 || state->m_has_addon_chip == HAS_SPC7110_RTC)
1188	1060	{
1189	1061	if (offset < 0x10000)
r21574	r21575
1192	1064	else
1193	1065	logerror("snes_w_bank1: Attempt to write to reserved address: %x = %02x\n", offset, data);
1194	1066	}
1195		else if ((state->m_cart[0].mode == SNES_MODE_20) && (state->m_has_addon_chip == HAS_DSP1) && (offset >= 0x200000))
1196		dsp_set_dr(data);
1197		else if ((state->m_cart[0].mode == SNES_MODE_20) && (state->m_has_addon_chip == HAS_DSP2) && (offset >= 0x200000))
1198		{
1199		if (address < 0xc000)
1200		dsp_set_dr(data);
1201		else
1202		dsp_set_sr(data);
1203		}
1204		else if ((state->m_has_addon_chip == HAS_DSP3) && (offset >= 0x200000))
1205		if (address < 0xc000)
1206		dsp_set_dr(data);
1207		else
1208		dsp_set_sr(data);
1209	1067	else
1210	1068	logerror( "(PC=%06x) Attempt to write to ROM address: %X\n",space.device().safe_pc(),offset );
1211	1069	}
r21574	r21575
1229	1087	{
1230	1088	if (state->m_has_addon_chip == HAS_SUPERFX)
1231	1089	snes_ram[0xf00000 + (offset & 0x1fff)] = data;  // here it should be 0xe00000 but there are mirroring issues
1232		else if (state->m_has_addon_chip == HAS_OBC1)
1233		obc1_write(space, offset, data, mem_mask);
1234		else if (state->m_has_addon_chip == HAS_CX4)
1235		CX4_write(space.machine(), address - 0x6000, data);
1236	1090	else if (state->m_has_addon_chip == HAS_SPC7110 || state->m_has_addon_chip == HAS_SPC7110_RTC)
1237	1091	{
1238	1092	if (offset < 0x10000)
r21574	r21575
1248	1102	else
1249	1103	logerror("snes_w_bank2: Attempt to write to reserved address: %X = %02x\n", offset + 0x300000, data);
1250	1104	}
1251		/* some dsp1 games use these banks 0x30 to 0x3f at address 0x8000 */
1252		else if ((state->m_cart[0].mode == SNES_MODE_20) && (state->m_has_addon_chip == HAS_DSP1))
1253		dsp_set_dr(data);
1254		else if ((state->m_cart[0].mode == SNES_MODE_20) && (state->m_has_addon_chip == HAS_DSP2))
1255		{
1256		if (address < 0xc000)
1257		dsp_set_dr(data);
1258		else
1259		dsp_set_sr(data);
1260		}
1261		else if ((state->m_has_addon_chip == HAS_DSP3) || (state->m_has_addon_chip == HAS_DSP4))
1262		if (address < 0xc000)
1263		dsp_set_dr(data);
1264		else
1265		dsp_set_sr(data);
1266	1105	else
1267	1106	logerror("(PC=%06x) Attempt to write to ROM address: %X\n",space.device().safe_pc(),offset + 0x300000);
1268	1107	}
r21574	r21575
1275	1114
1276	1115	if (state->m_has_addon_chip == HAS_SUPERFX)
1277	1116	snes_ram[0xe00000 + offset] = data;
1278		else if (state->m_has_addon_chip == HAS_ST010 || state->m_has_addon_chip == HAS_ST011)
1279		{
1280		if (offset >= 0x80000 && address < 0x1000)
1281		{
1282		st010_write_ram(state, address, data);
1283		}
1284		else if (offset == 0)
1285		{
1286		st010_set_dr(data);
1287		}
1288		else if (offset == 1)
1289		{
1290		st010_set_sr(data);
1291		}
1292		}
1293	1117	else if (state->m_cart[0].mode & 5)                 /* Mode 20 & 22 */
1294	1118	{
1295	1119	if (address >= 0x8000)
1296	1120	logerror("(PC=%06x) Attempt to write to ROM address: %X\n",space.device().safe_pc(),offset + 0x600000);
1297		else if (state->m_has_addon_chip == HAS_DSP1)
1298		dsp_set_dr(data);
1299	1121	else
1300	1122	logerror("snes_w_bank4: Attempt to write to reserved address: %X = %02x\n", offset + 0x600000, data);
1301	1123	}
r21574	r21575
1343	1165	space.write_byte(offset, data);
1344	1166	else if (address < 0x8000)
1345	1167	{
1346		if ((state->m_has_addon_chip == HAS_CX4) && (address >= 0x6000))
1347		CX4_write(space.machine(), address - 0x6000, data);
1348		else if (state->m_cart[0].mode != SNES_MODE_25)
	1168	if (state->m_cart[0].mode != SNES_MODE_25)
1349	1169	space.write_byte(offset, data);
1350	1170	else    /* Mode 25 has SRAM not mirrored from lower banks */
1351	1171	{
r21574	r21575
1360	1180	logerror("snes_w_bank6: Attempt to write to reserved address: %X = %02x\n", offset + 0x800000, data);
1361	1181	}
1362	1182	}
1363		else if ((state->m_cart[0].mode == SNES_MODE_20) && (state->m_has_addon_chip == HAS_DSP1) && (offset >= 0x200000))
1364		dsp_set_dr(data);
1365		else if ((state->m_cart[0].mode == SNES_MODE_20) && (state->m_has_addon_chip == HAS_DSP2) && (offset >= 0x200000))
1366		{
1367		if (address < 0xc000)
1368		dsp_set_dr(data);
1369		else
1370		dsp_set_sr(data);
1371		}
1372		else if ((state->m_has_addon_chip == HAS_DSP3) && (offset >= 0x200000))
1373		if (address < 0xc000)
1374		dsp_set_dr(data);
1375		else
1376		dsp_set_sr(data);
1377		else if ((state->m_has_addon_chip == HAS_DSP4) && (offset >= 0x300000))
1378		if (address < 0xc000)
1379		dsp_set_dr(data);
1380		else
1381		dsp_set_sr(data);
1382	1183	else
1383	1184	logerror("(PC=%06x) Attempt to write to ROM address: %X\n",space.device().safe_pc(),offset + 0x800000);
1384	1185	}
r21574	r21575
1400	1201	else
1401	1202	logerror("(PC=%06x) Attempt to write to ROM address: %X\n",space.device().safe_pc(),offset + 0xc00000);
1402	1203	}
1403		else if (state->m_has_addon_chip == HAS_ST010 || state->m_has_addon_chip == HAS_ST011)
1404		{
1405		if (offset >= 0x280000 && offset < 0x300000 && address < 0x1000)
1406		{
1407		st010_write_ram(state, address, data);
1408		}
1409		else if (offset == 0x200000)
1410		{
1411		st010_set_dr(data);
1412		}
1413		else if (offset == 0x200001)
1414		{
1415		st010_set_sr(data);
1416		}
1417		}
1418	1204	else if (state->m_cart[0].mode & 5)             /* Mode 20 & 22 */
1419	1205	{
1420	1206	if (address < 0x8000)

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