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r21563 Monday 4th March, 2013 at 12:30:07 UTC by Fabio Priuli
moved some snes stuff into the driver class. nw.
[src/mame/drivers]nss.c sfcbox.c snesb.c
[src/mame/includes]snes.h
[src/mame/machine]snes.c
[src/mess/drivers]snes.c

trunk/src/mess/drivers/snes.c
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724724
725725   MCFG_SCREEN_ADD("screen", RASTER)
726726   MCFG_SCREEN_RAW_PARAMS(DOTCLK_NTSC * 2, SNES_HTOTAL * 2, 0, SNES_SCR_WIDTH * 2, SNES_VTOTAL_NTSC, 0, SNES_SCR_HEIGHT_NTSC)
727   MCFG_SCREEN_UPDATE_DRIVER( snes_state, snes_screen_update )
727   MCFG_SCREEN_UPDATE_DRIVER( snes_state, screen_update )
728728
729729   /* sound hardware */
730730   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
trunk/src/mame/includes/snes.h
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660660   snes_cart_info m_cart[2];   // the second one is used by MESS for Sufami Turbo and, eventually, BS-X
661661
662662   snes_ppu_class        m_ppu;
663   UINT32 snes_screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
663   UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
664664
665665   /* devices */
666666   _5a22_device *m_maincpu;
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677677   DECLARE_DRIVER_INIT(snes_mess);
678678   DECLARE_DRIVER_INIT(snesst);
679679
680   inline int dma_abus_valid(UINT32 address);
681   inline UINT8 abus_read(address_space &space, UINT32 abus);
682   inline void dma_transfer(address_space &space, UINT8 dma, UINT32 abus, UINT16 bbus);
683   inline int is_last_active_channel(int dma);
684   inline UINT32 get_hdma_addr(int dma);
685   inline UINT32 get_hdma_iaddr(int dma);
686   void dma(address_space &space, UINT8 channels);
687   void hdma(address_space &space);
688   void hdma_init(address_space &space);
689   void hdma_update(address_space &space, int dma);
690   void hirq_tick();
680691
681692   TIMER_CALLBACK_MEMBER(snes_nmi_tick);
682693   TIMER_CALLBACK_MEMBER(snes_hirq_tick_callback);
trunk/src/mame/drivers/snesb.c
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646646
647647   MCFG_SCREEN_ADD("screen", RASTER)
648648   MCFG_SCREEN_RAW_PARAMS(DOTCLK_NTSC, SNES_HTOTAL, 0, SNES_SCR_WIDTH, SNES_VTOTAL_NTSC, 0, SNES_SCR_HEIGHT_NTSC)
649   MCFG_SCREEN_UPDATE_DRIVER( snes_state, snes_screen_update )
649   MCFG_SCREEN_UPDATE_DRIVER( snes_state, screen_update )
650650
651651   /* sound hardware */
652652   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
trunk/src/mame/drivers/nss.c
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793793INPUT_PORTS_END
794794
795795
796static MACHINE_CONFIG_START( snes, nss_state )
797
798   /* basic machine hardware */
799   MCFG_CPU_ADD("maincpu", _5A22, MCLK_NTSC)   /* 2.68Mhz, also 3.58Mhz */
800   MCFG_CPU_PROGRAM_MAP(snes_map)
801
802   MCFG_CPU_ADD("soundcpu", SPC700, 2048000/2) /* 2.048 Mhz, but internal divider */
803   MCFG_CPU_PROGRAM_MAP(spc_mem)
804
805   MCFG_QUANTUM_PERFECT_CPU("maincpu")
806
807   /* video hardware */
808   MCFG_VIDEO_START( snes )
809
810   MCFG_SCREEN_ADD("screen", RASTER)
811   MCFG_SCREEN_RAW_PARAMS(DOTCLK_NTSC, SNES_HTOTAL, 0, SNES_SCR_WIDTH, SNES_VTOTAL_NTSC, 0, SNES_SCR_HEIGHT_NTSC)
812   MCFG_SCREEN_UPDATE_DRIVER( snes_state, snes_screen_update )
813
814   /* sound hardware */
815   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
816   MCFG_SOUND_ADD("spc700", SNES, 0)
817   MCFG_SOUND_ROUTE(0, "lspeaker", 1.00)
818   MCFG_SOUND_ROUTE(1, "rspeaker", 1.00)
819MACHINE_CONFIG_END
820
821796INTERRUPT_GEN_MEMBER(nss_state::nss_vblank_irq)
822797{
823798   if(m_nmi_enable)
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841816   "osd"
842817};
843818
844static MACHINE_CONFIG_DERIVED( nss, snes )
819static MACHINE_CONFIG_START( nss, nss_state )
845820
821   /* base snes hardware */
822   MCFG_CPU_ADD("maincpu", _5A22, MCLK_NTSC)   /* 2.68Mhz, also 3.58Mhz */
823   MCFG_CPU_PROGRAM_MAP(snes_map)
824
825   MCFG_CPU_ADD("soundcpu", SPC700, 2048000/2) /* 2.048 Mhz, but internal divider */
826   MCFG_CPU_PROGRAM_MAP(spc_mem)
827
828   MCFG_QUANTUM_PERFECT_CPU("maincpu")
829
830   /* nss hardware */
846831   MCFG_CPU_ADD("bios", Z80, 4000000)
847832   MCFG_CPU_PROGRAM_MAP(bios_map)
848833   MCFG_CPU_IO_MAP(bios_io_map)
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853838   MCFG_RP5H01_ADD("rp5h01")
854839   MCFG_M6M80011AP_ADD("m6m80011ap")
855840
841   /* sound hardware */
842   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
843   MCFG_SOUND_ADD("spc700", SNES, 0)
844   MCFG_SOUND_ROUTE(0, "lspeaker", 1.00)
845   MCFG_SOUND_ROUTE(1, "rspeaker", 1.00)
846
847   /* video hardware */
848   MCFG_VIDEO_START( snes )
849
856850   /* TODO: the screen should actually superimpose, but for the time being let's just separate outputs */
857851   MCFG_DEFAULT_LAYOUT(layout_dualhsxs)
858852
853   // SNES PPU
854   MCFG_SCREEN_ADD("screen", RASTER)
855   MCFG_SCREEN_RAW_PARAMS(DOTCLK_NTSC, SNES_HTOTAL, 0, SNES_SCR_WIDTH, SNES_VTOTAL_NTSC, 0, SNES_SCR_HEIGHT_NTSC)
856   MCFG_SCREEN_UPDATE_DRIVER( snes_state, screen_update )
857
858   // NSS
859859   MCFG_SCREEN_ADD("osd", RASTER)
860860   MCFG_SCREEN_REFRESH_RATE(60)
861861   MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
trunk/src/mame/drivers/sfcbox.c
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148148   DECLARE_WRITE8_MEMBER( port_83_w );
149149   DECLARE_WRITE8_MEMBER( snes_map_0_w );
150150   DECLARE_WRITE8_MEMBER( snes_map_1_w );
151   DECLARE_MACHINE_START(sfcbox);
152   DECLARE_MACHINE_RESET(sfcbox);
151   virtual void machine_start();
152   virtual void machine_reset();
153153   DECLARE_READ8_MEMBER(spc_ram_100_r);
154154   DECLARE_WRITE8_MEMBER(spc_ram_100_w);
155155};
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438438#endif
439439INPUT_PORTS_END
440440
441static MACHINE_CONFIG_START( snes, sfcbox_state )
442
443   /* basic machine hardware */
444   MCFG_CPU_ADD("maincpu", _5A22, 3580000*6)   /* 2.68Mhz, also 3.58Mhz */
445   MCFG_CPU_PROGRAM_MAP(snes_map)
446
447   MCFG_CPU_ADD("soundcpu", SPC700, 2048000/2) /* 2.048 Mhz, but internal divider */
448   MCFG_CPU_PROGRAM_MAP(spc_mem)
449
450   MCFG_QUANTUM_PERFECT_CPU("maincpu")
451
452   MCFG_MACHINE_START( snes )
453   MCFG_MACHINE_RESET( snes )
454
455   /* video hardware */
456   MCFG_VIDEO_START( snes )
457
458   MCFG_SCREEN_ADD("screen", RASTER)
459   MCFG_SCREEN_RAW_PARAMS(DOTCLK_NTSC, SNES_HTOTAL, 0, SNES_SCR_WIDTH, SNES_VTOTAL_NTSC, 0, SNES_SCR_HEIGHT_NTSC)
460   MCFG_SCREEN_UPDATE_DRIVER( snes_state, snes_screen_update )
461
462   /* sound hardware */
463   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
464   MCFG_SOUND_ADD("spc700", SNES, 0)
465   MCFG_SOUND_ROUTE(0, "lspeaker", 1.00)
466   MCFG_SOUND_ROUTE(1, "rspeaker", 1.00)
467MACHINE_CONFIG_END
468
469
470MACHINE_START_MEMBER(sfcbox_state,sfcbox)
441void sfcbox_state::machine_start()
471442{
472443   MACHINE_START_CALL_LEGACY(snes);
473444
474445   m_is_sfcbox = 1;
475446}
476447
477MACHINE_RESET_MEMBER(sfcbox_state,sfcbox)
448void sfcbox_state::machine_reset()
478449{
479450   MACHINE_RESET_CALL_LEGACY( snes );
480451
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483454   m_soundcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
484455}
485456
486static MACHINE_CONFIG_DERIVED( sfcbox, snes )
457static MACHINE_CONFIG_START( sfcbox, sfcbox_state )
487458
459   /* base snes hardware */
460   MCFG_CPU_ADD("maincpu", _5A22, 3580000*6)   /* 2.68Mhz, also 3.58Mhz */
461   MCFG_CPU_PROGRAM_MAP(snes_map)
462
463   MCFG_CPU_ADD("soundcpu", SPC700, 2048000/2) /* 2.048 Mhz, but internal divider */
464   MCFG_CPU_PROGRAM_MAP(spc_mem)
465
466   MCFG_QUANTUM_PERFECT_CPU("maincpu")
467
468   /* sfcbox hardware */
488469   MCFG_CPU_ADD("bios", Z180, XTAL_12MHz / 2)  /* HD64180RF6X */
489470   MCFG_CPU_PROGRAM_MAP(sfcbox_map)
490471   MCFG_CPU_IO_MAP(sfcbox_io)
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492473   MCFG_MB90082_ADD("mb90082",XTAL_12MHz / 2) /* TODO: correct clock */
493474   MCFG_S3520CF_ADD("s3520cf") /* RTC */
494475
495   MCFG_MACHINE_START_OVERRIDE(sfcbox_state, sfcbox )
496   MCFG_MACHINE_RESET_OVERRIDE(sfcbox_state, sfcbox )
476   /* sound hardware */
477   MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
478   MCFG_SOUND_ADD("spc700", SNES, 0)
479   MCFG_SOUND_ROUTE(0, "lspeaker", 1.00)
480   MCFG_SOUND_ROUTE(1, "rspeaker", 1.00)
497481
482   /* video hardware */
483   MCFG_VIDEO_START( snes )
484
498485   /* TODO: the screen should actually superimpose, but for the time being let's just separate outputs */
499486   MCFG_DEFAULT_LAYOUT(layout_dualhsxs)
500487
488   // SNES PPU
489   MCFG_SCREEN_ADD("screen", RASTER)
490   MCFG_SCREEN_RAW_PARAMS(DOTCLK_NTSC, SNES_HTOTAL, 0, SNES_SCR_WIDTH, SNES_VTOTAL_NTSC, 0, SNES_SCR_HEIGHT_NTSC)
491   MCFG_SCREEN_UPDATE_DRIVER( snes_state, screen_update )
492
493   // SFCBOX
501494   MCFG_SCREEN_ADD("osd", RASTER)
502495   MCFG_SCREEN_REFRESH_RATE(60)
503496   MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
trunk/src/mame/machine/snes.c
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3131/* -- Globals -- */
3232UINT8  *snes_ram = NULL;        /* 65816 ram */
3333
34static void snes_dma(address_space &space, UINT8 channels);
35static void snes_hdma_init(address_space &space);
36static void snes_hdma(address_space &space);
37
3834static DECLARE_READ8_HANDLER(snes_io_dma_r);
3935static DECLARE_WRITE8_HANDLER(snes_io_dma_w);
4036
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10298   state->m_ppu.ppu_start(machine);
10399}
104100
105UINT32 snes_state::snes_screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
101UINT32 snes_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
106102{
107103   /* NTSC SNES draw range is 1-225. */
108104   for (int y = cliprect.min_y; y <= cliprect.max_y; y++)
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127123   m_nmi_timer->adjust(attotime::never);
128124}
129125
130static void snes_hirq_tick( running_machine &machine )
126void snes_state::hirq_tick()
131127{
132   snes_state *state = machine.driver_data<snes_state>();
133
134128   // latch the counters and pull IRQ
135129   // (don't need to switch to the 65816 context, we don't do anything dependant on it)
136   state->m_ppu.latch_counters(machine);
130   m_ppu.latch_counters(machine());
137131   snes_ram[TIMEUP] = 0x80;    /* Indicate that irq occurred */
138   state->m_maincpu->set_input_line(G65816_LINE_IRQ, ASSERT_LINE);
132   m_maincpu->set_input_line(G65816_LINE_IRQ, ASSERT_LINE);
139133
140134   // don't happen again
141   state->m_hirq_timer->adjust(attotime::never);
135   m_hirq_timer->adjust(attotime::never);
142136}
143137
144138TIMER_CALLBACK_MEMBER(snes_state::snes_hirq_tick_callback)
145139{
146   snes_hirq_tick(machine());
140   hirq_tick();
147141}
148142
149143TIMER_CALLBACK_MEMBER(snes_state::snes_reset_oam_address)
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162156TIMER_CALLBACK_MEMBER(snes_state::snes_reset_hdma)
163157{
164158   address_space &cpu0space = m_maincpu->space(AS_PROGRAM);
165   snes_hdma_init(cpu0space);
159   hdma_init(cpu0space);
166160}
167161
168162TIMER_CALLBACK_MEMBER(snes_state::snes_update_io)
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213207//          printf("HIRQ @ %d, %d\n", pixel * m_ppu.m_htmult, m_ppu.m_beam.current_vert);
214208         if (pixel == 0)
215209         {
216            snes_hirq_tick(machine());
210            hirq_tick();
217211         }
218212         else
219213         {
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244238   if (m_ppu.m_beam.current_vert == 0)
245239   {
246240      address_space &cpu0space = m_maincpu->space(AS_PROGRAM);
247      snes_hdma_init(cpu0space);
241      hdma_init(cpu0space);
248242   }
249243
250244   if (m_ppu.m_beam.current_vert == 0)
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281275      {
282276         /* Do HDMA */
283277         if (snes_ram[HDMAEN])
284            snes_hdma(cpu0space);
278            hdma(cpu0space);
285279
286280         machine().primary_screen->update_partial((m_ppu.m_interlace == 2) ? (m_ppu.m_beam.current_vert * m_ppu.m_interlace) : m_ppu.m_beam.current_vert - 1);
287281      }
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727721         state->m_vtime &= 0x1ff;
728722         return;
729723      case MDMAEN:    /* DMA channel designation and trigger */
730         snes_dma(space, data);
724         state->dma(space, data);
731725         data = 0;   /* Once DMA is done we need to reset all bits to 0 */
732726         break;
733727      case HDMAEN:    /* HDMA channel designation */
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19491943
19501944*************************************/
19511945
1952INLINE int dma_abus_valid( UINT32 address )
1946inline int snes_state::dma_abus_valid( UINT32 address )
19531947{
19541948   if((address & 0x40ff00) == 0x2100) return 0;  //$[00-3f|80-bf]:[2100-21ff]
19551949   if((address & 0x40fe00) == 0x4000) return 0;  //$[00-3f|80-bf]:[4000-41ff]
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19591953   return 1;
19601954}
19611955
1962INLINE UINT8 snes_abus_read( address_space &space, UINT32 abus )
1956inline UINT8 snes_state::abus_read( address_space &space, UINT32 abus )
19631957{
19641958   if (!dma_abus_valid(abus))
19651959      return 0;
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19671961   return space.read_byte(abus);
19681962}
19691963
1970INLINE void snes_dma_transfer( address_space &space, UINT8 dma, UINT32 abus, UINT16 bbus )
1964inline void snes_state::dma_transfer( address_space &space, UINT8 dma, UINT32 abus, UINT16 bbus )
19711965{
1972   snes_state *state = space.machine().driver_data<snes_state>();
1973
1974   if (state->m_dma_channel[dma].dmap & 0x80)  /* PPU->CPU */
1966   if (m_dma_channel[dma].dmap & 0x80)  /* PPU->CPU */
19751967   {
19761968      if (bbus == 0x2180 && ((abus & 0xfe0000) == 0x7e0000 || (abus & 0x40e000) == 0x0000))
19771969      {
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20001992      }
20011993      else
20021994      {
2003         space.write_byte(bbus, snes_abus_read(space, abus));
1995         space.write_byte(bbus, abus_read(space, abus));
20041996         return;
20051997      }
20061998   }
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20082000
20092001/* WIP: These have the advantage to automatically update the address, but then we would need to
20102002check again if the transfer is direct/indirect at each step... is it worth? */
2011INLINE UINT32 snes_get_hdma_addr( running_machine &machine, int dma )
2003inline UINT32 snes_state::get_hdma_addr( int dma )
20122004{
2013   snes_state *state = machine.driver_data<snes_state>();
2014   return (state->m_dma_channel[dma].bank << 16) | (state->m_dma_channel[dma].hdma_addr++);
2005   return (m_dma_channel[dma].bank << 16) | (m_dma_channel[dma].hdma_addr++);
20152006}
20162007
2017INLINE UINT32 snes_get_hdma_iaddr( running_machine &machine, int dma )
2008inline UINT32 snes_state::get_hdma_iaddr( int dma )
20182009{
2019   snes_state *state = machine.driver_data<snes_state>();
2020   return (state->m_dma_channel[dma].ibank << 16) | (state->m_dma_channel[dma].trans_size++);
2010   return (m_dma_channel[dma].ibank << 16) | (m_dma_channel[dma].trans_size++);
20212011}
20222012
2023INLINE int is_last_active_channel( running_machine &machine, int dma )
2013inline int snes_state::is_last_active_channel( int dma )
20242014{
2025   snes_state *state = machine.driver_data<snes_state>();
2026   int i;
2027
2028   for (i = dma + 1; i < 8; i++)
2015   for (int i = dma + 1; i < 8; i++)
20292016   {
2030      if (BIT(state->m_hdmaen, i) && state->m_dma_channel[i].hdma_line_counter)
2017      if (BIT(m_hdmaen, i) && m_dma_channel[i].hdma_line_counter)
20312018         return 0;   // there is still at least another channel with incomplete HDMA
20322019   }
20332020
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20352022   return 1;
20362023}
20372024
2038static void snes_hdma_update( address_space &space, int dma )
2025void snes_state::hdma_update( address_space &space, int dma )
20392026{
2040   snes_state *state = space.machine().driver_data<snes_state>();
2041   UINT32 abus = snes_get_hdma_addr(space.machine(), dma);
2027   UINT32 abus = get_hdma_addr(dma);
20422028
2043   state->m_dma_channel[dma].hdma_line_counter = snes_abus_read(space, abus);
2029   m_dma_channel[dma].hdma_line_counter = abus_read(space, abus);
20442030
2045   if (state->m_dma_channel[dma].dmap & 0x40)
2031   if (m_dma_channel[dma].dmap & 0x40)
20462032   {
20472033      /* One oddity: if $43xA is 0 and this is the last active HDMA channel for this scanline, only load
20482034      one byte for Address, and use the $00 for the low byte. So Address ends up incremented one less than
20492035      otherwise expected */
20502036
2051      abus = snes_get_hdma_addr(space.machine(), dma);
2052      state->m_dma_channel[dma].trans_size = snes_abus_read(space, abus) << 8;
2037      abus = get_hdma_addr(dma);
2038      m_dma_channel[dma].trans_size = abus_read(space, abus) << 8;
20532039
2054      if (state->m_dma_channel[dma].hdma_line_counter || !is_last_active_channel(space.machine(), dma))
2040      if (m_dma_channel[dma].hdma_line_counter || !is_last_active_channel(dma))
20552041      {
20562042         // we enter here if we have more transfers to be done or if there are other active channels after this one
2057         abus = snes_get_hdma_addr(space.machine(), dma);
2058         state->m_dma_channel[dma].trans_size >>= 8;
2059         state->m_dma_channel[dma].trans_size |= snes_abus_read(space, abus) << 8;
2043         abus = get_hdma_addr(dma);
2044         m_dma_channel[dma].trans_size >>= 8;
2045         m_dma_channel[dma].trans_size |= abus_read(space, abus) << 8;
20602046      }
20612047   }
20622048
2063   if (!state->m_dma_channel[dma].hdma_line_counter)
2064      state->m_hdmaen &= ~(1 << dma);
2049   if (!m_dma_channel[dma].hdma_line_counter)
2050      m_hdmaen &= ~(1 << dma);
20652051
2066   state->m_dma_channel[dma].do_transfer = 1;
2052   m_dma_channel[dma].do_transfer = 1;
20672053}
20682054
2069static void snes_hdma_init( address_space &space )
2055void snes_state::hdma_init( address_space &space )
20702056{
2071   snes_state *state = space.machine().driver_data<snes_state>();
2072   int i;
2073
2074   state->m_hdmaen = snes_ram[HDMAEN];
2075   for (i = 0; i < 8; i++)
2057   m_hdmaen = snes_ram[HDMAEN];
2058   for (int i = 0; i < 8; i++)
20762059   {
2077      if (BIT(state->m_hdmaen, i))
2060      if (BIT(m_hdmaen, i))
20782061      {
2079         state->m_dma_channel[i].hdma_addr = state->m_dma_channel[i].src_addr;
2080         snes_hdma_update(space, i);
2062         m_dma_channel[i].hdma_addr = m_dma_channel[i].src_addr;
2063         hdma_update(space, i);
20812064      }
20822065   }
20832066}
20842067
2085static void snes_hdma( address_space &space )
2068void snes_state::hdma( address_space &space )
20862069{
2087   snes_state *state = space.machine().driver_data<snes_state>();
20882070   UINT16 bbus;
20892071   UINT32 abus;
2090   int i;
20912072
2092   for (i = 0; i < 8; i++)
2073   for (int i = 0; i < 8; i++)
20932074   {
2094      if (BIT(state->m_hdmaen, i))
2075      if (BIT(m_hdmaen, i))
20952076      {
2096         if (state->m_dma_channel[i].do_transfer)
2077         if (m_dma_channel[i].do_transfer)
20972078         {
20982079            /* Get transfer addresses */
2099            if (state->m_dma_channel[i].dmap & 0x40)    /* Indirect */
2100               abus = (state->m_dma_channel[i].ibank << 16) + state->m_dma_channel[i].trans_size;
2080            if (m_dma_channel[i].dmap & 0x40)    /* Indirect */
2081               abus = (m_dma_channel[i].ibank << 16) + m_dma_channel[i].trans_size;
21012082            else                                    /* Absolute */
2102               abus = (state->m_dma_channel[i].bank << 16) + state->m_dma_channel[i].hdma_addr;
2083               abus = (m_dma_channel[i].bank << 16) + m_dma_channel[i].hdma_addr;
21032084
2104            bbus = state->m_dma_channel[i].dest_addr + 0x2100;
2085            bbus = m_dma_channel[i].dest_addr + 0x2100;
21052086
21062087
21072088
2108            switch (state->m_dma_channel[i].dmap & 0x07)
2089            switch (m_dma_channel[i].dmap & 0x07)
21092090            {
21102091            case 0:     /* 1 register write once             (1 byte:  p               ) */
2111               snes_dma_transfer(space, i, abus++, bbus);
2092               dma_transfer(space, i, abus++, bbus);
21122093               break;
21132094            case 5:     /* 2 registers write twice alternate (4 bytes: p, p+1, p,   p+1) */
2114               snes_dma_transfer(space, i, abus++, bbus);
2115               snes_dma_transfer(space, i, abus++, bbus + 1);
2116               snes_dma_transfer(space, i, abus++, bbus);
2117               snes_dma_transfer(space, i, abus++, bbus + 1);
2095               dma_transfer(space, i, abus++, bbus);
2096               dma_transfer(space, i, abus++, bbus + 1);
2097               dma_transfer(space, i, abus++, bbus);
2098               dma_transfer(space, i, abus++, bbus + 1);
21182099               break;
21192100            case 1:     /* 2 registers write once            (2 bytes: p, p+1          ) */
2120               snes_dma_transfer(space, i, abus++, bbus);
2121               snes_dma_transfer(space, i, abus++, bbus + 1);
2101               dma_transfer(space, i, abus++, bbus);
2102               dma_transfer(space, i, abus++, bbus + 1);
21222103               break;
21232104            case 2:     /* 1 register write twice            (2 bytes: p, p            ) */
21242105            case 6:
2125               snes_dma_transfer(space, i, abus++, bbus);
2126               snes_dma_transfer(space, i, abus++, bbus);
2106               dma_transfer(space, i, abus++, bbus);
2107               dma_transfer(space, i, abus++, bbus);
21272108               break;
21282109            case 3:     /* 2 registers write twice each      (4 bytes: p, p,   p+1, p+1) */
21292110            case 7:
2130               snes_dma_transfer(space, i, abus++, bbus);
2131               snes_dma_transfer(space, i, abus++, bbus);
2132               snes_dma_transfer(space, i, abus++, bbus + 1);
2133               snes_dma_transfer(space, i, abus++, bbus + 1);
2111               dma_transfer(space, i, abus++, bbus);
2112               dma_transfer(space, i, abus++, bbus);
2113               dma_transfer(space, i, abus++, bbus + 1);
2114               dma_transfer(space, i, abus++, bbus + 1);
21342115               break;
21352116            case 4:     /* 4 registers write once            (4 bytes: p, p+1, p+2, p+3) */
2136               snes_dma_transfer(space, i, abus++, bbus);
2137               snes_dma_transfer(space, i, abus++, bbus + 1);
2138               snes_dma_transfer(space, i, abus++, bbus + 2);
2139               snes_dma_transfer(space, i, abus++, bbus + 3);
2117               dma_transfer(space, i, abus++, bbus);
2118               dma_transfer(space, i, abus++, bbus + 1);
2119               dma_transfer(space, i, abus++, bbus + 2);
2120               dma_transfer(space, i, abus++, bbus + 3);
21402121               break;
21412122            default:
21422123#ifdef MAME_DEBUG
2143               mame_printf_debug( "  HDMA of unsupported type: %d\n", state->m_dma_channel[i].dmap & 0x07);
2124               mame_printf_debug( "  HDMA of unsupported type: %d\n", m_dma_channel[i].dmap & 0x07);
21442125#endif
21452126               break;
21462127            }
21472128
2148            if (state->m_dma_channel[i].dmap & 0x40)    /* Indirect */
2149               state->m_dma_channel[i].trans_size = abus;
2129            if (m_dma_channel[i].dmap & 0x40)    /* Indirect */
2130               m_dma_channel[i].trans_size = abus;
21502131            else                                    /* Absolute */
2151               state->m_dma_channel[i].hdma_addr = abus;
2132               m_dma_channel[i].hdma_addr = abus;
21522133
21532134         }
21542135      }
21552136   }
21562137
2157   for (i = 0; i < 8; i++)
2138   for (int i = 0; i < 8; i++)
21582139   {
2159      if (BIT(state->m_hdmaen, i))
2140      if (BIT(m_hdmaen, i))
21602141      {
2161         state->m_dma_channel[i].do_transfer = (--state->m_dma_channel[i].hdma_line_counter) & 0x80;
2142         m_dma_channel[i].do_transfer = (--m_dma_channel[i].hdma_line_counter) & 0x80;
21622143
2163         if (!(state->m_dma_channel[i].hdma_line_counter & 0x7f))
2164            snes_hdma_update(space, i);
2144         if (!(m_dma_channel[i].hdma_line_counter & 0x7f))
2145            hdma_update(space, i);
21652146      }
21662147   }
21672148}
21682149
2169static void snes_dma( address_space &space, UINT8 channels )
2150void snes_state::dma( address_space &space, UINT8 channels )
21702151{
2171   snes_state *state = space.machine().driver_data<snes_state>();
2172   int i;
21732152   INT8 increment;
21742153   UINT16 bbus;
21752154   UINT32 abus, abus_bank;
r21562r21563
21782157   /* FIXME: we also need to round to the nearest 8 master cycles */
21792158
21802159   /* Assume priority of the 8 DMA channels is 0-7 */
2181   for (i = 0; i < 8; i++)
2160   for (int i = 0; i < 8; i++)
21822161   {
21832162      if (BIT(channels, i))
21842163      {
21852164         /* FIXME: the following should be used to stop DMA if the same channel is used by HDMA (being set to 1 in snes_hdma)
21862165          However, this cannot be implemented as is atm, because currently DMA transfers always happen as soon as they are enabled... */
2187         state->m_dma_channel[i].dma_disabled = 0;
2166         m_dma_channel[i].dma_disabled = 0;
21882167
21892168         //printf( "Making a transfer on channel %d\n", i );
21902169         /* Find transfer addresses */
2191         abus = state->m_dma_channel[i].src_addr;
2192         abus_bank = state->m_dma_channel[i].bank << 16;
2193         bbus = state->m_dma_channel[i].dest_addr + 0x2100;
2170         abus = m_dma_channel[i].src_addr;
2171         abus_bank = m_dma_channel[i].bank << 16;
2172         bbus = m_dma_channel[i].dest_addr + 0x2100;
21942173
21952174         //printf("Address: %06x\n", abus | abus_bank);
21962175         /* Auto increment */
2197         if (state->m_dma_channel[i].dmap & 0x8)
2176         if (m_dma_channel[i].dmap & 0x8)
21982177            increment = 0;
21992178         else
22002179         {
2201            if (state->m_dma_channel[i].dmap & 0x10)
2180            if (m_dma_channel[i].dmap & 0x10)
22022181               increment = -1;
22032182            else
22042183               increment = 1;
22052184         }
22062185
22072186         /* Number of bytes to transfer */
2208         length = state->m_dma_channel[i].trans_size;
2187         length = m_dma_channel[i].trans_size;
22092188
2210//          printf( "DMA-Ch %d: len: %X, abus: %X, bbus: %X, incr: %d, dir: %s, type: %d\n", i, length, abus | abus_bank, bbus, increment, state->m_dma_channel[i].dmap & 0x80 ? "PPU->CPU" : "CPU->PPU", state->m_dma_channel[i].dmap & 0x07);
2189//          printf( "DMA-Ch %d: len: %X, abus: %X, bbus: %X, incr: %d, dir: %s, type: %d\n", i, length, abus | abus_bank, bbus, increment, m_dma_channel[i].dmap & 0x80 ? "PPU->CPU" : "CPU->PPU", m_dma_channel[i].dmap & 0x07);
22112190
22122191#ifdef SNES_DBG_DMA
2213         mame_printf_debug( "DMA-Ch %d: len: %X, abus: %X, bbus: %X, incr: %d, dir: %s, type: %d\n", i, length, abus | abus_bank, bbus, increment, state->m_dma_channel[i].dmap & 0x80 ? "PPU->CPU" : "CPU->PPU", state->m_dma_channel[i].dmap & 0x07);
2192         mame_printf_debug( "DMA-Ch %d: len: %X, abus: %X, bbus: %X, incr: %d, dir: %s, type: %d\n", i, length, abus | abus_bank, bbus, increment, m_dma_channel[i].dmap & 0x80 ? "PPU->CPU" : "CPU->PPU", m_dma_channel[i].dmap & 0x07);
22142193#endif
22152194
2216         switch (state->m_dma_channel[i].dmap & 0x07)
2195         switch (m_dma_channel[i].dmap & 0x07)
22172196         {
22182197            case 0:     /* 1 register write once */
22192198            case 2:     /* 1 register write twice */
22202199            case 6:     /* 1 register write twice */
22212200               do
22222201               {
2223                  snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
2202                  dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
22242203                  abus += increment;
2225               } while (--length && !state->m_dma_channel[i].dma_disabled);
2204               } while (--length && !m_dma_channel[i].dma_disabled);
22262205               break;
22272206            case 1:     /* 2 registers write once */
22282207            case 5:     /* 2 registers write twice alternate */
22292208               do
22302209               {
2231                  snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
2210                  dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
22322211                  abus += increment;
2233                  if (!(--length) || state->m_dma_channel[i].dma_disabled)
2212                  if (!(--length) || m_dma_channel[i].dma_disabled)
22342213                     break;
2235                  snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
2214                  dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
22362215                  abus += increment;
2237               } while (--length && !state->m_dma_channel[i].dma_disabled);
2216               } while (--length && !m_dma_channel[i].dma_disabled);
22382217               break;
22392218            case 3:     /* 2 registers write twice each */
22402219            case 7:     /* 2 registers write twice each */
22412220               do
22422221               {
2243                  snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
2222                  dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
22442223                  abus += increment;
2245                  if (!(--length) || state->m_dma_channel[i].dma_disabled)
2224                  if (!(--length) || m_dma_channel[i].dma_disabled)
22462225                     break;
2247                  snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
2226                  dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
22482227                  abus += increment;
2249                  if (!(--length) || state->m_dma_channel[i].dma_disabled)
2228                  if (!(--length) || m_dma_channel[i].dma_disabled)
22502229                     break;
2251                  snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
2230                  dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
22522231                  abus += increment;
2253                  if (!(--length) || state->m_dma_channel[i].dma_disabled)
2232                  if (!(--length) || m_dma_channel[i].dma_disabled)
22542233                     break;
2255                  snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
2234                  dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
22562235                  abus += increment;
2257               } while (--length && !state->m_dma_channel[i].dma_disabled);
2236               } while (--length && !m_dma_channel[i].dma_disabled);
22582237               break;
22592238            case 4:     /* 4 registers write once */
22602239               do
22612240               {
2262                  snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
2241                  dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
22632242                  abus += increment;
2264                  if (!(--length) || state->m_dma_channel[i].dma_disabled)
2243                  if (!(--length) || m_dma_channel[i].dma_disabled)
22652244                     break;
2266                  snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
2245                  dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
22672246                  abus += increment;
2268                  if (!(--length) || state->m_dma_channel[i].dma_disabled)
2247                  if (!(--length) || m_dma_channel[i].dma_disabled)
22692248                     break;
2270                  snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 2);
2249                  dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 2);
22712250                  abus += increment;
2272                  if (!(--length) || state->m_dma_channel[i].dma_disabled)
2251                  if (!(--length) || m_dma_channel[i].dma_disabled)
22732252                     break;
2274                  snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 3);
2253                  dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 3);
22752254                  abus += increment;
2276               } while (--length && !state->m_dma_channel[i].dma_disabled);
2255               } while (--length && !m_dma_channel[i].dma_disabled);
22772256               break;
22782257            default:
22792258#ifdef MAME_DEBUG
2280               mame_printf_debug("  DMA of unsupported type: %d\n", state->m_dma_channel[i].dmap & 0x07);
2259               mame_printf_debug("  DMA of unsupported type: %d\n", m_dma_channel[i].dmap & 0x07);
22812260#endif
22822261               break;
22832262         }
22842263
22852264         /* We're done, so write the new abus back to the registers */
2286         state->m_dma_channel[i].src_addr = abus;
2287         state->m_dma_channel[i].trans_size = 0;
2265         m_dma_channel[i].src_addr = abus;
2266         m_dma_channel[i].trans_size = 0;
22882267      }
22892268   }
22902269

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