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r21477 Thursday 28th February, 2013 at 03:04:48 UTC by R. Belmont
(nw)
[src/emu/cpu/sh2]sh2.h sh2comn.c sh2comn.h sh2drc.c

trunk/src/emu/cpu/sh2/sh2comn.h
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9090      sh2_exception(sh2,message,irq);         \
9191} while(0)
9292
93/* fast RAM info */
94struct fast_ram_info
95{
96   offs_t              start;                      /* start of the RAM block */
97   offs_t              end;                        /* end of the RAM block */
98   UINT8               readonly;                   /* TRUE if read-only */
99   void *              base;                       /* base in memory where the RAM lives */
100};
101
93102struct sh2_state
94103{
95104   UINT32  ppc;
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186195   uml::code_handle *  interrupt;              /* interrupt */
187196   uml::code_handle *  nocode;                 /* nocode */
188197   uml::code_handle *  out_of_cycles;              /* out of cycles exception handler */
198
199   /* fast RAM */
200   UINT32              fastram_select;
201   fast_ram_info       fastram[SH2_MAX_FASTRAM];
189202#endif
190203};
191204
trunk/src/emu/cpu/sh2/sh2.h
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8484#define SH2DRC_COMPATIBLE_OPTIONS   (SH2DRC_STRICT_VERIFY | SH2DRC_FLUSH_PC | SH2DRC_STRICT_PCREL)
8585#define SH2DRC_FASTEST_OPTIONS  (0)
8686
87enum
88{
89   CPUINFO_INT_SH2_DRC_OPTIONS = CPUINFO_INT_CPU_SPECIFIC,
90
91   CPUINFO_INT_SH2_FASTRAM_SELECT,
92   CPUINFO_INT_SH2_FASTRAM_START,
93   CPUINFO_INT_SH2_FASTRAM_END,
94   CPUINFO_INT_SH2_FASTRAM_READONLY,
95
96   CPUINFO_PTR_SH2_FASTRAM_BASE = CPUINFO_PTR_CPU_SPECIFIC
97};
98
99#define SH2_MAX_FASTRAM       4
100
87101void sh2drc_set_options(device_t *device, UINT32 options);
88102void sh2drc_add_pcflush(device_t *device, offs_t address);
103void sh2drc_add_fastram(device_t *device, offs_t start, offs_t end, UINT8 readonly, void *base);
89104
90105#endif /* __SH2_H__ */
trunk/src/emu/cpu/sh2/sh2drc.c
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77    Released for general non-commercial use under the MAME license
88    Visit http://mamedev.org for licensing and usage restrictions.
99
10    ST-V status:
11    colmns97 & stress crash due to SCSP stream->machine() getting corrupted.
12
13    cottonbm w/US bios: run to 60323B4 on master, then MOV insn @ 602f5aa crashes?
14    actually crash on slave @ 6032b38 after above.  reading wrong addr for jump vector.
15
1610***************************************************************************/
1711
1812#include "emu.h"
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128122
129123static void cfunc_printf_probe(void *param);
130124static void cfunc_unimplemented(void *param);
131static void cfunc_checkirqs(void *param);
132125static void cfunc_fastirq(void *param);
133126static void cfunc_MAC_W(void *param);
134127static void cfunc_MAC_L(void *param);
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284277}
285278
286279/*-------------------------------------------------
287    cfunc_checkirqs - checks for pending IRQs
288-------------------------------------------------*/
289static void cfunc_checkirqs(void *param)
290{
291   sh2_state *sh2 = (sh2_state *)param;
292   // if NMI is pending, evec etc are already set up
293   if (sh2->pending_nmi)
294   {
295      sh2->pending_nmi = 0;
296   }
297   else
298   {
299      sh2->evec = 0xffffffff;
300      CHECK_PENDING_IRQ("cfunc_checkirqs");
301   }
302}
303
304/*-------------------------------------------------
305280    cfunc_fastirq - checks for pending IRQs
306281-------------------------------------------------*/
307282static void cfunc_fastirq(void *param)
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11961171
11971172   UML_LABEL(block, label++);              // label:
11981173
1174#if 0   // DO NOT ENABLE - SEVERE AARON DAMAGE
1175   for (int ramnum = 0; ramnum < SH2_MAX_FASTRAM; ramnum++)
1176   {
1177      if (sh2->fastram[ramnum].base != NULL && (!iswrite || !sh2->fastram[ramnum].readonly))
1178      {
1179         void *fastbase = (UINT8 *)sh2->fastram[ramnum].base - sh2->fastram[ramnum].start;
1180         UINT32 skip = label++;
1181         if (sh2->fastram[ramnum].end != 0xffffffff)
1182         {
1183            UML_CMP(block, I0, sh2->fastram[ramnum].end);   // cmp     i0,end
1184            UML_JMPc(block, COND_A, skip);                                      // ja      skip
1185         }
1186         if (sh2->fastram[ramnum].start != 0x00000000)
1187         {
1188            UML_CMP(block, I0, sh2->fastram[ramnum].start);// cmp     i0,fastram_start
1189            UML_JMPc(block, COND_B, skip);                                      // jb      skip
1190         }
1191     
1192         if (!iswrite)
1193         {
1194            if (size == 1)
1195            {
1196               UML_XOR(block, I0, I0, BYTE4_XOR_LE(0));
1197               UML_LOAD(block, I0, fastbase, I0, SIZE_BYTE, SCALE_x1);             // load    i0,fastbase,i0,byte
1198            }
1199            else if (size == 2)
1200            {
1201               UML_XOR(block, I0, I0, WORD_XOR_LE(0));
1202               UML_LOAD(block, I0, fastbase, I0, SIZE_WORD, SCALE_x1);         // load    i0,fastbase,i0,word_x1
1203            }
1204            else if (size == 4)
1205            {
1206               UML_LOAD(block, I0, fastbase, I0, SIZE_DWORD, SCALE_x1);            // load    i0,fastbase,i0,dword_x1
1207            }
1208            UML_RET(block);                                                     // ret
1209         }
1210         else
1211         {
1212            if (size == 1)
1213            {
1214               UML_XOR(block, I0, I0, BYTE4_XOR_LE(0));
1215               UML_STORE(block, fastbase, I0, I1, SIZE_BYTE, SCALE_x1);// store   fastbase,i0,i1,byte
1216            }
1217            else if (size == 2)
1218            {
1219               UML_XOR(block, I0, I0, WORD_XOR_LE(0));
1220               UML_STORE(block, fastbase, I0, I1, SIZE_WORD, SCALE_x1);// store   fastbase,i0,i1,word_x1
1221            }
1222            else if (size == 4)
1223            {
1224               UML_STORE(block, fastbase, I0, I1, SIZE_DWORD, SCALE_x1);       // store   fastbase,i0,i1,dword_x1
1225            }
1226            UML_RET(block);                                                     // ret
1227         }
1228     
1229         UML_LABEL(block, skip);                                             // skip:
1230      }
1231   }
1232#endif
1233
11991234   if (iswrite)
12001235   {
12011236      switch (size)
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14051440
14061441/*-------------------------------------------------
14071442    log_add_disasm_comment - add a comment
1408    including disassembly of a MIPS instruction
1443    including disassembly of an SH2 instruction
14091444-------------------------------------------------*/
14101445
14111446static void log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op)
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19812016      return TRUE;
19822017
19832018   case 0x1b: // SLEEP();
1984      // inlined special version of generate_update_cycles here
1985      // if an interrupt is taken, the return address is set to the next instruction
1986      UML_CALLC(block, cfunc_checkirqs, sh2);
2019      {
2020         int skip = compiler->labelnum+1;
2021         compiler->labelnum += 3;
19872022
1988      UML_MOV(block, I0, mem(&sh2->evec));            // mov r0, evec
1989      UML_CMP(block, I0, 0xffffffff);         // cmp r0, 0xffffffff
1990      UML_JMPc(block, COND_Z, compiler->labelnum);            // jz skip
2023         UML_MOV(block, I0, mem(&sh2->sleep_mode));                     // mov i0, sleep_mode
2024         UML_CMP(block, I0, 0x2);                                 // cmp i0, #2
2025         UML_JMPc(block, COND_E, skip+1);                                // beq skip + 1
2026         // sleep mode != 2
2027         UML_CMP(block, I0, 0x0);                                 // cmp i0, #0
2028         UML_JMPc(block, COND_NE, skip);                              // bne skip
2029         UML_MOV(block, mem(&sh2->sleep_mode), 0x1);                     // mov sleep_mode, #1
2030                                                         
2031         UML_LABEL(block, skip);                                    // skip:
2032         generate_update_cycles(sh2, block, compiler, desc->pc, TRUE);      // repeat this insn
2033         UML_JMP(block, skip+2);                                      // jmp skip+2
19912034
1992      UML_SUB(block, R32(15), R32(15), 4);            // sub R15, R15, #4
1993      UML_MOV(block, I0, R32(15));                // mov r0, R15
1994      UML_MOV(block, I1, mem(&sh2->irqsr));           // mov r1, irqsr
1995      UML_CALLH(block, *sh2->write32);                    // call write32
2035         UML_LABEL(block, skip+1);                                   // skip + 1:
2036         // sleep_mode == 2
2037         UML_MOV(block, mem(&sh2->sleep_mode), 0x0);                     // sleep_mode = 0
2038         generate_update_cycles(sh2, block, compiler, desc->pc+2, TRUE);      // go to next insn
19962039
1997      UML_SUB(block, R32(15), R32(15), 4);            // sub R15, R15, #4
1998      UML_MOV(block, I0, R32(15));                // mov r0, R15
1999      UML_MOV(block, I1, desc->pc+2);             // mov r1, nextpc
2000      UML_CALLH(block, *sh2->write32);                    // call write32
2001
2002      UML_HASHJMP(block, 0, mem(&sh2->evec), *sh2->nocode);       // hashjmp sh2->evec
2003
2004      UML_LABEL(block, compiler->labelnum++);                 // skip:
2005
2006      // now go "out of cycles"
2007      if (compiler->cycles > 0)
2008      {
2009         UML_MOV(block, mem(&sh2->icount), 0);           // mov icount, #0
2010         UML_MAPVAR(block, MAPVAR_CYCLES, 0);                // mapvar  cycles,0
2011         UML_EXH(block, *sh2->out_of_cycles, desc->pc);      // go out of cycles
2040         UML_LABEL(block, skip+2);                                       // skip + 2:
20122041      }
2013      else
2014      {
2015         UML_HASHJMP(block, 0, desc->pc, *sh2->nocode);
2016      }
2017
20182042      return TRUE;
20192043
20202044   case 0x22: // STCVBR(Rn);
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31873211
31883212
31893213/*-------------------------------------------------
3214    sh2drc_add_fastram - add a new fastram
3215    region
3216-------------------------------------------------*/
3217
3218void sh2drc_add_fastram(device_t *device, offs_t start, offs_t end, UINT8 readonly, void *base)
3219{
3220   sh2_state *sh2 = get_safe_token(device);
3221   if (sh2->fastram_select < ARRAY_LENGTH(sh2->fastram))
3222   {
3223      sh2->fastram[sh2->fastram_select].start = start;
3224      sh2->fastram[sh2->fastram_select].end = end;
3225      sh2->fastram[sh2->fastram_select].readonly = readonly;
3226      sh2->fastram[sh2->fastram_select].base = base;
3227      sh2->fastram_select++;
3228   }
3229}
3230
3231/*-------------------------------------------------
31903232    sh2_internal_a5 - read handler for
31913233    SH2 internal map
31923234-------------------------------------------------*/
trunk/src/emu/cpu/sh2/sh2comn.c
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982982
983983   /* fetch PC */
984984   sh2->pc = RL( sh2, sh2->vbr + vector * 4 );
985   #endif
986
985987   if(sh2->sleep_mode == 1) { sh2->sleep_mode = 2; }
986   #endif
987988}
988989
989990void sh2_common_init(sh2_state *sh2, legacy_cpu_device *device, device_irq_acknowledge_callback irqcallback)

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