trunk/src/emu/cpu/h83002/h8_16.c
| r21296 | r21297 | |
|---|
| 312 | 312 | // push PC on stack |
| 313 | 313 | // extended mode stack push! |
| 314 | 314 | h8_setreg32(h8, H8_SP, h8_getreg32(h8, H8_SP)-4); |
| 315 | | h8_mem_write32(h8, h8_getreg32(h8, H8_SP), h8->pc); |
| 316 | | // push ccr |
| 317 | | h8_setreg32(h8, H8_SP, h8_getreg32(h8, H8_SP)-2); |
| 318 | | h8_mem_write16(h8, h8_getreg32(h8, H8_SP), h8_get_ccr(h8)); |
| 315 | h8_mem_write32(h8, h8_getreg32(h8, H8_SP), h8->pc | (h8_get_ccr(h8)<<24)); |
| 319 | 316 | |
| 320 | 317 | // generate address from vector |
| 321 | 318 | h8_set_ccr(h8, h8_get_ccr(h8) | 0x80); |
trunk/src/emu/cpu/h83002/h8ops.h
| r21296 | r21297 | |
|---|
| 1652 | 1652 | // rte |
| 1653 | 1653 | if(opcode == 0x5670) |
| 1654 | 1654 | { |
| 1655 | | // restore CCR |
| 1656 | | udata8 = (UINT8)h8_mem_read16(h8, h8_getreg32(h8, H8_SP)); |
| 1657 | | h8_setreg32(h8, H8_SP, h8_getreg32(h8, H8_SP)+2); |
| 1658 | | |
| 1659 | 1655 | // check if PC is 16 or 24/32 bits wide |
| 1660 | 1656 | if (h8->mode_8bit) |
| 1661 | 1657 | { |
| 1658 | // restore CCR |
| 1659 | udata8 = (UINT8)h8_mem_read16(h8, h8_getreg32(h8, H8_SP)); |
| 1660 | h8_setreg32(h8, H8_SP, h8_getreg32(h8, H8_SP)+2); |
| 1661 | |
| 1662 | 1662 | udata16 = h8_mem_read16(h8, h8_getreg16(h8, H8_SP)); |
| 1663 | 1663 | h8_setreg16(h8, H8_SP, h8_getreg16(h8, H8_SP)+2); |
| 1664 | 1664 | |
| r21296 | r21297 | |
|---|
| 1672 | 1672 | |
| 1673 | 1673 | // extended mode |
| 1674 | 1674 | h8->pc = udata32 & H8_ADDR_MASK; |
| 1675 | |
| 1676 | udata8 = (udata32>>24) & 0xff; |
| 1675 | 1677 | } |
| 1676 | 1678 | // must do this last, because set_ccr() does a check_irq() |
| 1677 | 1679 | h8_set_ccr(h8, udata8); |
trunk/src/mame/drivers/coinmvga.c
| r21296 | r21297 | |
|---|
| 875 | 875 | |
| 876 | 876 | DRIVER_INIT_MEMBER(coinmvga_state,colorama) |
| 877 | 877 | { |
| 878 | | UINT16 *ROM; |
| 879 | | ROM = (UINT16 *)memregion("maincpu")->base(); |
| 880 | | |
| 881 | | // rte in non-irq routines? wtf? patch them to rts... |
| 882 | | ROM[0x02B476/2] = 0x5470; |
| 883 | | ROM[0x02AE3A/2] = 0x5470; |
| 884 | | ROM[0x02A9FC/2] = 0x5470; |
| 885 | | ROM[0x02AA3A/2] = 0x5470; |
| 886 | | |
| 887 | | ROM[0x02729e/2] = 0x5470; |
| 888 | | ROM[0x029fb4/2] = 0x5470; |
| 889 | | ROM[0x02a224/2] = 0x5470; |
| 890 | | ROM[0x02a94e/2] = 0x5470; |
| 891 | 878 | } |
| 892 | 879 | |
| 893 | 880 | DRIVER_INIT_MEMBER(coinmvga_state,cmrltv75) |
| 894 | 881 | { |
| 895 | | UINT16 *ROM; |
| 896 | | ROM = (UINT16 *)memregion("maincpu")->base(); |
| 897 | | |
| 898 | | // rte in non-irq routines? wtf? patch them to rts... |
| 899 | | ROM[0x056fd6/2] = 0x5470; |
| 900 | | ROM[0x05655c/2] = 0x5470; |
| 901 | | ROM[0x05659a/2] = 0x5470; |
| 902 | | ROM[0x05699a/2] = 0x5470; |
| 903 | | |
| 904 | | //... |
| 905 | 882 | } |
| 906 | 883 | |
| 907 | 884 | |