trunk/src/emu/cpu/sh2/sh2comn.c
| r21226 | r21227 | |
|---|
| 571 | 571 | |
| 572 | 572 | // Watchdog |
| 573 | 573 | case 0x20: // WTCNT, RSTCSR |
| 574 | if((sh2->m[0x20] & 0xff000000) == 0x5a000000) |
| 575 | sh2->wtcnt = (sh2->m[0x20] >> 16) & 0xff; |
| 576 | |
| 577 | if((sh2->m[0x20] & 0xff000000) == 0xa5000000) |
| 578 | { |
| 579 | /* |
| 580 | WTCSR |
| 581 | x--- ---- Overflow in IT mode |
| 582 | -x-- ---- Timer mode (0: IT 1: watchdog) |
| 583 | --x- ---- Timer enable |
| 584 | ---1 1--- |
| 585 | ---- -xxx Clock select |
| 586 | */ |
| 587 | |
| 588 | sh2->wtcsr = (sh2->m[0x20] >> 16) & 0xff; |
| 589 | } |
| 590 | |
| 591 | if((sh2->m[0x20] & 0x0000ff00) == 0x00005a00) |
| 592 | { |
| 593 | // -x-- ---- RSTE (1: resets wtcnt when overflows 0: no reset) |
| 594 | // --x- ---- RSTS (0: power-on reset 1: Manual reset) |
| 595 | // ... |
| 596 | } |
| 597 | |
| 598 | if((sh2->m[0x20] & 0x0000ff00) == 0x0000a500) |
| 599 | { |
| 600 | // clear WOVF |
| 601 | // ... |
| 602 | } |
| 603 | |
| 604 | |
| 605 | |
| 574 | 606 | break; |
| 575 | 607 | |
| 576 | 608 | // Standby and cache |
| r21226 | r21227 | |
|---|
| 729 | 761 | case 0x06: // ICR |
| 730 | 762 | return sh2->icr << 16; |
| 731 | 763 | |
| 764 | case 0x20: |
| 765 | return (((sh2->wtcsr | 0x18) & 0xff) << 24) | ((sh2->wtcnt & 0xff) << 16); |
| 766 | |
| 732 | 767 | case 0x24: // SBYCR, CCR |
| 733 | 768 | return sh2->m[0x24] & ~0x3000; /* bit 4-5 of CCR are always zero */ |
| 734 | 769 | |
| r21226 | r21227 | |
|---|
| 1029 | 1064 | device->save_item(NAME(sh2->internal_irq_vector)); |
| 1030 | 1065 | device->save_item(NAME(sh2->dma_timer_active)); |
| 1031 | 1066 | device->save_item(NAME(sh2->dma_irq)); |
| 1067 | device->save_item(NAME(sh2->wtcnt)); |
| 1068 | device->save_item(NAME(sh2->wtcsr)); |
| 1032 | 1069 | } |