trunk/src/mess/drivers/dectalk.c
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| 10 | 10 | * which has been invaluable for work on this driver. |
| 11 | 11 | * Special thanks to leeeeee for helping figure out what the led selftest codes actually mean |
| 12 | 12 | * |
| 13 | * This driver dedicated in memory of Dennis Klatt and Jonathan Allen, without whose |
| 14 | * original work MITalk and hence KlattTalk and DECTALK would hever have existed. |
| 15 | * |
| 13 | 16 | * TODO: |
| 14 | 17 | * * DUART: |
| 15 | 18 | * * <DONE> DUART needs to be reset on reset line activation. as is it works ok, but it should be done anyway. |
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| 48 | 51 | * FE 03 - RAM check fail @ 0x88000-0x8bfff, ram at E34 or E47 " |
| 49 | 52 | * FE 04 - RAM check fail @ 0x8c000-0x8ffff, ram at E33 or E46 " |
| 50 | 53 | * FE 05 - RAM check fail @ 0x90000-0x93fff, ram at E32 or E44 " |
| 54 | * FE 0F - RAM check fail at multiple addresses |
| 51 | 55 | * FD 00 - DUART test & DUART interrupt test (test code at $046C) |
| 52 | 56 | * FC 00 - This test doesn't exist. Some vestiges of it may remain in code for the FD and FB tests. |
| 53 | | * FB 00 - TMS32010 extensive tests (test code at $051E): test spc interrupt [works] and make dtmf tone to test tlc interrupt [fails in mess, requires dtmf detection on output] |
| 57 | * FB 00 - TMS32010 extensive tests (test code at $051E): test spc interrupt [works] and make dtmf tone to test tlc interrupt [fails in mess, requires dtmf detection on output; this test is actually patented! US 4,552,992] |
| 54 | 58 | * Jump to $102C to skip the self tests |
| 55 | 59 | * During normal operation: |
| 56 | 60 | (table taken from http://www3.sympatico.ca/n.rieck/docs/DECtalk_notes.html ) |
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| 123 | 127 | SPC is INT level 5 |
| 124 | 128 | DUART is INT level 6 |
| 125 | 129 | */ |
| 130 | /* dtc-03 post by dave conroy from usenet comp.sys.dec on 12/2011: |
| 131 | > Wow. were they better than the DTC01? (OK, I guess they had to be.) |
| 132 | |
| 133 | I worked on both of these at DEC (in fact, I think if you look in the |
| 134 | options and modules |
| 135 | list, you will see my initials in the "responsible engineer" column |
| 136 | for the DTC03). |
| 137 | |
| 138 | The goals of the DTC03 were lower cost, better letter to sound rules, |
| 139 | and better packaging for large systems (it was pretty inconvenient to |
| 140 | set up 30-40 of |
| 141 | the big DTC01 boxes). |
| 142 | |
| 143 | The hardware was quite different. The DTC01 used a Motorola 68000 and |
| 144 | a TI DSP, connected |
| 145 | together by a big bank of (expensive) fifo chips. The DTC03 used then |
| 146 | (then new) Intel 80186 and the same |
| 147 | TI DSP, connected together by DMA (the DTC03 design was done in a way |
| 148 | that used *all* of the |
| 149 | capabilities of the 80186 to reduce the cost). The DTC01 used the |
| 150 | packaging of the VT240, and the DTC03 |
| 151 | used the packaging of a family of rack-mounted modems whose part |
| 152 | number escapes me. The |
| 153 | same guy (Rich Ellison) designed both of them. The DTC03 also had an |
| 154 | "option module" system which |
| 155 | was intended to allow non-US systems to be built without needing to |
| 156 | change the common |
| 157 | parts (because it was on an independent module, and could override all |
| 158 | of the telephone control ESC |
| 159 | sequences, it could be taken through the approval process in |
| 160 | isolation), although it was used |
| 161 | to build some semi-custom systems as well. |
| 162 | |
| 163 | The code in the DSP and the code that transformed a stream of phonemes |
| 164 | into a stream |
| 165 | of control commands for the DSP was pretty much the same in DTC01/ |
| 166 | DTC03, and was based on the work of |
| 167 | Dennis Klatt of MIT (Dennis actually wrote a lot of this code). The |
| 168 | letter to sound system |
| 169 | in DTC01 was the final step in the evolution of a set of letter-to- |
| 170 | sound rules that had been floating around DEC |
| 171 | for a long time; the bulk of the work getting them to work in the |
| 172 | DTC01 was done by |
| 173 | Martin Minow. The letter to sound system in DTC03 was a new design by |
| 174 | myself and Tony Vitale, |
| 175 | an ex-professor of linguistics from Cornell. Most people thought it |
| 176 | worked much |
| 177 | better; in reality, it's big advantage was it made far fewer stupid |
| 178 | stress-placement mistakes because |
| 179 | it did a much better job of understanding prefixes and suffixes. |
| 180 | |
| 181 | Dave Conroy |
| 182 | */ |
| 183 | /* |
| 184 | There are 3 things on the pins. Serial I/O. The telephone line. Power. |
| 185 | |
| 186 | I believe the power is +5 and +12/-12. The +5 is for the logic, |
| 187 | and the +12/-12 is for the RS232 buffers and all of the analog stuff |
| 188 | in the anti-aliasing |
| 189 | filter, which is built from a pile of op-amps and stuff. |
| 190 | |
| 191 | The serial I/O pins go straight to the RS232 buffers and |
| 192 | onward to the UART (an SCN2661, if my memory is correct). |
| 193 | |
| 194 | The telephone pins go to the option connectors and the on-board |
| 195 | telephone line interface for the USA/Canada. Audio is available |
| 196 | somewhere on the |
| 197 | option connectors, but a really easy way to get at it is to take the |
| 198 | phone off-hook (send a "dial" command with an empty phone number |
| 199 | string) |
| 200 | and use the telephone pins as a transformer-coupled audio output. This |
| 201 | is what we |
| 202 | used to do in the lab all the time. |
| 203 | |
| 204 | dgc (dg(no!spam)cx@mac.com) |
| 205 | */ |
| 206 | |
| 126 | 207 | // USE_LOOSE_TIMING makes the cpu interleave much lower and boosts it on fifo and flag writes by the 68k and semaphore sets by the dsp |
| 127 | 208 | #define USE_LOOSE_TIMING 1 |
| 128 | 209 | // generic logs like led state, and common writes for dsp and spc such as the speech int |
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| 157 | 238 | |
| 158 | 239 | UINT8 m_data[8]; // hack to prevent gcc bitching about struct pointers. not used. |
| 159 | 240 | UINT8 m_x2214_sram[256]; // NVRAM chip's temp sram space |
| 160 | | UINT8 m_statusLED; |
| 161 | 241 | // input fifo, between m68k and tms32010 |
| 162 | 242 | UINT16 m_infifo[32]; // technically eight 74LS224 4bit*16stage FIFO chips, arranged as a 32 stage, 16-bit wide fifo |
| 163 | 243 | UINT8 m_infifo_tail_ptr; |
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| 330 | 410 | dectalk_state *state = device->machine().driver_data<dectalk_state>(); |
| 331 | 411 | state->m_hack_self_test = 0; // hack |
| 332 | 412 | // stuff that is DIRECTLY affected by the RESET line |
| 333 | | state->m_statusLED = 0; // clear status led latch |
| 334 | 413 | state->dectalk_x2212_recall(); // nvram recall |
| 335 | 414 | state->m_m68k_spcflags_latch = 1; // initial status is speech reset(d0) active and spc int(d6) disabled |
| 336 | 415 | state->m_m68k_tlcflags_latch = 0; // initial status is tone detect int(d6) off, answer phone(d8) off, ring detect int(d14) off |
| 337 | 416 | device->machine().device("duart68681")->reset(); // reset the DUART |
| 338 | 417 | // stuff that is INDIRECTLY affected by the RESET line |
| 339 | 418 | state->dectalk_clear_all_fifos(); // speech reset clears the fifos, though we have to do it explicitly here since we're not actually in the m68k_spcflags_w function. |
| 340 | | state->dectalk_semaphore_w(0); // on the original state->m_dectalk pcb revision, this is a semaphore for the INPUT fifo, later dec hacked on a check for the 3 output fifo chips to see if they're in sync, and set both of these latches if true. |
| 419 | state->dectalk_semaphore_w(0); // on the original dectalk pcb revision, this is a semaphore for the INPUT fifo, later dec hacked on a check for the 3 output fifo chips to see if they're in sync, and set both of these latches if true. |
| 341 | 420 | state->m_spc_error_latch = 0; // spc error latch is cleared on /reset |
| 342 | 421 | device->machine().device("dsp")->execute().set_input_line(INPUT_LINE_RESET, ASSERT_LINE); // speech reset forces the CLR line active on the tms32010 |
| 343 | 422 | state->m_tlc_tonedetect = 0; // TODO, needed for selftest pass |
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| 368 | 447 | |
| 369 | 448 | WRITE8_MEMBER(dectalk_state::led_write) |
| 370 | 449 | { |
| 371 | | m_statusLED = data&0xFF; |
| 372 | 450 | popmessage("LED status: %02X\n", data&0xFF); |
| 373 | 451 | #ifdef VERBOSE |
| 374 | 452 | logerror("m68k: LED status: %02X\n", data&0xFF); |
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| 709 | 787 | #endif |
| 710 | 788 | machine().scheduler().timer_set(attotime::from_hz(10000), timer_expired_delegate(FUNC(dectalk_state::outfifo_read_cb),this)); |
| 711 | 789 | speaker->write_signed16(data); |
| 790 | // hack for break key, requires hacked up duart core so disabled for now |
| 791 | // also it doesn't work well, the setup menu is badly corrupt |
| 792 | /*device_t *duart = machine().device("duart68681"); |
| 793 | if (machine.input().code_pressed(KEYCODE_F1)) |
| 794 | duart68681_rx_break(duart, 1, 1); |
| 795 | else |
| 796 | duart68681_rx_break(duart, 1, 0);*/ |
| 712 | 797 | } |
| 713 | 798 | |
| 714 | 799 | /* Driver init: stuff that needs setting up which isn't directly affected by reset */ |
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| 770 | 855 | ROM_START( dectalk ) |
| 771 | 856 | ROM_REGION16_BE(0x40000,"maincpu", 0) |
| 772 | 857 | // dectalk dtc-01 firmware v2.0 (first half: 23Jul84 tag; second half: 02Jul84 tag), all roms are 27128 eproms |
| 773 | | // technically the correct rom names are probably 23-123e5.e8, etc, but the chips they were dumped from were NOT labeled that way |
| 774 | | ROM_LOAD16_BYTE("sp8510123e5.e8", 0x00000, 0x4000, CRC(03e1eefa) SHA1(e586de03e113683c2534fca1f3f40ba391193044)) // Label: "SP8510123E5" @ E8 |
| 775 | | ROM_LOAD16_BYTE("sp8510119e5.e22", 0x00001, 0x4000, CRC(af20411f) SHA1(7954bb56b7591f8954403a22d34de31c7d5441ac)) // Label: "SP8510119E5" @ E22 |
| 776 | | ROM_LOAD16_BYTE("sp8510124e5.e7", 0x08000, 0x4000, CRC(9edeafcb) SHA1(7724babf4ae5d77c0b4200f608d599058d04b25c)) // Label: "SP8510124E5" @ E7 |
| 777 | | ROM_LOAD16_BYTE("sp8510120e5.e21", 0x08001, 0x4000, CRC(f2a346a6) SHA1(af5e4ea0b3631f7d6f16c22e86a33fa2cb520ee0)) // Label: "SP8510120E5" @ E21 |
| 778 | | ROM_LOAD16_BYTE("sp8510125e5.e6", 0x10000, 0x4000, CRC(1c0100d1) SHA1(1b60cd71dfa83408b17e13f683b6bf3198c905cc)) // Label: "SP8510125E5" @ E6 |
| 779 | | ROM_LOAD16_BYTE("sp8510121e5.e20", 0x10001, 0x4000, CRC(4cb081bd) SHA1(4ad0b00628a90085cd7c78a354256c39fd14db6c)) // Label: "SP8510121E5" @ E20 |
| 780 | | ROM_LOAD16_BYTE("sp8510126e5.e5", 0x18000, 0x4000, CRC(7823dedb) SHA1(e2b2415eec838ddd46094f2fea93fd289dd0caa2)) // Label: "SP8510126E5" @ E5 |
| 781 | | ROM_LOAD16_BYTE("sp8510122e5.e19", 0x18001, 0x4000, CRC(b86370e6) SHA1(92ab22a24484ad0d0f5c8a07347105509999f3ee)) // Label: "SP8510122E5" @ E19 |
| 782 | | ROM_LOAD16_BYTE("sp8510103e5.e4", 0x20000, 0x4000, CRC(35aac6b9) SHA1(b5aec0bf37a176ff4d66d6a10357715957662ebd)) // Label: "SP8510103E5" @ E4 |
| 783 | | ROM_LOAD16_BYTE("sp8510095e5.e18", 0x20001, 0x4000, CRC(2296fe39) SHA1(891f3a3b4ce75ef14001257bc8f1f60463a9a7cb)) // Label: "SP8510095E5" @ E18 |
| 784 | | ROM_LOAD16_BYTE("sp8510104e5.e3", 0x28000, 0x4000, CRC(9658b43c) SHA1(4d6808f67cbdd316df23adc8ddf701df57aa854a)) // Label: "SP8510104E5" @ E3 |
| 785 | | ROM_LOAD16_BYTE("sp8510096e5.e17", 0x28001, 0x4000, CRC(cf236077) SHA1(496c69e52cfa013173f7b9c500ce544a03ad01f7)) // Label: "SP8510096E5" @ E17 |
| 786 | | ROM_LOAD16_BYTE("sp8510105e5.e2", 0x30000, 0x4000, CRC(09cddd28) SHA1(de0c25687bab3ff0c88c98622092e0b58331aa16)) // Label: "SP8510105E5" @ E2 |
| 787 | | ROM_LOAD16_BYTE("sp8510097e5.e16", 0x30001, 0x4000, CRC(49434da1) SHA1(c450abae0ccf372d7eb87370b8a8c97a45e164d3)) // Label: "SP8510097E5" @ E16 |
| 788 | | ROM_LOAD16_BYTE("sp8510106e5.e1", 0x38000, 0x4000, CRC(a389ab31) SHA1(355348bfc96a04193136cdde3418366e6476c3ca)) // Label: "SP8510106E5" @ E1 |
| 789 | | ROM_LOAD16_BYTE("sp8510098e5.e15", 0x38001, 0x4000, CRC(3d8910e7) SHA1(01921e77b46c2d4845023605239c45ffa4a35872)) // Label: "SP8510098E5" @ E15 |
| 858 | // technically the correct rom names are 23-123e5.e8, etc, but the chips they were dumped from were NOT labeled that way |
| 859 | // labels were SP8510123E5 etc, which means the chips were burned at dec in week 10, 1985 |
| 860 | /* the labels dec uses for most non-factory-programmed eproms, proms and pals is something like SPddddnnnto or WBddddnnto |
| 861 | * where: |
| 862 | * SP or WB = ? |
| 863 | * dddd is a 4 digit datecode with yyww (i.e. 8510 = week 10, 1985) |
| 864 | * nnn = the dec internal rom number for that type |
| 865 | * t = programmable chip type (e = eprom, otprom or mask rom; a,b,f = proms of various sorts; there are others for plas and pals) |
| 866 | * o = size of rom |
| 867 | * for eproms/otproms or mask roms it is: e1 = 0x400, e2 = 0x800, e3 = 0x1000, e4 = 0x2000, e5 = 0x4000, e6 = 0x8000, etc) |
| 868 | * for proms it is: a1 = 82s123(0x20, 8b TS); a2 = 82s129(0x100 4b TS); a9 = 82s131(0x200 4b TS); b1 = 82s135(0x100 8b TS); f1 = 82s137(0x400 4b TS); f4 = 82s191(0x800 8b TS); s0(mc68hc05); m2(i8051 or other MCS-51) (there are more) |
| 869 | */ |
| 870 | ROM_LOAD16_BYTE("23-123e5.e8", 0x00000, 0x4000, CRC(03e1eefa) SHA1(e586de03e113683c2534fca1f3f40ba391193044)) // Label: "SP8510123E5" @ E8 |
| 871 | ROM_LOAD16_BYTE("23-119e5.e22", 0x00001, 0x4000, CRC(af20411f) SHA1(7954bb56b7591f8954403a22d34de31c7d5441ac)) // Label: "SP8510119E5" @ E22 |
| 872 | ROM_LOAD16_BYTE("23-124e5.e7", 0x08000, 0x4000, CRC(9edeafcb) SHA1(7724babf4ae5d77c0b4200f608d599058d04b25c)) // Label: "SP8510124E5" @ E7 |
| 873 | ROM_LOAD16_BYTE("23-120e5.e21", 0x08001, 0x4000, CRC(f2a346a6) SHA1(af5e4ea0b3631f7d6f16c22e86a33fa2cb520ee0)) // Label: "SP8510120E5" @ E21 |
| 874 | ROM_LOAD16_BYTE("23-125e5.e6", 0x10000, 0x4000, CRC(1c0100d1) SHA1(1b60cd71dfa83408b17e13f683b6bf3198c905cc)) // Label: "SP8510125E5" @ E6 |
| 875 | ROM_LOAD16_BYTE("23-121e5.e20", 0x10001, 0x4000, CRC(4cb081bd) SHA1(4ad0b00628a90085cd7c78a354256c39fd14db6c)) // Label: "SP8510121E5" @ E20 |
| 876 | ROM_LOAD16_BYTE("23-126e5.e5", 0x18000, 0x4000, CRC(7823dedb) SHA1(e2b2415eec838ddd46094f2fea93fd289dd0caa2)) // Label: "SP8510126E5" @ E5 |
| 877 | ROM_LOAD16_BYTE("23-122e5.e19", 0x18001, 0x4000, CRC(b86370e6) SHA1(92ab22a24484ad0d0f5c8a07347105509999f3ee)) // Label: "SP8510122E5" @ E19 |
| 878 | ROM_LOAD16_BYTE("23-103e5.e4", 0x20000, 0x4000, CRC(35aac6b9) SHA1(b5aec0bf37a176ff4d66d6a10357715957662ebd)) // Label: "SP8510103E5" @ E4 |
| 879 | ROM_LOAD16_BYTE("23-095e5.e18", 0x20001, 0x4000, CRC(2296fe39) SHA1(891f3a3b4ce75ef14001257bc8f1f60463a9a7cb)) // Label: "SP8510095E5" @ E18 |
| 880 | ROM_LOAD16_BYTE("23-104e5.e3", 0x28000, 0x4000, CRC(9658b43c) SHA1(4d6808f67cbdd316df23adc8ddf701df57aa854a)) // Label: "SP8510104E5" @ E3 |
| 881 | ROM_LOAD16_BYTE("23-096e5.e17", 0x28001, 0x4000, CRC(cf236077) SHA1(496c69e52cfa013173f7b9c500ce544a03ad01f7)) // Label: "SP8510096E5" @ E17 |
| 882 | ROM_LOAD16_BYTE("23-105e5.e2", 0x30000, 0x4000, CRC(09cddd28) SHA1(de0c25687bab3ff0c88c98622092e0b58331aa16)) // Label: "SP8510105E5" @ E2 |
| 883 | ROM_LOAD16_BYTE("23-097e5.e16", 0x30001, 0x4000, CRC(49434da1) SHA1(c450abae0ccf372d7eb87370b8a8c97a45e164d3)) // Label: "SP8510097E5" @ E16 |
| 884 | ROM_LOAD16_BYTE("23-106e5.e1", 0x38000, 0x4000, CRC(a389ab31) SHA1(355348bfc96a04193136cdde3418366e6476c3ca)) // Label: "SP8510106E5" @ E1 |
| 885 | ROM_LOAD16_BYTE("23-098e5.e15", 0x38001, 0x4000, CRC(3d8910e7) SHA1(01921e77b46c2d4845023605239c45ffa4a35872)) // Label: "SP8510098E5" @ E15 |
| 790 | 886 | |
| 887 | /* the undumped 1.8 or 2.0 (beta?) version likely has roms: |
| 888 | 23-091e5.e22, 23-092e5.e21, 23-093e5.e20, 23-094e5.e19, |
| 889 | 23-099e5.e8, 23-100e5.e7, 23-101e5.e6, 23-102e5.e5 |
| 890 | and shares the 23-103e5 thru 106e5, and 095e5 thru 098e5 roms with |
| 891 | the 2.0 version above |
| 892 | */ |
| 893 | |
| 791 | 894 | ROM_REGION(0x2000,"dsp", 0) |
| 792 | | // dectalk dtc-01 'klsyn' tms32010 firmware v2.0, both proms are 82s191 equivalent |
| 793 | | ROM_LOAD16_BYTE("lm8506205f4.e70", 0x000, 0x800, CRC(ed76a3ad) SHA1(3136bae243ef48721e21c66fde70dab5fc3c21d0)) // Label: "LM8506205F4 // M1-76161-5" @ E70 |
| 794 | | ROM_LOAD16_BYTE("lm8504204f4.e69", 0x001, 0x800, CRC(79bb54ff) SHA1(9409f90f7a397b041e4440341f2d7934cb479285)) // Label: "LM8504204F4 // 78S191" @ E69 |
| 895 | // dectalk dtc-01 'klsyn' tms32010 firmware v2.0?, both proms are 82s191 equivalent |
| 896 | ROM_LOAD16_BYTE("23-205f4.e70", 0x000, 0x800, CRC(ed76a3ad) SHA1(3136bae243ef48721e21c66fde70dab5fc3c21d0)) // Label: "LM8506205F4 // M1-76161-5" @ E70 |
| 897 | ROM_LOAD16_BYTE("23-204f4.e69", 0x001, 0x800, CRC(79bb54ff) SHA1(9409f90f7a397b041e4440341f2d7934cb479285)) // Label: "LM8504204F4 // 78S191" @ E69 |
| 795 | 898 | |
| 796 | 899 | ROM_REGION(0x100,"nvram", 0) // default nvram image is at 0x1A7AE in main rom, read lsn first so 0x0005 in rom becomes 05 00 00 00 etc for all words of main rom |
| 797 | 900 | ROM_FILL(0x00, 0xff, 0x00) // blank it first; |