Previous

199869 Revisions

Next

r21161 Monday 18th February, 2013 at 14:57:32 UTC by Miodrag Milanović
Some mess modernization (nw)

[src/mess/drivers]

4004clk.c a2600.c apc.c apexc.c atari400.c craft.c dectalk.c gizmondo.c hp49gp.c ip20.c ip22.c jr100.c juicebox.c mini2440.c mmodular.c multi8.c mz2500.c n64.c nanos.c ng_aes.c palmz22.c pasogo.c pasopia7.c pc6001.c pc8801.c pc88va.c pc9801.c pdp11.c pegasus.c pockstat.c ptcsol.c scv.c sgi_ip2.c sgi_ip6.c smc777.c socrates.c ssem.c supercon.c supracan.c ti990_10.c ti990_4.c vii.c vk100.c vt100.c vtech1.c

trunk/src/mess/drivers/mz2500.c

r21160	r21161
196	196	DECLARE_WRITE_LINE_MEMBER(pit8253_clk0_irq);
197	197	DECLARE_WRITE_LINE_MEMBER(mz2500_rtc_alarm_irq);
198	198
199		void draw_80x25(running_machine &machine, bitmap_ind16 &bitmap,const rectangle &cliprect,UINT16 map_addr);
200		void draw_40x25(running_machine &machine, bitmap_ind16 &bitmap,const rectangle &cliprect,int plane,UINT16 map_addr);
201		void draw_cg4_screen(running_machine &machine, bitmap_ind16 &bitmap,const rectangle &cliprect,int pri);
202		void draw_cg16_screen(running_machine &machine, bitmap_ind16 &bitmap,const rectangle &cliprect,int plane,int x_size,int pri);
203		void draw_cg256_screen(running_machine &machine, bitmap_ind16 &bitmap,const rectangle &cliprect,int plane,int pri);
204		void draw_tv_screen(running_machine &machine, bitmap_ind16 &bitmap,const rectangle &cliprect);
205		void draw_cg_screen(running_machine &machine, bitmap_ind16 &bitmap,const rectangle &cliprect,int pri);
	199	void draw_80x25(bitmap_ind16 &bitmap,const rectangle &cliprect,UINT16 map_addr);
	200	void draw_40x25(bitmap_ind16 &bitmap,const rectangle &cliprect,int plane,UINT16 map_addr);
	201	void draw_cg4_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int pri);
	202	void draw_cg16_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int plane,int x_size,int pri);
	203	void draw_cg256_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int plane,int pri);
	204	void draw_tv_screen(bitmap_ind16 &bitmap,const rectangle &cliprect);
	205	void draw_cg_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int pri);
206	206
	207	void mz2500_draw_pixel(bitmap_ind16 &bitmap,int x,int y,UINT16  pen,UINT8 width,UINT8 height);
	208	void mz2500_reconfigure_screen();
	209	UINT8 pal_256_param(int index, int param);
	210	void mz2500_reset(mz2500_state *state, UINT8 type);
207	211	};
208	212
209	213
r21160	r21161
212	216	#define WRAM_RESET 0
213	217	#define IPL_RESET 1
214	218
215		static void mz2500_reset(mz2500_state *state, UINT8 type);
216	219	static const UINT8 bank_reset_val[2][8] =
217	220	{
218	221	{ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 },
r21160	r21161
236	239	*/
237	240
238	241	/* helper function, to draw stuff without getting crazy with height / width conditions :) */
239		static void mz2500_draw_pixel(running_machine &machine, bitmap_ind16 &bitmap,int x,int y,UINT16  pen,UINT8 width,UINT8 height)
	242	void mz2500_state::mz2500_draw_pixel(bitmap_ind16 &bitmap,int x,int y,UINT16  pen,UINT8 width,UINT8 height)
240	243	{
241	244	if(width && height)
242	245	{
243		bitmap.pix16(y*2+0, x*2+0) = machine.pens[pen];
244		bitmap.pix16(y*2+0, x*2+1) = machine.pens[pen];
245		bitmap.pix16(y*2+1, x*2+0) = machine.pens[pen];
246		bitmap.pix16(y*2+1, x*2+1) = machine.pens[pen];
	246	bitmap.pix16(y*2+0, x*2+0) = machine().pens[pen];
	247	bitmap.pix16(y*2+0, x*2+1) = machine().pens[pen];
	248	bitmap.pix16(y*2+1, x*2+0) = machine().pens[pen];
	249	bitmap.pix16(y*2+1, x*2+1) = machine().pens[pen];
247	250	}
248	251	else if(width)
249	252	{
250		bitmap.pix16(y, x*2+0) = machine.pens[pen];
251		bitmap.pix16(y, x*2+1) = machine.pens[pen];
	253	bitmap.pix16(y, x*2+0) = machine().pens[pen];
	254	bitmap.pix16(y, x*2+1) = machine().pens[pen];
252	255	}
253	256	else if(height)
254	257	{
255		bitmap.pix16(y*2+0, x) = machine.pens[pen];
256		bitmap.pix16(y*2+1, x) = machine.pens[pen];
	258	bitmap.pix16(y*2+0, x) = machine().pens[pen];
	259	bitmap.pix16(y*2+1, x) = machine().pens[pen];
257	260	}
258	261	else
259		bitmap.pix16(y, x) = machine.pens[pen];
	262	bitmap.pix16(y, x) = machine().pens[pen];
260	263	}
261	264
262		void mz2500_state::draw_80x25(running_machine &machine, bitmap_ind16 &bitmap,const rectangle &cliprect,UINT16 map_addr)
	265	void mz2500_state::draw_80x25(bitmap_ind16 &bitmap,const rectangle &cliprect,UINT16 map_addr)
263	266	{
264	267	UINT8 *vram = m_main_ram; // TODO
265	268	int x,y,count,xi,yi;
r21160	r21161
337	340	if(pen)
338	341	{
339	342	if((res_y) >= 0 && (res_y) < 200*y_step)
340		mz2500_draw_pixel(machine,bitmap,res_x,res_y,pen+(m_pal_select ? 0x00 : 0x10),0,0);
	343	mz2500_draw_pixel(bitmap,res_x,res_y,pen+(m_pal_select ? 0x00 : 0x10),0,0);
341	344	}
342	345	}
343	346	}
r21160	r21161
348	351	}
349	352	}
350	353
351		void mz2500_state::draw_40x25(running_machine &machine, bitmap_ind16 &bitmap,const rectangle &cliprect,int plane,UINT16 map_addr)
	354	void mz2500_state::draw_40x25(bitmap_ind16 &bitmap,const rectangle &cliprect,int plane,UINT16 map_addr)
352	355	{
353	356	UINT8 *vram = m_main_ram; // TODO
354	357	int x,y,count,xi,yi;
r21160	r21161
427	430	if(pen)
428	431	{
429	432	if((res_y) >= 0 && (res_y) < 200*y_step)
430		mz2500_draw_pixel(machine,bitmap,res_x,res_y,pen+(m_pal_select ? 0x00 : 0x10),m_scr_x_size == 640,0);
	433	mz2500_draw_pixel(bitmap,res_x,res_y,pen+(m_pal_select ? 0x00 : 0x10),m_scr_x_size == 640,0);
431	434	}
432	435	}
433	436	}
r21160	r21161
438	441	}
439	442	}
440	443
441		void mz2500_state::draw_cg4_screen(running_machine &machine, bitmap_ind16 &bitmap,const rectangle &cliprect,int pri)
	444	void mz2500_state::draw_cg4_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int pri)
442	445	{
443	446	UINT32 count;
444	447	UINT8 *vram = m_main_ram; // TODO
r21160	r21161
471	474
472	475	{
473	476	//if(pri == ((m_clut256[pen] & 0x100) >> 8))
474		mz2500_draw_pixel(machine,bitmap,res_x,res_y,pen,0,0);
	477	mz2500_draw_pixel(bitmap,res_x,res_y,pen,0,0);
475	478	}
476	479	}
477	480	count++;
r21160	r21161
479	482	}
480	483	}
481	484
482		void mz2500_state::draw_cg16_screen(running_machine &machine, bitmap_ind16 &bitmap,const rectangle &cliprect,int plane,int x_size,int pri)
	485	void mz2500_state::draw_cg16_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int plane,int x_size,int pri)
483	486	{
484	487	UINT32 count;
485	488	UINT8 *vram = m_main_ram; //TODO
r21160	r21161
526	529	pen |= pen_bit[pen_i];
527	530
528	531	if(pri == ((m_clut16[pen] & 0x10) >> 4) && m_clut16[pen] != 0x00 && pen_mask) //correct?
529		mz2500_draw_pixel(machine,bitmap,res_x,res_y,(m_clut16[pen] & 0x0f)+0x10,(x_size == 320 && m_scr_x_size == 640),cg_interlace == 2);
	532	mz2500_draw_pixel(bitmap,res_x,res_y,(m_clut16[pen] & 0x0f)+0x10,(x_size == 320 && m_scr_x_size == 640),cg_interlace == 2);
530	533	}
531	534	count++;
532	535	count&=((base_mask<<8) | 0xff);
r21160	r21161
536	539	}
537	540	}
538	541
539		void mz2500_state::draw_cg256_screen(running_machine &machine, bitmap_ind16 &bitmap,const rectangle &cliprect,int plane,int pri)
	542	void mz2500_state::draw_cg256_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int plane,int pri)
540	543	{
541	544	UINT32 count;
542	545	UINT8 *vram = m_main_ram;
r21160	r21161
583	586	pen |= pen_bit[pen_i];
584	587
585	588	if(pri == ((m_clut256[pen] & 0x100) >> 8))
586		mz2500_draw_pixel(machine,bitmap,res_x,res_y,(m_clut256[pen] & 0xff)+0x100,m_scr_x_size == 640,cg_interlace == 2);
	589	mz2500_draw_pixel(bitmap,res_x,res_y,(m_clut256[pen] & 0xff)+0x100,m_scr_x_size == 640,cg_interlace == 2);
587	590	}
588	591	count++;
589	592	count&=((base_mask<<8) | 0xff);
r21160	r21161
593	596	}
594	597	}
595	598
596		void mz2500_state::draw_tv_screen(running_machine &machine, bitmap_ind16 &bitmap,const rectangle &cliprect)
	599	void mz2500_state::draw_tv_screen(bitmap_ind16 &bitmap,const rectangle &cliprect)
597	600	{
598	601	UINT16 base_addr;
599	602
r21160	r21161
603	606	//  popmessage("%d %d %d %d",m_tv_hs,(m_tv_he),m_tv_vs,(m_tv_ve));
604	607
605	608	if(m_text_col_size)
606		draw_80x25(machine,bitmap,cliprect,base_addr);
	609	draw_80x25(bitmap,cliprect,base_addr);
607	610	else
608	611	{
609	612	int tv_mode;
r21160	r21161
613	616	switch(tv_mode & 3)
614	617	{
615	618	case 0: //mixed 6bpp mode, TODO
616		draw_40x25(machine,bitmap,cliprect,0,base_addr);
	619	draw_40x25(bitmap,cliprect,0,base_addr);
617	620	break;
618	621	case 1:
619		draw_40x25(machine,bitmap,cliprect,0,base_addr);
	622	draw_40x25(bitmap,cliprect,0,base_addr);
620	623	break;
621	624	case 2:
622		draw_40x25(machine,bitmap,cliprect,1,base_addr);
	625	draw_40x25(bitmap,cliprect,1,base_addr);
623	626	break;
624	627	case 3:
625		draw_40x25(machine,bitmap,cliprect,1,base_addr);
626		draw_40x25(machine,bitmap,cliprect,0,base_addr);
	628	draw_40x25(bitmap,cliprect,1,base_addr);
	629	draw_40x25(bitmap,cliprect,0,base_addr);
627	630	break;
628	631	//default: popmessage("%02x %02x %02x",tv_mode & 3,m_text_reg[1],m_text_reg[2]); break;
629	632	}
630	633	}
631	634	}
632	635
633		void mz2500_state::draw_cg_screen(running_machine &machine, bitmap_ind16 &bitmap,const rectangle &cliprect,int pri)
	636	void mz2500_state::draw_cg_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int pri)
634	637	{
635	638	//popmessage("%02x %02x",m_cg_reg[0x0e],m_cg_reg[0x18]);
636	639
r21160	r21161
639	642	case 0x00:
640	643	break;
641	644	case 0x03:
642		draw_cg4_screen(machine,bitmap,cliprect,0);
	645	draw_cg4_screen(bitmap,cliprect,0);
643	646	break;
644	647	case 0x14:
645		draw_cg16_screen(machine,bitmap,cliprect,0,320,pri);
646		draw_cg16_screen(machine,bitmap,cliprect,1,320,pri);
	648	draw_cg16_screen(bitmap,cliprect,0,320,pri);
	649	draw_cg16_screen(bitmap,cliprect,1,320,pri);
647	650	break;
648	651	case 0x15:
649		draw_cg16_screen(machine,bitmap,cliprect,1,320,pri);
650		draw_cg16_screen(machine,bitmap,cliprect,0,320,pri);
	652	draw_cg16_screen(bitmap,cliprect,1,320,pri);
	653	draw_cg16_screen(bitmap,cliprect,0,320,pri);
651	654	break;
652	655	case 0x17:
653		draw_cg16_screen(machine,bitmap,cliprect,0,640,pri);
	656	draw_cg16_screen(bitmap,cliprect,0,640,pri);
654	657	break;
655	658	case 0x1d:
656		draw_cg256_screen(machine,bitmap,cliprect,0,pri);
	659	draw_cg256_screen(bitmap,cliprect,0,pri);
657	660	break;
658	661	case 0x97:
659		draw_cg16_screen(machine,bitmap,cliprect,2,640,pri);
	662	draw_cg16_screen(bitmap,cliprect,2,640,pri);
660	663	break;
661	664	default:
662	665	popmessage("Unsupported CG mode %02x, contact MESS dev",m_cg_reg[0x0e]);
r21160	r21161
671	674	if(m_screen_enable)
672	675	return 0;
673	676
674		draw_cg_screen(machine(),bitmap,cliprect,0);
675		draw_tv_screen(machine(),bitmap,cliprect);
676		draw_cg_screen(machine(),bitmap,cliprect,1);
	677	draw_cg_screen(bitmap,cliprect,0);
	678	draw_tv_screen(bitmap,cliprect);
	679	draw_cg_screen(bitmap,cliprect,1);
677	680	//  popmessage("%02x (%02x %02x) (%02x %02x) (%02x %02x) (%02x %02x)",m_cg_reg[0x0f],m_cg_reg[0x10],m_cg_reg[0x11],m_cg_reg[0x12],m_cg_reg[0x13],m_cg_reg[0x14],m_cg_reg[0x15],m_cg_reg[0x16],m_cg_reg[0x17]);
678	681	//  popmessage("%02x",m_text_reg[0x0f]);
679	682
r21160	r21161
681	684	return 0;
682	685	}
683	686
684		static void mz2500_reconfigure_screen(running_machine &machine)
	687	void mz2500_state::mz2500_reconfigure_screen()
685	688	{
686		mz2500_state *state = machine.driver_data<mz2500_state>();
687	689	rectangle visarea;
688	690
689		if((state->m_cg_reg[0x0e] & 0x1f) == 0x17 || (state->m_cg_reg[0x0e] & 0x1f) == 0x03 || state->m_text_col_size)
690		state->m_scr_x_size = 640;
	691	if((m_cg_reg[0x0e] & 0x1f) == 0x17 || (m_cg_reg[0x0e] & 0x1f) == 0x03 || m_text_col_size)
	692	m_scr_x_size = 640;
691	693	else
692		state->m_scr_x_size = 320;
	694	m_scr_x_size = 320;
693	695
694		if((state->m_cg_reg[0x0e] & 0x1f) == 0x03)
695		state->m_scr_y_size = 400;
	696	if((m_cg_reg[0x0e] & 0x1f) == 0x03)
	697	m_scr_y_size = 400;
696	698	else
697		state->m_scr_y_size = 200 * ((state->m_text_font_reg) ? 1 : 2);
	699	m_scr_y_size = 200 * ((m_text_font_reg) ? 1 : 2);
698	700
699		visarea.set(0, state->m_scr_x_size - 1, 0, state->m_scr_y_size - 1);
	701	visarea.set(0, m_scr_x_size - 1, 0, m_scr_y_size - 1);
700	702
701		//popmessage("%d %d %d %d %02x",vs,ve,hs,he,state->m_cg_reg[0x0e]);
	703	//popmessage("%d %d %d %d %02x",vs,ve,hs,he,m_cg_reg[0x0e]);
702	704
703		machine.primary_screen->configure(720, 480, visarea, machine.primary_screen->frame_period().attoseconds);
	705	machine().primary_screen->configure(720, 480, visarea, machine().primary_screen->frame_period().attoseconds);
704	706
705	707	/* calculate CG window parameters here */
706		state->m_cg_vs = (state->m_cg_reg[0x08]) | ((state->m_cg_reg[0x09]<<8) & 1);
707		state->m_cg_ve = (state->m_cg_reg[0x0a]) | ((state->m_cg_reg[0x0b]<<8) & 1);
708		state->m_cg_hs = ((state->m_cg_reg[0x0c] & 0x7f)*8);
709		state->m_cg_he = ((state->m_cg_reg[0x0d] & 0x7f)*8);
	708	m_cg_vs = (m_cg_reg[0x08]) | ((m_cg_reg[0x09]<<8) & 1);
	709	m_cg_ve = (m_cg_reg[0x0a]) | ((m_cg_reg[0x0b]<<8) & 1);
	710	m_cg_hs = ((m_cg_reg[0x0c] & 0x7f)*8);
	711	m_cg_he = ((m_cg_reg[0x0d] & 0x7f)*8);
710	712
711		if(state->m_scr_x_size == 320)
	713	if(m_scr_x_size == 320)
712	714	{
713		state->m_cg_hs /= 2;
714		state->m_cg_he /= 2;
	715	m_cg_hs /= 2;
	716	m_cg_he /= 2;
715	717	}
716	718
717	719	/* calculate TV window parameters here */
718	720	{
719	721	int x_offs,y_offs;
720	722
721		state->m_monitor_type = ((state->m_text_reg[0x0f] & 0x08) >> 3);
	723	m_monitor_type = ((m_text_reg[0x0f] & 0x08) >> 3);
722	724
723		switch((state->m_monitor_type|state->m_text_col_size<<1) & 3)
	725	switch((m_monitor_type|m_text_col_size<<1) & 3)
724	726	{
725	727	default:
726	728	case 0: x_offs = 64; break;
r21160	r21161
728	730	case 2: x_offs = 72; break;
729	731	case 3: x_offs = 88; break;
730	732	}
731		//printf("%d %d %d\n",x_offs,(state->m_text_reg[7] & 0x7f) * 8,(state->m_text_reg[8] & 0x7f)* 8);
	733	//printf("%d %d %d\n",x_offs,(m_text_reg[7] & 0x7f) * 8,(m_text_reg[8] & 0x7f)* 8);
732	734
733		y_offs = (state->m_monitor_type) ? 76 : 34;
	735	y_offs = (m_monitor_type) ? 76 : 34;
734	736
735		state->m_tv_hs = ((state->m_text_reg[7] & 0x7f)*8) - x_offs;
736		state->m_tv_he = ((state->m_text_reg[8] & 0x7f)*8) - x_offs;
737		state->m_tv_vs = (state->m_text_reg[3]*2) - y_offs;
738		state->m_tv_ve = (state->m_text_reg[5]*2) - y_offs;
	737	m_tv_hs = ((m_text_reg[7] & 0x7f)*8) - x_offs;
	738	m_tv_he = ((m_text_reg[8] & 0x7f)*8) - x_offs;
	739	m_tv_vs = (m_text_reg[3]*2) - y_offs;
	740	m_tv_ve = (m_text_reg[5]*2) - y_offs;
739	741
740		if(state->m_scr_x_size == 320)
	742	if(m_scr_x_size == 320)
741	743	{
742		state->m_tv_hs /= 2;
743		state->m_tv_he /= 2;
	744	m_tv_hs /= 2;
	745	m_tv_he /= 2;
744	746	}
745	747
746		if(state->m_scr_y_size == 200)
	748	if(m_scr_y_size == 200)
747	749	{
748		state->m_tv_vs /= 2;
749		state->m_tv_ve /= 2;
	750	m_tv_vs /= 2;
	751	m_tv_ve /= 2;
750	752	}
751	753	}
752	754	}
r21160	r21161
1050	1052	[0x0f] ---- x--- sets monitor type interlace / progressive
1051	1053	*/
1052	1054
1053		static UINT8 pal_256_param(int index, int param)
	1055	UINT8 mz2500_state::pal_256_param(int index, int param)
1054	1056	{
1055	1057	UINT8 val = 0;
1056	1058
r21160	r21161
1084	1086	#endif
1085	1087	//popmessage("%d %02x %d %02x %d %d",m_text_reg[3],m_text_reg[4],m_text_reg[5],m_text_reg[6],m_text_reg[7]*8,m_text_reg[8]*8);
1086	1088
1087		mz2500_reconfigure_screen(machine());
	1089	mz2500_reconfigure_screen();
1088	1090
1089	1091	if(m_text_reg_index == 0x0a) // set 256 color palette
1090	1092	{
r21160	r21161
1140	1142	case 3:
1141	1143	/* Font size reg */
1142	1144	m_text_font_reg = data & 1;
1143		mz2500_reconfigure_screen(machine());
	1145	mz2500_reconfigure_screen();
1144	1146	break;
1145	1147	}
1146	1148	}
r21160	r21161
1389	1391	}
1390	1392
1391	1393	{
1392		mz2500_reconfigure_screen(machine());
	1394	mz2500_reconfigure_screen();
1393	1395	}
1394	1396
1395	1397	if(m_cg_reg_index & 0x80) //enable auto-inc
r21160	r21161
1722	1724	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
1723	1725	INPUT_PORTS_END
1724	1726
1725		static void mz2500_reset(mz2500_state *state, UINT8 type)
	1727	void mz2500_state::mz2500_reset(mz2500_state *state, UINT8 type)
1726	1728	{
1727	1729	int i;
1728	1730
1729	1731	for(i=0;i<8;i++)
1730		state->m_bank_val[i] = bank_reset_val[type][i];
	1732	m_bank_val[i] = bank_reset_val[type][i];
1731	1733	}
1732	1734
1733	1735	static const gfx_layout mz2500_pcg_layout_1bpp =
r21160	r21161
1945	1947	{
1946	1948	m_text_col_size = ((data & 0x20) >> 5);
1947	1949	m_prev_col_val = m_text_col_size;
1948		mz2500_reconfigure_screen(machine());
	1950	mz2500_reconfigure_screen();
1949	1951	}
1950	1952	m_key_mux = data & 0x1f;
1951	1953	}

trunk/src/mess/drivers/ip20.c

r21160	r21161
67	67	required_device<wd33c93_device> m_wd33c93;
68	68	required_device<scc8530_t> m_scc;
69	69	required_device<eeprom_device> m_eeprom;
	70	inline void ATTR_PRINTF(3,4) verboselog(int n_level, const char *s_fmt, ... );
70	71	};
71	72
72	73
73	74	#define VERBOSE_LEVEL ( 2 )
74	75
75		INLINE void ATTR_PRINTF(3,4) verboselog(running_machine &machine, int n_level, const char *s_fmt, ... )
	76	inline void ATTR_PRINTF(3,4) ip20_state::verboselog(int n_level, const char *s_fmt, ... )
76	77	{
77	78	if( VERBOSE_LEVEL >= n_level )
78	79	{
r21160	r21161
81	82	va_start( v, s_fmt );
82	83	vsprintf( buf, s_fmt, v );
83	84	va_end( v );
84		logerror( "%08x: %s", machine.device("maincpu")->safe_pc(), buf );
	85	logerror( "%08x: %s", machine().device("maincpu")->safe_pc(), buf );
85	86	}
86	87	}
87	88
r21160	r21161
122	123	offset <<= 2;
123	124	if( offset >= 0x0e00 && offset <= 0x0e7c )
124	125	{
125		verboselog(machine(), 2, "RTC RAM[0x%02x] Read: %02x\n", ( offset - 0xe00 ) >> 2, m_RTC.nRAM[ ( offset - 0xe00 ) >> 2 ] );
	126	verboselog(2, "RTC RAM[0x%02x] Read: %02x\n", ( offset - 0xe00 ) >> 2, m_RTC.nRAM[ ( offset - 0xe00 ) >> 2 ] );
126	127	return m_RTC.nRAM[ ( offset - 0xe00 ) >> 2 ];
127	128	}
128	129	switch( offset )
129	130	{
130	131	case 0x05c:
131		verboselog(machine(), 2, "HPC Unknown Read: %08x (%08x) (returning 0x000000a5 as kludge)\n", 0x1fb80000 + offset, mem_mask );
	132	verboselog(2, "HPC Unknown Read: %08x (%08x) (returning 0x000000a5 as kludge)\n", 0x1fb80000 + offset, mem_mask );
132	133	return 0x0000a500;
133	134	case 0x00ac:
134		verboselog(machine(), 2, "HPC Parallel Buffer Pointer Read: %08x (%08x)\n", m_HPC.nParBufPtr, mem_mask );
	135	verboselog(2, "HPC Parallel Buffer Pointer Read: %08x (%08x)\n", m_HPC.nParBufPtr, mem_mask );
135	136	return m_HPC.nParBufPtr;
136	137	case 0x00c0:
137		verboselog(machine(), 2, "HPC Endianness Read: %08x (%08x)\n", 0x0000001f, mem_mask );
	138	verboselog(2, "HPC Endianness Read: %08x (%08x)\n", 0x0000001f, mem_mask );
138	139	return 0x0000001f;
139	140	case 0x0120:
140	141	if (ACCESSING_BITS_8_15)
r21160	r21161
155	156	return 0;
156	157	}
157	158	case 0x01b0:
158		verboselog(machine(), 2, "HPC Misc. Status Read: %08x (%08x)\n", m_HPC.nMiscStatus, mem_mask );
	159	verboselog(2, "HPC Misc. Status Read: %08x (%08x)\n", m_HPC.nMiscStatus, mem_mask );
159	160	return m_HPC.nMiscStatus;
160	161	case 0x01bc:
161	162	//      verboselog(machine, 2, "HPC CPU Serial EEPROM Read\n" );
162	163	return m_eeprom->read_bit() << 4;
163	164	case 0x01c4:
164		verboselog(machine(), 2, "HPC Local IO Register 0 Mask Read: %08x (%08x)\n", m_HPC.nLocalIOReg0Mask, mem_mask );
	165	verboselog(2, "HPC Local IO Register 0 Mask Read: %08x (%08x)\n", m_HPC.nLocalIOReg0Mask, mem_mask );
165	166	return m_HPC.nLocalIOReg0Mask;
166	167	case 0x01cc:
167		verboselog(machine(), 2, "HPC Local IO Register 1 Mask Read: %08x (%08x)\n", m_HPC.nLocalIOReg0Mask, mem_mask );
	168	verboselog(2, "HPC Local IO Register 1 Mask Read: %08x (%08x)\n", m_HPC.nLocalIOReg0Mask, mem_mask );
168	169	return m_HPC.nLocalIOReg1Mask;
169	170	case 0x01d4:
170		verboselog(machine(), 2, "HPC VME Interrupt Mask 0 Read: %08x (%08x)\n", m_HPC.nLocalIOReg0Mask, mem_mask );
	171	verboselog(2, "HPC VME Interrupt Mask 0 Read: %08x (%08x)\n", m_HPC.nLocalIOReg0Mask, mem_mask );
171	172	return m_HPC.nVMEIntMask0;
172	173	case 0x01d8:
173		verboselog(machine(), 2, "HPC VME Interrupt Mask 1 Read: %08x (%08x)\n", m_HPC.nLocalIOReg0Mask, mem_mask );
	174	verboselog(2, "HPC VME Interrupt Mask 1 Read: %08x (%08x)\n", m_HPC.nLocalIOReg0Mask, mem_mask );
174	175	return m_HPC.nVMEIntMask1;
175	176	case 0x0d00:
176		verboselog(machine(), 2, "HPC DUART0 Channel B Control Read\n" );
	177	verboselog(2, "HPC DUART0 Channel B Control Read\n" );
177	178	//      return 0x00000004;
178	179	return 0x7c; //m_scc->reg_r(space, 0);
179	180	case 0x0d04:
180		verboselog(machine(), 2, "HPC DUART0 Channel B Data Read\n" );
	181	verboselog(2, "HPC DUART0 Channel B Data Read\n" );
181	182	//      return 0;
182	183	return m_scc->reg_r(space, 2);
183	184	case 0x0d08:
184		verboselog(machine(), 2, "HPC DUART0 Channel A Control Read (%08x)\n", mem_mask  );
	185	verboselog(2, "HPC DUART0 Channel A Control Read (%08x)\n", mem_mask  );
185	186	//      return 0x40;
186	187	return 0x7c; //m_scc->reg_r(space, 1);
187	188	case 0x0d0c:
188		verboselog(machine(), 2, "HPC DUART0 Channel A Data Read\n" );
	189	verboselog(2, "HPC DUART0 Channel A Data Read\n" );
189	190	//      return 0;
190	191	return m_scc->reg_r(space, 3);
191	192	case 0x0d10:
192	193	//      verboselog(machine, 2, "HPC DUART1 Channel B Control Read\n" );
193	194	return 0x00000004;
194	195	case 0x0d14:
195		verboselog(machine(), 2, "HPC DUART1 Channel B Data Read\n" );
	196	verboselog(2, "HPC DUART1 Channel B Data Read\n" );
196	197	return 0;
197	198	case 0x0d18:
198		verboselog(machine(), 2, "HPC DUART1 Channel A Control Read\n" );
	199	verboselog(2, "HPC DUART1 Channel A Control Read\n" );
199	200	return 0;
200	201	case 0x0d1c:
201		verboselog(machine(), 2, "HPC DUART1 Channel A Data Read\n" );
	202	verboselog(2, "HPC DUART1 Channel A Data Read\n" );
202	203	return 0;
203	204	case 0x0d20:
204		verboselog(machine(), 2, "HPC DUART2 Channel B Control Read\n" );
	205	verboselog(2, "HPC DUART2 Channel B Control Read\n" );
205	206	return 0x00000004;
206	207	case 0x0d24:
207		verboselog(machine(), 2, "HPC DUART2 Channel B Data Read\n" );
	208	verboselog(2, "HPC DUART2 Channel B Data Read\n" );
208	209	return 0;
209	210	case 0x0d28:
210		verboselog(machine(), 2, "HPC DUART2 Channel A Control Read\n" );
	211	verboselog(2, "HPC DUART2 Channel A Control Read\n" );
211	212	return 0;
212	213	case 0x0d2c:
213		verboselog(machine(), 2, "HPC DUART2 Channel A Data Read\n" );
	214	verboselog(2, "HPC DUART2 Channel A Data Read\n" );
214	215	return 0;
215	216	case 0x0d30:
216		verboselog(machine(), 2, "HPC DUART3 Channel B Control Read\n" );
	217	verboselog(2, "HPC DUART3 Channel B Control Read\n" );
217	218	return 0x00000004;
218	219	case 0x0d34:
219		verboselog(machine(), 2, "HPC DUART3 Channel B Data Read\n" );
	220	verboselog(2, "HPC DUART3 Channel B Data Read\n" );
220	221	return 0;
221	222	case 0x0d38:
222		verboselog(machine(), 2, "HPC DUART3 Channel A Control Read\n" );
	223	verboselog(2, "HPC DUART3 Channel A Control Read\n" );
223	224	return 0;
224	225	case 0x0d3c:
225		verboselog(machine(), 2, "HPC DUART3 Channel A Data Read\n" );
	226	verboselog(2, "HPC DUART3 Channel A Data Read\n" );
226	227	return 0;
227	228	}
228		verboselog(machine(), 0, "Unmapped HPC read: 0x%08x (%08x)\n", 0x1fb80000 + offset, mem_mask );
	229	verboselog(0, "Unmapped HPC read: 0x%08x (%08x)\n", 0x1fb80000 + offset, mem_mask );
229	230	return 0;
230	231	}
231	232
r21160	r21161
234	235	offset <<= 2;
235	236	if( offset >= 0x0e00 && offset <= 0x0e7c )
236	237	{
237		verboselog(machine(), 2, "RTC RAM[0x%02x] Write: %02x\n", ( offset - 0xe00 ) >> 2, data & 0x000000ff );
	238	verboselog(2, "RTC RAM[0x%02x] Write: %02x\n", ( offset - 0xe00 ) >> 2, data & 0x000000ff );
238	239	m_RTC.nRAM[ ( offset - 0xe00 ) >> 2 ] = data & 0x000000ff;
239	240	switch( ( offset - 0xe00 ) >> 2 )
240	241	{
r21160	r21161
284	285	break;
285	286
286	287	case 0x00ac:
287		verboselog(machine(), 2, "HPC Parallel Buffer Pointer Write: %08x (%08x)\n", data, mem_mask );
	288	verboselog(2, "HPC Parallel Buffer Pointer Write: %08x (%08x)\n", data, mem_mask );
288	289	m_HPC.nParBufPtr = data;
289	290	break;
290	291	case 0x0120:
291	292	if (ACCESSING_BITS_8_15)
292	293	{
293		verboselog(machine(), 2, "HPC SCSI Controller Register Write: %08x\n", ( data >> 8 ) & 0x000000ff );
	294	verboselog(2, "HPC SCSI Controller Register Write: %08x\n", ( data >> 8 ) & 0x000000ff );
294	295	m_wd33c93->write( space, 0, ( data >> 8 ) & 0x000000ff );
295	296	}
296	297	else
r21160	r21161
301	302	case 0x0124:
302	303	if (ACCESSING_BITS_8_15)
303	304	{
304		verboselog(machine(), 2, "HPC SCSI Controller Data Write: %08x\n", ( data >> 8 ) & 0x000000ff );
	305	verboselog(2, "HPC SCSI Controller Data Write: %08x\n", ( data >> 8 ) & 0x000000ff );
305	306	m_wd33c93->write( space, 1, ( data >> 8 ) & 0x000000ff );
306	307	}
307	308	else
r21160	r21161
310	311	}
311	312	break;
312	313	case 0x01b0:
313		verboselog(machine(), 2, "HPC Misc. Status Write: %08x (%08x)\n", data, mem_mask );
	314	verboselog(2, "HPC Misc. Status Write: %08x (%08x)\n", data, mem_mask );
314	315	if( data & 0x00000001 )
315	316	{
316		verboselog(machine(), 2, "  Force DSP hard reset\n" );
	317	verboselog(2, "  Force DSP hard reset\n" );
317	318	}
318	319	if( data & 0x00000002 )
319	320	{
320		verboselog(machine(), 2, "  Force IRQA\n" );
	321	verboselog(2, "  Force IRQA\n" );
321	322	}
322	323	if( data & 0x00000004 )
323	324	{
324		verboselog(machine(), 2, "  Set IRQA polarity high\n" );
	325	verboselog(2, "  Set IRQA polarity high\n" );
325	326	}
326	327	else
327	328	{
328		verboselog(machine(), 2, "  Set IRQA polarity low\n" );
	329	verboselog(2, "  Set IRQA polarity low\n" );
329	330	}
330	331	if( data & 0x00000008 )
331	332	{
332		verboselog(machine(), 2, "  SRAM size: 32K\n" );
	333	verboselog(2, "  SRAM size: 32K\n" );
333	334	}
334	335	else
335	336	{
336		verboselog(machine(), 2, "  SRAM size:  8K\n" );
	337	verboselog(2, "  SRAM size:  8K\n" );
337	338	}
338	339	m_HPC.nMiscStatus = data;
339	340	break;
r21160	r21161
341	342	//      verboselog(machine, 2, "HPC CPU Serial EEPROM Write: %08x (%08x)\n", data, mem_mask );
342	343	if( data & 0x00000001 )
343	344	{
344		verboselog(machine(), 2, "    CPU board LED on\n" );
	345	verboselog(2, "    CPU board LED on\n" );
345	346	}
346	347	m_eeprom->write_bit((data & 0x00000008) ? 1 : 0 );
347	348	m_eeprom->set_cs_line((data & 0x00000002) ? ASSERT_LINE : CLEAR_LINE );
348	349	m_eeprom->set_clock_line((data & 0x00000004) ? CLEAR_LINE : ASSERT_LINE );
349	350	break;
350	351	case 0x01c4:
351		verboselog(machine(), 2, "HPC Local IO Register 0 Mask Write: %08x (%08x)\n", data, mem_mask );
	352	verboselog(2, "HPC Local IO Register 0 Mask Write: %08x (%08x)\n", data, mem_mask );
352	353	m_HPC.nLocalIOReg0Mask = data;
353	354	break;
354	355	case 0x01cc:
355		verboselog(machine(), 2, "HPC Local IO Register 1 Mask Write: %08x (%08x)\n", data, mem_mask );
	356	verboselog(2, "HPC Local IO Register 1 Mask Write: %08x (%08x)\n", data, mem_mask );
356	357	m_HPC.nLocalIOReg1Mask = data;
357	358	break;
358	359	case 0x01d4:
359		verboselog(machine(), 2, "HPC VME Interrupt Mask 0 Write: %08x (%08x)\n", data, mem_mask );
	360	verboselog(2, "HPC VME Interrupt Mask 0 Write: %08x (%08x)\n", data, mem_mask );
360	361	m_HPC.nVMEIntMask0 = data;
361	362	break;
362	363	case 0x01d8:
363		verboselog(machine(), 2, "HPC VME Interrupt Mask 1 Write: %08x (%08x)\n", data, mem_mask );
	364	verboselog(2, "HPC VME Interrupt Mask 1 Write: %08x (%08x)\n", data, mem_mask );
364	365	m_HPC.nVMEIntMask1 = data;
365	366	break;
366	367	case 0x0d00:
367		verboselog(machine(), 2, "HPC DUART0 Channel B Control Write: %08x (%08x)\n", data, mem_mask );
	368	verboselog(2, "HPC DUART0 Channel B Control Write: %08x (%08x)\n", data, mem_mask );
368	369	m_scc->reg_w(space, 0, data);
369	370	break;
370	371	case 0x0d04:
371		verboselog(machine(), 2, "HPC DUART0 Channel B Data Write: %08x (%08x)\n", data, mem_mask );
	372	verboselog(2, "HPC DUART0 Channel B Data Write: %08x (%08x)\n", data, mem_mask );
372	373	m_scc->reg_w(space, 2, data);
373	374	break;
374	375	case 0x0d08:
375		verboselog(machine(), 2, "HPC DUART0 Channel A Control Write: %08x (%08x)\n", data, mem_mask );
	376	verboselog(2, "HPC DUART0 Channel A Control Write: %08x (%08x)\n", data, mem_mask );
376	377	m_scc->reg_w(space, 1, data);
377	378	break;
378	379	case 0x0d0c:
379		verboselog(machine(), 2, "HPC DUART0 Channel A Data Write: %08x (%08x)\n", data, mem_mask );
	380	verboselog(2, "HPC DUART0 Channel A Data Write: %08x (%08x)\n", data, mem_mask );
380	381	m_scc->reg_w(space, 3, data);
381	382	break;
382	383	case 0x0d10:
383	384	if( ( data & 0x000000ff ) >= 0x00000020 )
384	385	{
385		//          verboselog(machine(), 2, "HPC DUART1 Channel B Control Write: %08x (%08x) %c\n", data, mem_mask, data & 0x000000ff );
	386	//          verboselog(2, "HPC DUART1 Channel B Control Write: %08x (%08x) %c\n", data, mem_mask, data & 0x000000ff );
386	387	//mame_printf_info( "%c", data & 0x000000ff );
387	388	}
388	389	else
389	390	{
390		//          verboselog(machine(), 2, "HPC DUART1 Channel B Control Write: %08x (%08x)\n", data, mem_mask );
	391	//          verboselog(2, "HPC DUART1 Channel B Control Write: %08x (%08x)\n", data, mem_mask );
391	392	}
392	393	break;
393	394	case 0x0d14:
394	395	if( ( data & 0x000000ff ) >= 0x00000020 || ( data & 0x000000ff ) == 0x0d || ( data & 0x000000ff ) == 0x0a )
395	396	{
396		verboselog(machine(), 2, "HPC DUART1 Channel B Data Write: %08x (%08x) %c\n", data, mem_mask, data & 0x000000ff );
	397	verboselog(2, "HPC DUART1 Channel B Data Write: %08x (%08x) %c\n", data, mem_mask, data & 0x000000ff );
397	398	mame_printf_info( "%c", data & 0x000000ff );
398	399	}
399	400	else
400	401	{
401		verboselog(machine(), 2, "HPC DUART1 Channel B Data Write: %08x (%08x)\n", data, mem_mask );
	402	verboselog(2, "HPC DUART1 Channel B Data Write: %08x (%08x)\n", data, mem_mask );
402	403	}
403	404	break;
404	405	case 0x0d18:
405	406	mame_printf_info("HPC DUART1 Channel A Control Write: %08x (%08x)\n", data, mem_mask );
406	407	break;
407	408	case 0x0d1c:
408		verboselog(machine(), 2, "HPC DUART1 Channel A Data Write: %08x (%08x)\n", data, mem_mask );
	409	verboselog(2, "HPC DUART1 Channel A Data Write: %08x (%08x)\n", data, mem_mask );
409	410	break;
410	411	case 0x0d20:
411	412	mame_printf_info("HPC DUART2 Channel B Control Write: %08x (%08x)\n", data, mem_mask );
412	413	break;
413	414	case 0x0d24:
414		verboselog(machine(), 2, "HPC DUART2 Channel B Data Write: %08x (%08x)\n", data, mem_mask );
	415	verboselog(2, "HPC DUART2 Channel B Data Write: %08x (%08x)\n", data, mem_mask );
415	416	break;
416	417	case 0x0d28:
417	418	mame_printf_info("HPC DUART2 Channel A Control Write: %08x (%08x)\n", data, mem_mask );
418	419	break;
419	420	case 0x0d2c:
420		verboselog(machine(), 2, "HPC DUART2 Channel A Data Write: %08x (%08x)\n", data, mem_mask );
	421	verboselog(2, "HPC DUART2 Channel A Data Write: %08x (%08x)\n", data, mem_mask );
421	422	break;
422	423	case 0x0d30:
423	424	mame_printf_info("HPC DUART3 Channel B Control Write: %08x (%08x)\n", data, mem_mask );
424	425	break;
425	426	case 0x0d34:
426		verboselog(machine(), 2, "HPC DUART3 Channel B Data Write: %08x (%08x)\n", data, mem_mask );
	427	verboselog(2, "HPC DUART3 Channel B Data Write: %08x (%08x)\n", data, mem_mask );
427	428	break;
428	429	case 0x0d38:
429	430	mame_printf_info("HPC DUART3 Channel A Control Write: %08x (%08x)\n", data, mem_mask );
430	431	break;
431	432	case 0x0d3c:
432		verboselog(machine(), 2, "HPC DUART3 Channel A Data Write: %08x (%08x)\n", data, mem_mask );
	433	verboselog(2, "HPC DUART3 Channel A Data Write: %08x (%08x)\n", data, mem_mask );
433	434	break;
434	435	default:
435	436	mame_printf_info("Unmapped HPC write: 0x%08x (%08x): %08x\n", 0x1fb80000 + offset, mem_mask, data);

trunk/src/mess/drivers/vt100.c

r21160	r21161
63	63	INTERRUPT_GEN_MEMBER(vt100_vertical_interrupt);
64	64	TIMER_DEVICE_CALLBACK_MEMBER(keyboard_callback);
65	65	IRQ_CALLBACK_MEMBER(vt100_irq_callback);
	66	UINT8 bit_sel(UINT8 data);
66	67	};
67	68
68	69
r21160	r21161
107	108	return ret;
108	109	}
109	110
110		static UINT8 bit_sel(UINT8 data)
	111	UINT8 vt100_state::bit_sel(UINT8 data)
111	112	{
112	113	if (!BIT(data,7)) return 0x70;
113	114	if (!BIT(data,6)) return 0x60;

trunk/src/mess/drivers/mmodular.c

r21160	r21161
205	205	TIMER_DEVICE_CALLBACK_MEMBER(timer_update_irq2);
206	206	TIMER_DEVICE_CALLBACK_MEMBER(timer_update_irq_academy);
207	207	void common_chess_start();
	208	UINT8 convert_imputmask(UINT8 input);
	209	UINT8 convertMCIV2LED(UINT8 codedchar);
	210	void write_IOenable(unsigned char data,address_space &space);
208	211	};
209	212
210		static UINT8 convert_imputmask(UINT8 input)
	213	UINT8 polgar_state::convert_imputmask(UINT8 input)
211	214	{
212	215	input^=0xff;
213	216	switch (input) {
r21160	r21161
513	516	logerror("LEDs  Offset = %d Data = %d\n",offset,data);
514	517	}
515	518
516		static UINT8 convertMCIV2LED(UINT8 codedchar)
	519	UINT8 polgar_state::convertMCIV2LED(UINT8 codedchar)
517	520	{
518	521	UINT8 data = 0;
519	522	if (BIT(codedchar,0)) data |= 0x80;
r21160	r21161
857	860
858	861	}
859	862
860		static void write_IOenable(unsigned char data,address_space &space) {
	863	void polgar_state::write_IOenable(unsigned char data,address_space &space)
	864	{
861	865	hd44780_device * hd44780 = space.machine().device<hd44780_device>("hd44780");
862	866	device_t *speaker = space.machine().device("beep");
863	867

trunk/src/mess/drivers/multi8.c

r21160	r21161
70	70	virtual void palette_init();
71	71	UINT32 screen_update_multi8(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
72	72	TIMER_DEVICE_CALLBACK_MEMBER(keyboard_callback);
	73	void multi8_draw_pixel(bitmap_ind16 &bitmap,int y,int x,UINT8 pen,UINT8 width);
73	74	};
74	75
75	76	#define mc6845_h_char_total     (m_crtc_vreg[0])
r21160	r21161
101	102	m_p_chargen = memregion("chargen")->base();
102	103	}
103	104
104		static void multi8_draw_pixel(running_machine &machine, bitmap_ind16 &bitmap,int y,int x,UINT8 pen,UINT8 width)
	105	void multi8_state::multi8_draw_pixel(bitmap_ind16 &bitmap,int y,int x,UINT8 pen,UINT8 width)
105	106	{
106		if(!machine.primary_screen->visible_area().contains(x, y))
	107	if(!machine().primary_screen->visible_area().contains(x, y))
107	108	return;
108	109
109	110	if(width)
r21160	r21161
148	149	else
149	150	color = (pen_b) | (pen_r << 1) | (pen_g << 2);
150	151
151		multi8_draw_pixel(machine(),bitmap, y, x*8+xi,m_pen_clut[color], 0);
	152	multi8_draw_pixel(bitmap, y, x*8+xi,m_pen_clut[color], 0);
152	153	}
153	154	count++;
154	155	}
r21160	r21161
176	177	pen = (m_p_chargen[tile*8+yi] >> (7-xi) & 1) ? color : 0;
177	178
178	179	if(pen)
179		multi8_draw_pixel(machine(),bitmap, y*mc6845_tile_height+yi, x*8+xi, pen, (m_display_reg & 0x40) == 0x00);
	180	multi8_draw_pixel(bitmap, y*mc6845_tile_height+yi, x*8+xi, pen, (m_display_reg & 0x40) == 0x00);
180	181	}
181	182	}
182	183
r21160	r21161
201	202	for (yc=0; yc<(mc6845_tile_height-(mc6845_cursor_y_start & 7)); yc++)
202	203	{
203	204	for (xc=0; xc<8; xc++)
204		multi8_draw_pixel(machine(),bitmap, y*mc6845_tile_height+yc, x*8+xc,0x07,(m_display_reg & 0x40) == 0x00);
	205	multi8_draw_pixel(bitmap, y*mc6845_tile_height+yc, x*8+xc,0x07,(m_display_reg & 0x40) == 0x00);
205	206
206	207	}
207	208	}

trunk/src/mess/drivers/vtech1.c

r21160	r21161
199	199	DECLARE_READ8_MEMBER(vtech1_printer_r);
200	200	DECLARE_WRITE8_MEMBER(vtech1_strobe_w);
201	201	DECLARE_READ8_MEMBER(vtech1_mc6847_videoram_r);
	202	void vtech1_get_track();
	203	void vtech1_put_track();
202	204	};
203	205
204	206
r21160	r21161
283	285	vtech1->m_fdc_wrprot[id] = 0x80;
284	286	}
285	287
286		static void vtech1_get_track(running_machine &machine)
	288	void vtech1_state::vtech1_get_track()
287	289	{
288		vtech1_state *vtech1 = machine.driver_data<vtech1_state>();
289		device_image_interface *image = dynamic_cast<device_image_interface *>(floppy_get_device(machine,vtech1->m_drive));
	290	device_image_interface *image = dynamic_cast<device_image_interface *>(floppy_get_device(machine(),m_drive));
290	291
291	292	/* drive selected or and image file ok? */
292		if (vtech1->m_drive >= 0 && image->exists())
	293	if (m_drive >= 0 && image->exists())
293	294	{
294	295	int size, offs;
295	296	size = TRKSIZE_VZ;
296		offs = TRKSIZE_VZ * vtech1->m_fdc_track_x2[vtech1->m_drive]/2;
	297	offs = TRKSIZE_VZ * m_fdc_track_x2[m_drive]/2;
297	298	image->fseek(offs, SEEK_SET);
298		size = image->fread(vtech1->m_fdc_data, size);
	299	size = image->fread(m_fdc_data, size);
299	300	if (LOG_VTECH1_FDC)
300	301	logerror("get track @$%05x $%04x bytes\n", offs, size);
301	302	}
302		vtech1->m_fdc_offs = 0;
303		vtech1->m_fdc_write = 0;
	303	m_fdc_offs = 0;
	304	m_fdc_write = 0;
304	305	}
305	306
306		static void vtech1_put_track(running_machine &machine)
	307	void vtech1_state::vtech1_put_track()
307	308	{
308		vtech1_state *vtech1 = machine.driver_data<vtech1_state>();
309	309
310	310
311	311	/* drive selected and image file ok? */
312		if (vtech1->m_drive >= 0 && floppy_get_device(machine,vtech1->m_drive) != NULL)
	312	if (m_drive >= 0 && floppy_get_device(machine(),m_drive) != NULL)
313	313	{
314	314	int size, offs;
315		device_image_interface *image = dynamic_cast<device_image_interface *>(floppy_get_device(machine,vtech1->m_drive));
316		offs = TRKSIZE_VZ * vtech1->m_fdc_track_x2[vtech1->m_drive]/2;
317		image->fseek(offs + vtech1->m_fdc_start, SEEK_SET);
318		size = image->fwrite(&vtech1->m_fdc_data[vtech1->m_fdc_start], vtech1->m_fdc_write);
	315	device_image_interface *image = dynamic_cast<device_image_interface *>(floppy_get_device(machine(),m_drive));
	316	offs = TRKSIZE_VZ * m_fdc_track_x2[m_drive]/2;
	317	image->fseek(offs + m_fdc_start, SEEK_SET);
	318	size = image->fwrite(&m_fdc_data[m_fdc_start], m_fdc_write);
319	319	if (LOG_VTECH1_FDC)
320		logerror("put track @$%05X+$%X $%04X/$%04X bytes\n", offs, vtech1->m_fdc_start, size, vtech1->m_fdc_write);
	320	logerror("put track @$%05X+$%X $%04X/$%04X bytes\n", offs, m_fdc_start, size, m_fdc_write);
321	321	}
322	322	}
323	323
r21160	r21161
380	380	{
381	381	m_drive = drive;
382	382	if (m_drive >= 0)
383		vtech1_get_track(machine());
	383	vtech1_get_track();
384	384	}
385	385	if (m_drive >= 0)
386	386	{
r21160	r21161
394	394	if (LOG_VTECH1_FDC)
395	395	logerror("vtech1_fdc_w(%d) $%02X drive %d: stepout track #%2d.%d\n", offset, data, m_drive, m_fdc_track_x2[m_drive]/2,5*(m_fdc_track_x2[m_drive]&1));
396	396	if ((m_fdc_track_x2[m_drive] & 1) == 0)
397		vtech1_get_track(machine());
	397	vtech1_get_track();
398	398	}
399	399	else
400	400	if ((PHI0(data) && !(PHI1(data) || PHI2(data) || PHI3(data)) && PHI3(m_fdc_latch)) ||
r21160	r21161
407	407	if (LOG_VTECH1_FDC)
408	408	logerror("vtech1_fdc_w(%d) $%02X drive %d: stepin track #%2d.%d\n", offset, data, m_drive, m_fdc_track_x2[m_drive]/2,5*(m_fdc_track_x2[m_drive]&1));
409	409	if ((m_fdc_track_x2[m_drive] & 1) == 0)
410		vtech1_get_track(machine());
	410	vtech1_get_track();
411	411	}
412	412	if ((data & 0x40) == 0)
413	413	{
r21160	r21161
452	452	{
453	453	/* data written to track before? */
454	454	if (m_fdc_write)
455		vtech1_put_track(machine());
	455	vtech1_put_track();
456	456	}
457	457	m_fdc_bits = 8;
458	458	m_fdc_write = 0;

trunk/src/mess/drivers/apexc.c

r21160	r21161
35	35	INTERRUPT_GEN_MEMBER(apexc_interrupt);
36	36	DECLARE_READ8_MEMBER(tape_read);
37	37	DECLARE_WRITE8_MEMBER(tape_write);
	38	void apexc_draw_led(bitmap_ind16 &bitmap, int x, int y, int state);
	39	void apexc_draw_char(bitmap_ind16 &bitmap, char character, int x, int y, int color);
	40	void apexc_draw_string(bitmap_ind16 &bitmap, const char *buf, int x, int y, int color);
	41	void apexc_teletyper_init();
	42	void apexc_teletyper_linefeed();
	43	void apexc_teletyper_putchar(int character);
38	44	};
39	45
40
41		static void apexc_teletyper_init(running_machine &machine);
42		static void apexc_teletyper_putchar(running_machine &machine, int character);
43
44
45	46	void apexc_state::machine_start()
46	47	{
47		apexc_teletyper_init(machine());
	48	apexc_teletyper_init();
48	49	}
49	50
50	51
r21160	r21161
287	288	if (image->exists())
288	289	image->fwrite(& data5, 1);
289	290
290		apexc_teletyper_putchar(machine(), data & 0x1f);    /* display on screen */
	291	apexc_teletyper_putchar(data & 0x1f);    /* display on screen */
291	292	}
292	293
293	294	/*
r21160	r21161
567	568	}
568	569
569	570	/* draw a small 8*8 LED (well, there were no LEDs at the time, so let's call this a lamp ;-) ) */
570		static void apexc_draw_led(bitmap_ind16 &bitmap, int x, int y, int state)
	571	void apexc_state::apexc_draw_led(bitmap_ind16 &bitmap, int x, int y, int state)
571	572	{
572	573	int xx, yy;
573	574
r21160	r21161
577	578	}
578	579
579	580	/* write a single char on screen */
580		static void apexc_draw_char(running_machine &machine, bitmap_ind16 &bitmap, char character, int x, int y, int color)
	581	void apexc_state::apexc_draw_char(bitmap_ind16 &bitmap, char character, int x, int y, int color)
581	582	{
582		drawgfx_transpen(bitmap, bitmap.cliprect(), machine.gfx[0], character-32, color, 0, 0,
	583	drawgfx_transpen(bitmap, bitmap.cliprect(), machine().gfx[0], character-32, color, 0, 0,
583	584	x+1, y, 0);
584	585	}
585	586
586	587	/* write a string on screen */
587		static void apexc_draw_string(running_machine &machine, bitmap_ind16 &bitmap, const char *buf, int x, int y, int color)
	588	void apexc_state::apexc_draw_string(bitmap_ind16 &bitmap, const char *buf, int x, int y, int color)
588	589	{
589	590	while (* buf)
590	591	{
591		apexc_draw_char(machine, bitmap, *buf, x, y, color);
	592	apexc_draw_char(bitmap, *buf, x, y, color);
592	593
593	594	x += 8;
594	595	buf++;
r21160	r21161
602	603	char the_char;
603	604
604	605	bitmap.fill(0, /*machine().visible_area*/panel_window);
605		apexc_draw_string(machine(), bitmap, "power", 8, 0, 0);
606		apexc_draw_string(machine(), bitmap, "running", 8, 8, 0);
607		apexc_draw_string(machine(), bitmap, "data :", 0, 24, 0);
	606	apexc_draw_string(bitmap, "power", 8, 0, 0);
	607	apexc_draw_string(bitmap, "running", 8, 8, 0);
	608	apexc_draw_string(bitmap, "data :", 0, 24, 0);
608	609
609	610	copybitmap(bitmap, *m_bitmap, 0, 0, 0, 0, teletyper_window);
610	611
r21160	r21161
617	618	{
618	619	apexc_draw_led(bitmap, i*8, 32, (m_panel_data_reg << i) & 0x80000000UL);
619	620	the_char = '0' + ((i + 1) % 10);
620		apexc_draw_char(machine(), bitmap, the_char, i*8, 40, 0);
	621	apexc_draw_char(bitmap, the_char, i*8, 40, 0);
621	622	if (((i + 1) % 10) == 0)
622	623	{
623	624	the_char = '0' + ((i + 1) / 10);
624		apexc_draw_char(machine(), bitmap, the_char, i*8, 48, 0);
	625	apexc_draw_char(bitmap, the_char, i*8, 48, 0);
625	626	}
626	627	}
627	628	return 0;
628	629	}
629	630
630		static void apexc_teletyper_init(running_machine &machine)
	631	void apexc_state::apexc_teletyper_init()
631	632	{
632		apexc_state *state = machine.driver_data<apexc_state>();
633	633
634		state->m_letters = FALSE;
635		state->m_pos = 0;
	634	m_letters = FALSE;
	635	m_pos = 0;
636	636	}
637	637
638		static void apexc_teletyper_linefeed(running_machine &machine)
	638	void apexc_state::apexc_teletyper_linefeed()
639	639	{
640		apexc_state *state = machine.driver_data<apexc_state>();
641	640	UINT8 buf[teletyper_window_width];
642	641	int y;
643	642
644	643	for (y=teletyper_window_offset_y; y<teletyper_window_offset_y+teletyper_window_height-teletyper_scroll_step; y++)
645	644	{
646		extract_scanline8(*state->m_bitmap, teletyper_window_offset_x, y+teletyper_scroll_step, teletyper_window_width, buf);
647		draw_scanline8(*state->m_bitmap, teletyper_window_offset_x, y, teletyper_window_width, buf, machine.pens);
	645	extract_scanline8(*m_bitmap, teletyper_window_offset_x, y+teletyper_scroll_step, teletyper_window_width, buf);
	646	draw_scanline8(*m_bitmap, teletyper_window_offset_x, y, teletyper_window_width, buf, machine().pens);
648	647	}
649	648
650		state->m_bitmap->fill(0, teletyper_scroll_clear_window);
	649	m_bitmap->fill(0, teletyper_scroll_clear_window);
651	650	}
652	651
653		static void apexc_teletyper_putchar(running_machine &machine, int character)
	652	void apexc_state::apexc_teletyper_putchar(int character)
654	653	{
655	654	static const char ascii_table[2][32] =
656	655	{
r21160	r21161
676	675	}
677	676	};
678	677
679		apexc_state *state = machine.driver_data<apexc_state>();
680	678	char buffer[2] = "x";
681	679
682	680	character &= 0x1f;
r21160	r21161
685	683	{
686	684	case 19:
687	685	/* Line Space */
688		apexc_teletyper_linefeed(machine);
	686	apexc_teletyper_linefeed();
689	687	break;
690	688
691	689	case 24:
692	690	/* Carriage Return */
693		state->m_pos = 0;
	691	m_pos = 0;
694	692	break;
695	693
696	694	case 27:
697	695	/* Figures */
698		state->m_letters = FALSE;
	696	m_letters = FALSE;
699	697	break;
700	698
701	699	case 31:
702	700	/* Letters */
703		state->m_letters = TRUE;
	701	m_letters = TRUE;
704	702	break;
705	703
706	704	default:
707	705	/* Any printable character... */
708	706
709		if (state->m_pos >= 32)
	707	if (m_pos >= 32)
710	708	{   /* if past right border, wrap around */
711		apexc_teletyper_linefeed(machine);  /* next line */
712		state->m_pos = 0;                   /* return to start of line */
	709	apexc_teletyper_linefeed();  /* next line */
	710	m_pos = 0;                   /* return to start of line */
713	711	}
714	712
715	713	/* print character */
716		buffer[0] = ascii_table[state->m_letters][character];   /* lookup ASCII equivalent in table */
	714	buffer[0] = ascii_table[m_letters][character];   /* lookup ASCII equivalent in table */
717	715	buffer[1] = '\0';                               /* terminate string */
718		apexc_draw_string(machine, *state->m_bitmap, buffer, 8*state->m_pos, 176, 0);   /* print char */
719		state->m_pos++;                                         /* step carriage forward */
	716	apexc_draw_string(*m_bitmap, buffer, 8*m_pos, 176, 0);   /* print char */
	717	m_pos++;                                         /* step carriage forward */
720	718
721	719	break;
722	720	}

trunk/src/mess/drivers/supracan.c

r21160	r21161
208	208	TIMER_CALLBACK_MEMBER(supracan_line_off_callback);
209	209	TIMER_CALLBACK_MEMBER(supracan_video_callback);
210	210	DECLARE_DEVICE_IMAGE_LOAD_MEMBER(supracan_cart);
	211	inline void verboselog(const char *tag, int n_level, const char *s_fmt, ...);
	212	int supracan_tilemap_get_region(int layer);
	213	void supracan_tilemap_get_info_common(int layer, tile_data &tileinfo, int count);
	214	void supracan_tilemap_get_info_roz(int layer, tile_data &tileinfo, int count);
	215	int get_tilemap_dimensions(int &xsize, int &ysize, int layer);
	216	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect);
	217	void mark_active_tilemap_all_dirty(int layer);
	218	void supracan_suprnova_draw_roz(bitmap_ind16 &bitmap, const rectangle &cliprect, tilemap_t *tmap, UINT32 startx, UINT32 starty, int incxx, int incxy, int incyx, int incyy, int wraparound/*, int columnscroll, UINT32* scrollram*/, int transmask);
211	219	};
212	220
213	221
214	222
215	223	#if ENABLE_VERBOSE_LOG
216		INLINE void verboselog(const char *tag, running_machine &machine, int n_level, const char *s_fmt, ...)
	224	inline void supracan_state::verboselog(const char *tag, int n_level, const char *s_fmt, ...)
217	225	{
218	226	if( VERBOSE_LEVEL >= n_level )
219	227	{
r21160	r21161
222	230	va_start( v, s_fmt );
223	231	vsprintf( buf, s_fmt, v );
224	232	va_end( v );
225		logerror( "%06x: %s: %s", machine.device(tag)->safe_pc(), tag, buf );
	233	logerror( "%06x: %s: %s", machine().device(tag)->safe_pc(), tag, buf );
226	234	}
227	235	}
228	236
r21160	r21161
230	238	#define verboselog(w,x,y,z,...)
231	239	#endif
232	240
233		static int supracan_tilemap_get_region(running_machine &machine, int layer)
	241	int supracan_state::supracan_tilemap_get_region(int layer)
234	242	{
235		supracan_state *state = machine.driver_data<supracan_state>();
236	243
237	244	// HACK!!!
238	245	if (layer==2)
r21160	r21161
245	252	{
246	253	// roz layer
247	254
248		int gfx_mode = (state->m_roz_mode & 3);
	255	int gfx_mode = (m_roz_mode & 3);
249	256
250	257	switch(gfx_mode)
251	258	{
r21160	r21161
259	266	else
260	267	{
261	268	// normal layers
262		int gfx_mode = (state->m_tilemap_mode[layer] & 0x7000) >> 12;
	269	int gfx_mode = (m_tilemap_mode[layer] & 0x7000) >> 12;
263	270
264	271	switch(gfx_mode)
265	272	{
r21160	r21161
274	281
275	282	}
276	283
277		static void supracan_tilemap_get_info_common(running_machine &machine, int layer, tile_data &tileinfo, int count)
	284	void supracan_state::supracan_tilemap_get_info_common(int layer, tile_data &tileinfo, int count)
278	285	{
279		supracan_state *state = machine.driver_data<supracan_state>();
280	286
281		UINT16* supracan_vram = state->m_vram;
	287	UINT16* supracan_vram = m_vram;
282	288
283		UINT32 base = (state->m_tilemap_base_addr[layer]);
284		int gfx_mode = (state->m_tilemap_mode[layer] & 0x7000) >> 12;
285		int region = supracan_tilemap_get_region(machine, layer);
	289	UINT32 base = (m_tilemap_base_addr[layer]);
	290	int gfx_mode = (m_tilemap_mode[layer] & 0x7000) >> 12;
	291	int region = supracan_tilemap_get_region(layer);
286	292
287	293	count += base;
288	294
r21160	r21161
311	317	break;
312	318
313	319	default:
314		verboselog("maincpu", machine, 0, "Unsupported tilemap mode: %d\n", (state->m_tilemap_mode[layer] & 0x7000) >> 12);
	320	verboselog("maincpu", 0, "Unsupported tilemap mode: %d\n", (m_tilemap_mode[layer] & 0x7000) >> 12);
315	321	break;
316	322	}
317	323
r21160	r21161
325	331	int flipxy = (supracan_vram[count] & 0x0c00)>>10;
326	332	int palette = ((supracan_vram[count] & 0xf000) >> 12) + palette_bank;
327	333
328		SET_TILE_INFO(region, tile, palette, TILE_FLIPXY(flipxy));
	334	SET_TILE_INFO_MEMBER(region, tile, palette, TILE_FLIPXY(flipxy));
329	335	}
330	336
331	337	// I wonder how different this really is.. my guess, not at all.
332		static void supracan_tilemap_get_info_roz(running_machine &machine, int layer, tile_data &tileinfo, int count)
	338	void supracan_state::supracan_tilemap_get_info_roz(int layer, tile_data &tileinfo, int count)
333	339	{
334		supracan_state *state = machine.driver_data<supracan_state>();
335	340
336		UINT16* supracan_vram = state->m_vram;
	341	UINT16* supracan_vram = m_vram;
337	342
338		UINT32 base = state->m_roz_base_addr;
	343	UINT32 base = m_roz_base_addr;
339	344
340	345
341	346	int region = 1;
342	347	UINT16 tile_bank = 0;
343	348	UINT16 palette_bank = 0;
344	349
345		region = supracan_tilemap_get_region(machine, layer);
	350	region = supracan_tilemap_get_region(layer);
346	351
347		switch(state->m_roz_mode & 3) //FIXME: fix gfx bpp order
	352	switch(m_roz_mode & 3) //FIXME: fix gfx bpp order
348	353	{
349	354	case 0:
350	355	// hack: case for startup logo
r21160	r21161
356	361	if (count & 0x20) tile ^= 1;
357	362	tile |= (count & 0xc0)>>2;
358	363
359		SET_TILE_INFO(region, tile, 0, 0);
	364	SET_TILE_INFO_MEMBER(region, tile, 0, 0);
360	365	return;
361	366	}
362	367
363	368
364	369	case 1:
365		tile_bank = (state->m_roz_tile_bank & 0xf000) >> 3;
	370	tile_bank = (m_roz_tile_bank & 0xf000) >> 3;
366	371	break;
367	372
368	373	case 2:
369		tile_bank = (state->m_roz_tile_bank & 0xf000) >> 3;
	374	tile_bank = (m_roz_tile_bank & 0xf000) >> 3;
370	375	break;
371	376
372	377	case 3:
373		tile_bank = (state->m_roz_tile_bank & 0xf000) >> 3;
	378	tile_bank = (m_roz_tile_bank & 0xf000) >> 3;
374	379	break;
375	380	}
376	381
r21160	r21161
380	385	int flipxy = (supracan_vram[count] & 0x0c00)>>10;
381	386	int palette = ((supracan_vram[count] & 0xf000) >> 12) + palette_bank;
382	387
383		SET_TILE_INFO(region, tile, palette, TILE_FLIPXY(flipxy));
	388	SET_TILE_INFO_MEMBER(region, tile, palette, TILE_FLIPXY(flipxy));
384	389	}
385	390
386	391
387	392
388	393	TILE_GET_INFO_MEMBER(supracan_state::get_supracan_tilemap0_tile_info)
389	394	{
390		supracan_tilemap_get_info_common(machine(), 0, tileinfo, tile_index);
	395	supracan_tilemap_get_info_common(0, tileinfo, tile_index);
391	396	}
392	397
393	398	TILE_GET_INFO_MEMBER(supracan_state::get_supracan_tilemap1_tile_info)
394	399	{
395		supracan_tilemap_get_info_common(machine(), 1, tileinfo, tile_index);
	400	supracan_tilemap_get_info_common(1, tileinfo, tile_index);
396	401	}
397	402
398	403	TILE_GET_INFO_MEMBER(supracan_state::get_supracan_tilemap2_tile_info)
399	404	{
400		supracan_tilemap_get_info_common(machine(), 2, tileinfo, tile_index);
	405	supracan_tilemap_get_info_common(2, tileinfo, tile_index);
401	406	}
402	407
403	408	TILE_GET_INFO_MEMBER(supracan_state::get_supracan_roz_tile_info)
404	409	{
405		supracan_tilemap_get_info_roz(machine(), 3, tileinfo, tile_index);
	410	supracan_tilemap_get_info_roz(3, tileinfo, tile_index);
406	411	}
407	412
408	413
r21160	r21161
435	440	m_tilemap_sizes[3][3] = &machine().tilemap().create(tilemap_get_info_delegate(FUNC(supracan_state::get_supracan_roz_tile_info),this), TILEMAP_SCAN_ROWS, 8, 8, 64, 64);
436	441	}
437	442
438		static int get_tilemap_dimensions(running_machine &machine, int &xsize, int &ysize, int layer)
	443	int supracan_state::get_tilemap_dimensions(int &xsize, int &ysize, int layer)
439	444	{
440		supracan_state *state = (supracan_state *)machine.driver_data<supracan_state>();
441	445	int select;
442	446
443	447	xsize = 32;
444	448	ysize = 32;
445	449
446		if (layer==3) select = (state->m_roz_mode & 0x0f00);
447		else select = state->m_tilemap_flags[layer] & 0x0f00;
	450	if (layer==3) select = (m_roz_mode & 0x0f00);
	451	else select = m_tilemap_flags[layer] & 0x0f00;
448	452
449	453	switch(select)
450	454	{
r21160	r21161
464	468	return 3;
465	469
466	470	default:
467		verboselog("maincpu", machine, 0, "Unsupported tilemap size for layer %d: %04x\n", layer, select);
	471	verboselog("maincpu", 0, "Unsupported tilemap size for layer %d: %04x\n", layer, select);
468	472	return 0;
469	473	}
470	474	}
r21160	r21161
472	476
473	477
474	478
475		static void draw_sprites(running_machine &machine, bitmap_ind16 &bitmap, const rectangle &cliprect)
	479	void supracan_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect)
476	480	{
477		supracan_state *state = machine.driver_data<supracan_state>();
478		UINT16 *supracan_vram = state->m_vram;
	481	UINT16 *supracan_vram = m_vram;
479	482
480	483	//      [0]
481	484	//      -e-- ---- ---- ---- sprite enable?
r21160	r21161
495	498	//      -ooo oooo oooo oooo Sprite address
496	499
497	500	UINT32 skip_count = 0;
498		UINT32 start_word = (state->m_sprite_base_addr >> 1) + skip_count * 4;
499		UINT32 end_word = start_word + (state->m_sprite_count - skip_count) * 4;
500		int region = (state->m_sprite_flags & 1) ? 0 : 1; //8bpp : 4bpp
	501	UINT32 start_word = (m_sprite_base_addr >> 1) + skip_count * 4;
	502	UINT32 end_word = start_word + (m_sprite_count - skip_count) * 4;
	503	int region = (m_sprite_flags & 1) ? 0 : 1; //8bpp : 4bpp
501	504
502	505	//  printf("frame\n");
503	506	#define VRAM_MASK (0xffff)
r21160	r21161
514	517	int sprite_xflip = (supracan_vram[i+1] & 0x0800) >> 11;
515	518	int sprite_yflip = (supracan_vram[i+1] & 0x0400) >> 10;
516	519	//int xscale = (supracan_vram[i+2] & 0xf000) >> 12;
517		gfx_element *gfx = machine.gfx[region];
	520	gfx_element *gfx = machine().gfx[region];
518	521
519	522
520	523
r21160	r21161
626	629
627	630
628	631
629		static void mark_active_tilemap_all_dirty(running_machine &machine, int layer)
	632	void supracan_state::mark_active_tilemap_all_dirty(int layer)
630	633	{
631		supracan_state *state = (supracan_state *)machine.driver_data<supracan_state>();
632	634	int xsize = 0;
633	635	int ysize = 0;
634	636
635	637	int which_tilemap_size;
636	638
637		which_tilemap_size = get_tilemap_dimensions(machine, xsize, ysize, layer);
	639	which_tilemap_size = get_tilemap_dimensions(xsize, ysize, layer);
638	640	//  for (int i=0;i<4;i++)
639		//    tilemap_mark_all_tiles_dirty(state->m_tilemap_sizes[layer][i]);
640		state->m_tilemap_sizes[layer][which_tilemap_size]->mark_all_dirty();
	641	//    tilemap_mark_all_tiles_dirty(m_tilemap_sizes[layer][i]);
	642	m_tilemap_sizes[layer][which_tilemap_size]->mark_all_dirty();
641	643	}
642	644
643	645
644	646
645	647	/* draws ROZ with linescroll OR columnscroll to 16-bit indexed bitmap */
646		static void supracan_suprnova_draw_roz(running_machine &machine, bitmap_ind16 &bitmap, const rectangle &cliprect, tilemap_t *tmap, UINT32 startx, UINT32 starty, int incxx, int incxy, int incyx, int incyy, int wraparound/*, int columnscroll, UINT32* scrollram*/, int transmask)
	648	void supracan_state::supracan_suprnova_draw_roz(bitmap_ind16 &bitmap, const rectangle &cliprect, tilemap_t *tmap, UINT32 startx, UINT32 starty, int incxx, int incxy, int incyx, int incyy, int wraparound/*, int columnscroll, UINT32* scrollram*/, int transmask)
647	649	{
648	650	//bitmap_ind16 *destbitmap = bitmap;
649	651	bitmap_ind16 &srcbitmap = tmap->pixmap();
r21160	r21161
779	781	m_sprite_final_bitmap.fill(0x00, visarea);
780	782	bitmap.fill(0x80, visarea);
781	783
782		draw_sprites(machine(), m_sprite_final_bitmap, visarea);
	784	draw_sprites( m_sprite_final_bitmap, visarea);
783	785	}
784	786	}
785	787	else
r21160	r21161
787	789	m_sprite_final_bitmap.fill(0x00, cliprect);
788	790	bitmap.fill(0x80, cliprect);
789	791
790		draw_sprites(machine(), m_sprite_final_bitmap, cliprect);
	792	draw_sprites(m_sprite_final_bitmap, cliprect);
791	793	}
792	794
793	795
r21160	r21161
826	828	if (priority==pri)
827	829	{
828	830	//            tilemap_num = layer;
829		which_tilemap_size = get_tilemap_dimensions(machine(), xsize, ysize, layer);
	831	which_tilemap_size = get_tilemap_dimensions(xsize, ysize, layer);
830	832	bitmap_ind16 &src_bitmap = m_tilemap_sizes[layer][which_tilemap_size]->pixmap();
831		int gfx_region = supracan_tilemap_get_region(machine(), layer);
	833	int gfx_region = supracan_tilemap_get_region(layer);
832	834	int transmask = 0xff;
833	835
834	836	switch (gfx_region)
r21160	r21161
949	951
950	952
951	953	if (m_vram[m_roz_unk_base0/2 + y]) // incxx = 0, no draw?
952		supracan_suprnova_draw_roz(machine(), bitmap, clip, m_tilemap_sizes[layer][which_tilemap_size], scrollx<<8, scrolly<<8, incxx<<8, incxy<<8, incyx<<8, incyy<<8, wrap, transmask);
	954	supracan_suprnova_draw_roz(bitmap, clip, m_tilemap_sizes[layer][which_tilemap_size], scrollx<<8, scrolly<<8, incxx<<8, incxy<<8, incyx<<8, incyy<<8, wrap, transmask);
953	955	}
954	956	}
955	957	else
956	958	{
957		supracan_suprnova_draw_roz(machine(), bitmap, cliprect, m_tilemap_sizes[layer][which_tilemap_size], scrollx<<8, scrolly<<8, incxx<<8, incxy<<8, incyx<<8, incyy<<8, wrap, transmask);
	959	supracan_suprnova_draw_roz(bitmap, cliprect, m_tilemap_sizes[layer][which_tilemap_size], scrollx<<8, scrolly<<8, incxx<<8, incxy<<8, incyx<<8, incyy<<8, wrap, transmask);
958	960	}
959	961	}
960	962	}
r21160	r21161
993	995	{
994	996	case 0x00/2: // Source address MSW
995	997	case 0x10/2:
996		verboselog("maincpu", machine(), 0, "supracan_dma_w: source msw %d: %04x\n", ch, data);
	998	verboselog("maincpu", 0, "supracan_dma_w: source msw %d: %04x\n", ch, data);
997	999	acan_dma_regs->source[ch] &= 0x0000ffff;
998	1000	acan_dma_regs->source[ch] |= data << 16;
999	1001	break;
1000	1002	case 0x02/2: // Source address LSW
1001	1003	case 0x12/2:
1002		verboselog("maincpu", machine(), 0, "supracan_dma_w: source lsw %d: %04x\n", ch, data);
	1004	verboselog("maincpu", 0, "supracan_dma_w: source lsw %d: %04x\n", ch, data);
1003	1005	acan_dma_regs->source[ch] &= 0xffff0000;
1004	1006	acan_dma_regs->source[ch] |= data;
1005	1007	break;
1006	1008	case 0x04/2: // Destination address MSW
1007	1009	case 0x14/2:
1008		verboselog("maincpu", machine(), 0, "supracan_dma_w: dest msw %d: %04x\n", ch, data);
	1010	verboselog("maincpu", 0, "supracan_dma_w: dest msw %d: %04x\n", ch, data);
1009	1011	acan_dma_regs->dest[ch] &= 0x0000ffff;
1010	1012	acan_dma_regs->dest[ch] |= data << 16;
1011	1013	break;
1012	1014	case 0x06/2: // Destination address LSW
1013	1015	case 0x16/2:
1014		verboselog("maincpu", machine(), 0, "supracan_dma_w: dest lsw %d: %04x\n", ch, data);
	1016	verboselog("maincpu", 0, "supracan_dma_w: dest lsw %d: %04x\n", ch, data);
1015	1017	acan_dma_regs->dest[ch] &= 0xffff0000;
1016	1018	acan_dma_regs->dest[ch] |= data;
1017	1019	break;
1018	1020	case 0x08/2: // Byte count
1019	1021	case 0x18/2:
1020		verboselog("maincpu", machine(), 0, "supracan_dma_w: count %d: %04x\n", ch, data);
	1022	verboselog("maincpu", 0, "supracan_dma_w: count %d: %04x\n", ch, data);
1021	1023	acan_dma_regs->count[ch] = data;
1022	1024	break;
1023	1025	case 0x0a/2: // Control
1024	1026	case 0x1a/2:
1025		verboselog("maincpu", machine(), 0, "supracan_dma_w: control %d: %04x\n", ch, data);
	1027	verboselog("maincpu", 0, "supracan_dma_w: control %d: %04x\n", ch, data);
1026	1028	if(data & 0x8800)
1027	1029	{
1028	1030	//            if(data & 0x2000)
r21160	r21161
1050	1052	}
1051	1053	else if(data != 0x0000) // fake DMA, used by C.U.G.
1052	1054	{
1053		verboselog("maincpu", machine(), 0, "supracan_dma_w: Unknown DMA kickoff value of %04x (other regs %08x, %08x, %d)\n", data, acan_dma_regs->source[ch], acan_dma_regs->dest[ch], acan_dma_regs->count[ch] + 1);
	1055	verboselog("maincpu", 0, "supracan_dma_w: Unknown DMA kickoff value of %04x (other regs %08x, %08x, %d)\n", data, acan_dma_regs->source[ch], acan_dma_regs->dest[ch], acan_dma_regs->count[ch] + 1);
1054	1056	fatalerror("supracan_dma_w: Unknown DMA kickoff value of %04x (other regs %08x, %08x, %d)\n",data, acan_dma_regs->source[ch], acan_dma_regs->dest[ch], acan_dma_regs->count[ch] + 1);
1055	1057	}
1056	1058	break;
1057	1059	default:
1058		verboselog("maincpu", machine(), 0, "supracan_dma_w: Unknown register: %08x = %04x & %04x\n", 0xe90020 + (offset << 1), data, mem_mask);
	1060	verboselog("maincpu", 0, "supracan_dma_w: Unknown register: %08x = %04x & %04x\n", 0xe90020 + (offset << 1), data, mem_mask);
1059	1061	break;
1060	1062	}
1061	1063	}
r21160	r21161
1134	1136
1135	1137	case 0x410: // Sound IRQ enable
1136	1138	data = m_sound_irq_enable_reg;
1137		if(!mem.debugger_access()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", machine(), 0, "supracan_soundreg_r: IRQ enable: %04x\n", data);
	1139	if(!mem.debugger_access()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 0, "supracan_soundreg_r: IRQ enable: %04x\n", data);
1138	1140	if(!mem.debugger_access())
1139	1141	{
1140	1142	if(m_sound_irq_enable_reg & m_sound_irq_source_reg)
r21160	r21161
1150	1152	case 0x411: // Sound IRQ source
1151	1153	data = m_sound_irq_source_reg;
1152	1154	m_sound_irq_source_reg = 0;
1153		if(!mem.debugger_access()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", machine(), 3, "supracan_soundreg_r: IRQ source: %04x\n", data);
	1155	if(!mem.debugger_access()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 3, "supracan_soundreg_r: IRQ source: %04x\n", data);
1154	1156	if(!mem.debugger_access())
1155	1157	{
1156	1158	machine().device("soundcpu")->execute().set_input_line(0, CLEAR_LINE);
1157	1159	}
1158	1160	break;
1159	1161	case 0x420:
1160		if(!mem.debugger_access()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", machine(), 3, "supracan_soundreg_r: Sound hardware status? (not yet implemented): %02x\n", 0);
	1162	if(!mem.debugger_access()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 3, "supracan_soundreg_r: Sound hardware status? (not yet implemented): %02x\n", 0);
1161	1163	break;
1162	1164	case 0x422:
1163		if(!mem.debugger_access()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", machine(), 3, "supracan_soundreg_r: Sound hardware data? (not yet implemented): %02x\n", 0);
	1165	if(!mem.debugger_access()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 3, "supracan_soundreg_r: Sound hardware data? (not yet implemented): %02x\n", 0);
1164	1166	break;
1165	1167	case 0x404:
1166	1168	case 0x405:
r21160	r21161
1171	1173	default:
1172	1174	if(offset >= 0x300 && offset < 0x500)
1173	1175	{
1174		if(!mem.debugger_access()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", machine(), 0, "supracan_soundreg_r: Unknown register %04x\n", offset);
	1176	if(!mem.debugger_access()) verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 0, "supracan_soundreg_r: Unknown register %04x\n", offset);
1175	1177	}
1176	1178	break;
1177	1179	}
r21160	r21161
1186	1188	case 0x407:
1187	1189	if(m_sound_cpu_68k_irq_reg &~ data)
1188	1190	{
1189		verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", machine(), 0, "supracan_soundreg_w: sound_cpu_68k_irq_reg: %04x: Triggering M68k IRQ\n", data);
	1191	verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 0, "supracan_soundreg_w: sound_cpu_68k_irq_reg: %04x: Triggering M68k IRQ\n", data);
1190	1192	m_maincpu->set_input_line(7, HOLD_LINE);
1191	1193	}
1192	1194	else
1193	1195	{
1194		verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", machine(), 0, "supracan_soundreg_w: sound_cpu_68k_irq_reg: %04x\n", data);
	1196	verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 0, "supracan_soundreg_w: sound_cpu_68k_irq_reg: %04x\n", data);
1195	1197	}
1196	1198	m_sound_cpu_68k_irq_reg = data;
1197	1199	break;
1198	1200	case 0x410:
1199	1201	m_sound_irq_enable_reg = data;
1200		verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", machine(), 0, "supracan_soundreg_w: IRQ enable: %02x\n", data);
	1202	verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 0, "supracan_soundreg_w: IRQ enable: %02x\n", data);
1201	1203	break;
1202	1204	case 0x420:
1203		verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", machine(), 3, "supracan_soundreg_w: Sound hardware reg data? (not yet implemented): %02x\n", data);
	1205	verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 3, "supracan_soundreg_w: Sound hardware reg data? (not yet implemented): %02x\n", data);
1204	1206	break;
1205	1207	case 0x422:
1206		verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", machine(), 3, "supracan_soundreg_w: Sound hardware reg addr? (not yet implemented): %02x\n", data);
	1208	verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 3, "supracan_soundreg_w: Sound hardware reg addr? (not yet implemented): %02x\n", data);
1207	1209	break;
1208	1210	default:
1209	1211	if(offset >= 0x300 && offset < 0x500)
1210	1212	{
1211		verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", machine(), 0, "supracan_soundreg_w: Unknown register %04x = %02x\n", offset, data);
	1213	verboselog(m_hack_68k_to_6502_access ? "maincpu" : "soundcpu", 0, "supracan_soundreg_w: Unknown register %04x = %02x\n", offset, data);
1212	1214	}
1213	1215	m_soundram[offset] = data;
1214	1216	break;
r21160	r21161
1405	1407	switch( offset )
1406	1408	{
1407	1409	default:
1408		verboselog("maincpu", machine(), 0, "supracan_sound_r: Unknown register: (%08x) & %04x\n", 0xe90000 + (offset << 1), mem_mask);
	1410	verboselog("maincpu", 0, "supracan_sound_r: Unknown register: (%08x) & %04x\n", 0xe90000 + (offset << 1), mem_mask);
1409	1411	break;
1410	1412	}
1411	1413
r21160	r21161
1437	1439	/* Halt the sound cpu */
1438	1440	machine().device("soundcpu")->execute().set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
1439	1441	}
1440		verboselog("maincpu", machine(), 0, "sound cpu ctrl: %04x\n", data);
	1442	verboselog("maincpu", 0, "sound cpu ctrl: %04x\n", data);
1441	1443	break;
1442	1444	default:
1443		verboselog("maincpu", machine(), 0, "supracan_sound_w: Unknown register: %08x = %04x & %04x\n", 0xe90000 + (offset << 1), data, mem_mask);
	1445	verboselog("maincpu", 0, "supracan_sound_w: Unknown register: %08x = %04x & %04x\n", 0xe90000 + (offset << 1), data, mem_mask);
1444	1446	break;
1445	1447	}
1446	1448	}
r21160	r21161
1456	1458	case 0x00/2: // Video IRQ flags
1457	1459	if(!mem.debugger_access())
1458	1460	{
1459		//verboselog("maincpu", machine(), 0, "read video IRQ flags (%04x)\n", data);
	1461	//verboselog("maincpu", 0, "read video IRQ flags (%04x)\n", data);
1460	1462	m_maincpu->set_input_line(7, CLEAR_LINE);
1461	1463	}
1462	1464	break;
r21160	r21161
1466	1468	data = 0;
1467	1469	break;
1468	1470	case 0x100/2:
1469		if(!mem.debugger_access()) verboselog("maincpu", machine(), 0, "read tilemap_flags[0] (%04x)\n", data);
	1471	if(!mem.debugger_access()) verboselog("maincpu", 0, "read tilemap_flags[0] (%04x)\n", data);
1470	1472	break;
1471	1473	case 0x106/2:
1472		if(!mem.debugger_access()) verboselog("maincpu", machine(), 0, "read tilemap_scrolly[0] (%04x)\n", data);
	1474	if(!mem.debugger_access()) verboselog("maincpu", 0, "read tilemap_scrolly[0] (%04x)\n", data);
1473	1475	break;
1474	1476	case 0x120/2:
1475		if(!mem.debugger_access()) verboselog("maincpu", machine(), 0, "read tilemap_flags[1] (%04x)\n", data);
	1477	if(!mem.debugger_access()) verboselog("maincpu", 0, "read tilemap_flags[1] (%04x)\n", data);
1476	1478	break;
1477	1479	default:
1478		if(!mem.debugger_access()) verboselog("maincpu", machine(), 0, "supracan_video_r: Unknown register: %08x (%04x & %04x)\n", 0xf00000 + (offset << 1), data, mem_mask);
	1480	if(!mem.debugger_access()) verboselog("maincpu", 0, "supracan_video_r: Unknown register: %08x (%04x & %04x)\n", 0xf00000 + (offset << 1), data, mem_mask);
1479	1481	break;
1480	1482	}
1481	1483
r21160	r21161
1515	1517	m_video_regs[0] &= 0x7fff;
1516	1518
1517	1519	// we really need better management of this
1518		mark_active_tilemap_all_dirty(machine(), 0);
1519		mark_active_tilemap_all_dirty(machine(), 1);
1520		mark_active_tilemap_all_dirty(machine(), 2);
1521		mark_active_tilemap_all_dirty(machine(), 3);
	1520	mark_active_tilemap_all_dirty(0);
	1521	mark_active_tilemap_all_dirty(1);
	1522	mark_active_tilemap_all_dirty(2);
	1523	mark_active_tilemap_all_dirty(3);
1522	1524
1523	1525
1524	1526	break;
r21160	r21161
1530	1532	case 240:
1531	1533	if(m_irq_mask & 1)
1532	1534	{
1533		verboselog("maincpu", machine(), 0, "Triggering VBL IRQ\n\n");
	1535	verboselog("maincpu", 0, "Triggering VBL IRQ\n\n");
1534	1536	m_maincpu->set_input_line(7, HOLD_LINE);
1535	1537	}
1536	1538	break;
r21160	r21161
1554	1556	switch(offset)
1555	1557	{
1556	1558	case 0x10/2: // Byte count
1557		verboselog("maincpu", machine(), 0, "sprite dma word count: %04x\n", data);
	1559	verboselog("maincpu", 0, "sprite dma word count: %04x\n", data);
1558	1560	acan_sprdma_regs->count = data;
1559	1561	break;
1560	1562	case 0x12/2: // Destination address MSW
1561	1563	acan_sprdma_regs->dst &= 0x0000ffff;
1562	1564	acan_sprdma_regs->dst |= data << 16;
1563		verboselog("maincpu", machine(), 0, "sprite dma dest msw: %04x\n", data);
	1565	verboselog("maincpu", 0, "sprite dma dest msw: %04x\n", data);
1564	1566	break;
1565	1567	case 0x14/2: // Destination address LSW
1566	1568	acan_sprdma_regs->dst &= 0xffff0000;
1567	1569	acan_sprdma_regs->dst |= data;
1568		verboselog("maincpu", machine(), 0, "sprite dma dest lsw: %04x\n", data);
	1570	verboselog("maincpu", 0, "sprite dma dest lsw: %04x\n", data);
1569	1571	break;
1570	1572	case 0x16/2: // Source word increment
1571		verboselog("maincpu", machine(), 0, "sprite dma dest word inc: %04x\n", data);
	1573	verboselog("maincpu", 0, "sprite dma dest word inc: %04x\n", data);
1572	1574	acan_sprdma_regs->dst_inc = data;
1573	1575	break;
1574	1576	case 0x18/2: // Source address MSW
1575	1577	acan_sprdma_regs->src &= 0x0000ffff;
1576	1578	acan_sprdma_regs->src |= data << 16;
1577		verboselog("maincpu", machine(), 0, "sprite dma src msw: %04x\n", data);
	1579	verboselog("maincpu", 0, "sprite dma src msw: %04x\n", data);
1578	1580	break;
1579	1581	case 0x1a/2: // Source address LSW
1580		verboselog("maincpu", machine(), 0, "sprite dma src lsw: %04x\n", data);
	1582	verboselog("maincpu", 0, "sprite dma src lsw: %04x\n", data);
1581	1583	acan_sprdma_regs->src &= 0xffff0000;
1582	1584	acan_sprdma_regs->src |= data;
1583	1585	break;
1584	1586	case 0x1c/2: // Source word increment
1585		verboselog("maincpu", machine(), 0, "sprite dma src word inc: %04x\n", data);
	1587	verboselog("maincpu", 0, "sprite dma src word inc: %04x\n", data);
1586	1588	acan_sprdma_regs->src_inc = data;
1587	1589	break;
1588	1590	case 0x1e/2:
r21160	r21161
1619	1621	}
1620	1622	else
1621	1623	{
1622		verboselog("maincpu", machine(), 0, "supracan_dma_w: Attempting to kick off a DMA without bit 15 set! (%04x)\n", data);
	1624	verboselog("maincpu", 0, "supracan_dma_w: Attempting to kick off a DMA without bit 15 set! (%04x)\n", data);
1623	1625	}
1624	1626	break;
1625	1627	case 0x08/2:
1626	1628	{
1627		verboselog("maincpu", machine(), 3, "video_flags = %04x\n", data);
	1629	verboselog("maincpu", 3, "video_flags = %04x\n", data);
1628	1630	m_video_flags = data;
1629	1631
1630	1632	rectangle visarea = machine().primary_screen->visible_area();
r21160	r21161
1636	1638	case 0x0a/2:
1637	1639	{
1638	1640	// raster interrupt
1639		verboselog("maincpu", machine(), 0, "IRQ Trigger? = %04x\n", data);
	1641	verboselog("maincpu", 0, "IRQ Trigger? = %04x\n", data);
1640	1642	if(data & 0x8000)
1641	1643	{
1642	1644	m_line_on_timer->adjust(machine().primary_screen->time_until_pos((data & 0x00ff), 0));
r21160	r21161
1650	1652
1651	1653	case 0x0c/2:
1652	1654	{
1653		verboselog("maincpu", machine(), 0, "IRQ De-Trigger? = %04x\n", data);
	1655	verboselog("maincpu", 0, "IRQ De-Trigger? = %04x\n", data);
1654	1656	if(data & 0x8000)
1655	1657	{
1656	1658	m_line_off_timer->adjust(machine().primary_screen->time_until_pos(data & 0x00ff, 0));
r21160	r21161
1663	1665	break;
1664	1666
1665	1667	/* Sprites */
1666		case 0x20/2: m_sprite_base_addr = data << 2; verboselog("maincpu", machine(), 0, "sprite_base_addr = %04x\n", data); break;
1667		case 0x22/2: m_sprite_count = data+1; verboselog("maincpu", machine(), 0, "sprite_count = %d\n", data+1); break;
1668		case 0x26/2: m_sprite_flags = data; verboselog("maincpu", machine(), 0, "sprite_flags = %04x\n", data); break;
	1668	case 0x20/2: m_sprite_base_addr = data << 2; verboselog("maincpu", 0, "sprite_base_addr = %04x\n", data); break;
	1669	case 0x22/2: m_sprite_count = data+1; verboselog("maincpu", 0, "sprite_count = %d\n", data+1); break;
	1670	case 0x26/2: m_sprite_flags = data; verboselog("maincpu", 0, "sprite_flags = %04x\n", data); break;
1669	1671
1670	1672	/* Tilemap 0 */
1671		case 0x100/2: m_tilemap_flags[0] = data; verboselog("maincpu", machine(), 3, "tilemap_flags[0] = %04x\n", data); break;
1672		case 0x104/2: m_tilemap_scrollx[0] = data; verboselog("maincpu", machine(), 3, "tilemap_scrollx[0] = %04x\n", data); break;
1673		case 0x106/2: m_tilemap_scrolly[0] = data; verboselog("maincpu", machine(), 3, "tilemap_scrolly[0] = %04x\n", data); break;
1674		case 0x108/2: m_tilemap_base_addr[0] = (data) << 1; verboselog("maincpu", machine(), 3, "tilemap_base_addr[0] = %05x\n", data << 2); break;
1675		case 0x10a/2: m_tilemap_mode[0] = data; verboselog("maincpu", machine(), 3, "tilemap_mode[0] = %04x\n", data); break;
	1673	case 0x100/2: m_tilemap_flags[0] = data; verboselog("maincpu", 3, "tilemap_flags[0] = %04x\n", data); break;
	1674	case 0x104/2: m_tilemap_scrollx[0] = data; verboselog("maincpu", 3, "tilemap_scrollx[0] = %04x\n", data); break;
	1675	case 0x106/2: m_tilemap_scrolly[0] = data; verboselog("maincpu", 3, "tilemap_scrolly[0] = %04x\n", data); break;
	1676	case 0x108/2: m_tilemap_base_addr[0] = (data) << 1; verboselog("maincpu", 3, "tilemap_base_addr[0] = %05x\n", data << 2); break;
	1677	case 0x10a/2: m_tilemap_mode[0] = data; verboselog("maincpu", 3, "tilemap_mode[0] = %04x\n", data); break;
1676	1678
1677	1679	/* Tilemap 1 */
1678		case 0x120/2: m_tilemap_flags[1] = data; verboselog("maincpu", machine(), 3, "tilemap_flags[1] = %04x\n", data); break;
1679		case 0x124/2: m_tilemap_scrollx[1] = data; verboselog("maincpu", machine(), 3, "tilemap_scrollx[1] = %04x\n", data); break;
1680		case 0x126/2: m_tilemap_scrolly[1] = data; verboselog("maincpu", machine(), 3, "tilemap_scrolly[1] = %04x\n", data); break;
1681		case 0x128/2: m_tilemap_base_addr[1] = (data) << 1; verboselog("maincpu", machine(), 3, "tilemap_base_addr[1] = %05x\n", data << 2); break;
1682		case 0x12a/2: m_tilemap_mode[1] = data; verboselog("maincpu", machine(), 3, "tilemap_mode[1] = %04x\n", data); break;
	1680	case 0x120/2: m_tilemap_flags[1] = data; verboselog("maincpu", 3, "tilemap_flags[1] = %04x\n", data); break;
	1681	case 0x124/2: m_tilemap_scrollx[1] = data; verboselog("maincpu", 3, "tilemap_scrollx[1] = %04x\n", data); break;
	1682	case 0x126/2: m_tilemap_scrolly[1] = data; verboselog("maincpu", 3, "tilemap_scrolly[1] = %04x\n", data); break;
	1683	case 0x128/2: m_tilemap_base_addr[1] = (data) << 1; verboselog("maincpu", 3, "tilemap_base_addr[1] = %05x\n", data << 2); break;
	1684	case 0x12a/2: m_tilemap_mode[1] = data; verboselog("maincpu", 3, "tilemap_mode[1] = %04x\n", data); break;
1683	1685
1684	1686	/* Tilemap 2? */
1685		case 0x140/2: m_tilemap_flags[2] = data; verboselog("maincpu", machine(), 0, "tilemap_flags[2] = %04x\n", data); break;
1686		case 0x144/2: m_tilemap_scrollx[2] = data; verboselog("maincpu", machine(), 0, "tilemap_scrollx[2] = %04x\n", data); break;
1687		case 0x146/2: m_tilemap_scrolly[2] = data; verboselog("maincpu", machine(), 0, "tilemap_scrolly[2] = %04x\n", data); break;
1688		case 0x148/2: m_tilemap_base_addr[2] = (data) << 1; verboselog("maincpu", machine(), 0, "tilemap_base_addr[2] = %05x\n", data << 2); break;
1689		case 0x14a/2: m_tilemap_mode[2] = data; verboselog("maincpu", machine(), 0, "tilemap_mode[2] = %04x\n", data); break;
	1687	case 0x140/2: m_tilemap_flags[2] = data; verboselog("maincpu", 0, "tilemap_flags[2] = %04x\n", data); break;
	1688	case 0x144/2: m_tilemap_scrollx[2] = data; verboselog("maincpu", 0, "tilemap_scrollx[2] = %04x\n", data); break;
	1689	case 0x146/2: m_tilemap_scrolly[2] = data; verboselog("maincpu", 0, "tilemap_scrolly[2] = %04x\n", data); break;
	1690	case 0x148/2: m_tilemap_base_addr[2] = (data) << 1; verboselog("maincpu", 0, "tilemap_base_addr[2] = %05x\n", data << 2); break;
	1691	case 0x14a/2: m_tilemap_mode[2] = data; verboselog("maincpu", 0, "tilemap_mode[2] = %04x\n", data); break;
1690	1692
1691	1693	/* ROZ */
1692		case 0x180/2: m_roz_mode = data; verboselog("maincpu", machine(), 3, "roz_mode = %04x\n", data); break;
1693		case 0x184/2: m_roz_scrollx = (data << 16) | (m_roz_scrollx & 0xffff); m_roz_changed |= 1; verboselog("maincpu", machine(), 3, "roz_scrollx = %08x\n", m_roz_scrollx); break;
1694		case 0x186/2: m_roz_scrollx = (data) | (m_roz_scrollx & 0xffff0000); m_roz_changed |= 1; verboselog("maincpu", machine(), 3, "roz_scrollx = %08x\n", m_roz_scrollx); break;
1695		case 0x188/2: m_roz_scrolly = (data << 16) | (m_roz_scrolly & 0xffff); m_roz_changed |= 2; verboselog("maincpu", machine(), 3, "roz_scrolly = %08x\n", m_roz_scrolly); break;
1696		case 0x18a/2: m_roz_scrolly = (data) | (m_roz_scrolly & 0xffff0000); m_roz_changed |= 2; verboselog("maincpu", machine(), 3, "roz_scrolly = %08x\n", m_roz_scrolly); break;
1697		case 0x18c/2: m_roz_coeffa = data; verboselog("maincpu", machine(), 3, "roz_coeffa = %04x\n", data); break;
1698		case 0x18e/2: m_roz_coeffb = data; verboselog("maincpu", machine(), 3, "roz_coeffb = %04x\n", data); break;
1699		case 0x190/2: m_roz_coeffc = data; verboselog("maincpu", machine(), 3, "roz_coeffc = %04x\n", data); break;
1700		case 0x192/2: m_roz_coeffd = data; verboselog("maincpu", machine(), 3, "roz_coeffd = %04x\n", data); break;
1701		case 0x194/2: m_roz_base_addr = (data) << 1; verboselog("maincpu", machine(), 3, "roz_base_addr = %05x\n", data << 2); break;
1702		case 0x196/2: m_roz_tile_bank = data; verboselog("maincpu", machine(), 3, "roz_tile_bank = %04x\n", data); break; //tile bank
1703		case 0x198/2: m_roz_unk_base0 = data << 2; verboselog("maincpu", machine(), 3, "roz_unk_base0 = %05x\n", data << 2); break;
1704		case 0x19a/2: m_roz_unk_base1 = data << 2; verboselog("maincpu", machine(), 3, "roz_unk_base1 = %05x\n", data << 2); break;
1705		case 0x19e/2: m_roz_unk_base2 = data << 2; verboselog("maincpu", machine(), 3, "roz_unk_base2 = %05x\n", data << 2); break;
	1694	case 0x180/2: m_roz_mode = data; verboselog("maincpu", 3, "roz_mode = %04x\n", data); break;
	1695	case 0x184/2: m_roz_scrollx = (data << 16) | (m_roz_scrollx & 0xffff); m_roz_changed |= 1; verboselog("maincpu", 3, "roz_scrollx = %08x\n", m_roz_scrollx); break;
	1696	case 0x186/2: m_roz_scrollx = (data) | (m_roz_scrollx & 0xffff0000); m_roz_changed |= 1; verboselog("maincpu", 3, "roz_scrollx = %08x\n", m_roz_scrollx); break;
	1697	case 0x188/2: m_roz_scrolly = (data << 16) | (m_roz_scrolly & 0xffff); m_roz_changed |= 2; verboselog("maincpu", 3, "roz_scrolly = %08x\n", m_roz_scrolly); break;
	1698	case 0x18a/2: m_roz_scrolly = (data) | (m_roz_scrolly & 0xffff0000); m_roz_changed |= 2; verboselog("maincpu", 3, "roz_scrolly = %08x\n", m_roz_scrolly); break;
	1699	case 0x18c/2: m_roz_coeffa = data; verboselog("maincpu", 3, "roz_coeffa = %04x\n", data); break;
	1700	case 0x18e/2: m_roz_coeffb = data; verboselog("maincpu", 3, "roz_coeffb = %04x\n", data); break;
	1701	case 0x190/2: m_roz_coeffc = data; verboselog("maincpu", 3, "roz_coeffc = %04x\n", data); break;
	1702	case 0x192/2: m_roz_coeffd = data; verboselog("maincpu", 3, "roz_coeffd = %04x\n", data); break;
	1703	case 0x194/2: m_roz_base_addr = (data) << 1; verboselog("maincpu", 3, "roz_base_addr = %05x\n", data << 2); break;
	1704	case 0x196/2: m_roz_tile_bank = data; verboselog("maincpu", 3, "roz_tile_bank = %04x\n", data); break; //tile bank
	1705	case 0x198/2: m_roz_unk_base0 = data << 2; verboselog("maincpu", 3, "roz_unk_base0 = %05x\n", data << 2); break;
	1706	case 0x19a/2: m_roz_unk_base1 = data << 2; verboselog("maincpu", 3, "roz_unk_base1 = %05x\n", data << 2); break;
	1707	case 0x19e/2: m_roz_unk_base2 = data << 2; verboselog("maincpu", 3, "roz_unk_base2 = %05x\n", data << 2); break;
1706	1708
1707		case 0x1d0/2: m_unk_1d0 = data; verboselog("maincpu", machine(), 3, "unk_1d0 = %04x\n", data); break;
	1709	case 0x1d0/2: m_unk_1d0 = data; verboselog("maincpu", 3, "unk_1d0 = %04x\n", data); break;
1708	1710
1709	1711
1710	1712
r21160	r21161
1717	1719	m_maincpu->set_input_line(7, CLEAR_LINE);
1718	1720	}
1719	1721	#endif
1720		verboselog("maincpu", machine(), 3, "irq_mask = %04x\n", data);
	1722	verboselog("maincpu", 3, "irq_mask = %04x\n", data);
1721	1723	break;
1722	1724	default:
1723		verboselog("maincpu", machine(), 0, "supracan_video_w: Unknown register: %08x = %04x & %04x\n", 0xf00000 + (offset << 1), data, mem_mask);
	1725	verboselog("maincpu", 0, "supracan_video_w: Unknown register: %08x = %04x & %04x\n", 0xf00000 + (offset << 1), data, mem_mask);
1724	1726	break;
1725	1727	}
1726	1728	m_video_regs[offset] = data;

trunk/src/mess/drivers/hp49gp.c

r21160	r21161
11	11
12	12	#define VERBOSE_LEVEL ( 0 )
13	13
14		INLINE void ATTR_PRINTF(3,4) verboselog( running_machine &machine, int n_level, const char *s_fmt, ...)
15		{
16		if (VERBOSE_LEVEL >= n_level)
17		{
18		va_list v;
19		char buf[32768];
20		va_start( v, s_fmt);
21		vsprintf( buf, s_fmt, v);
22		va_end( v);
23		logerror( "%s: %s", machine.describe_context( ), buf);
24		}
25		}
26
27	14	struct lcd_spi_t
28	15	{
29	16	int l1;
r21160	r21161
47	34	virtual void machine_start();
48	35	virtual void machine_reset();
49	36	DECLARE_INPUT_CHANGED_MEMBER(port_changed);
	37	inline void ATTR_PRINTF(3,4) verboselog( int n_level, const char *s_fmt, ...);
	38	void lcd_spi_reset( );
	39	void lcd_spi_init( );
	40	void lcd_spi_line_w( int line, int data);
	41	int lcd_spi_line_r( int line);
50	42	};
51	43
52	44	/***************************************************************************
r21160	r21161
62	54	LCD_SPI_LINE_3
63	55	};
64	56
65		static void lcd_spi_reset( running_machine &machine)
	57	inline void ATTR_PRINTF(3,4) hp49gp_state::verboselog( int n_level, const char *s_fmt, ...)
66	58	{
67		hp49gp_state *hp49gp = machine.driver_data<hp49gp_state>();
68		verboselog( machine, 5, "lcd_spi_reset\n");
69		hp49gp->m_lcd_spi.l1 = 0;
70		hp49gp->m_lcd_spi.data = 0;
71		hp49gp->m_lcd_spi.l3 = 0;
	59	if (VERBOSE_LEVEL >= n_level)
	60	{
	61	va_list v;
	62	char buf[32768];
	63	va_start( v, s_fmt);
	64	vsprintf( buf, s_fmt, v);
	65	va_end( v);
	66	logerror( "%s: %s", machine().describe_context( ), buf);
	67	}
72	68	}
73	69
74		static void lcd_spi_init( running_machine &machine)
	70	void hp49gp_state::lcd_spi_reset( )
75	71	{
76		verboselog( machine, 5, "lcd_spi_init\n");
77		lcd_spi_reset( machine);
	72	verboselog( 5, "lcd_spi_reset\n");
	73	m_lcd_spi.l1 = 0;
	74	m_lcd_spi.data = 0;
	75	m_lcd_spi.l3 = 0;
78	76	}
79	77
80		static void lcd_spi_line_w( running_machine &machine, int line, int data)
	78	void hp49gp_state::lcd_spi_init( )
81	79	{
82		hp49gp_state *hp49gp = machine.driver_data<hp49gp_state>();
	80	verboselog( 5, "lcd_spi_init\n");
	81	lcd_spi_reset();
	82	}
	83
	84	void hp49gp_state::lcd_spi_line_w( int line, int data)
	85	{
83	86	switch (line)
84	87	{
85	88	case LCD_SPI_LINE_1 :
86	89	{
87		if (data != hp49gp->m_lcd_spi.l1)
	90	if (data != m_lcd_spi.l1)
88	91	{
89	92	if (data == 0)
90	93	{
91		hp49gp->m_lcd_spi.shift = 0;
92		hp49gp->m_lcd_spi.bits = 0;
	94	m_lcd_spi.shift = 0;
	95	m_lcd_spi.bits = 0;
93	96	}
94		verboselog( machine, 5, "LCD_SPI_LINE_1 <- %d\n", data);
95		hp49gp->m_lcd_spi.l1 = data;
	97	verboselog( 5, "LCD_SPI_LINE_1 <- %d\n", data);
	98	m_lcd_spi.l1 = data;
96	99	}
97	100	}
98	101	break;
99	102	case LCD_SPI_LINE_DATA :
100	103	{
101		if (data != hp49gp->m_lcd_spi.data)
	104	if (data != m_lcd_spi.data)
102	105	{
103		verboselog( machine, 5, "LCD_SPI_LINE_DATA <- %d\n", data);
104		hp49gp->m_lcd_spi.data = data;
	106	verboselog( 5, "LCD_SPI_LINE_DATA <- %d\n", data);
	107	m_lcd_spi.data = data;
105	108	}
106	109	}
107	110	break;
108	111	case LCD_SPI_LINE_3 :
109	112	{
110		if (data != hp49gp->m_lcd_spi.l3)
	113	if (data != m_lcd_spi.l3)
111	114	{
112		if ((data != 0) && (hp49gp->m_lcd_spi.l1 == 0))
	115	if ((data != 0) && (m_lcd_spi.l1 == 0))
113	116	{
114		verboselog( machine, 5, "LCD SPI write bit %d\n", hp49gp->m_lcd_spi.data ? 1 : 0);
115		if (hp49gp->m_lcd_spi.bits < 8)
	117	verboselog( 5, "LCD SPI write bit %d\n", m_lcd_spi.data ? 1 : 0);
	118	if (m_lcd_spi.bits < 8)
116	119	{
117		hp49gp->m_lcd_spi.shift = (hp49gp->m_lcd_spi.shift << 1) | (hp49gp->m_lcd_spi.data ? 1 : 0);
	120	m_lcd_spi.shift = (m_lcd_spi.shift << 1) | (m_lcd_spi.data ? 1 : 0);
118	121	}
119		hp49gp->m_lcd_spi.bits++;
120		if (hp49gp->m_lcd_spi.bits == 8)
	122	m_lcd_spi.bits++;
	123	if (m_lcd_spi.bits == 8)
121	124	{
122		verboselog( machine, 5, "LCD SPI write byte %02X\n", hp49gp->m_lcd_spi.shift);
	125	verboselog( 5, "LCD SPI write byte %02X\n", m_lcd_spi.shift);
123	126	}
124		else if (hp49gp->m_lcd_spi.bits == 9)
	127	else if (m_lcd_spi.bits == 9)
125	128	{
126		verboselog( machine, 5, "LCD SPI write ack %d\n", (hp49gp->m_lcd_spi.data ? 1 : 0));
	129	verboselog( 5, "LCD SPI write ack %d\n", (m_lcd_spi.data ? 1 : 0));
127	130	}
128	131	}
129		verboselog( machine, 5, "LCD_SPI_LINE_3 <- %d\n", data);
130		hp49gp->m_lcd_spi.l3 = data;
	132	verboselog( 5, "LCD_SPI_LINE_3 <- %d\n", data);
	133	m_lcd_spi.l3 = data;
131	134	}
132	135	}
133	136	break;
134	137	}
135	138	}
136	139
137		static int lcd_spi_line_r( running_machine &machine, int line)
	140	int hp49gp_state::lcd_spi_line_r( int line)
138	141	{
139		hp49gp_state *hp49gp = machine.driver_data<hp49gp_state>();
140	142	switch (line)
141	143	{
142	144	case LCD_SPI_LINE_1 :
143	145	{
144		verboselog( machine, 7, "LCD_SPI_LINE_1 -> %d\n", hp49gp->m_lcd_spi.l1);
145		return hp49gp->m_lcd_spi.l1;
	146	verboselog( 7, "LCD_SPI_LINE_1 -> %d\n", m_lcd_spi.l1);
	147	return m_lcd_spi.l1;
146	148	}
147	149	break;
148	150	case LCD_SPI_LINE_DATA :
149	151	{
150		verboselog( machine, 7, "LCD_SPI_LINE_DATA -> %d\n", hp49gp->m_lcd_spi.data);
151		return hp49gp->m_lcd_spi.data;
	152	verboselog( 7, "LCD_SPI_LINE_DATA -> %d\n", m_lcd_spi.data);
	153	return m_lcd_spi.data;
152	154	}
153	155	break;
154	156	case LCD_SPI_LINE_3 :
155	157	{
156		verboselog( machine, 7, "LCD_SPI_LINE_3 -> %d\n", hp49gp->m_lcd_spi.l3);
157		return hp49gp->m_lcd_spi.l3;
	158	verboselog( 7, "LCD_SPI_LINE_3 -> %d\n", m_lcd_spi.l3);
	159	return m_lcd_spi.l3;
158	160	}
159	161	break;
160	162	}
r21160	r21161
178	180	{
179	181	data = data | 0x0008;
180	182	data = data & ~0x3200;
181		data |= (lcd_spi_line_r( device->machine(), LCD_SPI_LINE_1) ? 1 : 0) << 9;
182		data |= (lcd_spi_line_r( device->machine(), LCD_SPI_LINE_DATA) ? 1 : 0) << 12;
183		data |= (lcd_spi_line_r( device->machine(), LCD_SPI_LINE_3) ? 1 : 0) << 13;
	183	data |= (hp49gp->lcd_spi_line_r( LCD_SPI_LINE_1) ? 1 : 0) << 9;
	184	data |= (hp49gp->lcd_spi_line_r( LCD_SPI_LINE_DATA) ? 1 : 0) << 12;
	185	data |= (hp49gp->lcd_spi_line_r( LCD_SPI_LINE_3) ? 1 : 0) << 13;
184	186	}
185	187	break;
186	188	case S3C2410_GPIO_PORT_E :
r21160	r21161
222	224	{
223	225	case S3C2410_GPIO_PORT_D :
224	226	{
225		lcd_spi_line_w( device->machine(), LCD_SPI_LINE_1, BIT( data, 9) ? 1 : 0);
226		lcd_spi_line_w( device->machine(), LCD_SPI_LINE_DATA, BIT( data, 12) ? 1 : 0);
227		lcd_spi_line_w( device->machine(), LCD_SPI_LINE_3, BIT( data, 13) ? 1 : 0);
	227	hp49gp->lcd_spi_line_w( LCD_SPI_LINE_1, BIT( data, 9) ? 1 : 0);
	228	hp49gp->lcd_spi_line_w( LCD_SPI_LINE_DATA, BIT( data, 12) ? 1 : 0);
	229	hp49gp->lcd_spi_line_w( LCD_SPI_LINE_3, BIT( data, 13) ? 1 : 0);
228	230	}
229	231	break;
230	232	}
r21160	r21161
269	271	{
270	272	UINT8 *rom = (UINT8 *)machine().root_device().memregion( "maincpu")->base();
271	273	memcpy( m_steppingstone, rom, 1024);
272		lcd_spi_init( machine());
	274	lcd_spi_init();
273	275	}
274	276
275	277	static S3C2410_INTERFACE( hp49gp_s3c2410_intf )

trunk/src/mess/drivers/ip22.c

r21160	r21161
143	143	required_device<device_t> m_lpt0;
144	144	required_device<pit8254_device> m_pit;
145	145	required_device<dac_device> m_dac;
	146	inline void ATTR_PRINTF(3,4) verboselog(int n_level, const char *s_fmt, ... );
	147	void int3_raise_local0_irq(UINT8 source_mask);
	148	void int3_lower_local0_irq(UINT8 source_mask);
	149	void int3_raise_local1_irq(UINT8 source_mask);
	150	void int3_lower_local1_irq(UINT8 source_mask);
	151	void dump_chain(address_space &space, UINT32 ch_base);
	152	void rtc_update();
146	153	};
147	154
148	155
149	156	#define VERBOSE_LEVEL ( 0 )
150	157
151	158
152		INLINE void ATTR_PRINTF(3,4) verboselog(running_machine &machine, int n_level, const char *s_fmt, ... )
	159	inline void ATTR_PRINTF(3,4) ip22_state::verboselog(int n_level, const char *s_fmt, ... )
153	160	{
154	161	if( VERBOSE_LEVEL >= n_level )
155	162	{
r21160	r21161
158	165	va_start( v, s_fmt );
159	166	vsprintf( buf, s_fmt, v );
160	167	va_end( v );
161		logerror("%08x: %s", machine.device("maincpu")->safe_pc(), buf);
	168	logerror("%08x: %s", machine().device("maincpu")->safe_pc(), buf);
162	169	}
163	170	}
164	171
r21160	r21161
209	216	#define INT3_LOCAL1_RETRACE (0x80)
210	217
211	218	// raise a local0 interrupt
212		static void int3_raise_local0_irq(running_machine &machine, UINT8 source_mask)
	219	void ip22_state::int3_raise_local0_irq(UINT8 source_mask)
213	220	{
214		ip22_state *state = machine.driver_data<ip22_state>();
215	221	// signal the interrupt is pending
216		state->m_int3_regs[0] |= source_mask;
	222	m_int3_regs[0] |= source_mask;
217	223
218	224	// if it's not masked, also assert it now at the CPU
219		if (state->m_int3_regs[1] & source_mask)
220		state->m_maincpu->set_input_line(MIPS3_IRQ0, ASSERT_LINE);
	225	if (m_int3_regs[1] & source_mask)
	226	m_maincpu->set_input_line(MIPS3_IRQ0, ASSERT_LINE);
221	227	}
222	228
223	229	// lower a local0 interrupt
224		static void int3_lower_local0_irq(ip22_state *state, UINT8 source_mask)
	230	void ip22_state::int3_lower_local0_irq(UINT8 source_mask)
225	231	{
226		state->m_int3_regs[0] &= ~source_mask;
	232	m_int3_regs[0] &= ~source_mask;
227	233	}
228	234
229	235	#ifdef UNUSED_FUNCTION
230	236	// raise a local1 interrupt
231		static void int3_raise_local1_irq(running_machine &machine, UINT8 source_mask)
	237	void ip22_state::int3_raise_local1_irq(UINT8 source_mask)
232	238	{
233		ip22_state *state = machine.driver_data<ip22_state>();
234	239	// signal the interrupt is pending
235		state->m_int3_regs[2] |= source_mask;
	240	m_int3_regs[2] |= source_mask;
236	241
237	242	// if it's not masked, also assert it now at the CPU
238		if (state->m_int3_regs[2] & source_mask)
239		state->m_maincpu->set_input_line(MIPS3_IRQ1, ASSERT_LINE);
	243	if (m_int3_regs[2] & source_mask)
	244	m_maincpu->set_input_line(MIPS3_IRQ1, ASSERT_LINE);
240	245	}
241	246
242	247	// lower a local1 interrupt
243		static void int3_lower_local1_irq(UINT8 source_mask)
	248	void ip22_state::int3_lower_local1_irq(UINT8 source_mask)
244	249	{
245		ip22_state *state = machine.driver_data<ip22_state>();
246		state->m_int3_regs[2] &= ~source_mask;
	250	m_int3_regs[2] &= ~source_mask;
247	251	}
248	252	#endif
249	253
r21160	r21161
254	258	{
255	259	case 0x004/4:
256	260	ret8 = pc_lpt_control_r(m_lpt0, space, 0) ^ 0x0d;
257		//verboselog(( machine, 0, "Parallel Control Read: %02x\n", ret8 );
	261	//verboselog(0, "Parallel Control Read: %02x\n", ret8 );
258	262	return ret8;
259	263	case 0x008/4:
260	264	ret8 = pc_lpt_status_r(m_lpt0, space, 0) ^ 0x80;
261		//verboselog(( machine, 0, "Parallel Status Read: %02x\n", ret8 );
	265	//verboselog(0, "Parallel Status Read: %02x\n", ret8 );
262	266	return ret8;
263	267	case 0x030/4:
264		//verboselog(( machine, 2, "Serial 1 Command Transfer Read, 0x1fbd9830: %02x\n", 0x04 );
	268	//verboselog(2, "Serial 1 Command Transfer Read, 0x1fbd9830: %02x\n", 0x04 );
265	269	switch(space.device().safe_pc())
266	270	{
267	271	case 0x9fc1d9e4:    // interpreter (ip244415)
r21160	r21161
274	278	}
275	279	return 0x00000004;
276	280	case 0x038/4:
277		//verboselog(( machine, 2, "Serial 2 Command Transfer Read, 0x1fbd9838: %02x\n", 0x04 );
	281	//verboselog(2, "Serial 2 Command Transfer Read, 0x1fbd9838: %02x\n", 0x04 );
278	282	return 0x00000004;
279	283	case 0x40/4:
280	284	return kbdc8042_8_r(space, 0);
r21160	r21161
298	302	return m_int3_regs[offset-0x80/4];
299	303	case 0xb0/4:
300	304	ret8 = pit8253_r(m_pit, space, 0);
301		//verboselog(( machine, 0, "HPC PBUS6 IOC4 Timer Counter 0 Register Read: 0x%02x (%08x)\n", ret8, mem_mask );
	305	//verboselog(0, "HPC PBUS6 IOC4 Timer Counter 0 Register Read: 0x%02x (%08x)\n", ret8, mem_mask );
302	306	return ret8;
303	307	case 0xb4/4:
304	308	ret8 = pit8253_r(m_pit, space, 1);
305		//verboselog(( machine, 0, "HPC PBUS6 IOC4 Timer Counter 1 Register Read: 0x%02x (%08x)\n", ret8, mem_mask );
	309	//verboselog(0, "HPC PBUS6 IOC4 Timer Counter 1 Register Read: 0x%02x (%08x)\n", ret8, mem_mask );
306	310	return ret8;
307	311	case 0xb8/4:
308	312	ret8 = pit8253_r(m_pit, space, 2);
309		//verboselog(( machine, 0, "HPC PBUS6 IOC4 Timer Counter 2 Register Read: 0x%02x (%08x)\n", ret8, mem_mask );
	313	//verboselog(0, "HPC PBUS6 IOC4 Timer Counter 2 Register Read: 0x%02x (%08x)\n", ret8, mem_mask );
310	314	return ret8;
311	315	case 0xbc/4:
312	316	ret8 = pit8253_r(m_pit, space, 3);
313		//verboselog(( machine, 0, "HPC PBUS6 IOC4 Timer Control Word Register Read: 0x%02x (%08x)\n", ret8, mem_mask );
	317	//verboselog(0, "HPC PBUS6 IOC4 Timer Control Word Register Read: 0x%02x (%08x)\n", ret8, mem_mask );
314	318	return ret8;
315	319	default:
316		//verboselog(( machine, 0, "Unknown HPC PBUS6 Read: 0x%08x (%08x)\n", 0x1fbd9800 + ( offset << 2 ), mem_mask );
	320	//verboselog(0, "Unknown HPC PBUS6 Read: 0x%08x (%08x)\n", 0x1fbd9800 + ( offset << 2 ), mem_mask );
317	321	return 0;
318	322	}
319	323	return 0;
r21160	r21161
326	330	switch( offset )
327	331	{
328	332	case 0x004/4:
329		//verboselog(( machine, 0, "Parallel Control Write: %08x\n", data );
	333	//verboselog(0, "Parallel Control Write: %08x\n", data );
330	334	pc_lpt_control_w(m_lpt0, space, 0, data ^ 0x0d);
331	335	//m_nIOC_ParCntl = data;
332	336	break;
333	337	case 0x030/4:
334	338	if( ( data & 0x000000ff ) >= 0x20 )
335	339	{
336		//verboselog(( machine, 2, "Serial 1 Command Transfer Write: %02x: %c\n", data & 0x000000ff, data & 0x000000ff );
	340	//verboselog(2, "Serial 1 Command Transfer Write: %02x: %c\n", data & 0x000000ff, data & 0x000000ff );
337	341	}
338	342	else
339	343	{
340		//verboselog(( machine, 2, "Serial 1 Command Transfer Write: %02x\n", data & 0x000000ff );
	344	//verboselog(2, "Serial 1 Command Transfer Write: %02x\n", data & 0x000000ff );
341	345	}
342	346	cChar = data & 0x000000ff;
343	347	if( cChar >= 0x20 || cChar == 0x0d || cChar == 0x0a )
r21160	r21161
348	352	case 0x034/4:
349	353	if( ( data & 0x000000ff ) >= 0x20 )
350	354	{
351		//verboselog(( machine, 2, "Serial 1 Data Transfer Write: %02x: %c\n", data & 0x000000ff, data & 0x000000ff );
	355	//verboselog(2, "Serial 1 Data Transfer Write: %02x: %c\n", data & 0x000000ff, data & 0x000000ff );
352	356	}
353	357	else
354	358	{
355		//verboselog(( machine, 2, "Serial 1 Data Transfer Write: %02x\n", data & 0x000000ff );
	359	//verboselog(2, "Serial 1 Data Transfer Write: %02x\n", data & 0x000000ff );
356	360	}
357	361	cChar = data & 0x000000ff;
358	362	if( cChar >= 0x20 || cChar == 0x0d || cChar == 0x0a )
r21160	r21161
393	397
394	398	break;
395	399	case 0xb0/4:
396		//verboselog(( machine, 0, "HPC PBUS6 IOC4 Timer Counter 0 Register Write: 0x%08x (%08x)\n", data, mem_mask );
	400	//verboselog(0, "HPC PBUS6 IOC4 Timer Counter 0 Register Write: 0x%08x (%08x)\n", data, mem_mask );
397	401	pit8253_w(m_pit, space, 0, data & 0x000000ff);
398	402	return;
399	403	case 0xb4/4:
400		//verboselog(( machine, 0, "HPC PBUS6 IOC4 Timer Counter 1 Register Write: 0x%08x (%08x)\n", data, mem_mask );
	404	//verboselog(0, "HPC PBUS6 IOC4 Timer Counter 1 Register Write: 0x%08x (%08x)\n", data, mem_mask );
401	405	pit8253_w(m_pit, space, 1, data & 0x000000ff);
402	406	return;
403	407	case 0xb8/4:
404		//verboselog(( machine, 0, "HPC PBUS6 IOC4 Timer Counter 2 Register Write: 0x%08x (%08x)\n", data, mem_mask );
	408	//verboselog(0, "HPC PBUS6 IOC4 Timer Counter 2 Register Write: 0x%08x (%08x)\n", data, mem_mask );
405	409	pit8253_w(m_pit, space, 2, data & 0x000000ff);
406	410	return;
407	411	case 0xbc/4:
408		//verboselog(( machine, 0, "HPC PBUS6 IOC4 Timer Control Word Register Write: 0x%08x (%08x)\n", data, mem_mask );
	412	//verboselog(0, "HPC PBUS6 IOC4 Timer Control Word Register Write: 0x%08x (%08x)\n", data, mem_mask );
409	413	pit8253_w(m_pit, space, 3, data & 0x000000ff);
410	414	return;
411	415	default:
412		//verboselog(( machine, 0, "Unknown HPC PBUS6 Write: 0x%08x: 0x%08x (%08x)\n", 0x1fbd9800 + ( offset << 2 ), data, mem_mask );
	416	//verboselog(0, "Unknown HPC PBUS6 Write: 0x%08x: 0x%08x (%08x)\n", 0x1fbd9800 + ( offset << 2 ), data, mem_mask );
413	417	break;
414	418	}
415	419	}
r21160	r21161
565	569	}
566	570	}
567	571
568		#define RTC_SECONDS state->m_RTC.nRegs[0x00]
569		#define RTC_SECONDS_A   state->m_RTC.nRegs[0x01]
570		#define RTC_MINUTES state->m_RTC.nRegs[0x02]
571		#define RTC_MINUTES_A   state->m_RTC.nRegs[0x03]
572		#define RTC_HOURS   state->m_RTC.nRegs[0x04]
573		#define RTC_HOURS_A state->m_RTC.nRegs[0x05]
574		#define RTC_DAYOFWEEK   state->m_RTC.nRegs[0x06]
575		#define RTC_DAYOFMONTH  state->m_RTC.nRegs[0x07]
576		#define RTC_MONTH   state->m_RTC.nRegs[0x08]
577		#define RTC_YEAR    state->m_RTC.nRegs[0x09]
578		#define RTC_REGISTERA   state->m_RTC.nRegs[0x0a]
579		#define RTC_REGISTERB   state->m_RTC.nRegs[0x0b]
580		#define RTC_REGISTERC   state->m_RTC.nRegs[0x0c]
581		#define RTC_REGISTERD   state->m_RTC.nRegs[0x0d]
582		#define RTC_MODELBYTE   state->m_RTC.nRegs[0x40]
583		#define RTC_SERBYTE0    state->m_RTC.nRegs[0x41]
584		#define RTC_SERBYTE1    state->m_RTC.nRegs[0x42]
585		#define RTC_SERBYTE2    state->m_RTC.nRegs[0x43]
586		#define RTC_SERBYTE3    state->m_RTC.nRegs[0x44]
587		#define RTC_SERBYTE4    state->m_RTC.nRegs[0x45]
588		#define RTC_SERBYTE5    state->m_RTC.nRegs[0x46]
589		#define RTC_CRC     state->m_RTC.nRegs[0x47]
590		#define RTC_CENTURY state->m_RTC.nRegs[0x48]
591		#define RTC_DAYOFMONTH_A state->m_RTC.nRegs[0x49]
592		#define RTC_EXTCTRL0    state->m_RTC.nRegs[0x4a]
593		#define RTC_EXTCTRL1    state->m_RTC.nRegs[0x4b]
594		#define RTC_RTCADDR2    state->m_RTC.nRegs[0x4e]
595		#define RTC_RTCADDR3    state->m_RTC.nRegs[0x4f]
596		#define RTC_RAMLSB  state->m_RTC.nRegs[0x50]
597		#define RTC_RAMMSB  state->m_RTC.nRegs[0x51]
598		#define RTC_WRITECNT    state->m_RTC.nRegs[0x5e]
	572	#define RTC_SECONDS m_RTC.nRegs[0x00]
	573	#define RTC_SECONDS_A   m_RTC.nRegs[0x01]
	574	#define RTC_MINUTES m_RTC.nRegs[0x02]
	575	#define RTC_MINUTES_A   m_RTC.nRegs[0x03]
	576	#define RTC_HOURS   m_RTC.nRegs[0x04]
	577	#define RTC_HOURS_A m_RTC.nRegs[0x05]
	578	#define RTC_DAYOFWEEK   m_RTC.nRegs[0x06]
	579	#define RTC_DAYOFMONTH  m_RTC.nRegs[0x07]
	580	#define RTC_MONTH   m_RTC.nRegs[0x08]
	581	#define RTC_YEAR    m_RTC.nRegs[0x09]
	582	#define RTC_REGISTERA   m_RTC.nRegs[0x0a]
	583	#define RTC_REGISTERB   m_RTC.nRegs[0x0b]
	584	#define RTC_REGISTERC   m_RTC.nRegs[0x0c]
	585	#define RTC_REGISTERD   m_RTC.nRegs[0x0d]
	586	#define RTC_MODELBYTE   m_RTC.nRegs[0x40]
	587	#define RTC_SERBYTE0    m_RTC.nRegs[0x41]
	588	#define RTC_SERBYTE1    m_RTC.nRegs[0x42]
	589	#define RTC_SERBYTE2    m_RTC.nRegs[0x43]
	590	#define RTC_SERBYTE3    m_RTC.nRegs[0x44]
	591	#define RTC_SERBYTE4    m_RTC.nRegs[0x45]
	592	#define RTC_SERBYTE5    m_RTC.nRegs[0x46]
	593	#define RTC_CRC     m_RTC.nRegs[0x47]
	594	#define RTC_CENTURY m_RTC.nRegs[0x48]
	595	#define RTC_DAYOFMONTH_A m_RTC.nRegs[0x49]
	596	#define RTC_EXTCTRL0    m_RTC.nRegs[0x4a]
	597	#define RTC_EXTCTRL1    m_RTC.nRegs[0x4b]
	598	#define RTC_RTCADDR2    m_RTC.nRegs[0x4e]
	599	#define RTC_RTCADDR3    m_RTC.nRegs[0x4f]
	600	#define RTC_RAMLSB  m_RTC.nRegs[0x50]
	601	#define RTC_RAMMSB  m_RTC.nRegs[0x51]
	602	#define RTC_WRITECNT    m_RTC.nRegs[0x5e]
599	603
600	604	READ32_MEMBER(ip22_state::rtc_r)
601	605	{
602		ip22_state *state = machine().driver_data<ip22_state>();
603
604	606	if( offset <= 0x0d )
605	607	{
606	608	switch( offset )
r21160	r21161
729	731
730	732	WRITE32_MEMBER(ip22_state::rtc_w)
731	733	{
732		ip22_state *state = machine().driver_data<ip22_state>();
733	734	RTC_WRITECNT++;
734	735
735	736	//  mame_printf_info("RTC_W: offset %x => %x (PC=%x)\n", data, offset, activecpu_get_pc());
r21160	r21161
1196	1197
1197	1198	void ip22_state::machine_reset()
1198	1199	{
1199		ip22_state *state = machine().driver_data<ip22_state>();
1200	1200	m_HPC3.nenetr_nbdp = 0x80000000;
1201	1201	m_HPC3.nenetr_cbp = 0x80000000;
1202	1202	m_nIntCounter = 0;
r21160	r21161
1210	1210
1211	1211	m_PBUS_DMA.nActive = 0;
1212	1212
1213		mips3drc_set_options(state->m_maincpu, MIPS3DRC_COMPATIBLE_OPTIONS | MIPS3DRC_CHECK_OVERFLOWS);
	1213	mips3drc_set_options(m_maincpu, MIPS3DRC_COMPATIBLE_OPTIONS | MIPS3DRC_CHECK_OVERFLOWS);
1214	1214	}
1215	1215
1216		static void dump_chain(address_space &space, UINT32 ch_base)
	1216	void ip22_state::dump_chain(address_space &space, UINT32 ch_base)
1217	1217	{
1218	1218	printf("node: %08x %08x %08x (len = %x)\n", space.read_dword(ch_base), space.read_dword(ch_base+4), space.read_dword(ch_base+8), space.read_dword(ch_base+4) & 0x3fff);
1219	1219
r21160	r21161
1260	1260
1261	1261	printf("DMA to device: %d words @ %x\n", words, wptr);
1262	1262
1263		dump_chain(space, drvstate->m_HPC3.nSCSI0Descriptor);
	1263	drvstate->dump_chain(space, drvstate->m_HPC3.nSCSI0Descriptor);
1264	1264
1265	1265	if (words <= (512/4))
1266	1266	{
r21160	r21161
1401	1401
1402	1402	//              mame_printf_info("DMA from device: %d words @ %x\n", words, wptr);
1403	1403
1404		dump_chain(space, drvstate->m_HPC3.nSCSI0Descriptor);
	1404	drvstate->dump_chain(space, drvstate->m_HPC3.nSCSI0Descriptor);
1405	1405
1406	1406	if (words <= (1024/4))
1407	1407	{
r21160	r21161
1463	1463	drvstate->m_HPC3.nSCSI0DMACtrl &= ~HPC3_DMACTRL_ENABLE;
1464	1464
1465	1465	// set the interrupt
1466		int3_raise_local0_irq(machine, INT3_LOCAL0_SCSI0);
	1466	drvstate->int3_raise_local0_irq(INT3_LOCAL0_SCSI0);
1467	1467	}
1468	1468	else
1469	1469	{
1470		int3_lower_local0_irq(drvstate, INT3_LOCAL0_SCSI0);
	1470	drvstate->int3_lower_local0_irq(INT3_LOCAL0_SCSI0);
1471	1471	}
1472	1472	}
1473	1473
r21160	r21161
1514	1514	PORT_INCLUDE( at_keyboard )     /* IN4 - IN11 */
1515	1515	INPUT_PORTS_END
1516	1516
1517		static void rtc_update(ip22_state *state)
	1517	void ip22_state::rtc_update()
1518	1518	{
1519	1519	RTC_SECONDS++;
1520	1520
r21160	r21161
1584	1584	//  if( m_nIntCounter == 60 )
1585	1585	{
1586	1586	m_nIntCounter = 0;
1587		rtc_update(this);
	1587	rtc_update();
1588	1588	}
1589	1589	}
1590	1590

trunk/src/mess/drivers/atari400.c

r21160	r21161
341	341	void a1200xl_mmu(UINT8 new_mmu);
342	342	void xegs_mmu(UINT8 new_mmu);
343	343	void a800_setup_mappers(int type);
	344	int a800_get_pcb_id(const char *pcb);
	345	int a800_get_type(device_image_interface &image);
	346	int a800_check_cart_type(device_image_interface &image);
344	347	};
345	348
346	349	/**************************************************************
r21160	r21161
1180	1183	{"N/A", A800_UNKNOWN}
1181	1184	};
1182	1185
1183		static int a800_get_pcb_id(const char *pcb)
	1186	int a400_state::a800_get_pcb_id(const char *pcb)
1184	1187	{
1185	1188	int i;
1186	1189
r21160	r21161
1374	1377	}
1375	1378
1376	1379
1377		static int a800_get_type(device_image_interface &image)
	1380	int a400_state::a800_get_type(device_image_interface &image)
1378	1381	{
1379	1382	UINT8 header[16];
1380	1383	image.fread(header, 0x10);
r21160	r21161
1439	1442	}
1440	1443
1441	1444
1442		static int a800_check_cart_type(device_image_interface &image)
	1445	int a400_state::a800_check_cart_type(device_image_interface &image)
1443	1446	{
1444	1447	const char  *pcb_name;
1445	1448	int type = A800_UNKNOWN;

trunk/src/mess/drivers/palmz22.c

r21160	r21161
71	71
72	72	#define VERBOSE_LEVEL ( 0 )
73	73
74		INLINE void ATTR_PRINTF(3,4) verboselog( running_machine &machine, int n_level, const char *s_fmt, ...)
75		{
76		if (VERBOSE_LEVEL >= n_level)
77		{
78		va_list v;
79		char buf[32768];
80		va_start( v, s_fmt);
81		vsprintf( buf, s_fmt, v);
82		va_end( v);
83		logerror( "%s: %s", machine.describe_context(), buf);
84		}
85		}
86
87	74	class palmz22_state : public driver_device
88	75	{
89	76	public:
r21160	r21161
102	89	virtual void machine_start();
103	90	virtual void machine_reset();
104	91	DECLARE_INPUT_CHANGED_MEMBER(palmz22_input_changed);
	92	inline void ATTR_PRINTF(3,4) verboselog( int n_level, const char *s_fmt, ...);
105	93	};
106	94
	95
	96	inline void ATTR_PRINTF(3,4) palmz22_state::verboselog( int n_level, const char *s_fmt, ...)
	97	{
	98	if (VERBOSE_LEVEL >= n_level)
	99	{
	100	va_list v;
	101	char buf[32768];
	102	va_start( v, s_fmt);
	103	vsprintf( buf, s_fmt, v);
	104	va_end( v);
	105	logerror( "%s: %s", machine().describe_context(), buf);
	106	}
	107	}
	108
107	109	/***************************************************************************
108	110	MACHINE HARDWARE
109	111	***************************************************************************/
r21160	r21161
113	115	static WRITE8_DEVICE_HANDLER( s3c2410_nand_command_w )
114	116	{
115	117	palmz22_state *state = space.machine().driver_data<palmz22_state>();
116		verboselog( space.machine(), 9, "s3c2410_nand_command_w %02X\n", data);
	118	state->verboselog(9, "s3c2410_nand_command_w %02X\n", data);
117	119	state->m_nand->command_w(data);
118	120	}
119	121
120	122	static WRITE8_DEVICE_HANDLER( s3c2410_nand_address_w )
121	123	{
122	124	palmz22_state *state = space.machine().driver_data<palmz22_state>();
123		verboselog( space.machine(), 9, "s3c2410_nand_address_w %02X\n", data);
	125	state->verboselog(9, "s3c2410_nand_address_w %02X\n", data);
124	126	state->m_nand->address_w(data);
125	127	}
126	128
r21160	r21161
128	130	{
129	131	palmz22_state *state = space.machine().driver_data<palmz22_state>();
130	132	UINT8 data = state->m_nand->data_r();
131		verboselog( space.machine(), 9, "s3c2410_nand_data_r %02X\n", data);
	133	state->verboselog(9, "s3c2410_nand_data_r %02X\n", data);
132	134	return data;
133	135	}
134	136
135	137	static WRITE8_DEVICE_HANDLER( s3c2410_nand_data_w )
136	138	{
137	139	palmz22_state *state = space.machine().driver_data<palmz22_state>();
138		verboselog( space.machine(), 9, "s3c2410_nand_data_w %02X\n", data);
	140	state->verboselog(9, "s3c2410_nand_data_w %02X\n", data);
139	141	state->m_nand->data_w(data);
140	142	}
141	143
r21160	r21161
143	145	{
144	146	palmz22_state *state = device->machine().driver_data<palmz22_state>();
145	147	UINT8 data = state->m_nand->is_busy();
146		verboselog( device->machine(), 9, "s3c2410_nand_busy_r %02X\n", data);
	148	state->verboselog(9, "s3c2410_nand_busy_r %02X\n", data);
147	149	return data;
148	150	}
149	151
r21160	r21161
212	214
213	215	static READ32_DEVICE_HANDLER( s3c2410_adc_data_r )
214	216	{
	217	palmz22_state *state = device->machine().driver_data<palmz22_state>();
215	218	UINT32 data = 0;
216	219	switch (offset)
217	220	{
r21160	r21161
220	223	case 2 + 0 : data = space.machine().root_device().ioport( "PENX")->read(); break;
221	224	case 2 + 1 : data = 0x3FF - space.machine().root_device().ioport( "PENY")->read(); break;
222	225	}
223		verboselog( space.machine(), 5,  "s3c2410_adc_data_r %08X\n", data);
	226	state->verboselog(5,  "s3c2410_adc_data_r %08X\n", data);
224	227	return data;
225	228	}
226	229

trunk/src/mess/drivers/a2600.c

r21160	r21161
153	153	void install_banks(int count, unsigned init);
154	154
155	155	UINT8   *m_cart;
	156	int detect_modeDC();
	157	int detect_modef6();
	158	int detect_mode3E();
	159	int detect_modeSS();
	160	int detect_modeFE();
	161	int detect_modeE0();
	162	int detect_modeCV();
	163	int detect_modeFV();
	164	int detect_modeJVP();
	165	int detect_modeE7();
	166	int detect_modeUA();
	167	int detect_8K_mode3F();
	168	int detect_32K_mode3F();
	169	int detect_super_chip();
	170	unsigned long detect_2600controllers();
156	171	};
157	172
158	173
159	174
160		#define CART machine.root_device().memregion("user1")->base()
161		#define CART_MEMBER machine().root_device().memregion("user1")->base()
	175	#define CART machine().root_device().memregion("user1")->base()
162	176
163	177	#define MASTER_CLOCK_NTSC   3579545
164	178	#define MASTER_CLOCK_PAL    3546894
r21160	r21161
191	205
192	206	static const UINT16 supported_screen_heights[4] = { 262, 312, 328, 342 };
193	207
194		static int detect_modeDC(running_machine &machine)
	208	int a2600_state::detect_modeDC()
195	209	{
196		a2600_state *state = machine.driver_data<a2600_state>();
197	210	int i,numfound = 0;
198	211	// signature is also in 'video reflex'.. maybe figure out that controller port someday...
199	212	static const unsigned char signature[3] = { 0x8d, 0xf0, 0xff };
200		if (state->m_cart_size == 0x10000)
	213	if (m_cart_size == 0x10000)
201	214	{
202	215	UINT8 *cart = CART;
203		for (i = 0; i < state->m_cart_size - sizeof signature; i++)
	216	for (i = 0; i < m_cart_size - sizeof signature; i++)
204	217	{
205	218	if (!memcmp(&cart[i], signature,sizeof signature))
206	219	{
r21160	r21161
212	225	return 0;
213	226	}
214	227
215		static int detect_modef6(running_machine &machine)
	228	int a2600_state::detect_modef6()
216	229	{
217		a2600_state *state = machine.driver_data<a2600_state>();
218	230	int i, numfound = 0;
219	231	static const unsigned char signature[3] = { 0x8d, 0xf6, 0xff };
220		if (state->m_cart_size == 0x4000)
	232	if (m_cart_size == 0x4000)
221	233	{
222	234	UINT8 *cart = CART;
223		for (i = 0; i < state->m_cart_size - sizeof signature; i++)
	235	for (i = 0; i < m_cart_size - sizeof signature; i++)
224	236	{
225	237	if (!memcmp(&cart[i], signature, sizeof signature))
226	238	{
r21160	r21161
232	244	return 0;
233	245	}
234	246
235		static int detect_mode3E(running_machine &machine)
	247	int a2600_state::detect_mode3E()
236	248	{
237		a2600_state *state = machine.driver_data<a2600_state>();
238	249	// this one is a little hacky.. looks for STY $3e, which is unique to
239	250	// 'not boulderdash', but is the only example i have (cow)
240	251	// Would have used STA $3e, but 'Alien' and 'Star Raiders' do that for unknown reasons
241	252
242	253	int i,numfound = 0;
243	254	static const unsigned char signature[3] = { 0x84, 0x3e, 0x9d };
244		if (state->m_cart_size == 0x0800 || state->m_cart_size == 0x1000)
	255	if (m_cart_size == 0x0800 || m_cart_size == 0x1000)
245	256	{
246	257	UINT8 *cart = CART;
247		for (i = 0; i < state->m_cart_size - sizeof signature; i++)
	258	for (i = 0; i < m_cart_size - sizeof signature; i++)
248	259	{
249	260	if (!memcmp(&cart[i], signature,sizeof signature))
250	261	{
r21160	r21161
256	267	return 0;
257	268	}
258	269
259		static int detect_modeSS(running_machine &machine)
	270	int a2600_state::detect_modeSS()
260	271	{
261		a2600_state *state = machine.driver_data<a2600_state>();
262	272	int i,numfound = 0;
263	273	static const unsigned char signature[5] = { 0xbd, 0xe5, 0xff, 0x95, 0x81 };
264		if (state->m_cart_size == 0x0800 || state->m_cart_size == 0x1000)
	274	if (m_cart_size == 0x0800 || m_cart_size == 0x1000)
265	275	{
266	276	UINT8 *cart = CART;
267		for (i = 0; i < state->m_cart_size - sizeof signature; i++)
	277	for (i = 0; i < m_cart_size - sizeof signature; i++)
268	278	{
269	279	if (!memcmp(&cart[i], signature,sizeof signature))
270	280	{
r21160	r21161
276	286	return 0;
277	287	}
278	288
279		static int detect_modeFE(running_machine &machine)
	289	int a2600_state::detect_modeFE()
280	290	{
281		a2600_state *state = machine.driver_data<a2600_state>();
282	291	int i,j,numfound = 0;
283	292	static const unsigned char signatures[][5] =  {
284	293	{ 0x20, 0x00, 0xd0, 0xc6, 0xc5 },
r21160	r21161
286	295	{ 0xd0, 0xfb, 0x20, 0x73, 0xfe },
287	296	{ 0x20, 0x00, 0xf0, 0x84, 0xd6 }
288	297	};
289		if (state->m_cart_size == 0x2000)
	298	if (m_cart_size == 0x2000)
290	299	{
291	300	UINT8 *cart = CART;
292		for (i = 0; i < state->m_cart_size - (sizeof signatures/sizeof signatures[0]); i++)
	301	for (i = 0; i < m_cart_size - (sizeof signatures/sizeof signatures[0]); i++)
293	302	{
294	303	for (j = 0; j < (sizeof signatures/sizeof signatures[0]) && !numfound; j++)
295	304	{
r21160	r21161
304	313	return 0;
305	314	}
306	315
307		static int detect_modeE0(running_machine &machine)
	316	int a2600_state::detect_modeE0()
308	317	{
309		a2600_state *state = machine.driver_data<a2600_state>();
310	318	int i,j,numfound = 0;
311	319	static const unsigned char signatures[][3] =  {
312	320	{ 0x8d, 0xe0, 0x1f },
r21160	r21161
316	324	{ 0xad, 0xed, 0xff },
317	325	{ 0xad, 0xf3, 0xbf }
318	326	};
319		if (state->m_cart_size == 0x2000)
	327	if (m_cart_size == 0x2000)
320	328	{
321	329	UINT8 *cart = CART;
322		for (i = 0; i < state->m_cart_size - (sizeof signatures/sizeof signatures[0]); i++)
	330	for (i = 0; i < m_cart_size - (sizeof signatures/sizeof signatures[0]); i++)
323	331	{
324	332	for (j = 0; j < (sizeof signatures/sizeof signatures[0]) && !numfound; j++)
325	333	{
r21160	r21161
334	342	return 0;
335	343	}
336	344
337		static int detect_modeCV(running_machine &machine)
	345	int a2600_state::detect_modeCV()
338	346	{
339		a2600_state *state = machine.driver_data<a2600_state>();
340	347	int i,j,numfound = 0;
341	348	static const unsigned char signatures[][3] = {
342	349	{ 0x9d, 0xff, 0xf3 },
343	350	{ 0x99, 0x00, 0xf4 }
344	351	};
345		if (state->m_cart_size == 0x0800 || state->m_cart_size == 0x1000)
	352	if (m_cart_size == 0x0800 || m_cart_size == 0x1000)
346	353	{
347	354	UINT8 *cart = CART;
348		for (i = 0; i < state->m_cart_size - (sizeof signatures/sizeof signatures[0]); i++)
	355	for (i = 0; i < m_cart_size - (sizeof signatures/sizeof signatures[0]); i++)
349	356	{
350	357	for (j = 0; j < (sizeof signatures/sizeof signatures[0]) && !numfound; j++)
351	358	{
r21160	r21161
360	367	return 0;
361	368	}
362	369
363		static int detect_modeFV(running_machine &machine)
	370	int a2600_state::detect_modeFV()
364	371	{
365		a2600_state *state = machine.driver_data<a2600_state>();
366	372	int i,j,numfound = 0;
367	373	static const unsigned char signatures[][3] = {
368	374	{ 0x2c, 0xd0, 0xff }
369	375	};
370		if (state->m_cart_size == 0x2000)
	376	if (m_cart_size == 0x2000)
371	377	{
372	378	UINT8 *cart = CART;
373		for (i = 0; i < state->m_cart_size - (sizeof signatures/sizeof signatures[0]); i++)
	379	for (i = 0; i < m_cart_size - (sizeof signatures/sizeof signatures[0]); i++)
374	380	{
375	381	for (j = 0; j < (sizeof signatures/sizeof signatures[0]) && !numfound; j++)
376	382	{
r21160	r21161
380	386	}
381	387	}
382	388	}
383		state->m_FVlocked = 0;
	389	m_FVlocked = 0;
384	390	}
385	391	if (numfound) return 1;
386	392	return 0;
387	393	}
388	394
389		static int detect_modeJVP(running_machine &machine)
	395	int a2600_state::detect_modeJVP()
390	396	{
391		a2600_state *state = machine.driver_data<a2600_state>();
392	397	int i,j,numfound = 0;
393	398	static const unsigned char signatures[][4] = {
394	399	{ 0x2c, 0xc0, 0xef, 0x60 },
395	400	{ 0x8d, 0xa0, 0x0f, 0xf0 }
396	401	};
397		if (state->m_cart_size == 0x4000 || state->m_cart_size == 0x2000)
	402	if (m_cart_size == 0x4000 || m_cart_size == 0x2000)
398	403	{
399	404	UINT8 *cart = CART;
400		for (i = 0; i < state->m_cart_size - (sizeof signatures/sizeof signatures[0]); i++)
	405	for (i = 0; i < m_cart_size - (sizeof signatures/sizeof signatures[0]); i++)
401	406	{
402	407	for (j = 0; j < (sizeof signatures/sizeof signatures[0]) && !numfound; j++)
403	408	{
r21160	r21161
412	417	return 0;
413	418	}
414	419
415		static int detect_modeE7(running_machine &machine)
	420	int a2600_state::detect_modeE7()
416	421	{
417		a2600_state *state = machine.driver_data<a2600_state>();
418	422	int i,j,numfound = 0;
419	423	static const unsigned char signatures[][3] = {
420	424	{ 0xad, 0xe5, 0xff },
421	425	{ 0x8d, 0xe7, 0xff }
422	426	};
423		if (state->m_cart_size == 0x2000 || state->m_cart_size == 0x4000)
	427	if (m_cart_size == 0x2000 || m_cart_size == 0x4000)
424	428	{
425	429	UINT8 *cart = CART;
426		for (i = 0; i < state->m_cart_size - (sizeof signatures/sizeof signatures[0]); i++)
	430	for (i = 0; i < m_cart_size - (sizeof signatures/sizeof signatures[0]); i++)
427	431	{
428	432	for (j = 0; j < (sizeof signatures/sizeof signatures[0]) && !numfound; j++)
429	433	{
r21160	r21161
438	442	return 0;
439	443	}
440	444
441		static int detect_modeUA(running_machine &machine)
	445	int a2600_state::detect_modeUA()
442	446	{
443		a2600_state *state = machine.driver_data<a2600_state>();
444	447	int i,numfound = 0;
445	448	static const unsigned char signature[3] = { 0x8d, 0x40, 0x02 };
446		if (state->m_cart_size == 0x2000)
	449	if (m_cart_size == 0x2000)
447	450	{
448	451	UINT8 *cart = CART;
449		for (i = 0; i < state->m_cart_size - sizeof signature; i++)
	452	for (i = 0; i < m_cart_size - sizeof signature; i++)
450	453	{
451	454	if (!memcmp(&cart[i], signature,sizeof signature))
452	455	{
r21160	r21161
458	461	return 0;
459	462	}
460	463
461		static int detect_8K_mode3F(running_machine &machine)
	464	int a2600_state::detect_8K_mode3F()
462	465	{
463		a2600_state *state = machine.driver_data<a2600_state>();
464	466	int i,numfound = 0;
465	467	static const unsigned char signature1[4] = { 0xa9, 0x01, 0x85, 0x3f };
466	468	static const unsigned char signature2[4] = { 0xa9, 0x02, 0x85, 0x3f };
467	469	// have to look for two signatures because 'not boulderdash' gives false positive otherwise
468		if (state->m_cart_size == 0x2000)
	470	if (m_cart_size == 0x2000)
469	471	{
470	472	UINT8 *cart = CART;
471		for (i = 0; i < state->m_cart_size - sizeof signature1; i++)
	473	for (i = 0; i < m_cart_size - sizeof signature1; i++)
472	474	{
473	475	if (!memcmp(&cart[i], signature1,sizeof signature1))
474	476	{
r21160	r21161
484	486	return 0;
485	487	}
486	488
487		static int detect_32K_mode3F(running_machine &machine)
	489	int a2600_state::detect_32K_mode3F()
488	490	{
489		a2600_state *state = machine.driver_data<a2600_state>();
490	491	int i,numfound = 0;
491	492	static const unsigned char signature[4] = { 0xa9, 0x0e, 0x85, 0x3f };
492		if (state->m_cart_size >= 0x8000)
	493	if (m_cart_size >= 0x8000)
493	494	{
494	495	UINT8 *cart = CART;
495		for (i = 0; i < state->m_cart_size - sizeof signature; i++)
	496	for (i = 0; i < m_cart_size - sizeof signature; i++)
496	497	{
497	498	if (!memcmp(&cart[i], signature,sizeof signature))
498	499	{
r21160	r21161
504	505	return 0;
505	506	}
506	507
507		static int detect_super_chip(running_machine &machine)
	508	int a2600_state::detect_super_chip()
508	509	{
509		a2600_state *state = machine.driver_data<a2600_state>();
510	510	int i,j;
511	511	UINT8 *cart = CART;
512	512	static const unsigned char signatures[][5] = {
r21160	r21161
514	514	{ 0xae, 0xf6, 0xff, 0x4c, 0x00 } // off the wall
515	515	};
516	516
517		if (state->m_cart_size == 0x4000)
	517	if (m_cart_size == 0x4000)
518	518	{
519		for (i = 0; i < state->m_cart_size - (sizeof signatures/sizeof signatures[0]); i++)
	519	for (i = 0; i < m_cart_size - (sizeof signatures/sizeof signatures[0]); i++)
520	520	{
521	521	for (j = 0; j < (sizeof signatures/sizeof signatures[0]); j++)
522	522	{
r21160	r21161
527	527	}
528	528	}
529	529	}
530		for (i = 0x1000; i < state->m_cart_size; i += 0x1000)
	530	for (i = 0x1000; i < m_cart_size; i += 0x1000)
531	531	{
532	532	if (memcmp(cart, cart + i, 0x100))
533	533	{
r21160	r21161
619	619	}
620	620	}
621	621
622		if (!(m_cart_size == 0x4000 && detect_modef6(machine())))
	622	if (!(m_cart_size == 0x4000 && detect_modef6()))
623	623	{
624	624	while (m_cart_size > 0x00800)
625	625	{
r21160	r21161
1458	1458	memset( m_riot_ram, 0x00, 0x80 );
1459	1459	m_current_reset_bank_counter = 0xFF;
1460	1460	m_dpc.oscillator = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(a2600_state::modeDPC_timer_callback),this));
1461		m_cart = CART_MEMBER;
	1461	m_cart = CART;
1462	1462	m_modeSS_last_address = 0;
1463	1463	}
1464	1464
1465	1465
1466	1466	#ifdef UNUSED_FUNCTIONS
1467	1467	// try to detect 2600 controller setup. returns 32bits with left/right controller info
1468		static unsigned long detect_2600controllers(running_machine &machine)
	1468	unsigned a2600_state::long detect_2600controllers()
1469	1469	{
1470		a2600_state *state = machine.driver_data<a2600_state>();
1471	1470	#define JOYS 0x001
1472	1471	#define PADD 0x002
1473	1472	#define KEYP 0x004
r21160	r21161
1513	1512	// it can be fixed here with a new signature (note that the Coleco Gemini has this setup also)
1514	1513	left = JOYS+PADD; right = JOYS+PADD;
1515	1514	// default for bad dumps and roms too large to have special controllers
1516		if ((state->m_cart_size > 0x4000) || (state->m_cart_size & 0x7ff)) return (left << 16) + right;
	1515	if ((m_cart_size > 0x4000) || (m_cart_size & 0x7ff)) return (left << 16) + right;
1517	1516
1518	1517	cart = CART;
1519		for (i = 0; i < state->m_cart_size - (sizeof signatures/sizeof signatures[0]); i++)
	1518	for (i = 0; i < m_cart_size - (sizeof signatures/sizeof signatures[0]); i++)
1520	1519	{
1521	1520	for (j = 0; j < (sizeof signatures/sizeof signatures[0]); j++)
1522	1521	{
r21160	r21161
1553	1552	m_current_reset_bank_counter++;
1554	1553
1555	1554	/* auto-detect bank mode */
1556		if (m_banking_mode == 0xff) if (detect_modeDC(machine())) m_banking_mode = modeDC;
1557		if (m_banking_mode == 0xff) if (detect_mode3E(machine())) m_banking_mode = mode3E;
1558		if (m_banking_mode == 0xff) if (detect_modeFE(machine())) m_banking_mode = modeFE;
1559		if (m_banking_mode == 0xff) if (detect_modeSS(machine())) m_banking_mode = modeSS;
1560		if (m_banking_mode == 0xff) if (detect_modeE0(machine())) m_banking_mode = modeE0;
1561		if (m_banking_mode == 0xff) if (detect_modeCV(machine())) m_banking_mode = modeCV;
1562		if (m_banking_mode == 0xff) if (detect_modeFV(machine())) m_banking_mode = modeFV;
1563		if (m_banking_mode == 0xff) if (detect_modeJVP(machine())) m_banking_mode = modeJVP;
1564		if (m_banking_mode == 0xff) if (detect_modeUA(machine())) m_banking_mode = modeUA;
1565		if (m_banking_mode == 0xff) if (detect_8K_mode3F(machine())) m_banking_mode = mode3F;
1566		if (m_banking_mode == 0xff) if (detect_32K_mode3F(machine())) m_banking_mode = mode3F;
1567		if (m_banking_mode == 0xff) if (detect_modeE7(machine())) m_banking_mode = modeE7;
	1555	if (m_banking_mode == 0xff) if (detect_modeDC()) m_banking_mode = modeDC;
	1556	if (m_banking_mode == 0xff) if (detect_mode3E()) m_banking_mode = mode3E;
	1557	if (m_banking_mode == 0xff) if (detect_modeFE()) m_banking_mode = modeFE;
	1558	if (m_banking_mode == 0xff) if (detect_modeSS()) m_banking_mode = modeSS;
	1559	if (m_banking_mode == 0xff) if (detect_modeE0()) m_banking_mode = modeE0;
	1560	if (m_banking_mode == 0xff) if (detect_modeCV()) m_banking_mode = modeCV;
	1561	if (m_banking_mode == 0xff) if (detect_modeFV()) m_banking_mode = modeFV;
	1562	if (m_banking_mode == 0xff) if (detect_modeJVP()) m_banking_mode = modeJVP;
	1563	if (m_banking_mode == 0xff) if (detect_modeUA()) m_banking_mode = modeUA;
	1564	if (m_banking_mode == 0xff) if (detect_8K_mode3F()) m_banking_mode = mode3F;
	1565	if (m_banking_mode == 0xff) if (detect_32K_mode3F()) m_banking_mode = mode3F;
	1566	if (m_banking_mode == 0xff) if (detect_modeE7()) m_banking_mode = modeE7;
1568	1567
1569	1568	if (m_banking_mode == 0xff)
1570	1569	{
r21160	r21161
1607	1606
1608	1607	if (m_cart_size == 0x2000 || m_cart_size == 0x4000 || m_cart_size == 0x8000)
1609	1608	{
1610		chip = detect_super_chip(machine());
	1609	chip = detect_super_chip();
1611	1610	}
1612	1611
1613	1612	/* Super chip games:
r21160	r21161
1648	1647
1649	1648	case modeF8:
1650	1649	m_current_reset_bank_counter = 0;
1651		if (!memcmp(&CART_MEMBER[0x1ffc],snowwhite,sizeof(snowwhite)))
	1650	if (!memcmp(&CART[0x1ffc],snowwhite,sizeof(snowwhite)))
1652	1651	{
1653	1652	install_banks(1, 0x0000);
1654	1653	}
r21160	r21161
1809	1808	case modeSS:
1810	1809	space.install_read_handler(0x1000, 0x1fff, read8_delegate(FUNC(a2600_state::modeSS_r),this));
1811	1810	m_bank_base[1] = m_extra_RAM->base() + 2 * 0x800;
1812		m_bank_base[2] = CART_MEMBER;
	1811	m_bank_base[2] = CART;
1813	1812	membank("bank1")->set_base(m_bank_base[1] );
1814	1813	membank("bank2")->set_base(m_bank_base[2] );
1815	1814	m_modeSS_write_enabled = 0;
r21160	r21161
1842	1841	break;
1843	1842
1844	1843	case mode32in1:
1845		membank("bank1")->set_base(CART_MEMBER + m_current_reset_bank_counter * 0x800 );
1846		membank("bank2")->set_base(CART_MEMBER + m_current_reset_bank_counter * 0x800 );
	1844	membank("bank1")->set_base(CART + m_current_reset_bank_counter * 0x800 );
	1845	membank("bank2")->set_base(CART + m_current_reset_bank_counter * 0x800 );
1847	1846	break;
1848	1847
1849	1848	case modeJVP:

trunk/src/mess/drivers/sgi_ip2.c

r21160	r21161
110	110	UINT8 m_mbp;
111	111	virtual void machine_start();
112	112	virtual void machine_reset();
	113	inline void ATTR_PRINTF(3,4) verboselog( int n_level, const char *s_fmt, ... );
113	114	};
114	115
115	116
r21160	r21161
118	119	#define ENABLE_VERBOSE_LOG (0)
119	120
120	121	#if ENABLE_VERBOSE_LOG
121		INLINE void ATTR_PRINTF(3,4) verboselog( running_machine &machine, int n_level, const char *s_fmt, ... )
	122	inline void ATTR_PRINTF(3,4) sgi_ip2_state::verboselog( int n_level, const char *s_fmt, ... )
122	123	{
123	124	if( VERBOSE_LEVEL >= n_level )
124	125	{
r21160	r21161
127	128	va_start( v, s_fmt );
128	129	vsprintf( buf, s_fmt, v );
129	130	va_end( v );
130		logerror("%08x: %s", machine.device("maincpu")->safe_pc(), buf);
	131	logerror("%08x: %s", machine().device("maincpu")->safe_pc(), buf);
131	132	}
132	133	}
133	134	#else
r21160	r21161
147	148
148	149	READ8_MEMBER(sgi_ip2_state::sgi_ip2_m_but_r)
149	150	{
150		verboselog(machine(), 0, "sgi_ip2_m_but_r: %02x\n", m_mbut | BOARD_REV1);
	151	verboselog(0, "sgi_ip2_m_but_r: %02x\n", m_mbut | BOARD_REV1);
151	152	return m_mbut | BOARD_REV1;
152	153	}
153	154
154	155	WRITE8_MEMBER(sgi_ip2_state::sgi_ip2_m_but_w)
155	156	{
156		verboselog(machine(), 0, "sgi_ip2_m_but_w: %02x\n", data);
	157	verboselog(0, "sgi_ip2_m_but_w: %02x\n", data);
157	158	m_mbut = data;
158	159	}
159	160
r21160	r21161
165	166
166	167	READ16_MEMBER(sgi_ip2_state::sgi_ip2_m_quad_r)
167	168	{
168		verboselog(machine(), 0, "sgi_ip2_m_quad_r: %04x\n", m_mquad);
	169	verboselog(0, "sgi_ip2_m_quad_r: %04x\n", m_mquad);
169	170	return m_mquad;
170	171	}
171	172
172	173	WRITE16_MEMBER(sgi_ip2_state::sgi_ip2_m_quad_w)
173	174	{
174		verboselog(machine(), 0, "sgi_ip2_m_quad_w = %04x & %04x\n", data, mem_mask);
	175	verboselog(0, "sgi_ip2_m_quad_w = %04x & %04x\n", data, mem_mask);
175	176	COMBINE_DATA(&m_mquad);
176	177	}
177	178
178	179	READ16_MEMBER(sgi_ip2_state::sgi_ip2_swtch_r)
179	180	{
180		verboselog(machine(), 0, "sgi_ip2_swtch_r: %04x\n", ioport("SWTCH")->read());
	181	verboselog(0, "sgi_ip2_swtch_r: %04x\n", ioport("SWTCH")->read());
181	182	return ioport("SWTCH")->read();
182	183	}
183	184
184	185	READ8_MEMBER(sgi_ip2_state::sgi_ip2_clock_ctl_r)
185	186	{
186	187	UINT8 ret = m_rtc->read(space, 1);
187		verboselog(machine(), 1, "sgi_ip2_clock_ctl_r: %02x\n", ret);
	188	verboselog(1, "sgi_ip2_clock_ctl_r: %02x\n", ret);
188	189	return ret;
189	190	}
190	191
191	192	WRITE8_MEMBER(sgi_ip2_state::sgi_ip2_clock_ctl_w)
192	193	{
193		verboselog(machine(), 1, "sgi_ip2_clock_ctl_w: %02x\n", data);
	194	verboselog(1, "sgi_ip2_clock_ctl_w: %02x\n", data);
194	195	m_rtc->write(space, 1, data);
195	196	}
196	197
197	198	READ8_MEMBER(sgi_ip2_state::sgi_ip2_clock_data_r)
198	199	{
199	200	UINT8 ret = m_rtc->read(space, 0);
200		verboselog(machine(), 1, "sgi_ip2_clock_data_r: %02x\n", ret);
	201	verboselog(1, "sgi_ip2_clock_data_r: %02x\n", ret);
201	202	return ret;
202	203	}
203	204
204	205	WRITE8_MEMBER(sgi_ip2_state::sgi_ip2_clock_data_w)
205	206	{
206		verboselog(machine(), 1, "sgi_ip2_clock_data_w: %02x\n", data);
	207	verboselog(1, "sgi_ip2_clock_data_w: %02x\n", data);
207	208	m_rtc->write(space, 0, data);
208	209	}
209	210
r21160	r21161
213	214	switch(offset)
214	215	{
215	216	default:
216		verboselog(machine(), 0, "sgi_ip2_os_base_r: Unknown Register %08x\n", 0x36000000 + offset);
	217	verboselog(0, "sgi_ip2_os_base_r: Unknown Register %08x\n", 0x36000000 + offset);
217	218	break;
218	219	}
219	220	return 0;
r21160	r21161
224	225	switch(offset)
225	226	{
226	227	default:
227		verboselog(machine(), 0, "sgi_ip2_os_base_w: Unknown Register %08x = %02x\n", 0x36000000 + offset, data);
	228	verboselog(0, "sgi_ip2_os_base_w: Unknown Register %08x = %02x\n", 0x36000000 + offset, data);
228	229	break;
229	230	}
230	231	}
r21160	r21161
234	235	switch(offset)
235	236	{
236	237	default:
237		verboselog(machine(), 0, "sgi_ip2_status_r: Unknown Register %08x & %04x\n", 0x38000000 + (offset << 1), mem_mask);
	238	verboselog(0, "sgi_ip2_status_r: Unknown Register %08x & %04x\n", 0x38000000 + (offset << 1), mem_mask);
238	239	break;
239	240	}
240	241	return 0;
r21160	r21161
245	246	switch(offset)
246	247	{
247	248	default:
248		verboselog(machine(), 0, "sgi_ip2_status_w: Unknown Register %08x = %04x & %04x\n", 0x38000000 + (offset << 1), data, mem_mask);
	249	verboselog(0, "sgi_ip2_status_w: Unknown Register %08x = %04x & %04x\n", 0x38000000 + (offset << 1), data, mem_mask);
249	250	break;
250	251	}
251	252	}
r21160	r21161
262	263
263	264	READ8_MEMBER(sgi_ip2_state::sgi_ip2_parctl_r)
264	265	{
265		verboselog(machine(), 0, "sgi_ip2_parctl_r: %02x\n", m_parctl);
	266	verboselog(0, "sgi_ip2_parctl_r: %02x\n", m_parctl);
266	267	return m_parctl;
267	268	}
268	269
269	270	WRITE8_MEMBER(sgi_ip2_state::sgi_ip2_parctl_w)
270	271	{
271		verboselog(machine(), 0, "sgi_ip2_parctl_w: %02x\n", data);
	272	verboselog(0, "sgi_ip2_parctl_w: %02x\n", data);
272	273	m_parctl = data;
273	274	}
274	275
r21160	r21161
284	285
285	286	READ8_MEMBER(sgi_ip2_state::sgi_ip2_mbp_r)
286	287	{
287		verboselog(machine(), 0, "sgi_ip2_mbp_r: %02x\n", m_mbp);
	288	verboselog(0, "sgi_ip2_mbp_r: %02x\n", m_mbp);
288	289	return m_mbp;
289	290	}
290	291
291	292	WRITE8_MEMBER(sgi_ip2_state::sgi_ip2_mbp_w)
292	293	{
293		verboselog(machine(), 0, "sgi_ip2_mbp_w: %02x\n", data);
	294	verboselog(0, "sgi_ip2_mbp_w: %02x\n", data);
294	295	m_mbp = data;
295	296	}
296	297
297	298
298	299	READ32_MEMBER(sgi_ip2_state::sgi_ip2_ptmap_r)
299	300	{
300		verboselog(machine(), 0, "sgi_ip2_ptmap_r: %08x = %08x & %08x\n", 0x3b000000 + (offset << 2), m_ptmap[offset], mem_mask);
	301	verboselog(0, "sgi_ip2_ptmap_r: %08x = %08x & %08x\n", 0x3b000000 + (offset << 2), m_ptmap[offset], mem_mask);
301	302	return m_ptmap[offset];
302	303	}
303	304
304	305	WRITE32_MEMBER(sgi_ip2_state::sgi_ip2_ptmap_w)
305	306	{
306		verboselog(machine(), 0, "sgi_ip2_ptmap_w: %08x = %08x & %08x\n", 0x3b000000 + (offset << 2), data, mem_mask);
	307	verboselog(0, "sgi_ip2_ptmap_w: %08x = %08x & %08x\n", 0x3b000000 + (offset << 2), data, mem_mask);
307	308	COMBINE_DATA(&m_ptmap[offset]);
308	309	}
309	310
310	311
311	312	READ16_MEMBER(sgi_ip2_state::sgi_ip2_tdbase_r)
312	313	{
313		verboselog(machine(), 0, "sgi_ip2_tdbase_r: %04x\n", m_tdbase);
	314	verboselog(0, "sgi_ip2_tdbase_r: %04x\n", m_tdbase);
314	315	return m_tdbase;
315	316	}
316	317
317	318	WRITE16_MEMBER(sgi_ip2_state::sgi_ip2_tdbase_w)
318	319	{
319		verboselog(machine(), 0, "sgi_ip2_tdbase_w: %04x & %04x\n", data, mem_mask);
	320	verboselog(0, "sgi_ip2_tdbase_w: %04x & %04x\n", data, mem_mask);
320	321	COMBINE_DATA(&m_tdbase);
321	322	}
322	323
323	324
324	325	READ16_MEMBER(sgi_ip2_state::sgi_ip2_tdlmt_r)
325	326	{
326		verboselog(machine(), 0, "sgi_ip2_tdlmt_r: %04x\n", m_tdlmt);
	327	verboselog(0, "sgi_ip2_tdlmt_r: %04x\n", m_tdlmt);
327	328	return m_tdlmt;
328	329	}
329	330
330	331	WRITE16_MEMBER(sgi_ip2_state::sgi_ip2_tdlmt_w)
331	332	{
332		verboselog(machine(), 0, "sgi_ip2_tdlmt_w: %04x & %04x\n", data, mem_mask);
	333	verboselog(0, "sgi_ip2_tdlmt_w: %04x & %04x\n", data, mem_mask);
333	334	COMBINE_DATA(&m_tdlmt);
334	335	}
335	336
336	337
337	338	READ16_MEMBER(sgi_ip2_state::sgi_ip2_stkbase_r)
338	339	{
339		verboselog(machine(), 0, "sgi_ip2_stkbase_r: %04x\n", m_stkbase);
	340	verboselog(0, "sgi_ip2_stkbase_r: %04x\n", m_stkbase);
340	341	return m_stkbase;
341	342	}
342	343
343	344	WRITE16_MEMBER(sgi_ip2_state::sgi_ip2_stkbase_w)
344	345	{
345		verboselog(machine(), 0, "sgi_ip2_stkbase_w: %04x & %04x\n", data, mem_mask);
	346	verboselog(0, "sgi_ip2_stkbase_w: %04x & %04x\n", data, mem_mask);
346	347	COMBINE_DATA(&m_stkbase);
347	348	}
348	349
349	350
350	351	READ16_MEMBER(sgi_ip2_state::sgi_ip2_stklmt_r)
351	352	{
352		verboselog(machine(), 0, "sgi_ip2_stklmt_r: %04x\n", m_stklmt);
	353	verboselog(0, "sgi_ip2_stklmt_r: %04x\n", m_stklmt);
353	354	return m_stklmt;
354	355	}
355	356
356	357	WRITE16_MEMBER(sgi_ip2_state::sgi_ip2_stklmt_w)
357	358	{
358		verboselog(machine(), 0, "sgi_ip2_stklmt_w: %04x & %04x\n", data, mem_mask);
	359	verboselog(0, "sgi_ip2_stklmt_w: %04x & %04x\n", data, mem_mask);
359	360	COMBINE_DATA(&m_stklmt);
360	361	}
361	362

trunk/src/mess/drivers/ti990_4.c

r21160	r21161
63	63	virtual void video_start();
64	64	UINT32 screen_update_ti990_4(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
65	65	INTERRUPT_GEN_MEMBER(ti990_4_line_interrupt);
	66	void idle_callback(int state);
66	67	};
67	68
68	69
r21160	r21161
88	89	}
89	90
90	91	#ifdef UNUSED_FUNCTION
91		static void idle_callback(int state)
	92	void ti990_4_state::idle_callback(int state)
92	93	{
93	94	}
94	95	#endif

trunk/src/mess/drivers/pc6001.c

r21160	r21161
299	299	UINT8 check_joy_press();
300	300	UINT8 check_keyboard_press();
301	301	void vram_bank_change(UINT8 vram_bank);
	302	ATTR_CONST UINT8 pc6001_get_attributes(UINT8 c,int scanline, int pos);
	303	const UINT8 *pc6001_get_video_ram(int scanline);
	304	UINT8 pc6001_get_char_rom(UINT8 ch, int line);
302	305	};
303	306
304	307
r21160	r21161
838	841	}
839	842
840	843	#if 0
841		static ATTR_CONST UINT8 pc6001_get_attributes(running_machine &machine, UINT8 c,int scanline, int pos)
	844	ATTR_CONST pc6001_state::UINT8 pc6001_get_attributes(UINT8 c,int scanline, int pos)
842	845	{
843		pc6001_state *state = machine.driver_data<pc6001_state>();
844	846	UINT8 result = 0x00;
845		UINT8 val = state->m_video_ram [(scanline / 12) * 0x20 + pos];
	847	UINT8 val = m_video_ram [(scanline / 12) * 0x20 + pos];
846	848
847	849	if (val & 0x01) {
848	850	result |= M6847_INV;
r21160	r21161
854	856	return result;
855	857	}
856	858
857		static const UINT8 *pc6001_get_video_ram(running_machine &machine, int scanline)
	859	const pc6001_state::UINT8 *pc6001_get_video_ram(int scanline)
858	860	{
859		pc6001_state *state = machine.driver_data<pc6001_state>();
860		return state->m_video_ram +0x0200+ (scanline / 12) * 0x20;
	861	return m_video_ram +0x0200+ (scanline / 12) * 0x20;
861	862	}
862	863
863		static UINT8 pc6001_get_char_rom(running_machine &machine, UINT8 ch, int line)
	864	UINT8 pc6001_state::pc6001_get_char_rom(UINT8 ch, int line)
864	865	{
865	866	UINT8 *gfx = m_region_gfx1->base();
866	867	return gfx[ch*16+line];

trunk/src/mess/drivers/pc88va.c

r21160	r21161
152	152	DECLARE_FLOPPY_FORMATS( floppy_formats );
153	153	void pc88va_fdc_update_ready(floppy_image_device *, int);
154	154	IRQ_CALLBACK_MEMBER(pc88va_irq_callback);
	155	void draw_sprites(bitmap_rgb32 &bitmap, const rectangle &cliprect);
	156	UINT32 calc_kanji_rom_addr(UINT8 jis1,UINT8 jis2,int x,int y);
	157	void draw_text(bitmap_rgb32 &bitmap, const rectangle &cliprect);
	158	void tsp_sprite_enable(UINT32 spr_offset, UINT8 sw_bit);
	159	void execute_sync_cmd();
	160	void execute_dspon_cmd();
	161	void execute_dspdef_cmd();
	162	void execute_curdef_cmd();
	163	void execute_actscr_cmd();
	164	void execute_curs_cmd();
	165	void execute_emul_cmd();
	166	void execute_spron_cmd();
	167	void execute_sprsw_cmd();
155	168	};
156	169
157	170
r21160	r21161
160	173	{
161	174	}
162	175
163		static void draw_sprites(running_machine &machine, bitmap_rgb32 &bitmap, const rectangle &cliprect)
	176	void pc88va_state::draw_sprites(bitmap_rgb32 &bitmap, const rectangle &cliprect)
164	177	{
165		pc88va_state *state = machine.driver_data<pc88va_state>();
166		UINT16 *tvram = (UINT16 *)(*state->memregion("tvram"));
	178	UINT16 *tvram = (UINT16 *)(*memregion("tvram"));
167	179	int offs,i;
168	180
169		offs = state->m_tsp.spr_offset;
	181	offs = m_tsp.spr_offset;
170	182	for(i=0;i<(0x100);i+=(8))
171	183	{
172	184	int xp,yp,sw,md,xsize,ysize,spda,fg_col,bc;
r21160	r21161
221	233	pen = pen & 1 ? fg_col : (bc) ? 8 : -1;
222	234
223	235	if(pen != -1) //transparent pen
224		bitmap.pix32(yp+y_i, xp+x_i+(x_s)) = machine.pens[pen];
	236	bitmap.pix32(yp+y_i, xp+x_i+(x_s)) = machine().pens[pen];
225	237	}
226	238	spr_count+=2;
227	239	}
r21160	r21161
246	258	pen = (BITSWAP16(tvram[(spda+spr_count) / 2],7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8)) >> (16-(x_s*8)) & 0xf;
247	259
248	260	//if(bc != -1) //transparent pen
249		bitmap.pix32(yp+y_i, xp+x_i+(x_s)) = machine.pens[pen];
	261	bitmap.pix32(yp+y_i, xp+x_i+(x_s)) = machine().pens[pen];
250	262	}
251	263	spr_count+=2;
252	264	}
r21160	r21161
256	268	}
257	269
258	270	/* TODO: this is either a result of an hand-crafted ROM or the JIS stuff is really attribute related ... */
259		static UINT32 calc_kanji_rom_addr(UINT8 jis1,UINT8 jis2,int x,int y)
	271	UINT32 pc88va_state::calc_kanji_rom_addr(UINT8 jis1,UINT8 jis2,int x,int y)
260	272	{
261	273	if(jis1 < 0x30)
262	274	return ((jis2 & 0x60) << 8) + ((jis1 & 0x07) << 10) + ((jis2 & 0x1f) << 5);
r21160	r21161
270	282	return 0;
271	283	}
272	284
273		static void draw_text(running_machine &machine, bitmap_rgb32 &bitmap, const rectangle &cliprect)
	285	void pc88va_state::draw_text(bitmap_rgb32 &bitmap, const rectangle &cliprect)
274	286	{
275		pc88va_state *state = machine.driver_data<pc88va_state>();
276		UINT8 *tvram = machine.root_device().memregion("tvram")->base();
277		UINT8 *kanji = state->memregion("kanji")->base();
	287	UINT8 *tvram = machine().root_device().memregion("tvram")->base();
	288	UINT8 *kanji = memregion("kanji")->base();
278	289	int xi,yi;
279	290	int x,y;
280	291	int res_x,res_y;
r21160	r21161
288	299	//UINT8 blink,dwidc,dwid,uline,hline;
289	300	UINT8 screen_fg_col,screen_bg_col;
290	301
291		count = (tvram[state->m_tsp.tvram_vreg_offset+0] | tvram[state->m_tsp.tvram_vreg_offset+1] << 8);
	302	count = (tvram[m_tsp.tvram_vreg_offset+0] | tvram[m_tsp.tvram_vreg_offset+1] << 8);
292	303
293		attr_mode = tvram[state->m_tsp.tvram_vreg_offset+0xa] & 0x1f;
	304	attr_mode = tvram[m_tsp.tvram_vreg_offset+0xa] & 0x1f;
294	305	/* Note: bug in docs has the following two reversed */
295		screen_fg_col = (tvram[state->m_tsp.tvram_vreg_offset+0xb] & 0xf0) >> 4;
296		screen_bg_col = tvram[state->m_tsp.tvram_vreg_offset+0xb] & 0x0f;
	306	screen_fg_col = (tvram[m_tsp.tvram_vreg_offset+0xb] & 0xf0) >> 4;
	307	screen_bg_col = tvram[m_tsp.tvram_vreg_offset+0xb] & 0x0f;
297	308
298	309	for(y=0;y<13;y++)
299	310	{
r21160	r21161
305	316
306	317	tile_num = calc_kanji_rom_addr(jis1,jis2,x,y);
307	318
308		attr = (tvram[count+state->m_tsp.attr_offset] & 0x00ff);
	319	attr = (tvram[count+m_tsp.attr_offset] & 0x00ff);
309	320
310	321	fg_col = bg_col = reverse = secret = 0; //blink = dwidc = dwid = uline = hline = 0;
311	322
r21160	r21161
442	453	if(secret) { pen = 0; } //hide text
443	454
444	455	if(pen != -1) //transparent
445		bitmap.pix32(res_y, res_x) = machine.pens[pen];
	456	bitmap.pix32(res_y, res_x) = machine().pens[pen];
446	457	}
447	458	}
448	459
r21160	r21161
496	507	{
497	508	switch(cur_pri_lv & 3) // (palette color mode)
498	509	{
499		case 0: draw_text(machine(),bitmap,cliprect); break;
500		case 1: if(m_tsp.spr_on) { draw_sprites(machine(),bitmap,cliprect); } break;
	510	case 0: draw_text(bitmap,cliprect); break;
	511	case 1: if(m_tsp.spr_on) { draw_sprites(bitmap,cliprect); } break;
501	512	case 2: /* A = graphic 0 */ break;
502	513	case 3: /* B = graphic 1 */ break;
503	514	}
r21160	r21161
697	708	}
698	709	}
699	710
700		static void tsp_sprite_enable(running_machine &machine, UINT32 spr_offset, UINT8 sw_bit)
	711	void pc88va_state::tsp_sprite_enable(UINT32 spr_offset, UINT8 sw_bit)
701	712	{
702		address_space &space = machine.device("maincpu")->memory().space(AS_PROGRAM);
	713	address_space &space = machine().device("maincpu")->memory().space(AS_PROGRAM);
703	714
704	715	space.write_word(spr_offset, space.read_word(spr_offset) & ~0x200);
705	716	space.write_word(spr_offset, space.read_word(spr_offset) | (sw_bit & 0x200));
706	717	}
707	718
708	719	/* TODO: very preliminary, needs something showable first */
709		static void execute_sync_cmd(running_machine &machine)
	720	void pc88va_state::execute_sync_cmd()
710	721	{
711		pc88va_state *state = machine.driver_data<pc88va_state>();
712	722	/*
713	723	???? ???? [0] - unknown
714	724	???? ???? [1] - unknown
r21160	r21161
736	746	//printf("V border end: %d\n",(sync_cmd[0xc]));
737	747	//printf("V blank end: %d\n",(sync_cmd[0xd]));
738	748
739		x_vis_area = state->m_buf_ram[4] * 4;
740		y_vis_area = (state->m_buf_ram[0xa])|((state->m_buf_ram[0xb] & 0x40)<<2);
	749	x_vis_area = m_buf_ram[4] * 4;
	750	y_vis_area = (m_buf_ram[0xa])|((m_buf_ram[0xb] & 0x40)<<2);
741	751
742	752	visarea.set(0, x_vis_area - 1, 0, y_vis_area - 1);
743	753
r21160	r21161
748	758
749	759	refresh = HZ_TO_ATTOSECONDS(60);
750	760
751		machine.primary_screen->configure(640, 480, visarea, refresh);
	761	machine().primary_screen->configure(640, 480, visarea, refresh);
752	762	}
753	763
754		static void execute_dspon_cmd(running_machine &machine)
	764	void pc88va_state::execute_dspon_cmd()
755	765	{
756		pc88va_state *state = machine.driver_data<pc88va_state>();
757	766	/*
758	767	[0] text table offset (hi word)
759	768	[1] unknown
760	769	[2] unknown
761	770	*/
762		state->m_tsp.tvram_vreg_offset = state->m_buf_ram[0] << 8;
763		state->m_tsp.disp_on = 1;
	771	m_tsp.tvram_vreg_offset = m_buf_ram[0] << 8;
	772	m_tsp.disp_on = 1;
764	773	}
765	774
766		static void execute_dspdef_cmd(running_machine &machine)
	775	void pc88va_state::execute_dspdef_cmd()
767	776	{
768		pc88va_state *state = machine.driver_data<pc88va_state>();
769	777	/*
770	778	[0] attr offset (lo word)
771	779	[1] attr offset (hi word)
r21160	r21161
774	782	[4] hline vertical position
775	783	[5] blink number
776	784	*/
777		state->m_tsp.attr_offset = state->m_buf_ram[0] | state->m_buf_ram[1] << 8;
778		state->m_tsp.pitch = (state->m_buf_ram[2] & 0xf0) >> 4;
779		state->m_tsp.line_height = state->m_buf_ram[3] + 1;
780		state->m_tsp.h_line_pos = state->m_buf_ram[4];
781		state->m_tsp.blink = (state->m_buf_ram[5] & 0xf8) >> 3;
	785	m_tsp.attr_offset = m_buf_ram[0] | m_buf_ram[1] << 8;
	786	m_tsp.pitch = (m_buf_ram[2] & 0xf0) >> 4;
	787	m_tsp.line_height = m_buf_ram[3] + 1;
	788	m_tsp.h_line_pos = m_buf_ram[4];
	789	m_tsp.blink = (m_buf_ram[5] & 0xf8) >> 3;
782	790	}
783	791
784		static void execute_curdef_cmd(running_machine &machine)
	792	void pc88va_state::execute_curdef_cmd()
785	793	{
786		pc88va_state *state = machine.driver_data<pc88va_state>();
787	794	/*
788	795	xxxx x--- [0] Sprite Cursor number (sprite RAM entry)
789	796	---- --x- [0] show cursor bit (actively modifies the spriteram entry)
r21160	r21161
791	798	*/
792	799
793	800	/* TODO: needs basic sprite emulation */
794		state->m_tsp.curn = (state->m_buf_ram[0] & 0xf8);
795		state->m_tsp.curn_blink = (state->m_buf_ram[0] & 1);
	801	m_tsp.curn = (m_buf_ram[0] & 0xf8);
	802	m_tsp.curn_blink = (m_buf_ram[0] & 1);
796	803
797		tsp_sprite_enable(machine, 0xa0000 + state->m_tsp.spr_offset + state->m_tsp.curn, (state->m_buf_ram[0] & 2) << 8);
	804	tsp_sprite_enable(0xa0000 + m_tsp.spr_offset + m_tsp.curn, (m_buf_ram[0] & 2) << 8);
798	805	}
799	806
800		static void execute_actscr_cmd(running_machine &machine)
	807	void pc88va_state::execute_actscr_cmd()
801	808	{
802		//pc88va_state *state = machine.driver_data<pc88va_state>();
803	809	/*
804	810	This command assigns a strip where the cursor is located.
805	811	xxxx xxxx [0] strip ID * 32 (???)
806	812	*/
807	813
808	814	/* TODO: no idea about this command */
809		//printf("ACTSCR: %02x\n",state->m_buf_ram[0]);
	815	//printf("ACTSCR: %02x\n",m_buf_ram[0]);
810	816	}
811	817
812		static void execute_curs_cmd(running_machine &machine)
	818	void pc88va_state::execute_curs_cmd()
813	819	{
814		pc88va_state *state = machine.driver_data<pc88va_state>();
815	820	/*
816	821	[0] Cursor Position Y (lo word)
817	822	[1] Cursor Position Y (hi word)
r21160	r21161
819	824	[3] Cursor Position X (hi word)
820	825	*/
821	826
822		state->m_tsp.cur_pos_y = state->m_buf_ram[0] | state->m_buf_ram[1] << 8;
823		state->m_tsp.cur_pos_x = state->m_buf_ram[2] | state->m_buf_ram[3] << 8;
	827	m_tsp.cur_pos_y = m_buf_ram[0] | m_buf_ram[1] << 8;
	828	m_tsp.cur_pos_x = m_buf_ram[2] | m_buf_ram[3] << 8;
824	829	}
825	830
826		static void execute_emul_cmd(running_machine &machine)
	831	void pc88va_state::execute_emul_cmd()
827	832	{
828	833	/*
829	834	[0] Emulate target strip ID x 32
r21160	r21161
836	841	//popmessage("Warning: TSP executes EMUL command, contact MESSdev");
837	842	}
838	843
839		static void execute_spron_cmd(running_machine &machine)
	844	void pc88va_state::execute_spron_cmd()
840	845	{
841		pc88va_state *state = machine.driver_data<pc88va_state>();
842	846	/*
843	847	[0] Sprite Table Offset (hi word)
844	848	[1] (unknown / reserved)
r21160	r21161
846	850	---- --x- [2] MG: all sprites are 2x zoomed vertically when 1
847	851	---- ---x [2] GR: 1 to enable the group collision detection
848	852	*/
849		state->m_tsp.spr_offset = state->m_buf_ram[0] << 8;
850		state->m_tsp.spr_on = 1;
851		printf("SPR TABLE %02x %02x %02x\n",state->m_buf_ram[0],state->m_buf_ram[1],state->m_buf_ram[2]);
	853	m_tsp.spr_offset = m_buf_ram[0] << 8;
	854	m_tsp.spr_on = 1;
	855	printf("SPR TABLE %02x %02x %02x\n",m_buf_ram[0],m_buf_ram[1],m_buf_ram[2]);
852	856	}
853	857
854		static void execute_sprsw_cmd(running_machine &machine)
	858	void pc88va_state::execute_sprsw_cmd()
855	859	{
856		pc88va_state *state = machine.driver_data<pc88va_state>();
857	860	/*
858	861	Toggle an individual sprite in the sprite ram entry
859	862	[0] xxxx x--- target sprite number
860	863	[0] ---- --x- sprite off/on switch
861	864	*/
862	865
863		tsp_sprite_enable(machine, 0xa0000 + state->m_tsp.spr_offset + (state->m_buf_ram[0] & 0xf8), (state->m_buf_ram[0] & 2) << 8);
	866	tsp_sprite_enable(0xa0000 + m_tsp.spr_offset + (m_buf_ram[0] & 0xf8), (m_buf_ram[0] & 2) << 8);
864	867	}
865	868
866	869	WRITE8_MEMBER(pc88va_state::idp_param_w)
r21160	r21161
876	879	m_buf_index = 0;
877	880	switch(m_cmd)
878	881	{
879		case SYNC:      execute_sync_cmd(machine());    break;
880		case DSPON:     execute_dspon_cmd(machine());   break;
881		case DSPDEF:    execute_dspdef_cmd(machine()); break;
882		case CURDEF:    execute_curdef_cmd(machine()); break;
883		case ACTSCR:    execute_actscr_cmd(machine()); break;
884		case CURS:      execute_curs_cmd(machine());   break;
885		case EMUL:      execute_emul_cmd(machine());   break;
886		case SPRON:     execute_spron_cmd(machine());  break;
887		case SPRSW:     execute_sprsw_cmd(machine());   break;
	882	case SYNC:      execute_sync_cmd();    break;
	883	case DSPON:     execute_dspon_cmd();   break;
	884	case DSPDEF:    execute_dspdef_cmd(); break;
	885	case CURDEF:    execute_curdef_cmd(); break;
	886	case ACTSCR:    execute_actscr_cmd(); break;
	887	case CURS:      execute_curs_cmd();   break;
	888	case EMUL:      execute_emul_cmd();   break;
	889	case SPRON:     execute_spron_cmd();  break;
	890	case SPRSW:     execute_sprsw_cmd();   break;
888	891
889	892	default:
890	893	//printf("%02x\n",data);

trunk/src/mess/drivers/4004clk.c

r21160	r21161
30	30	UINT8 m_timer;
31	31	virtual void machine_start();
32	32	TIMER_DEVICE_CALLBACK_MEMBER(timer_callback);
	33	UINT8 nixie_to_num(UINT16 val);
	34	inline void output_set_nixie_value(int index, int value);
	35	inline void output_set_neon_value(int index, int value);
33	36	};
34	37
35	38	READ8_MEMBER(nixieclock_state::data_r)
r21160	r21161
37	40	return ioport("INPUT")->read() & 0x0f;
38	41	}
39	42
40		static UINT8 nixie_to_num(UINT16 val)
	43	UINT8 nixieclock_state::nixie_to_num(UINT16 val)
41	44	{
42	45	if (BIT(val,0)) return 0;
43	46	if (BIT(val,1)) return 1;
r21160	r21161
52	55	return 10;
53	56	}
54	57
55		INLINE void output_set_nixie_value(int index, int value)
	58	inline void nixieclock_state::output_set_nixie_value(int index, int value)
56	59	{
57	60	output_set_indexed_value("nixie", index, value);
58	61	}
59	62
60		INLINE void output_set_neon_value(int index, int value)
	63	inline void nixieclock_state::output_set_neon_value(int index, int value)
61	64	{
62	65	output_set_indexed_value("neon", index, value);
63	66	}

trunk/src/mess/drivers/nanos.c

r21160	r21161
90	90	required_ioport m_line5;
91	91	required_ioport m_line6;
92	92	required_ioport m_linec;
	93	UINT8 row_number(UINT8 code);
93	94	};
94	95
95	96
r21160	r21161
366	367	}
367	368	}
368	369
369		static UINT8 row_number(UINT8 code) {
	370	UINT8 nanos_state::row_number(UINT8 code)
	371	{
370	372	if BIT(code,0) return 0;
371	373	if BIT(code,1) return 1;
372	374	if BIT(code,2) return 2;

trunk/src/mess/drivers/jr100.c

r21160	r21161
63	63	DECLARE_WRITE8_MEMBER(jr100_via_write_a);
64	64	DECLARE_WRITE8_MEMBER(jr100_via_write_b);
65	65	DECLARE_WRITE_LINE_MEMBER(jr100_via_write_cb2);
	66	UINT32 readByLittleEndian(UINT8 *buf,int pos);
66	67
67	68	protected:
68	69	required_device<via6522_device> m_via;
r21160	r21161
329	330	}
330	331	}
331	332
332		static UINT32 readByLittleEndian(UINT8 *buf,int pos)
	333	UINT32 jr100_state::readByLittleEndian(UINT8 *buf,int pos)
333	334	{
334	335	return buf[pos] + (buf[pos+1] << 8) + (buf[pos+2] << 16) + (buf[pos+3] << 24);
335	336	}
r21160	r21161
352	353	return IMAGE_INIT_FAIL;
353	354	}
354	355	int pos = 4;
355		if (readByLittleEndian(buf,pos)!=1) {
	356	if (state->readByLittleEndian(buf,pos)!=1) {
356	357	// not version 1 of PRG file
357	358	return IMAGE_INIT_FAIL;
358	359	}
359	360	pos += 4;
360		UINT32 len =readByLittleEndian(buf,pos); pos+= 4;
	361	UINT32 len =state->readByLittleEndian(buf,pos); pos+= 4;
361	362	pos += len; // skip name
362		UINT32 start_address = readByLittleEndian(buf,pos); pos+= 4;
363		UINT32 code_length   = readByLittleEndian(buf,pos); pos+= 4;
364		UINT32 flag          = readByLittleEndian(buf,pos); pos+= 4;
	363	UINT32 start_address = state->readByLittleEndian(buf,pos); pos+= 4;
	364	UINT32 code_length   = state->readByLittleEndian(buf,pos); pos+= 4;
	365	UINT32 flag          = state->readByLittleEndian(buf,pos); pos+= 4;
365	366
366	367	UINT32 end_address = start_address + code_length - 1;
367	368	// copy code

trunk/src/mess/drivers/pdp11.c

r21160	r21161
92	92	virtual void machine_reset();
93	93	DECLARE_MACHINE_RESET(pdp11ub2);
94	94	DECLARE_MACHINE_RESET(pdp11qb);
	95	void load9312prom(UINT8 *desc, UINT8 *src, int size);
95	96	};
96	97
97	98	WRITE16_MEMBER(pdp11_state::term_w)
r21160	r21161
248	249	}
249	250	}
250	251
251		static void load9312prom(UINT8 *desc, UINT8 *src, int size)
	252	void pdp11_state::load9312prom(UINT8 *desc, UINT8 *src, int size)
252	253	{
253	254	//   3   2   1   8
254	255	//   7   6   5   4

trunk/src/mess/drivers/dectalk.c

r21160	r21161
196	196	virtual void machine_reset();
197	197	TIMER_CALLBACK_MEMBER(outfifo_read_cb);
198	198	DECLARE_WRITE8_MEMBER(dectalk_kbd_put);
	199	void dectalk_outfifo_check ();
	200	void dectalk_clear_all_fifos(  );
	201	void dectalk_x2212_store(  );
	202	void dectalk_x2212_recall(  );
	203	void dectalk_semaphore_w ( UINT16 data );
	204	UINT16 dectalk_outfifo_r (  );
199	205	};
200	206
201	207
r21160	r21161
247	253	#define SPC_INITIALIZE state->m_m68k_spcflags_latch&0x1 // speech initialize flag
248	254	#define SPC_IRQ_ENABLED ((state->m_m68k_spcflags_latch&0x40)>>6) // irq enable flag
249	255
250		static void dectalk_outfifo_check (running_machine &machine)
	256	void dectalk_state::dectalk_outfifo_check ()
251	257	{
252		dectalk_state *state = machine.driver_data<dectalk_state>();
253	258	// check if output fifo is full; if it isn't, set the int on the dsp
254		if (((state->m_outfifo_head_ptr-1)&0xF) != state->m_outfifo_tail_ptr)
255		machine.device("dsp")->execute().set_input_line(0, ASSERT_LINE); // TMS32010 INT
	259	if (((m_outfifo_head_ptr-1)&0xF) != m_outfifo_tail_ptr)
	260	machine().device("dsp")->execute().set_input_line(0, ASSERT_LINE); // TMS32010 INT
256	261	else
257		machine.device("dsp")->execute().set_input_line(0, CLEAR_LINE); // TMS32010 INT
	262	machine().device("dsp")->execute().set_input_line(0, CLEAR_LINE); // TMS32010 INT
258	263	}
259	264
260		static void dectalk_clear_all_fifos( running_machine &machine )
	265	void dectalk_state::dectalk_clear_all_fifos(  )
261	266	{
262		dectalk_state *state = machine.driver_data<dectalk_state>();
263	267	// clear fifos (TODO: memset would work better here...)
264	268	int i;
265		for (i=0; i<16; i++) state->m_outfifo[i] = 0;
266		for (i=0; i<32; i++) state->m_infifo[i] = 0;
267		state->m_outfifo_tail_ptr = state->m_outfifo_head_ptr = 0;
268		state->m_infifo_tail_ptr = state->m_infifo_head_ptr = 0;
269		dectalk_outfifo_check(machine);
	269	for (i=0; i<16; i++) m_outfifo[i] = 0;
	270	for (i=0; i<32; i++) m_infifo[i] = 0;
	271	m_outfifo_tail_ptr = m_outfifo_head_ptr = 0;
	272	m_infifo_tail_ptr = m_infifo_head_ptr = 0;
	273	dectalk_outfifo_check();
270	274	}
271	275
272		static void dectalk_x2212_store( running_machine &machine )
	276	void dectalk_state::dectalk_x2212_store(  )
273	277	{
274		dectalk_state *state = machine.driver_data<dectalk_state>();
275		UINT8 *nvram = state->memregion("nvram")->base();
	278	UINT8 *nvram = memregion("nvram")->base();
276	279	int i;
277	280	for (i = 0; i < 256; i++)
278		nvram[i] = state->m_x2214_sram[i];
	281	nvram[i] = m_x2214_sram[i];
279	282	#ifdef NVRAM_LOG
280	283	logerror("nvram store done\n");
281	284	#endif
282	285	}
283	286
284		static void dectalk_x2212_recall( running_machine &machine )
	287	void dectalk_state::dectalk_x2212_recall(  )
285	288	{
286		dectalk_state *state = machine.driver_data<dectalk_state>();
287		UINT8 *nvram = state->memregion("nvram")->base();
	289	UINT8 *nvram = memregion("nvram")->base();
288	290	int i;
289	291	for (i = 0; i < 256; i++)
290		state->m_x2214_sram[i] = nvram[i];
	292	m_x2214_sram[i] = nvram[i];
291	293	#ifdef NVRAM_LOG
292	294	logerror("nvram recall done\n");
293	295	#endif
294	296	}
295	297
296	298	// helper for dsp infifo_semaphore flag to make dealing with interrupts easier
297		static void dectalk_semaphore_w ( running_machine &machine, UINT16 data )
	299	void dectalk_state::dectalk_semaphore_w ( UINT16 data )
298	300	{
299		dectalk_state *state = machine.driver_data<dectalk_state>();
300		state->m_infifo_semaphore = data&1;
301		if ((state->m_infifo_semaphore == 1) && (state->m_m68k_spcflags_latch&0x40))
	301	m_infifo_semaphore = data&1;
	302	if ((m_infifo_semaphore == 1) && (m_m68k_spcflags_latch&0x40))
302	303	{
303	304	#ifdef VERBOSE
304	305	logerror("speech int fired!\n");
305	306	#endif
306		machine.device("maincpu")->execute().set_input_line_and_vector(M68K_IRQ_5, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
	307	machine().device("maincpu")->execute().set_input_line_and_vector(M68K_IRQ_5, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
307	308	}
308	309	else
309		machine.device("maincpu")->execute().set_input_line_and_vector(M68K_IRQ_5, CLEAR_LINE, M68K_INT_ACK_AUTOVECTOR);
	310	machine().device("maincpu")->execute().set_input_line_and_vector(M68K_IRQ_5, CLEAR_LINE, M68K_INT_ACK_AUTOVECTOR);
310	311	}
311	312
312	313	// read the output fifo and set the interrupt line active on the dsp
313		static UINT16 dectalk_outfifo_r ( running_machine &machine )
	314	UINT16 dectalk_state::dectalk_outfifo_r (  )
314	315	{
315		dectalk_state *state = machine.driver_data<dectalk_state>();
316	316	UINT16 data = 0xFFFF;
317		data = state->m_outfifo[state->m_outfifo_tail_ptr];
	317	data = m_outfifo[m_outfifo_tail_ptr];
318	318	// if fifo is empty (tail ptr == head ptr), do not increment the tail ptr, otherwise do.
319		//if (state->m_outfifo_tail_ptr != state->m_outfifo_head_ptr) state->m_outfifo_tail_ptr++; // technically correct but doesn't match sn74ls224 sheet
320		if (((state->m_outfifo_head_ptr-1)&0xF) != state->m_outfifo_tail_ptr) state->m_outfifo_tail_ptr++; // matches sn74ls224 sheet
321		state->m_outfifo_tail_ptr&=0xF;
322		dectalk_outfifo_check(machine);
	319	//if (m_outfifo_tail_ptr != m_outfifo_head_ptr) m_outfifo_tail_ptr++; // technically correct but doesn't match sn74ls224 sheet
	320	if (((m_outfifo_head_ptr-1)&0xF) != m_outfifo_tail_ptr) m_outfifo_tail_ptr++; // matches sn74ls224 sheet
	321	m_outfifo_tail_ptr&=0xF;
	322	dectalk_outfifo_check();
323	323	return ((data&0xfff0)^0x8000); // yes this is right, top bit is inverted and bottom 4 are ignored
324	324	//return data; // not right but want to get it working first
325	325	}
r21160	r21161
331	331	state->m_hack_self_test = 0; // hack
332	332	// stuff that is DIRECTLY affected by the RESET line
333	333	state->m_statusLED = 0; // clear status led latch
334		dectalk_x2212_recall(device->machine()); // nvram recall
	334	state->dectalk_x2212_recall(); // nvram recall
335	335	state->m_m68k_spcflags_latch = 1; // initial status is speech reset(d0) active and spc int(d6) disabled
336	336	state->m_m68k_tlcflags_latch = 0; // initial status is tone detect int(d6) off, answer phone(d8) off, ring detect int(d14) off
337	337	device->machine().device("duart68681")->reset(); // reset the DUART
338	338	// stuff that is INDIRECTLY affected by the RESET line
339		dectalk_clear_all_fifos(device->machine()); // speech reset clears the fifos, though we have to do it explicitly here since we're not actually in the m68k_spcflags_w function.
340		dectalk_semaphore_w(device->machine(), 0); // on the original state->m_dectalk pcb revision, this is a semaphore for the INPUT fifo, later dec hacked on a check for the 3 output fifo chips to see if they're in sync, and set both of these latches if true.
	339	state->dectalk_clear_all_fifos(); // speech reset clears the fifos, though we have to do it explicitly here since we're not actually in the m68k_spcflags_w function.
	340	state->dectalk_semaphore_w(0); // on the original state->m_dectalk pcb revision, this is a semaphore for the INPUT fifo, later dec hacked on a check for the 3 output fifo chips to see if they're in sync, and set both of these latches if true.
341	341	state->m_spc_error_latch = 0; // spc error latch is cleared on /reset
342	342	device->machine().device("dsp")->execute().set_input_line(INPUT_LINE_RESET, ASSERT_LINE); // speech reset forces the CLR line active on the tms32010
343	343	state->m_tlc_tonedetect = 0; // TODO, needed for selftest pass
r21160	r21161
362	362	logerror("m68k: nvram read at %08X: %02X\n", offset, data);
363	363	#endif
364	364	if (offset&0x200) // if a9 is set, do a /RECALL
365		dectalk_x2212_recall(machine());
	365	dectalk_x2212_recall();
366	366	return data;
367	367	}
368	368
r21160	r21161
383	383	#endif
384	384	m_x2214_sram[offset&0xff] = (UINT8)data&0x0f; // TODO: should this be before or after a possible /STORE? I'm guessing before.
385	385	if (offset&0x200) // if a9 is set, do a /STORE
386		dectalk_x2212_store(machine());
	386	dectalk_x2212_store();
387	387	}
388	388
389	389	WRITE16_MEMBER(dectalk_state::m68k_infifo_w)// 68k write to the speech input fifo
r21160	r21161
434	434	#ifdef SPC_LOG_68K
435	435	logerror(" | 0x01: initialize speech: fifos reset, clear error+semaphore latches and dsp reset\n");
436	436	#endif
437		dectalk_clear_all_fifos(machine());
	437	dectalk_clear_all_fifos();
438	438	machine().device("dsp")->execute().set_input_line(INPUT_LINE_RESET, ASSERT_LINE); // speech reset forces the CLR line active on the tms32010
439	439	// clear the two speech side latches
440	440	m_spc_error_latch = 0;
441		dectalk_semaphore_w(machine(), 0);
	441	dectalk_semaphore_w(0);
442	442	}
443	443	else // (data&0x1) == 0
444	444	{
r21160	r21161
454	454	#endif
455	455	// clear the two speech side latches
456	456	m_spc_error_latch = 0;
457		dectalk_semaphore_w(machine(), 0);
	457	dectalk_semaphore_w(0);
458	458	}
459	459	if ((data&0x40) == 0x40) // bit 6 - spc irq enable
460	460	{
r21160	r21161
572	572	#ifdef SPC_LOG_DSP
573	573	logerror("dsp: set fifo semaphore and set error status = %01X\n",data&1);
574	574	#endif
575		dectalk_semaphore_w(machine(), (~m_simulate_outfifo_error)&1); // always set to 1 here, unless outfifo error.
	575	dectalk_semaphore_w((~m_simulate_outfifo_error)&1); // always set to 1 here, unless outfifo error.
576	576	m_spc_error_latch = (data&1);
577	577	}
578	578
r21160	r21161
608	608	m_outfifo[m_outfifo_head_ptr] = data;
609	609	m_outfifo_head_ptr++;
610	610	m_outfifo_head_ptr&=0xF;
611		//dectalk_outfifo_check(machine()); // commented to allow int to clear
	611	//dectalk_outfifo_check(); // commented to allow int to clear
612	612	}
613	613
614	614	READ16_MEMBER(dectalk_state::spc_semaphore_r)// Return state of d-latch 74ls74 @ E64 'lower half' in d0 which indicates whether infifo is readable
r21160	r21161
703	703	{
704	704	UINT16 data;
705	705	dac_device *speaker = machine().device<dac_device>("dac");
706		data = dectalk_outfifo_r(machine());
	706	data = dectalk_outfifo_r();
707	707	#ifdef VERBOSE
708	708	if (data!= 0x8000) logerror("sample output: %04X\n", data);
709	709	#endif
r21160	r21161
714	714	/* Driver init: stuff that needs setting up which isn't directly affected by reset */
715	715	DRIVER_INIT_MEMBER(dectalk_state,dectalk)
716	716	{
717		dectalk_clear_all_fifos(machine());
	717	dectalk_clear_all_fifos();
718	718	m_simulate_outfifo_error = 0;
719	719	machine().scheduler().timer_set(attotime::from_hz(10000), timer_expired_delegate(FUNC(dectalk_state::outfifo_read_cb),this));
720	720	}

trunk/src/mess/drivers/socrates.c

r21160	r21161
131	131	INTERRUPT_GEN_MEMBER(assert_irq);
132	132	TIMER_CALLBACK_MEMBER(clear_speech_cb);
133	133	TIMER_CALLBACK_MEMBER(clear_irq_cb);
	134	void socrates_set_rom_bank();
	135	void socrates_set_ram_bank();
	136	void socrates_update_kb();
	137	void socrates_check_kb_latch();
	138	rgb_t socrates_create_color(UINT8 color);
134	139	};
135	140
136	141
r21160	r21161
140	145
141	146	/* Devices */
142	147
143		static void socrates_set_rom_bank( running_machine &machine )
	148	void socrates_state::socrates_set_rom_bank(  )
144	149	{
145		socrates_state *state = machine.driver_data<socrates_state>();
146		state->membank( "bank1" )->set_base( state->memregion("maincpu")->base() + ( state->m_rom_bank * 0x4000 ));
	150	membank( "bank1" )->set_base( memregion("maincpu")->base() + ( m_rom_bank * 0x4000 ));
147	151	}
148	152
149		static void socrates_set_ram_bank( running_machine &machine )
	153	void socrates_state::socrates_set_ram_bank(  )
150	154	{
151		socrates_state *state = machine.driver_data<socrates_state>();
152		state->membank( "bank2" )->set_base( machine.root_device().memregion("vram")->base() + ( (state->m_ram_bank&0x3) * 0x4000 )); // window 0
153		state->membank( "bank3" )->set_base( state->memregion("vram")->base() + ( ((state->m_ram_bank&0xC)>>2) * 0x4000 )); // window 1
	155	membank( "bank2" )->set_base( machine().root_device().memregion("vram")->base() + ( (m_ram_bank&0x3) * 0x4000 )); // window 0
	156	membank( "bank3" )->set_base( memregion("vram")->base() + ( ((m_ram_bank&0xC)>>2) * 0x4000 )); // window 1
154	157	}
155	158
156		static void socrates_update_kb( running_machine &machine )
	159	void socrates_state::socrates_update_kb(  )
157	160	{
158		socrates_state *state = machine.driver_data<socrates_state>();
159	161	static const char *const rownames[] = { "keyboard_40", "keyboard_41", "keyboard_42", "keyboard_43", "keyboard_44" };
160	162	int row, keyvalue, powerof2;
161	163	int shift = 0;
162	164	// first check that the kb latch[1] is clear; if it isn't, don't touch it!
163		if ((state->m_kb_latch_low[1] != 0) || (state->m_kb_latch_high[1] != 1)) return;
	165	if ((m_kb_latch_low[1] != 0) || (m_kb_latch_high[1] != 1)) return;
164	166	// next check for joypad buttons
165		keyvalue = machine.root_device().ioport("keyboard_jp")->read();
	167	keyvalue = machine().root_device().ioport("keyboard_jp")->read();
166	168	if (keyvalue != 0)
167	169	{
168		state->m_kb_latch_low[1] = (keyvalue & 0xFF0)>>4;
169		state->m_kb_latch_high[1] = 0x80 | (keyvalue & 0xF);
	170	m_kb_latch_low[1] = (keyvalue & 0xFF0)>>4;
	171	m_kb_latch_high[1] = 0x80 | (keyvalue & 0xF);
170	172	return; // get out of this function; due to the way key priorities work, we're done here.
171	173	}
172	174	// next check for mouse movement.
173	175	// this isn't written yet, so write me please!
174	176	// next check if shift is down
175		shift = machine.root_device().ioport("keyboard_50")->read();
	177	shift = machine().root_device().ioport("keyboard_50")->read();
176	178	// find key low and high byte ok keyboard section
177	179	for (row = 4; row>=0; row--)
178	180	{
179		keyvalue = machine.root_device().ioport(rownames[row])->read();
	181	keyvalue = machine().root_device().ioport(rownames[row])->read();
180	182	if (keyvalue != 0)
181	183	{
182	184	for (powerof2 = 9; powerof2 >= 0; powerof2--)
183	185	{
184	186	if ((keyvalue&(1<<powerof2)) == (1<<powerof2))
185	187	{
186		state->m_kb_latch_low[1] = (shift?0x50:0x40)+row;
187		state->m_kb_latch_high[1] = (0x80 | powerof2);
	188	m_kb_latch_low[1] = (shift?0x50:0x40)+row;
	189	m_kb_latch_high[1] = (0x80 | powerof2);
188	190	return; // get out of the for loop; due to the way key priorities work, we're done here.
189	191	}
190	192	}
r21160	r21161
193	195	// no key was pressed... check if shift was hit then?
194	196	if (shift != 0)
195	197	{
196		state->m_kb_latch_low[1] = 0x50;
197		state->m_kb_latch_high[1] = 0x80;
	198	m_kb_latch_low[1] = 0x50;
	199	m_kb_latch_high[1] = 0x80;
198	200	}
199	201	}
200	202
201		static void socrates_check_kb_latch( running_machine &machine ) // if kb[1] is full and kb[0] is not, shift [1] to [0] and clear [1]
	203	void socrates_state::socrates_check_kb_latch(  ) // if kb[1] is full and kb[0] is not, shift [1] to [0] and clear [1]
202	204	{
203		socrates_state *state = machine.driver_data<socrates_state>();
204		if (((state->m_kb_latch_low[1] != 0) || (state->m_kb_latch_high[1] != 1)) &&
205		((state->m_kb_latch_low[0] == 0) && (state->m_kb_latch_high[0] == 1)))
	205	if (((m_kb_latch_low[1] != 0) || (m_kb_latch_high[1] != 1)) &&
	206	((m_kb_latch_low[0] == 0) && (m_kb_latch_high[0] == 1)))
206	207	{
207		state->m_kb_latch_low[0] = state->m_kb_latch_low[1];
208		state->m_kb_latch_low[1] = 0;
209		state->m_kb_latch_high[0] = state->m_kb_latch_high[1];
210		state->m_kb_latch_high[1] = 1;
	208	m_kb_latch_low[0] = m_kb_latch_low[1];
	209	m_kb_latch_low[1] = 0;
	210	m_kb_latch_high[0] = m_kb_latch_high[1];
	211	m_kb_latch_high[1] = 1;
211	212	}
212	213	}
213	214
214	215	void socrates_state::machine_reset()
215	216	{
216	217	m_rom_bank = 0xF3; // actually set semi-randomly on real console but we need to initialize it somewhere...
217		socrates_set_rom_bank( machine() );
	218	socrates_set_rom_bank();
218	219	m_ram_bank = 0;  // the actual console sets it semi randomly on power up, and the bios cleans it up.
219		socrates_set_ram_bank( machine() );
	220	socrates_set_ram_bank();
220	221	m_kb_latch_low[0] = 0xFF;
221	222	m_kb_latch_high[0] = 0x8F;
222	223	m_kb_latch_low[1] = 0x00;
r21160	r21161
253	254	WRITE8_MEMBER(socrates_state::socrates_rom_bank_w)
254	255	{
255	256	m_rom_bank = data;
256		socrates_set_rom_bank(machine());
	257	socrates_set_rom_bank();
257	258	}
258	259
259	260	READ8_MEMBER(socrates_state::socrates_ram_bank_r)
r21160	r21161
264	265	WRITE8_MEMBER(socrates_state::socrates_ram_bank_w)
265	266	{
266	267	m_ram_bank = data&0xF;
267		socrates_set_ram_bank(machine());
	268	socrates_set_ram_bank();
268	269	}
269	270
270	271	READ8_MEMBER(socrates_state::read_f3)// used for read-only i/o ports as mame/mess doesn't have a way to set the unmapped area to read as 0xF3
r21160	r21161
449	450
450	451	READ8_MEMBER(socrates_state::socrates_keyboard_low_r)// keyboard code low
451	452	{
452		socrates_update_kb(machine());
453		socrates_check_kb_latch(machine());
	453	socrates_update_kb();
	454	socrates_check_kb_latch();
454	455	return m_kb_latch_low[0];
455	456	}
456	457
457	458	READ8_MEMBER(socrates_state::socrates_keyboard_high_r)// keyboard code high
458	459	{
459		socrates_update_kb(machine());
460		socrates_check_kb_latch(machine());
	460	socrates_update_kb();
	461	socrates_check_kb_latch();
461	462	return m_kb_latch_high[0];
462	463	}
463	464
r21160	r21161
510	511	// gamma: this needs to be messed with... may differ on different systems... attach to slider somehow?
511	512	#define GAMMA 1.5
512	513
513		static rgb_t socrates_create_color(UINT8 color)
	514	rgb_t socrates_state::socrates_create_color(UINT8 color)
514	515	{
515	516	rgb_t composedcolor;
516	517	static const double lumatable[256] = {

trunk/src/mess/drivers/ng_aes.c

r21160	r21161
210	210	required_ioport m_io_ctrlsel;
211	211
212	212	void common_machine_start();
	213	INT32 SekIdle(INT32 nCycles);
213	214	};
214	215
215	216
r21160	r21161
688	689
689	690
690	691
691		static INT32 SekIdle(INT32 nCycles)
	692	INT32 ng_aes_state::SekIdle(INT32 nCycles)
692	693	{
693	694	return nCycles;
694	695	}

trunk/src/mess/drivers/sgi_ip6.c

r21160	r21161
43	43	virtual void video_start();
44	44	UINT32 screen_update_sgi_ip6(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
45	45	INTERRUPT_GEN_MEMBER(sgi_ip6_vbl);
	46	inline void ATTR_PRINTF(3,4) verboselog( int n_level, const char *s_fmt, ... );
46	47	};
47	48
48	49
r21160	r21161
51	52	#define ENABLE_VERBOSE_LOG (1)
52	53
53	54	#if ENABLE_VERBOSE_LOG
54		INLINE void ATTR_PRINTF(3,4) verboselog( running_machine &machine, int n_level, const char *s_fmt, ... )
	55	inline void ATTR_PRINTF(3,4) sgi_ip6_state::verboselog( int n_level, const char *s_fmt, ... )
55	56	{
56	57	if( VERBOSE_LEVEL >= n_level )
57	58	{
r21160	r21161
60	61	va_start( v, s_fmt );
61	62	vsprintf( buf, s_fmt, v );
62	63	va_end( v );
63		logerror("%08x: %s", machine.device("maincpu")->safe_pc(), buf);
	64	logerror("%08x: %s", machine().device("maincpu")->safe_pc(), buf);
64	65	}
65	66	}
66	67	#else
r21160	r21161
93	94	case 0x0000/4:
94	95	if(ACCESSING_BITS_16_31)
95	96	{
96		verboselog(machine(), 0, "ip6_unk1_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
	97	verboselog(0, "ip6_unk1_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
97	98	}
98	99	if(ACCESSING_BITS_0_15)
99	100	{
100		verboselog(machine(), 0, "ip6_unk1_r: Unknown Halfword 0: %08x & %08x\n", m_ip6_regs.unknown_half_0, mem_mask );
	101	verboselog(0, "ip6_unk1_r: Unknown Halfword 0: %08x & %08x\n", m_ip6_regs.unknown_half_0, mem_mask );
101	102	ret |= m_ip6_regs.unknown_half_0;
102	103	}
103	104	break;
104	105	default:
105		verboselog(machine(), 0, "ip6_unk1_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
	106	verboselog(0, "ip6_unk1_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
106	107	break;
107	108	}
108	109	return ret;
r21160	r21161
115	116	case 0x0000/4:
116	117	if(ACCESSING_BITS_16_31)
117	118	{
118		verboselog(machine(), 0, "ip6_unk1_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
	119	verboselog(0, "ip6_unk1_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
119	120	}
120	121	if(ACCESSING_BITS_0_15)
121	122	{
122		verboselog(machine(), 0, "ip6_unk1_w: Unknown Halfword 0 = %04x & %04x\n", data & 0x0000ffff, mem_mask & 0x0000ffff );
	123	verboselog(0, "ip6_unk1_w: Unknown Halfword 0 = %04x & %04x\n", data & 0x0000ffff, mem_mask & 0x0000ffff );
123	124	m_ip6_regs.unknown_half_0 = data & 0x0000ffff;
124	125	}
125	126	break;
126	127	default:
127		verboselog(machine(), 0, "ip6_unk1_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
	128	verboselog(0, "ip6_unk1_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
128	129	break;
129	130	}
130	131	}
r21160	r21161
137	138	case 0x0000/4:
138	139	if(!ACCESSING_BITS_24_31)
139	140	{
140		verboselog(machine(), 0, "ip6_unk2_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
	141	verboselog(0, "ip6_unk2_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
141	142	}
142	143	if(ACCESSING_BITS_24_31)
143	144	{
144		verboselog(machine(), 0, "ip6_unk2_r: Unknown Byte 0 = %02x & %02x\n", m_ip6_regs.unknown_byte_0, mem_mask >> 24 );
	145	verboselog(0, "ip6_unk2_r: Unknown Byte 0 = %02x & %02x\n", m_ip6_regs.unknown_byte_0, mem_mask >> 24 );
145	146	ret |= m_ip6_regs.unknown_byte_0 << 24;
146	147	}
147	148	break;
148	149	default:
149		verboselog(machine(), 0, "ip6_unk2_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
	150	verboselog(0, "ip6_unk2_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
150	151	break;
151	152	}
152	153	return ret;
r21160	r21161
159	160	case 0x0000/4:
160	161	if(!ACCESSING_BITS_24_31)
161	162	{
162		verboselog(machine(), 0, "ip6_unk2_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
	163	verboselog(0, "ip6_unk2_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
163	164	}
164	165	if(ACCESSING_BITS_24_31)
165	166	{
166		verboselog(machine(), 0, "ip6_unk2_w: Unknown Byte 0 = %02x & %02x\n", data >> 24, mem_mask >> 24 );
	167	verboselog(0, "ip6_unk2_w: Unknown Byte 0 = %02x & %02x\n", data >> 24, mem_mask >> 24 );
167	168	m_ip6_regs.unknown_byte_0 = (data & 0xff000000) >> 24;
168	169	}
169	170	break;
170	171	default:
171		verboselog(machine(), 0, "ip6_unk2_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
	172	verboselog(0, "ip6_unk2_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
172	173	break;
173	174	}
174	175	}
r21160	r21161
178	179	UINT32 ret = 0;
179	180	if(ACCESSING_BITS_16_23)
180	181	{
181		verboselog(machine(), 0, "ip6_unk3_r: Unknown Byte 1: %02x & %02x\n", m_ip6_regs.unknown_byte_1, (mem_mask >> 16) & 0x000000ff);
	182	verboselog(0, "ip6_unk3_r: Unknown Byte 1: %02x & %02x\n", m_ip6_regs.unknown_byte_1, (mem_mask >> 16) & 0x000000ff);
182	183	ret |= m_ip6_regs.unknown_byte_1 << 16;
183	184	}
184	185	else
185	186	{
186		verboselog(machine(), 0, "ip6_unk3_r: Unknown address: %08x & %08x\n", 0x1fb00000 + (offset << 2), mem_mask );
	187	verboselog(0, "ip6_unk3_r: Unknown address: %08x & %08x\n", 0x1fb00000 + (offset << 2), mem_mask );
187	188	}
188	189	return ret;
189	190	}
190	191
191	192	WRITE32_MEMBER(sgi_ip6_state::ip6_unk3_w)
192	193	{
193		verboselog(machine(), 0, "ip6_unk3_w: Unknown address: %08x = %08x & %08x\n", 0x1fb00000 + (offset << 2), data, mem_mask );
	194	verboselog(0, "ip6_unk3_w: Unknown address: %08x = %08x & %08x\n", 0x1fb00000 + (offset << 2), data, mem_mask );
194	195	}
195	196
196	197	INTERRUPT_GEN_MEMBER(sgi_ip6_state::sgi_ip6_vbl)

trunk/src/mess/drivers/apc.c

r21160	r21161
157	157
158	158	virtual void video_start();
159	159	virtual void palette_init();
	160	inline void set_dma_channel(int channel, int state);
160	161	};
161	162
162	163	void apc_state::video_start()
r21160	r21161
955	956	program.write_byte(addr, data);
956	957	}
957	958
958		static void set_dma_channel(running_machine &machine, int channel, int state)
	959	inline void apc_state::set_dma_channel(int channel, int state)
959	960	{
960		apc_state *drvstate = machine.driver_data<apc_state>();
961		if (!state) drvstate->m_dack = channel;
	961	if (!state) m_dack = channel;
962	962	}
963	963
964		WRITE_LINE_MEMBER(apc_state::apc_dack0_w){ /*printf("%02x 0\n",state);*/ set_dma_channel(machine(), 0, state); }
965		WRITE_LINE_MEMBER(apc_state::apc_dack1_w){ /*printf("%02x 1\n",state);*/ set_dma_channel(machine(), 1, state); }
966		WRITE_LINE_MEMBER(apc_state::apc_dack2_w){ /*printf("%02x 2\n",state);*/ set_dma_channel(machine(), 2, state); }
967		WRITE_LINE_MEMBER(apc_state::apc_dack3_w){ /*printf("%02x 3\n",state);*/ set_dma_channel(machine(), 3, state); }
	964	WRITE_LINE_MEMBER(apc_state::apc_dack0_w){ /*printf("%02x 0\n",state);*/ set_dma_channel(0, state); }
	965	WRITE_LINE_MEMBER(apc_state::apc_dack1_w){ /*printf("%02x 1\n",state);*/ set_dma_channel(1, state); }
	966	WRITE_LINE_MEMBER(apc_state::apc_dack2_w){ /*printf("%02x 2\n",state);*/ set_dma_channel(2, state); }
	967	WRITE_LINE_MEMBER(apc_state::apc_dack3_w){ /*printf("%02x 3\n",state);*/ set_dma_channel(3, state); }
968	968
969	969	READ8_MEMBER(apc_state::fdc_r)
970	970	{

trunk/src/mess/drivers/supercon.c

r21160	r21161
117	117	required_ioport m_board_7;
118	118	required_ioport m_board_8;
119	119	void mouse_update();
	120	int get_first_cleared_bit(UINT8 data);
	121	int get_first_bit(UINT8 data);
120	122	};
121	123
122	124
r21160	r21161
199	201	}
200	202	}
201	203
202		static int get_first_cleared_bit(UINT8 data)
	204	int supercon_state::get_first_cleared_bit(UINT8 data)
203	205	{
204	206	int i;
205	207
r21160	r21161
210	212	return NOT_VALID;
211	213	}
212	214
213		static int get_first_bit(UINT8 data)
	215	int supercon_state::get_first_bit(UINT8 data)
214	216	{
215	217	int i;
216	218

trunk/src/mess/drivers/craft.c

r21160	r21161
13	13	#define ENABLE_VERBOSE_LOG (0)
14	14
15	15	#if ENABLE_VERBOSE_LOG
16		INLINE void verboselog(running_machine &machine, int n_level, const char *s_fmt, ...)
	16	inline void craft_state::verboselog(int n_level, const char *s_fmt, ...)
17	17	{
18	18	if( VERBOSE_LEVEL >= n_level )
19	19	{
r21160	r21161
22	22	va_start( v, s_fmt );
23	23	vsprintf( buf, s_fmt, v );
24	24	va_end( v );
25		logerror( "%08x: %s", machine.device("maincpu")->safe_pc(), buf );
	25	logerror( "%08x: %s", machine().device("maincpu")->safe_pc(), buf );
26	26	}
27	27	}
28	28	#else
r21160	r21161
76	76	DECLARE_DRIVER_INIT(craft);
77	77	virtual void machine_reset();
78	78	UINT32 screen_update_craft(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
	79	#if ENABLE_VERBOSE_LOG
	80	inline void verboselog(int n_level, const char *s_fmt, ...);
	81	#endif
79	82	};
80	83
81	84	void craft_state::machine_start()

trunk/src/mess/drivers/vk100.c

r21160	r21161
204	204	DECLARE_WRITE_LINE_MEMBER(i8251_rxrdy_int);
205	205	DECLARE_WRITE_LINE_MEMBER(i8251_txrdy_int);
206	206	DECLARE_WRITE_LINE_MEMBER(i8251_rts);
	207	UINT8 vram_read();
	208	void vram_write(UINT8 data);
207	209	};
208	210
209	211	// vram access functions:
r21160	r21161
228	230	*/
229	231
230	232	// returns one nybble from vram array based on X and Y regs
231		static UINT8 vram_read(running_machine &machine)
	233	UINT8 vk100_state::vram_read()
232	234	{
233		vk100_state *state = machine.driver_data<vk100_state>();
234	235	// XFinal is (X'&0x3FC)|(X&0x3)
235		UINT16 XFinal = state->m_trans[(state->m_vgX&0x3FC)>>2]<<2|(state->m_vgX&0x3); // appears correct
	236	UINT16 XFinal = m_trans[(m_vgX&0x3FC)>>2]<<2|(m_vgX&0x3); // appears correct
236	237	// EA is the effective ram address for a 16-bit block
237		UINT16 EA = ((state->m_vgY&0x1FE)<<5)|(XFinal>>4); // appears correct
	238	UINT16 EA = ((m_vgY&0x1FE)<<5)|(XFinal>>4); // appears correct
238	239	// block is the 16 bit block directly (note EA has to be <<1 to correctly index a byte)
239		UINT16 block = state->m_vram[(EA<<1)+1] | (state->m_vram[(EA<<1)]<<8);
	240	UINT16 block = m_vram[(EA<<1)+1] | (m_vram[(EA<<1)]<<8);
240	241	// nybbleNum is which of the four nybbles within the block to address. should NEVER be 3!
241	242	UINT8 nybbleNum = (XFinal&0xC)>>2;
242	243	return (block>>(4*nybbleNum))&0xF;
243	244	}
244	245
245		static void vram_write(running_machine &machine, UINT8 data)
	246	void vk100_state::vram_write(UINT8 data)
246	247	{
247		vk100_state *state = machine.driver_data<vk100_state>();
248	248	// XFinal is (X'&0x3FC)|(X&0x3)
249		UINT16 XFinal = state->m_trans[(state->m_vgX&0x3FC)>>2]<<2|(state->m_vgX&0x3); // appears correct
	249	UINT16 XFinal = m_trans[(m_vgX&0x3FC)>>2]<<2|(m_vgX&0x3); // appears correct
250	250	// EA is the effective ram address for a 16-bit block
251		UINT16 EA = ((state->m_vgY&0x1FE)<<5)|(XFinal>>4); // appears correct
	251	UINT16 EA = ((m_vgY&0x1FE)<<5)|(XFinal>>4); // appears correct
252	252	// block is the 16 bit block directly (note EA has to be <<1 to correctly index a byte)
253		UINT16 block = state->m_vram[(EA<<1)+1] | (state->m_vram[(EA<<1)]<<8);
	253	UINT16 block = m_vram[(EA<<1)+1] | (m_vram[(EA<<1)]<<8);
254	254	// nybbleNum is which of the four nybbles within the block to address. should NEVER be 3!
255	255	UINT8 nybbleNum = (XFinal&0xC)>>2;
256	256	block &= ~((UINT16)0xF<<(nybbleNum*4)); // mask out the part we want to replace
257	257	block |= data<<(nybbleNum*4); // write the new part
258	258	// NOTE: this next part may have to be made conditional on VG_MODE
259	259	// check if the attribute nybble is supposed to be modified, and if so do so
260		if (state->VG_WOPS&0x08) block = (block&0x0FFF)|(((UINT16)state->VG_WOPS&0xF0)<<8);
261		state->m_vram[(EA<<1)+1] = block&0xFF; // write block back to vram
262		state->m_vram[(EA<<1)] = (block&0xFF00)>>8; // ''
	260	if (VG_WOPS&0x08) block = (block&0x0FFF)|(((UINT16)VG_WOPS&0xF0)<<8);
	261	m_vram[(EA<<1)+1] = block&0xFF; // write block back to vram
	262	m_vram[(EA<<1)] = (block&0xFF00)>>8; // ''
263	263	}
264	264
265	265	TIMER_CALLBACK_MEMBER(vk100_state::execute_vg)
266	266	{
267		UINT8 thisNyb = vram_read(machine()); // read in the nybble
	267	UINT8 thisNyb = vram_read(); // read in the nybble
268	268	// pattern rom addressing is a complex mess. see the pattern rom def later in this file.
269	269	UINT8 newNyb = m_pattern[((m_vgPAT&m_vgPAT_Mask)?0x200:0)|((VG_WOPS&7)<<6)|((m_vgX&3)<<4)|thisNyb]; // calculate new nybble based on pattern rom
270	270	// finally write the block back to ram depending on the VG_MODE (sort of a hack until we get the vector and synd and dir roms all hooked up)
r21160	r21161
275	275	case 1: // dot: only write the LAST pixel in the chain? TODO: some fallthrough magic here?
276	276	if ((m_vgDownCount) == 0x00)
277	277	{
278		vram_write(machine(), newNyb); // write out the modified nybble
	278	vram_write(newNyb); // write out the modified nybble
279	279	}
280	280	break;
281	281	case 2: // vec: draw the vector
282		vram_write(machine(), newNyb); // write out the modified nybble
	282	vram_write(newNyb); // write out the modified nybble
283	283	break;
284	284	case 3: // er: erase: special case here: wipe the entire screen (except for color/attrib?) and then set done.
285	285	for (int i = 0; i < 0x8000; i++)
r21160	r21161
576	576	#ifdef SYSTAT_A_VERBOSE
577	577	if (m_maincpu->pc() != 0x31D) logerror("0x%04X: SYSTAT_A Read!\n", m_maincpu->pc());
578	578	#endif
579		return ((m_vgGO?0:1)<<7)|(vram_read(machine())<<3)|(((m_dipsw->read()>>dipswitchLUT[offset])&1)?0x4:0)|(m_vsync?0x2:0);
	579	return ((m_vgGO?0:1)<<7)|(vram_read()<<3)|(((m_dipsw->read()>>dipswitchLUT[offset])&1)?0x4:0)|(m_vsync?0x2:0);
580	580	}
581	581
582	582	/* port 0x48: "SYSTAT B"; NOT documented in the tech manual at all.

trunk/src/mess/drivers/juicebox.c

r21160	r21161
18	18
19	19	#define VERBOSE_LEVEL ( 0 )
20	20
21		INLINE void ATTR_PRINTF(3,4) verboselog( running_machine &machine, int n_level, const char *s_fmt, ...)
22		{
23		if (VERBOSE_LEVEL >= n_level)
24		{
25		va_list v;
26		char buf[32768];
27		va_start( v, s_fmt);
28		vsprintf( buf, s_fmt, v);
29		va_end( v);
30		logerror( "%s: %s", machine.describe_context(), buf);
31		}
32		}
33
34	21	struct smc_t
35	22	{
36	23	int add_latch;
r21160	r21161
60	47	virtual void machine_start();
61	48	virtual void machine_reset();
62	49	DECLARE_INPUT_CHANGED_MEMBER(port_changed);
	50	inline void ATTR_PRINTF(3,4) verboselog( int n_level, const char *s_fmt, ...);
	51	void smc_reset( );
	52	void smc_init( );
	53	UINT8 smc_read( );
	54	void smc_write( UINT8 data);
63	55	};
64	56
	57	inline void ATTR_PRINTF(3,4)  juicebox_state::verboselog( int n_level, const char *s_fmt, ...)
	58	{
	59	if (VERBOSE_LEVEL >= n_level)
	60	{
	61	va_list v;
	62	char buf[32768];
	63	va_start( v, s_fmt);
	64	vsprintf( buf, s_fmt, v);
	65	va_end( v);
	66	logerror( "%s: %s", machine().describe_context(), buf);
	67	}
	68	}
	69
	70
65	71	/***************************************************************************
66	72	MACHINE HARDWARE
67	73	***************************************************************************/
r21160	r21161
69	75
70	76	// SMARTMEDIA
71	77
72		static void smc_reset( running_machine &machine)
	78	void juicebox_state::smc_reset( )
73	79	{
74		juicebox_state *state = machine.driver_data<juicebox_state>();
75		verboselog( machine, 5, "smc_reset\n");
76		state->smc.add_latch = 0;
77		state->smc.cmd_latch = 0;
	80	verboselog(5, "smc_reset\n");
	81	smc.add_latch = 0;
	82	smc.cmd_latch = 0;
78	83	}
79	84
80		static void smc_init( running_machine &machine)
	85	void juicebox_state::smc_init( )
81	86	{
82		verboselog( machine, 5, "smc_init\n");
83		smc_reset( machine);
	87	verboselog(5, "smc_init\n");
	88	smc_reset();
84	89	}
85	90
86		static UINT8 smc_read( running_machine &machine)
	91	UINT8 juicebox_state::smc_read( )
87	92	{
88		smartmedia_image_device *smartmedia = machine.device<smartmedia_image_device>( "smartmedia");
	93	smartmedia_image_device *smartmedia = machine().device<smartmedia_image_device>( "smartmedia");
89	94	UINT8 data;
90	95	if (smartmedia->is_present())
91	96	{
r21160	r21161
95	100	{
96	101	data = 0xFF;
97	102	}
98		verboselog( machine, 5, "smc_read %08X\n", data);
	103	verboselog(5, "smc_read %08X\n", data);
99	104	return data;
100	105	}
101	106
102		static void smc_write( running_machine &machine, UINT8 data)
	107	void juicebox_state::smc_write( UINT8 data)
103	108	{
104		juicebox_state *state = machine.driver_data<juicebox_state>();
105		smartmedia_image_device *smartmedia = machine.device<smartmedia_image_device>( "smartmedia");
106		verboselog( machine, 5, "smc_write %08X\n", data);
	109	smartmedia_image_device *smartmedia = machine().device<smartmedia_image_device>( "smartmedia");
	110	verboselog(5, "smc_write %08X\n", data);
107	111	if (smartmedia->is_present())
108	112	{
109		if (state->smc.cmd_latch)
	113	if (smc.cmd_latch)
110	114	{
111		verboselog( machine, 5, "smartmedia_command_w %08X\n", data);
	115	verboselog(5, "smartmedia_command_w %08X\n", data);
112	116	smartmedia->command_w(data);
113	117	}
114		else if (state->smc.add_latch)
	118	else if (smc.add_latch)
115	119	{
116		verboselog( machine, 5, "smartmedia_address_w %08X\n", data);
	120	verboselog(5, "smartmedia_address_w %08X\n", data);
117	121	smartmedia->address_w(data);
118	122	}
119	123	else
120	124	{
121		verboselog( machine, 5, "smartmedia_data_w %08X\n", data);
	125	verboselog(5, "smartmedia_data_w %08X\n", data);
122	126	smartmedia->data_w(data);
123	127	}
124	128	}
r21160	r21161
201	205	{
202	206	juicebox->smc.cmd_latch = ((data & 0x00000020) != 0);
203	207	juicebox->smc.add_latch = ((data & 0x00000040) != 0);
204		verboselog( device->machine(), 5, "s3c44b0_gpio_port_w - nand cle %d ale %d\n", (data & 0x20) ? 1 : 0, (data & 0x40) ? 1 : 0);
	208	juicebox->verboselog( 5, "s3c44b0_gpio_port_w - nand cle %d ale %d\n", (data & 0x20) ? 1 : 0, (data & 0x40) ? 1 : 0);
205	209	}
206	210	break;
207	211	}
r21160	r21161
212	216	READ32_MEMBER(juicebox_state::juicebox_nand_r)
213	217	{
214	218	UINT32 data = 0;
215		if (mem_mask & 0x000000FF) data = data | (smc_read(machine()) <<  0);
216		if (mem_mask & 0x0000FF00) data = data | (smc_read(machine()) <<  8);
217		if (mem_mask & 0x00FF0000) data = data | (smc_read(machine()) << 16);
218		if (mem_mask & 0xFF000000) data = data | (smc_read(machine()) << 24);
219		verboselog( machine(), 5, "juicebox_nand_r %08X %08X %08X\n", offset, mem_mask, data);
	219	if (mem_mask & 0x000000FF) data = data | (smc_read() <<  0);
	220	if (mem_mask & 0x0000FF00) data = data | (smc_read() <<  8);
	221	if (mem_mask & 0x00FF0000) data = data | (smc_read() << 16);
	222	if (mem_mask & 0xFF000000) data = data | (smc_read() << 24);
	223	verboselog( 5, "juicebox_nand_r %08X %08X %08X\n", offset, mem_mask, data);
220	224	return data;
221	225	}
222	226
223	227	WRITE32_MEMBER(juicebox_state::juicebox_nand_w)
224	228	{
225		verboselog( machine(), 5, "juicebox_nand_w %08X %08X %08X\n", offset, mem_mask, data);
226		if (mem_mask & 0x000000FF) smc_write(machine(), (data >>  0) & 0xFF);
227		if (mem_mask & 0x0000FF00) smc_write(machine(), (data >>  8) & 0xFF);
228		if (mem_mask & 0x00FF0000) smc_write(machine(), (data >> 16) & 0xFF);
229		if (mem_mask & 0xFF000000) smc_write(machine(), (data >> 24) & 0xFF);
	229	verboselog( 5, "juicebox_nand_w %08X %08X %08X\n", offset, mem_mask, data);
	230	if (mem_mask & 0x000000FF) smc_write((data >>  0) & 0xFF);
	231	if (mem_mask & 0x0000FF00) smc_write((data >>  8) & 0xFF);
	232	if (mem_mask & 0x00FF0000) smc_write((data >> 16) & 0xFF);
	233	if (mem_mask & 0xFF000000) smc_write((data >> 24) & 0xFF);
230	234	}
231	235
232	236	// I2S
r21160	r21161
249	253	void juicebox_state::machine_start()
250	254	{
251	255	s3c44b0 = machine().device( "s3c44b0");
252		smc_init( machine());
	256	smc_init();
253	257	dac = machine().device<dac_device>( "dac");
254	258	}
255	259
256	260	void juicebox_state::machine_reset()
257	261	{
258	262	machine().device("maincpu")->reset();
259		smc_reset( machine());
	263	smc_reset();
260	264	}
261	265
262	266	/***************************************************************************

trunk/src/mess/drivers/ssem.c

r21160	r21161
25	25	UINT32 screen_update_ssem(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
26	26	DECLARE_INPUT_CHANGED_MEMBER(panel_check);
27	27	DECLARE_DEVICE_IMAGE_LOAD_MEMBER(ssem_store);
	28	inline UINT32 reverse(UINT32 v);
	29	void glyph_print(bitmap_rgb32 &bitmap, INT32 x, INT32 y, const char *msg, ...);
	30	void strlower(char *buf);
28	31	};
29	32
30	33
r21160	r21161
37	40	// The de facto snapshot format for other SSEM simulators stores the data physically in that format as well.
38	41	// Therefore, in MESS, every 32-bit word has its bits reversed, too, and as a result the values must be
39	42	// un-reversed before being used.
40		INLINE UINT32 reverse(UINT32 v)
	43	inline UINT32 ssem_state::reverse(UINT32 v)
41	44	{
42	45	// Taken from http://www-graphics.stanford.edu/~seander/bithacks.html#ReverseParallel
43	46	// swap odd and even bits
r21160	r21161
396	399	{ 0xff, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0xff },
397	400	};
398	401
399		static void glyph_print(running_machine &machine, bitmap_rgb32 &bitmap, INT32 x, INT32 y, const char *msg, ...)
	402	void ssem_state::glyph_print(bitmap_rgb32 &bitmap, INT32 x, INT32 y, const char *msg, ...)
400	403	{
401	404	va_list arg_list;
402	405	char buf[32768];
403	406	INT32 index = 0;
404		screen_device *screen = machine.first_screen();
	407	screen_device *screen = machine().first_screen();
405	408	const rectangle &visarea = screen->visible_area();
406	409
407	410	va_start( arg_list, msg );
r21160	r21161
463	466	{
464	467	if(word & (1 << (31 - bit)))
465	468	{
466		glyph_print(machine(), bitmap, bit << 3, line << 3, "%c", line == m_store_line ? 4 : 2);
	469	glyph_print(bitmap, bit << 3, line << 3, "%c", line == m_store_line ? 4 : 2);
467	470	}
468	471	else
469	472	{
470		glyph_print(machine(), bitmap, bit << 3, line << 3, "%c", line == m_store_line ? 3 : 1);
	473	glyph_print(bitmap, bit << 3, line << 3, "%c", line == m_store_line ? 3 : 1);
471	474	}
472	475	}
473	476	}
r21160	r21161
476	479	{
477	480	if(accum & (1 << bit))
478	481	{
479		glyph_print(machine(), bitmap, bit << 3, 264, "%c", 2);
	482	glyph_print(bitmap, bit << 3, 264, "%c", 2);
480	483	}
481	484	else
482	485	{
483		glyph_print(machine(), bitmap, bit << 3, 264, "%c", 1);
	486	glyph_print(bitmap, bit << 3, 264, "%c", 1);
484	487	}
485	488	}
486	489
r21160	r21161
488	491	(m_store[(m_store_line << 2) | 1] << 16) |
489	492	(m_store[(m_store_line << 2) | 2] <<  8) |
490	493	(m_store[(m_store_line << 2) | 3] <<  0));
491		glyph_print(machine(), bitmap, 0, 272, "LINE:%02d  VALUE:%08x  HALT:%d", m_store_line, word, ssem_cpu->state().state_int(SSEM_HALT));
	494	glyph_print(bitmap, 0, 272, "LINE:%02d  VALUE:%08x  HALT:%d", m_store_line, word, ssem_cpu->state().state_int(SSEM_HALT));
492	495	return 0;
493	496	}
494	497
r21160	r21161
496	499	* Image helper functions                             *
497	500	\****************************************************/
498	501
499		static void strlower(char *buf)
	502	void ssem_state::strlower(char *buf)
500	503	{
501	504	if(buf)
502	505	{

trunk/src/mess/drivers/pasogo.c

r21160	r21161
74	74	TIMER_DEVICE_CALLBACK_MEMBER(vg230_timer);
75	75	DECLARE_WRITE_LINE_MEMBER(pasogo_pic8259_set_int_line);
76	76	IRQ_CALLBACK_MEMBER(pasogo_irq_callback);
	77	void vg230_reset();
	78	void vg230_init();
77	79	};
78	80
79	81
r21160	r21161
107	109	}
108	110	}
109	111
110		static void vg230_reset(running_machine &machine)
	112	void pasogo_state::vg230_reset()
111	113	{
112		pasogo_state *state = machine.driver_data<pasogo_state>();
113		vg230_t *vg230 = &state->m_vg230;
	114	vg230_t *vg230 = &m_vg230;
114	115	system_time systime;
115	116
116	117	memset(vg230, 0, sizeof(*vg230));
117	118	vg230->pmu.write_protected=TRUE;
118		machine.base_datetime(systime);
	119	machine().base_datetime(systime);
119	120
120	121	vg230->rtc.seconds= systime.local_time.second;
121	122	vg230->rtc.minutes= systime.local_time.minute;
r21160	r21161
125	126	vg230->bios_timer.data=0x7200; // HACK
126	127	}
127	128
128		static void vg230_init(running_machine &machine)
	129	void pasogo_state::vg230_init()
129	130	{
130		vg230_reset(machine);
	131	vg230_reset();
131	132	}
132	133
133	134
r21160	r21161
547	548
548	549	DRIVER_INIT_MEMBER(pasogo_state,pasogo)
549	550	{
550		vg230_init(machine());
	551	vg230_init();
551	552	memset(&m_ems, 0, sizeof(m_ems));
552	553	membank( "bank27" )->set_base( machine().root_device().memregion("user1")->base() + 0x00000 );
553	554	membank( "bank28" )->set_base( memregion("maincpu")->base() + 0xb8000/*?*/ );

trunk/src/mess/drivers/mini2440.c

r21160	r21161
13	13
14	14	#define VERBOSE_LEVEL ( 0 )
15	15
16		INLINE void ATTR_PRINTF(3,4) verboselog( running_machine &machine, int n_level, const char *s_fmt, ...)
17		{
18		if (VERBOSE_LEVEL >= n_level)
19		{
20		va_list v;
21		char buf[32768];
22		va_start( v, s_fmt);
23		vsprintf( buf, s_fmt, v);
24		va_end( v);
25		logerror( "%s: %s", machine.describe_context(), buf);
26		}
27		}
28
29	16	class mini2440_state : public driver_device
30	17	{
31	18	public:
r21160	r21161
53	40	virtual void machine_start();
54	41	virtual void machine_reset();
55	42	DECLARE_INPUT_CHANGED_MEMBER(mini2440_input_changed);
	43	inline void ATTR_PRINTF(3,4) verboselog( int n_level, const char *s_fmt, ...);
56	44	};
57	45
	46	inline void ATTR_PRINTF(3,4) mini2440_state::verboselog( int n_level, const char *s_fmt, ...)
	47	{
	48	if (VERBOSE_LEVEL >= n_level)
	49	{
	50	va_list v;
	51	char buf[32768];
	52	va_start( v, s_fmt);
	53	vsprintf( buf, s_fmt, v);
	54	va_end( v);
	55	logerror( "%s: %s", machine().describe_context(), buf);
	56	}
	57	}
	58
58	59	/***************************************************************************
59	60	MACHINE HARDWARE
60	61	***************************************************************************/
r21160	r21161
87	88	{
88	89	case S3C2440_GPIO_PORT_B :
89	90	{
90		verboselog( device->machine(), 5,  "LED %d %d %d %d\n", BIT( data, 5), BIT( data, 6), BIT( data, 7), BIT( data, 8));
	91	state->verboselog(5,  "LED %d %d %d %d\n", BIT( data, 5), BIT( data, 6), BIT( data, 7), BIT( data, 8));
91	92	}
92	93	break;
93	94	}
r21160	r21161
166	167	case 2 + 0 : data = state->m_penx->read(); break;
167	168	case 2 + 1 : data = 915 - state->m_peny->read() + 90; break;
168	169	}
169		verboselog( space.machine(), 5,  "s3c2440_adc_data_r %08X\n", data);
	170	state->verboselog(5,  "s3c2440_adc_data_r %08X\n", data);
170	171	return data;
171	172	}
172	173

trunk/src/mess/drivers/pc8801.c

r21160	r21161
484	484	DECLARE_READ8_MEMBER(opn_porta_r);
485	485	DECLARE_READ8_MEMBER(opn_portb_r);
486	486	IRQ_CALLBACK_MEMBER(pc8801_irq_callback);
	487	void pc8801_raise_irq(UINT8 irq,UINT8 state);
487	488	};
488	489
489	490
r21160	r21161
2268	2269	};
2269	2270
2270	2271	#ifdef USE_PROPER_I8214
2271		void pc8801_raise_irq(running_machine &machine,UINT8 irq,UINT8 state)
	2272	void pc8801_state::pc8801_raise_irq(UINT8 irq,UINT8 state)
2272	2273	{
2273		pc8801_state *drvstate = machine.driver_data<pc8801_state>();
2274	2274	if(state)
2275	2275	{
2276		drvstate->m_int_state |= irq;
	2276	drvm_int_state |= irq;
2277	2277
2278		drvstate->m_pic->r_w(~irq);
	2278	drvm_pic->r_w(~irq);
2279	2279
2280	2280	m_maincpu->set_input_line(0,ASSERT_LINE);
2281	2281	}
2282	2282	else
2283	2283	{
2284		//drvstate->m_int_state &= ~irq;
	2284	//drvm_int_state &= ~irq;
2285	2285
2286	2286	//m_maincpu->set_input_line(0,CLEAR_LINE);
2287	2287	}

trunk/src/mess/drivers/n64.c

r21160	r21161
25	25	DECLARE_MACHINE_START(n64dd);
26	26	INTERRUPT_GEN_MEMBER(n64_reset_poll);
27	27	DECLARE_DEVICE_IMAGE_LOAD_MEMBER(n64_cart);
	28	void mempak_format(UINT8* pak);
28	29	};
29	30
30	31	READ32_MEMBER(n64_mess_state::dd_null_r)
r21160	r21161
141	142	62500000            /* system clock */
142	143	};
143	144
144		static void mempak_format(UINT8* pak)
	145	void n64_mess_state::mempak_format(UINT8* pak)
145	146	{
146	147	unsigned char pak_header[] =
147	148	{

trunk/src/mess/drivers/ti990_10.c

r21160	r21161
90	90	virtual void video_start();
91	91	UINT32 screen_update_ti990_10(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
92	92	INTERRUPT_GEN_MEMBER(ti990_10_line_interrupt);
	93	void idle_callback(int state);
93	94	};
94	95
95	96
r21160	r21161
115	116	}
116	117
117	118	#ifdef UNUSED_FUNCTION
118		static void idle_callback(int state)
	119	void ti990_10_state::idle_callback(int state)
119	120	{
120	121	}
121	122	#endif

trunk/src/mess/drivers/scv.c

r21160	r21161
82	82	required_memory_region m_charrom;
83	83
84	84	void scv_set_banks();
	85	inline void plot_sprite_part( bitmap_ind16 &bitmap, UINT8 x, UINT8 y, UINT8 pat, UINT8 col, UINT8 screen_sprite_start_line );
	86	inline void draw_sprite( bitmap_ind16 &bitmap, UINT8 x, UINT8 y, UINT8 tile_idx, UINT8 col, UINT8 left, UINT8 right, UINT8 top, UINT8 bottom, UINT8 clip_y, UINT8 screen_sprite_start_line );
	87	inline void draw_text( bitmap_ind16 &bitmap, UINT8 x, UINT8 y, UINT8 *char_data, UINT8 fg, UINT8 bg );
	88	inline void draw_semi_graph( bitmap_ind16 &bitmap, UINT8 x, UINT8 y, UINT8 data, UINT8 fg );
	89	inline void draw_block_graph( bitmap_ind16 &bitmap, UINT8 x, UINT8 y, UINT8 col );
85	90	};
86	91
87	92
r21160	r21161
469	474	}
470	475
471	476
472		INLINE void plot_sprite_part( bitmap_ind16 &bitmap, UINT8 x, UINT8 y, UINT8 pat, UINT8 col, UINT8 screen_sprite_start_line )
	477	inline void scv_state::plot_sprite_part( bitmap_ind16 &bitmap, UINT8 x, UINT8 y, UINT8 pat, UINT8 col, UINT8 screen_sprite_start_line )
473	478	{
474	479	if ( x < 4 )
475	480	{
r21160	r21161
500	505	}
501	506
502	507
503		INLINE void draw_sprite( scv_state *state, bitmap_ind16 &bitmap, UINT8 x, UINT8 y, UINT8 tile_idx, UINT8 col, UINT8 left, UINT8 right, UINT8 top, UINT8 bottom, UINT8 clip_y, UINT8 screen_sprite_start_line )
	508	inline void scv_state::draw_sprite( bitmap_ind16 &bitmap, UINT8 x, UINT8 y, UINT8 tile_idx, UINT8 col, UINT8 left, UINT8 right, UINT8 top, UINT8 bottom, UINT8 clip_y, UINT8 screen_sprite_start_line )
504	509	{
505	510	int j;
506	511
507	512	y += clip_y * 2;
508	513	for ( j = clip_y * 4; j < 32; j += 4 )
509	514	{
510		UINT8 pat0 = state->m_videoram[ tile_idx * 32 + j + 0 ];
511		UINT8 pat1 = state->m_videoram[ tile_idx * 32 + j + 1 ];
512		UINT8 pat2 = state->m_videoram[ tile_idx * 32 + j + 2 ];
513		UINT8 pat3 = state->m_videoram[ tile_idx * 32 + j + 3 ];
	515	UINT8 pat0 = m_videoram[ tile_idx * 32 + j + 0 ];
	516	UINT8 pat1 = m_videoram[ tile_idx * 32 + j + 1 ];
	517	UINT8 pat2 = m_videoram[ tile_idx * 32 + j + 2 ];
	518	UINT8 pat3 = m_videoram[ tile_idx * 32 + j + 3 ];
514	519
515	520	if ( ( top && j < 16 ) || ( bottom && j >= 16 ) )
516	521	{
r21160	r21161
542	547	}
543	548
544	549
545		INLINE void draw_text( bitmap_ind16 &bitmap, UINT8 x, UINT8 y, UINT8 *char_data, UINT8 fg, UINT8 bg )
	550	inline void scv_state::draw_text( bitmap_ind16 &bitmap, UINT8 x, UINT8 y, UINT8 *char_data, UINT8 fg, UINT8 bg )
546	551	{
547	552	int i;
548	553
r21160	r21161
575	580	}
576	581
577	582
578		INLINE void draw_semi_graph( bitmap_ind16 &bitmap, UINT8 x, UINT8 y, UINT8 data, UINT8 fg )
	583	inline void scv_state::draw_semi_graph( bitmap_ind16 &bitmap, UINT8 x, UINT8 y, UINT8 data, UINT8 fg )
579	584	{
580	585	int i;
581	586
r21160	r21161
592	597	}
593	598
594	599
595		INLINE void draw_block_graph( bitmap_ind16 &bitmap, UINT8 x, UINT8 y, UINT8 col )
	600	inline void scv_state::draw_block_graph( bitmap_ind16 &bitmap, UINT8 x, UINT8 y, UINT8 col )
596	601	{
597	602	int i;
598	603
r21160	r21161
750	755	if ( ( m_videoram[0x1400] & 0x20 ) && ( i & 0x20 ) )
751	756	{
752	757	/* 2 color sprite handling */
753		draw_sprite( this, bitmap, spr_x, spr_y, tile_idx, col, left, right, top, bottom, clip, screen_start_sprite_line );
	758	draw_sprite( bitmap, spr_x, spr_y, tile_idx, col, left, right, top, bottom, clip, screen_start_sprite_line );
754	759	if ( x_32 || y_32 )
755	760	{
756	761	static const UINT8 spr_2col_lut0[16] = { 0, 15, 12, 13, 10, 11,  8, 9, 6, 7,  4,  5, 2, 3,  1,  1 };
757	762	static const UINT8 spr_2col_lut1[16] = { 0,  1,  8, 11,  2,  3, 10, 9, 4, 5, 12, 13, 6, 7, 14, 15 };
758	763
759		draw_sprite( this, bitmap, spr_x, spr_y, tile_idx ^ ( 8 * x_32 + y_32 ), ( i & 0x40 ) ? spr_2col_lut1[col] : spr_2col_lut0[col], left, right, top, bottom, clip, screen_start_sprite_line );
	764	draw_sprite( bitmap, spr_x, spr_y, tile_idx ^ ( 8 * x_32 + y_32 ), ( i & 0x40 ) ? spr_2col_lut1[col] : spr_2col_lut0[col], left, right, top, bottom, clip, screen_start_sprite_line );
760	765	}
761	766	}
762	767	else
763	768	{
764	769	/* regular sprite handling */
765		draw_sprite( this, bitmap, spr_x, spr_y, tile_idx, col, left, right, top, bottom, clip, screen_start_sprite_line );
	770	draw_sprite( bitmap, spr_x, spr_y, tile_idx, col, left, right, top, bottom, clip, screen_start_sprite_line );
766	771	if ( x_32 )
767	772	{
768		draw_sprite( this, bitmap, spr_x + 16, spr_y, tile_idx | 8, col, 1, 1, top, bottom, clip, screen_start_sprite_line );
	773	draw_sprite( bitmap, spr_x + 16, spr_y, tile_idx | 8, col, 1, 1, top, bottom, clip, screen_start_sprite_line );
769	774	}
770	775
771	776	if ( y_32 )
772	777	{
773	778	clip = ( clip & 0x08 ) ? ( clip & 0x07 ) : 0;
774		draw_sprite( this, bitmap, spr_x, spr_y + 16, tile_idx | 1, col, left, right, 1, 1, clip, screen_start_sprite_line );
	779	draw_sprite( bitmap, spr_x, spr_y + 16, tile_idx | 1, col, left, right, 1, 1, clip, screen_start_sprite_line );
775	780	if ( x_32 )
776	781	{
777		draw_sprite( this, bitmap, spr_x + 16, spr_y + 16, tile_idx | 9, col, 1, 1, 1, 1, clip, screen_start_sprite_line );
	782	draw_sprite( bitmap, spr_x + 16, spr_y + 16, tile_idx | 9, col, 1, 1, 1, 1, clip, screen_start_sprite_line );
778	783	}
779	784	}
780	785	}

trunk/src/mess/drivers/ptcsol.c

r21160	r21161
181	181	DECLARE_DRIVER_INIT(sol20);
182	182	TIMER_CALLBACK_MEMBER(sol20_cassette_tc);
183	183	TIMER_CALLBACK_MEMBER(sol20_boot);
	184	cassette_image_device *cassette_device_image();
184	185	};
185	186
186	187
187	188	/* timer to read cassette waveforms */
188	189
189	190
190		static cassette_image_device *cassette_device_image(running_machine &machine)
	191	cassette_image_device *sol20_state::cassette_device_image()
191	192	{
192		sol20_state *state = machine.driver_data<sol20_state>();
193		if (state->m_sol20_fa & 0x40)
194		return machine.device<cassette_image_device>(CASSETTE2_TAG);
	193	if (m_sol20_fa & 0x40)
	194	return machine().device<cassette_image_device>(CASSETTE2_TAG);
195	195	else
196		return machine.device<cassette_image_device>(CASSETTE_TAG);
	196	return machine().device<cassette_image_device>(CASSETTE_TAG);
197	197	}
198	198
199	199
r21160	r21161
210	210
211	211	m_cass_data.input.length++;
212	212
213		cass_ws = ((cassette_device_image(machine()))->input() > +0.02) ? 1 : 0;
	213	cass_ws = ((cassette_device_image())->input() > +0.02) ? 1 : 0;
214	214
215	215	if (cass_ws != m_cass_data.input.level)
216	216	{
r21160	r21161
239	239	if (!((m_cass_data.output.bit == 0) && (m_cass_data.output.length & 4)))
240	240	{
241	241	m_cass_data.output.level ^= 1;          // toggle output this, except on 2nd half of low bit
242		cassette_device_image(machine())->output(m_cass_data.output.level ? -1.0 : +1.0);
	242	cassette_device_image()->output(m_cass_data.output.level ? -1.0 : +1.0);
243	243	}
244	244	}
245	245	return;
r21160	r21161
248	248	/* loading a tape */
249	249	m_cass_data.input.length++;
250	250
251		cass_ws = ((cassette_device_image(machine()))->input() > +0.02) ? 1 : 0;
	251	cass_ws = ((cassette_device_image())->input() > +0.02) ? 1 : 0;
252	252
253	253	if (cass_ws != m_cass_data.input.level || m_cass_data.input.length == 10)
254	254	{
r21160	r21161
279	279	if (!((m_cass_data.output.bit == 0) && (m_cass_data.output.length & 8)))
280	280	{
281	281	m_cass_data.output.level ^= 1;          // toggle output this, except on 2nd half of low bit
282		cassette_device_image(machine())->output(m_cass_data.output.level ? -1.0 : +1.0);
	282	cassette_device_image()->output(m_cass_data.output.level ? -1.0 : +1.0);
283	283	}
284	284	}
285	285	return;

trunk/src/mess/drivers/gizmondo.c

r21160	r21161
36	36
37	37	#define VERBOSE_LEVEL ( 0 )
38	38
39		INLINE void ATTR_PRINTF(3,4) verboselog( running_machine &machine, int n_level, const char *s_fmt, ...)
40		{
41		if (VERBOSE_LEVEL >= n_level)
42		{
43		va_list v;
44		char buf[32768];
45		va_start( v, s_fmt);
46		vsprintf( buf, s_fmt, v);
47		va_end( v);
48		logerror( "%s: %s", machine.describe_context( ), buf);
49		}
50		}
51	39
52	40	#define BIT(x,n) (((x)>>(n))&1)
53	41	#define BITS(x,m,n) (((x)>>(n))&(((UINT32)1<<((m)-(n)+1))-1))
r21160	r21161
64	52	virtual void machine_start();
65	53	virtual void machine_reset();
66	54	DECLARE_INPUT_CHANGED_MEMBER(port_changed);
	55	inline void ATTR_PRINTF(3,4) verboselog( int n_level, const char *s_fmt, ...);
67	56	};
68	57
	58
	59	inline void ATTR_PRINTF(3,4) gizmondo_state::verboselog( int n_level, const char *s_fmt, ...)
	60	{
	61	if (VERBOSE_LEVEL >= n_level)
	62	{
	63	va_list v;
	64	char buf[32768];
	65	va_start( v, s_fmt);
	66	vsprintf( buf, s_fmt, v);
	67	va_end( v);
	68	logerror( "%s: %s", machine().describe_context( ), buf);
	69	}
	70	}
69	71	/*******************************************************************************
70	72	...
71	73	*******************************************************************************/

trunk/src/mess/drivers/pc9801.c

r21160	r21161
655	655
656	656	DECLARE_DRIVER_INIT(pc9801_kanji);
657	657	IRQ_CALLBACK_MEMBER(irq_callback);
	658	inline void set_dma_channel(int channel, int state);
658	659	};
659	660
660	661
r21160	r21161
3036	3037	program.write_byte(addr, data);
3037	3038	}
3038	3039
3039		static void set_dma_channel(running_machine &machine, int channel, int state)
	3040	void pc9801_state::set_dma_channel(int channel, int state)
3040	3041	{
3041		pc9801_state *drvstate = machine.driver_data<pc9801_state>();
3042		if (!state) drvstate->m_dack = channel;
	3042	if (!state) m_dack = channel;
3043	3043	}
3044	3044
3045		WRITE_LINE_MEMBER(pc9801_state::pc9801_dack0_w){ /*printf("%02x 0\n",state);*/ set_dma_channel(machine(), 0, state); }
3046		WRITE_LINE_MEMBER(pc9801_state::pc9801_dack1_w){ /*printf("%02x 1\n",state);*/ set_dma_channel(machine(), 1, state); }
3047		WRITE_LINE_MEMBER(pc9801_state::pc9801_dack2_w){ /*printf("%02x 2\n",state);*/ set_dma_channel(machine(), 2, state); }
3048		WRITE_LINE_MEMBER(pc9801_state::pc9801_dack3_w){ /*printf("%02x 3\n",state);*/ set_dma_channel(machine(), 3, state); }
	3045	WRITE_LINE_MEMBER(pc9801_state::pc9801_dack0_w){ /*printf("%02x 0\n",state);*/ set_dma_channel(0, state); }
	3046	WRITE_LINE_MEMBER(pc9801_state::pc9801_dack1_w){ /*printf("%02x 1\n",state);*/ set_dma_channel(1, state); }
	3047	WRITE_LINE_MEMBER(pc9801_state::pc9801_dack2_w){ /*printf("%02x 2\n",state);*/ set_dma_channel(2, state); }
	3048	WRITE_LINE_MEMBER(pc9801_state::pc9801_dack3_w){ /*printf("%02x 3\n",state);*/ set_dma_channel(3, state); }
3049	3049
3050	3050	READ8_MEMBER(pc9801_state::fdc_2hd_r)
3051	3051	{

trunk/src/mess/drivers/pockstat.c

r21160	r21161
127	127	TIMER_CALLBACK_MEMBER(timer_tick);
128	128	TIMER_CALLBACK_MEMBER(rtc_tick);
129	129	DECLARE_DEVICE_IMAGE_LOAD_MEMBER( pockstat_flash );
	130	inline void ATTR_PRINTF(3,4) verboselog( int n_level, const char *s_fmt, ... );
	131	UINT32 ps_intc_get_interrupt_line(UINT32 line);
	132	void ps_intc_set_interrupt_line(UINT32 line, int state);
	133	void ps_timer_start(int index);
130	134	};
131	135
132	136
r21160	r21161
157	161	#define ENABLE_VERBOSE_LOG  (0)
158	162
159	163	#if ENABLE_VERBOSE_LOG
160		INLINE void ATTR_PRINTF(3,4) verboselog( running_machine &machine, int n_level, const char *s_fmt, ... )
	164	inline void ATTR_PRINTF(3,4) pockstat_state::verboselog( int n_level, const char *s_fmt, ... )
161	165	{
162	166	if( VERBOSE_LEVEL >= n_level )
163	167	{
r21160	r21161
166	170	va_start( v, s_fmt );
167	171	vsprintf( buf, s_fmt, v );
168	172	va_end( v );
169		logerror( "%s: %s", machine.describe_context(), buf );
	173	logerror( "%s: %s", machine().describe_context(), buf );
170	174	}
171	175	}
172	176	#else
173	177	#define verboselog(x,y,z,...)
174	178	#endif
175	179
176
177		// Flash TLB
178
179
180
181		// Interrupt Controller
182		static UINT32 ps_intc_get_interrupt_line(running_machine &machine, UINT32 line);
183		static void ps_intc_set_interrupt_line(running_machine &machine, UINT32 line, int state);
184
185
186
187		// Timers
188
189		static void ps_timer_start(running_machine &machine, int index);
190
191
192
193		// Clock
194
195
196
197		// RTC
198
199
200
201
202	180	#define PS_INT_BTN_ACTION       0x00000001 // "Action button"
203	181	#define PS_INT_BTN_RIGHT        0x00000002 // "Right button"
204	182	#define PS_INT_BTN_LEFT         0x00000004 // "Left button"
r21160	r21161
222	200	switch(offset)
223	201	{
224	202	case 0x0000/4:
225		verboselog(machine(), 0, "ps_ftlb_r: FlashROM TLB Control = %08x & %08x\n", m_ftlb_regs.control, mem_mask );
	203	verboselog(0, "ps_ftlb_r: FlashROM TLB Control = %08x & %08x\n", m_ftlb_regs.control, mem_mask );
226	204	return m_ftlb_regs.control | 1; // ???
227	205	case 0x0004/4:
228		verboselog(machine(), 0, "ps_ftlb_r: Unknown (F_STAT) = %08x & %08x\n", m_ftlb_regs.stat, mem_mask );
	206	verboselog(0, "ps_ftlb_r: Unknown (F_STAT) = %08x & %08x\n", m_ftlb_regs.stat, mem_mask );
229	207	return m_ftlb_regs.stat;
230	208	case 0x0008/4:
231		verboselog(machine(), 0, "ps_ftlb_r: FlashROM TLB Valid Tag = %08x & %08x\n", m_ftlb_regs.valid, mem_mask );
	209	verboselog(0, "ps_ftlb_r: FlashROM TLB Valid Tag = %08x & %08x\n", m_ftlb_regs.valid, mem_mask );
232	210	return m_ftlb_regs.valid;
233	211	case 0x000c/4:
234		verboselog(machine(), 0, "ps_ftlb_r: Unknown (F_WAIT1) = %08x & %08x\n", m_ftlb_regs.wait1, mem_mask );
	212	verboselog(0, "ps_ftlb_r: Unknown (F_WAIT1) = %08x & %08x\n", m_ftlb_regs.wait1, mem_mask );
235	213	return m_ftlb_regs.wait1;
236	214	case 0x0010/4:
237		verboselog(machine(), 0, "ps_ftlb_r: Unknown (F_WAIT2) = %08x & %08x\n", m_ftlb_regs.wait2 | 0x04, mem_mask );
	215	verboselog(0, "ps_ftlb_r: Unknown (F_WAIT2) = %08x & %08x\n", m_ftlb_regs.wait2 | 0x04, mem_mask );
238	216	return m_ftlb_regs.wait2 | 0x04;
239	217	case 0x0100/4:
240	218	case 0x0104/4:
r21160	r21161
252	230	case 0x0134/4:
253	231	case 0x0138/4:
254	232	case 0x013c/4:
255		verboselog(machine(), 0, "ps_ftlb_r: FlashROM TLB Entry %d = %08x & %08x\n", offset - 0x100/4, m_ftlb_regs.entry[offset - 0x100/4], mem_mask );
	233	verboselog(0, "ps_ftlb_r: FlashROM TLB Entry %d = %08x & %08x\n", offset - 0x100/4, m_ftlb_regs.entry[offset - 0x100/4], mem_mask );
256	234	return m_ftlb_regs.entry[offset - 0x100/4];
257	235	case 0x0300/4:
258		verboselog(machine(), 0, "ps_ftlb_r: Unknown (F_SN) = %08x & %08x\n", m_ftlb_regs.serial, mem_mask );
	236	verboselog(0, "ps_ftlb_r: Unknown (F_SN) = %08x & %08x\n", m_ftlb_regs.serial, mem_mask );
259	237	return m_ftlb_regs.serial;
260	238	default:
261		verboselog(machine(), 0, "ps_ftlb_r: Unknown Register %08x & %08x\n", 0x06000000 + (offset << 2), mem_mask );
	239	verboselog(0, "ps_ftlb_r: Unknown Register %08x & %08x\n", 0x06000000 + (offset << 2), mem_mask );
262	240	break;
263	241	}
264	242	return 0;
r21160	r21161
269	247	switch(offset)
270	248	{
271	249	case 0x0000/4:
272		verboselog(machine(), 0, "ps_ftlb_w: FlashROM TLB Control = %08x & %08x\n", data, mem_mask );
	250	verboselog(0, "ps_ftlb_w: FlashROM TLB Control = %08x & %08x\n", data, mem_mask );
273	251	COMBINE_DATA(&m_ftlb_regs.control);
274	252	break;
275	253	case 0x0004/4:
276		verboselog(machine(), 0, "ps_ftlb_w: Unknown (F_STAT) = %08x & %08x\n", data, mem_mask );
	254	verboselog(0, "ps_ftlb_w: Unknown (F_STAT) = %08x & %08x\n", data, mem_mask );
277	255	COMBINE_DATA(&m_ftlb_regs.stat);
278	256	break;
279	257	case 0x0008/4:
280		verboselog(machine(), 0, "ps_ftlb_w: FlashROM TLB Valid Tag = %08x & %08x\n", data, mem_mask );
	258	verboselog(0, "ps_ftlb_w: FlashROM TLB Valid Tag = %08x & %08x\n", data, mem_mask );
281	259	COMBINE_DATA(&m_ftlb_regs.valid);
282	260	break;
283	261	case 0x000c/4:
284		verboselog(machine(), 0, "ps_ftlb_w: Unknown (F_WAIT1) = %08x & %08x\n", data, mem_mask );
	262	verboselog(0, "ps_ftlb_w: Unknown (F_WAIT1) = %08x & %08x\n", data, mem_mask );
285	263	COMBINE_DATA(&m_ftlb_regs.wait1);
286	264	break;
287	265	case 0x0010/4:
288		verboselog(machine(), 0, "ps_ftlb_w: Unknown (F_WAIT2) = %08x & %08x\n", data, mem_mask );
	266	verboselog(0, "ps_ftlb_w: Unknown (F_WAIT2) = %08x & %08x\n", data, mem_mask );
289	267	COMBINE_DATA(&m_ftlb_regs.wait2);
290	268	break;
291	269	case 0x0100/4:
r21160	r21161
304	282	case 0x0134/4:
305	283	case 0x0138/4:
306	284	case 0x013c/4:
307		verboselog(machine(), 0, "ps_ftlb_w: FlashROM TLB Entry %d = %08x & %08x\n", offset - 0x100/4, data, mem_mask );
	285	verboselog(0, "ps_ftlb_w: FlashROM TLB Entry %d = %08x & %08x\n", offset - 0x100/4, data, mem_mask );
308	286	COMBINE_DATA(&m_ftlb_regs.entry[offset - 0x100/4]);
309	287	break;
310	288	case 0x0300/4:
311		verboselog(machine(), 0, "ps_ftlb_w: Unknown (F_SN) = %08x & %08x\n", data, mem_mask );
	289	verboselog(0, "ps_ftlb_w: Unknown (F_SN) = %08x & %08x\n", data, mem_mask );
312	290	COMBINE_DATA(&m_ftlb_regs.serial);
313	291	break;
314	292	default:
315		verboselog(machine(), 0, "ps_ftlb_w: Unknown Register %08x = %08x & %08x\n", 0x06000000 + (offset << 2), data, mem_mask );
	293	verboselog(0, "ps_ftlb_w: Unknown Register %08x = %08x & %08x\n", 0x06000000 + (offset << 2), data, mem_mask );
316	294	break;
317	295	}
318	296	}
319	297
320		static UINT32 ps_intc_get_interrupt_line(running_machine &machine, UINT32 line)
	298	UINT32 pockstat_state::ps_intc_get_interrupt_line(UINT32 line)
321	299	{
322		pockstat_state *state = machine.driver_data<pockstat_state>();
323		return state->m_intc_regs.status & line;
	300	return m_intc_regs.status & line;
324	301	}
325	302
326		static void ps_intc_set_interrupt_line(running_machine &machine, UINT32 line, int state)
	303	void pockstat_state::ps_intc_set_interrupt_line(UINT32 line, int state)
327	304	{
328		pockstat_state *drvstate = machine.driver_data<pockstat_state>();
329		//printf( "%08x %d %08x %08x %08x\n", line, state, drvstate->m_intc_regs.hold, drvstate->m_intc_regs.status, drvstate->m_intc_regs.enable );
	305	//printf( "%08x %d %08x %08x %08x\n", line, state, drvm_intc_regs.hold, drvm_intc_regs.status, drvm_intc_regs.enable );
330	306	if(line)
331	307	{
332	308	if(state)
333	309	{
334		drvstate->m_intc_regs.status |= line & PS_INT_STATUS_MASK;
335		drvstate->m_intc_regs.hold |= line &~ PS_INT_STATUS_MASK;
336		//printf( " Setting %08x, status = %08x, hold = %08x\n", line, drvstate->m_intc_regs.status, drvstate->m_intc_regs.hold );
	310	m_intc_regs.status |= line & PS_INT_STATUS_MASK;
	311	m_intc_regs.hold |= line &~ PS_INT_STATUS_MASK;
	312	//printf( " Setting %08x, status = %08x, hold = %08x\n", line, m_intc_regs.status, m_intc_regs.hold );
337	313	}
338	314	else
339	315	{
340		drvstate->m_intc_regs.status &= ~line;
341		drvstate->m_intc_regs.hold &= ~line;
342		//printf( "Clearing %08x, status = %08x, hold = %08x\n", line, drvstate->m_intc_regs.status, drvstate->m_intc_regs.hold );
	316	m_intc_regs.status &= ~line;
	317	m_intc_regs.hold &= ~line;
	318	//printf( "Clearing %08x, status = %08x, hold = %08x\n", line, m_intc_regs.status, m_intc_regs.hold );
343	319	}
344	320	}
345		if(drvstate->m_intc_regs.hold & drvstate->m_intc_regs.enable & PS_INT_IRQ_MASK)
	321	if(m_intc_regs.hold & m_intc_regs.enable & PS_INT_IRQ_MASK)
346	322	{
347		machine.device("maincpu")->execute().set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
	323	machine().device("maincpu")->execute().set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
348	324	}
349	325	else
350	326	{
351		machine.device("maincpu")->execute().set_input_line(ARM7_IRQ_LINE, CLEAR_LINE);
	327	machine().device("maincpu")->execute().set_input_line(ARM7_IRQ_LINE, CLEAR_LINE);
352	328	}
353		if(drvstate->m_intc_regs.hold & drvstate->m_intc_regs.enable & PS_INT_FIQ_MASK)
	329	if(m_intc_regs.hold & m_intc_regs.enable & PS_INT_FIQ_MASK)
354	330	{
355		machine.device("maincpu")->execute().set_input_line(ARM7_FIRQ_LINE, ASSERT_LINE);
	331	machine().device("maincpu")->execute().set_input_line(ARM7_FIRQ_LINE, ASSERT_LINE);
356	332	}
357	333	else
358	334	{
359		machine.device("maincpu")->execute().set_input_line(ARM7_FIRQ_LINE, CLEAR_LINE);
	335	machine().device("maincpu")->execute().set_input_line(ARM7_FIRQ_LINE, CLEAR_LINE);
360	336	}
361	337	}
362	338
r21160	r21161
365	341	switch(offset)
366	342	{
367	343	case 0x0000/4:
368		verboselog(machine(), 0, "ps_intc_r: Held Interrupt = %08x & %08x\n", m_intc_regs.hold, mem_mask );
	344	verboselog(0, "ps_intc_r: Held Interrupt = %08x & %08x\n", m_intc_regs.hold, mem_mask );
369	345	return m_intc_regs.hold;
370	346	case 0x0004/4:
371		verboselog(machine(), 0, "ps_intc_r: Interrupt Status = %08x & %08x\n", m_intc_regs.status, mem_mask );
	347	verboselog(0, "ps_intc_r: Interrupt Status = %08x & %08x\n", m_intc_regs.status, mem_mask );
372	348	return m_intc_regs.status;
373	349	case 0x0008/4:
374		verboselog(machine(), 0, "ps_intc_r: Interrupt Enable = %08x & %08x\n", m_intc_regs.enable, mem_mask );
	350	verboselog(0, "ps_intc_r: Interrupt Enable = %08x & %08x\n", m_intc_regs.enable, mem_mask );
375	351	return m_intc_regs.enable;
376	352	case 0x000c/4:
377		verboselog(machine(), 0, "ps_intc_r: Interrupt Mask (Invalid Read) = %08x & %08x\n", 0, mem_mask );
	353	verboselog(0, "ps_intc_r: Interrupt Mask (Invalid Read) = %08x & %08x\n", 0, mem_mask );
378	354	return 0;
379	355	case 0x0010/4:
380		verboselog(machine(), 0, "ps_intc_r: Interrupt Acknowledge (Invalid Read) = %08x & %08x\n", 0, mem_mask );
	356	verboselog(0, "ps_intc_r: Interrupt Acknowledge (Invalid Read) = %08x & %08x\n", 0, mem_mask );
381	357	return 0;
382	358	default:
383		verboselog(machine(), 0, "ps_intc_r: Unknown Register %08x & %08x\n", 0x0a000000 + (offset << 2), mem_mask );
	359	verboselog(0, "ps_intc_r: Unknown Register %08x & %08x\n", 0x0a000000 + (offset << 2), mem_mask );
384	360	break;
385	361	}
386	362	return 0;
r21160	r21161
391	367	switch(offset)
392	368	{
393	369	case 0x0000/4:
394		verboselog(machine(), 0, "ps_intc_w: Held Interrupt (Invalid Write) = %08x & %08x\n", data, mem_mask );
	370	verboselog(0, "ps_intc_w: Held Interrupt (Invalid Write) = %08x & %08x\n", data, mem_mask );
395	371	break;
396	372	case 0x0004/4:
397		verboselog(machine(), 0, "ps_intc_w: Interrupt Status (Invalid Write) = %08x & %08x\n", data, mem_mask );
	373	verboselog(0, "ps_intc_w: Interrupt Status (Invalid Write) = %08x & %08x\n", data, mem_mask );
398	374	break;
399	375	case 0x0008/4:
400		verboselog(machine(), 0, "ps_intc_w: Interrupt Enable = %08x & %08x\n", data, mem_mask );
	376	verboselog(0, "ps_intc_w: Interrupt Enable = %08x & %08x\n", data, mem_mask );
401	377	m_intc_regs.enable |= data;
402	378	//COMBINE_DATA(&m_intc_regs.enable);
403	379	//m_intc_regs.status &= m_intc_regs.enable;
404	380	//m_intc_regs.hold &= m_intc_regs.enable;
405		ps_intc_set_interrupt_line(machine(), 0, 0);
	381	ps_intc_set_interrupt_line(0, 0);
406	382	break;
407	383	case 0x000c/4:
408		verboselog(machine(), 0, "ps_intc_w: Interrupt Mask = %08x & %08x\n", data, mem_mask );
	384	verboselog(0, "ps_intc_w: Interrupt Mask = %08x & %08x\n", data, mem_mask );
409	385	m_intc_regs.enable &= ~data;
410	386	COMBINE_DATA(&m_intc_regs.mask);
411	387	//m_intc_regs.status &= m_intc_regs.enable;
412	388	//m_intc_regs.hold &= m_intc_regs.enable;
413		ps_intc_set_interrupt_line(machine(), 0, 0);
	389	ps_intc_set_interrupt_line(0, 0);
414	390	break;
415	391	case 0x0010/4:
416		verboselog(machine(), 0, "ps_intc_w: Interrupt Acknowledge = %08x & %08x\n", data, mem_mask );
	392	verboselog(0, "ps_intc_w: Interrupt Acknowledge = %08x & %08x\n", data, mem_mask );
417	393	m_intc_regs.hold &= ~data;
418	394	m_intc_regs.status &= ~data;
419		ps_intc_set_interrupt_line(machine(), 0, 0);
	395	ps_intc_set_interrupt_line(0, 0);
420	396	//COMBINE_DATA(&m_intc_regs.acknowledge);
421	397	break;
422	398	default:
423		verboselog(machine(), 0, "ps_intc_w: Unknown Register %08x = %08x & %08x\n", 0x0a000000 + (offset << 2), data, mem_mask );
	399	verboselog(0, "ps_intc_w: Unknown Register %08x = %08x & %08x\n", 0x0a000000 + (offset << 2), data, mem_mask );
424	400	break;
425	401	}
426	402	}
427	403
428	404	TIMER_CALLBACK_MEMBER(pockstat_state::timer_tick)
429	405	{
430		ps_intc_set_interrupt_line(machine(), param == 2 ? PS_INT_TIMER2 : (param == 1 ? PS_INT_TIMER1 : PS_INT_TIMER0), 1);
	406	ps_intc_set_interrupt_line(param == 2 ? PS_INT_TIMER2 : (param == 1 ? PS_INT_TIMER1 : PS_INT_TIMER0), 1);
431	407	//printf( "Timer %d is calling back\n", param );
432	408	m_timer_regs.timer[param].count = m_timer_regs.timer[param].period;
433		ps_timer_start(machine(), param);
	409	ps_timer_start(param);
434	410	}
435	411
436		static void ps_timer_start(running_machine &machine, int index)
	412	void pockstat_state::ps_timer_start(int index)
437	413	{
438		pockstat_state *state = machine.driver_data<pockstat_state>();
439	414	int divisor = 1;
440	415	attotime period;
441		switch(state->m_timer_regs.timer[index].control & 3)
	416	switch(m_timer_regs.timer[index].control & 3)
442	417	{
443	418	case 0:
444	419	case 3:
r21160	r21161
451	426	divisor = 256;
452	427	break;
453	428	}
454		period = attotime::from_hz(CPU_FREQ[state->m_clock_regs.mode & 0x0f] / 2) * divisor;
455		period = period * state->m_timer_regs.timer[index].count;
456		state->m_timer_regs.timer[index].timer->adjust(period, index);
	429	period = attotime::from_hz(CPU_FREQ[m_clock_regs.mode & 0x0f] / 2) * divisor;
	430	period = period * m_timer_regs.timer[index].count;
	431	m_timer_regs.timer[index].timer->adjust(period, index);
457	432	}
458	433
459	434	READ32_MEMBER(pockstat_state::ps_timer_r)
r21160	r21161
463	438	case 0x0000/4:
464	439	case 0x0010/4:
465	440	case 0x0020/4:
466		verboselog(machine(), 0, "ps_timer_r: Timer %d Period = %08x & %08x\n", offset / (0x10/4), m_timer_regs.timer[offset / (0x10/4)].period, mem_mask );
	441	verboselog(0, "ps_timer_r: Timer %d Period = %08x & %08x\n", offset / (0x10/4), m_timer_regs.timer[offset / (0x10/4)].period, mem_mask );
467	442	return m_timer_regs.timer[offset / (0x10/4)].period;
468	443	case 0x0004/4:
469	444	case 0x0014/4:
470	445	case 0x0024/4:
471		verboselog(machine(), 0, "ps_timer_r: Timer %d Count = %08x & %08x\n", offset / (0x10/4), m_timer_regs.timer[offset / (0x10/4)].count, mem_mask );
	446	verboselog(0, "ps_timer_r: Timer %d Count = %08x & %08x\n", offset / (0x10/4), m_timer_regs.timer[offset / (0x10/4)].count, mem_mask );
472	447	if(m_timer_regs.timer[offset / (0x10/4)].control & 4)
473	448	{
474	449	m_timer_regs.timer[offset / (0x10/4)].count--;
r21160	r21161
482	457	case 0x0008/4:
483	458	case 0x0018/4:
484	459	case 0x0028/4:
485		verboselog(machine(), 0, "ps_timer_r: Timer %d Control = %08x & %08x\n", offset / (0x10/4), m_timer_regs.timer[offset / (0x10/4)].control, mem_mask );
	460	verboselog(0, "ps_timer_r: Timer %d Control = %08x & %08x\n", offset / (0x10/4), m_timer_regs.timer[offset / (0x10/4)].control, mem_mask );
486	461	return m_timer_regs.timer[offset / (0x10/4)].control;
487	462	default:
488		verboselog(machine(), 0, "ps_timer_r: Unknown Register %08x & %08x\n", 0x0a800000 + (offset << 2), mem_mask );
	463	verboselog(0, "ps_timer_r: Unknown Register %08x & %08x\n", 0x0a800000 + (offset << 2), mem_mask );
489	464	break;
490	465	}
491	466	return 0;
r21160	r21161
498	473	case 0x0000/4:
499	474	case 0x0010/4:
500	475	case 0x0020/4:
501		verboselog(machine(), 0, "ps_timer_w: Timer %d Period = %08x & %08x\n", offset / (0x10/4), data, mem_mask );
	476	verboselog(0, "ps_timer_w: Timer %d Period = %08x & %08x\n", offset / (0x10/4), data, mem_mask );
502	477	COMBINE_DATA(&m_timer_regs.timer[offset / (0x10/4)].period);
503	478	break;
504	479	case 0x0004/4:
505	480	case 0x0014/4:
506	481	case 0x0024/4:
507		verboselog(machine(), 0, "ps_timer_w: Timer %d Count = %08x & %08x\n", offset / (0x10/4), data, mem_mask );
	482	verboselog(0, "ps_timer_w: Timer %d Count = %08x & %08x\n", offset / (0x10/4), data, mem_mask );
508	483	COMBINE_DATA(&m_timer_regs.timer[offset / (0x10/4)].count);
509	484	break;
510	485	case 0x0008/4:
511	486	case 0x0018/4:
512	487	case 0x0028/4:
513		verboselog(machine(), 0, "ps_timer_w: Timer %d Control = %08x & %08x\n", offset / (0x10/4), data, mem_mask );
	488	verboselog(0, "ps_timer_w: Timer %d Control = %08x & %08x\n", offset / (0x10/4), data, mem_mask );
514	489	COMBINE_DATA(&m_timer_regs.timer[offset / (0x10/4)].control);
515	490	if(m_timer_regs.timer[offset / (0x10/4)].control & 4)
516	491	{
517		ps_timer_start(machine(), offset / (0x10/4));
	492	ps_timer_start(offset / (0x10/4));
518	493	}
519	494	else
520	495	{
r21160	r21161
522	497	}
523	498	break;
524	499	default:
525		verboselog(machine(), 0, "ps_timer_w: Unknown Register %08x = %08x & %08x\n", 0x0a800000 + (offset << 2), data, mem_mask );
	500	verboselog(0, "ps_timer_w: Unknown Register %08x = %08x & %08x\n", 0x0a800000 + (offset << 2), data, mem_mask );
526	501	break;
527	502	}
528	503	}
r21160	r21161
532	507	switch(offset)
533	508	{
534	509	case 0x0000/4:
535		verboselog(machine(), 0, "ps_clock_r: Clock Mode = %08x & %08x\n", m_clock_regs.mode | 0x10, mem_mask );
	510	verboselog(0, "ps_clock_r: Clock Mode = %08x & %08x\n", m_clock_regs.mode | 0x10, mem_mask );
536	511	return m_clock_regs.mode | PS_CLOCK_STEADY;
537	512	case 0x0004/4:
538		verboselog(machine(), 0, "ps_clock_r: Clock Control = %08x & %08x\n", m_clock_regs.control, mem_mask );
	513	verboselog(0, "ps_clock_r: Clock Control = %08x & %08x\n", m_clock_regs.control, mem_mask );
539	514	return m_clock_regs.control;
540	515	default:
541		verboselog(machine(), 0, "ps_clock_r: Unknown Register %08x & %08x\n", 0x0b000000 + (offset << 2), mem_mask );
	516	verboselog(0, "ps_clock_r: Unknown Register %08x & %08x\n", 0x0b000000 + (offset << 2), mem_mask );
542	517	break;
543	518	}
544	519	return 0;
r21160	r21161
549	524	switch(offset)
550	525	{
551	526	case 0x0000/4:
552		verboselog(machine(), 0, "ps_clock_w: Clock Mode = %08x & %08x\n", data, mem_mask );
	527	verboselog(0, "ps_clock_w: Clock Mode = %08x & %08x\n", data, mem_mask );
553	528	COMBINE_DATA(&m_clock_regs.mode);
554	529	machine().device("maincpu")->set_unscaled_clock(CPU_FREQ[m_clock_regs.mode & 0x0f]);
555	530	break;
556	531	case 0x0004/4:
557		verboselog(machine(), 0, "ps_clock_w: Clock Control = %08x & %08x\n", data, mem_mask );
	532	verboselog(0, "ps_clock_w: Clock Control = %08x & %08x\n", data, mem_mask );
558	533	COMBINE_DATA(&m_clock_regs.control);
559	534	break;
560	535	default:
561		verboselog(machine(), 0, "ps_clock_w: Unknown Register %08x = %08x & %08x\n", 0x0b000000 + (offset << 2), data, mem_mask );
	536	verboselog(0, "ps_clock_w: Unknown Register %08x = %08x & %08x\n", 0x0b000000 + (offset << 2), data, mem_mask );
562	537	break;
563	538	}
564	539	}
r21160	r21161
566	541	TIMER_CALLBACK_MEMBER(pockstat_state::rtc_tick)
567	542	{
568	543	//printf( "RTC is calling back\n" );
569		ps_intc_set_interrupt_line(machine(), PS_INT_RTC, ps_intc_get_interrupt_line(machine(), PS_INT_RTC) ? 0 : 1);
	544	ps_intc_set_interrupt_line(PS_INT_RTC, ps_intc_get_interrupt_line(PS_INT_RTC) ? 0 : 1);
570	545	if(!(m_rtc_regs.mode & 1))
571	546	{
572	547	m_rtc_regs.time++;
r21160	r21161
614	589	switch(offset)
615	590	{
616	591	case 0x0000/4:
617		verboselog(machine(), 0, "ps_rtc_r: RTC Mode = %08x & %08x\n", m_rtc_regs.mode, mem_mask );
	592	verboselog(0, "ps_rtc_r: RTC Mode = %08x & %08x\n", m_rtc_regs.mode, mem_mask );
618	593	return m_rtc_regs.mode;
619	594	case 0x0004/4:
620		verboselog(machine(), 0, "ps_rtc_r: RTC Control = %08x & %08x\n", m_rtc_regs.control, mem_mask );
	595	verboselog(0, "ps_rtc_r: RTC Control = %08x & %08x\n", m_rtc_regs.control, mem_mask );
621	596	return m_rtc_regs.control;
622	597	case 0x0008/4:
623		verboselog(machine(), 0, "ps_rtc_r: RTC Time = %08x & %08x\n", m_rtc_regs.time, mem_mask );
	598	verboselog(0, "ps_rtc_r: RTC Time = %08x & %08x\n", m_rtc_regs.time, mem_mask );
624	599	return m_rtc_regs.time;
625	600	case 0x000c/4:
626		verboselog(machine(), 0, "ps_rtc_r: RTC Date = %08x & %08x\n", m_rtc_regs.date, mem_mask );
	601	verboselog(0, "ps_rtc_r: RTC Date = %08x & %08x\n", m_rtc_regs.date, mem_mask );
627	602	return m_rtc_regs.date;
628	603	default:
629		verboselog(machine(), 0, "ps_rtc_r: Unknown Register %08x & %08x\n", 0x0b800000 + (offset << 2), mem_mask );
	604	verboselog(0, "ps_rtc_r: Unknown Register %08x & %08x\n", 0x0b800000 + (offset << 2), mem_mask );
630	605	break;
631	606	}
632	607	return 0;
r21160	r21161
637	612	switch(offset)
638	613	{
639	614	case 0x0000/4:
640		verboselog(machine(), 0, "ps_rtc_w: RTC Mode = %08x & %08x\n", data, mem_mask );
	615	verboselog(0, "ps_rtc_w: RTC Mode = %08x & %08x\n", data, mem_mask );
641	616	COMBINE_DATA(&m_rtc_regs.mode);
642	617	break;
643	618	case 0x0004/4:
644		verboselog(machine(), 0, "ps_rtc_w: RTC Control = %08x & %08x\n", data, mem_mask );
	619	verboselog(0, "ps_rtc_w: RTC Control = %08x & %08x\n", data, mem_mask );
645	620	if(m_rtc_regs.control == 1 && data == 1)
646	621	{
647	622	switch(m_rtc_regs.mode >> 1)
r21160	r21161
738	713	}
739	714	break;
740	715	default:
741		verboselog(machine(), 0, "ps_rtc_w: Unknown Register %08x = %08x & %08x\n", 0x0b800000 + (offset << 2), data, mem_mask );
	716	verboselog(0, "ps_rtc_w: Unknown Register %08x = %08x & %08x\n", 0x0b800000 + (offset << 2), data, mem_mask );
742	717	break;
743	718	}
744	719	}
r21160	r21161
749	724	switch(offset)
750	725	{
751	726	case 0x0000/4:
752		verboselog(machine(), 0, "ps_lcd_r: LCD Control = %08x & %08x\n", m_lcd_control | 0x100, mem_mask );
	727	verboselog(0, "ps_lcd_r: LCD Control = %08x & %08x\n", m_lcd_control | 0x100, mem_mask );
753	728	return m_lcd_control;
754	729	default:
755		verboselog(machine(), 0, "ps_lcd_r: Unknown Register %08x & %08x\n", 0x0d000000 + (offset << 2), mem_mask );
	730	verboselog(0, "ps_lcd_r: Unknown Register %08x & %08x\n", 0x0d000000 + (offset << 2), mem_mask );
756	731	break;
757	732	}
758	733	return 0;
r21160	r21161
763	738	switch(offset)
764	739	{
765	740	case 0x0000/4:
766		verboselog(machine(), 0, "ps_lcd_w: LCD Control = %08x & %08x\n", data, mem_mask );
	741	verboselog(0, "ps_lcd_w: LCD Control = %08x & %08x\n", data, mem_mask );
767	742	COMBINE_DATA(&m_lcd_control);
768	743	break;
769	744	default:
770		verboselog(machine(), 0, "ps_lcd_w: Unknown Register %08x = %08x & %08x\n", 0x0d000000 + (offset << 2), data, mem_mask );
	745	verboselog(0, "ps_lcd_w: Unknown Register %08x = %08x & %08x\n", 0x0d000000 + (offset << 2), data, mem_mask );
771	746	break;
772	747	}
773	748	}
r21160	r21161
776	751	{
777	752	UINT32 buttons = machine().root_device().ioport("BUTTONS")->read();
778	753
779		ps_intc_set_interrupt_line(machine(), PS_INT_BTN_ACTION, (buttons &  1) ? 1 : 0);
780		ps_intc_set_interrupt_line(machine(), PS_INT_BTN_RIGHT, (buttons &  2) ? 1 : 0);
781		ps_intc_set_interrupt_line(machine(), PS_INT_BTN_LEFT,  (buttons &  4) ? 1 : 0);
782		ps_intc_set_interrupt_line(machine(), PS_INT_BTN_DOWN,  (buttons &  8) ? 1 : 0);
783		ps_intc_set_interrupt_line(machine(), PS_INT_BTN_UP,    (buttons & 16) ? 1 : 0);
	754	ps_intc_set_interrupt_line(PS_INT_BTN_ACTION, (buttons &  1) ? 1 : 0);
	755	ps_intc_set_interrupt_line(PS_INT_BTN_RIGHT, (buttons &  2) ? 1 : 0);
	756	ps_intc_set_interrupt_line(PS_INT_BTN_LEFT,  (buttons &  4) ? 1 : 0);
	757	ps_intc_set_interrupt_line(PS_INT_BTN_DOWN,  (buttons &  8) ? 1 : 0);
	758	ps_intc_set_interrupt_line(PS_INT_BTN_UP,    (buttons & 16) ? 1 : 0);
784	759	}
785	760
786	761	READ32_MEMBER(pockstat_state::ps_rombank_r)
r21160	r21161
830	805
831	806	READ32_MEMBER(pockstat_state::ps_audio_r)
832	807	{
833		verboselog(machine(), 0, "ps_audio_r: Unknown Read: %08x = %08x & %08x\n", 0xd800000 + (offset << 2), 0x10, mem_mask);
	808	verboselog(0, "ps_audio_r: Unknown Read: %08x = %08x & %08x\n", 0xd800000 + (offset << 2), 0x10, mem_mask);
834	809	return 0;
835	810	}
836	811
837	812	WRITE32_MEMBER(pockstat_state::ps_audio_w)
838	813	{
839		verboselog(machine(), 0, "ps_audio_w: Unknown Write: %08x = %08x & %08x\n", 0xd800000 + (offset << 2), data, mem_mask);
	814	verboselog(0, "ps_audio_w: Unknown Write: %08x = %08x & %08x\n", 0xd800000 + (offset << 2), data, mem_mask);
840	815	}
841	816
842	817	WRITE32_MEMBER(pockstat_state::ps_dac_w)

trunk/src/mess/drivers/pasopia7.c

r21160	r21161
116	116
117	117	void fdc_irq(bool state);
118	118	TIMER_CALLBACK_MEMBER(pio_timer);
	119	void draw_cg4_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int width);
	120	void draw_tv_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int width);
	121	void draw_mixed_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int width);
119	122	};
120	123
121	124	#define VDP_CLOCK XTAL_3_579545MHz/4
r21160	r21161
132	135	m_p7_pal = auto_alloc_array(machine(), UINT8, 0x10);
133	136	}
134	137
135		static void draw_cg4_screen(running_machine &machine, bitmap_ind16 &bitmap,const rectangle &cliprect,int width)
	138	void pasopia7_state::draw_cg4_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int width)
136	139	{
137		UINT8 *vram = machine.root_device().memregion("vram")->base();
	140	UINT8 *vram = machine().root_device().memregion("vram")->base();
138	141	int x,y,xi,yi;
139	142	int count;
140	143
r21160	r21161
155	158
156	159	color =  pen_g<<2 | pen_r<<1 | pen_b<<0;
157	160
158		bitmap.pix16(y+yi, x+xi) = machine.pens[color];
	161	bitmap.pix16(y+yi, x+xi) = machine().pens[color];
159	162	}
160	163	count+=8;
161	164	}
r21160	r21161
163	166	}
164	167	}
165	168
166		static void draw_tv_screen(running_machine &machine, bitmap_ind16 &bitmap,const rectangle &cliprect,int width)
	169	void pasopia7_state::draw_tv_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int width)
167	170	{
168		pasopia7_state *state = machine.driver_data<pasopia7_state>();
169		UINT8 *vram = machine.root_device().memregion("vram")->base();
170		UINT8 *gfx_data = state->memregion("font")->base();
	171	UINT8 *vram = machine().root_device().memregion("vram")->base();
	172	UINT8 *gfx_data = memregion("font")->base();
171	173	int x,y,xi,yi;
172	174	int count;
173	175
r21160	r21161
188	190	int pen;
189	191	pen = ((gfx_data[tile*8+yi]>>(7-xi)) & 1) ? color : 0;
190	192
191		bitmap.pix16(y*8+yi, x*8+xi) = machine.pens[pen];
	193	bitmap.pix16(y*8+yi, x*8+xi) = machine().pens[pen];
192	194	}
193	195	}
194	196
195	197	// draw cursor
196		if(state->m_cursor_addr*8 == count)
	198	if(m_cursor_addr*8 == count)
197	199	{
198	200	int xc,yc,cursor_on;
199	201
200	202	cursor_on = 0;
201		switch(state->m_cursor_raster & 0x60)
	203	switch(m_cursor_raster & 0x60)
202	204	{
203	205	case 0x00: cursor_on = 1; break; //always on
204	206	case 0x20: cursor_on = 0; break; //always off
205		case 0x40: if(machine.primary_screen->frame_number() & 0x10) { cursor_on = 1; } break; //fast blink
206		case 0x60: if(machine.primary_screen->frame_number() & 0x20) { cursor_on = 1; } break; //slow blink
	207	case 0x40: if(machine().primary_screen->frame_number() & 0x10) { cursor_on = 1; } break; //fast blink
	208	case 0x60: if(machine().primary_screen->frame_number() & 0x20) { cursor_on = 1; } break; //slow blink
207	209	}
208	210
209	211	if(cursor_on)
210	212	{
211		for(yc=0;yc<(8-(state->m_cursor_raster & 7));yc++)
	213	for(yc=0;yc<(8-(m_cursor_raster & 7));yc++)
212	214	{
213	215	for(xc=0;xc<8;xc++)
214	216	{
215		bitmap.pix16(y*8-yc+7, x*8+xc) = machine.pens[7];
	217	bitmap.pix16(y*8-yc+7, x*8+xc) = machine().pens[7];
216	218	}
217	219	}
218	220	}
r21160	r21161
222	224	}
223	225	}
224	226
225		static void draw_mixed_screen(running_machine &machine, bitmap_ind16 &bitmap,const rectangle &cliprect,int width)
	227	void pasopia7_state::draw_mixed_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int width)
226	228	{
227		pasopia7_state *state = machine.driver_data<pasopia7_state>();
228		UINT8 *vram = machine.root_device().memregion("vram")->base();
229		UINT8 *gfx_data = state->memregion("font")->base();
	229	UINT8 *vram = machine().root_device().memregion("vram")->base();
	230	UINT8 *gfx_data = memregion("font")->base();
230	231	int x,y,xi,yi;
231	232	int count;
232	233
r21160	r21161
254	255
255	256	pen =  pen_g<<2 | pen_r<<1 | pen_b<<0;
256	257
257		bitmap.pix16(y*8+yi, x*8+xi) = machine.pens[pen];
	258	bitmap.pix16(y*8+yi, x*8+xi) = machine().pens[pen];
258	259	}
259	260	}
260	261	else
r21160	r21161
266	267	int pen;
267	268	pen = ((gfx_data[tile*8+yi]>>(7-xi)) & 1) ? color : 0;
268	269
269		bitmap.pix16(y*8+yi, x*8+xi) = machine.pens[pen];
	270	bitmap.pix16(y*8+yi, x*8+xi) = machine().pens[pen];
270	271	}
271	272	}
272	273	}
273	274
274	275	// draw cursor
275		if(state->m_cursor_addr*8 == count)
	276	if(m_cursor_addr*8 == count)
276	277	{
277	278	int xc,yc,cursor_on;
278	279
279	280	cursor_on = 0;
280		switch(state->m_cursor_raster & 0x60)
	281	switch(m_cursor_raster & 0x60)
281	282	{
282	283	case 0x00: cursor_on = 1; break; //always on
283	284	case 0x20: cursor_on = 0; break; //always off
284		case 0x40: if(machine.primary_screen->frame_number() & 0x10) { cursor_on = 1; } break; //fast blink
285		case 0x60: if(machine.primary_screen->frame_number() & 0x20) { cursor_on = 1; } break; //slow blink
	285	case 0x40: if(machine().primary_screen->frame_number() & 0x10) { cursor_on = 1; } break; //fast blink
	286	case 0x60: if(machine().primary_screen->frame_number() & 0x20) { cursor_on = 1; } break; //slow blink
286	287	}
287	288
288	289	if(cursor_on)
289	290	{
290		for(yc=0;yc<(8-(state->m_cursor_raster & 7));yc++)
	291	for(yc=0;yc<(8-(m_cursor_raster & 7));yc++)
291	292	{
292	293	for(xc=0;xc<8;xc++)
293	294	{
294		bitmap.pix16(y*8-yc+7, x*8+xc) = machine.pens[7];
	295	bitmap.pix16(y*8-yc+7, x*8+xc) = machine().pens[7];
295	296	}
296	297	}
297	298	}
r21160	r21161
311	312	width = m_x_width ? 80 : 40;
312	313
313	314	if(m_gfx_mode)
314		draw_mixed_screen(machine(),bitmap,cliprect,width);
	315	draw_mixed_screen(bitmap,cliprect,width);
315	316	else
316	317	{
317		draw_cg4_screen(machine(),bitmap,cliprect,width);
318		draw_tv_screen(machine(),bitmap,cliprect,width);
	318	draw_cg4_screen(bitmap,cliprect,width);
	319	draw_tv_screen(bitmap,cliprect,width);
319	320	}
320	321
321	322	return 0;

trunk/src/mess/drivers/pegasus.c

r21160	r21161
87	87	DECLARE_DEVICE_IMAGE_LOAD_MEMBER(pegasus_cart_3);
88	88	DECLARE_DEVICE_IMAGE_LOAD_MEMBER(pegasus_cart_4);
89	89	DECLARE_DEVICE_IMAGE_LOAD_MEMBER(pegasus_cart_5);
	90	void pegasus_decrypt_rom( UINT16 addr );
90	91	};
91	92
92	93	TIMER_DEVICE_CALLBACK_MEMBER(pegasus_state::pegasus_firq)
r21160	r21161
419	420
420	421	/* An encrypted single rom starts with 02, decrypted with 20. Not sure what
421	422	multipart roms will have. */
422		static void pegasus_decrypt_rom( running_machine &machine, UINT16 addr )
	423	void pegasus_state::pegasus_decrypt_rom( UINT16 addr )
423	424	{
424		UINT8 b, *ROM = machine.root_device().memregion("maincpu")->base();
	425	UINT8 b, *ROM = machine().root_device().memregion("maincpu")->base();
425	426	UINT16 i, j;
426	427	UINT8 buff[0x1000];
427	428	if (ROM[addr] == 0x02)
r21160	r21161
441	442	DEVICE_IMAGE_LOAD_MEMBER( pegasus_state, pegasus_cart_1 )
442	443	{
443	444	image.fread(image.device().machine().root_device().memregion("maincpu")->base() + 0x0000, 0x1000);
444		pegasus_decrypt_rom( image.device().machine(), 0x0000 );
	445	pegasus_decrypt_rom( 0x0000 );
445	446
446	447	return IMAGE_INIT_PASS;
447	448	}
r21160	r21161
449	450	DEVICE_IMAGE_LOAD_MEMBER( pegasus_state, pegasus_cart_2 )
450	451	{
451	452	image.fread(image.device().machine().root_device().memregion("maincpu")->base() + 0x1000, 0x1000);
452		pegasus_decrypt_rom( image.device().machine(), 0x1000 );
	453	pegasus_decrypt_rom( 0x1000 );
453	454
454	455	return IMAGE_INIT_PASS;
455	456	}
r21160	r21161
457	458	DEVICE_IMAGE_LOAD_MEMBER( pegasus_state, pegasus_cart_3 )
458	459	{
459	460	image.fread(image.device().machine().root_device().memregion("maincpu")->base() + 0x2000, 0x1000);
460		pegasus_decrypt_rom( image.device().machine(), 0x2000 );
	461	pegasus_decrypt_rom( 0x2000 );
461	462
462	463	return IMAGE_INIT_PASS;
463	464	}
r21160	r21161
465	466	DEVICE_IMAGE_LOAD_MEMBER( pegasus_state, pegasus_cart_4 )
466	467	{
467	468	image.fread(image.device().machine().root_device().memregion("maincpu")->base() + 0xc000, 0x1000);
468		pegasus_decrypt_rom( image.device().machine(), 0xc000 );
	469	pegasus_decrypt_rom( 0xc000 );
469	470
470	471	return IMAGE_INIT_PASS;
471	472	}
r21160	r21161
473	474	DEVICE_IMAGE_LOAD_MEMBER( pegasus_state, pegasus_cart_5 )
474	475	{
475	476	image.fread( image.device().machine().root_device().memregion("maincpu")->base() + 0xd000, 0x1000);
476		pegasus_decrypt_rom( image.device().machine(), 0xd000 );
	477	pegasus_decrypt_rom( 0xd000 );
477	478
478	479	return IMAGE_INIT_PASS;
479	480	}
r21160	r21161
492	493
493	494	DRIVER_INIT_MEMBER(pegasus_state,pegasus)
494	495	{
495		pegasus_decrypt_rom( machine(), 0xf000 );
	496	pegasus_decrypt_rom( 0xf000 );
496	497	}
497	498
498	499	static MACHINE_CONFIG_START( pegasus, pegasus_state )

trunk/src/mess/drivers/vii.c

r21160	r21161
157	157	void vii_blit_page(bitmap_rgb32 &bitmap, const rectangle &cliprect, int depth, UINT32 bitmap_addr, UINT16 *regs);
158	158	void vii_blit_sprite(bitmap_rgb32 &bitmap, const rectangle &cliprect, int depth, UINT32 base_addr);
159	159	void vii_blit_sprites(bitmap_rgb32 &bitmap, const rectangle &cliprect, int depth);
	160	inline void verboselog(int n_level, const char *s_fmt, ...);
	161	inline UINT8 expand_rgb5_to_rgb8(UINT8 val);
	162	inline UINT8 vii_mix_channel(UINT8 a, UINT8 b);
	163	void vii_mix_pixel(UINT32 offset, UINT16 rgb);
	164	void vii_set_pixel(UINT32 offset, UINT16 rgb);
160	165	};
161	166
162	167	enum
r21160	r21161
179	184	#define ENABLE_VERBOSE_LOG (1)
180	185
181	186	#if ENABLE_VERBOSE_LOG
182		INLINE void verboselog(running_machine &machine, int n_level, const char *s_fmt, ...)
	187	inline void vii_state::verboselog(int n_level, const char *s_fmt, ...)
183	188	{
184	189	if( VERBOSE_LEVEL >= n_level )
185	190	{
r21160	r21161
188	193	va_start( v, s_fmt );
189	194	vsprintf( buf, s_fmt, v );
190	195	va_end( v );
191		logerror( "%04x: %s", machine.driver_data<vii_state>()->m_maincpu->pc(), buf );
192	196	}
193	197	}
194	198	#else
r21160	r21161
203	207	{
204	208	}
205	209
206		INLINE UINT8 expand_rgb5_to_rgb8(UINT8 val)
	210	inline UINT8 vii_state::expand_rgb5_to_rgb8(UINT8 val)
207	211	{
208	212	UINT8 temp = val & 0x1f;
209	213	return (temp << 3) | (temp >> 2);
210	214	}
211	215
212	216	// Perform a lerp between a and b
213		INLINE UINT8 vii_mix_channel(vii_state *state, UINT8 a, UINT8 b)
	217	inline UINT8 vii_state::vii_mix_channel(UINT8 a, UINT8 b)
214	218	{
215		UINT8 alpha = state->m_video_regs[0x1c] & 0x00ff;
	219	UINT8 alpha = m_video_regs[0x1c] & 0x00ff;
216	220	return ((64 - alpha) * a + alpha * b) / 64;
217	221	}
218	222
219		static void vii_mix_pixel(vii_state *state, UINT32 offset, UINT16 rgb)
	223	void vii_state::vii_mix_pixel(UINT32 offset, UINT16 rgb)
220	224	{
221		state->m_screen[offset].r = vii_mix_channel(state, state->m_screen[offset].r, expand_rgb5_to_rgb8(rgb >> 10));
222		state->m_screen[offset].g = vii_mix_channel(state, state->m_screen[offset].g, expand_rgb5_to_rgb8(rgb >> 5));
223		state->m_screen[offset].b = vii_mix_channel(state, state->m_screen[offset].b, expand_rgb5_to_rgb8(rgb));
	225	m_screen[offset].r = vii_mix_channel(m_screen[offset].r, expand_rgb5_to_rgb8(rgb >> 10));
	226	m_screen[offset].g = vii_mix_channel(m_screen[offset].g, expand_rgb5_to_rgb8(rgb >> 5));
	227	m_screen[offset].b = vii_mix_channel(m_screen[offset].b, expand_rgb5_to_rgb8(rgb));
224	228	}
225	229
226		static void vii_set_pixel(vii_state *state, UINT32 offset, UINT16 rgb)
	230	void vii_state::vii_set_pixel(UINT32 offset, UINT16 rgb)
227	231	{
228		state->m_screen[offset].r = expand_rgb5_to_rgb8(rgb >> 10);
229		state->m_screen[offset].g = expand_rgb5_to_rgb8(rgb >> 5);
230		state->m_screen[offset].b = expand_rgb5_to_rgb8(rgb);
	232	m_screen[offset].r = expand_rgb5_to_rgb8(rgb >> 10);
	233	m_screen[offset].g = expand_rgb5_to_rgb8(rgb >> 5);
	234	m_screen[offset].b = expand_rgb5_to_rgb8(rgb);
231	235	}
232	236
233	237	void vii_state::vii_blit(bitmap_rgb32 &bitmap, const rectangle &cliprect, UINT32 xoff, UINT32 yoff, UINT32 attr, UINT32 ctrl, UINT32 bitmap_addr, UINT16 tile)
r21160	r21161
286	290	{
287	291	if (attr & 0x4000)
288	292	{
289		vii_mix_pixel(this, xx + 320*yy, rgb);
	293	vii_mix_pixel(xx + 320*yy, rgb);
290	294	}
291	295	else
292	296	{
293		vii_set_pixel(this, xx + 320*yy, rgb);
	297	vii_set_pixel(xx + 320*yy, rgb);
294	298	}
295	299	}
296	300	}
r21160	r21161
477	481	switch(offset)
478	482	{
479	483	case 0x62: // Video IRQ Enable
480		verboselog(machine(), 0, "vii_video_r: Video IRQ Enable: %04x\n", VII_VIDEO_IRQ_ENABLE);
	484	verboselog(0, "vii_video_r: Video IRQ Enable: %04x\n", VII_VIDEO_IRQ_ENABLE);
481	485	return VII_VIDEO_IRQ_ENABLE;
482	486
483	487	case 0x63: // Video IRQ Status
484		verboselog(machine(), 0, "vii_video_r: Video IRQ Status: %04x\n", VII_VIDEO_IRQ_STATUS);
	488	verboselog(0, "vii_video_r: Video IRQ Status: %04x\n", VII_VIDEO_IRQ_STATUS);
485	489	return VII_VIDEO_IRQ_STATUS;
486	490
487	491	default:
488		verboselog(machine(), 0, "vii_video_r: Unknown register %04x = %04x\n", 0x2800 + offset, m_video_regs[offset]);
	492	verboselog(0, "vii_video_r: Unknown register %04x = %04x\n", 0x2800 + offset, m_video_regs[offset]);
489	493	break;
490	494	}
491	495	return m_video_regs[offset];
r21160	r21161
510	514	COMBINE_DATA(&m_video_regs[offset]);
511	515	break;
512	516	case 0x62: // Video IRQ Enable
513		verboselog(machine(), 0, "vii_video_w: Video IRQ Enable = %04x (%04x)\n", data, mem_mask);
	517	verboselog(0, "vii_video_w: Video IRQ Enable = %04x (%04x)\n", data, mem_mask);
514	518	COMBINE_DATA(&VII_VIDEO_IRQ_ENABLE);
515	519	break;
516	520
517	521	case 0x63: // Video IRQ Acknowledge
518		verboselog(machine(), 0, "vii_video_w: Video IRQ Acknowledge = %04x (%04x)\n", data, mem_mask);
	522	verboselog(0, "vii_video_w: Video IRQ Acknowledge = %04x (%04x)\n", data, mem_mask);
519	523	VII_VIDEO_IRQ_STATUS &= ~data;
520	524	if(!VII_VIDEO_IRQ_STATUS)
521	525	{
r21160	r21161
524	528	break;
525	529
526	530	case 0x70: // Video DMA Source
527		verboselog(machine(), 0, "vii_video_w: Video DMA Source = %04x (%04x)\n", data, mem_mask);
	531	verboselog(0, "vii_video_w: Video DMA Source = %04x (%04x)\n", data, mem_mask);
528	532	COMBINE_DATA(&m_video_regs[offset]);
529	533	break;
530	534
531	535	case 0x71: // Video DMA Dest
532		verboselog(machine(), 0, "vii_video_w: Video DMA Dest = %04x (%04x)\n", data, mem_mask);
	536	verboselog(0, "vii_video_w: Video DMA Dest = %04x (%04x)\n", data, mem_mask);
533	537	COMBINE_DATA(&m_video_regs[offset]);
534	538	break;
535	539
536	540	case 0x72: // Video DMA Length
537		verboselog(machine(), 0, "vii_video_w: Video DMA Length = %04x (%04x)\n", data, mem_mask);
	541	verboselog(0, "vii_video_w: Video DMA Length = %04x (%04x)\n", data, mem_mask);
538	542	vii_do_dma(data);
539	543	break;
540	544
541	545	default:
542		verboselog(machine(), 0, "vii_video_w: Unknown register %04x = %04x (%04x)\n", 0x2800 + offset, data, mem_mask);
	546	verboselog(0, "vii_video_w: Unknown register %04x = %04x (%04x)\n", 0x2800 + offset, data, mem_mask);
543	547	COMBINE_DATA(&m_video_regs[offset]);
544	548	break;
545	549	}
r21160	r21161
550	554	switch(offset)
551	555	{
552	556	default:
553		verboselog(machine(), 4, "vii_audio_r: Unknown register %04x\n", 0x3000 + offset);
	557	verboselog(4, "vii_audio_r: Unknown register %04x\n", 0x3000 + offset);
554	558	break;
555	559	}
556	560	return 0;
r21160	r21161
561	565	switch(offset)
562	566	{
563	567	default:
564		verboselog(machine(), 4, "vii_audio_w: Unknown register %04x = %04x (%04x)\n", 0x3000 + offset, data, mem_mask);
	568	verboselog(4, "vii_audio_w: Unknown register %04x = %04x (%04x)\n", 0x3000 + offset, data, mem_mask);
565	569	break;
566	570	}
567	571	}
r21160	r21161
654	658	{
655	659	case 0x01: case 0x06: case 0x0b: // GPIO Data Port A/B/C
656	660	vii_do_gpio(offset);
657		verboselog(machine(), 3, "vii_io_r: %s %c = %04x (%04x)\n", gpioregs[(offset - 1) % 5], gpioports[(offset - 1) / 5], m_io_regs[offset], mem_mask);
	661	verboselog(3, "vii_io_r: %s %c = %04x (%04x)\n", gpioregs[(offset - 1) % 5], gpioports[(offset - 1) / 5], m_io_regs[offset], mem_mask);
658	662	val = m_io_regs[offset];
659	663	break;
660	664
661	665	case 0x02: case 0x03: case 0x04: case 0x05:
662	666	case 0x07: case 0x08: case 0x09: case 0x0a:
663	667	case 0x0c: case 0x0d: case 0x0e: case 0x0f: // Other GPIO regs
664		verboselog(machine(), 3, "vii_io_r: %s %c = %04x (%04x)\n", gpioregs[(offset - 1) % 5], gpioports[(offset - 1) / 5], m_io_regs[offset], mem_mask);
	668	verboselog(3, "vii_io_r: %s %c = %04x (%04x)\n", gpioregs[(offset - 1) % 5], gpioports[(offset - 1) / 5], m_io_regs[offset], mem_mask);
665	669	break;
666	670
667	671	case 0x1c: // Random
668	672	val = machine().rand() & 0x00ff;
669		verboselog(machine(), 3, "vii_io_r: Random = %04x (%04x)\n", val, mem_mask);
	673	verboselog(3, "vii_io_r: Random = %04x (%04x)\n", val, mem_mask);
670	674	break;
671	675
672	676	case 0x21: // IRQ Control
673		verboselog(machine(), 3, "vii_io_r: Controller IRQ Control = %04x (%04x)\n", val, mem_mask);
	677	verboselog(3, "vii_io_r: Controller IRQ Control = %04x (%04x)\n", val, mem_mask);
674	678	break;
675	679
676	680	case 0x22: // IRQ Status
677		verboselog(machine(), 3, "vii_io_r: Controller IRQ Status = %04x (%04x)\n", val, mem_mask);
	681	verboselog(3, "vii_io_r: Controller IRQ Status = %04x (%04x)\n", val, mem_mask);
678	682	break;
679	683
680	684	case 0x2c: case 0x2d: // Timers?
681	685	val = machine().rand() & 0x0000ffff;
682		verboselog(machine(), 3, "vii_io_r: Unknown Timer %d Register = %04x (%04x)\n", offset - 0x2c, val, mem_mask);
	686	verboselog(3, "vii_io_r: Unknown Timer %d Register = %04x (%04x)\n", offset - 0x2c, val, mem_mask);
683	687	break;
684	688
685	689	case 0x2f: // Data Segment
686	690	val = machine().device("maincpu")->state().state_int(UNSP_SR) >> 10;
687		verboselog(machine(), 3, "vii_io_r: Data Segment = %04x (%04x)\n", val, mem_mask);
	691	verboselog(3, "vii_io_r: Data Segment = %04x (%04x)\n", val, mem_mask);
688	692	break;
689	693
690	694	case 0x31: // Unknown, UART Status?
691		verboselog(machine(), 3, "vii_io_r: Unknown (UART Status?) = %04x (%04x)\n", 3, mem_mask);
	695	verboselog(3, "vii_io_r: Unknown (UART Status?) = %04x (%04x)\n", 3, mem_mask);
692	696	val = 3;
693	697	break;
694	698
695	699	case 0x36: // UART RX Data
696	700	val = m_controller_input[m_uart_rx_count];
697	701	m_uart_rx_count = (m_uart_rx_count + 1) % 8;
698		verboselog(machine(), 3, "vii_io_r: UART RX Data = %04x (%04x)\n", val, mem_mask);
	702	verboselog(3, "vii_io_r: UART RX Data = %04x (%04x)\n", val, mem_mask);
699	703	break;
700	704
701	705	case 0x59: // I2C Status
702		verboselog(machine(), 3, "vii_io_r: I2C Status = %04x (%04x)\n", val, mem_mask);
	706	verboselog(3, "vii_io_r: I2C Status = %04x (%04x)\n", val, mem_mask);
703	707	break;
704	708
705	709	case 0x5e: // I2C Data In
706		verboselog(machine(), 3, "vii_io_r: I2C Data In = %04x (%04x)\n", val, mem_mask);
	710	verboselog(3, "vii_io_r: I2C Data In = %04x (%04x)\n", val, mem_mask);
707	711	break;
708	712
709	713	default:
710		verboselog(machine(), 3, "vii_io_r: Unknown register %04x\n", 0x3d00 + offset);
	714	verboselog(3, "vii_io_r: Unknown register %04x\n", 0x3d00 + offset);
711	715	break;
712	716	}
713	717
r21160	r21161
726	730	switch(offset)
727	731	{
728	732	case 0x00: // GPIO special function select
729		verboselog(machine(), 3, "vii_io_w: GPIO Function Select = %04x (%04x)\n", data, mem_mask);
	733	verboselog(3, "vii_io_w: GPIO Function Select = %04x (%04x)\n", data, mem_mask);
730	734	COMBINE_DATA(&m_io_regs[offset]);
731	735	break;
732	736
r21160	r21161
737	741	case 0x02: case 0x03: case 0x04: case 0x05: // Port A
738	742	case 0x07: case 0x08: case 0x09: case 0x0a: // Port B
739	743	case 0x0c: case 0x0d: case 0x0e: case 0x0f: // Port C
740		verboselog(machine(), 3, "vii_io_w: %s %c = %04x (%04x)\n", gpioregs[(offset - 1) % 5], gpioports[(offset - 1) / 5], data, mem_mask);
	744	verboselog(3, "vii_io_w: %s %c = %04x (%04x)\n", gpioregs[(offset - 1) % 5], gpioports[(offset - 1) / 5], data, mem_mask);
741	745	COMBINE_DATA(&m_io_regs[offset]);
742	746	vii_do_gpio(offset);
743	747	break;
r21160	r21161
745	749	case 0x10:      // timebase control
746	750	if ((m_io_regs[offset] & 0x0003) != (data & 0x0003)) {
747	751	UINT16 hz = 8 << (data & 0x0003);
748		verboselog(machine(), 3, "*** TMB1 FREQ set to %dHz\n", hz);
	752	verboselog(3, "*** TMB1 FREQ set to %dHz\n", hz);
749	753	m_tmb1->adjust(attotime::zero, 0, attotime::from_hz( hz ));
750	754	}
751	755	if ((m_io_regs[offset] & 0x000c) != (data & 0x000c)) {
752	756	UINT16 hz = 128 << ((data & 0x000c) >> 2);
753		verboselog(machine(), 3, "*** TMB2 FREQ set to %dHz\n", hz);
	757	verboselog(3, "*** TMB2 FREQ set to %dHz\n", hz);
754	758	m_tmb2->adjust(attotime::zero, 0, attotime::from_hz( hz ));
755	759	}
756	760	COMBINE_DATA(&m_io_regs[offset]);
757	761	break;
758	762	case 0x21: // IRQ Enable
759		verboselog(machine(), 3, "vii_io_w: Controller IRQ Control = %04x (%04x)\n", data, mem_mask);
	763	verboselog(3, "vii_io_w: Controller IRQ Control = %04x (%04x)\n", data, mem_mask);
760	764	COMBINE_DATA(&VII_CTLR_IRQ_ENABLE);
761	765	if(!VII_CTLR_IRQ_ENABLE)
762	766	{
r21160	r21161
765	769	break;
766	770
767	771	case 0x22: // IRQ Acknowledge
768		verboselog(machine(), 3, "vii_io_w: Controller IRQ Acknowledge = %04x (%04x)\n", data, mem_mask);
	772	verboselog(3, "vii_io_w: Controller IRQ Acknowledge = %04x (%04x)\n", data, mem_mask);
769	773	m_io_regs[0x22] &= ~data;
770	774	if(!m_io_regs[0x22])
771	775	{
r21160	r21161
776	780	case 0x2f: // Data Segment
777	781	temp = machine().device("maincpu")->state().state_int(UNSP_SR);
778	782	machine().device("maincpu")->state().set_state_int(UNSP_SR, (temp & 0x03ff) | ((data & 0x3f) << 10));
779		verboselog(machine(), 3, "vii_io_w: Data Segment = %04x (%04x)\n", data, mem_mask);
	783	verboselog(3, "vii_io_w: Data Segment = %04x (%04x)\n", data, mem_mask);
780	784	break;
781	785
782	786	case 0x31: // Unknown UART
783		verboselog(machine(), 3, "vii_io_w: Unknown UART = %04x (%04x)\n", data, mem_mask);
	787	verboselog(3, "vii_io_w: Unknown UART = %04x (%04x)\n", data, mem_mask);
784	788	COMBINE_DATA(&m_io_regs[offset]);
785	789	break;
786	790
787	791	case 0x32: // UART Reset
788		verboselog(machine(), 3, "vii_io_r: UART Reset\n");
	792	verboselog(3, "vii_io_r: UART Reset\n");
789	793	break;
790	794
791	795	case 0x33: // UART Baud Rate
792		verboselog(machine(), 3, "vii_io_w: UART Baud Rate = %u\n", 27000000 / 16 / (0x10000 - (m_io_regs[0x34] << 8) - data));
	796	verboselog(3, "vii_io_w: UART Baud Rate = %u\n", 27000000 / 16 / (0x10000 - (m_io_regs[0x34] << 8) - data));
793	797	COMBINE_DATA(&m_io_regs[offset]);
794	798	break;
795	799
796	800	case 0x35: // UART TX Data
797		verboselog(machine(), 3, "vii_io_w: UART Baud Rate = %u\n", 27000000 / 16 / (0x10000 - (data << 8) - m_io_regs[0x33]));
	801	verboselog(3, "vii_io_w: UART Baud Rate = %u\n", 27000000 / 16 / (0x10000 - (data << 8) - m_io_regs[0x33]));
798	802	COMBINE_DATA(&m_io_regs[offset]);
799	803	break;
800	804
801	805	case 0x5a: // I2C Access Mode
802		verboselog(machine(), 3, "vii_io_w: I2C Access Mode = %04x (%04x)\n", data, mem_mask);
	806	verboselog(3, "vii_io_w: I2C Access Mode = %04x (%04x)\n", data, mem_mask);
803	807	COMBINE_DATA(&m_io_regs[offset]);
804	808	break;
805	809
806	810	case 0x5b: // I2C Device Address
807		verboselog(machine(), 3, "vii_io_w: I2C Device Address = %04x (%04x)\n", data, mem_mask);
	811	verboselog(3, "vii_io_w: I2C Device Address = %04x (%04x)\n", data, mem_mask);
808	812	COMBINE_DATA(&m_io_regs[offset]);
809	813	break;
810	814
811	815	case 0x5c: // I2C Sub-Address
812		verboselog(machine(), 3, "vii_io_w: I2C Sub-Address = %04x (%04x)\n", data, mem_mask);
	816	verboselog(3, "vii_io_w: I2C Sub-Address = %04x (%04x)\n", data, mem_mask);
813	817	COMBINE_DATA(&m_io_regs[offset]);
814	818	break;
815	819
816	820	case 0x5d: // I2C Data Out
817		verboselog(machine(), 3, "vii_io_w: I2C Data Out = %04x (%04x)\n", data, mem_mask);
	821	verboselog(3, "vii_io_w: I2C Data Out = %04x (%04x)\n", data, mem_mask);
818	822	COMBINE_DATA(&m_io_regs[offset]);
819	823	break;
820	824
821	825	case 0x5e: // I2C Data In
822		verboselog(machine(), 3, "vii_io_w: I2C Data In = %04x (%04x)\n", data, mem_mask);
	826	verboselog(3, "vii_io_w: I2C Data In = %04x (%04x)\n", data, mem_mask);
823	827	COMBINE_DATA(&m_io_regs[offset]);
824	828	break;
825	829
826	830	case 0x5f: // I2C Controller Mode
827		verboselog(machine(), 3, "vii_io_w: I2C Controller Mode = %04x (%04x)\n", data, mem_mask);
	831	verboselog(3, "vii_io_w: I2C Controller Mode = %04x (%04x)\n", data, mem_mask);
828	832	COMBINE_DATA(&m_io_regs[offset]);
829	833	break;
830	834
831	835	case 0x58: // I2C Command
832		verboselog(machine(), 3, "vii_io_w: I2C Command = %04x (%04x)\n", data, mem_mask);
	836	verboselog(3, "vii_io_w: I2C Command = %04x (%04x)\n", data, mem_mask);
833	837	COMBINE_DATA(&m_io_regs[offset]);
834	838	vii_do_i2c();
835	839	break;
836	840
837	841	case 0x59: // I2C Status / IRQ Acknowledge(?)
838		verboselog(machine(), 3, "vii_io_w: I2C Status / Ack = %04x (%04x)\n", data, mem_mask);
	842	verboselog(3, "vii_io_w: I2C Status / Ack = %04x (%04x)\n", data, mem_mask);
839	843	m_io_regs[offset] &= ~data;
840	844	break;
841	845
r21160	r21161
850	854	break;
851	855
852	856	default:
853		verboselog(machine(), 3, "vii_io_w: Unknown register %04x = %04x (%04x)\n", 0x3d00 + offset, data, mem_mask);
	857	verboselog(3, "vii_io_w: Unknown register %04x = %04x (%04x)\n", 0x3d00 + offset, data, mem_mask);
854	858	COMBINE_DATA(&m_io_regs[offset]);
855	859	break;
856	860	}
r21160	r21161
862	866	switch(offset)
863	867	{
864	868	default:
865		verboselog(machine(), 0, "vii_rowscroll_w: %04x = %04x (%04x)\n", 0x2900 + offset, data, mem_mask);
	869	verboselog(0, "vii_rowscroll_w: %04x = %04x (%04x)\n", 0x2900 + offset, data, mem_mask);
866	870	break;
867	871	}
868	872	}
r21160	r21161
872	876	switch(offset)
873	877	{
874	878	default:
875		verboselog(machine(), 0, "vii_spriteram_w: %04x = %04x (%04x)\n", 0x2c00 + offset, data, mem_mask);
	879	verboselog(0, "vii_spriteram_w: %04x = %04x (%04x)\n", 0x2c00 + offset, data, mem_mask);
876	880	break;
877	881	}
878	882	}
r21160	r21161
1054	1058	VII_VIDEO_IRQ_STATUS = VII_VIDEO_IRQ_ENABLE & 1;
1055	1059	if(VII_VIDEO_IRQ_STATUS)
1056	1060	{
1057		verboselog(machine(), 0, "Video IRQ\n");
	1061	verboselog(0, "Video IRQ\n");
1058	1062	machine().device("maincpu")->execute().set_input_line(UNSP_IRQ0_LINE, ASSERT_LINE);
1059	1063	}
1060	1064
1061	1065	//  {
1062		//      verboselog(machine(), 0, "audio 1 IRQ\n");
	1066	//      verboselog(0, "audio 1 IRQ\n");
1063	1067	//      machine().device("maincpu")->execute().set_input_line(UNSP_IRQ1_LINE, ASSERT_LINE);
1064	1068	//  }
1065	1069	if(m_io_regs[0x22] & m_io_regs[0x21] & 0x0c00)
1066	1070	{
1067		verboselog(machine(), 0, "timerA, timer B IRQ\n");
	1071	verboselog(0, "timerA, timer B IRQ\n");
1068	1072	machine().device("maincpu")->execute().set_input_line(UNSP_IRQ2_LINE, ASSERT_LINE);
1069	1073	}
1070	1074
r21160	r21161
1072	1076	// For now trigger always if any enabled
1073	1077	if(VII_CTLR_IRQ_ENABLE)
1074	1078	{
1075		verboselog(machine(), 0, "UART, ADC IRQ\n");
	1079	verboselog(0, "UART, ADC IRQ\n");
1076	1080	machine().device("maincpu")->execute().set_input_line(UNSP_IRQ3_LINE, ASSERT_LINE);
1077	1081	}
1078	1082	//  {
1079		//      verboselog(machine(), 0, "audio 4 IRQ\n");
	1083	//      verboselog(0, "audio 4 IRQ\n");
1080	1084	//      machine().device("maincpu")->execute().set_input_line(UNSP_IRQ4_LINE, ASSERT_LINE);
1081	1085	//  }
1082	1086
1083	1087	if(m_io_regs[0x22] & m_io_regs[0x21] & 0x1200)
1084	1088	{
1085		verboselog(machine(), 0, "External IRQ\n");
	1089	verboselog(0, "External IRQ\n");
1086	1090	machine().device("maincpu")->execute().set_input_line(UNSP_IRQ5_LINE, ASSERT_LINE);
1087	1091	}
1088	1092	if(m_io_regs[0x22] & m_io_regs[0x21] & 0x0070)
1089	1093	{
1090		verboselog(machine(), 0, "1024Hz, 2048HZ, 4096HZ IRQ\n");
	1094	verboselog(0, "1024Hz, 2048HZ, 4096HZ IRQ\n");
1091	1095	machine().device("maincpu")->execute().set_input_line(UNSP_IRQ6_LINE, ASSERT_LINE);
1092	1096	}
1093	1097	if(m_io_regs[0x22] & m_io_regs[0x21] & 0x008b)
1094	1098	{
1095		verboselog(machine(), 0, "TMB1, TMB2, 4Hz, key change IRQ\n");
	1099	verboselog(0, "TMB1, TMB2, 4Hz, key change IRQ\n");
1096	1100	machine().device("maincpu")->execute().set_input_line(UNSP_IRQ7_LINE, ASSERT_LINE);
1097	1101	}
1098	1102

trunk/src/mess/drivers/smc777.c

r21160	r21161
120	120	TIMER_DEVICE_CALLBACK_MEMBER(keyboard_callback);
121	121	DECLARE_WRITE_LINE_MEMBER(smc777_fdc_intrq_w);
122	122	DECLARE_WRITE_LINE_MEMBER(smc777_fdc_drq_w);
	123	void check_floppy_inserted();
123	124	};
124	125
125	126
r21160	r21161
371	372	}
372	373
373	374
374		static void check_floppy_inserted(running_machine &machine)
	375	void smc777_state::check_floppy_inserted()
375	376	{
376	377	int f_num;
377	378	floppy_image_legacy *floppy;
r21160	r21161
380	381	/* FIXME: floppy drive 1 doesn't work? */
381	382	for(f_num=0;f_num<2;f_num++)
382	383	{
383		floppy = flopimg_get_image(floppy_get_device(machine, f_num));
384		floppy_mon_w(floppy_get_device(machine, f_num), (floppy != NULL) ? 0 : 1);
385		floppy_drive_set_ready_state(floppy_get_device(machine, f_num), (floppy != NULL) ? 1 : 0,0);
	384	floppy = flopimg_get_image(floppy_get_device(machine(), f_num));
	385	floppy_mon_w(floppy_get_device(machine(), f_num), (floppy != NULL) ? 0 : 1);
	386	floppy_drive_set_ready_state(floppy_get_device(machine(), f_num), (floppy != NULL) ? 1 : 0,0);
386	387	}
387	388	}
388	389
389	390	READ8_MEMBER(smc777_state::smc777_fdc1_r)
390	391	{
391		check_floppy_inserted(machine());
	392	check_floppy_inserted();
392	393
393	394	switch(offset)
394	395	{
r21160	r21161
411	412
412	413	WRITE8_MEMBER(smc777_state::smc777_fdc1_w)
413	414	{
414		check_floppy_inserted(machine());
	415	check_floppy_inserted();
415	416
416	417	switch(offset)
417	418	{

Previous

199869 Revisions

Next

---

© 1997-2024 The MAME Team